diff options
author | Steve Reinhardt <stever@gmail.com> | 2009-04-22 01:55:52 -0400 |
---|---|---|
committer | Steve Reinhardt <stever@gmail.com> | 2009-04-22 01:55:52 -0400 |
commit | 7b40c36fbd1c348e5ef43231325923aae1cd0809 (patch) | |
tree | b1d142d10229a7ca68eff864aa9aae672230e41a /tests/quick/00.hello/ref/mips/linux/o3-timing | |
parent | 6629d9b2bc58a885bfebce1517fd12483497b6e4 (diff) | |
download | gem5-7b40c36fbd1c348e5ef43231325923aae1cd0809.tar.xz |
Update stats for new single bad-address responder.
Mostly just config.ini updates, though the different response
latency for bad addresses caused very minor timing changes
in the O3 Linux boot tests.
Diffstat (limited to 'tests/quick/00.hello/ref/mips/linux/o3-timing')
3 files changed, 46 insertions, 49 deletions
diff --git a/tests/quick/00.hello/ref/mips/linux/o3-timing/config.ini b/tests/quick/00.hello/ref/mips/linux/o3-timing/config.ini index d64731634..9e32dcc7f 100644 --- a/tests/quick/00.hello/ref/mips/linux/o3-timing/config.ini +++ b/tests/quick/00.hello/ref/mips/linux/o3-timing/config.ini @@ -158,11 +158,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=2 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=10 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -331,11 +330,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=2 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=10 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -367,11 +365,10 @@ type=BaseCache addr_range=0:18446744073709551615 assoc=2 block_size=64 -cpu_side_filter_ranges= +forward_snoops=true hash_delay=1 latency=1000 max_miss_count=0 -mem_side_filter_ranges= mshrs=10 prefetch_cache_check_push=true prefetch_data_accesses_only=false @@ -415,7 +412,7 @@ egid=100 env= errout=cerr euid=100 -executable=tests/test-progs/hello/bin/mips/linux/hello +executable=/dist/m5/regression/test-progs/hello/bin/mips/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/00.hello/ref/mips/linux/o3-timing/simout b/tests/quick/00.hello/ref/mips/linux/o3-timing/simout index 09c4684d8..4849c504d 100755 --- a/tests/quick/00.hello/ref/mips/linux/o3-timing/simout +++ b/tests/quick/00.hello/ref/mips/linux/o3-timing/simout @@ -5,10 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Apr 18 2009 10:32:20 -M5 revision dfe15f43c57e 6039 default qtip tip o3-mips-hello-regress -M5 started Apr 18 2009 10:37:22 -M5 executing on zooks +M5 compiled Apr 21 2009 18:01:16 +M5 revision e6dd09514462 6117 default qtip tip stats-update +M5 started Apr 21 2009 18:01:42 +M5 executing on zizzer command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/o3-timing -re tests/run.py build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt index f4a13baba..abebc01ef 100644 --- a/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt +++ b/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 49036 # Simulator instruction rate (inst/s) -host_mem_usage 153428 # Number of bytes of host memory used -host_seconds 0.10 # Real time elapsed on the host -host_tick_rate 135151055 # Simulator tick rate (ticks/s) +host_inst_rate 62820 # Simulator instruction rate (inst/s) +host_mem_usage 202152 # Number of bytes of host memory used +host_seconds 0.08 # Real time elapsed on the host +host_tick_rate 173066613 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5024 # Number of instructions simulated sim_seconds 0.000014 # Number of seconds simulated @@ -19,23 +19,23 @@ system.cpu.BPredUnit.usedRAS 384 # Nu system.cpu.commit.COM:branches 879 # Number of branches committed system.cpu.commit.COM:bw_lim_events 63 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 14165 -system.cpu.commit.COM:committed_per_cycle::min_value 0 -system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% -system.cpu.commit.COM:committed_per_cycle::0-1 11701 82.61% -system.cpu.commit.COM:committed_per_cycle::1-2 1166 8.23% -system.cpu.commit.COM:committed_per_cycle::2-3 493 3.48% -system.cpu.commit.COM:committed_per_cycle::3-4 279 1.97% -system.cpu.commit.COM:committed_per_cycle::4-5 290 2.05% -system.cpu.commit.COM:committed_per_cycle::5-6 74 0.52% -system.cpu.commit.COM:committed_per_cycle::6-7 61 0.43% -system.cpu.commit.COM:committed_per_cycle::7-8 38 0.27% -system.cpu.commit.COM:committed_per_cycle::8 63 0.44% -system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% -system.cpu.commit.COM:committed_per_cycle::total 14165 -system.cpu.commit.COM:committed_per_cycle::max_value 8 -system.cpu.commit.COM:committed_per_cycle::mean 0.399223 -system.cpu.commit.COM:committed_per_cycle::stdev 1.126414 +system.cpu.commit.COM:committed_per_cycle::samples 14165 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0-1 11701 82.61% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1-2 1166 8.23% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2-3 493 3.48% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3-4 279 1.97% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4-5 290 2.05% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5-6 74 0.52% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6-7 61 0.43% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7-8 38 0.27% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 63 0.44% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::total 14165 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 0.399223 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 1.126414 # Number of insts commited each cycle system.cpu.commit.COM:count 5655 # Number of instructions committed system.cpu.commit.COM:loads 1130 # Number of loads committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed @@ -141,23 +141,23 @@ system.cpu.fetch.branchRate 0.084246 # Nu system.cpu.fetch.icacheStallCycles 2162 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.predictedBranches 933 # Number of branches that fetch has predicted taken system.cpu.fetch.rate 0.549669 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 15217 -system.cpu.fetch.rateDist::min_value 0 -system.cpu.fetch.rateDist::underflows 0 0.00% -system.cpu.fetch.rateDist::0-1 11225 73.77% -system.cpu.fetch.rateDist::1-2 1766 11.61% -system.cpu.fetch.rateDist::2-3 196 1.29% -system.cpu.fetch.rateDist::3-4 137 0.90% -system.cpu.fetch.rateDist::4-5 314 2.06% -system.cpu.fetch.rateDist::5-6 113 0.74% -system.cpu.fetch.rateDist::6-7 304 2.00% -system.cpu.fetch.rateDist::7-8 249 1.64% -system.cpu.fetch.rateDist::8 913 6.00% -system.cpu.fetch.rateDist::overflows 0 0.00% -system.cpu.fetch.rateDist::total 15217 -system.cpu.fetch.rateDist::max_value 8 -system.cpu.fetch.rateDist::mean 1.002892 -system.cpu.fetch.rateDist::stdev 2.262712 +system.cpu.fetch.rateDist::samples 15217 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0-1 11225 73.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1-2 1766 11.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2-3 196 1.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3-4 137 0.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4-5 314 2.06% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5-6 113 0.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6-7 304 2.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7-8 249 1.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 913 6.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 15217 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.002892 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.262712 # Number of instructions fetched each cycle (Total) system.cpu.icache.ReadReq_accesses 2162 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 35500 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 34915.151515 # average ReadReq mshr miss latency |