Stats: Re update stats.

3 files changed, 120 insertions, 101 deletions

diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/config.ini b/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/config.ini
index b37edc581..15d83d7b2 100644
--- a/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/config.ini
+++ b/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/config.ini
@@ -1,13 +1,22 @@
 [root]
 type=Root
 children=system
-dummy=0
+time_sync_enable=false
+time_sync_period=100000000
+time_sync_spin_threshold=100000
 
 [system]
 type=System
-children=cpu physmem ruby
-mem_mode=atomic
+children=cpu dir_cntrl0 l1_cntrl0 physmem ruby
+mem_mode=timing
 physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
 
 [system.cpu]
 type=TimingSimpleCPU
@@ -86,8 +95,8 @@ progress_interval=0
 system=system
 tracer=system.cpu.tracer
 workload=system.cpu.workload
-dcache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[1]
-icache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[0]
+dcache_port=system.ruby.cpu_ruby_ports.port[1]
+icache_port=system.ruby.cpu_ruby_ports.port[0]
 
 [system.cpu.dtb]
 type=MipsTLB
@@ -108,7 +117,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=tests/test-progs/hello/bin/mips/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/mips/linux/hello
 gid=100
 input=cin
 max_stack_size=67108864
@@ -119,6 +128,59 @@ simpoint=0
 system=system
 uid=100
 
+[system.dir_cntrl0]
+type=Directory_Controller
+children=directory memBuffer
+buffer_size=0
+directory=system.dir_cntrl0.directory
+directory_latency=12
+memBuffer=system.dir_cntrl0.memBuffer
+number_of_TBEs=256
+recycle_latency=10
+transitions_per_cycle=32
+version=0
+
+[system.dir_cntrl0.directory]
+type=RubyDirectoryMemory
+map_levels=4
+numa_high_bit=6
+size=134217728
+use_map=false
+version=0
+
+[system.dir_cntrl0.memBuffer]
+type=RubyMemoryControl
+bank_bit_0=8
+bank_busy_time=11
+bank_queue_size=12
+banks_per_rank=8
+basic_bus_busy_time=2
+dimm_bit_0=12
+dimms_per_channel=2
+mem_bus_cycle_multiplier=10
+mem_ctl_latency=12
+mem_fixed_delay=0
+mem_random_arbitrate=0
+rank_bit_0=11
+rank_rank_delay=1
+ranks_per_dimm=2
+read_write_delay=2
+refresh_period=1560
+tFaw=0
+version=0
+
+[system.l1_cntrl0]
+type=L1Cache_Controller
+buffer_size=0
+cacheMemory=system.ruby.cpu_ruby_ports.dcache
+cache_response_latency=12
+issue_latency=2
+number_of_TBEs=256
+recycle_latency=10
+sequencer=system.ruby.cpu_ruby_ports
+transitions_per_cycle=32
+version=0
+
 [system.physmem]
 type=PhysicalMemory
 file=
@@ -127,35 +189,48 @@ latency_var=0
 null=false
 range=0:134217727
 zero=false
-port=system.ruby.network.topology.ext_links0.ext_node.sequencer.physMemPort
+port=system.ruby.cpu_ruby_ports.physMemPort
 
 [system.ruby]
 type=RubySystem
-children=debug network profiler tracer
+children=cpu_ruby_ports network profiler tracer
 block_size_bytes=64
 clock=1
-debug=system.ruby.debug
 mem_size=134217728
 network=system.ruby.network
+no_mem_vec=false
 profiler=system.ruby.profiler
 random_seed=1234
 randomization=false
 stats_filename=ruby.stats
-tech_nm=45
 tracer=system.ruby.tracer
 
-[system.ruby.debug]
-type=RubyDebug
-filter_string=none
-output_filename=none
-protocol_trace=false
-start_time=1
-verbosity_string=none
+[system.ruby.cpu_ruby_ports]
+type=RubySequencer
+children=dcache
+access_phys_mem=true
+dcache=system.ruby.cpu_ruby_ports.dcache
+deadlock_threshold=500000
+icache=system.ruby.cpu_ruby_ports.dcache
+max_outstanding_requests=16
+physmem=system.physmem
+using_ruby_tester=false
+version=0
+physMemPort=system.physmem.port[0]
+port=system.cpu.icache_port system.cpu.dcache_port
+
+[system.ruby.cpu_ruby_ports.dcache]
+type=RubyCache
+assoc=2
+latency=3
+replacement_policy=PSEUDO_LRU
+size=256
+start_index_bit=6
 
 [system.ruby.network]
 type=SimpleNetwork
 children=topology
-adaptive_routing=true
+adaptive_routing=false
 buffer_size=0
 control_msg_size=8
 endpoint_bandwidth=10000
@@ -166,6 +241,7 @@ topology=system.ruby.network.topology
 [system.ruby.network.topology]
 type=Topology
 children=ext_links0 ext_links1 int_links0 int_links1
+description=Crossbar
 ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1
 int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1
 num_int_nodes=3
@@ -173,93 +249,20 @@ print_config=false
 
 [system.ruby.network.topology.ext_links0]
 type=ExtLink
-children=ext_node
 bw_multiplier=64
-ext_node=system.ruby.network.topology.ext_links0.ext_node
+ext_node=system.l1_cntrl0
 int_node=0
 latency=1
 weight=1
 
-[system.ruby.network.topology.ext_links0.ext_node]
-type=L1Cache_Controller
-children=sequencer
-buffer_size=0
-cacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
-cache_response_latency=12
-issue_latency=2
-number_of_TBEs=256
-recycle_latency=10
-sequencer=system.ruby.network.topology.ext_links0.ext_node.sequencer
-transitions_per_cycle=32
-version=0
-
-[system.ruby.network.topology.ext_links0.ext_node.sequencer]
-type=RubySequencer
-children=icache
-dcache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
-deadlock_threshold=500000
-icache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
-max_outstanding_requests=16
-physmem=system.physmem
-using_ruby_tester=false
-version=0
-physMemPort=system.physmem.port[0]
-port=system.cpu.icache_port system.cpu.dcache_port
-
-[system.ruby.network.topology.ext_links0.ext_node.sequencer.icache]
-type=RubyCache
-assoc=2
-latency=3
-replacement_policy=PSEUDO_LRU
-size=256
-
 [system.ruby.network.topology.ext_links1]
 type=ExtLink
-children=ext_node
 bw_multiplier=64
-ext_node=system.ruby.network.topology.ext_links1.ext_node
+ext_node=system.dir_cntrl0
 int_node=1
 latency=1
 weight=1
 
-[system.ruby.network.topology.ext_links1.ext_node]
-type=Directory_Controller
-children=directory memBuffer
-buffer_size=0
-directory=system.ruby.network.topology.ext_links1.ext_node.directory
-directory_latency=12
-memBuffer=system.ruby.network.topology.ext_links1.ext_node.memBuffer
-number_of_TBEs=256
-recycle_latency=10
-transitions_per_cycle=32
-version=0
-
-[system.ruby.network.topology.ext_links1.ext_node.directory]
-type=RubyDirectoryMemory
-size=134217728
-version=0
-
-[system.ruby.network.topology.ext_links1.ext_node.memBuffer]
-type=RubyMemoryControl
-bank_bit_0=8
-bank_busy_time=11
-bank_queue_size=12
-banks_per_rank=8
-basic_bus_busy_time=2
-dimm_bit_0=12
-dimms_per_channel=2
-mem_bus_cycle_multiplier=10
-mem_ctl_latency=12
-mem_fixed_delay=0
-mem_random_arbitrate=0
-rank_bit_0=11
-rank_rank_delay=1
-ranks_per_dimm=2
-read_write_delay=2
-refresh_period=1560
-tFaw=0
-version=0
-
 [system.ruby.network.topology.int_links0]
 type=IntLink
 bw_multiplier=16
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/simout b/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/simout
index 87d5c1036..4a1640a47 100755
--- a/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/simout
+++ b/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/simout
@@ -5,10 +5,10 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Jan 21 2010 11:12:15
-M5 revision a2fac757fb31+ 6860+ default qtip brad/rubycfg_orion_update tip
-M5 started Jan 21 2010 11:12:51
-M5 executing on svvint07
+M5 compiled Feb  7 2011 01:55:51
+M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
+M5 started Feb  7 2011 01:56:00
+M5 executing on burrito
 command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-timing-ruby -re tests/run.py build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-timing-ruby
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt b/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt
index c0deed77b..0a46cd560 100644
--- a/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt
+++ b/tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                  24278                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 347460                       # Number of bytes of host memory used
+host_inst_rate                                  24226                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 234168                       # Number of bytes of host memory used
 host_seconds                                     0.24                       # Real time elapsed on the host
-host_tick_rate                                1220626                       # Simulator tick rate (ticks/s)
+host_tick_rate                                1216878                       # Simulator tick rate (ticks/s)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
 sim_insts                                        5827                       # Number of instructions simulated
 sim_seconds                                  0.000293                       # Number of seconds simulated
@@ -29,8 +29,24 @@ system.cpu.itb.write_hits                           0                       # DT
 system.cpu.itb.write_misses                         0                       # DTB write misses
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.numCycles                           292960                       # number of cpu cycles simulated
+system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
+system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
+system.cpu.num_busy_cycles                     292960                       # Number of busy cycles
+system.cpu.num_conditional_control_insts          677                       # number of instructions that are conditional controls
+system.cpu.num_fp_alu_accesses                      2                       # Number of float alu accesses
+system.cpu.num_fp_insts                             2                       # number of float instructions
+system.cpu.num_fp_register_reads                    3                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes                   1                       # number of times the floating registers were written
+system.cpu.num_func_calls                         194                       # number of times a function call or return occured
+system.cpu.num_idle_cycles                          0                       # Number of idle cycles
 system.cpu.num_insts                             5827                       # Number of instructions executed
-system.cpu.num_refs                              2090                       # Number of memory references
+system.cpu.num_int_alu_accesses                  5126                       # Number of integer alu accesses
+system.cpu.num_int_insts                         5126                       # number of integer instructions
+system.cpu.num_int_register_reads                7301                       # number of times the integer registers were read
+system.cpu.num_int_register_writes               3409                       # number of times the integer registers were written
+system.cpu.num_load_insts                        1164                       # Number of load instructions
+system.cpu.num_mem_refs                          2090                       # number of memory refs
+system.cpu.num_store_insts                        926                       # Number of store instructions
 system.cpu.workload.PROG:num_syscalls               8                       # Number of system calls
 
 ---------- End Simulation Statistics   ----------