diff options
author | Korey Sewell <ksewell@umich.edu> | 2011-02-04 00:09:22 -0500 |
---|---|---|
committer | Korey Sewell <ksewell@umich.edu> | 2011-02-04 00:09:22 -0500 |
commit | a48fe2729a0c7b5e269c82375b2b1810b8caac79 (patch) | |
tree | 2e5e721909b611f49c446fd7972dc1705a1f0af9 /tests/quick/00.hello/ref/mips/linux | |
parent | e396a34b0155d5054a099c67a91baa66c095d3d8 (diff) | |
download | gem5-a48fe2729a0c7b5e269c82375b2b1810b8caac79.tar.xz |
imported patch regression_updates
Diffstat (limited to 'tests/quick/00.hello/ref/mips/linux')
3 files changed, 177 insertions, 174 deletions
diff --git a/tests/quick/00.hello/ref/mips/linux/inorder-timing/config.ini b/tests/quick/00.hello/ref/mips/linux/inorder-timing/config.ini index 8312243a4..d479ef8bf 100644 --- a/tests/quick/00.hello/ref/mips/linux/inorder-timing/config.ini +++ b/tests/quick/00.hello/ref/mips/linux/inorder-timing/config.ini @@ -89,6 +89,7 @@ div8RepeatRate=1 do_checkpoint_insts=true do_statistics_insts=true dtb=system.cpu.dtb +fetchBuffSize=4 fetchMemPort=icache_port functionTrace=false functionTraceStart=0 @@ -115,7 +116,7 @@ phase=0 predType=tournament progress_interval=0 stageTracing=false -stageWidth=1 +stageWidth=4 system=system threadModel=SMT tracer=system.cpu.tracer @@ -245,7 +246,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/mips/linux/hello +executable=tests/test-progs/hello/bin/mips/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/00.hello/ref/mips/linux/inorder-timing/simout b/tests/quick/00.hello/ref/mips/linux/inorder-timing/simout index 4692f4932..dc388ddae 100755 --- a/tests/quick/00.hello/ref/mips/linux/inorder-timing/simout +++ b/tests/quick/00.hello/ref/mips/linux/inorder-timing/simout @@ -1,5 +1,3 @@ -Redirecting stdout to build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/inorder-timing/simout -Redirecting stderr to build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/inorder-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -7,13 +5,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 26 2010 12:56:28 -M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix -M5 started Aug 26 2010 12:56:32 -M5 executing on zizzer -command line: build/MIPS_SE/m5.opt -d build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/inorder-timing -re tests/run.py build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/inorder-timing +M5 compiled Jan 24 2011 18:37:16 +M5 revision 09e8ac96522d+ 7823+ default regression_updates qtip tip +M5 started Jan 24 2011 18:37:18 +M5 executing on zooks +command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/inorder-timing -re tests/run.py build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello World! -Exiting @ tick 28659500 because target called exit() +Exiting @ tick 21534000 because target called exit() diff --git a/tests/quick/00.hello/ref/mips/linux/inorder-timing/stats.txt b/tests/quick/00.hello/ref/mips/linux/inorder-timing/stats.txt index 18095c949..170c01854 100644 --- a/tests/quick/00.hello/ref/mips/linux/inorder-timing/stats.txt +++ b/tests/quick/00.hello/ref/mips/linux/inorder-timing/stats.txt @@ -1,37 +1,37 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 16536 # Simulator instruction rate (inst/s) -host_mem_usage 205460 # Number of bytes of host memory used -host_seconds 0.35 # Real time elapsed on the host -host_tick_rate 81268272 # Simulator tick rate (ticks/s) +host_inst_rate 32637 # Simulator instruction rate (inst/s) +host_mem_usage 156860 # Number of bytes of host memory used +host_seconds 0.18 # Real time elapsed on the host +host_tick_rate 120410651 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5827 # Number of instructions simulated -sim_seconds 0.000029 # Number of seconds simulated -sim_ticks 28659500 # Number of ticks simulated -system.cpu.AGEN-Unit.agens 2090 # Number of Address Generations -system.cpu.Branch-Predictor.BTBHitPct 15.000000 # BTB Hit Percentage -system.cpu.Branch-Predictor.BTBHits 24 # Number of BTB hits -system.cpu.Branch-Predictor.BTBLookups 160 # Number of BTB lookups -system.cpu.Branch-Predictor.RASInCorrect 35 # Number of incorrect RAS predictions. -system.cpu.Branch-Predictor.condIncorrect 556 # Number of conditional branches incorrect -system.cpu.Branch-Predictor.condPredicted 677 # Number of conditional branches predicted -system.cpu.Branch-Predictor.lookups 916 # Number of BP lookups -system.cpu.Branch-Predictor.predictedNotTaken 802 # Number of Branches Predicted As Not Taken (False). -system.cpu.Branch-Predictor.predictedTaken 114 # Number of Branches Predicted As Taken (True). +sim_seconds 0.000022 # Number of seconds simulated +sim_ticks 21534000 # Number of ticks simulated +system.cpu.AGEN-Unit.agens 2404 # Number of Address Generations +system.cpu.Branch-Predictor.BTBHitPct 14.054054 # BTB Hit Percentage +system.cpu.Branch-Predictor.BTBHits 26 # Number of BTB hits +system.cpu.Branch-Predictor.BTBLookups 185 # Number of BTB lookups +system.cpu.Branch-Predictor.RASInCorrect 30 # Number of incorrect RAS predictions. +system.cpu.Branch-Predictor.condIncorrect 845 # Number of conditional branches incorrect +system.cpu.Branch-Predictor.condPredicted 778 # Number of conditional branches predicted +system.cpu.Branch-Predictor.lookups 1066 # Number of BP lookups +system.cpu.Branch-Predictor.predictedNotTaken 949 # Number of Branches Predicted As Not Taken (False). +system.cpu.Branch-Predictor.predictedTaken 117 # Number of Branches Predicted As Taken (True). system.cpu.Branch-Predictor.usedRAS 86 # Number of times the RAS was used to get a target. -system.cpu.Execution-Unit.executions 3734 # Number of Instructions Executed. -system.cpu.Execution-Unit.mispredictPct 60.698690 # Percentage of Incorrect Branches Predicts -system.cpu.Execution-Unit.mispredicted 556 # Number of Branches Incorrectly Predicted -system.cpu.Execution-Unit.predicted 360 # Number of Branches Incorrectly Predicted -system.cpu.Execution-Unit.predictedNotTakenIncorrect 519 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.Execution-Unit.predictedTakenIncorrect 37 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.Execution-Unit.executions 3963 # Number of Instructions Executed. +system.cpu.Execution-Unit.mispredictPct 92.148310 # Percentage of Incorrect Branches Predicts +system.cpu.Execution-Unit.mispredicted 845 # Number of Branches Incorrectly Predicted +system.cpu.Execution-Unit.predicted 72 # Number of Branches Incorrectly Predicted +system.cpu.Execution-Unit.predictedNotTakenIncorrect 813 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.Execution-Unit.predictedTakenIncorrect 32 # Number of Branches Incorrectly Predicted As Taken. system.cpu.Mult-Div-Unit.divides 1 # Number of Divide Operations Executed system.cpu.Mult-Div-Unit.multiplies 3 # Number of Multipy Operations Executed -system.cpu.RegFile-Manager.regFileAccesses 10688 # Number of Total Accesses (Read+Write) to the Register File -system.cpu.RegFile-Manager.regFileReads 7278 # Number of Reads from Register File +system.cpu.RegFile-Manager.regFileAccesses 10006 # Number of Total Accesses (Read+Write) to the Register File +system.cpu.RegFile-Manager.regFileReads 6596 # Number of Reads from Register File system.cpu.RegFile-Manager.regFileWrites 3410 # Number of Writes to Register File -system.cpu.RegFile-Manager.regForwards 25 # Number of Registers Read Through Forwarding Logic -system.cpu.activity 20.706560 # Percentage of cycles cpu is active +system.cpu.RegFile-Manager.regForwards 1378 # Number of Registers Read Through Forwarding Logic +system.cpu.activity 13.935777 # Percentage of cycles cpu is active system.cpu.comBranches 916 # Number of Branches instructions committed system.cpu.comFloats 0 # Number of Floating Point instructions committed system.cpu.comInts 2155 # Number of Integer instructions committed @@ -42,62 +42,64 @@ system.cpu.comStores 925 # Nu system.cpu.committedInsts 5827 # Number of Instructions Simulated (Per-Thread) system.cpu.committedInsts_total 5827 # Number of Instructions Simulated (Total) system.cpu.contextSwitches 1 # Number of context switches -system.cpu.cpi 9.836966 # CPI: Cycles Per Instruction (Per-Thread) -system.cpu.cpi_total 9.836966 # CPI: Total CPI of All Threads +system.cpu.cpi 7.391282 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi_total 7.391282 # CPI: Total CPI of All Threads system.cpu.dcache.ReadReq_accesses 1164 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 56229.885057 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53229.885057 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 1077 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 4892000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.074742 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 87 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 4631000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_avg_miss_latency 56681.818182 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53683.908046 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 1076 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 4988000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.075601 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 88 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 1 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 4670500 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.074742 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 87 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 925 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 56254.901961 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53254.901961 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 874 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 2869000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.055135 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 51 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 2716000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_avg_miss_latency 55935.483871 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53637.254902 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 832 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 5202000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.100541 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 93 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 42 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 2735500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.055135 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 51 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 14.137681 # Average number of references to valid blocks. +system.cpu.dcache.avg_blocked_cycles::no_targets 53100 # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 13.826087 # Average number of references to valid blocks. system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 5 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 265500 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 2089 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 56239.130435 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 53239.130435 # average overall mshr miss latency -system.cpu.dcache.demand_hits 1951 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 7761000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.066060 # miss rate for demand accesses -system.cpu.dcache.demand_misses 138 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 7347000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_avg_miss_latency 56298.342541 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 53666.666667 # average overall mshr miss latency +system.cpu.dcache.demand_hits 1908 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 10190000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.086644 # miss rate for demand accesses +system.cpu.dcache.demand_misses 181 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 43 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 7406000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.066060 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 138 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.021533 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 88.199028 # Average occupied blocks per context +system.cpu.dcache.occ_%::0 0.021745 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 89.066455 # Average occupied blocks per context system.cpu.dcache.overall_accesses 2089 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 56239.130435 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 53239.130435 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 56298.342541 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 53666.666667 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 1951 # number of overall hits -system.cpu.dcache.overall_miss_latency 7761000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.066060 # miss rate for overall accesses -system.cpu.dcache.overall_misses 138 # number of overall misses -system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 7347000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_hits 1908 # number of overall hits +system.cpu.dcache.overall_miss_latency 10190000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.086644 # miss rate for overall accesses +system.cpu.dcache.overall_misses 181 # number of overall misses +system.cpu.dcache.overall_mshr_hits 43 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 7406000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.066060 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 138 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -105,8 +107,8 @@ system.cpu.dcache.overall_mshr_uncacheable_misses 0 system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 88.199028 # Cycle average of tags in use -system.cpu.dcache.total_refs 1951 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 89.066455 # Cycle average of tags in use +system.cpu.dcache.total_refs 1908 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks system.cpu.dtb.accesses 0 # DTB accesses @@ -118,64 +120,65 @@ system.cpu.dtb.read_misses 0 # DT system.cpu.dtb.write_accesses 0 # DTB write accesses system.cpu.dtb.write_hits 0 # DTB write hits system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.icache.ReadReq_accesses 5869 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 55795.379538 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 52795.379538 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 5566 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 16906000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.051627 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 303 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 15997000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.051627 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 303 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_accesses 853 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 55526.246719 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 53153.605016 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 472 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 21155500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.446659 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 381 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 62 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 16956000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.373974 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 319 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 18.369637 # Average number of references to valid blocks. +system.cpu.icache.avg_blocked_cycles::no_targets 31000 # average number of cycles each access was blocked +system.cpu.icache.avg_refs 1.479624 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 2 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 62000 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 5869 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 55795.379538 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 52795.379538 # average overall mshr miss latency -system.cpu.icache.demand_hits 5566 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 16906000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.051627 # miss rate for demand accesses -system.cpu.icache.demand_misses 303 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 15997000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.051627 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 303 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_accesses 853 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 55526.246719 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 53153.605016 # average overall mshr miss latency +system.cpu.icache.demand_hits 472 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 21155500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.446659 # miss rate for demand accesses +system.cpu.icache.demand_misses 381 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 62 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 16956000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.373974 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 319 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.065748 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 134.651831 # Average occupied blocks per context -system.cpu.icache.overall_accesses 5869 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 55795.379538 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 52795.379538 # average overall mshr miss latency +system.cpu.icache.occ_%::0 0.070944 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 145.293265 # Average occupied blocks per context +system.cpu.icache.overall_accesses 853 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 55526.246719 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 53153.605016 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 5566 # number of overall hits -system.cpu.icache.overall_miss_latency 16906000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.051627 # miss rate for overall accesses -system.cpu.icache.overall_misses 303 # number of overall misses -system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 15997000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.051627 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 303 # number of overall MSHR misses +system.cpu.icache.overall_hits 472 # number of overall hits +system.cpu.icache.overall_miss_latency 21155500 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.446659 # miss rate for overall accesses +system.cpu.icache.overall_misses 381 # number of overall misses +system.cpu.icache.overall_mshr_hits 62 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 16956000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.373974 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 319 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.replacements 13 # number of replacements -system.cpu.icache.sampled_refs 303 # Sample count of references to valid blocks. +system.cpu.icache.sampled_refs 319 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 134.651831 # Cycle average of tags in use -system.cpu.icache.total_refs 5566 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 145.293265 # Cycle average of tags in use +system.cpu.icache.total_refs 472 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 45451 # Number of cycles cpu's stages were not processed -system.cpu.ipc 0.101657 # IPC: Instructions Per Cycle (Per-Thread) -system.cpu.ipc_total 0.101657 # IPC: Total IPC of All Threads +system.cpu.idleCycles 37067 # Number of cycles cpu's stages were not processed +system.cpu.ipc 0.135295 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.ipc_total 0.135295 # IPC: Total IPC of All Threads system.cpu.itb.accesses 0 # DTB accesses system.cpu.itb.hits 0 # DTB hits system.cpu.itb.misses 0 # DTB misses @@ -186,91 +189,92 @@ system.cpu.itb.write_accesses 0 # DT system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.l2cache.ReadExReq_accesses 51 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 52254.901961 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40098.039216 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 2665000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_avg_miss_latency 52470.588235 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40235.294118 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 2676000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_misses 51 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 2045000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 2052000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 51 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 390 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 52086.340206 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40048.969072 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_accesses 406 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 52355.198020 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40152.227723 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 20209500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.994872 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 388 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 15539000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.994872 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 388 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_miss_latency 21151500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.995074 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 404 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 16221500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.995074 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 404 # number of ReadReq MSHR misses system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.005155 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.004950 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 441 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 52105.922551 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40054.669704 # average overall mshr miss latency +system.cpu.l2cache.demand_accesses 457 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 52368.131868 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40161.538462 # average overall mshr miss latency system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 22874500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.995465 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 439 # number of demand (read+write) misses +system.cpu.l2cache.demand_miss_latency 23827500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.995624 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 455 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 17584000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.995465 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 439 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 18273500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.995624 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 455 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.005821 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 190.726729 # Average occupied blocks per context -system.cpu.l2cache.overall_accesses 441 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 52105.922551 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 40054.669704 # average overall mshr miss latency +system.cpu.l2cache.occ_%::0 0.006169 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 202.148379 # Average occupied blocks per context +system.cpu.l2cache.overall_accesses 457 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 52368.131868 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 40161.538462 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 2 # number of overall hits -system.cpu.l2cache.overall_miss_latency 22874500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.995465 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 439 # number of overall misses +system.cpu.l2cache.overall_miss_latency 23827500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.995624 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 455 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 17584000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.995465 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 439 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 18273500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.995624 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 455 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 388 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 404 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 190.726729 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 202.148379 # Cycle average of tags in use system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 57320 # number of cpu cycles simulated -system.cpu.runCycles 11869 # Number of cycles cpu stages are processed. +system.cpu.numCycles 43069 # number of cpu cycles simulated +system.cpu.runCycles 6002 # Number of cycles cpu stages are processed. system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode system.cpu.smt_cpi no_value # CPI: Total SMT-CPI system.cpu.smt_ipc no_value # IPC: Total SMT-IPC -system.cpu.stage-0.idleCycles 51451 # Number of cycles 0 instructions are processed. -system.cpu.stage-0.runCycles 5869 # Number of cycles 1+ instructions are processed. -system.cpu.stage-0.utilization 10.239009 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-1.idleCycles 51492 # Number of cycles 0 instructions are processed. -system.cpu.stage-1.runCycles 5828 # Number of cycles 1+ instructions are processed. -system.cpu.stage-1.utilization 10.167481 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-2.idleCycles 51488 # Number of cycles 0 instructions are processed. -system.cpu.stage-2.runCycles 5832 # Number of cycles 1+ instructions are processed. -system.cpu.stage-2.utilization 10.174459 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-3.idleCycles 55230 # Number of cycles 0 instructions are processed. -system.cpu.stage-3.runCycles 2090 # Number of cycles 1+ instructions are processed. -system.cpu.stage-3.utilization 3.646197 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-4.idleCycles 51493 # Number of cycles 0 instructions are processed. -system.cpu.stage-4.runCycles 5827 # Number of cycles 1+ instructions are processed. -system.cpu.stage-4.utilization 10.165736 # Percentage of cycles stage was utilized (processing insts). -system.cpu.threadCycles 57320 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.stage-0.idleCycles 39196 # Number of cycles 0 instructions are processed. +system.cpu.stage-0.runCycles 3873 # Number of cycles 1+ instructions are processed. +system.cpu.stage-0.utilization 8.992547 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage-1.idleCycles 40152 # Number of cycles 0 instructions are processed. +system.cpu.stage-1.runCycles 2917 # Number of cycles 1+ instructions are processed. +system.cpu.stage-1.utilization 6.772853 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage-2.idleCycles 40243 # Number of cycles 0 instructions are processed. +system.cpu.stage-2.runCycles 2826 # Number of cycles 1+ instructions are processed. +system.cpu.stage-2.utilization 6.561564 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage-3.idleCycles 41749 # Number of cycles 0 instructions are processed. +system.cpu.stage-3.runCycles 1320 # Number of cycles 1+ instructions are processed. +system.cpu.stage-3.utilization 3.064849 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage-4.idleCycles 39866 # Number of cycles 0 instructions are processed. +system.cpu.stage-4.runCycles 3203 # Number of cycles 1+ instructions are processed. +system.cpu.stage-4.utilization 7.436904 # Percentage of cycles stage was utilized (processing insts). +system.cpu.threadCycles 10184 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.timesIdled 427 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 8 # Number of system calls ---------- End Simulation Statistics ---------- |