diff options
author | Steve Reinhardt <stever@gmail.com> | 2009-02-16 12:09:45 -0500 |
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committer | Steve Reinhardt <stever@gmail.com> | 2009-02-16 12:09:45 -0500 |
commit | 89ea32325094665c16688212b5a2cd7b7bbf5f03 (patch) | |
tree | 2259a04ed0e6c700096d8f662726c51a2c6da525 /tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini | |
parent | 89a7fb03934b3e38c7d8b2c4818794b3ec874fdf (diff) | |
download | gem5-89ea32325094665c16688212b5a2cd7b7bbf5f03.tar.xz |
Update stats for new prefetching fixes.
Prefetching is not enabled in any of our regressions, so no significant
stat values have changed, but zero-valued prefetch stats no longer
show up when prefetching is disabled so there are noticable changes
in the reference stat files anyway.
Diffstat (limited to 'tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini')
-rw-r--r-- | tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini index c8a9fb583..f68b9582f 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini +++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini @@ -12,9 +12,12 @@ physmem=system.physmem [system.cpu] type=TimingSimpleCPU children=dcache dtb icache itb l2cache toL2Bus tracer workload +checker=Null clock=500 cpu_id=0 defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 @@ -43,12 +46,11 @@ latency=1000 max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -80,12 +82,11 @@ latency=1000 max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=10000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false @@ -117,12 +118,11 @@ latency=10000 max_miss_count=0 mem_side_filter_ranges= mshrs=10 -prefetch_access=false prefetch_cache_check_push=true prefetch_data_accesses_only=false prefetch_degree=1 prefetch_latency=100000 -prefetch_miss=false +prefetch_on_access=false prefetch_past_page=false prefetch_policy=none prefetch_serial_squash=false |