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author | Nathan Binkert <nate@binkert.org> | 2009-04-08 22:21:30 -0700 |
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committer | Nathan Binkert <nate@binkert.org> | 2009-04-08 22:21:30 -0700 |
commit | 374ba9bae359e68c1496f8db25c38a817af2da19 (patch) | |
tree | 48fe4ae90f77f19aa6005fa5ec2426e836299bc9 /tests/quick/02.insttest/ref/sparc/linux/simple-timing | |
parent | e0de2c34433be76eac7798e58e1ae02f5bffb732 (diff) | |
download | gem5-374ba9bae359e68c1496f8db25c38a817af2da19.tar.xz |
tests: update tests for TLB unification
Diffstat (limited to 'tests/quick/02.insttest/ref/sparc/linux/simple-timing')
3 files changed, 11 insertions, 11 deletions
diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini index 8777df95f..2a3a9cb21 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini @@ -68,7 +68,7 @@ cpu_side=system.cpu.dcache_port mem_side=system.cpu.toL2Bus.port[1] [system.cpu.dtb] -type=SparcDTB +type=SparcTLB size=64 [system.cpu.icache] @@ -104,7 +104,7 @@ cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.port[0] [system.cpu.itb] -type=SparcITB +type=SparcTLB size=64 [system.cpu.l2cache] diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/simout b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/simout index 65fc22a94..788bf8fe4 100755 --- a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/simout +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 16 2009 00:17:12 -M5 revision d8c62c2eaaa6 5874 default qtip pf1 tip qbase -M5 started Feb 16 2009 00:17:34 -M5 executing on zizzer -command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/simple-timing -re tests/run.py quick/02.insttest/sparc/linux/simple-timing +M5 compiled Apr 8 2009 12:30:02 +M5 revision 233a4a1a6110 6024 default qtip tip test_unifytlb.diff +M5 started Apr 8 2009 12:30:40 +M5 executing on maize +command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Begining test of difficult SPARC instructions... diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stats.txt index 323f23c0d..81d91e476 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 71328 # Simulator instruction rate (inst/s) -host_mem_usage 200972 # Number of bytes of host memory used -host_seconds 0.21 # Real time elapsed on the host -host_tick_rate 200611199 # Simulator tick rate (ticks/s) +host_inst_rate 11404 # Simulator instruction rate (inst/s) +host_mem_usage 202820 # Number of bytes of host memory used +host_seconds 1.33 # Real time elapsed on the host +host_tick_rate 32108089 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 15175 # Number of instructions simulated sim_seconds 0.000043 # Number of seconds simulated |