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author | Ali Saidi <saidi@eecs.umich.edu> | 2007-03-03 17:22:47 -0500 |
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committer | Ali Saidi <saidi@eecs.umich.edu> | 2007-03-03 17:22:47 -0500 |
commit | 36f43ff6a5618154f6388650cc2a8526efdd7b30 (patch) | |
tree | cfdd7163931c436ed6d04aec815c125e5dedef4d /tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.out | |
parent | f892608ff7c9898dcbed6dd553632ac2caf4b1ae (diff) | |
download | gem5-36f43ff6a5618154f6388650cc2a8526efdd7b30.tar.xz |
Implement Niagara I/O interface and rework interrupts
configs/common/FSConfig.py:
Use binaries we've compiled instead of the ones that come with Legion
src/arch/alpha/interrupts.hh:
get rid of post(int int_type) and add a get_vec function that gets the interrupt vector for an interrupt number
src/arch/sparc/asi.cc:
Add AsiIsInterrupt() to AsiIsMmu()
src/arch/sparc/faults.cc:
src/arch/sparc/faults.hh:
Add InterruptVector type
src/arch/sparc/interrupts.hh:
rework interrupts. They are no longer cleared when created... A I/O or ASI read/write needs to happen before they are cleared
src/arch/sparc/isa_traits.hh:
Add the "interrupt" trap types to isa traits
src/arch/sparc/miscregfile.cc:
add names for all the misc registers and possible post an interrupt when TL is changed.
src/arch/sparc/miscregfile.hh:
Add a helper function to post an interrupt when pil < some set softint
src/arch/sparc/regfile.cc:
src/arch/sparc/regfile.hh:
InterruptLevel shouldn't really live here, moved to interrupt.hh
src/arch/sparc/tlb.cc:
Add interrupt ASIs to TLB
src/arch/sparc/ua2005.cc:
Add checkSoftInt to check if a softint needs to be posted
Check that a tickCompare isn't scheduled before scheduling one
Post and clear interrupts on queue writes and what not
src/base/bitfield.hh:
Add an helper function to return the msb that is set
src/cpu/base.cc:
src/cpu/base.hh:
get rid of post_interrupt(type) since it's no longer needed.. Add a way to see what interrupts are pending
src/cpu/intr_control.cc:
src/cpu/intr_control.hh:
src/dev/alpha/tsunami_cchip.cc:
src/python/m5/objects/IntrControl.py:
Make IntrControl have a system pointer rather than using a cpu pointer to get one
src/dev/sparc/SConscript:
add iob to SConsscrip
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.out:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.out:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.out:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.out:
tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini:
tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.out:
update config.ini/out for intrcntrl not having a cpu pointer anymore
--HG--
extra : convert_revision : 38614f6b9ffc8f3c93949a94ff04b7d2987168dd
Diffstat (limited to 'tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.out')
-rw-r--r-- | tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.out | 118 |
1 files changed, 33 insertions, 85 deletions
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.out b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.out index c1e5baadb..a4dd003e4 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.out +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.out @@ -34,40 +34,9 @@ clock=2 width=64 responder_set=false -[system.cpu0.itb] -type=AlphaITB -size=48 - -[system.cpu0.dtb] -type=AlphaDTB -size=64 - -[system.cpu0] -type=TimingSimpleCPU -max_insts_any_thread=0 -max_insts_all_threads=0 -max_loads_any_thread=0 -max_loads_all_threads=0 -progress_interval=0 -system=system -cpu_id=0 -itb=system.cpu0.itb -dtb=system.cpu0.dtb -profile=0 -do_quiesce=true -do_checkpoint_insts=true -do_statistics_insts=true -clock=1 -phase=0 -defer_registration=false -// width not specified -function_trace=false -function_trace_start=0 -// simulate_stalls not specified - [system.intrctrl] type=IntrControl -cpu=system.cpu0 +sys=system [system.tsunami] type=Tsunami @@ -132,6 +101,37 @@ image=system.disk2.image driveID=master delay=2000 +[system.cpu0.itb] +type=AlphaITB +size=48 + +[system.cpu0.dtb] +type=AlphaDTB +size=64 + +[system.cpu0] +type=TimingSimpleCPU +max_insts_any_thread=0 +max_insts_all_threads=0 +max_loads_any_thread=0 +max_loads_all_threads=0 +progress_interval=0 +system=system +cpu_id=0 +itb=system.cpu0.itb +dtb=system.cpu0.dtb +profile=0 +do_quiesce=true +do_checkpoint_insts=true +do_statistics_insts=true +clock=1 +phase=0 +defer_registration=false +// width not specified +function_trace=false +function_trace_start=0 +// simulate_stalls not specified + [system.cpu1.itb] type=AlphaITB size=48 @@ -275,15 +275,11 @@ size=16777216 platform=system.tsunami system=system -[system.sim_console.listener] -type=ConsoleListener -port=3456 - [system.sim_console] type=SimConsole -listener=system.sim_console.listener intr_control=system.intrctrl output=console +port=3456 append_name=true number=0 @@ -654,51 +650,3 @@ clock=2 width=64 responder_set=true -[trace] -flags= -start=0 -cycle=0 -bufsize=0 -file=cout -dump_on_exit=false -ignore= - -[stats] -descriptions=true -project_name=test -simulation_name=test -simulation_sample=0 -text_file=m5stats.txt -text_compat=true -mysql_db= -mysql_user= -mysql_password= -mysql_host= -events_start=-1 -dump_reset=false -dump_cycle=0 -dump_period=0 -ignore_events= - -[random] -seed=1 - -[exetrace] -speculative=true -print_cycle=true -print_opclass=true -print_thread=true -print_effaddr=true -print_data=true -print_iregs=false -print_fetchseq=false -print_cpseq=false -print_reg_delta=false -pc_symbol=true -intel_format=false -legion_lockstep=false -trace_system=client - -[statsreset] -reset_cycle=0 - |