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author | Kevin Lim <ktlim@umich.edu> | 2006-10-10 11:04:05 -0400 |
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committer | Kevin Lim <ktlim@umich.edu> | 2006-10-10 11:04:05 -0400 |
commit | f9284b111158275c5a0ef5043f5b8845dd729261 (patch) | |
tree | 65f16633ee13aaa5e9ea6b0ce66d6c867a97da76 /tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt | |
parent | e5b13138b1e045bb43a443882221b39d820553df (diff) | |
download | gem5-f9284b111158275c5a0ef5043f5b8845dd729261.tar.xz |
Updates refs.
tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini:
tests/quick/00.hello/ref/alpha/linux/o3-timing/config.out:
tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini:
tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.out:
tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini:
tests/quick/00.hello/ref/alpha/linux/simple-timing/config.out:
tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt:
tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout:
tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini:
tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.out:
tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini:
tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.out:
tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini:
tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.out:
tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt:
tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout:
tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini:
tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.out:
tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt:
tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.out:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.out:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.out:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stderr:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.out:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stderr:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout:
Update refs.
--HG--
extra : convert_revision : 5341341507ddbe1211992e5f72013d7be0000bae
Diffstat (limited to 'tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt')
-rw-r--r-- | tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt index ff9a06cc7..3f540d0ea 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 719379 # Simulator instruction rate (inst/s) -host_mem_usage 197268 # Number of bytes of host memory used -host_seconds 92.21 # Real time elapsed on the host -host_tick_rate 40502079 # Simulator tick rate (ticks/s) +host_inst_rate 255147 # Simulator instruction rate (inst/s) +host_mem_usage 198260 # Number of bytes of host memory used +host_seconds 260.00 # Real time elapsed on the host +host_tick_rate 14365182 # Simulator tick rate (ticks/s) sim_freq 2000000000 # Frequency of simulated ticks sim_insts 66337257 # Number of instructions simulated sim_seconds 1.867449 # Number of seconds simulated @@ -116,7 +116,7 @@ system.cpu0.kern.syscall_setgid 1 0.56% 98.32% # nu system.cpu0.kern.syscall_getrlimit 1 0.56% 98.88% # number of syscalls executed system.cpu0.kern.syscall_setsid 2 1.12% 100.00% # number of syscalls executed system.cpu0.not_idle_fraction 0.017483 # Percentage of non-idle cycles -system.cpu0.numCycles 0 # number of cpu cycles simulated +system.cpu0.numCycles 3734379018 # number of cpu cycles simulated system.cpu0.num_insts 51973218 # Number of instructions executed system.cpu0.num_refs 13496062 # Number of memory references system.cpu1.dtb.accesses 477041 # DTB accesses @@ -217,7 +217,7 @@ system.cpu1.kern.syscall_fcntl 2 1.33% 97.33% # nu system.cpu1.kern.syscall_setgid 3 2.00% 99.33% # number of syscalls executed system.cpu1.kern.syscall_getrlimit 1 0.67% 100.00% # number of syscalls executed system.cpu1.not_idle_fraction 0.005073 # Percentage of non-idle cycles -system.cpu1.numCycles 0 # number of cpu cycles simulated +system.cpu1.numCycles 3734898877 # number of cpu cycles simulated system.cpu1.num_insts 14364039 # Number of instructions executed system.cpu1.num_refs 4590544 # Number of memory references system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -234,7 +234,7 @@ system.disk2.dma_write_full_pages 1 # Nu system.disk2.dma_write_txs 1 # Number of DMA write transactions. system.tsunami.ethernet.coalescedRxDesc <err: div-0> # average number of RxDesc's coalesced into each post system.tsunami.ethernet.coalescedRxIdle <err: div-0> # average number of RxIdle's coalesced into each post -system.tsunami.ethernet.coalescedRxOk no value # average number of RxOk's coalesced into each post +system.tsunami.ethernet.coalescedRxOk <err: div-0> # average number of RxOk's coalesced into each post system.tsunami.ethernet.coalescedRxOrn <err: div-0> # average number of RxOrn's coalesced into each post system.tsunami.ethernet.coalescedSwi <err: div-0> # average number of Swi's coalesced into each post system.tsunami.ethernet.coalescedTotal <err: div-0> # average number of interrupts coalesced into each post |