diff options
author | Andreas Hansson <andreas.hansson@arm.com> | 2013-01-31 07:49:16 -0500 |
---|---|---|
committer | Andreas Hansson <andreas.hansson@arm.com> | 2013-01-31 07:49:16 -0500 |
commit | fce3433b2eb764d9519ffbc4c7e95049f3200ba3 (patch) | |
tree | 26e90c5190c4751532683d1f4b5bf6094e6ba4b7 /tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt | |
parent | c4898b15bcf5458e35f17cb0c3b4185cec0081aa (diff) | |
download | gem5-fce3433b2eb764d9519ffbc4c7e95049f3200ba3.tar.xz |
stats: Update stats for regressions using SimpleDDR3
This patch updates the regression stats to reflect that they are using
the SimpleDDR3 controller by default.
Diffstat (limited to 'tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt')
-rw-r--r-- | tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt | 1134 |
1 files changed, 567 insertions, 567 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt index e3ca77030..37fa2c1e1 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt @@ -1,94 +1,94 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.910582 # Number of seconds simulated -sim_ticks 1910582068000 # Number of ticks simulated -final_tick 1910582068000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.910548 # Number of seconds simulated +sim_ticks 1910547559000 # Number of ticks simulated +final_tick 1910547559000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 951839 # Simulator instruction rate (inst/s) -host_op_rate 951839 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 32401800424 # Simulator tick rate (ticks/s) -host_mem_usage 374212 # Number of bytes of host memory used -host_seconds 58.97 # Real time elapsed on the host -sim_insts 56125446 # Number of instructions simulated -sim_ops 56125446 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 850560 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24847488 # Number of bytes read from this memory +host_inst_rate 1284259 # Simulator instruction rate (inst/s) +host_op_rate 1284258 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 43720523895 # Simulator tick rate (ticks/s) +host_mem_usage 330356 # Number of bytes of host memory used +host_seconds 43.70 # Real time elapsed on the host +sim_insts 56120911 # Number of instructions simulated +sim_ops 56120911 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 850624 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24858368 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 2652352 # Number of bytes read from this memory -system.physmem.bytes_read::total 28350400 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 850560 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 850560 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7392192 # Number of bytes written to this memory -system.physmem.bytes_written::total 7392192 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 13290 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 388242 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 28361344 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 850624 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 850624 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7404352 # Number of bytes written to this memory +system.physmem.bytes_written::total 7404352 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 13291 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 388412 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 41443 # Number of read requests responded to by this memory -system.physmem.num_reads::total 442975 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 115503 # Number of write requests responded to by this memory -system.physmem.num_writes::total 115503 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 445184 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 13005193 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1388243 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14838619 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 445184 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 445184 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3869078 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3869078 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3869078 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 445184 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 13005193 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1388243 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 18707698 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 442975 # Total number of read requests seen -system.physmem.writeReqs 115503 # Total number of write requests seen -system.physmem.cpureqs 559567 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 28350400 # Total number of bytes read from memory -system.physmem.bytesWritten 7392192 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 28350400 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7392192 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 51 # Number of read reqs serviced by write Q +system.physmem.num_reads::total 443146 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 115693 # Number of write requests responded to by this memory +system.physmem.num_writes::total 115693 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 445225 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 13011122 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1388268 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 14844616 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 445225 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 445225 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3875513 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3875513 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3875513 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 445225 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 13011122 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1388268 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 18720129 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 443146 # Total number of read requests seen +system.physmem.writeReqs 115693 # Total number of write requests seen +system.physmem.cpureqs 561589 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 28361344 # Total number of bytes read from memory +system.physmem.bytesWritten 7404352 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 28361344 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 7404352 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 45 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 130 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 28021 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 27576 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 27724 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 27399 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 28096 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 27946 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 27736 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 27622 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 27577 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 27238 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 27723 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 27886 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 27600 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 27483 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 27641 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 27656 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 7552 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 7244 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 7137 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 6901 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 7584 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 7386 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 7208 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 7095 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 7184 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 6832 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 7257 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 7441 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 7265 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 7126 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 7165 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 7126 # Track writes on a per bank basis +system.physmem.perBankRdReqs::0 27901 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 27706 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 27556 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 27375 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 27676 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 27765 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 27827 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 27615 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 28008 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 27777 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 27792 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 27562 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 27598 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 27733 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 27646 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 27564 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 7483 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 7263 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 7148 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 7032 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 7167 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 7214 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 7312 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 7182 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 7584 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 7357 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 7354 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 7067 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 7154 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 7184 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 7113 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 7079 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 404 # Number of times wr buffer was full causing retry -system.physmem.totGap 1910570168000 # Total gap between requests +system.physmem.numWrRetry 2065 # Number of times wr buffer was full causing retry +system.physmem.totGap 1910535659000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 442975 # Categorize read packet sizes +system.physmem.readPktSize::6 443146 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -97,7 +97,7 @@ system.physmem.writePktSize::2 0 # ca system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 115907 # categorize write packet sizes +system.physmem.writePktSize::6 117758 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -109,27 +109,27 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 130 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 404639 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 7455 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 5269 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 2334 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2835 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2403 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1793 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 2009 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1658 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1931 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1592 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1535 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1623 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1782 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 1204 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1459 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 903 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 267 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 130 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 101 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 402456 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 4645 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 3680 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 2219 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 3123 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2964 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2721 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 2721 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 2666 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 2589 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1544 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1454 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1412 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1360 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 1368 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 1379 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 1611 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 1491 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 926 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 759 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 13 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -142,69 +142,69 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 4142 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 4753 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4845 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 4893 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 4973 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 4987 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 5015 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 5016 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 5017 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 5022 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 5022 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 5022 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 5022 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 5022 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 5022 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 5022 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 5022 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5022 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5022 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5022 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5021 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5021 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5021 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 880 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 269 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 177 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 129 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 49 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 35 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 3510 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 3683 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4101 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 4153 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 4653 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 5001 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 5007 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 5012 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 5015 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 5030 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 5030 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 5030 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 5030 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 5030 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 5030 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 5030 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 5030 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5030 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5030 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5030 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5030 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5030 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5030 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 1521 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 1348 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 930 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 877 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 377 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 29 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 23 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 15 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 2804911869 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 10779125869 # Sum of mem lat for all requests -system.physmem.totBusLat 1771696000 # Total cycles spent in databus access -system.physmem.totBankLat 6202518000 # Total cycles spent in bank access -system.physmem.avgQLat 6332.72 # Average queueing delay per request -system.physmem.avgBankLat 14003.57 # Average bank access latency per request -system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 24336.29 # Average memory access latency +system.physmem.totQLat 4718066660 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 13230246660 # Sum of mem lat for all requests +system.physmem.totBusLat 2215505000 # Total cycles spent in databus access +system.physmem.totBankLat 6296675000 # Total cycles spent in bank access +system.physmem.avgQLat 10647.84 # Average queueing delay per request +system.physmem.avgBankLat 14210.47 # Average bank access latency per request +system.physmem.avgBusLat 5000.00 # Average bus latency per request +system.physmem.avgMemAccLat 29858.31 # Average memory access latency system.physmem.avgRdBW 14.84 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 3.87 # Average achieved write bandwidth in MB/s +system.physmem.avgWrBW 3.88 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 14.84 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 3.87 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 0.12 # Data bus utilization in percentage +system.physmem.avgConsumedWrBW 3.88 # Average consumed write bandwidth in MB/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 0.15 # Data bus utilization in percentage system.physmem.avgRdQLen 0.01 # Average read queue length over time -system.physmem.avgWrQLen 14.48 # Average write queue length over time -system.physmem.readRowHits 423327 # Number of row buffer hits during reads -system.physmem.writeRowHits 74914 # Number of row buffer hits during writes -system.physmem.readRowHitRate 95.58 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 64.86 # Row buffer hit rate for writes -system.physmem.avgGap 3421030.31 # Average gap between requests +system.physmem.avgWrQLen 11.47 # Average write queue length over time +system.physmem.readRowHits 415807 # Number of row buffer hits during reads +system.physmem.writeRowHits 89941 # Number of row buffer hits during writes +system.physmem.readRowHitRate 93.84 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 77.74 # Row buffer hit rate for writes +system.physmem.avgGap 3418758.64 # Average gap between requests system.iocache.replacements 41685 # number of replacements -system.iocache.tagsinuse 1.342666 # Cycle average of tags in use +system.iocache.tagsinuse 1.342284 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 1745691885000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::tsunami.ide 1.342666 # Average occupied blocks per requestor -system.iocache.occ_percent::tsunami.ide 0.083917 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.083917 # Average percentage of cache occupancy +system.iocache.warmup_cycle 1745701071000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::tsunami.ide 1.342284 # Average occupied blocks per requestor +system.iocache.occ_percent::tsunami.ide 0.083893 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.083893 # Average percentage of cache occupancy system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses @@ -215,12 +215,12 @@ system.iocache.overall_misses::tsunami.ide 41725 # system.iocache.overall_misses::total 41725 # number of overall misses system.iocache.ReadReq_miss_latency::tsunami.ide 20927998 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 20927998 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 9475235806 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 9475235806 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 9496163804 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 9496163804 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 9496163804 # number of overall miss cycles -system.iocache.overall_miss_latency::total 9496163804 # number of overall miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 10644331806 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 10644331806 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 10665259804 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 10665259804 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 10665259804 # number of overall miss cycles +system.iocache.overall_miss_latency::total 10665259804 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) @@ -239,17 +239,17 @@ system.iocache.overall_miss_rate::tsunami.ide 1 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::tsunami.ide 120971.086705 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total 120971.086705 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 228033.206729 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 228033.206729 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 227589.306267 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 227589.306267 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 227589.306267 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 227589.306267 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 189601 # number of cycles access was blocked +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 256168.940268 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 256168.940268 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 255608.383559 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 255608.383559 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 255608.383559 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 255608.383559 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 285028 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 23064 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 27152 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8.220647 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 10.497496 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -263,14 +263,14 @@ system.iocache.demand_mshr_misses::tsunami.ide 41725 system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11931000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 11931000 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 7312468500 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 7312468500 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 7324399500 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 7324399500 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 7324399500 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 7324399500 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11931250 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 11931250 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8482336109 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 8482336109 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 8494267359 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 8494267359 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 8494267359 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 8494267359 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -279,14 +279,14 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68965.317919 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 68965.317919 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 175983.550732 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 175983.550732 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 175539.832235 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 175539.832235 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 175539.832235 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 175539.832235 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68966.763006 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 68966.763006 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 204137.853990 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 204137.853990 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 203577.408244 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 203577.408244 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 203577.408244 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 203577.408244 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -304,22 +304,22 @@ system.cpu.dtb.fetch_hits 0 # IT system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 9055970 # DTB read hits +system.cpu.dtb.read_hits 9055197 # DTB read hits system.cpu.dtb.read_misses 10329 # DTB read misses system.cpu.dtb.read_acv 210 # DTB read access violations system.cpu.dtb.read_accesses 728856 # DTB read accesses -system.cpu.dtb.write_hits 6351685 # DTB write hits +system.cpu.dtb.write_hits 6350929 # DTB write hits system.cpu.dtb.write_misses 1142 # DTB write misses system.cpu.dtb.write_acv 157 # DTB write access violations system.cpu.dtb.write_accesses 291931 # DTB write accesses -system.cpu.dtb.data_hits 15407655 # DTB hits +system.cpu.dtb.data_hits 15406126 # DTB hits system.cpu.dtb.data_misses 11471 # DTB misses system.cpu.dtb.data_acv 367 # DTB access violations system.cpu.dtb.data_accesses 1020787 # DTB accesses -system.cpu.itb.fetch_hits 4974178 # ITB hits +system.cpu.itb.fetch_hits 4974131 # ITB hits system.cpu.itb.fetch_misses 5006 # ITB misses system.cpu.itb.fetch_acv 184 # ITB acv -system.cpu.itb.fetch_accesses 4979184 # ITB accesses +system.cpu.itb.fetch_accesses 4979137 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -332,51 +332,51 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 3821164136 # number of cpu cycles simulated +system.cpu.numCycles 3821095118 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 56125446 # Number of instructions committed -system.cpu.committedOps 56125446 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 51999916 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 324393 # Number of float alu accesses -system.cpu.num_func_calls 1482010 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 6463546 # number of instructions that are conditional controls -system.cpu.num_int_insts 51999916 # number of integer instructions -system.cpu.num_fp_insts 324393 # number of float instructions -system.cpu.num_int_register_reads 71242345 # number of times the integer registers were read -system.cpu.num_int_register_writes 38476410 # number of times the integer registers were written -system.cpu.num_fp_register_reads 163609 # number of times the floating registers were read -system.cpu.num_fp_register_writes 166486 # number of times the floating registers were written -system.cpu.num_mem_refs 15460271 # number of memory refs -system.cpu.num_load_insts 9092827 # Number of load instructions -system.cpu.num_store_insts 6367444 # Number of store instructions -system.cpu.num_idle_cycles 3587332264.998123 # Number of idle cycles -system.cpu.num_busy_cycles 233831871.001878 # Number of busy cycles -system.cpu.not_idle_fraction 0.061194 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.938806 # Percentage of idle cycles +system.cpu.committedInsts 56120911 # Number of instructions committed +system.cpu.committedOps 56120911 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 51995405 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 324259 # Number of float alu accesses +system.cpu.num_func_calls 1481756 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 6462892 # number of instructions that are conditional controls +system.cpu.num_int_insts 51995405 # number of integer instructions +system.cpu.num_fp_insts 324259 # number of float instructions +system.cpu.num_int_register_reads 71234690 # number of times the integer registers were read +system.cpu.num_int_register_writes 38473511 # number of times the integer registers were written +system.cpu.num_fp_register_reads 163543 # number of times the floating registers were read +system.cpu.num_fp_register_writes 166418 # number of times the floating registers were written +system.cpu.num_mem_refs 15458726 # number of memory refs +system.cpu.num_load_insts 9092044 # Number of load instructions +system.cpu.num_store_insts 6366682 # Number of store instructions +system.cpu.num_idle_cycles 3587142255.998123 # Number of idle cycles +system.cpu.num_busy_cycles 233952862.001878 # Number of busy cycles +system.cpu.not_idle_fraction 0.061227 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.938773 # Percentage of idle cycles system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6378 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 211969 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74892 40.89% 40.89% # number of times we switched to this ipl +system.cpu.kern.inst.quiesce 6380 # number of quiesce instructions executed +system.cpu.kern.inst.hwrei 211970 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74891 40.89% 40.89% # number of times we switched to this ipl system.cpu.kern.ipl_count::21 131 0.07% 40.96% # number of times we switched to this ipl -system.cpu.kern.ipl_count::22 1930 1.05% 42.02% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 106200 57.98% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 183153 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73525 49.31% 49.31% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_count::22 1930 1.05% 42.01% # number of times we switched to this ipl +system.cpu.kern.ipl_count::31 106204 57.99% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 183156 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73524 49.31% 49.31% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::21 131 0.09% 49.40% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::22 1930 1.29% 50.69% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73525 49.31% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 149111 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1855918085500 97.14% 97.14% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 91164500 0.00% 97.14% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 736454000 0.04% 97.18% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 53835630000 2.82% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1910581334000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_good::31 73524 49.31% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 149109 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1855675111500 97.13% 97.13% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 91586500 0.00% 97.13% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 735892500 0.04% 97.17% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 54044234500 2.83% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1910546825000 # number of cycles we spent at this ipl system.cpu.kern.ipl_used::0 0.981747 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.692326 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.814134 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.692290 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.814109 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -412,10 +412,10 @@ system.cpu.kern.callpal::cserve 1 0.00% 0.00% # nu system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal::swpctx 4176 2.17% 2.17% # number of callpals executed -system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed +system.cpu.kern.callpal::swpctx 4174 2.16% 2.17% # number of callpals executed +system.cpu.kern.callpal::tbi 54 0.03% 2.19% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed -system.cpu.kern.callpal::swpipl 175936 91.22% 93.42% # number of callpals executed +system.cpu.kern.callpal::swpipl 175939 91.22% 93.42% # number of callpals executed system.cpu.kern.callpal::rdps 6831 3.54% 96.96% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.96% # number of callpals executed @@ -424,21 +424,21 @@ system.cpu.kern.callpal::whami 2 0.00% 96.97% # nu system.cpu.kern.callpal::rti 5155 2.67% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 192878 # number of callpals executed -system.cpu.kern.mode_switch::kernel 5901 # number of protection mode switches -system.cpu.kern.mode_switch::user 1741 # number of protection mode switches -system.cpu.kern.mode_switch::idle 2096 # number of protection mode switches -system.cpu.kern.mode_good::kernel 1911 -system.cpu.kern.mode_good::user 1741 -system.cpu.kern.mode_good::idle 170 -system.cpu.kern.mode_switch_good::kernel 0.323843 # fraction of useful protection mode switches +system.cpu.kern.callpal::total 192879 # number of callpals executed +system.cpu.kern.mode_switch::kernel 5900 # number of protection mode switches +system.cpu.kern.mode_switch::user 1744 # number of protection mode switches +system.cpu.kern.mode_switch::idle 2095 # number of protection mode switches +system.cpu.kern.mode_good::kernel 1913 +system.cpu.kern.mode_good::user 1744 +system.cpu.kern.mode_good::idle 169 +system.cpu.kern.mode_switch_good::kernel 0.324237 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.081107 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.392483 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 45587423000 2.39% 2.39% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 5075517000 0.27% 2.65% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1859918392000 97.35% 100.00% # number of ticks spent at the given mode -system.cpu.kern.swap_context 4177 # number of times the context was actually changed +system.cpu.kern.mode_switch_good::idle 0.080668 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::total 0.392853 # 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miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13752.601547 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13752.601547 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13752.601547 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13752.601547 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13752.601547 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13752.601547 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -523,126 +523,126 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # 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Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 93552000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 511.980842 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999963 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999963 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 7806239 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7806239 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 5847887 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 5847887 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 183020 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 183020 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 199223 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 199223 # 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miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21247.653610 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 21247.653610 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28263.090339 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 28263.090339 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13220.519073 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13220.519073 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 22802.025405 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 22802.025405 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 22802.025405 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 22802.025405 # average overall miss latency +system.cpu.dcache.ReadReq_hits::cpu.data 7805620 # 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number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 304374 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 304374 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 17254 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 17254 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1373090 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1373090 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1373090 # number of overall misses +system.cpu.dcache.overall_misses::total 1373090 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 22883646000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 22883646000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 8388017500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 8388017500 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 229841000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 229841000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 31271663500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 31271663500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 31271663500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 31271663500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 8874336 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 8874336 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6151362 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6151362 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200239 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 200239 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 199218 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 199218 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 15025698 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15025698 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15025698 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15025698 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120428 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.120428 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049481 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.049481 # 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average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13321.027008 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 22774.664079 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 22774.664079 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 22774.664079 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 22774.664079 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -799,54 +799,54 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 834403 # number of writebacks -system.cpu.dcache.writebacks::total 834403 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1068876 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1068876 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304232 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 304232 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17223 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 17223 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1373108 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1373108 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1373108 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1373108 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 20573355000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 20573355000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7990072500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 7990072500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 193251000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 193251000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28563427500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 28563427500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28563427500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 28563427500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1424236000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1424236000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2010997500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2010997500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3435233500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 3435233500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120435 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120435 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049452 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049452 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086010 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086010 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091375 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.091375 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091375 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.091375 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19247.653610 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19247.653610 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 26263.090339 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 26263.090339 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11220.519073 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11220.519073 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20802.025405 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20802.025405 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20802.025405 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20802.025405 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 834499 # number of writebacks +system.cpu.dcache.writebacks::total 834499 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1068716 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1068716 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304374 # 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number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2010997000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3435232500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 3435232500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120428 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120428 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049481 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049481 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086167 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086167 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091383 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.091383 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091383 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.091383 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19412.279782 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19412.279782 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25558.258918 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25558.258918 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11321.027008 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11321.027008 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20774.664079 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20774.664079 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20774.664079 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20774.664079 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency |