diff options
| author | Andreas Sandberg <andreas.sandberg@arm.com> | 2016-08-12 14:12:59 +0100 |
|---|---|---|
| committer | Andreas Sandberg <andreas.sandberg@arm.com> | 2016-08-12 14:12:59 +0100 |
| commit | 55ed9609f1056280404a8dc49e53e4ba33ae51dd (patch) | |
| tree | 6e50ced504e91a6d9dadff1b43b89a0911df3d7a /tests/quick/se | |
| parent | ee7d8fdcb2226139fd1d6a6f0cde987721ea3699 (diff) | |
| download | gem5-55ed9609f1056280404a8dc49e53e4ba33ae51dd.tar.xz | |
stats: Update to match classic memory changes
Diffstat (limited to 'tests/quick/se')
63 files changed, 18748 insertions, 18461 deletions
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt index 20c464e74..5987fdc63 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000038 # Number of seconds simulated -sim_ticks 37822000 # Number of ticks simulated -final_tick 37822000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 38282000 # Number of ticks simulated +final_tick 38282000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 100508 # Simulator instruction rate (inst/s) -host_op_rate 100471 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 592356577 # Simulator tick rate (ticks/s) -host_mem_usage 249008 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host +host_inst_rate 159466 # Simulator instruction rate (inst/s) +host_op_rate 159415 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 951356890 # Simulator tick rate (ticks/s) +host_mem_usage 253388 # Number of bytes of host memory used +host_seconds 0.04 # Real time elapsed on the host sim_insts 6413 # Number of instructions simulated sim_ops 6413 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 37822000 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 38282000 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 23232 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 10816 # Number of bytes read from this memory system.physmem.bytes_read::total 34048 # Number of bytes read from this memory @@ -22,14 +22,14 @@ system.physmem.bytes_inst_read::total 23232 # Nu system.physmem.num_reads::cpu.inst 363 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 169 # Number of read requests responded to by this memory system.physmem.num_reads::total 532 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 614245677 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 285971128 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 900216805 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 614245677 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 614245677 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 614245677 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 285971128 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 900216805 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 606864845 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 282534873 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 889399718 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 606864845 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 606864845 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 606864845 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 282534873 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 889399718 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 532 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 532 # Number of DRAM read bursts, including those serviced by the write queue @@ -76,7 +76,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 37718000 # Total gap between requests +system.physmem.totGap 38177000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -187,71 +187,71 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 82 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 385.560976 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 252.880176 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 333.081835 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 17 20.73% 20.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 21 25.61% 46.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 9 10.98% 57.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 11 13.41% 70.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 4 4.88% 75.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 3 3.66% 79.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 3 3.66% 82.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 5 6.10% 89.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 9 10.98% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 82 # Bytes accessed per row activation -system.physmem.totQLat 3215000 # Total ticks spent queuing -system.physmem.totMemAccLat 13190000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 83 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 377.831325 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 247.256857 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 329.629090 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 18 21.69% 21.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 20 24.10% 45.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 11 13.25% 59.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 11 13.25% 72.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 3 3.61% 75.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 4 4.82% 80.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 3 3.61% 84.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 4 4.82% 89.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 9 10.84% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 83 # Bytes accessed per row activation +system.physmem.totQLat 3252000 # Total ticks spent queuing +system.physmem.totMemAccLat 13227000 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2660000 # Total ticks spent in databus transfers -system.physmem.avgQLat 6043.23 # Average queueing delay per DRAM burst +system.physmem.avgQLat 6112.78 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 24793.23 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 900.22 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 24862.78 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 889.40 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 900.22 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 889.40 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 7.03 # Data bus utilization in percentage -system.physmem.busUtilRead 7.03 # Data bus utilization in percentage for reads +system.physmem.busUtil 6.95 # Data bus utilization in percentage +system.physmem.busUtilRead 6.95 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.18 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 438 # Number of row buffer hits during reads +system.physmem.readRowHits 437 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.33 # Row buffer hit rate for reads +system.physmem.readRowHitRate 82.14 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 70898.50 # Average gap between requests -system.physmem.pageHitRate 82.33 # Row buffer hit rate, read and write combined +system.physmem.avgGap 71761.28 # Average gap between requests +system.physmem.pageHitRate 82.14 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 234360 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 127875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 2043600 # Energy for read commands per rank (pJ) +system.physmem_0.readEnergy 2020200 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 2034240 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 21404070 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 67500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 25911645 # Total energy per rank (pJ) -system.physmem_0.averagePower 825.080242 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 366250 # Time in different power states +system.physmem_0.actBackEnergy 21270690 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 184500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 25871865 # Total energy per rank (pJ) +system.physmem_0.averagePower 823.813565 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 196750 # Time in different power states system.physmem_0.memoryStateTime::REF 1040000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 30363250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 30182000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 340200 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 185625 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1521000 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 347760 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 189750 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1505400 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 2034240 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 20148930 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1168500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 25398495 # Total energy per rank (pJ) -system.physmem_1.averagePower 808.740487 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1794750 # Time in different power states +system.physmem_1.actBackEnergy 20078820 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1230000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 25385970 # Total energy per rank (pJ) +system.physmem_1.averagePower 808.341665 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2146500 # Time in different power states system.physmem_1.memoryStateTime::REF 1040000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 28584000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 28481000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 37822000 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 38282000 # Cumulative time (in ticks) in various power states system.cpu.branchPred.lookups 2005 # Number of BP lookups system.cpu.branchPred.condPredicted 1239 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 379 # Number of conditional branches incorrect @@ -299,16 +299,16 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 37822000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 75644 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 38282000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 76564 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 6413 # Number of instructions committed system.cpu.committedOps 6413 # Number of ops (including micro ops) committed system.cpu.discardedOps 1095 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 11.795416 # CPI: cycles per instruction -system.cpu.ipc 0.084779 # IPC: instructions per cycle +system.cpu.cpi 11.938874 # CPI: cycles per instruction +system.cpu.ipc 0.083760 # IPC: instructions per cycle system.cpu.op_class_0::No_OpClass 19 0.30% 0.30% # Class of committed instruction system.cpu.op_class_0::IntAlu 4331 67.53% 67.83% # Class of committed instruction system.cpu.op_class_0::IntMult 1 0.02% 67.85% # Class of committed instruction @@ -345,24 +345,24 @@ system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 6413 # Class of committed instruction system.cpu.tickCycles 12651 # Number of cycles that the object actually ticked -system.cpu.idleCycles 62993 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 37822000 # Cumulative time (in ticks) in various power states +system.cpu.idleCycles 63913 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 38282000 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 103.701168 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 103.736314 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1990 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 169 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 11.775148 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 103.701168 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.025318 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.025318 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 103.736314 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.025326 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.025326 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 169 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 22 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 147 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.041260 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 4591 # Number of tag accesses system.cpu.dcache.tags.data_accesses 4591 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 37822000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 38282000 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 1250 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1250 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 740 # number of WriteReq hits @@ -379,14 +379,14 @@ system.cpu.dcache.demand_misses::cpu.data 221 # n system.cpu.dcache.demand_misses::total 221 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 221 # number of overall misses system.cpu.dcache.overall_misses::total 221 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 7590000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 7590000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 9158000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 9158000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 16748000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 16748000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 16748000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 16748000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 7713000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 7713000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 9281000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 9281000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 16994000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 16994000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 16994000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 16994000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1346 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1346 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) @@ -403,14 +403,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.099955 system.cpu.dcache.demand_miss_rate::total 0.099955 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.099955 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.099955 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 79062.500000 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 79062.500000 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73264 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 73264 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 75782.805430 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 75782.805430 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 75782.805430 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 75782.805430 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 80343.750000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 80343.750000 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 74248 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 74248 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 76895.927602 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 76895.927602 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 76895.927602 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 76895.927602 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -431,14 +431,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 169 system.cpu.dcache.demand_mshr_misses::total 169 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 169 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 169 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7494000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 7494000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5379500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5379500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12873500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 12873500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12873500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 12873500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7617000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 7617000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5452500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5452500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13069500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 13069500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13069500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 13069500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.071322 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.071322 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses @@ -447,31 +447,31 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.076436 system.cpu.dcache.demand_mshr_miss_rate::total 0.076436 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076436 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.076436 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78062.500000 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78062.500000 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73691.780822 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73691.780822 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76174.556213 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 76174.556213 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76174.556213 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 76174.556213 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 37822000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 79343.750000 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 79343.750000 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74691.780822 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74691.780822 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77334.319527 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 77334.319527 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77334.319527 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 77334.319527 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 38282000 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 174.485780 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 174.445567 # Cycle average of tags in use system.cpu.icache.tags.total_refs 2322 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 364 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 6.379121 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 174.485780 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.085198 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.085198 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 174.445567 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.085178 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.085178 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 364 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 105 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 259 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 260 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.177734 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 5736 # Number of tag accesses system.cpu.icache.tags.data_accesses 5736 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 37822000 # Cumulative time (in ticks) in various power states +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 38282000 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 2322 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 2322 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 2322 # number of demand (read+write) hits @@ -484,12 +484,12 @@ system.cpu.icache.demand_misses::cpu.inst 364 # n system.cpu.icache.demand_misses::total 364 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 364 # number of overall misses system.cpu.icache.overall_misses::total 364 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 28087500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 28087500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 28087500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 28087500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 28087500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 28087500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 28460500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 28460500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 28460500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 28460500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 28460500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 28460500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 2686 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 2686 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 2686 # number of demand (read+write) accesses @@ -502,12 +502,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.135517 system.cpu.icache.demand_miss_rate::total 0.135517 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.135517 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.135517 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 77163.461538 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 77163.461538 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 77163.461538 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 77163.461538 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 77163.461538 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 77163.461538 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 78188.186813 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 78188.186813 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 78188.186813 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 78188.186813 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 78188.186813 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 78188.186813 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -520,43 +520,43 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 364 system.cpu.icache.demand_mshr_misses::total 364 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 364 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 364 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 27723500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 27723500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 27723500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 27723500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 27723500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 27723500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 28096500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 28096500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 28096500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 28096500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 28096500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 28096500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.135517 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.135517 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.135517 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.135517 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.135517 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.135517 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 76163.461538 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 76163.461538 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 76163.461538 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 76163.461538 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 76163.461538 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 76163.461538 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 37822000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 77188.186813 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 77188.186813 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 77188.186813 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 77188.186813 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 77188.186813 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 77188.186813 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 38282000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 232.271171 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 278.242026 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 459 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.002179 # Average number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 532 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.001880 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 174.500375 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 57.770796 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005325 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.001763 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.007088 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 459 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 121 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 338 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.014008 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_blocks::cpu.inst 174.459359 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 103.782667 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005324 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.003167 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.008491 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 532 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 125 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 407 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.016235 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 4796 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 4796 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 37822000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 38282000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1 # number of ReadCleanReq hits system.cpu.l2cache.ReadCleanReq_hits::total 1 # number of ReadCleanReq hits system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits @@ -575,18 +575,18 @@ system.cpu.l2cache.demand_misses::total 532 # nu system.cpu.l2cache.overall_misses::cpu.inst 363 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 169 # number of overall misses system.cpu.l2cache.overall_misses::total 532 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5270000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 5270000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 27166000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 27166000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 7348500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 7348500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 27166000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 12618500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 39784500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 27166000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 12618500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 39784500 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5343000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 5343000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 27539000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 27539000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 7471500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 7471500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 27539000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 12814500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 40353500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 27539000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 12814500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 40353500 # number of overall miss cycles system.cpu.l2cache.ReadExReq_accesses::cpu.data 73 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 73 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 364 # number of ReadCleanReq accesses(hits+misses) @@ -611,18 +611,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.998124 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.997253 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.998124 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72191.780822 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72191.780822 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74837.465565 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74837.465565 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 76546.875000 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 76546.875000 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74837.465565 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74665.680473 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 74782.894737 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74837.465565 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74665.680473 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 74782.894737 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73191.780822 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73191.780822 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75865.013774 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75865.013774 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 77828.125000 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 77828.125000 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75865.013774 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75825.443787 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 75852.443609 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75865.013774 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75825.443787 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 75852.443609 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -641,18 +641,18 @@ system.cpu.l2cache.demand_mshr_misses::total 532 system.cpu.l2cache.overall_mshr_misses::cpu.inst 363 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 169 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 532 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4540000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4540000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 23536000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 23536000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6388500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 6388500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 23536000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10928500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 34464500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 23536000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10928500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 34464500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4613000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4613000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 23909000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 23909000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6511500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 6511500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 23909000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11124500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 35033500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 23909000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11124500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 35033500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.997253 # mshr miss rate for ReadCleanReq accesses @@ -665,25 +665,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.998124 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.997253 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.998124 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62191.780822 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62191.780822 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64837.465565 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64837.465565 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 66546.875000 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 66546.875000 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64837.465565 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64665.680473 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64782.894737 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64837.465565 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64665.680473 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64782.894737 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63191.780822 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63191.780822 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65865.013774 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65865.013774 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 67828.125000 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 67828.125000 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65865.013774 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65825.443787 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65852.443609 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65865.013774 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65825.443787 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65852.443609 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 533 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 37822000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 38282000 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 460 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 73 # Transaction distribution @@ -714,7 +714,13 @@ system.cpu.toL2Bus.respLayer0.occupancy 546000 # La system.cpu.toL2Bus.respLayer0.utilization 1.4 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 253500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 37822000 # Cumulative time (in ticks) in various power states +system.membus.snoop_filter.tot_requests 532 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 38282000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 459 # Transaction distribution system.membus.trans_dist::ReadExReq 73 # Transaction distribution system.membus.trans_dist::ReadExResp 73 # Transaction distribution @@ -738,6 +744,6 @@ system.membus.snoop_fanout::total 532 # Re system.membus.reqLayer0.occupancy 608000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.6 # Layer utilization (%) system.membus.respLayer1.occupancy 2826500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 7.5 # Layer utilization (%) +system.membus.respLayer1.utilization 7.4 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt index 0781260bf..1341b2242 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000022 # Number of seconds simulated -sim_ticks 22019000 # Number of ticks simulated -final_tick 22019000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 22248000 # Number of ticks simulated +final_tick 22248000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 122018 # Simulator instruction rate (inst/s) -host_op_rate 121990 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 420608458 # Simulator tick rate (ticks/s) -host_mem_usage 250288 # Number of bytes of host memory used -host_seconds 0.05 # Real time elapsed on the host +host_inst_rate 114507 # Simulator instruction rate (inst/s) +host_op_rate 114481 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 398824007 # Simulator tick rate (ticks/s) +host_mem_usage 254412 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host sim_insts 6385 # Number of instructions simulated sim_ops 6385 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 22019000 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 22248000 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 19968 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 11072 # Number of bytes read from this memory system.physmem.bytes_read::total 31040 # Number of bytes read from this memory @@ -22,14 +22,14 @@ system.physmem.bytes_inst_read::total 19968 # Nu system.physmem.num_reads::cpu.inst 312 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 173 # Number of read requests responded to by this memory system.physmem.num_reads::total 485 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 906853172 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 502838458 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1409691630 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 906853172 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 906853172 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 906853172 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 502838458 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1409691630 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 897518878 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 497662711 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1395181589 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 897518878 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 897518878 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 897518878 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 497662711 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1395181589 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 485 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 485 # Number of DRAM read bursts, including those serviced by the write queue @@ -76,7 +76,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 21881000 # Total gap between requests +system.physmem.totGap 22109000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -92,8 +92,8 @@ system.physmem.writePktSize::4 0 # Wr system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) system.physmem.rdQLenPdf::0 272 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 133 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 57 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 135 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 55 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 15 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -188,76 +188,76 @@ system.physmem.wrQLenPdf::61 0 # Wh system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see system.physmem.bytesPerActivate::samples 76 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 353.684211 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 230.878571 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 321.867393 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 352.842105 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 230.159600 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 321.021248 # Bytes accessed per row activation system.physmem.bytesPerActivate::0-127 18 23.68% 23.68% # Bytes accessed per row activation system.physmem.bytesPerActivate::128-255 19 25.00% 48.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 10 13.16% 61.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 10 13.16% 75.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 5 6.58% 81.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2 2.63% 84.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 9 11.84% 60.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 11 14.47% 75.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 6 7.89% 82.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1 1.32% 84.21% # Bytes accessed per row activation system.physmem.bytesPerActivate::768-895 2 2.63% 86.84% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 10 13.16% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 76 # Bytes accessed per row activation -system.physmem.totQLat 4444750 # Total ticks spent queuing -system.physmem.totMemAccLat 13538500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 4498250 # Total ticks spent queuing +system.physmem.totMemAccLat 13592000 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2425000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9164.43 # Average queueing delay per DRAM burst +system.physmem.avgQLat 9274.74 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 27914.43 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1409.69 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 28024.74 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1395.18 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1409.69 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1395.18 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 11.01 # Data bus utilization in percentage -system.physmem.busUtilRead 11.01 # Data bus utilization in percentage for reads +system.physmem.busUtil 10.90 # Data bus utilization in percentage +system.physmem.busUtilRead 10.90 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.74 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.73 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing system.physmem.readRowHits 394 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 81.24 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 45115.46 # Average gap between requests +system.physmem.avgGap 45585.57 # Average gap between requests system.physmem.pageHitRate 81.24 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 196560 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 107250 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1653600 # Energy for read commands per rank (pJ) +system.physmem_0.readEnergy 1645800 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) system.physmem_0.actBackEnergy 10785825 # Energy for active background per rank (pJ) system.physmem_0.preBackEnergy 38250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 13798605 # Total energy per rank (pJ) -system.physmem_0.averagePower 871.536712 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 297750 # Time in different power states +system.physmem_0.totalEnergy 13790805 # Total energy per rank (pJ) +system.physmem_0.averagePower 871.044055 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 22500 # Time in different power states system.physmem_0.memoryStateTime::REF 520000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_0.memoryStateTime::ACT 15303750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.physmem_1.actEnergy 294840 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 160875 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1271400 # Energy for read commands per rank (pJ) +system.physmem_1.readEnergy 1255800 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 10085580 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 657000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 13486815 # Total energy per rank (pJ) -system.physmem_1.averagePower 851.440341 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1024500 # Time in different power states +system.physmem_1.actBackEnergy 10074465 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 662250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 13465350 # Total energy per rank (pJ) +system.physmem_1.averagePower 850.487920 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1034500 # Time in different power states system.physmem_1.memoryStateTime::REF 520000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 14308250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 14291750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 22019000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 2849 # Number of BP lookups -system.cpu.branchPred.condPredicted 1676 # Number of conditional branches predicted +system.pwrStateResidencyTicks::UNDEFINED 22248000 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 2853 # Number of BP lookups +system.cpu.branchPred.condPredicted 1680 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 481 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 2197 # Number of BTB lookups +system.cpu.branchPred.BTBLookups 2201 # Number of BTB lookups system.cpu.branchPred.BTBHits 713 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 32.453345 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 32.394366 # BTB Hit Percentage system.cpu.branchPred.usedRAS 442 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 41 # Number of incorrect RAS predictions. system.cpu.branchPred.indirectLookups 461 # Number of indirect predictor lookups. @@ -281,10 +281,10 @@ system.cpu.dtb.data_hits 3300 # DT system.cpu.dtb.data_misses 76 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations system.cpu.dtb.data_accesses 3376 # DTB accesses -system.cpu.itb.fetch_hits 2293 # ITB hits +system.cpu.itb.fetch_hits 2294 # ITB hits system.cpu.itb.fetch_misses 27 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 2320 # ITB accesses +system.cpu.itb.fetch_accesses 2321 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -298,65 +298,65 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 22019000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 44039 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 22248000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 44497 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 8533 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 16533 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2849 # Number of branches that fetch encountered +system.cpu.fetch.icacheStallCycles 8475 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 16557 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2853 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 1180 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 5068 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.Cycles 5121 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 1044 # Number of cycles fetch has spent squashing system.cpu.fetch.MiscStallCycles 22 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 654 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 2293 # Number of cache lines fetched +system.cpu.fetch.PendingTrapStallCycles 656 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 2294 # Number of cache lines fetched system.cpu.fetch.IcacheSquashes 333 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 14799 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.117170 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.500450 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::samples 14796 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.119019 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.502117 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 11815 79.84% 79.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 299 2.02% 81.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 232 1.57% 83.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 256 1.73% 85.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 292 1.97% 87.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 232 1.57% 88.70% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 283 1.91% 90.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 144 0.97% 91.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1246 8.42% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 11808 79.81% 79.81% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 299 2.02% 81.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 232 1.57% 83.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 257 1.74% 85.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 292 1.97% 87.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 233 1.57% 88.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 283 1.91% 90.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 144 0.97% 91.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1248 8.43% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 14799 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.064693 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.375417 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 8370 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 3320 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2446 # Number of cycles decode is running +system.cpu.fetch.rateDist::total 14796 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.064117 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.372093 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 8328 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 3356 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2449 # Number of cycles decode is running system.cpu.decode.UnblockCycles 215 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 448 # Number of cycles decode is squashing system.cpu.decode.BranchResolved 226 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 75 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 14994 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 15018 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 221 # Number of squashed instructions handled by decode system.cpu.rename.SquashCycles 448 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 8529 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 1727 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 614 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2478 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 1003 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 14444 # Number of instructions processed by rename +system.cpu.rename.IdleCycles 8488 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 1745 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 620 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2480 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 1015 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 14460 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 2 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 21 # Number of times rename has blocked due to IQ full system.cpu.rename.LQFullEvents 10 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 937 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 10925 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 17893 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 17884 # Number of integer rename lookups +system.cpu.rename.SQFullEvents 949 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 10938 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 17913 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 17904 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 8 # Number of floating rename lookups system.cpu.rename.CommittedMaps 4577 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 6348 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 6361 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 28 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 22 # count of temporary serializing insts renamed system.cpu.rename.skidInsts 585 # count of insts added to the skid buffer @@ -364,109 +364,109 @@ system.cpu.memDep0.insertedLoads 2839 # Nu system.cpu.memDep0.insertedStores 1293 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 18 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 6 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 13053 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 13069 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 27 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 10776 # Number of instructions issued +system.cpu.iq.iqInstsIssued 10787 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 17 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 6694 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3672 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedInstsExamined 6710 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3679 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 10 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 14799 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.728157 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.465404 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 14796 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.729048 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.467428 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 10757 72.69% 72.69% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1297 8.76% 81.45% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 917 6.20% 87.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 680 4.59% 92.24% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 523 3.53% 95.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 348 2.35% 98.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 194 1.31% 99.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 10757 72.70% 72.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1291 8.73% 81.43% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 918 6.20% 87.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 680 4.60% 92.23% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 521 3.52% 95.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 349 2.36% 98.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 197 1.33% 99.44% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 55 0.37% 99.81% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 28 0.19% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 14799 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 14796 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 19 13.77% 13.77% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 13.77% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 13.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 13.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 13.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 13.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 13.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 13.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 13.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 13.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 13.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 13.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 13.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 13.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 13.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 13.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 13.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 13.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 13.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 13.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 13.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 13.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 13.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 13.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 13.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 13.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 13.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 13.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 13.77% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 82 59.42% 73.19% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 37 26.81% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 21 15.00% 15.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 15.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 15.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 15.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 15.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 15.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 15.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 15.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 15.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 15.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 15.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 15.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 15.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 15.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 15.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 15.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 15.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 15.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 15.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 15.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 15.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 15.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 15.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 15.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 15.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 15.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 15.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 15.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 15.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 82 58.57% 73.57% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 37 26.43% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 7177 66.60% 66.62% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1 0.01% 66.63% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.63% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 66.65% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.65% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.65% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.65% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.65% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.65% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.65% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.65% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.65% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.65% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.65% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.65% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.65% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.65% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.65% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.65% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.65% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.65% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.65% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.65% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.65% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.65% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.65% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.65% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.65% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.65% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2482 23.03% 89.68% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1112 10.32% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 7188 66.64% 66.65% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1 0.01% 66.66% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.66% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 66.68% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.68% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.68% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.68% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.68% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.68% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2482 23.01% 89.69% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1112 10.31% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 10776 # Type of FU issued -system.cpu.iq.rate 0.244692 # Inst issue rate -system.cpu.iq.fu_busy_cnt 138 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.012806 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 36485 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 19785 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 9739 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 10787 # Type of FU issued +system.cpu.iq.rate 0.242421 # Inst issue rate +system.cpu.iq.fu_busy_cnt 140 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.012979 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 36506 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 19817 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 9751 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 21 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 10 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 10 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 10901 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 10914 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 11 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 119 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address @@ -480,54 +480,54 @@ system.cpu.iew.lsq.thread0.rescheduledLoads 1 # system.cpu.iew.lsq.thread0.cacheBlocked 89 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewSquashCycles 448 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1371 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 296 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 13164 # Number of instructions dispatched to IQ +system.cpu.iew.iewBlockCycles 1381 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 302 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 13180 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 125 # Number of squashed instructions skipped by dispatch system.cpu.iew.iewDispLoadInsts 2839 # Number of dispatched load instructions system.cpu.iew.iewDispStoreInsts 1293 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 27 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 7 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 289 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 295 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 23 # Number of memory order violations system.cpu.iew.predictedTakenIncorrect 107 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 390 # Number of branches that were predicted not taken incorrectly system.cpu.iew.branchMispredicts 497 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 10291 # Number of executed instructions +system.cpu.iew.iewExecutedInsts 10303 # Number of executed instructions system.cpu.iew.iewExecLoadInsts 2309 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 485 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecSquashedInsts 484 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 84 # number of nop insts executed system.cpu.iew.exec_refs 3386 # number of memory reference insts executed -system.cpu.iew.exec_branches 1641 # Number of branches executed +system.cpu.iew.exec_branches 1643 # Number of branches executed system.cpu.iew.exec_stores 1077 # Number of stores executed -system.cpu.iew.exec_rate 0.233679 # Inst execution rate -system.cpu.iew.wb_sent 9945 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 9749 # cumulative count of insts written-back -system.cpu.iew.wb_producers 5139 # num instructions producing a value -system.cpu.iew.wb_consumers 7002 # num instructions consuming a value -system.cpu.iew.wb_rate 0.221372 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.733933 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 6711 # The number of squashed insts skipped by commit +system.cpu.iew.exec_rate 0.231544 # Inst execution rate +system.cpu.iew.wb_sent 9957 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 9761 # cumulative count of insts written-back +system.cpu.iew.wb_producers 5150 # num instructions producing a value +system.cpu.iew.wb_consumers 7013 # num instructions consuming a value +system.cpu.iew.wb_rate 0.219363 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.734350 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 6727 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 407 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 13565 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.471950 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.389989 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 13560 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.472124 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.390428 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 11138 82.11% 82.11% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1158 8.54% 90.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 11134 82.11% 82.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1157 8.53% 90.64% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::2 469 3.46% 94.10% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::3 205 1.51% 95.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 134 0.99% 96.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 84 0.62% 97.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 133 0.98% 96.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 85 0.63% 97.22% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::6 96 0.71% 97.93% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::7 89 0.66% 98.58% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::8 192 1.42% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 13565 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 13560 # Number of insts commited each cycle system.cpu.commit.committedInsts 6402 # Number of instructions committed system.cpu.commit.committedOps 6402 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -574,63 +574,63 @@ system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Cl system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 6402 # Class of committed instruction system.cpu.commit.bw_lim_events 192 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 26135 # The number of ROB reads -system.cpu.rob.rob_writes 27477 # The number of ROB writes -system.cpu.timesIdled 253 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 29240 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 26146 # The number of ROB reads +system.cpu.rob.rob_writes 27511 # The number of ROB writes +system.cpu.timesIdled 250 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 29701 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 6385 # Number of Instructions Simulated system.cpu.committedOps 6385 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 6.897259 # CPI: Cycles Per Instruction -system.cpu.cpi_total 6.897259 # CPI: Total CPI of All Threads -system.cpu.ipc 0.144985 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.144985 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 12924 # number of integer regfile reads -system.cpu.int_regfile_writes 7434 # number of integer regfile writes +system.cpu.cpi 6.968990 # CPI: Cycles Per Instruction +system.cpu.cpi_total 6.968990 # CPI: Total CPI of All Threads +system.cpu.ipc 0.143493 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.143493 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 12938 # number of integer regfile reads +system.cpu.int_regfile_writes 7444 # number of integer regfile writes system.cpu.fp_regfile_reads 8 # number of floating regfile reads system.cpu.fp_regfile_writes 2 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 22019000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 22248000 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 109.409218 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 2405 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 109.756228 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 2407 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 173 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 13.901734 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 13.913295 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 109.409218 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.026711 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.026711 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 109.756228 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.026796 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.026796 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 173 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 129 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.042236 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 6061 # Number of tag accesses system.cpu.dcache.tags.data_accesses 6061 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 22019000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 22248000 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 1899 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1899 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 506 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 506 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2405 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2405 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2405 # number of overall hits -system.cpu.dcache.overall_hits::total 2405 # number of overall hits +system.cpu.dcache.WriteReq_hits::cpu.data 508 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 508 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 2407 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2407 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2407 # number of overall hits +system.cpu.dcache.overall_hits::total 2407 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 180 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 180 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 359 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 359 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 539 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 539 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 539 # number of overall misses -system.cpu.dcache.overall_misses::total 539 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 12774500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 12774500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 23738475 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 23738475 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 36512975 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 36512975 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 36512975 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 36512975 # number of overall miss cycles +system.cpu.dcache.WriteReq_misses::cpu.data 357 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 357 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 537 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 537 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 537 # number of overall misses +system.cpu.dcache.overall_misses::total 537 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 12910000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 12910000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 24562475 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 24562475 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 37472475 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 37472475 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 37472475 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 37472475 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 2079 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 2079 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) @@ -641,34 +641,34 @@ system.cpu.dcache.overall_accesses::cpu.data 2944 system.cpu.dcache.overall_accesses::total 2944 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.086580 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.086580 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.415029 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.415029 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.183084 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.183084 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.183084 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.183084 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 70969.444444 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 70969.444444 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 66123.885794 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 66123.885794 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 67742.068646 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 67742.068646 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 67742.068646 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 67742.068646 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 2423 # number of cycles access was blocked +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.412717 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.412717 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.182405 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.182405 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.182405 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.182405 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 71722.222222 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 71722.222222 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 68802.450980 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 68802.450980 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 69781.145251 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 69781.145251 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 69781.145251 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 69781.145251 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 2459 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 43 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 56.348837 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 57.186047 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.ReadReq_mshr_hits::cpu.data 79 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 79 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 287 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 287 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 366 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 366 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 366 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 366 # number of overall MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 285 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 285 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 364 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 364 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 364 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 364 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 101 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 101 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 72 # number of WriteReq MSHR misses @@ -677,14 +677,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 173 system.cpu.dcache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 173 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 173 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8466000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 8466000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5695500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5695500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14161500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 14161500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14161500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 14161500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8568000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 8568000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6031500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 6031500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14599500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 14599500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14599500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 14599500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.048581 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.048581 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.083237 # mshr miss rate for WriteReq accesses @@ -693,122 +693,122 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.058764 system.cpu.dcache.demand_mshr_miss_rate::total 0.058764 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.058764 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.058764 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 83821.782178 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 83821.782178 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79104.166667 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79104.166667 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 81858.381503 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 81858.381503 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 81858.381503 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 81858.381503 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 22019000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 84831.683168 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 84831.683168 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 83770.833333 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 83770.833333 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 84390.173410 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 84390.173410 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 84390.173410 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 84390.173410 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 22248000 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 158.432951 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1836 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 159.084059 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1838 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 313 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 5.865815 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 5.872204 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 158.432951 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.077360 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.077360 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 159.084059 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.077678 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.077678 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 313 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 139 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 174 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 137 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 176 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.152832 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 4899 # Number of tag accesses -system.cpu.icache.tags.data_accesses 4899 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 22019000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 1836 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1836 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1836 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1836 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1836 # number of overall hits -system.cpu.icache.overall_hits::total 1836 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 457 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 457 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 457 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 457 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 457 # number of overall misses -system.cpu.icache.overall_misses::total 457 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 32838500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 32838500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 32838500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 32838500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 32838500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 32838500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 2293 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 2293 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 2293 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 2293 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 2293 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 2293 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.199302 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.199302 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.199302 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.199302 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.199302 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.199302 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 71856.673961 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 71856.673961 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 71856.673961 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 71856.673961 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 71856.673961 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 71856.673961 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 54 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 4901 # Number of tag accesses +system.cpu.icache.tags.data_accesses 4901 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 22248000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 1838 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1838 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1838 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1838 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1838 # number of overall hits +system.cpu.icache.overall_hits::total 1838 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 456 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 456 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 456 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 456 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 456 # number of overall misses +system.cpu.icache.overall_misses::total 456 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 32999500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 32999500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 32999500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 32999500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 32999500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 32999500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 2294 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 2294 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 2294 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 2294 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 2294 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 2294 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.198779 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.198779 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.198779 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.198779 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.198779 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.198779 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 72367.324561 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 72367.324561 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 72367.324561 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 72367.324561 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 72367.324561 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 72367.324561 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 56 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 54 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 56 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 144 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 144 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 144 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 144 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 144 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 144 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 143 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 143 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 143 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 143 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 143 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 143 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 313 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 313 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 313 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 313 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 313 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 313 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24470500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 24470500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24470500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 24470500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24470500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 24470500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.136502 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.136502 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.136502 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.136502 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.136502 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.136502 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 78180.511182 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 78180.511182 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 78180.511182 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 78180.511182 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 78180.511182 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 78180.511182 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 22019000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24573000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 24573000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24573000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 24573000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24573000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 24573000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.136443 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.136443 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.136443 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.136443 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.136443 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.136443 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 78507.987220 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 78507.987220 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 78507.987220 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 78507.987220 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 78507.987220 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 78507.987220 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 22248000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 220.994877 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 268.962928 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 413 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.002421 # Average number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 485 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.002062 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 158.475596 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 62.519281 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004836 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.001908 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.006744 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 413 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 172 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 241 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012604 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_blocks::cpu.inst 159.125052 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 109.837876 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004856 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.003352 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.008208 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 485 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 180 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 305 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.014801 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 4373 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 4373 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 22019000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 22248000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1 # number of ReadCleanReq hits system.cpu.l2cache.ReadCleanReq_hits::total 1 # number of ReadCleanReq hits system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits @@ -827,18 +827,18 @@ system.cpu.l2cache.demand_misses::total 485 # nu system.cpu.l2cache.overall_misses::cpu.inst 312 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 173 # number of overall misses system.cpu.l2cache.overall_misses::total 485 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5584500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 5584500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 23987500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 23987500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 8306000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 8306000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 23987500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 13890500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 37878000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 23987500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 13890500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 37878000 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5920500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 5920500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 24090000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 24090000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 8408000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 8408000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 24090000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 14328500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 38418500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 24090000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 14328500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 38418500 # number of overall miss cycles system.cpu.l2cache.ReadExReq_accesses::cpu.data 72 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 72 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 313 # number of ReadCleanReq accesses(hits+misses) @@ -863,18 +863,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.997942 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996805 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.997942 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77562.500000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77562.500000 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76883.012821 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76883.012821 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 82237.623762 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 82237.623762 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76883.012821 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 80291.907514 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 78098.969072 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76883.012821 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 80291.907514 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 78098.969072 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 82229.166667 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 82229.166667 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 77211.538462 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 77211.538462 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 83247.524752 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 83247.524752 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77211.538462 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 82823.699422 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 79213.402062 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77211.538462 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 82823.699422 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 79213.402062 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -893,18 +893,18 @@ system.cpu.l2cache.demand_mshr_misses::total 485 system.cpu.l2cache.overall_mshr_misses::cpu.inst 312 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 173 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 485 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4864500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4864500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 20867500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 20867500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7296000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 7296000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 20867500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 12160500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 33028000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 20867500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 12160500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 33028000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5200500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5200500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 20970000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 20970000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7398000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 7398000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 20970000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 12598500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 33568500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 20970000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 12598500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 33568500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.996805 # mshr miss rate for ReadCleanReq accesses @@ -917,25 +917,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.997942 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996805 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.997942 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67562.500000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67562.500000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66883.012821 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66883.012821 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72237.623762 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72237.623762 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66883.012821 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70291.907514 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68098.969072 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66883.012821 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70291.907514 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68098.969072 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 72229.166667 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 72229.166667 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67211.538462 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67211.538462 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73247.524752 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73247.524752 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67211.538462 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72823.699422 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69213.402062 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67211.538462 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72823.699422 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69213.402062 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 486 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 22019000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 22248000 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 414 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 72 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 72 # Transaction distribution @@ -966,7 +966,13 @@ system.cpu.toL2Bus.respLayer0.occupancy 469500 # La system.cpu.toL2Bus.respLayer0.utilization 2.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 259500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 22019000 # Cumulative time (in ticks) in various power states +system.membus.snoop_filter.tot_requests 485 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 22248000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 413 # Transaction distribution system.membus.trans_dist::ReadExReq 72 # Transaction distribution system.membus.trans_dist::ReadExResp 72 # Transaction distribution @@ -987,9 +993,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 485 # Request fanout histogram -system.membus.reqLayer0.occupancy 590500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 591500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 2579250 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 11.7 # Layer utilization (%) +system.membus.respLayer1.occupancy 2578750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 11.6 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/stats.txt index 724287a51..f237b4325 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000003 # Nu sim_ticks 3214500 # Number of ticks simulated final_tick 3214500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1026789 # Simulator instruction rate (inst/s) -host_op_rate 1024872 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 513643962 # Simulator tick rate (ticks/s) -host_mem_usage 238508 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host +host_inst_rate 280584 # Simulator instruction rate (inst/s) +host_op_rate 280421 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 140703848 # Simulator tick rate (ticks/s) +host_mem_usage 242116 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host sim_insts 6403 # Number of instructions simulated sim_ops 6403 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -130,6 +130,12 @@ system.cpu.op_class::MemWrite 868 13.54% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 6413 # Class of executed instruction +system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.pwrStateResidencyTicks::UNDEFINED 3214500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 7598 # Transaction distribution system.membus.trans_dist::ReadResp 7598 # Transaction distribution @@ -144,14 +150,14 @@ system.membus.pkt_size::total 41152 # Cu system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) system.membus.snoop_fanout::samples 8463 # Request fanout histogram -system.membus.snoop_fanout::mean 0.757769 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.428459 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 2050 24.22% 24.22% # Request fanout histogram -system.membus.snoop_fanout::1 6413 75.78% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 8463 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 8463 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt index d4fc31bad..ffd6a3082 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000036 # Number of seconds simulated -sim_ticks 35682500 # Number of ticks simulated -final_tick 35682500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 36128500 # Number of ticks simulated +final_tick 36128500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 318235 # Simulator instruction rate (inst/s) -host_op_rate 317806 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1768975757 # Simulator tick rate (ticks/s) -host_mem_usage 248500 # Number of bytes of host memory used +host_inst_rate 310790 # Simulator instruction rate (inst/s) +host_op_rate 310669 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1752338800 # Simulator tick rate (ticks/s) +host_mem_usage 252108 # Number of bytes of host memory used host_seconds 0.02 # Real time elapsed on the host sim_insts 6403 # Number of instructions simulated sim_ops 6403 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 35682500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 36128500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 17792 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 10752 # Number of bytes read from this memory system.physmem.bytes_read::total 28544 # Number of bytes read from this memory @@ -22,15 +22,15 @@ system.physmem.bytes_inst_read::total 17792 # Nu system.physmem.num_reads::cpu.inst 278 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 168 # Number of read requests responded to by this memory system.physmem.num_reads::total 446 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 498619772 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 301324179 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 799943950 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 498619772 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 498619772 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 498619772 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 301324179 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 799943950 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 35682500 # Cumulative time (in ticks) in various power states +system.physmem.bw_read::cpu.inst 492464398 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 297604384 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 790068782 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 492464398 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 492464398 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 492464398 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 297604384 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 790068782 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 36128500 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses @@ -65,8 +65,8 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 35682500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 71365 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 36128500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 72257 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 6403 # Number of instructions committed @@ -85,7 +85,7 @@ system.cpu.num_mem_refs 2060 # nu system.cpu.num_load_insts 1192 # Number of load instructions system.cpu.num_store_insts 868 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 71365 # Number of busy cycles +system.cpu.num_busy_cycles 72257 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 1056 # Number of branches fetched @@ -124,23 +124,23 @@ system.cpu.op_class::MemWrite 868 13.54% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 6413 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 35682500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 36128500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 103.763836 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 103.721081 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1882 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 168 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 11.202381 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 103.763836 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.025333 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.025333 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 103.721081 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.025323 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.025323 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 168 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 25 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 143 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 144 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.041016 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 4268 # Number of tag accesses system.cpu.dcache.tags.data_accesses 4268 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 35682500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 36128500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 1090 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1090 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 792 # number of WriteReq hits @@ -157,14 +157,14 @@ system.cpu.dcache.demand_misses::cpu.data 168 # n system.cpu.dcache.demand_misses::total 168 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 168 # number of overall misses system.cpu.dcache.overall_misses::total 168 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5890000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5890000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 4526000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 4526000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 10416000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 10416000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 10416000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 10416000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5985000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5985000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4599000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4599000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 10584000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 10584000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 10584000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 10584000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1185 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1185 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) @@ -181,14 +181,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.081951 system.cpu.dcache.demand_miss_rate::total 0.081951 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.081951 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.081951 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62000 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 62000 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 62000 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 62000 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 62000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 62000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 62000 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 63000 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 63000 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 63000 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 63000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 63000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 63000 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -203,14 +203,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 168 system.cpu.dcache.demand_mshr_misses::total 168 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 168 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5795000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5795000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4453000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4453000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10248000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10248000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10248000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10248000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5890000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5890000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4526000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4526000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10416000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10416000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10416000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10416000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.080169 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.080169 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses @@ -219,31 +219,31 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.081951 system.cpu.dcache.demand_mshr_miss_rate::total 0.081951 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.081951 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.081951 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61000 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61000 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 35682500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 62000 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 62000 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62000 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 62000 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 62000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 62000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 62000 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 36128500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 127.232065 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 127.170991 # Cycle average of tags in use system.cpu.icache.tags.total_refs 6135 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 279 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 21.989247 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 127.232065 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.062125 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.062125 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 127.170991 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.062095 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.062095 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 279 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 95 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 184 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 94 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 185 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.136230 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 13107 # Number of tag accesses system.cpu.icache.tags.data_accesses 13107 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 35682500 # Cumulative time (in ticks) in various power states +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 36128500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 6135 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 6135 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 6135 # number of demand (read+write) hits @@ -256,12 +256,12 @@ system.cpu.icache.demand_misses::cpu.inst 279 # n system.cpu.icache.demand_misses::total 279 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 279 # number of overall misses system.cpu.icache.overall_misses::total 279 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 17250500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 17250500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 17250500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 17250500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 17250500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 17250500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 17528500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 17528500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 17528500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 17528500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 17528500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 17528500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 6414 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 6414 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 6414 # number of demand (read+write) accesses @@ -274,12 +274,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.043499 system.cpu.icache.demand_miss_rate::total 0.043499 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.043499 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.043499 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61829.749104 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 61829.749104 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 61829.749104 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 61829.749104 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 61829.749104 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 61829.749104 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62826.164875 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 62826.164875 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 62826.164875 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 62826.164875 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 62826.164875 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 62826.164875 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -292,43 +292,43 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 279 system.cpu.icache.demand_mshr_misses::total 279 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 279 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 279 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16971500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 16971500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16971500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 16971500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16971500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 16971500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17249500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 17249500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17249500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 17249500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17249500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 17249500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.043499 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.043499 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.043499 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.043499 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.043499 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.043499 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60829.749104 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60829.749104 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60829.749104 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 60829.749104 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60829.749104 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 60829.749104 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 35682500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61826.164875 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61826.164875 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61826.164875 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 61826.164875 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61826.164875 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 61826.164875 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 36128500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 184.000496 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 230.937880 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 373 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.002681 # Average number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 446 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.002242 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 127.230075 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 56.770421 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003883 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.001732 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.005615 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 373 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 112 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 261 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.011383 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_blocks::cpu.inst 127.167974 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 103.769906 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003881 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.003167 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.007048 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 446 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 117 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 329 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.013611 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 4022 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 4022 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 35682500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 36128500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1 # number of ReadCleanReq hits system.cpu.l2cache.ReadCleanReq_hits::total 1 # number of ReadCleanReq hits system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits @@ -347,18 +347,18 @@ system.cpu.l2cache.demand_misses::total 446 # nu system.cpu.l2cache.overall_misses::cpu.inst 278 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 168 # number of overall misses system.cpu.l2cache.overall_misses::total 446 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4343500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 4343500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 16541500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 16541500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 5652500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 5652500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 16541500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 9996000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 26537500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 16541500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 9996000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 26537500 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4416500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 4416500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 16819500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 16819500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 5747500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 5747500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 16819500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 10164000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 26983500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 16819500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 10164000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 26983500 # number of overall miss cycles system.cpu.l2cache.ReadExReq_accesses::cpu.data 73 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 73 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 279 # number of ReadCleanReq accesses(hits+misses) @@ -383,18 +383,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.997763 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996416 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.997763 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59501.798561 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59501.798561 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59501.798561 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59500 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 59501.121076 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59501.798561 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 59501.121076 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60501.798561 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60501.798561 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60500 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60500 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60501.798561 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60500 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 60501.121076 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60501.798561 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60500 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 60501.121076 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -413,18 +413,18 @@ system.cpu.l2cache.demand_mshr_misses::total 446 system.cpu.l2cache.overall_mshr_misses::cpu.inst 278 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 446 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3613500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3613500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 13761500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 13761500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4702500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4702500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 13761500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8316000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 22077500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 13761500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8316000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 22077500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3686500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3686500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 14039500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 14039500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4797500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4797500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 14039500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8484000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 22523500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 14039500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8484000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 22523500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.996416 # mshr miss rate for ReadCleanReq accesses @@ -437,25 +437,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.997763 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996416 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.997763 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49501.798561 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49501.798561 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49501.798561 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49501.121076 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49501.798561 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49501.121076 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50501.798561 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50501.798561 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50501.798561 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50501.121076 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50501.798561 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50501.121076 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 447 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 35682500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 36128500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 374 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 73 # Transaction distribution @@ -486,7 +486,13 @@ system.cpu.toL2Bus.respLayer0.occupancy 418500 # La system.cpu.toL2Bus.respLayer0.utilization 1.2 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 252000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 35682500 # Cumulative time (in ticks) in various power states +system.membus.snoop_filter.tot_requests 446 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 36128500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 373 # Transaction distribution system.membus.trans_dist::ReadExReq 73 # Transaction distribution system.membus.trans_dist::ReadExResp 73 # Transaction distribution @@ -508,7 +514,7 @@ system.membus.snoop_fanout::min_value 0 # Re system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 446 # Request fanout histogram system.membus.reqLayer0.occupancy 446500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 1.3 # Layer utilization (%) +system.membus.reqLayer0.utilization 1.2 # Layer utilization (%) system.membus.respLayer1.occupancy 2230000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 6.2 # Layer utilization (%) diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt index ac371de2b..95775a988 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000020 # Number of seconds simulated -sim_ticks 20329000 # Number of ticks simulated -final_tick 20329000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000021 # Number of seconds simulated +sim_ticks 20616000 # Number of ticks simulated +final_tick 20616000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 113549 # Simulator instruction rate (inst/s) -host_op_rate 113428 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 891182571 # Simulator tick rate (ticks/s) -host_mem_usage 248724 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host +host_inst_rate 91304 # Simulator instruction rate (inst/s) +host_op_rate 91266 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 727585147 # Simulator tick rate (ticks/s) +host_mem_usage 252076 # Number of bytes of host memory used +host_seconds 0.03 # Real time elapsed on the host sim_insts 2585 # Number of instructions simulated sim_ops 2585 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 20329000 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 20616000 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 14400 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 5440 # Number of bytes read from this memory system.physmem.bytes_read::total 19840 # Number of bytes read from this memory @@ -22,14 +22,14 @@ system.physmem.bytes_inst_read::total 14400 # Nu system.physmem.num_reads::cpu.inst 225 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 85 # Number of read requests responded to by this memory system.physmem.num_reads::total 310 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 708347681 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 267598013 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 975945693 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 708347681 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 708347681 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 708347681 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 267598013 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 975945693 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 698486612 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 263872720 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 962359333 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 698486612 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 698486612 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 698486612 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 263872720 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 962359333 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 310 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 310 # Number of DRAM read bursts, including those serviced by the write queue @@ -76,7 +76,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 20241500 # Total gap between requests +system.physmem.totGap 20527500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -188,70 +188,70 @@ system.physmem.wrQLenPdf::61 0 # Wh system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see system.physmem.bytesPerActivate::samples 41 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 429.268293 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 281.421645 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 332.320856 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 424.585366 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 277.937119 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 331.553388 # Bytes accessed per row activation system.physmem.bytesPerActivate::0-127 10 24.39% 24.39% # Bytes accessed per row activation system.physmem.bytesPerActivate::128-255 6 14.63% 39.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4 9.76% 48.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3 7.32% 56.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5 12.20% 51.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2 4.88% 56.10% # Bytes accessed per row activation system.physmem.bytesPerActivate::512-639 6 14.63% 70.73% # Bytes accessed per row activation system.physmem.bytesPerActivate::640-767 2 4.88% 75.61% # Bytes accessed per row activation system.physmem.bytesPerActivate::768-895 4 9.76% 85.37% # Bytes accessed per row activation system.physmem.bytesPerActivate::896-1023 3 7.32% 92.68% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 3 7.32% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 41 # Bytes accessed per row activation -system.physmem.totQLat 1774250 # Total ticks spent queuing -system.physmem.totMemAccLat 7586750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 1590750 # Total ticks spent queuing +system.physmem.totMemAccLat 7403250 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 1550000 # Total ticks spent in databus transfers -system.physmem.avgQLat 5723.39 # Average queueing delay per DRAM burst +system.physmem.avgQLat 5131.45 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 24473.39 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 975.95 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 23881.45 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 962.36 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 975.95 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 962.36 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 7.62 # Data bus utilization in percentage -system.physmem.busUtilRead 7.62 # Data bus utilization in percentage for reads +system.physmem.busUtil 7.52 # Data bus utilization in percentage +system.physmem.busUtilRead 7.52 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.25 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.24 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing system.physmem.readRowHits 260 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 83.87 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 65295.16 # Average gap between requests +system.physmem.avgGap 66217.74 # Average gap between requests system.physmem.pageHitRate 83.87 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 83160 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 45375 # Energy for precharge commands per rank (pJ) system.physmem_0.readEnergy 787800 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 10557540 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 238500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 12729495 # Total energy per rank (pJ) -system.physmem_0.averagePower 804.010422 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 825750 # Time in different power states +system.physmem_0.actBackEnergy 10790100 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 34500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 12758055 # Total energy per rank (pJ) +system.physmem_0.averagePower 805.814306 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 727750 # Time in different power states system.physmem_0.memoryStateTime::REF 520000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 14971750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 15310750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.physmem_1.actEnergy 189000 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 103125 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1185600 # Energy for read commands per rank (pJ) +system.physmem_1.readEnergy 1162200 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 10490850 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 299250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 13284945 # Total energy per rank (pJ) -system.physmem_1.averagePower 838.894625 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 457000 # Time in different power states +system.physmem_1.actBackEnergy 10417320 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 361500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 13250265 # Total energy per rank (pJ) +system.physmem_1.averagePower 836.902890 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 560000 # Time in different power states system.physmem_1.memoryStateTime::REF 520000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 14872250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 14766250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 20329000 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 20616000 # Cumulative time (in ticks) in various power states system.cpu.branchPred.lookups 794 # Number of BP lookups system.cpu.branchPred.condPredicted 394 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 170 # Number of conditional branches incorrect @@ -299,16 +299,16 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 20329000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 40658 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 20616000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 41232 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 2585 # Number of instructions committed system.cpu.committedOps 2585 # Number of ops (including micro ops) committed system.cpu.discardedOps 573 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 15.728433 # CPI: cycles per instruction -system.cpu.ipc 0.063579 # IPC: instructions per cycle +system.cpu.cpi 15.950484 # CPI: cycles per instruction +system.cpu.ipc 0.062694 # IPC: instructions per cycle system.cpu.op_class_0::No_OpClass 189 7.31% 7.31% # Class of committed instruction system.cpu.op_class_0::IntAlu 1678 64.91% 72.22% # Class of committed instruction system.cpu.op_class_0::IntMult 1 0.04% 72.26% # Class of committed instruction @@ -344,25 +344,25 @@ system.cpu.op_class_0::MemWrite 298 11.53% 100.00% # Cl system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 2585 # Class of committed instruction -system.cpu.tickCycles 5421 # Number of cycles that the object actually ticked -system.cpu.idleCycles 35237 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 20329000 # Cumulative time (in ticks) in various power states +system.cpu.tickCycles 5423 # Number of cycles that the object actually ticked +system.cpu.idleCycles 35809 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 20616000 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 48.302993 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 48.342284 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 692 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 85 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 8.141176 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 48.302993 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.011793 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.011793 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 48.342284 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.011802 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.011802 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 85 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 33 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 52 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.020752 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 1673 # Number of tag accesses system.cpu.dcache.tags.data_accesses 1673 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 20329000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 20616000 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 441 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 441 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 251 # number of WriteReq hits @@ -379,14 +379,14 @@ system.cpu.dcache.demand_misses::cpu.data 102 # n system.cpu.dcache.demand_misses::total 102 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 102 # number of overall misses system.cpu.dcache.overall_misses::total 102 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 4783500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 4783500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 3258000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 3258000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 8041500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 8041500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 8041500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 8041500 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 4617500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4617500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 3301000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 3301000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 7918500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 7918500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 7918500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 7918500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 500 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 500 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 294 # number of WriteReq accesses(hits+misses) @@ -403,14 +403,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.128463 system.cpu.dcache.demand_miss_rate::total 0.128463 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.128463 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.128463 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 81076.271186 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 81076.271186 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 75767.441860 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 75767.441860 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 78838.235294 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 78838.235294 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 78838.235294 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 78838.235294 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 78262.711864 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 78262.711864 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76767.441860 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 76767.441860 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 77632.352941 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 77632.352941 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 77632.352941 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 77632.352941 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -433,14 +433,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 85 system.cpu.dcache.demand_mshr_misses::total 85 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 85 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4654000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4654000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2017500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2017500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6671500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6671500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6671500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6671500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4487000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4487000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2044500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2044500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6531500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6531500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6531500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6531500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.116000 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.116000 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.091837 # mshr miss rate for WriteReq accesses @@ -449,31 +449,31 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.107053 system.cpu.dcache.demand_mshr_miss_rate::total 0.107053 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.107053 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.107053 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 80241.379310 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 80241.379310 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74722.222222 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74722.222222 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78488.235294 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 78488.235294 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78488.235294 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 78488.235294 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 20329000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 77362.068966 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 77362.068966 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75722.222222 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75722.222222 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76841.176471 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 76841.176471 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76841.176471 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 76841.176471 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 20616000 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 119.197826 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 119.307121 # Cycle average of tags in use system.cpu.icache.tags.total_refs 754 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 225 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 3.351111 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 119.197826 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.058202 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.058202 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 119.307121 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.058255 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.058255 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 225 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 100 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 125 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 98 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 127 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.109863 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 2183 # Number of tag accesses system.cpu.icache.tags.data_accesses 2183 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 20329000 # Cumulative time (in ticks) in various power states +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 20616000 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 754 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 754 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 754 # number of demand (read+write) hits @@ -486,12 +486,12 @@ system.cpu.icache.demand_misses::cpu.inst 225 # n system.cpu.icache.demand_misses::total 225 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 225 # number of overall misses system.cpu.icache.overall_misses::total 225 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 17116000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 17116000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 17116000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 17116000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 17116000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 17116000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 17383000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 17383000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 17383000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 17383000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 17383000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 17383000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 979 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 979 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 979 # number of demand (read+write) accesses @@ -504,12 +504,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.229826 system.cpu.icache.demand_miss_rate::total 0.229826 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.229826 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.229826 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 76071.111111 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 76071.111111 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 76071.111111 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 76071.111111 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 76071.111111 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 76071.111111 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 77257.777778 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 77257.777778 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 77257.777778 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 77257.777778 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 77257.777778 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 77257.777778 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -522,43 +522,43 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 225 system.cpu.icache.demand_mshr_misses::total 225 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 225 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 225 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16891000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 16891000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16891000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 16891000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16891000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 16891000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17158000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 17158000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17158000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 17158000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17158000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 17158000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.229826 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.229826 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.229826 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.229826 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.229826 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.229826 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75071.111111 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75071.111111 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75071.111111 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 75071.111111 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75071.111111 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 75071.111111 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 20329000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 76257.777778 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 76257.777778 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 76257.777778 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 76257.777778 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 76257.777778 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 76257.777778 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 20616000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 147.090026 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 167.807293 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 0 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 283 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 310 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 119.314039 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 27.775987 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003641 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.000848 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.004489 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 283 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 131 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 152 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.008636 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_blocks::cpu.inst 119.421716 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 48.385576 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003644 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.001477 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.005121 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 310 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 130 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 180 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.009460 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 2790 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 2790 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 20329000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 20616000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.ReadExReq_misses::cpu.data 27 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 27 # number of ReadExReq misses system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 225 # number of ReadCleanReq misses @@ -571,18 +571,18 @@ system.cpu.l2cache.demand_misses::total 310 # nu system.cpu.l2cache.overall_misses::cpu.inst 225 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 85 # number of overall misses system.cpu.l2cache.overall_misses::total 310 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1977000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1977000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 16553500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 16553500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 4566000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 4566000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 16553500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 6543000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 23096500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 16553500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 6543000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 23096500 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2004000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 2004000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 16820500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 16820500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 4399000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 4399000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 16820500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 6403000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 23223500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 16820500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 6403000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 23223500 # number of overall miss cycles system.cpu.l2cache.ReadExReq_accesses::cpu.data 27 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 27 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 225 # number of ReadCleanReq accesses(hits+misses) @@ -607,18 +607,18 @@ system.cpu.l2cache.demand_miss_rate::total 1 # system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73222.222222 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73222.222222 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 73571.111111 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 73571.111111 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 78724.137931 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 78724.137931 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73571.111111 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76976.470588 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 74504.838710 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73571.111111 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76976.470588 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 74504.838710 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74222.222222 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74222.222222 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74757.777778 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74757.777778 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 75844.827586 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 75844.827586 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74757.777778 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75329.411765 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 74914.516129 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74757.777778 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75329.411765 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 74914.516129 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -637,18 +637,18 @@ system.cpu.l2cache.demand_mshr_misses::total 310 system.cpu.l2cache.overall_mshr_misses::cpu.inst 225 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 310 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1707000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1707000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 14303500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 14303500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 3986000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 3986000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 14303500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5693000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 19996500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 14303500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5693000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 19996500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1734000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1734000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 14570500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 14570500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 3819000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 3819000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 14570500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5553000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 20123500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 14570500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5553000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 20123500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses @@ -661,25 +661,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 1 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63222.222222 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63222.222222 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 63571.111111 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 63571.111111 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 68724.137931 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 68724.137931 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63571.111111 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66976.470588 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64504.838710 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63571.111111 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66976.470588 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64504.838710 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64222.222222 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64222.222222 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64757.777778 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64757.777778 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 65844.827586 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 65844.827586 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64757.777778 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65329.411765 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64914.516129 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64757.777778 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65329.411765 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64914.516129 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 310 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 20329000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 20616000 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 283 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 27 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 27 # Transaction distribution @@ -707,10 +707,16 @@ system.cpu.toL2Bus.snoop_fanout::total 310 # Re system.cpu.toL2Bus.reqLayer0.occupancy 155000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 337500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 1.7 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.utilization 1.6 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 127500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.6 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 20329000 # Cumulative time (in ticks) in various power states +system.membus.snoop_filter.tot_requests 310 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 20616000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 283 # Transaction distribution system.membus.trans_dist::ReadExReq 27 # Transaction distribution system.membus.trans_dist::ReadExResp 27 # Transaction distribution @@ -733,7 +739,7 @@ system.membus.snoop_fanout::max_value 0 # Re system.membus.snoop_fanout::total 310 # Request fanout histogram system.membus.reqLayer0.occupancy 363000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 1648250 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 8.1 # Layer utilization (%) +system.membus.respLayer1.occupancy 1648750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 8.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt index 51e8f72d6..cdae5e837 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000012 # Number of seconds simulated -sim_ticks 12409500 # Number of ticks simulated -final_tick 12409500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000013 # Number of seconds simulated +sim_ticks 12542500 # Number of ticks simulated +final_tick 12542500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 95060 # Simulator instruction rate (inst/s) -host_op_rate 95002 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 493600045 # Simulator tick rate (ticks/s) -host_mem_usage 248984 # Number of bytes of host memory used -host_seconds 0.03 # Real time elapsed on the host +host_inst_rate 60996 # Simulator instruction rate (inst/s) +host_op_rate 60977 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 320317516 # Simulator tick rate (ticks/s) +host_mem_usage 253100 # Number of bytes of host memory used +host_seconds 0.04 # Real time elapsed on the host sim_insts 2387 # Number of instructions simulated sim_ops 2387 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 12409500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 12542500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 11968 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 5440 # Number of bytes read from this memory system.physmem.bytes_read::total 17408 # Number of bytes read from this memory @@ -22,14 +22,14 @@ system.physmem.bytes_inst_read::total 11968 # Nu system.physmem.num_reads::cpu.inst 187 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 85 # Number of read requests responded to by this memory system.physmem.num_reads::total 272 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 964422418 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 438373827 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1402796245 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 964422418 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 964422418 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 964422418 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 438373827 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1402796245 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 954195735 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 433725334 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1387921068 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 954195735 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 954195735 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 954195735 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 433725334 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1387921068 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 272 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 272 # Number of DRAM read bursts, including those serviced by the write queue @@ -76,7 +76,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 12313000 # Total gap between requests +system.physmem.totGap 12445000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -91,8 +91,8 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 156 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 81 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 157 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 80 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 29 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 5 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see @@ -188,9 +188,9 @@ system.physmem.wrQLenPdf::61 0 # Wh system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see system.physmem.bytesPerActivate::samples 36 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 398.222222 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 237.741650 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 358.174986 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 394.666667 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 235.952583 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 357.320824 # Bytes accessed per row activation system.physmem.bytesPerActivate::0-127 12 33.33% 33.33% # Bytes accessed per row activation system.physmem.bytesPerActivate::128-255 5 13.89% 47.22% # Bytes accessed per row activation system.physmem.bytesPerActivate::256-383 3 8.33% 55.56% # Bytes accessed per row activation @@ -201,37 +201,37 @@ system.physmem.bytesPerActivate::768-895 2 5.56% 83.33% # By system.physmem.bytesPerActivate::896-1023 1 2.78% 86.11% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 5 13.89% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 36 # Bytes accessed per row activation -system.physmem.totQLat 1652750 # Total ticks spent queuing -system.physmem.totMemAccLat 6752750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 1866000 # Total ticks spent queuing +system.physmem.totMemAccLat 6966000 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 1360000 # Total ticks spent in databus transfers -system.physmem.avgQLat 6076.29 # Average queueing delay per DRAM burst +system.physmem.avgQLat 6860.29 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 24826.29 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1402.80 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 25610.29 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1387.92 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1402.80 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1387.92 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 10.96 # Data bus utilization in percentage -system.physmem.busUtilRead 10.96 # Data bus utilization in percentage for reads +system.physmem.busUtil 10.84 # Data bus utilization in percentage +system.physmem.busUtilRead 10.84 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.68 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.70 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing system.physmem.readRowHits 226 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 83.09 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 45268.38 # Average gap between requests +system.physmem.avgGap 45753.68 # Average gap between requests system.physmem.pageHitRate 83.09 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 68040 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 37125 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 592800 # Energy for read commands per rank (pJ) +system.physmem_0.readEnergy 585000 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 508560 # Energy for refresh commands per rank (pJ) system.physmem_0.actBackEnergy 5478840 # Energy for active background per rank (pJ) system.physmem_0.preBackEnergy 21750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 6707115 # Total energy per rank (pJ) -system.physmem_0.averagePower 833.570297 # Core power per rank (mW) +system.physmem_0.totalEnergy 6699315 # Total energy per rank (pJ) +system.physmem_0.averagePower 832.600901 # Core power per rank (mW) system.physmem_0.memoryStateTime::IDLE 22500 # Time in different power states system.physmem_0.memoryStateTime::REF 260000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states @@ -239,31 +239,31 @@ system.physmem_0.memoryStateTime::ACT 7777500 # Ti system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.physmem_1.actEnergy 128520 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 70125 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 795600 # Energy for read commands per rank (pJ) +system.physmem_1.readEnergy 787800 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 508560 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 5200965 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 265500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 6969270 # Total energy per rank (pJ) -system.physmem_1.averagePower 866.151313 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 708000 # Time in different power states +system.physmem_1.actBackEnergy 5198400 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 267750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 6961155 # Total energy per rank (pJ) +system.physmem_1.averagePower 865.142768 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 432500 # Time in different power states system.physmem_1.memoryStateTime::REF 260000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 7371500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 7367500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 12409500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 1003 # Number of BP lookups +system.pwrStateResidencyTicks::UNDEFINED 12542500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 1001 # Number of BP lookups system.cpu.branchPred.condPredicted 492 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 213 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 688 # Number of BTB lookups +system.cpu.branchPred.BTBLookups 687 # Number of BTB lookups system.cpu.branchPred.BTBHits 176 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 25.581395 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 221 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 25.618632 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 220 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 18 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 101 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectLookups 100 # Number of indirect predictor lookups. system.cpu.branchPred.indirectHits 3 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 98 # Number of indirect misses. +system.cpu.branchPred.indirectMisses 97 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 33 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits @@ -282,10 +282,10 @@ system.cpu.dtb.data_hits 1061 # DT system.cpu.dtb.data_misses 30 # DTB misses system.cpu.dtb.data_acv 1 # DTB access violations system.cpu.dtb.data_accesses 1091 # DTB accesses -system.cpu.itb.fetch_hits 878 # ITB hits +system.cpu.itb.fetch_hits 877 # ITB hits system.cpu.itb.fetch_misses 32 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 910 # ITB accesses +system.cpu.itb.fetch_accesses 909 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -299,53 +299,53 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 12409500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 24820 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 12542500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 25086 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 4371 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 6065 # Number of instructions fetch has processed -system.cpu.fetch.Branches 1003 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 400 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 1173 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.icacheStallCycles 4377 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 6059 # Number of instructions fetch has processed +system.cpu.fetch.Branches 1001 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 399 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 1174 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 472 # Number of cycles fetch has spent squashing system.cpu.fetch.MiscStallCycles 18 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1146 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingTrapStallCycles 1154 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 11 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 878 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 148 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 6955 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.872035 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.274710 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 877 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 147 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 6970 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.869297 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.271813 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 5922 85.15% 85.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 27 0.39% 85.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 100 1.44% 86.97% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 87 1.25% 88.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 141 2.03% 90.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 81 1.16% 91.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 46 0.66% 92.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 76 1.09% 93.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 475 6.83% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 5938 85.19% 85.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 27 0.39% 85.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 100 1.43% 87.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 87 1.25% 88.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 141 2.02% 90.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 81 1.16% 91.45% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 45 0.65% 92.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 76 1.09% 93.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 475 6.81% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 6955 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.040411 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.244359 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 5210 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 623 # Number of cycles decode is blocked +system.cpu.fetch.rateDist::total 6970 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.039903 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.241529 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 5221 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 627 # Number of cycles decode is blocked system.cpu.decode.RunCycles 919 # Number of cycles decode is running system.cpu.decode.UnblockCycles 40 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 163 # Number of cycles decode is squashing system.cpu.decode.BranchResolved 145 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 75 # Number of times decode detected a branch misprediction system.cpu.decode.DecodedInsts 5274 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 268 # Number of squashed instructions handled by decode +system.cpu.decode.SquashedInsts 263 # Number of squashed instructions handled by decode system.cpu.rename.SquashCycles 163 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 5285 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 327 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 288 # count of cycles rename stalled for serializing inst +system.cpu.rename.IdleCycles 5296 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 329 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 290 # count of cycles rename stalled for serializing inst system.cpu.rename.RunCycles 881 # Number of cycles rename is running system.cpu.rename.UnblockCycles 11 # Number of cycles rename is unblocking system.cpu.rename.RenamedInsts 5069 # Number of instructions processed by rename @@ -371,23 +371,23 @@ system.cpu.iq.iqSquashedInstsIssued 28 # Nu system.cpu.iq.iqSquashedInstsExamined 2005 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedOperandsExamined 1025 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 6955 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.540331 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.279888 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 6970 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.539168 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.278867 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 5508 79.19% 79.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 469 6.74% 85.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 342 4.92% 90.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 254 3.65% 94.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 193 2.77% 97.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 103 1.48% 98.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 56 0.81% 99.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 5524 79.25% 79.25% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 467 6.70% 85.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 343 4.92% 90.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 254 3.64% 94.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 193 2.77% 97.29% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 103 1.48% 98.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 56 0.80% 99.57% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 20 0.29% 99.86% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 10 0.14% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 6955 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 6970 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 6 9.84% 9.84% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 9.84% # attempts to use FU when none available @@ -457,10 +457,10 @@ system.cpu.iq.FU_type_0::MemWrite 373 9.93% 100.00% # Ty system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::total 3758 # Type of FU issued -system.cpu.iq.rate 0.151410 # Inst issue rate +system.cpu.iq.rate 0.149805 # Inst issue rate system.cpu.iq.fu_busy_cnt 61 # FU busy when requested system.cpu.iq.fu_busy_rate 0.016232 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 14547 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_reads 14562 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 6395 # Number of integer instruction queue writes system.cpu.iq.int_inst_queue_wakeup_accesses 3419 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 13 # Number of floating instruction queue reads @@ -480,7 +480,7 @@ system.cpu.iew.lsq.thread0.rescheduledLoads 0 # system.cpu.iew.lsq.thread0.cacheBlocked 56 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewSquashCycles 163 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 297 # Number of cycles IEW is blocking +system.cpu.iew.iewBlockCycles 299 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 3 # Number of cycles IEW is unblocking system.cpu.iew.iewDispatchedInsts 4700 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 46 # Number of squashed instructions skipped by dispatch @@ -501,33 +501,33 @@ system.cpu.iew.exec_nop 307 # nu system.cpu.iew.exec_refs 1093 # number of memory reference insts executed system.cpu.iew.exec_branches 599 # Number of branches executed system.cpu.iew.exec_stores 366 # Number of stores executed -system.cpu.iew.exec_rate 0.146414 # Inst execution rate +system.cpu.iew.exec_rate 0.144862 # Inst execution rate system.cpu.iew.wb_sent 3483 # cumulative count of insts sent to commit system.cpu.iew.wb_count 3425 # cumulative count of insts written-back system.cpu.iew.wb_producers 1633 # num instructions producing a value system.cpu.iew.wb_consumers 2097 # num instructions consuming a value -system.cpu.iew.wb_rate 0.137994 # insts written-back per cycle +system.cpu.iew.wb_rate 0.136530 # insts written-back per cycle system.cpu.iew.wb_fanout 0.778732 # average fanout of values written-back system.cpu.commit.commitSquashedInsts 2122 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 4 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 140 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 6540 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.393884 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.249766 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 6555 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.392982 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.248476 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 5669 86.68% 86.68% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 198 3.03% 89.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 318 4.86% 94.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 5684 86.71% 86.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 198 3.02% 89.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 318 4.85% 94.58% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::3 118 1.80% 96.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 63 0.96% 97.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 63 0.96% 97.35% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::5 53 0.81% 98.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 37 0.57% 98.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 37 0.56% 98.72% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::7 23 0.35% 99.07% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::8 61 0.93% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 6540 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 6555 # Number of insts commited each cycle system.cpu.commit.committedInsts 2576 # Number of instructions committed system.cpu.commit.committedOps 2576 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -574,38 +574,38 @@ system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Cl system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 2576 # Class of committed instruction system.cpu.commit.bw_lim_events 61 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 10930 # The number of ROB reads +system.cpu.rob.rob_reads 10945 # The number of ROB reads system.cpu.rob.rob_writes 9815 # The number of ROB writes system.cpu.timesIdled 154 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 17865 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 18116 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 2387 # Number of Instructions Simulated system.cpu.committedOps 2387 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 10.397989 # CPI: Cycles Per Instruction -system.cpu.cpi_total 10.397989 # CPI: Total CPI of All Threads -system.cpu.ipc 0.096172 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.096172 # IPC: Total IPC of All Threads +system.cpu.cpi 10.509426 # CPI: Cycles Per Instruction +system.cpu.cpi_total 10.509426 # CPI: Total CPI of All Threads +system.cpu.ipc 0.095153 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.095153 # IPC: Total IPC of All Threads system.cpu.int_regfile_reads 4383 # number of integer regfile reads system.cpu.int_regfile_writes 2640 # number of integer regfile writes system.cpu.fp_regfile_reads 6 # number of floating regfile reads system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 12409500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 12542500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 45.439304 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 45.419736 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 735 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 85 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 8.647059 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 45.439304 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.011094 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.011094 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 45.419736 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.011089 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.011089 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 85 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 24 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.020752 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 1919 # Number of tag accesses system.cpu.dcache.tags.data_accesses 1919 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 12409500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 12542500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 522 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 522 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 213 # number of WriteReq hits @@ -622,14 +622,14 @@ system.cpu.dcache.demand_misses::cpu.data 182 # n system.cpu.dcache.demand_misses::total 182 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 182 # number of overall misses system.cpu.dcache.overall_misses::total 182 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 6673500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 6673500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 5672000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 5672000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 12345500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 12345500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 12345500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 12345500 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 6754500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 6754500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 5744000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 5744000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 12498500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 12498500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 12498500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 12498500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 623 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 623 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 294 # number of WriteReq accesses(hits+misses) @@ -646,19 +646,19 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.198473 system.cpu.dcache.demand_miss_rate::total 0.198473 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.198473 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.198473 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66074.257426 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 66074.257426 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 70024.691358 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 70024.691358 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 67832.417582 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 67832.417582 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 67832.417582 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 67832.417582 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 256 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66876.237624 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 66876.237624 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 70913.580247 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 70913.580247 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 68673.076923 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 68673.076923 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 68673.076923 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 68673.076923 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 260 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 6 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 42.666667 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 43.333333 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.ReadReq_mshr_hits::cpu.data 40 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 40 # number of ReadReq MSHR hits @@ -676,14 +676,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 85 system.cpu.dcache.demand_mshr_misses::total 85 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 85 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4797000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4797000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1851000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1851000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6648000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6648000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6648000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6648000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4858000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4858000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1875000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1875000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6733000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6733000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6733000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6733000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.097913 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.097913 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.081633 # mshr miss rate for WriteReq accesses @@ -692,72 +692,72 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.092694 system.cpu.dcache.demand_mshr_miss_rate::total 0.092694 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.092694 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.092694 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78639.344262 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78639.344262 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77125 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77125 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78211.764706 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 78211.764706 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78211.764706 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 78211.764706 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 12409500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 79639.344262 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 79639.344262 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78125 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78125 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 79211.764706 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 79211.764706 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 79211.764706 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 79211.764706 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 12542500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 90.399218 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 625 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 90.302659 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 624 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 187 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 3.342246 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 3.336898 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 90.399218 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.044140 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.044140 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 90.302659 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.044093 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.044093 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 187 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 158 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 29 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 156 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 31 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.091309 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 1943 # Number of tag accesses -system.cpu.icache.tags.data_accesses 1943 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 12409500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 625 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 625 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 625 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 625 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 625 # number of overall hits -system.cpu.icache.overall_hits::total 625 # number of overall hits +system.cpu.icache.tags.tag_accesses 1941 # Number of tag accesses +system.cpu.icache.tags.data_accesses 1941 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 12542500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 624 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 624 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 624 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 624 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 624 # number of overall hits +system.cpu.icache.overall_hits::total 624 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 253 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 253 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 253 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 253 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 253 # number of overall misses system.cpu.icache.overall_misses::total 253 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 18863999 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 18863999 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 18863999 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 18863999 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 18863999 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 18863999 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 878 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 878 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 878 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 878 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 878 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 878 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.288155 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.288155 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.288155 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.288155 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.288155 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.288155 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 74561.260870 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 74561.260870 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 74561.260870 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 74561.260870 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 74561.260870 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 74561.260870 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 125 # number of cycles access was blocked +system.cpu.icache.ReadReq_miss_latency::cpu.inst 19081499 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 19081499 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 19081499 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 19081499 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 19081499 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 19081499 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 877 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 877 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 877 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 877 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 877 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 877 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.288483 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.288483 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.288483 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.288483 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.288483 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.288483 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75420.944664 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 75420.944664 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 75420.944664 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 75420.944664 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 75420.944664 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 75420.944664 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 127 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 62.500000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 63.500000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.ReadReq_mshr_hits::cpu.inst 66 # number of ReadReq MSHR hits system.cpu.icache.ReadReq_mshr_hits::total 66 # number of ReadReq MSHR hits @@ -771,43 +771,43 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 187 system.cpu.icache.demand_mshr_misses::total 187 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 187 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 187 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14160499 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 14160499 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14160499 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 14160499 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14160499 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 14160499 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.212984 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.212984 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.212984 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.212984 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.212984 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.212984 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75724.593583 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75724.593583 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75724.593583 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 75724.593583 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75724.593583 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 75724.593583 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 12409500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14560999 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 14560999 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14560999 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 14560999 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14560999 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 14560999 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.213227 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.213227 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.213227 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.213227 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.213227 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.213227 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 77866.304813 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 77866.304813 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 77866.304813 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 77866.304813 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 77866.304813 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 77866.304813 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 12542500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 119.261302 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 135.950101 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 0 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 248 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 272 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 90.557444 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 28.703859 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002764 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.000876 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.003640 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 248 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 205 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 43 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.007568 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_blocks::cpu.inst 90.459206 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 45.490894 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002761 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.001388 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.004149 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 272 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 217 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 55 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.008301 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 2448 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 2448 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 12409500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 12542500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.ReadExReq_misses::cpu.data 24 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 24 # number of ReadExReq misses system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 187 # number of ReadCleanReq misses @@ -820,18 +820,18 @@ system.cpu.l2cache.demand_misses::total 272 # nu system.cpu.l2cache.overall_misses::cpu.inst 187 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 85 # number of overall misses system.cpu.l2cache.overall_misses::total 272 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1813500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1813500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 13879000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 13879000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 4705500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 4705500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 13879000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 6519000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 20398000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 13879000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 6519000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 20398000 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1837500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1837500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 14279500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 14279500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 4766500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 4766500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 14279500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 6604000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 20883500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 14279500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 6604000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 20883500 # number of overall miss cycles system.cpu.l2cache.ReadExReq_accesses::cpu.data 24 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 24 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 187 # number of ReadCleanReq accesses(hits+misses) @@ -856,18 +856,18 @@ system.cpu.l2cache.demand_miss_rate::total 1 # system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75562.500000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75562.500000 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74219.251337 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74219.251337 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 77139.344262 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 77139.344262 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74219.251337 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76694.117647 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 74992.647059 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74219.251337 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76694.117647 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 74992.647059 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76562.500000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76562.500000 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76360.962567 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76360.962567 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 78139.344262 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 78139.344262 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76360.962567 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77694.117647 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 76777.573529 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76360.962567 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77694.117647 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 76777.573529 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -886,18 +886,18 @@ system.cpu.l2cache.demand_mshr_misses::total 272 system.cpu.l2cache.overall_mshr_misses::cpu.inst 187 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 272 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1573500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1573500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 12009000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 12009000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4095500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4095500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12009000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5669000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 17678000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12009000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5669000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 17678000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1597500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1597500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 12409500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 12409500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4156500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4156500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12409500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5754000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 18163500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12409500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5754000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 18163500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses @@ -910,25 +910,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 1 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65562.500000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65562.500000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64219.251337 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64219.251337 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 67139.344262 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 67139.344262 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64219.251337 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66694.117647 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64992.647059 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64219.251337 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66694.117647 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64992.647059 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66562.500000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66562.500000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66360.962567 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66360.962567 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 68139.344262 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 68139.344262 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66360.962567 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67694.117647 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66777.573529 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66360.962567 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67694.117647 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66777.573529 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 272 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 12409500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 12542500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 248 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 24 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 24 # Transaction distribution @@ -956,10 +956,16 @@ system.cpu.toL2Bus.snoop_fanout::total 272 # Re system.cpu.toL2Bus.reqLayer0.occupancy 136000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 280500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.3 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.utilization 2.2 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 127500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 12409500 # Cumulative time (in ticks) in various power states +system.membus.snoop_filter.tot_requests 272 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 12542500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 248 # Transaction distribution system.membus.trans_dist::ReadExReq 24 # Transaction distribution system.membus.trans_dist::ReadExResp 24 # Transaction distribution @@ -980,9 +986,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 272 # Request fanout histogram -system.membus.reqLayer0.occupancy 337000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 337500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.7 # Layer utilization (%) system.membus.respLayer1.occupancy 1440000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 11.6 # Layer utilization (%) +system.membus.respLayer1.utilization 11.5 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/stats.txt index a36aefa9a..74510a8b2 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000001 # Nu sim_ticks 1297500 # Number of ticks simulated final_tick 1297500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 290379 # Simulator instruction rate (inst/s) -host_op_rate 289620 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 145475657 # Simulator tick rate (ticks/s) -host_mem_usage 238224 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host +host_inst_rate 120967 # Simulator instruction rate (inst/s) +host_op_rate 120887 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 60829891 # Simulator tick rate (ticks/s) +host_mem_usage 241828 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -130,6 +130,12 @@ system.cpu.op_class::MemWrite 298 11.53% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 2585 # Class of executed instruction +system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.pwrStateResidencyTicks::UNDEFINED 1297500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 3000 # Transaction distribution system.membus.trans_dist::ReadResp 3000 # Transaction distribution @@ -144,14 +150,14 @@ system.membus.pkt_size::total 15414 # Cu system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) system.membus.snoop_fanout::samples 3294 # Request fanout histogram -system.membus.snoop_fanout::mean 0.784760 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.411051 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 709 21.52% 21.52% # Request fanout histogram -system.membus.snoop_fanout::1 2585 78.48% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 3294 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 3294 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt index c5f7031d7..f7ca8186a 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000018 # Number of seconds simulated -sim_ticks 18239500 # Number of ticks simulated -final_tick 18239500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 18484500 # Number of ticks simulated +final_tick 18484500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 190443 # Simulator instruction rate (inst/s) -host_op_rate 190287 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1345802218 # Simulator tick rate (ticks/s) -host_mem_usage 247188 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host +host_inst_rate 121029 # Simulator instruction rate (inst/s) +host_op_rate 120936 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 866943608 # Simulator tick rate (ticks/s) +host_mem_usage 250796 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 18239500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 18484500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 10432 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 5248 # Number of bytes read from this memory system.physmem.bytes_read::total 15680 # Number of bytes read from this memory @@ -22,15 +22,15 @@ system.physmem.bytes_inst_read::total 10432 # Nu system.physmem.num_reads::cpu.inst 163 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 82 # Number of read requests responded to by this memory system.physmem.num_reads::total 245 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 571945503 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 287727186 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 859672688 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 571945503 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 571945503 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 571945503 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 287727186 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 859672688 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 18239500 # Cumulative time (in ticks) in various power states +system.physmem.bw_read::cpu.inst 564364738 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 283913549 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 848278287 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 564364738 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 564364738 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 564364738 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 283913549 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 848278287 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 18484500 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses @@ -65,8 +65,8 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 18239500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 36479 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 18484500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 36969 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 2577 # Number of instructions committed @@ -85,7 +85,7 @@ system.cpu.num_mem_refs 717 # nu system.cpu.num_load_insts 419 # Number of load instructions system.cpu.num_store_insts 298 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 36479 # Number of busy cycles +system.cpu.num_busy_cycles 36969 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 396 # Number of branches fetched @@ -124,23 +124,23 @@ system.cpu.op_class::MemWrite 298 11.53% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 2585 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 18239500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 18484500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 47.277997 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 47.258408 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 627 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 82 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 7.646341 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 47.277997 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.011542 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.011542 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 47.258408 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.011538 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.011538 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 82 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 33 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 49 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.020020 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 1500 # Number of tag accesses system.cpu.dcache.tags.data_accesses 1500 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 18239500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 18484500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 360 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 360 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 267 # number of WriteReq hits @@ -157,14 +157,14 @@ system.cpu.dcache.demand_misses::cpu.data 82 # n system.cpu.dcache.demand_misses::total 82 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 82 # number of overall misses system.cpu.dcache.overall_misses::total 82 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 3410000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 3410000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 1674000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 1674000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 5084000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 5084000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 5084000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 5084000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 3465000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 3465000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 1701000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 1701000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 5166000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 5166000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 5166000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 5166000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 415 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 415 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 294 # number of WriteReq accesses(hits+misses) @@ -181,14 +181,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.115656 system.cpu.dcache.demand_miss_rate::total 0.115656 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.115656 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.115656 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62000 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 62000 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 62000 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 62000 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 62000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 62000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 62000 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 63000 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 63000 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 63000 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 63000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 63000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 63000 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -203,14 +203,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 82 system.cpu.dcache.demand_mshr_misses::total 82 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 82 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 82 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3355000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3355000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1647000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1647000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5002000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 5002000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5002000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 5002000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3410000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3410000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1674000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1674000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5084000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 5084000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5084000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 5084000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.132530 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.132530 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.091837 # mshr miss rate for WriteReq accesses @@ -219,31 +219,31 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.115656 system.cpu.dcache.demand_mshr_miss_rate::total 0.115656 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.115656 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.115656 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61000 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61000 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 18239500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 62000 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 62000 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62000 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 62000 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 62000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 62000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 62000 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 18484500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 79.677134 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 79.631047 # Cycle average of tags in use system.cpu.icache.tags.total_refs 2423 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 163 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 14.865031 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 79.677134 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.038905 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.038905 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 79.631047 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.038882 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.038882 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 163 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 94 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 69 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 92 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 71 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.079590 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 5335 # Number of tag accesses system.cpu.icache.tags.data_accesses 5335 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 18239500 # Cumulative time (in ticks) in various power states +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 18484500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 2423 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 2423 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 2423 # number of demand (read+write) hits @@ -256,12 +256,12 @@ system.cpu.icache.demand_misses::cpu.inst 163 # n system.cpu.icache.demand_misses::total 163 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 163 # number of overall misses system.cpu.icache.overall_misses::total 163 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 10106500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 10106500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 10106500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 10106500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 10106500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 10106500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 10269500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 10269500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 10269500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 10269500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 10269500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 10269500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 2586 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 2586 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 2586 # number of demand (read+write) accesses @@ -274,12 +274,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.063032 system.cpu.icache.demand_miss_rate::total 0.063032 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.063032 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.063032 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62003.067485 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 62003.067485 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 62003.067485 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 62003.067485 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 62003.067485 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 62003.067485 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 63003.067485 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 63003.067485 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 63003.067485 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 63003.067485 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 63003.067485 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 63003.067485 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -292,43 +292,43 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 163 system.cpu.icache.demand_mshr_misses::total 163 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 163 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 163 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9943500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 9943500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9943500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 9943500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9943500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 9943500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10106500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 10106500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10106500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 10106500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10106500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 10106500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.063032 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.063032 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.063032 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.063032 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.063032 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.063032 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61003.067485 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61003.067485 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61003.067485 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 61003.067485 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61003.067485 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 61003.067485 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 18239500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 62003.067485 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 62003.067485 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 62003.067485 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 62003.067485 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 62003.067485 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 62003.067485 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 18484500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 106.649585 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 127.028625 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 0 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 218 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 245 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 79.770969 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 26.878617 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002434 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.000820 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.003255 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 218 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 124 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 94 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.006653 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_blocks::cpu.inst 79.723638 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 47.304987 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002433 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.001444 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.003877 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 245 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 125 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 120 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.007477 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 2205 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 2205 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 18239500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 18484500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.ReadExReq_misses::cpu.data 27 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 27 # number of ReadExReq misses system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 163 # number of ReadCleanReq misses @@ -341,18 +341,18 @@ system.cpu.l2cache.demand_misses::total 245 # nu system.cpu.l2cache.overall_misses::cpu.inst 163 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 82 # number of overall misses system.cpu.l2cache.overall_misses::total 245 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1606500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1606500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 9699000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 9699000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 3272500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 3272500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 9699000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 4879000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 14578000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 9699000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 4879000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 14578000 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1633500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1633500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 9862000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 9862000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 3327500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 3327500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 9862000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 4961000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 14823000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 9862000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 4961000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 14823000 # number of overall miss cycles system.cpu.l2cache.ReadExReq_accesses::cpu.data 27 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 27 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 163 # number of ReadCleanReq accesses(hits+misses) @@ -377,18 +377,18 @@ system.cpu.l2cache.demand_miss_rate::total 1 # system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59503.067485 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59503.067485 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59503.067485 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59500 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 59502.040816 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59503.067485 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 59502.040816 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60503.067485 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60503.067485 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60500 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60500 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60503.067485 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60500 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 60502.040816 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60503.067485 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60500 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 60502.040816 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -407,18 +407,18 @@ system.cpu.l2cache.demand_mshr_misses::total 245 system.cpu.l2cache.overall_mshr_misses::cpu.inst 163 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 82 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 245 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1336500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1336500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 8069000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 8069000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2722500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2722500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 8069000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4059000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 12128000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 8069000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4059000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 12128000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1363500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1363500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 8232000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 8232000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2777500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2777500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 8232000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4141000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 12373000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 8232000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4141000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 12373000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses @@ -431,25 +431,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 1 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49503.067485 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49503.067485 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49503.067485 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49502.040816 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49503.067485 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49502.040816 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50503.067485 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50503.067485 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50503.067485 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50502.040816 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50503.067485 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50502.040816 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 245 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 18239500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 18484500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 218 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 27 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 27 # Transaction distribution @@ -480,7 +480,13 @@ system.cpu.toL2Bus.respLayer0.occupancy 244500 # La system.cpu.toL2Bus.respLayer0.utilization 1.3 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 123000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 18239500 # Cumulative time (in ticks) in various power states +system.membus.snoop_filter.tot_requests 245 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 18484500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 218 # Transaction distribution system.membus.trans_dist::ReadExReq 27 # Transaction distribution system.membus.trans_dist::ReadExResp 27 # Transaction distribution @@ -504,6 +510,6 @@ system.membus.snoop_fanout::total 245 # Re system.membus.reqLayer0.occupancy 245500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.3 # Layer utilization (%) system.membus.respLayer1.occupancy 1225000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 6.7 # Layer utilization (%) +system.membus.respLayer1.utilization 6.6 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt index ebafeb85e..9ca1ab172 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000030 # Number of seconds simulated -sim_ticks 30083500 # Number of ticks simulated -final_tick 30083500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 30404500 # Number of ticks simulated +final_tick 30404500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 80042 # Simulator instruction rate (inst/s) -host_op_rate 93682 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 522670316 # Simulator tick rate (ticks/s) -host_mem_usage 264608 # Number of bytes of host memory used +host_inst_rate 82707 # Simulator instruction rate (inst/s) +host_op_rate 96800 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 545818868 # Simulator tick rate (ticks/s) +host_mem_usage 269760 # Number of bytes of host memory used host_seconds 0.06 # Real time elapsed on the host sim_insts 4605 # Number of instructions simulated sim_ops 5391 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 30083500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 30404500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 19520 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 7424 # Number of bytes read from this memory system.physmem.bytes_read::total 26944 # Number of bytes read from this memory @@ -22,14 +22,14 @@ system.physmem.bytes_inst_read::total 19520 # Nu system.physmem.num_reads::cpu.inst 305 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 116 # Number of read requests responded to by this memory system.physmem.num_reads::total 421 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 648860671 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 246779796 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 895640467 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 648860671 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 648860671 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 648860671 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 246779796 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 895640467 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 642010229 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 244174382 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 886184611 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 642010229 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 642010229 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 642010229 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 244174382 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 886184611 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 421 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 421 # Number of DRAM read bursts, including those serviced by the write queue @@ -76,7 +76,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 29992500 # Total gap between requests +system.physmem.totGap 30312500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -187,71 +187,71 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 62 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 408.774194 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 287.809352 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 328.256468 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 8 12.90% 12.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 17 27.42% 40.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 12 19.35% 59.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 6 9.68% 69.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 3 4.84% 74.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 3 4.84% 79.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 3 4.84% 83.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1 1.61% 85.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 9 14.52% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 62 # Bytes accessed per row activation -system.physmem.totQLat 2221000 # Total ticks spent queuing -system.physmem.totMemAccLat 10114750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 63 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 402.285714 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 286.546821 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 324.800854 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 7 11.11% 11.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 19 30.16% 41.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 13 20.63% 61.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 6 9.52% 71.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2 3.17% 74.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 3 4.76% 79.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 3 4.76% 84.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1 1.59% 85.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 9 14.29% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 63 # Bytes accessed per row activation +system.physmem.totQLat 2201250 # Total ticks spent queuing +system.physmem.totMemAccLat 10095000 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2105000 # Total ticks spent in databus transfers -system.physmem.avgQLat 5275.53 # Average queueing delay per DRAM burst +system.physmem.avgQLat 5228.62 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 24025.53 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 895.64 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 23978.62 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 886.18 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 895.64 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 886.18 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 7.00 # Data bus utilization in percentage -system.physmem.busUtilRead 7.00 # Data bus utilization in percentage for reads +system.physmem.busUtil 6.92 # Data bus utilization in percentage +system.physmem.busUtilRead 6.92 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.22 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 350 # Number of row buffer hits during reads +system.physmem.readRowHits 349 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.14 # Row buffer hit rate for reads +system.physmem.readRowHitRate 82.90 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 71241.09 # Average gap between requests -system.physmem.pageHitRate 83.14 # Row buffer hit rate, read and write combined +system.physmem.avgGap 72001.19 # Average gap between requests +system.physmem.pageHitRate 82.90 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 272160 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 148500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1965600 # Energy for read commands per rank (pJ) +system.physmem_0.readEnergy 1942200 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 16103925 # Energy for active background per rank (pJ) +system.physmem_0.actBackEnergy 16099650 # Energy for active background per rank (pJ) system.physmem_0.preBackEnergy 48750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 20064615 # Total energy per rank (pJ) -system.physmem_0.averagePower 849.295873 # Core power per rank (mW) +system.physmem_0.totalEnergy 20036940 # Total energy per rank (pJ) +system.physmem_0.averagePower 848.348875 # Core power per rank (mW) system.physmem_0.memoryStateTime::IDLE 12000 # Time in different power states system.physmem_0.memoryStateTime::REF 780000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 22845750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 22840500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.physmem_1.actEnergy 128520 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 70125 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 694200 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 15554160 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 527250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 18499935 # Total energy per rank (pJ) -system.physmem_1.averagePower 783.273247 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2015750 # Time in different power states +system.physmem_1.actBackEnergy 15442155 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 625500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 18486180 # Total energy per rank (pJ) +system.physmem_1.averagePower 782.690871 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2431750 # Time in different power states system.physmem_1.memoryStateTime::REF 780000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 22043250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 21880250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 30083500 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 30404500 # Cumulative time (in ticks) in various power states system.cpu.branchPred.lookups 1968 # Number of BP lookups system.cpu.branchPred.condPredicted 1178 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 351 # Number of conditional branches incorrect @@ -266,7 +266,7 @@ system.cpu.branchPred.indirectHits 8 # Nu system.cpu.branchPred.indirectMisses 127 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 62 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 30083500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 30404500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -296,7 +296,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 30083500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 30404500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -326,7 +326,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 30083500 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 30404500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -356,7 +356,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 30083500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 30404500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -387,16 +387,16 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 30083500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 60167 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 30404500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 60809 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 4605 # Number of instructions committed system.cpu.committedOps 5391 # Number of ops (including micro ops) committed system.cpu.discardedOps 1193 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 13.065581 # CPI: cycles per instruction -system.cpu.ipc 0.076537 # IPC: instructions per cycle +system.cpu.cpi 13.204995 # CPI: cycles per instruction +system.cpu.ipc 0.075729 # IPC: instructions per cycle system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction system.cpu.op_class_0::IntAlu 3419 63.42% 63.42% # Class of committed instruction system.cpu.op_class_0::IntMult 4 0.07% 63.49% # Class of committed instruction @@ -432,25 +432,25 @@ system.cpu.op_class_0::MemWrite 938 17.40% 100.00% # Cl system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 5391 # Class of committed instruction -system.cpu.tickCycles 10719 # Number of cycles that the object actually ticked -system.cpu.idleCycles 49448 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 30083500 # Cumulative time (in ticks) in various power states +system.cpu.tickCycles 10721 # Number of cycles that the object actually ticked +system.cpu.idleCycles 50088 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 30404500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 86.478936 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 86.589882 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1918 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 13.136986 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 86.478936 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.021113 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.021113 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 86.589882 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.021140 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.021140 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 108 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 36 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 110 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.035645 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 4334 # Number of tag accesses system.cpu.dcache.tags.data_accesses 4334 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 30083500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 30404500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 1050 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1050 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 846 # number of WriteReq hits @@ -471,14 +471,14 @@ system.cpu.dcache.demand_misses::cpu.data 176 # n system.cpu.dcache.demand_misses::total 176 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 176 # number of overall misses system.cpu.dcache.overall_misses::total 176 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 6690500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 6690500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 5002500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 5002500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 11693000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 11693000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 11693000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 11693000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 6774500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 6774500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 5069500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 5069500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 11844000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 11844000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 11844000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 11844000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1159 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1159 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) @@ -499,14 +499,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.084942 system.cpu.dcache.demand_miss_rate::total 0.084942 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.084942 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.084942 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 61380.733945 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 61380.733945 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 74664.179104 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 74664.179104 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 66437.500000 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 66437.500000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 66437.500000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 66437.500000 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62151.376147 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 62151.376147 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 75664.179104 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 75664.179104 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 67295.454545 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 67295.454545 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 67295.454545 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 67295.454545 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -529,14 +529,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 146 system.cpu.dcache.demand_mshr_misses::total 146 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 146 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 146 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6338000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6338000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3188000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3188000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9526000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 9526000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9526000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 9526000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6419000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6419000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3231000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3231000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9650000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9650000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9650000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 9650000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.088870 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.088870 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047097 # mshr miss rate for WriteReq accesses @@ -545,31 +545,31 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.070463 system.cpu.dcache.demand_mshr_miss_rate::total 0.070463 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.070463 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.070463 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61533.980583 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61533.980583 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74139.534884 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74139.534884 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 65246.575342 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 65246.575342 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 65246.575342 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 65246.575342 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 30083500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 62320.388350 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 62320.388350 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75139.534884 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75139.534884 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66095.890411 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 66095.890411 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66095.890411 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 66095.890411 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 30404500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 4 # number of replacements -system.cpu.icache.tags.tagsinuse 161.834516 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 162.072741 # Cycle average of tags in use system.cpu.icache.tags.total_refs 1963 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 322 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 6.096273 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 161.834516 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.079021 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.079021 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 162.072741 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.079137 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.079137 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 318 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 106 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 212 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 103 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 215 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.155273 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 4892 # Number of tag accesses system.cpu.icache.tags.data_accesses 4892 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 30083500 # Cumulative time (in ticks) in various power states +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 30404500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 1963 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 1963 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 1963 # number of demand (read+write) hits @@ -582,12 +582,12 @@ system.cpu.icache.demand_misses::cpu.inst 322 # n system.cpu.icache.demand_misses::total 322 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 322 # number of overall misses system.cpu.icache.overall_misses::total 322 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 23678000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 23678000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 23678000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 23678000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 23678000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 23678000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 23964000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 23964000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 23964000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 23964000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 23964000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 23964000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 2285 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 2285 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 2285 # number of demand (read+write) accesses @@ -600,12 +600,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.140919 system.cpu.icache.demand_miss_rate::total 0.140919 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.140919 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.140919 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 73534.161491 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 73534.161491 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 73534.161491 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 73534.161491 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 73534.161491 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 73534.161491 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 74422.360248 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 74422.360248 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 74422.360248 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 74422.360248 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 74422.360248 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 74422.360248 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -620,43 +620,43 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 322 system.cpu.icache.demand_mshr_misses::total 322 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 322 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 322 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23356000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 23356000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23356000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 23356000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23356000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 23356000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23642000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 23642000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23642000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 23642000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23642000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 23642000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.140919 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.140919 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.140919 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.140919 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.140919 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.140919 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72534.161491 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72534.161491 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72534.161491 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 72534.161491 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72534.161491 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 72534.161491 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 30083500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 73422.360248 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 73422.360248 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 73422.360248 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 73422.360248 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 73422.360248 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 73422.360248 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 30404500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 195.879475 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 223.657376 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 42 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 378 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.111111 # Average number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 421 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.099762 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 154.746810 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 41.132665 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004722 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.001255 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.005978 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 378 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 124 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 254 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.011536 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_blocks::cpu.inst 154.975765 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 68.681611 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004729 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.002096 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.006825 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 421 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 125 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 296 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012848 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 4189 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 4189 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 30083500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 30404500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackClean_hits::writebacks 3 # number of WritebackClean hits system.cpu.l2cache.WritebackClean_hits::total 3 # number of WritebackClean hits system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 17 # number of ReadCleanReq hits @@ -681,18 +681,18 @@ system.cpu.l2cache.demand_misses::total 429 # nu system.cpu.l2cache.overall_misses::cpu.inst 305 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 124 # number of overall misses system.cpu.l2cache.overall_misses::total 429 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3123500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 3123500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 22677500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 22677500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 5924000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 5924000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 22677500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 9047500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 31725000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 22677500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 9047500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 31725000 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3166500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 3166500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 22963500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 22963500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 6005000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 6005000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 22963500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 9171500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 32135000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 22963500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 9171500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 32135000 # number of overall miss cycles system.cpu.l2cache.WritebackClean_accesses::writebacks 3 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::total 3 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 43 # number of ReadExReq accesses(hits+misses) @@ -719,18 +719,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.916667 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.947205 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.849315 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.916667 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72639.534884 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72639.534884 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74352.459016 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74352.459016 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 73135.802469 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 73135.802469 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74352.459016 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72963.709677 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 73951.048951 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74352.459016 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72963.709677 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 73951.048951 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73639.534884 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73639.534884 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75290.163934 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75290.163934 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 74135.802469 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 74135.802469 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75290.163934 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73963.709677 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 74906.759907 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75290.163934 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73963.709677 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 74906.759907 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -755,18 +755,18 @@ system.cpu.l2cache.demand_mshr_misses::total 421 system.cpu.l2cache.overall_mshr_misses::cpu.inst 305 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 116 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 421 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2693500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2693500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 19627500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 19627500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4648000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4648000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19627500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7341500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 26969000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19627500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7341500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 26969000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2736500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2736500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 19913500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 19913500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4721000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4721000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19913500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7457500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 27371000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19913500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7457500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 27371000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.947205 # mshr miss rate for ReadCleanReq accesses @@ -779,25 +779,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.899573 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.947205 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.794521 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.899573 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62639.534884 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62639.534884 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64352.459016 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64352.459016 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 63671.232877 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 63671.232877 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64352.459016 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63288.793103 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64059.382423 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64352.459016 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63288.793103 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64059.382423 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63639.534884 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63639.534884 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65290.163934 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65290.163934 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 64671.232877 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 64671.232877 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65290.163934 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64288.793103 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65014.251781 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65290.163934 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64288.793103 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65014.251781 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 472 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 50 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 30083500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 30404500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 425 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 4 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 43 # Transaction distribution @@ -829,7 +829,13 @@ system.cpu.toL2Bus.respLayer0.occupancy 483000 # La system.cpu.toL2Bus.respLayer0.utilization 1.6 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 222992 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 30083500 # Cumulative time (in ticks) in various power states +system.membus.snoop_filter.tot_requests 421 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 30404500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 378 # Transaction distribution system.membus.trans_dist::ReadExReq 43 # Transaction distribution system.membus.trans_dist::ReadExResp 43 # Transaction distribution @@ -852,7 +858,7 @@ system.membus.snoop_fanout::max_value 0 # Re system.membus.snoop_fanout::total 421 # Request fanout histogram system.membus.reqLayer0.occupancy 490000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.6 # Layer utilization (%) -system.membus.respLayer1.occupancy 2237750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2238500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 7.4 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt index 117199ea9..012901358 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000017 # Number of seconds simulated -sim_ticks 17232500 # Number of ticks simulated -final_tick 17232500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 17458500 # Number of ticks simulated +final_tick 17458500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 74373 # Simulator instruction rate (inst/s) -host_op_rate 87086 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 279001739 # Simulator tick rate (ticks/s) -host_mem_usage 265896 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host +host_inst_rate 52261 # Simulator instruction rate (inst/s) +host_op_rate 61197 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 198636102 # Simulator tick rate (ticks/s) +host_mem_usage 269760 # Number of bytes of host memory used +host_seconds 0.09 # Real time elapsed on the host sim_insts 4592 # Number of instructions simulated sim_ops 5378 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 17458500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 17664 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 7744 # Number of bytes read from this memory system.physmem.bytes_read::total 25408 # Number of bytes read from this memory @@ -22,14 +22,14 @@ system.physmem.bytes_inst_read::total 17664 # Nu system.physmem.num_reads::cpu.inst 276 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 121 # Number of read requests responded to by this memory system.physmem.num_reads::total 397 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1025039896 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 449383432 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1474423328 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1025039896 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1025039896 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1025039896 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 449383432 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1474423328 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1011770771 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 443566171 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1455336942 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1011770771 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1011770771 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1011770771 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 443566171 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1455336942 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 397 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 397 # Number of DRAM read bursts, including those serviced by the write queue @@ -76,7 +76,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 17147000 # Total gap between requests +system.physmem.totGap 17373000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -91,10 +91,10 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 207 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 120 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 52 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 15 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 209 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 119 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 50 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 16 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -187,78 +187,78 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 63 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 391.111111 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 256.618090 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 341.397843 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 13 20.63% 20.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 18 28.57% 49.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 7 11.11% 60.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 6 9.52% 69.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 4 6.35% 76.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2 3.17% 79.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 2 3.17% 82.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2 3.17% 85.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 9 14.29% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 63 # Bytes accessed per row activation -system.physmem.totQLat 3287250 # Total ticks spent queuing -system.physmem.totMemAccLat 10731000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 61 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 398.688525 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 264.215339 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 341.944807 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 12 19.67% 19.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 15 24.59% 44.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 9 14.75% 59.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 7 11.48% 70.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 3 4.92% 75.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2 3.28% 78.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 2 3.28% 81.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2 3.28% 85.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 9 14.75% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 61 # Bytes accessed per row activation +system.physmem.totQLat 3455750 # Total ticks spent queuing +system.physmem.totMemAccLat 10899500 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 1985000 # Total ticks spent in databus transfers -system.physmem.avgQLat 8280.23 # Average queueing delay per DRAM burst +system.physmem.avgQLat 8704.66 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 27030.23 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1474.42 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 27454.66 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1455.34 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1474.42 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1455.34 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 11.52 # Data bus utilization in percentage -system.physmem.busUtilRead 11.52 # Data bus utilization in percentage for reads +system.physmem.busUtil 11.37 # Data bus utilization in percentage +system.physmem.busUtilRead 11.37 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.85 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.88 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 331 # Number of row buffer hits during reads +system.physmem.readRowHits 330 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.38 # Row buffer hit rate for reads +system.physmem.readRowHitRate 83.12 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 43191.44 # Average gap between requests -system.physmem.pageHitRate 83.38 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 309960 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 169125 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 2090400 # Energy for read commands per rank (pJ) +system.physmem.avgGap 43760.71 # Average gap between requests +system.physmem.pageHitRate 83.12 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 294840 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 160875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 2051400 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) system.physmem_0.actBackEnergy 10792665 # Energy for active background per rank (pJ) system.physmem_0.preBackEnergy 32250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 14411520 # Total energy per rank (pJ) -system.physmem_0.averagePower 910.249171 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 69250 # Time in different power states +system.physmem_0.totalEnergy 14349150 # Total energy per rank (pJ) +system.physmem_0.averagePower 906.309806 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 11500 # Time in different power states system.physmem_0.memoryStateTime::REF 520000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 16107250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 15314750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 151200 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 82500 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 764400 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 143640 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 78375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 748800 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 10407915 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 369750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 12792885 # Total energy per rank (pJ) -system.physmem_1.averagePower 808.014211 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 741250 # Time in different power states +system.physmem_1.actBackEnergy 10299330 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 466500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 12753765 # Total energy per rank (pJ) +system.physmem_1.averagePower 805.416167 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 734500 # Time in different power states system.physmem_1.memoryStateTime::REF 520000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 14752750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 14593500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 2837 # Number of BP lookups +system.pwrStateResidencyTicks::UNDEFINED 17458500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 2836 # Number of BP lookups system.cpu.branchPred.condPredicted 1744 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 464 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 2401 # Number of BTB lookups -system.cpu.branchPred.BTBHits 865 # Number of BTB hits +system.cpu.branchPred.BTBLookups 2400 # Number of BTB lookups +system.cpu.branchPred.BTBHits 864 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 36.026656 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 36.000000 # BTB Hit Percentage system.cpu.branchPred.usedRAS 314 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 70 # Number of incorrect RAS predictions. system.cpu.branchPred.indirectLookups 265 # Number of indirect predictor lookups. @@ -266,7 +266,7 @@ system.cpu.branchPred.indirectHits 14 # Nu system.cpu.branchPred.indirectMisses 251 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 63 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.checker.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states +system.cpu.checker.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 17458500 # Cumulative time (in ticks) in various power states system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -296,7 +296,7 @@ system.cpu.checker.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.checker.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.checker.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.checker.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.checker.dtb.walker.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states +system.cpu.checker.dtb.walker.pwrStateResidencyTicks::UNDEFINED 17458500 # Cumulative time (in ticks) in various power states system.cpu.checker.dtb.walker.walks 0 # Table walker walks requested system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -326,7 +326,7 @@ system.cpu.checker.dtb.inst_accesses 0 # IT system.cpu.checker.dtb.hits 0 # DTB hits system.cpu.checker.dtb.misses 0 # DTB misses system.cpu.checker.dtb.accesses 0 # DTB accesses -system.cpu.checker.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states +system.cpu.checker.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 17458500 # Cumulative time (in ticks) in various power states system.cpu.checker.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -356,7 +356,7 @@ system.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.checker.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.checker.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.checker.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.checker.itb.walker.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states +system.cpu.checker.itb.walker.pwrStateResidencyTicks::UNDEFINED 17458500 # Cumulative time (in ticks) in various power states system.cpu.checker.itb.walker.walks 0 # Table walker walks requested system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -387,11 +387,11 @@ system.cpu.checker.itb.hits 0 # DT system.cpu.checker.itb.misses 0 # DTB misses system.cpu.checker.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls -system.cpu.checker.pwrStateResidencyTicks::ON 17232500 # Cumulative time (in ticks) in various power states +system.cpu.checker.pwrStateResidencyTicks::ON 17458500 # Cumulative time (in ticks) in various power states system.cpu.checker.numCycles 5391 # number of cpu cycles simulated system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 17458500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -421,7 +421,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 17458500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -451,7 +451,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 17458500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -481,7 +481,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 17458500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -511,66 +511,66 @@ system.cpu.itb.inst_accesses 0 # IT system.cpu.itb.hits 0 # DTB hits system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses -system.cpu.pwrStateResidencyTicks::ON 17232500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 34466 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 17458500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 34918 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 7588 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 12295 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2837 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 1193 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 4873 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.icacheStallCycles 7601 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 12293 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2836 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 1192 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 4902 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 977 # Number of cycles fetch has spent squashing system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 246 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingTrapStallCycles 248 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 17 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 1961 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 284 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 13213 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.120412 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.482171 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 1960 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 282 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 13257 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.116542 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.478893 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 10520 79.62% 79.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 264 2.00% 81.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 185 1.40% 83.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 203 1.54% 84.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 282 2.13% 86.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 396 3.00% 89.68% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 139 1.05% 90.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 173 1.31% 92.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1051 7.95% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 10565 79.69% 79.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 264 1.99% 81.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 184 1.39% 83.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 203 1.53% 84.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 282 2.13% 86.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 396 2.99% 89.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 139 1.05% 90.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 173 1.30% 92.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1051 7.93% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 13213 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.082313 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.356728 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 6291 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 4311 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2142 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 135 # Number of cycles decode is unblocking +system.cpu.fetch.rateDist::total 13257 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.081219 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.352053 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 6292 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 4354 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2143 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 134 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 334 # Number of cycles decode is squashing system.cpu.decode.BranchResolved 431 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 160 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 12135 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 12137 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 489 # Number of squashed instructions handled by decode system.cpu.rename.SquashCycles 334 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 6519 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 770 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 2303 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2037 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 1250 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 11429 # Number of instructions processed by rename +system.cpu.rename.IdleCycles 6521 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 773 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 2325 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2036 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 1268 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 11426 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 4 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 166 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 130 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 1074 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 11638 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 52321 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 12347 # Number of integer rename lookups +system.cpu.rename.IQFullEvents 168 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 132 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 1090 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 11634 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 52309 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 12345 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 199 # Number of floating rename lookups system.cpu.rename.CommittedMaps 5494 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 6144 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 6140 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 40 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 34 # count of temporary serializing insts renamed system.cpu.rename.skidInsts 441 # count of insts added to the skid buffer @@ -578,109 +578,109 @@ system.cpu.memDep0.insertedLoads 2200 # Nu system.cpu.memDep0.insertedStores 1540 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 32 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 22 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 10167 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 10163 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 43 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 8103 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 38 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 4832 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 12329 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 8100 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 40 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 4828 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 12342 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 6 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 13213 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.613260 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.341984 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 13257 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.610998 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.340069 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 9987 75.58% 75.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1172 8.87% 84.45% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 771 5.84% 90.29% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 475 3.59% 93.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 345 2.61% 96.50% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 273 2.07% 98.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 121 0.92% 99.48% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 10033 75.68% 75.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1170 8.83% 84.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 770 5.81% 90.31% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 479 3.61% 93.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 341 2.57% 96.50% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 274 2.07% 98.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 121 0.91% 99.48% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 59 0.45% 99.92% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 10 0.08% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 13213 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 13257 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 9 6.21% 6.21% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 6.21% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 6.21% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.21% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.21% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.21% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 6.21% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.21% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 6.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 6.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.21% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 65 44.83% 51.03% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 71 48.97% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 9 6.16% 6.16% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 6.16% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 6.16% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.16% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.16% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.16% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 6.16% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.16% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 6.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 6.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.16% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 65 44.52% 50.68% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 72 49.32% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 5027 62.04% 62.04% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 7 0.09% 62.13% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.13% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.13% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.13% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.13% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.13% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.13% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 62.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.16% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 1882 23.23% 85.39% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1184 14.61% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 5026 62.05% 62.05% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 7 0.09% 62.14% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 62.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.17% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 1881 23.22% 85.40% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1183 14.60% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 8103 # Type of FU issued -system.cpu.iq.rate 0.235101 # Inst issue rate -system.cpu.iq.fu_busy_cnt 145 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.017895 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 29511 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 14929 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 7407 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 8100 # Type of FU issued +system.cpu.iq.rate 0.231972 # Inst issue rate +system.cpu.iq.fu_busy_cnt 146 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.018025 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 29552 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 14921 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 7399 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 91 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 132 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 32 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 8205 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 8203 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 43 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 23 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address @@ -694,10 +694,10 @@ system.cpu.iew.lsq.thread0.rescheduledLoads 31 # system.cpu.iew.lsq.thread0.cacheBlocked 4 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewSquashCycles 334 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 683 # Number of cycles IEW is blocking +system.cpu.iew.iewBlockCycles 684 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 18 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 10219 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 125 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispatchedInsts 10215 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 130 # Number of squashed instructions skipped by dispatch system.cpu.iew.iewDispLoadInsts 2200 # Number of dispatched load instructions system.cpu.iew.iewDispStoreInsts 1540 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 31 # Number of dispatched non-speculative instructions @@ -707,41 +707,41 @@ system.cpu.iew.memOrderViolationEvents 19 # Nu system.cpu.iew.predictedTakenIncorrect 94 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 263 # Number of branches that were predicted not taken incorrectly system.cpu.iew.branchMispredicts 357 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 7814 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 1772 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 289 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 7807 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 1773 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 293 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 9 # number of nop insts executed -system.cpu.iew.exec_refs 2923 # number of memory reference insts executed +system.cpu.iew.exec_refs 2920 # number of memory reference insts executed system.cpu.iew.exec_branches 1492 # Number of branches executed -system.cpu.iew.exec_stores 1151 # Number of stores executed -system.cpu.iew.exec_rate 0.226716 # Inst execution rate -system.cpu.iew.wb_sent 7536 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 7439 # cumulative count of insts written-back -system.cpu.iew.wb_producers 3504 # num instructions producing a value -system.cpu.iew.wb_consumers 6831 # num instructions consuming a value -system.cpu.iew.wb_rate 0.215836 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.512956 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 4840 # The number of squashed insts skipped by commit +system.cpu.iew.exec_stores 1147 # Number of stores executed +system.cpu.iew.exec_rate 0.223581 # Inst execution rate +system.cpu.iew.wb_sent 7528 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 7431 # cumulative count of insts written-back +system.cpu.iew.wb_producers 3502 # num instructions producing a value +system.cpu.iew.wb_consumers 6830 # num instructions consuming a value +system.cpu.iew.wb_rate 0.212813 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.512738 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 4836 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 310 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 12359 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.435148 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.280013 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 12404 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.433570 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.278209 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 10307 83.40% 83.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 885 7.16% 90.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 420 3.40% 93.96% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 217 1.76% 95.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 108 0.87% 96.59% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 219 1.77% 98.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 55 0.45% 98.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 39 0.32% 99.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 10353 83.47% 83.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 884 7.13% 90.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 420 3.39% 93.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 217 1.75% 95.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 107 0.86% 96.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 220 1.77% 98.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 55 0.44% 98.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 39 0.31% 99.12% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::8 109 0.88% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 12359 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 12404 # Number of insts commited each cycle system.cpu.commit.committedInsts 4592 # Number of instructions committed system.cpu.commit.committedOps 5378 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -788,52 +788,52 @@ system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Cl system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 5378 # Class of committed instruction system.cpu.commit.bw_lim_events 109 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 22311 # The number of ROB reads -system.cpu.rob.rob_writes 21303 # The number of ROB writes +system.cpu.rob.rob_reads 22352 # The number of ROB reads +system.cpu.rob.rob_writes 21294 # The number of ROB writes system.cpu.timesIdled 191 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 21253 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 21661 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 4592 # Number of Instructions Simulated system.cpu.committedOps 5378 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 7.505662 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.505662 # CPI: Total CPI of All Threads -system.cpu.ipc 0.133233 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.133233 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 7659 # number of integer regfile reads -system.cpu.int_regfile_writes 4270 # number of integer regfile writes +system.cpu.cpi 7.604094 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.604094 # CPI: Total CPI of All Threads +system.cpu.ipc 0.131508 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.131508 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 7649 # number of integer regfile reads +system.cpu.int_regfile_writes 4266 # number of integer regfile writes system.cpu.fp_regfile_reads 32 # number of floating regfile reads -system.cpu.cc_regfile_reads 27801 # number of cc regfile reads -system.cpu.cc_regfile_writes 3276 # number of cc regfile writes -system.cpu.misc_regfile_reads 2980 # number of misc regfile reads +system.cpu.cc_regfile_reads 27780 # number of cc regfile reads +system.cpu.cc_regfile_writes 3273 # number of cc regfile writes +system.cpu.misc_regfile_reads 2976 # number of misc regfile reads system.cpu.misc_regfile_writes 24 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 17458500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 88.359063 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 2095 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 88.222961 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 2096 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 147 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 14.251701 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 14.258503 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 88.359063 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.021572 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.021572 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 88.222961 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.021539 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.021539 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 147 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 92 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.035889 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 5339 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 5339 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 1477 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1477 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 5341 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 5341 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 17458500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 1478 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1478 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 597 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 597 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 10 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 10 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 2074 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2074 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2074 # number of overall hits -system.cpu.dcache.overall_hits::total 2074 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 2075 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2075 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2075 # number of overall hits +system.cpu.dcache.overall_hits::total 2075 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 183 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 183 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 316 # number of WriteReq misses @@ -844,53 +844,53 @@ system.cpu.dcache.demand_misses::cpu.data 499 # n system.cpu.dcache.demand_misses::total 499 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 499 # number of overall misses system.cpu.dcache.overall_misses::total 499 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 10736000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 10736000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 22555500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 22555500 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 142000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 142000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 33291500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 33291500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 33291500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 33291500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1660 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1660 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_latency::cpu.data 10847000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 10847000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 22859500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 22859500 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 144000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 144000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 33706500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 33706500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 33706500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 33706500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1661 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1661 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 12 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 12 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2573 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2573 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2573 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2573 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.110241 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.110241 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2574 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2574 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2574 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2574 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.110175 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.110175 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.346112 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.346112 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.166667 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.166667 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.193937 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.193937 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.193937 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.193937 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 58666.666667 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 58666.666667 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 71378.164557 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 71378.164557 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 71000 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 71000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 66716.432866 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 66716.432866 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 66716.432866 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 66716.432866 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 145 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.193862 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.193862 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.193862 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.193862 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 59273.224044 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 59273.224044 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 72340.189873 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 72340.189873 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 72000 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 72000 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 67548.096192 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 67548.096192 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 67548.096192 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 67548.096192 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 147 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 48.333333 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 49 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.ReadReq_mshr_hits::cpu.data 78 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 78 # number of ReadReq MSHR hits @@ -910,88 +910,88 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 147 system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7020000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 7020000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3398000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3398000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10418000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10418000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10418000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10418000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.063253 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.063253 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7089000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 7089000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3440000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3440000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10529000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10529000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10529000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10529000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.063215 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.063215 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046002 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046002 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.057132 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.057132 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.057132 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.057132 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 66857.142857 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66857.142857 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80904.761905 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80904.761905 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 70870.748299 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 70870.748299 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 70870.748299 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 70870.748299 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.057110 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.057110 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.057110 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.057110 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 67514.285714 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 67514.285714 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 81904.761905 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 81904.761905 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 71625.850340 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 71625.850340 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 71625.850340 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 71625.850340 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 17458500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 2 # number of replacements -system.cpu.icache.tags.tagsinuse 150.405898 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1577 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 149.958367 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1576 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 294 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 5.363946 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 5.360544 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 150.405898 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.073440 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.073440 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 149.958367 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.073222 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.073222 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 292 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 169 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 123 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 166 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 126 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.142578 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 4216 # Number of tag accesses -system.cpu.icache.tags.data_accesses 4216 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 1577 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1577 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1577 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1577 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1577 # number of overall hits -system.cpu.icache.overall_hits::total 1577 # number of overall hits +system.cpu.icache.tags.tag_accesses 4214 # Number of tag accesses +system.cpu.icache.tags.data_accesses 4214 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 17458500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 1576 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1576 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1576 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1576 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1576 # number of overall hits +system.cpu.icache.overall_hits::total 1576 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 384 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 384 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 384 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 384 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 384 # number of overall misses system.cpu.icache.overall_misses::total 384 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 26669500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 26669500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 26669500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 26669500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 26669500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 26669500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1961 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1961 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1961 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1961 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1961 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1961 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.195818 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.195818 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.195818 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.195818 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.195818 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.195818 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69451.822917 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 69451.822917 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 69451.822917 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 69451.822917 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 69451.822917 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 69451.822917 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 423 # number of cycles access was blocked +system.cpu.icache.ReadReq_miss_latency::cpu.inst 27225000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 27225000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 27225000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 27225000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 27225000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 27225000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1960 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1960 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1960 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1960 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1960 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1960 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.195918 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.195918 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.195918 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.195918 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.195918 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.195918 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70898.437500 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 70898.437500 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 70898.437500 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 70898.437500 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 70898.437500 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 70898.437500 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 433 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 84.600000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 86.600000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.writebacks::writebacks 2 # number of writebacks system.cpu.icache.writebacks::total 2 # number of writebacks @@ -1007,43 +1007,43 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 294 system.cpu.icache.demand_mshr_misses::total 294 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 294 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 294 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 21733500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 21733500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 21733500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 21733500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 21733500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 21733500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.149924 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.149924 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.149924 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.149924 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.149924 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.149924 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 73923.469388 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 73923.469388 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 73923.469388 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 73923.469388 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 73923.469388 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 73923.469388 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22193500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 22193500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22193500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 22193500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22193500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 22193500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.150000 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.150000 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.150000 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.150000 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.150000 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.150000 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75488.095238 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75488.095238 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75488.095238 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 75488.095238 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75488.095238 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 75488.095238 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 17458500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 187.999052 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 215.001500 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 39 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 355 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.109859 # Average number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 397 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.098237 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 141.158865 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 46.840188 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004308 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.001429 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.005737 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 355 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 193 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 162 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.010834 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_blocks::cpu.inst 140.723037 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 74.278463 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004295 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.002267 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.006561 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 397 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 200 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 197 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012115 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 3933 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 3933 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 17458500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackClean_hits::writebacks 1 # number of WritebackClean hits system.cpu.l2cache.WritebackClean_hits::total 1 # number of WritebackClean hits system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 18 # number of ReadCleanReq hits @@ -1068,18 +1068,18 @@ system.cpu.l2cache.demand_misses::total 403 # nu system.cpu.l2cache.overall_misses::cpu.inst 276 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 127 # number of overall misses system.cpu.l2cache.overall_misses::total 403 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3333000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 3333000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 21084500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 21084500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 6625500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 6625500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 21084500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 9958500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 31043000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 21084500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 9958500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 31043000 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3375000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 3375000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 21544500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 21544500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 6694500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 6694500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 21544500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 10069500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 31614000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 21544500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 10069500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 31614000 # number of overall miss cycles system.cpu.l2cache.WritebackClean_accesses::writebacks 1 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::total 1 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 42 # number of ReadExReq accesses(hits+misses) @@ -1106,18 +1106,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.913832 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.938776 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.863946 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.913832 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79357.142857 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79357.142857 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76393.115942 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76393.115942 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 77947.058824 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 77947.058824 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76393.115942 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78413.385827 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 77029.776675 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76393.115942 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78413.385827 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 77029.776675 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80357.142857 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80357.142857 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 78059.782609 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 78059.782609 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 78758.823529 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 78758.823529 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 78059.782609 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79287.401575 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 78446.650124 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 78059.782609 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79287.401575 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 78446.650124 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1142,18 +1142,18 @@ system.cpu.l2cache.demand_mshr_misses::total 397 system.cpu.l2cache.overall_mshr_misses::cpu.inst 276 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 121 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 397 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2913000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2913000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 18324500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 18324500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5436000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 5436000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18324500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8349000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 26673500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 18324500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8349000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 26673500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2955000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2955000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 18784500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 18784500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5499000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 5499000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18784500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8454000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 27238500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 18784500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8454000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 27238500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.938776 # mshr miss rate for ReadCleanReq accesses @@ -1166,25 +1166,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.900227 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.938776 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.823129 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.900227 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69357.142857 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69357.142857 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66393.115942 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66393.115942 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 68810.126582 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 68810.126582 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66393.115942 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67187.657431 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66393.115942 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67187.657431 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70357.142857 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70357.142857 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 68059.782609 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 68059.782609 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 69607.594937 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 69607.594937 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68059.782609 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69867.768595 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68610.831234 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68059.782609 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69867.768595 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68610.831234 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 443 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 45 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 17458500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 399 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 2 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 42 # Transaction distribution @@ -1213,10 +1213,16 @@ system.cpu.toL2Bus.snoop_fanout::total 441 # Re system.cpu.toL2Bus.reqLayer0.occupancy 223500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 441000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.6 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.utilization 2.5 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 223494 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states +system.membus.snoop_filter.tot_requests 397 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 17458500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 355 # Transaction distribution system.membus.trans_dist::ReadExReq 42 # Transaction distribution system.membus.trans_dist::ReadExResp 42 # Transaction distribution @@ -1239,7 +1245,7 @@ system.membus.snoop_fanout::max_value 0 # Re system.membus.snoop_fanout::total 397 # Request fanout histogram system.membus.reqLayer0.occupancy 488000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 2101750 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 12.2 # Layer utilization (%) +system.membus.respLayer1.occupancy 2102000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 12.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt index 7324072b2..bfd96912f 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt @@ -1,52 +1,52 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000019 # Number of seconds simulated -sim_ticks 18821000 # Number of ticks simulated -final_tick 18821000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 19046000 # Number of ticks simulated +final_tick 19046000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 81076 # Simulator instruction rate (inst/s) -host_op_rate 94934 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 332169191 # Simulator tick rate (ticks/s) -host_mem_usage 262700 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host +host_inst_rate 51970 # Simulator instruction rate (inst/s) +host_op_rate 60857 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 215490046 # Simulator tick rate (ticks/s) +host_mem_usage 266056 # Number of bytes of host memory used +host_seconds 0.09 # Real time elapsed on the host sim_insts 4592 # Number of instructions simulated sim_ops 5378 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 18821000 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 19046000 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 18560 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 8064 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 8192 # Number of bytes read from this memory system.physmem.bytes_read::cpu.l2cache.prefetcher 1728 # Number of bytes read from this memory -system.physmem.bytes_read::total 28352 # Number of bytes read from this memory +system.physmem.bytes_read::total 28480 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 18560 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 18560 # Number of instructions bytes read from this memory system.physmem.num_reads::cpu.inst 290 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 126 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 128 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.l2cache.prefetcher 27 # Number of read requests responded to by this memory -system.physmem.num_reads::total 443 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 986132512 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 428457574 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 91812337 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1506402423 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 986132512 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 986132512 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 986132512 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 428457574 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 91812337 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1506402423 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 443 # Number of read requests accepted +system.physmem.num_reads::total 445 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 974482831 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 430116560 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 90727712 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1495327103 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 974482831 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 974482831 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 974482831 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 430116560 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 90727712 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1495327103 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 445 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 443 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 445 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 28352 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 28480 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 28352 # Total read bytes from the system interface side +system.physmem.bytesReadSys 28480 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 101 # Per bank write bursts +system.physmem.perBankRdBursts::0 103 # Per bank write bursts system.physmem.perBankRdBursts::1 48 # Per bank write bursts system.physmem.perBankRdBursts::2 19 # Per bank write bursts system.physmem.perBankRdBursts::3 45 # Per bank write bursts @@ -80,14 +80,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 18779500 # Total gap between requests +system.physmem.totGap 19004500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 443 # Read request sizes (log2) +system.physmem.readPktSize::6 445 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -96,11 +96,11 @@ system.physmem.writePktSize::4 0 # Wr system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) system.physmem.rdQLenPdf::0 246 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 134 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 34 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 132 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 35 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 15 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 2 # What read queue length does an incoming req see @@ -192,77 +192,77 @@ system.physmem.wrQLenPdf::61 0 # Wh system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see system.physmem.bytesPerActivate::samples 63 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 427.682540 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 292.140083 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 354.445538 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 7 11.11% 11.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 18 28.57% 39.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 429.714286 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 289.613657 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 357.341954 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 8 12.70% 12.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 17 26.98% 39.68% # Bytes accessed per row activation system.physmem.bytesPerActivate::256-383 11 17.46% 57.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 7 11.11% 68.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 1 1.59% 69.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 4 6.35% 76.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1 1.59% 77.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 6 9.52% 66.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 3 4.76% 71.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2 3.17% 74.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 2 3.17% 77.78% # Bytes accessed per row activation system.physmem.bytesPerActivate::896-1023 2 3.17% 80.95% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 12 19.05% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 63 # Bytes accessed per row activation -system.physmem.totQLat 3401243 # Total ticks spent queuing -system.physmem.totMemAccLat 11707493 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2215000 # Total ticks spent in databus transfers -system.physmem.avgQLat 7677.75 # Average queueing delay per DRAM burst +system.physmem.totQLat 4296708 # Total ticks spent queuing +system.physmem.totMemAccLat 12640458 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2225000 # Total ticks spent in databus transfers +system.physmem.avgQLat 9655.52 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26427.75 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1506.40 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 28405.52 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1495.33 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1506.40 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1495.33 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 11.77 # Data bus utilization in percentage -system.physmem.busUtilRead 11.77 # Data bus utilization in percentage for reads +system.physmem.busUtil 11.68 # Data bus utilization in percentage +system.physmem.busUtilRead 11.68 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.80 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.86 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 371 # Number of row buffer hits during reads +system.physmem.readRowHits 373 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.75 # Row buffer hit rate for reads +system.physmem.readRowHitRate 83.82 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 42391.65 # Average gap between requests -system.physmem.pageHitRate 83.75 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 294840 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 160875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 2160600 # Energy for read commands per rank (pJ) +system.physmem.avgGap 42706.74 # Average gap between requests +system.physmem.pageHitRate 83.82 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 287280 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 156750 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 2152800 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 10755900 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 64500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 14453835 # Total energy per rank (pJ) -system.physmem_0.averagePower 912.921838 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 51750 # Time in different power states +system.physmem_0.actBackEnergy 10689210 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 123000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 14426160 # Total energy per rank (pJ) +system.physmem_0.averagePower 911.173851 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 148750 # Time in different power states system.physmem_0.memoryStateTime::REF 520000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 15274500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 15177500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.physmem_1.actEnergy 128520 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 70125 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 811200 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 10734525 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 83250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 12844740 # Total energy per rank (pJ) -system.physmem_1.averagePower 811.289436 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 945250 # Time in different power states +system.physmem_1.actBackEnergy 10733670 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 84000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 12844635 # Total energy per rank (pJ) +system.physmem_1.averagePower 811.282804 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1145250 # Time in different power states system.physmem_1.memoryStateTime::REF 520000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 15229250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 15228250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 18821000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 2438 # Number of BP lookups -system.cpu.branchPred.condPredicted 1442 # Number of conditional branches predicted +system.pwrStateResidencyTicks::UNDEFINED 19046000 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 2439 # Number of BP lookups +system.cpu.branchPred.condPredicted 1443 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 524 # Number of conditional branches incorrect system.cpu.branchPred.BTBLookups 915 # Number of BTB lookups -system.cpu.branchPred.BTBHits 449 # Number of BTB hits +system.cpu.branchPred.BTBHits 448 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 49.071038 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 48.961749 # BTB Hit Percentage system.cpu.branchPred.usedRAS 286 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 57 # Number of incorrect RAS predictions. system.cpu.branchPred.indirectLookups 163 # Number of indirect predictor lookups. @@ -270,7 +270,7 @@ system.cpu.branchPred.indirectHits 13 # Nu system.cpu.branchPred.indirectMisses 150 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 60 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 18821000 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 19046000 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -300,7 +300,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 18821000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 19046000 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -330,7 +330,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 18821000 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 19046000 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -360,7 +360,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 18821000 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 19046000 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -391,85 +391,85 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 18821000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 37643 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 19046000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 38093 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 6083 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 11454 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2438 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 748 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 8291 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.icacheStallCycles 6117 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 11468 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2439 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 747 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 8723 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 1091 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 169 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 272 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 412 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 3904 # Number of cache lines fetched +system.cpu.fetch.MiscStallCycles 171 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 274 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 416 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 3907 # Number of cache lines fetched system.cpu.fetch.IcacheSquashes 178 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 15772 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.863365 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.208800 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::samples 16246 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.839530 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.200509 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 9389 59.53% 59.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2507 15.90% 75.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 518 3.28% 78.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 3358 21.29% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 9855 60.66% 60.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2507 15.43% 76.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 520 3.20% 79.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 3364 20.71% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 15772 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.064766 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.304280 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 5832 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 4243 # Number of cycles decode is blocked +system.cpu.fetch.rateDist::total 16246 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.064028 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.301053 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 5842 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 4705 # Number of cycles decode is blocked system.cpu.decode.RunCycles 5178 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 133 # Number of cycles decode is unblocking +system.cpu.decode.UnblockCycles 135 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 386 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 373 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 161 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 10169 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 1675 # Number of squashed instructions handled by decode +system.cpu.decode.BranchResolved 375 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 162 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 10177 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 1679 # Number of squashed instructions handled by decode system.cpu.rename.SquashCycles 386 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 6945 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 1086 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 2318 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 4187 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 850 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 9093 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 454 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 23 # Number of times rename has blocked due to ROB full +system.cpu.rename.IdleCycles 6957 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 1136 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 2347 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 4188 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 1232 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 9097 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 461 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 24 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 1 # Number of times rename has blocked due to IQ full system.cpu.rename.LQFullEvents 28 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 744 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 9450 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 41121 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 9999 # Number of integer rename lookups +system.cpu.rename.SQFullEvents 1125 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 9457 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 41127 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 9997 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 17 # Number of floating rename lookups system.cpu.rename.CommittedMaps 5494 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 3956 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 3963 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 29 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 27 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 331 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 1823 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1291 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.skidInsts 333 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 1824 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1284 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. system.cpu.iq.iqInstsAdded 8515 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 38 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 7234 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 175 # Number of squashed instructions issued +system.cpu.iq.iqInstsIssued 7229 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 177 # Number of squashed instructions issued system.cpu.iq.iqSquashedInstsExamined 3175 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 8237 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedOperandsExamined 8254 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 1 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 15772 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.458661 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 0.847067 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 16246 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.444971 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 0.838160 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 11502 72.93% 72.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1999 12.67% 85.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 1621 10.28% 95.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 607 3.85% 99.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 43 0.27% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 11980 73.74% 73.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1997 12.29% 86.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 1618 9.96% 95.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 608 3.74% 99.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 43 0.26% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle @@ -477,105 +477,105 @@ system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Nu system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 4 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 15772 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 16246 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 415 28.78% 28.78% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 28.78% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 28.78% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 28.78% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 28.78% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 28.78% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 28.78% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 28.78% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 28.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 28.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 28.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 28.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 28.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 28.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 28.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 28.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 28.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 28.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 28.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 28.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 28.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 28.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 28.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 28.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 28.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 28.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 28.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 28.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 28.78% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 474 32.87% 61.65% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 553 38.35% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 416 28.89% 28.89% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 28.89% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 28.89% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 28.89% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 28.89% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 28.89% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 28.89% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 28.89% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 28.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 28.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 28.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 28.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 28.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 28.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 28.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 28.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 28.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 28.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 28.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 28.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 28.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 28.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 28.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 28.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 28.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 28.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 28.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 28.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 28.89% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 475 32.99% 61.87% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 549 38.12% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 4534 62.68% 62.68% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 5 0.07% 62.75% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.75% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.75% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.75% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.75% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.75% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.75% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 62.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.79% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 1605 22.19% 84.97% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1087 15.03% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 4534 62.72% 62.72% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 5 0.07% 62.79% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.79% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.79% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.79% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.79% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.79% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.79% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 62.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.83% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 1606 22.22% 85.05% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1081 14.95% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 7234 # Type of FU issued -system.cpu.iq.rate 0.192174 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1442 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.199336 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 31813 # Number of integer instruction queue reads +system.cpu.iq.FU_type_0::total 7229 # Type of FU issued +system.cpu.iq.rate 0.189772 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1440 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.199198 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 32277 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 11719 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 6621 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_wakeup_accesses 6614 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 44 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 8648 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 8641 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 28 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 11 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 12 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 796 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 797 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 7 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 353 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 346 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 7 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 18 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewSquashCycles 386 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 336 # Number of cycles IEW is blocking +system.cpu.iew.iewBlockCycles 339 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 11 # Number of cycles IEW is unblocking system.cpu.iew.iewDispatchedInsts 8566 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 1823 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1291 # Number of dispatched store instructions +system.cpu.iew.iewDispLoadInsts 1824 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1284 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 26 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 6 # Number of times the LSQ has become full, causing a stall @@ -583,41 +583,41 @@ system.cpu.iew.memOrderViolationEvents 7 # Nu system.cpu.iew.predictedTakenIncorrect 59 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 319 # Number of branches that were predicted not taken incorrectly system.cpu.iew.branchMispredicts 378 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 6824 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 1421 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 410 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 6820 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 1423 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 409 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 13 # number of nop insts executed -system.cpu.iew.exec_refs 2451 # number of memory reference insts executed -system.cpu.iew.exec_branches 1299 # Number of branches executed -system.cpu.iew.exec_stores 1030 # Number of stores executed -system.cpu.iew.exec_rate 0.181282 # Inst execution rate -system.cpu.iew.wb_sent 6681 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 6637 # cumulative count of insts written-back -system.cpu.iew.wb_producers 2986 # num instructions producing a value -system.cpu.iew.wb_consumers 5424 # num instructions consuming a value -system.cpu.iew.wb_rate 0.176314 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.550516 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 2706 # The number of squashed insts skipped by commit +system.cpu.iew.exec_refs 2448 # number of memory reference insts executed +system.cpu.iew.exec_branches 1296 # Number of branches executed +system.cpu.iew.exec_stores 1025 # Number of stores executed +system.cpu.iew.exec_rate 0.179036 # Inst execution rate +system.cpu.iew.wb_sent 6675 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 6630 # cumulative count of insts written-back +system.cpu.iew.wb_producers 2985 # num instructions producing a value +system.cpu.iew.wb_consumers 5422 # num instructions consuming a value +system.cpu.iew.wb_rate 0.174048 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.550535 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 2710 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 365 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 15204 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.353723 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 0.993092 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 15677 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.343050 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 0.979995 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 12538 82.47% 82.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1405 9.24% 91.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 597 3.93% 95.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 300 1.97% 97.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 170 1.12% 98.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 79 0.52% 99.24% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 44 0.29% 99.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 28 0.18% 99.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 43 0.28% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 13011 82.99% 82.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1405 8.96% 91.96% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 598 3.81% 95.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 299 1.91% 97.68% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 169 1.08% 98.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 80 0.51% 99.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 44 0.28% 99.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 28 0.18% 99.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 43 0.27% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 15204 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 15677 # Number of insts commited each cycle system.cpu.commit.committedInsts 4592 # Number of instructions committed system.cpu.commit.committedOps 5378 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -664,40 +664,40 @@ system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Cl system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 5378 # Class of committed instruction system.cpu.commit.bw_lim_events 43 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 23088 # The number of ROB reads -system.cpu.rob.rob_writes 16743 # The number of ROB writes -system.cpu.timesIdled 215 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 21871 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 23565 # The number of ROB reads +system.cpu.rob.rob_writes 16751 # The number of ROB writes +system.cpu.timesIdled 216 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 21847 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 4592 # Number of Instructions Simulated system.cpu.committedOps 5378 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 8.197517 # CPI: Cycles Per Instruction -system.cpu.cpi_total 8.197517 # CPI: Total CPI of All Threads -system.cpu.ipc 0.121988 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.121988 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 6777 # number of integer regfile reads -system.cpu.int_regfile_writes 3787 # number of integer regfile writes +system.cpu.cpi 8.295514 # CPI: Cycles Per Instruction +system.cpu.cpi_total 8.295514 # CPI: Total CPI of All Threads +system.cpu.ipc 0.120547 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.120547 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 6772 # number of integer regfile reads +system.cpu.int_regfile_writes 3788 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.cc_regfile_reads 24229 # number of cc regfile reads -system.cpu.cc_regfile_writes 2921 # number of cc regfile writes -system.cpu.misc_regfile_reads 2564 # number of misc regfile reads +system.cpu.cc_regfile_reads 24217 # number of cc regfile reads +system.cpu.cc_regfile_writes 2924 # number of cc regfile writes +system.cpu.misc_regfile_reads 2559 # number of misc regfile reads system.cpu.misc_regfile_writes 24 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 18821000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 19046000 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 1 # number of replacements -system.cpu.dcache.tags.tagsinuse 84.368926 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 84.349867 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1930 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 143 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 13.496503 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 84.368926 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.164783 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.164783 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 84.349867 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.164746 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.164746 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 142 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 88 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 89 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.277344 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 4723 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 4723 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 18821000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.tag_accesses 4725 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 4725 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 19046000 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 1188 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1188 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 722 # number of WriteReq hits @@ -710,76 +710,76 @@ system.cpu.dcache.demand_hits::cpu.data 1910 # nu system.cpu.dcache.demand_hits::total 1910 # number of demand (read+write) hits system.cpu.dcache.overall_hits::cpu.data 1910 # number of overall hits system.cpu.dcache.overall_hits::total 1910 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 167 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 167 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::cpu.data 168 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 168 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 191 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 191 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 358 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 358 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 358 # number of overall misses -system.cpu.dcache.overall_misses::total 358 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 10679500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 10679500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 7608000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 7608000 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 125000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 125000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 18287500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 18287500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 18287500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 18287500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1355 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1355 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 359 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 359 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 359 # number of overall misses +system.cpu.dcache.overall_misses::total 359 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 10937500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 10937500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 9601000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 9601000 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 127000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 127000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 20538500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 20538500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 20538500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 20538500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1356 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1356 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2268 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2268 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2268 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2268 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.123247 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.123247 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2269 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2269 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2269 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2269 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.123894 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.123894 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.209200 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.209200 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.181818 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.181818 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.157848 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.157848 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.157848 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.157848 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63949.101796 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 63949.101796 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39832.460733 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 39832.460733 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 62500 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 62500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 51082.402235 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 51082.402235 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 51082.402235 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 51082.402235 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.158219 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.158219 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.158219 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.158219 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 65104.166667 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 65104.166667 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 50267.015707 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 50267.015707 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 63500 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 63500 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 57210.306407 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 57210.306407 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 57210.306407 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 57210.306407 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 818 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 1304 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 18 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 45.444444 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 72.444444 # average number of cycles each access was blocked system.cpu.dcache.writebacks::writebacks 1 # number of writebacks system.cpu.dcache.writebacks::total 1 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 64 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 64 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 65 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 65 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 150 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 150 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 214 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 214 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 214 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 214 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 215 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 215 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 215 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 215 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 103 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 103 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 41 # number of WriteReq MSHR misses @@ -788,189 +788,187 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 144 system.cpu.dcache.demand_mshr_misses::total 144 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 144 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 144 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6934000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6934000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2433000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2433000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9367000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 9367000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9367000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 9367000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076015 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076015 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7149000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 7149000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2700500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2700500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9849500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9849500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9849500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 9849500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075959 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075959 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044907 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044907 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.063492 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.063492 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.063492 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.063492 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 67320.388350 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 67320.388350 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59341.463415 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59341.463415 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 65048.611111 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 65048.611111 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 65048.611111 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 65048.611111 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 18821000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.063464 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.063464 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.063464 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.063464 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 69407.766990 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 69407.766990 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 65865.853659 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 65865.853659 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68399.305556 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 68399.305556 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68399.305556 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 68399.305556 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 19046000 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 44 # number of replacements -system.cpu.icache.tags.tagsinuse 137.890102 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 3540 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 137.872552 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 3542 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 299 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 11.839465 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 11.846154 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 137.890102 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.269317 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.269317 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 137.872552 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.269282 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.269282 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 255 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 157 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 98 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 155 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 100 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.498047 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 8101 # Number of tag accesses -system.cpu.icache.tags.data_accesses 8101 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 18821000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 3540 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 3540 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 3540 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 3540 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 3540 # number of overall hits -system.cpu.icache.overall_hits::total 3540 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 361 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 361 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 361 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 361 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 361 # number of overall misses -system.cpu.icache.overall_misses::total 361 # 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average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 62331.469613 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 62331.469613 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 62331.469613 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 62331.469613 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 62331.469613 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 8558 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 35 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 95 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 88.568421 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 33 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 90.084211 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 35 # average number of cycles each access was blocked system.cpu.icache.writebacks::writebacks 44 # number of writebacks system.cpu.icache.writebacks::total 44 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 62 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 62 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 62 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 62 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 62 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 62 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 63 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 63 # 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number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19775992 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 19775992 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19775992 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 19775992 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.076647 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.076647 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.076647 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.076647 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.076647 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.076647 # 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average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66344.454849 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66344.454849 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 66344.454849 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66344.454849 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 66344.454849 # average overall mshr miss latency +system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 19046000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.prefetcher.num_hwpf_issued 112 # number of hwpf issued system.cpu.l2cache.prefetcher.pfIdentified 112 # number of prefetch candidates identified system.cpu.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue system.cpu.l2cache.prefetcher.pfInCache 0 # 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Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 41 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.073171 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 10.572819 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 9.233490 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.000645 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.000564 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.001209 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1022 16 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 32 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_blocks::writebacks 9.233331 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 8.162055 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.000564 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.000498 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.001062 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1022 13 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 28 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1022::0 8 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::1 8 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 26 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 6 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1022 0.000977 # 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Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackClean_hits::writebacks 33 # number of WritebackClean hits system.cpu.l2cache.WritebackClean_hits::total 33 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 11 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 11 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 10 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 10 # number of ReadExReq hits system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 8 # number of ReadCleanReq hits system.cpu.l2cache.ReadCleanReq_hits::total 8 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 2 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 2 # number of ReadSharedReq hits system.cpu.l2cache.demand_hits::cpu.inst 8 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 13 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 21 # 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number of overall miss cycles +system.cpu.l2cache.overall_misses::cpu.data 134 # number of overall misses +system.cpu.l2cache.overall_misses::total 425 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2572500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 2572500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 19478500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 19478500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 6989500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 6989500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 19478500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 9562000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 29040500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 19478500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 9562000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 29040500 # number of overall miss cycles system.cpu.l2cache.WritebackClean_accesses::writebacks 33 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::total 33 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 41 # number of ReadExReq accesses(hits+misses) @@ -985,116 +983,117 @@ system.cpu.l2cache.demand_accesses::total 443 # n system.cpu.l2cache.overall_accesses::cpu.inst 299 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 144 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 443 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.731707 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.731707 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.756098 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.756098 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.973244 # miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.973244 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.980583 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.980583 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.973244 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.909722 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.952596 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.930556 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.959368 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.973244 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.909722 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.952596 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76633.333333 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76633.333333 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 66726.804124 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 66726.804124 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 66935.643564 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 66935.643564 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66726.804124 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69156.488550 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 67481.042654 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66726.804124 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69156.488550 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 67481.042654 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::cpu.data 0.930556 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.959368 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 82983.870968 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 82983.870968 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 66936.426117 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 66936.426117 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 67859.223301 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 67859.223301 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66936.426117 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71358.208955 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 68330.588235 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66936.426117 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71358.208955 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 68330.588235 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 1 # number of ReadExReq MSHR hits +system.cpu.l2cache.ReadExReq_mshr_hits::total 1 # number of ReadExReq MSHR hits system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 5 # number of ReadSharedReq MSHR hits system.cpu.l2cache.ReadSharedReq_mshr_hits::total 5 # number of ReadSharedReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 5 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 6 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 6 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 7 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 5 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 6 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 6 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 7 # number of overall MSHR hits system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 53 # number of HardPFReq MSHR misses system.cpu.l2cache.HardPFReq_mshr_misses::total 53 # number of HardPFReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 30 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 30 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 290 # number of ReadCleanReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::total 290 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 96 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 96 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 98 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 98 # number of ReadSharedReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 290 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 126 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 416 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 128 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 418 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 290 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 126 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 128 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 53 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 469 # number of overall MSHR misses -system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 1908926 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 1908926 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2119000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2119000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 17622000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 17622000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5892000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 5892000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 17622000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8011000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 25633000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17622000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8011000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 1908926 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 27541926 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::total 471 # number of overall MSHR misses +system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 3053926 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 3053926 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2154000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2154000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 17682000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 17682000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6104000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 6104000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 17682000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8258000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 25940000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17682000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8258000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 3053926 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 28993926 # number of overall MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.731707 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.731707 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.969900 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.969900 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.932039 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.932039 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.951456 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.951456 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.969900 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.875000 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.939052 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.888889 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.943567 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.969900 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.875000 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.888889 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 1.058691 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 36017.471698 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 36017.471698 # average HardPFReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70633.333333 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70633.333333 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 60765.517241 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 60765.517241 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 61375 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 61375 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60765.517241 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63579.365079 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61617.788462 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60765.517241 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63579.365079 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 36017.471698 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58724.788913 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 1.063205 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 57621.245283 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 57621.245283 # average HardPFReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71800 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71800 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 60972.413793 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 60972.413793 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 62285.714286 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 62285.714286 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60972.413793 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64515.625000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62057.416268 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60972.413793 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64515.625000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 57621.245283 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61558.229299 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 488 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 74 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 12 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 411 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 370 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 41 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 18821000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.snoop_filter.tot_snoops 26 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 24 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 2 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 19046000 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 401 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 45 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 385 # Transaction distribution system.cpu.toL2Bus.trans_dist::HardPFReq 69 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 41 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 41 # Transaction distribution @@ -1106,49 +1105,55 @@ system.cpu.toL2Bus.pkt_count::total 930 # Pa system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 21952 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9216 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size::total 31168 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 454 # Total snoops (count) +system.cpu.toL2Bus.snoops 69 # Total snoops (count) system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 897 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.549610 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.582523 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 512 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.134766 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.353072 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 445 49.61% 49.61% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 411 45.82% 95.43% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 41 4.57% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 445 86.91% 86.91% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 65 12.70% 99.61% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 2 0.39% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 897 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 512 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 289000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.5 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 448999 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 2.4 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 216995 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 18821000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 412 # Transaction distribution +system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%) +system.membus.snoop_filter.tot_requests 445 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 35 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 19046000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 414 # Transaction distribution system.membus.trans_dist::ReadExReq 30 # Transaction distribution system.membus.trans_dist::ReadExResp 30 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 413 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 885 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 885 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 28288 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 28288 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 415 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 889 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 889 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 28416 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 28416 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 443 # Request fanout histogram +system.membus.snoop_fanout::samples 445 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 443 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 445 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 443 # Request fanout histogram -system.membus.reqLayer0.occupancy 561444 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 445 # Request fanout histogram +system.membus.reqLayer0.occupancy 562944 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 3.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 2329257 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 12.4 # Layer utilization (%) +system.membus.respLayer1.occupancy 2340257 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 12.3 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt index 55d542711..83c02dd61 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000003 # Nu sim_ticks 2695000 # Number of ticks simulated final_tick 2695000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 427598 # Simulator instruction rate (inst/s) -host_op_rate 499586 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 249859240 # Simulator tick rate (ticks/s) -host_mem_usage 254616 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host +host_inst_rate 207093 # Simulator instruction rate (inst/s) +host_op_rate 242387 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 121392563 # Simulator tick rate (ticks/s) +host_mem_usage 259512 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host sim_insts 4592 # Number of instructions simulated sim_ops 5378 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -344,6 +344,12 @@ system.cpu.op_class::MemWrite 938 17.40% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 5391 # Class of executed instruction +system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.pwrStateResidencyTicks::UNDEFINED 2695000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 5597 # Transaction distribution system.membus.trans_dist::ReadResp 5608 # Transaction distribution @@ -361,14 +367,14 @@ system.membus.pkt_size::total 26559 # Cu system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) system.membus.snoop_fanout::samples 6532 # Request fanout histogram -system.membus.snoop_fanout::mean 0.704991 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.456082 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 1927 29.50% 29.50% # Request fanout histogram -system.membus.snoop_fanout::1 4605 70.50% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 6532 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 6532 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt index 43260b12f..b8117da74 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000003 # Nu sim_ticks 2695000 # Number of ticks simulated final_tick 2695000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 433184 # Simulator instruction rate (inst/s) -host_op_rate 506134 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 253162440 # Simulator tick rate (ticks/s) -host_mem_usage 254364 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host +host_inst_rate 213878 # Simulator instruction rate (inst/s) +host_op_rate 250318 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 125362190 # Simulator tick rate (ticks/s) +host_mem_usage 258232 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host sim_insts 4592 # Number of instructions simulated sim_ops 5378 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -220,6 +220,12 @@ system.cpu.op_class::MemWrite 938 17.40% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 5391 # Class of executed instruction +system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.pwrStateResidencyTicks::UNDEFINED 2695000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 5597 # Transaction distribution system.membus.trans_dist::ReadResp 5608 # Transaction distribution @@ -237,14 +243,14 @@ system.membus.pkt_size::total 26559 # Cu system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) system.membus.snoop_fanout::samples 6532 # Request fanout histogram -system.membus.snoop_fanout::mean 0.704991 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.456082 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 1927 29.50% 29.50% # Request fanout histogram -system.membus.snoop_fanout::1 4605 70.50% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 6532 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 6532 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt index 40170ff2c..6ed816eb8 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000028 # Number of seconds simulated -sim_ticks 28298500 # Number of ticks simulated -final_tick 28298500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000029 # Number of seconds simulated +sim_ticks 28648500 # Number of ticks simulated +final_tick 28648500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 246555 # Simulator instruction rate (inst/s) -host_op_rate 287459 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1524533550 # Simulator tick rate (ticks/s) -host_mem_usage 264352 # Number of bytes of host memory used +host_inst_rate 192730 # Simulator instruction rate (inst/s) +host_op_rate 224907 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1208517164 # Simulator tick rate (ticks/s) +host_mem_usage 267456 # Number of bytes of host memory used host_seconds 0.02 # Real time elapsed on the host sim_insts 4566 # Number of instructions simulated sim_ops 5330 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 28648500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 14400 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 8000 # Number of bytes read from this memory system.physmem.bytes_read::total 22400 # Number of bytes read from this memory @@ -22,17 +22,17 @@ system.physmem.bytes_inst_read::total 14400 # Nu system.physmem.num_reads::cpu.inst 225 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 125 # Number of read requests responded to by this memory system.physmem.num_reads::total 350 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 508860894 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 282700496 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 791561390 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 508860894 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 508860894 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 508860894 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 282700496 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 791561390 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states +system.physmem.bw_read::cpu.inst 502644117 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 279246732 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 781890849 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 502644117 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 502644117 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 502644117 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 279246732 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 781890849 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 28648500 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 28648500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -62,7 +62,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 28648500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -92,7 +92,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 28648500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -122,7 +122,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 28648500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -153,8 +153,8 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 28298500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 56597 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 28648500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 57297 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 4566 # Number of instructions committed @@ -175,7 +175,7 @@ system.cpu.num_mem_refs 1965 # nu system.cpu.num_load_insts 1027 # Number of load instructions system.cpu.num_store_insts 938 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 56596.998000 # Number of busy cycles +system.cpu.num_busy_cycles 57296.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 1008 # Number of branches fetched @@ -214,23 +214,23 @@ system.cpu.op_class::MemWrite 938 17.40% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 5391 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 28648500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 82.647245 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 82.616265 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1786 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 141 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 12.666667 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 82.647245 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.020178 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.020178 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 82.616265 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.020170 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.020170 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 141 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 103 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 104 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.034424 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 3995 # Number of tag accesses system.cpu.dcache.tags.data_accesses 3995 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 28648500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 894 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 894 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 870 # number of WriteReq hits @@ -251,14 +251,14 @@ system.cpu.dcache.demand_misses::cpu.data 141 # n system.cpu.dcache.demand_misses::total 141 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 141 # number of overall misses system.cpu.dcache.overall_misses::total 141 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5308000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5308000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 2666000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 2666000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 7974000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 7974000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 7974000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 7974000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5390000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5390000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 2709000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 2709000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 8099000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 8099000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 8099000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 8099000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 992 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 992 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) @@ -279,14 +279,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.074016 system.cpu.dcache.demand_miss_rate::total 0.074016 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.074016 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.074016 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54163.265306 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 54163.265306 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 62000 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 56553.191489 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 56553.191489 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 56553.191489 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 56553.191489 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 63000 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 57439.716312 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 57439.716312 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 57439.716312 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 57439.716312 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -301,14 +301,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 141 system.cpu.dcache.demand_mshr_misses::total 141 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 141 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5210000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5210000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2623000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2623000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7833000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7833000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7833000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7833000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5292000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5292000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2666000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2666000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7958000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 7958000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7958000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7958000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.098790 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.098790 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047097 # mshr miss rate for WriteReq accesses @@ -317,31 +317,31 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.074016 system.cpu.dcache.demand_mshr_miss_rate::total 0.074016 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074016 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.074016 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53163.265306 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53163.265306 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 55553.191489 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 55553.191489 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 55553.191489 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 55553.191489 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 54000 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 54000 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62000 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 56439.716312 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 56439.716312 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 56439.716312 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 56439.716312 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 28648500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 1 # number of replacements -system.cpu.icache.tags.tagsinuse 114.043293 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 113.995886 # Cycle average of tags in use system.cpu.icache.tags.total_refs 4365 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 241 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 18.112033 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 114.043293 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.055685 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.055685 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 113.995886 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.055662 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.055662 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 240 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 96 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 144 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 95 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 145 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.117188 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 9453 # Number of tag accesses system.cpu.icache.tags.data_accesses 9453 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 28648500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 4365 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 4365 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 4365 # number of demand (read+write) hits @@ -354,12 +354,12 @@ system.cpu.icache.demand_misses::cpu.inst 241 # n system.cpu.icache.demand_misses::total 241 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 241 # number of overall misses system.cpu.icache.overall_misses::total 241 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 14179500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 14179500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 14179500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 14179500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14179500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14179500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 14404500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 14404500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 14404500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 14404500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 14404500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 14404500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 4606 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 4606 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 4606 # number of demand (read+write) accesses @@ -372,12 +372,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.052323 system.cpu.icache.demand_miss_rate::total 0.052323 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.052323 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.052323 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 58836.099585 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 58836.099585 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 58836.099585 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 58836.099585 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 58836.099585 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 58836.099585 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 59769.709544 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 59769.709544 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 59769.709544 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 59769.709544 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 59769.709544 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 59769.709544 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -392,43 +392,43 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 241 system.cpu.icache.demand_mshr_misses::total 241 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 241 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 241 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13938500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 13938500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13938500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 13938500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13938500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 13938500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14163500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 14163500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14163500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 14163500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14163500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 14163500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.052323 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.052323 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.052323 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.052323 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.052323 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.052323 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 57836.099585 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 57836.099585 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 57836.099585 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 57836.099585 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 57836.099585 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 57836.099585 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 58769.709544 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 58769.709544 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 58769.709544 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 58769.709544 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 58769.709544 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 58769.709544 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 28648500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 153.328645 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 180.559791 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 32 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 307 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.104235 # Average number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 350 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.091429 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.330622 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 47.998022 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003214 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.001465 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.004679 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 307 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 116 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 191 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.009369 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.285464 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 75.274327 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003213 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.002297 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.005510 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 350 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 119 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 231 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.010681 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 3406 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 3406 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 28648500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 16 # number of ReadCleanReq hits system.cpu.l2cache.ReadCleanReq_hits::total 16 # number of ReadCleanReq hits system.cpu.l2cache.ReadSharedReq_hits::cpu.data 16 # number of ReadSharedReq hits @@ -451,18 +451,18 @@ system.cpu.l2cache.demand_misses::total 350 # nu system.cpu.l2cache.overall_misses::cpu.inst 225 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 125 # number of overall misses system.cpu.l2cache.overall_misses::total 350 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2558500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 2558500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 13393000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 13393000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 4879000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 4879000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 13393000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7437500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 20830500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 13393000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7437500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 20830500 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2601500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 2601500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 13618000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 13618000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 4961000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 4961000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 13618000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 7562500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 21180500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 13618000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 7562500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 21180500 # number of overall miss cycles system.cpu.l2cache.ReadExReq_accesses::cpu.data 43 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 43 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 241 # number of ReadCleanReq accesses(hits+misses) @@ -487,18 +487,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.916230 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.933610 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.886525 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.916230 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59524.444444 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59524.444444 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59524.444444 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59500 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 59515.714286 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59524.444444 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 59515.714286 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60524.444444 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60524.444444 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60500 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60500 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60524.444444 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60500 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 60515.714286 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60524.444444 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60500 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 60515.714286 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -517,18 +517,18 @@ system.cpu.l2cache.demand_mshr_misses::total 350 system.cpu.l2cache.overall_mshr_misses::cpu.inst 225 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 125 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 350 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2128500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2128500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 11143000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 11143000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4059000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4059000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11143000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6187500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 17330500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11143000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6187500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 17330500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2171500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2171500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 11368000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 11368000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4141000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4141000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11368000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6312500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 17680500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11368000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6312500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 17680500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.933610 # mshr miss rate for ReadCleanReq accesses @@ -541,25 +541,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.916230 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.933610 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.886525 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.916230 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49524.444444 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49524.444444 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49524.444444 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49515.714286 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49524.444444 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49515.714286 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50524.444444 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50524.444444 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50524.444444 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50515.714286 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50524.444444 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50515.714286 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 383 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 32 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 28648500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 339 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 1 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 43 # Transaction distribution @@ -591,7 +591,13 @@ system.cpu.toL2Bus.respLayer0.occupancy 361500 # La system.cpu.toL2Bus.respLayer0.utilization 1.3 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 211500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states +system.membus.snoop_filter.tot_requests 350 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 28648500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 307 # Transaction distribution system.membus.trans_dist::ReadExReq 43 # Transaction distribution system.membus.trans_dist::ReadExResp 43 # Transaction distribution @@ -613,8 +619,8 @@ system.membus.snoop_fanout::min_value 0 # Re system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 350 # Request fanout histogram system.membus.reqLayer0.occupancy 355500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 1.3 # Layer utilization (%) +system.membus.reqLayer0.utilization 1.2 # Layer utilization (%) system.membus.respLayer1.occupancy 1750000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 6.2 # Layer utilization (%) +system.membus.respLayer1.utilization 6.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt index ba0daa415..fce732112 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000023 # Number of seconds simulated -sim_ticks 22532000 # Number of ticks simulated -final_tick 22532000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 22838000 # Number of ticks simulated +final_tick 22838000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 94024 # Simulator instruction rate (inst/s) -host_op_rate 93989 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 423490323 # Simulator tick rate (ticks/s) -host_mem_usage 248172 # Number of bytes of host memory used -host_seconds 0.05 # Real time elapsed on the host +host_inst_rate 76246 # Simulator instruction rate (inst/s) +host_op_rate 76230 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 348191953 # Simulator tick rate (ticks/s) +host_mem_usage 252304 # Number of bytes of host memory used +host_seconds 0.07 # Real time elapsed on the host sim_insts 4999 # Number of instructions simulated sim_ops 4999 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 22532000 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 22838000 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 21056 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 8960 # Number of bytes read from this memory system.physmem.bytes_read::total 30016 # Number of bytes read from this memory @@ -22,14 +22,14 @@ system.physmem.bytes_inst_read::total 21056 # Nu system.physmem.num_reads::cpu.inst 329 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 140 # Number of read requests responded to by this memory system.physmem.num_reads::total 469 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 934493165 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 397656666 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1332149831 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 934493165 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 934493165 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 934493165 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 397656666 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1332149831 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 921972152 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 392328575 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1314300727 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 921972152 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 921972152 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 921972152 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 392328575 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1314300727 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 469 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 469 # Number of DRAM read bursts, including those serviced by the write queue @@ -76,7 +76,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 22446500 # Total gap between requests +system.physmem.totGap 22751500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -91,8 +91,8 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 275 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 131 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 276 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 130 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 41 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 17 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see @@ -187,32 +187,32 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 106 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 257.207547 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 176.154447 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 250.139569 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 32 30.19% 30.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 32 30.19% 60.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 19 17.92% 78.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 9 8.49% 86.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 4 3.77% 90.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2 1.89% 92.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 2 1.89% 94.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 6 5.66% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 106 # Bytes accessed per row activation -system.physmem.totQLat 4611250 # Total ticks spent queuing -system.physmem.totMemAccLat 13405000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 105 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 259.047619 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 178.738362 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 250.145511 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 30 28.57% 28.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 33 31.43% 60.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 19 18.10% 78.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 9 8.57% 86.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 4 3.81% 90.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2 1.90% 92.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 2 1.90% 94.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 6 5.71% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 105 # Bytes accessed per row activation +system.physmem.totQLat 4619250 # Total ticks spent queuing +system.physmem.totMemAccLat 13413000 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2345000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9832.09 # Average queueing delay per DRAM burst +system.physmem.avgQLat 9849.15 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28582.09 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1332.15 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 28599.15 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1314.30 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1332.15 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1314.30 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 10.41 # Data bus utilization in percentage -system.physmem.busUtilRead 10.41 # Data bus utilization in percentage for reads +system.physmem.busUtil 10.27 # Data bus utilization in percentage +system.physmem.busUtilRead 10.27 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.73 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing @@ -220,49 +220,49 @@ system.physmem.readRowHits 353 # Nu system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 75.27 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 47860.34 # Average gap between requests +system.physmem.avgGap 48510.66 # Average gap between requests system.physmem.pageHitRate 75.27 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 128520 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 70125 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 538200 # Energy for read commands per rank (pJ) +system.physmem_0.readEnergy 514800 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 9591390 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1086000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 12431355 # Total energy per rank (pJ) -system.physmem_0.averagePower 785.179536 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2005750 # Time in different power states +system.physmem_0.actBackEnergy 9522135 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1146750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 12399450 # Total energy per rank (pJ) +system.physmem_0.averagePower 783.164377 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1868000 # Time in different power states system.physmem_0.memoryStateTime::REF 520000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 13559250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 13458250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 529200 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 288750 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 2176200 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 521640 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 284625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 2168400 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 10730250 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 87000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 14828520 # Total energy per rank (pJ) -system.physmem_1.averagePower 936.587399 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 103500 # Time in different power states +system.physmem_1.actBackEnergy 10729395 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 87750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 14808930 # Total energy per rank (pJ) +system.physmem_1.averagePower 935.350071 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 200750 # Time in different power states system.physmem_1.memoryStateTime::REF 520000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 15222750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 15221750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 22532000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 2183 # Number of BP lookups -system.cpu.branchPred.condPredicted 1455 # Number of conditional branches predicted +system.pwrStateResidencyTicks::UNDEFINED 22838000 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 2189 # Number of BP lookups +system.cpu.branchPred.condPredicted 1457 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 425 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 1779 # Number of BTB lookups +system.cpu.branchPred.BTBLookups 1784 # Number of BTB lookups system.cpu.branchPred.BTBHits 587 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 32.996065 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 250 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 32.903587 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 251 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 70 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 269 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectLookups 270 # Number of indirect predictor lookups. system.cpu.branchPred.indirectHits 2 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 267 # Number of indirect misses. +system.cpu.branchPred.indirectMisses 268 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 96 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.read_hits 0 # DTB read hits @@ -284,95 +284,95 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 7 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 22532000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 45065 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 22838000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 45677 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 9068 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 12986 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2183 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 839 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 4746 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.icacheStallCycles 9081 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 13012 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2189 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 840 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 4774 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 870 # Number of cycles fetch has spent squashing system.cpu.fetch.PendingTrapStallCycles 205 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 2047 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 264 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 14454 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.898436 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.187928 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 2050 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 263 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 14495 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.897689 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.187204 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 11097 76.77% 76.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1507 10.43% 87.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 110 0.76% 87.96% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 162 1.12% 89.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 279 1.93% 91.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 99 0.68% 91.70% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 140 0.97% 92.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 158 1.09% 93.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 902 6.24% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 11134 76.81% 76.81% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1506 10.39% 87.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 111 0.77% 87.97% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 162 1.12% 89.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 279 1.92% 91.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 100 0.69% 91.70% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 142 0.98% 92.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 158 1.09% 93.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 903 6.23% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 14454 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.048441 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.288162 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 8443 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 2703 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2773 # Number of cycles decode is running +system.cpu.fetch.rateDist::total 14495 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.047923 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.284870 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 8449 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 2734 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2777 # Number of cycles decode is running system.cpu.decode.UnblockCycles 140 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 395 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 182 # Number of times decode resolved a branch +system.cpu.decode.BranchResolved 183 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 40 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 12006 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 12026 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 160 # Number of squashed instructions handled by decode system.cpu.rename.SquashCycles 395 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 8593 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 592 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 973 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2745 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 1156 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 11571 # Number of instructions processed by rename +system.cpu.rename.IdleCycles 8600 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 597 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 983 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2748 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 1172 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 11590 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 5 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 4 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 175 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 954 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 6940 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 13573 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 13340 # Number of integer rename lookups +system.cpu.rename.LQFullEvents 177 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 968 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 6955 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 13597 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 13364 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 3 # Number of floating rename lookups system.cpu.rename.CommittedMaps 3292 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 3648 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 3663 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 13 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 9 # count of temporary serializing insts renamed system.cpu.rename.skidInsts 307 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2471 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedLoads 2472 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 1158 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 6 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 2 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 9030 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 9034 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 10 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 8122 # Number of instructions issued +system.cpu.iq.iqInstsIssued 8125 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 19 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 4040 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 2024 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedInstsExamined 4044 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 2026 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 1 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 14454 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.561921 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.290505 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 14495 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.560538 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.289389 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 11129 77.00% 77.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1334 9.23% 86.23% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 725 5.02% 91.24% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 461 3.19% 94.43% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 340 2.35% 96.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 284 1.96% 98.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 111 0.77% 99.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 51 0.35% 99.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 11167 77.04% 77.04% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1340 9.24% 86.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 721 4.97% 91.26% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 460 3.17% 94.43% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 343 2.37% 96.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 283 1.95% 98.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 110 0.76% 99.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 52 0.36% 99.87% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 19 0.13% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 14454 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 14495 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 7 3.87% 3.87% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 3.87% # attempts to use FU when none available @@ -408,54 +408,54 @@ system.cpu.iq.fu_full::MemWrite 57 31.49% 100.00% # at system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 4782 58.88% 58.88% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 4784 58.88% 58.88% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 4 0.05% 58.93% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 1 0.01% 58.94% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 58.96% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 58.96% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 58.96% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 58.96% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 58.96% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 58.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 58.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 58.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 58.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 58.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 58.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 58.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 58.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 58.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 58.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 58.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 58.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 58.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 58.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 58.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 58.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 58.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 58.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 58.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 58.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 58.96% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2272 27.97% 86.94% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 58.97% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 58.97% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 58.97% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 58.97% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 58.97% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 58.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 58.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 58.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 58.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 58.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 58.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 58.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 58.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 58.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 58.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 58.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 58.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 58.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 58.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 58.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 58.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 58.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 58.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 58.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 58.97% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 58.97% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2273 27.98% 86.94% # Type of FU issued system.cpu.iq.FU_type_0::MemWrite 1061 13.06% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 8122 # Type of FU issued -system.cpu.iq.rate 0.180229 # Inst issue rate +system.cpu.iq.FU_type_0::total 8125 # Type of FU issued +system.cpu.iq.rate 0.177879 # Inst issue rate system.cpu.iq.fu_busy_cnt 181 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.022285 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 30894 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 13087 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 7350 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fu_busy_rate 0.022277 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 30941 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 13095 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 7347 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 4 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 2 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 2 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 8301 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 8304 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 2 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 78 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1336 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1337 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 10 # Number of memory ordering violations system.cpu.iew.lsq.thread0.squashedStores 257 # Number of stores squashed @@ -465,54 +465,54 @@ system.cpu.iew.lsq.thread0.rescheduledLoads 0 # system.cpu.iew.lsq.thread0.cacheBlocked 25 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewSquashCycles 395 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 490 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 57 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 10642 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 148 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2471 # Number of dispatched load instructions +system.cpu.iew.iewBlockCycles 491 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 59 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 10646 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 156 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2472 # Number of dispatched load instructions system.cpu.iew.iewDispStoreInsts 1158 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 10 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 57 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 59 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 10 # Number of memory order violations system.cpu.iew.predictedTakenIncorrect 101 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 338 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 439 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 7800 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2128 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 322 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedNotTakenIncorrect 339 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 440 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 7799 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2130 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 326 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 1602 # number of nop insts executed -system.cpu.iew.exec_refs 3177 # number of memory reference insts executed -system.cpu.iew.exec_branches 1369 # Number of branches executed +system.cpu.iew.exec_refs 3179 # number of memory reference insts executed +system.cpu.iew.exec_branches 1368 # Number of branches executed system.cpu.iew.exec_stores 1049 # Number of stores executed -system.cpu.iew.exec_rate 0.173083 # Inst execution rate -system.cpu.iew.wb_sent 7447 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 7352 # cumulative count of insts written-back -system.cpu.iew.wb_producers 2874 # num instructions producing a value +system.cpu.iew.exec_rate 0.170742 # Inst execution rate +system.cpu.iew.wb_sent 7444 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 7349 # cumulative count of insts written-back +system.cpu.iew.wb_producers 2873 # num instructions producing a value system.cpu.iew.wb_consumers 4285 # num instructions consuming a value -system.cpu.iew.wb_rate 0.163142 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.670712 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 4995 # The number of squashed insts skipped by commit +system.cpu.iew.wb_rate 0.160891 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.670478 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 4999 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 9 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 385 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 13572 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.415561 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.228101 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 13612 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.414340 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.226502 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 11381 83.86% 83.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 886 6.53% 90.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 519 3.82% 94.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 254 1.87% 96.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 162 1.19% 97.27% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 163 1.20% 98.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 62 0.46% 98.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 41 0.30% 99.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 104 0.77% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 11422 83.91% 83.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 884 6.49% 90.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 520 3.82% 94.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 254 1.87% 96.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 161 1.18% 97.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 165 1.21% 98.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 61 0.45% 98.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 41 0.30% 99.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 104 0.76% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 13572 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 13612 # Number of insts commited each cycle system.cpu.commit.committedInsts 5640 # Number of instructions committed system.cpu.commit.committedOps 5640 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -559,46 +559,46 @@ system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Cl system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 5640 # Class of committed instruction system.cpu.commit.bw_lim_events 104 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 24090 # The number of ROB reads -system.cpu.rob.rob_writes 22160 # The number of ROB writes -system.cpu.timesIdled 263 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 30611 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 24134 # The number of ROB reads +system.cpu.rob.rob_writes 22169 # The number of ROB writes +system.cpu.timesIdled 264 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 31182 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 4999 # Number of Instructions Simulated system.cpu.committedOps 4999 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 9.014803 # CPI: Cycles Per Instruction -system.cpu.cpi_total 9.014803 # CPI: Total CPI of All Threads -system.cpu.ipc 0.110929 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.110929 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 10573 # number of integer regfile reads -system.cpu.int_regfile_writes 5151 # number of integer regfile writes +system.cpu.cpi 9.137227 # CPI: Cycles Per Instruction +system.cpu.cpi_total 9.137227 # CPI: Total CPI of All Threads +system.cpu.ipc 0.109442 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.109442 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 10569 # number of integer regfile reads +system.cpu.int_regfile_writes 5149 # number of integer regfile writes system.cpu.fp_regfile_reads 3 # number of floating regfile reads system.cpu.fp_regfile_writes 1 # number of floating regfile writes system.cpu.misc_regfile_reads 160 # number of misc regfile reads -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 22532000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 22838000 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 90.625823 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 2393 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 90.737808 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 2395 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 140 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 17.092857 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 17.107143 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 90.625823 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.022125 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.022125 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 90.737808 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.022153 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.022153 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 140 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 35 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 105 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 34 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 106 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.034180 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 5950 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 5950 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 22532000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 1837 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1837 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 5954 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 5954 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 22838000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 1839 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1839 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 556 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 556 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2393 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2393 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2393 # number of overall hits -system.cpu.dcache.overall_hits::total 2393 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 2395 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2395 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2395 # number of overall hits +system.cpu.dcache.overall_hits::total 2395 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 167 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 167 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 345 # number of WriteReq misses @@ -607,43 +607,43 @@ system.cpu.dcache.demand_misses::cpu.data 512 # n system.cpu.dcache.demand_misses::total 512 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 512 # number of overall misses system.cpu.dcache.overall_misses::total 512 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11867500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11867500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 24012499 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 24012499 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 35879999 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 35879999 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 35879999 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 35879999 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 2004 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 2004 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_latency::cpu.data 12256500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 12256500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 24340499 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 24340499 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 36596999 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 36596999 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 36596999 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 36596999 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 2006 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 2006 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2905 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2905 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2905 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2905 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.083333 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.083333 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2907 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2907 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2907 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2907 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.083250 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.083250 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.382908 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.382908 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.176248 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.176248 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.176248 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.176248 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 71062.874251 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 71062.874251 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69601.446377 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 69601.446377 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 70078.123047 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 70078.123047 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 70078.123047 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 70078.123047 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 592 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.176127 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.176127 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.176127 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.176127 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 73392.215569 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 73392.215569 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 70552.171014 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 70552.171014 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 71478.513672 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 71478.513672 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 71478.513672 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 71478.513672 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 600 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 10 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 59.200000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 60 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.ReadReq_mshr_hits::cpu.data 77 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 77 # number of ReadReq MSHR hits @@ -661,83 +661,83 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 140 system.cpu.dcache.demand_mshr_misses::total 140 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 140 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 140 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7550000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 7550000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4082999 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4082999 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11632999 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 11632999 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11632999 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 11632999 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.044910 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.044910 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7898000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 7898000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4132999 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4132999 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12030999 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 12030999 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12030999 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 12030999 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.044865 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.044865 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055494 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055494 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.048193 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.048193 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.048193 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.048193 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 83888.888889 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 83888.888889 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 81659.980000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 81659.980000 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 83092.850000 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 83092.850000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 83092.850000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 83092.850000 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 22532000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.048160 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.048160 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.048160 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.048160 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 87755.555556 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 87755.555556 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 82659.980000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 82659.980000 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 85935.707143 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 85935.707143 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 85935.707143 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 85935.707143 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 22838000 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 17 # number of replacements -system.cpu.icache.tags.tagsinuse 158.780297 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1610 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 158.952170 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1612 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 332 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 4.849398 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 4.855422 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 158.780297 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.077529 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.077529 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 158.952170 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.077613 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.077613 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 315 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 143 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 172 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 141 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 174 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.153809 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 4426 # Number of tag accesses -system.cpu.icache.tags.data_accesses 4426 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 22532000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 1610 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1610 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1610 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1610 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1610 # number of overall hits -system.cpu.icache.overall_hits::total 1610 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 437 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 437 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 437 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 437 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 437 # number of overall misses -system.cpu.icache.overall_misses::total 437 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 32774000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 32774000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 32774000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 32774000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 32774000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 32774000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 2047 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 2047 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 2047 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 2047 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 2047 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 2047 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.213483 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.213483 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.213483 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.213483 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.213483 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.213483 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 74997.711670 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 74997.711670 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 74997.711670 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 74997.711670 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 74997.711670 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 74997.711670 # average overall miss latency +system.cpu.icache.tags.tag_accesses 4432 # Number of tag accesses +system.cpu.icache.tags.data_accesses 4432 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 22838000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 1612 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1612 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1612 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1612 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1612 # number of overall hits +system.cpu.icache.overall_hits::total 1612 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 438 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 438 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 438 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 438 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 438 # number of overall misses +system.cpu.icache.overall_misses::total 438 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 33275000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 33275000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 33275000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 33275000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 33275000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 33275000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 2050 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 2050 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 2050 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 2050 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 2050 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 2050 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.213659 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.213659 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.213659 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.213659 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.213659 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.213659 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75970.319635 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 75970.319635 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 75970.319635 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 75970.319635 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 75970.319635 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 75970.319635 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -746,55 +746,55 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.writebacks::writebacks 17 # number of writebacks system.cpu.icache.writebacks::total 17 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 105 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 105 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 105 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 105 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 105 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 105 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 106 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 106 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 106 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 106 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 106 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 106 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 332 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 332 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 332 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 332 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 332 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 332 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 26055500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 26055500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 26055500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 26055500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 26055500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 26055500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.162189 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.162189 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.162189 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.162189 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.162189 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.162189 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 78480.421687 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 78480.421687 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 78480.421687 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 78480.421687 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 78480.421687 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 78480.421687 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 22532000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 26133000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 26133000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 26133000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 26133000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 26133000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 26133000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.161951 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.161951 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.161951 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.161951 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.161951 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.161951 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 78713.855422 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 78713.855422 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 78713.855422 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 78713.855422 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 78713.855422 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 78713.855422 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 22838000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 218.003826 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 251.694203 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 20 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 419 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.047733 # Average number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 469 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.042644 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 160.713393 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 57.290433 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004905 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.001748 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.006653 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 419 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 181 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 238 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012787 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_blocks::cpu.inst 160.892029 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 90.802174 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004910 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.002771 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.007681 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 469 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 187 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 282 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.014313 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 4381 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 4381 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 22532000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 22838000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackClean_hits::writebacks 17 # number of WritebackClean hits system.cpu.l2cache.WritebackClean_hits::total 17 # number of WritebackClean hits system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 3 # number of ReadCleanReq hits @@ -815,18 +815,18 @@ system.cpu.l2cache.demand_misses::total 469 # nu system.cpu.l2cache.overall_misses::cpu.inst 329 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 140 # number of overall misses system.cpu.l2cache.overall_misses::total 469 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4007000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 4007000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 25524500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 25524500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 7412000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 7412000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 25524500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 11419000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 36943500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 25524500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 11419000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 36943500 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4057000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 4057000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 25602000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 25602000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 7760000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 7760000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 25602000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 11817000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 37419000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 25602000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 11817000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 37419000 # number of overall miss cycles system.cpu.l2cache.WritebackClean_accesses::writebacks 17 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::total 17 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 50 # number of ReadExReq accesses(hits+misses) @@ -853,18 +853,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.993644 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.990964 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.993644 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80140 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80140 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 77582.066869 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 77582.066869 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 82355.555556 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 82355.555556 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77582.066869 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81564.285714 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 78770.788913 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77582.066869 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81564.285714 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 78770.788913 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81140 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81140 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 77817.629179 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 77817.629179 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 86222.222222 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 86222.222222 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77817.629179 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 84407.142857 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 79784.648188 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77817.629179 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 84407.142857 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 79784.648188 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -883,18 +883,18 @@ system.cpu.l2cache.demand_mshr_misses::total 469 system.cpu.l2cache.overall_mshr_misses::cpu.inst 329 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 140 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 469 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3507000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3507000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 22234500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 22234500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6512000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 6512000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22234500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10019000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 32253500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22234500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10019000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 32253500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3557000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3557000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 22312000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 22312000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6860000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 6860000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22312000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10417000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 32729000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22312000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10417000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 32729000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.990964 # mshr miss rate for ReadCleanReq accesses @@ -907,25 +907,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.993644 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.990964 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.993644 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70140 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70140 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67582.066869 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67582.066869 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72355.555556 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72355.555556 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67582.066869 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71564.285714 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68770.788913 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67582.066869 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71564.285714 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68770.788913 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71140 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71140 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67817.629179 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67817.629179 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 76222.222222 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76222.222222 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67817.629179 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 74407.142857 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69784.648188 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67817.629179 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 74407.142857 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69784.648188 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 489 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 17 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 22532000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 22838000 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 422 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 17 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 50 # Transaction distribution @@ -952,12 +952,18 @@ system.cpu.toL2Bus.snoop_fanout::min_value 0 # system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 472 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 261500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) +system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 498000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 2.2 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 210000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 22532000 # Cumulative time (in ticks) in various power states +system.membus.snoop_filter.tot_requests 469 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 22838000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 419 # Transaction distribution system.membus.trans_dist::ReadExReq 50 # Transaction distribution system.membus.trans_dist::ReadExResp 50 # Transaction distribution @@ -978,9 +984,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 469 # Request fanout histogram -system.membus.reqLayer0.occupancy 582000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.6 # Layer utilization (%) -system.membus.respLayer1.occupancy 2494000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 11.1 # Layer utilization (%) +system.membus.reqLayer0.occupancy 581500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.5 # Layer utilization (%) +system.membus.respLayer1.occupancy 2494250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 10.9 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/stats.txt index 619b5f6ac..fd6e40c23 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000003 # Nu sim_ticks 2820500 # Number of ticks simulated final_tick 2820500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 890532 # Simulator instruction rate (inst/s) -host_op_rate 888973 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 443763917 # Simulator tick rate (ticks/s) -host_mem_usage 236392 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host +host_inst_rate 280567 # Simulator instruction rate (inst/s) +host_op_rate 280375 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 140096420 # Simulator tick rate (ticks/s) +host_mem_usage 239748 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host sim_insts 5641 # Number of instructions simulated sim_ops 5641 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -116,6 +116,12 @@ system.cpu.op_class::MemWrite 902 15.99% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 5642 # Class of executed instruction +system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.pwrStateResidencyTicks::UNDEFINED 2820500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 6777 # Transaction distribution system.membus.trans_dist::ReadResp 6777 # Transaction distribution @@ -130,14 +136,14 @@ system.membus.pkt_size::total 30470 # Cu system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) system.membus.snoop_fanout::samples 7678 # Request fanout histogram -system.membus.snoop_fanout::mean 0.734827 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.441454 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 2036 26.52% 26.52% # Request fanout histogram -system.membus.snoop_fanout::1 5642 73.48% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 7678 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 7678 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt index 29abc2b26..657853e9f 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000034 # Number of seconds simulated -sim_ticks 33932500 # Number of ticks simulated -final_tick 33932500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 34362500 # Number of ticks simulated +final_tick 34362500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 18620 # Simulator instruction rate (inst/s) -host_op_rate 18619 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 111991731 # Simulator tick rate (ticks/s) -host_mem_usage 246380 # Number of bytes of host memory used -host_seconds 0.30 # Real time elapsed on the host +host_inst_rate 251821 # Simulator instruction rate (inst/s) +host_op_rate 251667 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1532173253 # Simulator tick rate (ticks/s) +host_mem_usage 250252 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host sim_insts 5641 # Number of instructions simulated sim_ops 5641 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 33932500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 34362500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 18752 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 8768 # Number of bytes read from this memory system.physmem.bytes_read::total 27520 # Number of bytes read from this memory @@ -22,15 +22,15 @@ system.physmem.bytes_inst_read::total 18752 # Nu system.physmem.num_reads::cpu.inst 293 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 137 # Number of read requests responded to by this memory system.physmem.num_reads::total 430 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 552626538 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 258395344 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 811021882 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 552626538 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 552626538 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 552626538 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 258395344 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 811021882 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 33932500 # Cumulative time (in ticks) in various power states +system.physmem.bw_read::cpu.inst 545711168 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 255161877 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 800873045 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 545711168 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 545711168 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 545711168 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 255161877 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 800873045 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 34362500 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses @@ -51,8 +51,8 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 7 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 33932500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 67865 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 34362500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 68725 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 5641 # Number of instructions committed @@ -71,7 +71,7 @@ system.cpu.num_mem_refs 2037 # nu system.cpu.num_load_insts 1135 # Number of load instructions system.cpu.num_store_insts 902 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 67865 # Number of busy cycles +system.cpu.num_busy_cycles 68725 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 886 # Number of branches fetched @@ -110,23 +110,23 @@ system.cpu.op_class::MemWrite 902 15.99% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 5642 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 33932500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 34362500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 86.030444 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 86.019878 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1899 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 137 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 13.861314 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 86.030444 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.021004 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.021004 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 86.019878 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.021001 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.021001 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 137 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 22 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 115 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.033447 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 4209 # Number of tag accesses system.cpu.dcache.tags.data_accesses 4209 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 33932500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 34362500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 1048 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1048 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 851 # number of WriteReq hits @@ -143,14 +143,14 @@ system.cpu.dcache.demand_misses::cpu.data 137 # n system.cpu.dcache.demand_misses::total 137 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 137 # number of overall misses system.cpu.dcache.overall_misses::total 137 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5394000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5394000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 3100000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 3100000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 8494000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 8494000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 8494000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 8494000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5481000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5481000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 3150000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 3150000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 8631000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 8631000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 8631000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 8631000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1135 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1135 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 901 # number of WriteReq accesses(hits+misses) @@ -167,14 +167,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.067289 system.cpu.dcache.demand_miss_rate::total 0.067289 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.067289 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.067289 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62000 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 62000 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 62000 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 62000 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 62000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 62000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 62000 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 63000 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 63000 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 63000 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 63000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 63000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 63000 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -189,14 +189,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 137 system.cpu.dcache.demand_mshr_misses::total 137 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 137 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 137 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5307000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5307000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3050000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3050000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8357000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 8357000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8357000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 8357000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5394000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5394000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3100000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3100000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8494000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 8494000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8494000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 8494000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076652 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076652 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055494 # mshr miss rate for WriteReq accesses @@ -205,31 +205,31 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.067289 system.cpu.dcache.demand_mshr_miss_rate::total 0.067289 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.067289 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.067289 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61000 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61000 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 33932500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 62000 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 62000 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62000 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 62000 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 62000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 62000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 62000 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 34362500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 13 # number of replacements -system.cpu.icache.tags.tagsinuse 128.953338 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 128.944610 # Cycle average of tags in use system.cpu.icache.tags.total_refs 5348 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 295 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 18.128814 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 128.953338 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.062965 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.062965 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 128.944610 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.062961 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.062961 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 282 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 105 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 177 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.137695 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 11581 # Number of tag accesses system.cpu.icache.tags.data_accesses 11581 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 33932500 # Cumulative time (in ticks) in various power states +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 34362500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 5348 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 5348 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 5348 # number of demand (read+write) hits @@ -242,12 +242,12 @@ system.cpu.icache.demand_misses::cpu.inst 295 # n system.cpu.icache.demand_misses::total 295 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 295 # number of overall misses system.cpu.icache.overall_misses::total 295 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 18192500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 18192500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 18192500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 18192500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 18192500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 18192500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 18485500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 18485500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 18485500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 18485500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 18485500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 18485500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 5643 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 5643 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 5643 # number of demand (read+write) accesses @@ -260,12 +260,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.052277 system.cpu.icache.demand_miss_rate::total 0.052277 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.052277 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.052277 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61669.491525 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 61669.491525 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 61669.491525 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 61669.491525 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 61669.491525 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 61669.491525 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62662.711864 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 62662.711864 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 62662.711864 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 62662.711864 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 62662.711864 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 62662.711864 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -280,43 +280,43 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 295 system.cpu.icache.demand_mshr_misses::total 295 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 295 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 295 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17897500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 17897500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17897500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 17897500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17897500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 17897500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 18190500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 18190500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 18190500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 18190500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 18190500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 18190500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.052277 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.052277 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.052277 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.052277 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.052277 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.052277 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60669.491525 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60669.491525 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60669.491525 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 60669.491525 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60669.491525 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 60669.491525 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 33932500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61662.711864 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61662.711864 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61662.711864 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 61662.711864 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61662.711864 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 61662.711864 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 34362500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 183.490494 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 216.139082 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 15 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 380 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.039474 # Average number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 430 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.034884 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 130.087016 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 53.403478 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 130.077342 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 86.061740 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003970 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.001630 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.005600 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 380 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 125 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 255 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.011597 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_percent::cpu.data 0.002626 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.006596 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 430 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 130 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 300 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.013123 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 3990 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 3990 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 33932500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 34362500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackClean_hits::writebacks 13 # number of WritebackClean hits system.cpu.l2cache.WritebackClean_hits::total 13 # number of WritebackClean hits system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2 # number of ReadCleanReq hits @@ -337,18 +337,18 @@ system.cpu.l2cache.demand_misses::total 430 # nu system.cpu.l2cache.overall_misses::cpu.inst 293 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 137 # number of overall misses system.cpu.l2cache.overall_misses::total 430 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2975000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 2975000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 17434000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 17434000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 5176500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 5176500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 17434000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 8151500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 25585500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 17434000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 8151500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 25585500 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3025000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 3025000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 17727000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 17727000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 5263500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 5263500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 17727000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 8288500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 26015500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 17727000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 8288500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 26015500 # number of overall miss cycles system.cpu.l2cache.WritebackClean_accesses::writebacks 13 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::total 13 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 50 # number of ReadExReq accesses(hits+misses) @@ -375,18 +375,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.995370 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993220 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.995370 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59501.706485 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59501.706485 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59501.706485 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59500 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 59501.162791 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59501.706485 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 59501.162791 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60501.706485 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60501.706485 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60500 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60500 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60501.706485 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60500 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 60501.162791 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60501.706485 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60500 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 60501.162791 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -405,18 +405,18 @@ system.cpu.l2cache.demand_mshr_misses::total 430 system.cpu.l2cache.overall_mshr_misses::cpu.inst 293 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 137 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 430 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2475000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2475000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 14504000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 14504000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4306500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4306500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 14504000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6781500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 21285500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 14504000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6781500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 21285500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2525000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2525000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 14797000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 14797000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4393500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4393500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 14797000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6918500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 21715500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 14797000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6918500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 21715500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.993220 # mshr miss rate for ReadCleanReq accesses @@ -429,25 +429,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.995370 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993220 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.995370 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49501.706485 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49501.706485 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49501.706485 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49501.162791 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49501.706485 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49501.162791 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50501.706485 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50501.706485 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50501.706485 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50501.162791 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50501.706485 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50501.162791 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 445 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 13 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 33932500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 34362500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 382 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 13 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 50 # Transaction distribution @@ -479,7 +479,13 @@ system.cpu.toL2Bus.respLayer0.occupancy 442500 # La system.cpu.toL2Bus.respLayer0.utilization 1.3 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 205500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.6 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 33932500 # Cumulative time (in ticks) in various power states +system.membus.snoop_filter.tot_requests 430 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 34362500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 380 # Transaction distribution system.membus.trans_dist::ReadExReq 50 # Transaction distribution system.membus.trans_dist::ReadExResp 50 # Transaction distribution diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt index a1b1af10d..ee06020dc 100644 --- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000020 # Number of seconds simulated -sim_ticks 19908000 # Number of ticks simulated -final_tick 19908000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 20159000 # Number of ticks simulated +final_tick 20159000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 79311 # Simulator instruction rate (inst/s) -host_op_rate 79299 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 272523705 # Simulator tick rate (ticks/s) -host_mem_usage 246096 # Number of bytes of host memory used -host_seconds 0.07 # Real time elapsed on the host +host_inst_rate 70194 # Simulator instruction rate (inst/s) +host_op_rate 70182 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 244226628 # Simulator tick rate (ticks/s) +host_mem_usage 249960 # Number of bytes of host memory used +host_seconds 0.08 # Real time elapsed on the host sim_insts 5792 # Number of instructions simulated sim_ops 5792 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 19908000 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 20159000 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 21952 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 6400 # Number of bytes read from this memory system.physmem.bytes_read::total 28352 # Number of bytes read from this memory @@ -22,14 +22,14 @@ system.physmem.bytes_inst_read::total 21952 # Nu system.physmem.num_reads::cpu.inst 343 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 100 # Number of read requests responded to by this memory system.physmem.num_reads::total 443 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1102672293 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 321478802 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1424151095 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1102672293 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1102672293 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1102672293 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 321478802 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1424151095 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1088942904 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 317476065 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1406418969 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1088942904 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1088942904 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1088942904 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 317476065 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1406418969 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 445 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 445 # Number of DRAM read bursts, including those serviced by the write queue @@ -76,7 +76,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 19857500 # Total gap between requests +system.physmem.totGap 20108500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -189,31 +189,30 @@ system.physmem.wrQLenPdf::62 0 # Wh system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see system.physmem.bytesPerActivate::samples 76 # Bytes accessed per row activation system.physmem.bytesPerActivate::mean 341.894737 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 206.686426 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 337.291153 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 25 32.89% 32.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 17 22.37% 55.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 10 13.16% 68.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 206.930275 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 338.261263 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 24 31.58% 31.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 19 25.00% 56.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 9 11.84% 68.42% # Bytes accessed per row activation system.physmem.bytesPerActivate::384-511 3 3.95% 72.37% # Bytes accessed per row activation system.physmem.bytesPerActivate::512-639 4 5.26% 77.63% # Bytes accessed per row activation system.physmem.bytesPerActivate::640-767 4 5.26% 82.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1 1.32% 84.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 3 3.95% 88.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 9 11.84% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 5 6.58% 89.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8 10.53% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 76 # Bytes accessed per row activation -system.physmem.totQLat 3759500 # Total ticks spent queuing -system.physmem.totMemAccLat 12103250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 3790750 # Total ticks spent queuing +system.physmem.totMemAccLat 12134500 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2225000 # Total ticks spent in databus transfers -system.physmem.avgQLat 8448.31 # Average queueing delay per DRAM burst +system.physmem.avgQLat 8518.54 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 27198.31 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1430.58 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 27268.54 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1412.77 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1430.58 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1412.77 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 11.18 # Data bus utilization in percentage -system.physmem.busUtilRead 11.18 # Data bus utilization in percentage for reads +system.physmem.busUtil 11.04 # Data bus utilization in percentage +system.physmem.busUtilRead 11.04 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.78 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing @@ -221,37 +220,37 @@ system.physmem.readRowHits 360 # Nu system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 80.90 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 44623.60 # Average gap between requests +system.physmem.avgGap 45187.64 # Average gap between requests system.physmem.pageHitRate 80.90 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 438480 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 239250 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 2511600 # Energy for read commands per rank (pJ) +system.physmem_0.readEnergy 2496000 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 10783260 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 40500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 15030210 # Total energy per rank (pJ) -system.physmem_0.averagePower 949.326386 # Core power per rank (mW) +system.physmem_0.actBackEnergy 10814895 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 32250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 15037995 # Total energy per rank (pJ) +system.physmem_0.averagePower 947.872361 # Core power per rank (mW) system.physmem_0.memoryStateTime::IDLE 11500 # Time in different power states system.physmem_0.memoryStateTime::REF 520000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 15314750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 15347250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.physmem_1.actEnergy 68040 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 37125 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 288600 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 7632585 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 2804250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 11847720 # Total energy per rank (pJ) -system.physmem_1.averagePower 748.316438 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 6301750 # Time in different power states +system.physmem_1.actBackEnergy 7519725 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 2903250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 11833860 # Total energy per rank (pJ) +system.physmem_1.averagePower 747.441023 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 6690750 # Time in different power states system.physmem_1.memoryStateTime::REF 520000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 10721750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 10557750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 19908000 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 20159000 # Cumulative time (in ticks) in various power states system.cpu.branchPred.lookups 2407 # Number of BP lookups system.cpu.branchPred.condPredicted 1979 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 409 # Number of conditional branches incorrect @@ -285,96 +284,96 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 9 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 19908000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 39817 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 20159000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 40319 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 7705 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 13362 # Number of instructions fetch has processed +system.cpu.fetch.icacheStallCycles 7699 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 13357 # Number of instructions fetch has processed system.cpu.fetch.Branches 2407 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 936 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 3591 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.Cycles 4134 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 847 # Number of cycles fetch has spent squashing system.cpu.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 146 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 22 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 1856 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 289 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 11892 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.123613 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.518960 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 1855 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 288 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 12429 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.074664 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.474276 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 9557 80.36% 80.36% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 166 1.40% 81.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 217 1.82% 83.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 147 1.24% 84.82% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 245 2.06% 86.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 147 1.24% 88.12% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 275 2.31% 90.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 148 1.24% 91.68% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 990 8.32% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 10095 81.22% 81.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 166 1.34% 82.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 217 1.75% 84.30% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 147 1.18% 85.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 245 1.97% 87.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 146 1.17% 88.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 275 2.21% 90.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 148 1.19% 92.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 990 7.97% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 11892 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.060452 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.335585 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 7298 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 2243 # Number of cycles decode is blocked +system.cpu.fetch.rateDist::total 12429 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.059699 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.331283 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 7289 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 2789 # Number of cycles decode is blocked system.cpu.decode.RunCycles 1948 # Number of cycles decode is running system.cpu.decode.UnblockCycles 128 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 275 # Number of cycles decode is squashing system.cpu.decode.BranchResolved 323 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 149 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 11471 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 450 # Number of squashed instructions handled by decode +system.cpu.decode.DecodedInsts 11479 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 451 # Number of squashed instructions handled by decode system.cpu.rename.SquashCycles 275 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 7466 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 800 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 447 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 1898 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 1006 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 11040 # Number of instructions processed by rename +system.cpu.rename.IdleCycles 7458 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 805 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 449 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 1896 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 1546 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 11044 # Number of instructions processed by rename system.cpu.rename.IQFullEvents 12 # Number of times rename has blocked due to IQ full system.cpu.rename.LQFullEvents 2 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 965 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 9709 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 17887 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 17861 # Number of integer rename lookups +system.cpu.rename.SQFullEvents 1504 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 9711 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 17893 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 17867 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 26 # Number of floating rename lookups system.cpu.rename.CommittedMaps 4998 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 4711 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 4713 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 27 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 27 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 354 # count of insts added to the skid buffer +system.cpu.rename.skidInsts 365 # count of insts added to the skid buffer system.cpu.memDep0.insertedLoads 1936 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1591 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1592 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 55 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 30 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 10171 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 10175 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 63 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 8811 # Number of instructions issued +system.cpu.iq.iqInstsIssued 8810 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 53 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 4442 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3468 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedInstsExamined 4446 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3475 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 47 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 11892 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.740918 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.536831 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 12429 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.708826 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.510537 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 8764 73.70% 73.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 985 8.28% 81.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 659 5.54% 87.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 457 3.84% 91.36% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 433 3.64% 95.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 285 2.40% 97.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 215 1.81% 99.21% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 62 0.52% 99.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 32 0.27% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 9301 74.83% 74.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 985 7.93% 82.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 659 5.30% 88.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 457 3.68% 91.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 433 3.48% 95.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 286 2.30% 97.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 214 1.72% 99.24% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 62 0.50% 99.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 32 0.26% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 11892 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 12429 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 12 6.35% 6.35% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 6.35% # attempts to use FU when none available @@ -413,66 +412,66 @@ system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Ty system.cpu.iq.FU_type_0::IntAlu 5533 62.80% 62.80% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 0 0.00% 62.80% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.80% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 62.82% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.82% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.82% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.82% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.82% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.82% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 1812 20.57% 83.38% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 62.83% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.83% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.83% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.83% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.83% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.83% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 1811 20.56% 83.38% # Type of FU issued system.cpu.iq.FU_type_0::MemWrite 1464 16.62% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 8811 # Type of FU issued -system.cpu.iq.rate 0.221287 # Inst issue rate +system.cpu.iq.FU_type_0::total 8810 # Type of FU issued +system.cpu.iq.rate 0.218507 # Inst issue rate system.cpu.iq.fu_busy_cnt 189 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.021450 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 29694 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 14646 # Number of integer instruction queue writes +system.cpu.iq.fu_busy_rate 0.021453 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 30229 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 14654 # Number of integer instruction queue writes system.cpu.iq.int_inst_queue_wakeup_accesses 8112 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 62 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 36 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 27 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 8966 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 8965 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 34 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 83 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread0.squashedLoads 975 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 6 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 545 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 546 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 7 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewSquashCycles 275 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 716 # Number of cycles IEW is blocking +system.cpu.iew.iewBlockCycles 721 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 77 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 10234 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispatchedInsts 10238 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 32 # Number of squashed instructions skipped by dispatch system.cpu.iew.iewDispLoadInsts 1936 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1591 # Number of dispatched store instructions +system.cpu.iew.iewDispStoreInsts 1592 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 53 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 12 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 66 # Number of times the LSQ has become full, causing a stall @@ -482,39 +481,39 @@ system.cpu.iew.predictedNotTakenIncorrect 256 # N system.cpu.iew.branchMispredicts 324 # Number of branch mispredicts detected at execute system.cpu.iew.iewExecutedInsts 8460 # Number of executed instructions system.cpu.iew.iewExecLoadInsts 1699 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 351 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecSquashedInsts 350 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed system.cpu.iew.exec_refs 3077 # number of memory reference insts executed -system.cpu.iew.exec_branches 1357 # Number of branches executed +system.cpu.iew.exec_branches 1359 # Number of branches executed system.cpu.iew.exec_stores 1378 # Number of stores executed -system.cpu.iew.exec_rate 0.212472 # Inst execution rate +system.cpu.iew.exec_rate 0.209827 # Inst execution rate system.cpu.iew.wb_sent 8239 # cumulative count of insts sent to commit system.cpu.iew.wb_count 8139 # cumulative count of insts written-back -system.cpu.iew.wb_producers 4434 # num instructions producing a value -system.cpu.iew.wb_consumers 7122 # num instructions consuming a value -system.cpu.iew.wb_rate 0.204410 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.622578 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 4444 # The number of squashed insts skipped by commit +system.cpu.iew.wb_producers 4432 # num instructions producing a value +system.cpu.iew.wb_consumers 7119 # num instructions consuming a value +system.cpu.iew.wb_rate 0.201865 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.622559 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 4448 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 16 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 270 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 11191 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.517559 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.381685 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 11727 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.493903 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.354058 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 9014 80.55% 80.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 859 7.68% 88.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 529 4.73% 92.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 217 1.94% 94.89% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 185 1.65% 96.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 107 0.96% 97.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 121 1.08% 98.58% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 49 0.44% 99.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 110 0.98% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 9550 81.44% 81.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 859 7.32% 88.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 529 4.51% 93.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 217 1.85% 95.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 185 1.58% 96.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 107 0.91% 97.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 121 1.03% 98.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 49 0.42% 99.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 110 0.94% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 11191 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 11727 # Number of insts commited each cycle system.cpu.commit.committedInsts 5792 # Number of instructions committed system.cpu.commit.committedOps 5792 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -561,37 +560,37 @@ system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Cl system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 5792 # Class of committed instruction system.cpu.commit.bw_lim_events 110 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 21317 # The number of ROB reads -system.cpu.rob.rob_writes 21174 # The number of ROB writes -system.cpu.timesIdled 231 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 27925 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 21857 # The number of ROB reads +system.cpu.rob.rob_writes 21183 # The number of ROB writes +system.cpu.timesIdled 230 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 27890 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5792 # Number of Instructions Simulated system.cpu.committedOps 5792 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 6.874482 # CPI: Cycles Per Instruction -system.cpu.cpi_total 6.874482 # CPI: Total CPI of All Threads -system.cpu.ipc 0.145466 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.145466 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 13370 # number of integer regfile reads -system.cpu.int_regfile_writes 7150 # number of integer regfile writes +system.cpu.cpi 6.961153 # CPI: Cycles Per Instruction +system.cpu.cpi_total 6.961153 # CPI: Total CPI of All Threads +system.cpu.ipc 0.143654 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.143654 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 13369 # number of integer regfile reads +system.cpu.int_regfile_writes 7149 # number of integer regfile writes system.cpu.fp_regfile_reads 25 # number of floating regfile reads system.cpu.fp_regfile_writes 2 # number of floating regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 19908000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 20159000 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 64.466372 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 64.445386 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 2199 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 102 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 21.558824 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 64.466372 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.015739 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.015739 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 64.445386 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.015734 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.015734 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 102 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 72 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 75 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.024902 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 5374 # Number of tag accesses system.cpu.dcache.tags.data_accesses 5374 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 19908000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 20159000 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 1477 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1477 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 722 # number of WriteReq hits @@ -608,14 +607,14 @@ system.cpu.dcache.demand_misses::cpu.data 437 # n system.cpu.dcache.demand_misses::total 437 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 437 # number of overall misses system.cpu.dcache.overall_misses::total 437 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 7807000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 7807000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 23805496 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 23805496 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 31612496 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 31612496 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 31612496 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 31612496 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 7904000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 7904000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 32053496 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 32053496 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 39957496 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 39957496 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 39957496 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 39957496 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1590 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1590 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 1046 # number of WriteReq accesses(hits+misses) @@ -632,19 +631,19 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.165781 system.cpu.dcache.demand_miss_rate::total 0.165781 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.165781 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.165781 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 69088.495575 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 69088.495575 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73473.753086 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 73473.753086 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 72339.807780 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 72339.807780 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 72339.807780 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 72339.807780 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 598 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 69946.902655 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 69946.902655 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 98930.543210 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 98930.543210 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 91435.917620 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 91435.917620 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 91435.917620 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 91435.917620 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 604 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 6 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 99.666667 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 100.666667 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.ReadReq_mshr_hits::cpu.data 56 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 56 # number of ReadReq MSHR hits @@ -662,14 +661,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 104 system.cpu.dcache.demand_mshr_misses::total 104 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 104 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 104 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4432500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4432500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4005998 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4005998 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8438498 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 8438498 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8438498 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 8438498 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4485500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4485500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4548998 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4548998 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9034498 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9034498 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9034498 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 9034498 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.035849 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.035849 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044933 # mshr miss rate for WriteReq accesses @@ -678,72 +677,72 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.039454 system.cpu.dcache.demand_mshr_miss_rate::total 0.039454 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.039454 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.039454 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 77763.157895 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 77763.157895 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 85234 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 85234 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 81139.403846 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 81139.403846 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 81139.403846 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 81139.403846 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 19908000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78692.982456 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78692.982456 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 96787.191489 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 96787.191489 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 86870.173077 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 86870.173077 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 86870.173077 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 86870.173077 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 20159000 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 169.073673 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1420 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 169.030938 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1419 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 349 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 4.068768 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 4.065903 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 169.073673 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.082556 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.082556 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 169.030938 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.082535 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.082535 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 349 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 186 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 163 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 183 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 166 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.170410 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 4061 # Number of tag accesses -system.cpu.icache.tags.data_accesses 4061 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 19908000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 1420 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1420 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1420 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1420 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1420 # number of overall hits -system.cpu.icache.overall_hits::total 1420 # number of overall hits +system.cpu.icache.tags.tag_accesses 4059 # Number of tag accesses +system.cpu.icache.tags.data_accesses 4059 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 20159000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 1419 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1419 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1419 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1419 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1419 # number of overall hits +system.cpu.icache.overall_hits::total 1419 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 436 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 436 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 436 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 436 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 436 # number of overall misses system.cpu.icache.overall_misses::total 436 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 32169000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 32169000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 32169000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 32169000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 32169000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 32169000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1856 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1856 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1856 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1856 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1856 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1856 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.234914 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.234914 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.234914 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.234914 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.234914 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.234914 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 73782.110092 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 73782.110092 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 73782.110092 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 73782.110092 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 73782.110092 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 73782.110092 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 497 # number of cycles access was blocked +system.cpu.icache.ReadReq_miss_latency::cpu.inst 31654500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 31654500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 31654500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 31654500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 31654500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 31654500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1855 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1855 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1855 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1855 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1855 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1855 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.235040 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.235040 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.235040 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.235040 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.235040 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.235040 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 72602.064220 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 72602.064220 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 72602.064220 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 72602.064220 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 72602.064220 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 72602.064220 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 507 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 99.400000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 101.400000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.ReadReq_mshr_hits::cpu.inst 86 # number of ReadReq MSHR hits system.cpu.icache.ReadReq_mshr_hits::total 86 # number of ReadReq MSHR hits @@ -757,43 +756,43 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 350 system.cpu.icache.demand_mshr_misses::total 350 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 350 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 350 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 26574000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 26574000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 26574000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 26574000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 26574000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 26574000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.188578 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.188578 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.188578 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.188578 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.188578 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.188578 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75925.714286 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75925.714286 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75925.714286 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 75925.714286 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75925.714286 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 75925.714286 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 19908000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 26454000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 26454000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 26454000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 26454000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 26454000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 26454000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.188679 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.188679 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.188679 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.188679 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.188679 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.188679 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75582.857143 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75582.857143 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75582.857143 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 75582.857143 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75582.857143 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 75582.857143 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 20159000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 199.665471 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 231.417144 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 8 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 396 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.020202 # Average number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 443 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.018059 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 167.879354 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 31.786117 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005123 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.000970 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.006093 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 396 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 199 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 197 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012085 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_blocks::cpu.inst 167.835616 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 63.581529 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005122 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.001940 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.007062 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 443 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 202 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 241 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.013519 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 4075 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 4075 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 19908000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 20159000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 6 # number of ReadCleanReq hits system.cpu.l2cache.ReadCleanReq_hits::total 6 # number of ReadCleanReq hits system.cpu.l2cache.ReadSharedReq_hits::cpu.data 2 # number of ReadSharedReq hits @@ -816,18 +815,18 @@ system.cpu.l2cache.demand_misses::total 446 # nu system.cpu.l2cache.overall_misses::cpu.inst 344 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 102 # number of overall misses system.cpu.l2cache.overall_misses::total 446 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3932000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 3932000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 25981000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 25981000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 4326000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 4326000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 25981000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 8258000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 34239000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 25981000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 8258000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 34239000 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4475000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 4475000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 25861000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 25861000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 4379000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 4379000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 25861000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 8854000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 34715000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 25861000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 8854000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 34715000 # number of overall miss cycles system.cpu.l2cache.ReadExReq_accesses::cpu.data 47 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 47 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 350 # number of ReadCleanReq accesses(hits+misses) @@ -852,18 +851,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.982379 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.982857 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.980769 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.982379 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 83659.574468 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 83659.574468 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75526.162791 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75526.162791 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 78654.545455 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 78654.545455 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75526.162791 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 80960.784314 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 76769.058296 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75526.162791 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 80960.784314 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 76769.058296 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 95212.765957 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 95212.765957 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75177.325581 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75177.325581 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 79618.181818 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 79618.181818 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75177.325581 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 86803.921569 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 77836.322870 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75177.325581 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 86803.921569 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 77836.322870 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -882,18 +881,18 @@ system.cpu.l2cache.demand_mshr_misses::total 446 system.cpu.l2cache.overall_mshr_misses::cpu.inst 344 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 102 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 446 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3462000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3462000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 22551000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 22551000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 3796000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 3796000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22551000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7258000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 29809000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22551000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7258000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 29809000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4005000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4005000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 22431000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 22431000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 3849000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 3849000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22431000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7854000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 30285000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22431000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7854000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 30285000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.982857 # mshr miss rate for ReadCleanReq accesses @@ -906,25 +905,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.982379 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.982857 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.980769 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.982379 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 73659.574468 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 73659.574468 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65555.232558 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65555.232558 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 69018.181818 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 69018.181818 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65555.232558 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71156.862745 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66836.322870 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65555.232558 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71156.862745 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66836.322870 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 85212.765957 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 85212.765957 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65206.395349 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65206.395349 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 69981.818182 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 69981.818182 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65206.395349 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 77000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67903.587444 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65206.395349 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 77000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67903.587444 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 454 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 8 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 19908000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 20159000 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 404 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 47 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 47 # Transaction distribution @@ -955,7 +954,13 @@ system.cpu.toL2Bus.respLayer0.occupancy 523500 # La system.cpu.toL2Bus.respLayer0.utilization 2.6 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 153000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 19908000 # Cumulative time (in ticks) in various power states +system.membus.snoop_filter.tot_requests 445 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 20159000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 396 # Transaction distribution system.membus.trans_dist::ReadExReq 47 # Transaction distribution system.membus.trans_dist::ReadExResp 47 # Transaction distribution @@ -977,8 +982,8 @@ system.membus.snoop_fanout::min_value 0 # Re system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 445 # Request fanout histogram system.membus.reqLayer0.occupancy 553500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 2338750 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 11.7 # Layer utilization (%) +system.membus.reqLayer0.utilization 2.7 # Layer utilization (%) +system.membus.respLayer1.occupancy 2340000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 11.6 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/stats.txt index c2dda4058..55872626c 100644 --- a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000003 # Nu sim_ticks 2896000 # Number of ticks simulated final_tick 2896000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 667625 # Simulator instruction rate (inst/s) -host_op_rate 666766 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 332924076 # Simulator tick rate (ticks/s) -host_mem_usage 235336 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host +host_inst_rate 247008 # Simulator instruction rate (inst/s) +host_op_rate 246868 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 123347407 # Simulator tick rate (ticks/s) +host_mem_usage 238692 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host sim_insts 5793 # Number of instructions simulated sim_ops 5793 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -116,6 +116,12 @@ system.cpu.op_class::MemWrite 1046 18.06% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 5793 # Class of executed instruction +system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.pwrStateResidencyTicks::UNDEFINED 2896000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 6754 # Transaction distribution system.membus.trans_dist::ReadResp 6754 # Transaction distribution @@ -130,14 +136,14 @@ system.membus.pkt_size::total 31101 # Cu system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) system.membus.snoop_fanout::samples 7800 # Request fanout histogram -system.membus.snoop_fanout::mean 0.742692 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.437178 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 2007 25.73% 25.73% # Request fanout histogram -system.membus.snoop_fanout::1 5793 74.27% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 7800 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 7800 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt index c6c8dc595..7638ef846 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000003 # Nu sim_ticks 2694500 # Number of ticks simulated final_tick 2694500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 588885 # Simulator instruction rate (inst/s) -host_op_rate 587162 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 296343205 # Simulator tick rate (ticks/s) -host_mem_usage 237088 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host +host_inst_rate 238347 # Simulator instruction rate (inst/s) +host_op_rate 238214 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 120430561 # Simulator tick rate (ticks/s) +host_mem_usage 240180 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host sim_insts 5327 # Number of instructions simulated sim_ops 5327 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -98,6 +98,12 @@ system.cpu.op_class::MemWrite 678 12.63% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 5370 # Class of executed instruction +system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.pwrStateResidencyTicks::UNDEFINED 2694500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 6085 # Transaction distribution system.membus.trans_dist::ReadResp 6085 # Transaction distribution @@ -112,14 +118,14 @@ system.membus.pkt_size::total 31147 # Cu system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) system.membus.snoop_fanout::samples 6758 # Request fanout histogram -system.membus.snoop_fanout::mean 0.794614 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.404013 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 1388 20.54% 20.54% # Request fanout histogram -system.membus.snoop_fanout::1 5370 79.46% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 6758 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 6758 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt index 61bfb723b..9112c70f3 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000031 # Number of seconds simulated -sim_ticks 30526500 # Number of ticks simulated -final_tick 30526500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 30915500 # Number of ticks simulated +final_tick 30915500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 232577 # Simulator instruction rate (inst/s) -host_op_rate 232336 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1330299281 # Simulator tick rate (ticks/s) -host_mem_usage 247080 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host +host_inst_rate 184246 # Simulator instruction rate (inst/s) +host_op_rate 184150 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1068222426 # Simulator tick rate (ticks/s) +host_mem_usage 250688 # Number of bytes of host memory used +host_seconds 0.03 # Real time elapsed on the host sim_insts 5327 # Number of instructions simulated sim_ops 5327 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 30526500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 30915500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 16320 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 8576 # Number of bytes read from this memory system.physmem.bytes_read::total 24896 # Number of bytes read from this memory @@ -22,19 +22,19 @@ system.physmem.bytes_inst_read::total 16320 # Nu system.physmem.num_reads::cpu.inst 255 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 134 # Number of read requests responded to by this memory system.physmem.num_reads::total 389 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 534617464 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 280936236 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 815553699 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 534617464 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 534617464 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 534617464 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 280936236 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 815553699 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 30526500 # Cumulative time (in ticks) in various power states +system.physmem.bw_read::cpu.inst 527890540 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 277401304 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 805291844 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 527890540 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 527890540 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 527890540 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 277401304 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 805291844 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 30915500 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 30526500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 61053 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 30915500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 61831 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 5327 # Number of instructions committed @@ -53,7 +53,7 @@ system.cpu.num_mem_refs 1401 # nu system.cpu.num_load_insts 723 # Number of load instructions system.cpu.num_store_insts 678 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 61052.998000 # Number of busy cycles +system.cpu.num_busy_cycles 61830.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 1121 # Number of branches fetched @@ -92,23 +92,23 @@ system.cpu.op_class::MemWrite 678 12.63% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 5370 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 30526500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 30915500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 81.961543 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 81.942328 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1253 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 135 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 9.281481 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 81.961543 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.020010 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.020010 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 81.942328 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.020005 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.020005 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 135 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 28 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 107 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.032959 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 2911 # Number of tag accesses system.cpu.dcache.tags.data_accesses 2911 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 30526500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 30915500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 661 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 661 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 592 # number of WriteReq hits @@ -125,14 +125,14 @@ system.cpu.dcache.demand_misses::cpu.data 135 # n system.cpu.dcache.demand_misses::total 135 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 135 # number of overall misses system.cpu.dcache.overall_misses::total 135 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 3300000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 3300000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 5022000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 5022000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 8322000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 8322000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 8322000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 8322000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 3353000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 3353000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 5103000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 5103000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 8456000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 8456000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 8456000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 8456000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 715 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 715 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 673 # number of WriteReq accesses(hits+misses) @@ -149,14 +149,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.097262 system.cpu.dcache.demand_miss_rate::total 0.097262 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.097262 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.097262 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 61111.111111 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 61111.111111 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 62000 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 61644.444444 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 61644.444444 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 61644.444444 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 61644.444444 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62092.592593 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 62092.592593 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 63000 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 62637.037037 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 62637.037037 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 62637.037037 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 62637.037037 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -171,14 +171,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 135 system.cpu.dcache.demand_mshr_misses::total 135 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 135 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 135 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3246000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3246000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4941000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4941000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8187000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 8187000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8187000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 8187000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3299000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3299000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5022000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5022000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8321000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 8321000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8321000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 8321000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075524 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075524 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.120357 # mshr miss rate for WriteReq accesses @@ -187,31 +187,31 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.097262 system.cpu.dcache.demand_mshr_miss_rate::total 0.097262 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.097262 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.097262 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 60111.111111 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 60111.111111 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 60644.444444 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 60644.444444 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 60644.444444 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 60644.444444 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 30526500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61092.592593 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61092.592593 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62000 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 61637.037037 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 61637.037037 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61637.037037 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 61637.037037 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 30915500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 116.865384 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 116.844047 # Cycle average of tags in use system.cpu.icache.tags.total_refs 5114 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 257 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 19.898833 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 116.865384 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.057063 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.057063 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 116.844047 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.057053 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.057053 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 257 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 158 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 98 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 159 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.125488 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 10999 # Number of tag accesses system.cpu.icache.tags.data_accesses 10999 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 30526500 # Cumulative time (in ticks) in various power states +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 30915500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 5114 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 5114 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 5114 # number of demand (read+write) hits @@ -224,12 +224,12 @@ system.cpu.icache.demand_misses::cpu.inst 257 # n system.cpu.icache.demand_misses::total 257 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 257 # number of overall misses system.cpu.icache.overall_misses::total 257 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 15838500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 15838500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 15838500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 15838500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 15838500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 15838500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 16093500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 16093500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 16093500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 16093500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 16093500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 16093500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 5371 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 5371 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 5371 # number of demand (read+write) accesses @@ -242,12 +242,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.047850 system.cpu.icache.demand_miss_rate::total 0.047850 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.047850 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.047850 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61628.404669 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 61628.404669 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 61628.404669 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 61628.404669 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 61628.404669 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 61628.404669 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62620.622568 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 62620.622568 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 62620.622568 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 62620.622568 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 62620.622568 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 62620.622568 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -260,43 +260,43 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 257 system.cpu.icache.demand_mshr_misses::total 257 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 257 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 257 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15581500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 15581500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15581500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 15581500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15581500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 15581500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15836500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 15836500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15836500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 15836500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15836500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 15836500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.047850 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.047850 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.047850 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.047850 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.047850 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.047850 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60628.404669 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60628.404669 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60628.404669 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 60628.404669 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60628.404669 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 60628.404669 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 30526500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61620.622568 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61620.622568 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61620.622568 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 61620.622568 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61620.622568 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 61620.622568 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 30915500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 141.950442 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 197.305193 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 3 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 308 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.009740 # Average number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 389 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.007712 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 116.319383 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 25.631059 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003550 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.000782 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.004332 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 308 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 118 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 190 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.009399 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_blocks::cpu.inst 116.297024 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 81.008169 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003549 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.002472 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.006021 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 389 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 124 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 265 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.011871 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 3525 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 3525 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 30526500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 30915500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2 # number of ReadCleanReq hits system.cpu.l2cache.ReadCleanReq_hits::total 2 # number of ReadCleanReq hits system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1 # number of ReadSharedReq hits @@ -319,18 +319,18 @@ system.cpu.l2cache.demand_misses::total 389 # nu system.cpu.l2cache.overall_misses::cpu.inst 255 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 134 # number of overall misses system.cpu.l2cache.overall_misses::total 389 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4819500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 4819500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 15173000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 15173000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 3153500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 3153500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 15173000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7973000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 23146000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 15173000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7973000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 23146000 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4900500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 4900500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 15428000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 15428000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 3206500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 3206500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 15428000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 8107000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 23535000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 15428000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 8107000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 23535000 # number of overall miss cycles system.cpu.l2cache.ReadExReq_accesses::cpu.data 81 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 81 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 257 # number of ReadCleanReq accesses(hits+misses) @@ -355,18 +355,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.992347 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.992218 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.992593 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.992347 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59501.960784 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59501.960784 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59501.960784 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59500 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 59501.285347 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59501.960784 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 59501.285347 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60501.960784 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60501.960784 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60500 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60500 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60501.960784 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60500 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 60501.285347 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60501.960784 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60500 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 60501.285347 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -385,18 +385,18 @@ system.cpu.l2cache.demand_mshr_misses::total 389 system.cpu.l2cache.overall_mshr_misses::cpu.inst 255 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 389 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4009500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4009500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 12623000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 12623000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2623500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2623500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12623000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6633000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 19256000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12623000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6633000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 19256000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4090500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4090500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 12878000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 12878000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2676500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2676500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12878000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6767000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 19645000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12878000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6767000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 19645000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.992218 # mshr miss rate for ReadCleanReq accesses @@ -409,25 +409,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.992347 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.992218 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.992593 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.992347 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49501.960784 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49501.960784 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49501.960784 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49501.285347 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49501.960784 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49501.285347 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50501.960784 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50501.960784 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50501.960784 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50501.285347 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50501.960784 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50501.285347 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 392 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 3 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 30526500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 30915500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 311 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 81 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 81 # Transaction distribution @@ -455,10 +455,16 @@ system.cpu.toL2Bus.snoop_fanout::total 392 # Re system.cpu.toL2Bus.reqLayer0.occupancy 196000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 385500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 1.3 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.utilization 1.2 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 202500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 30526500 # Cumulative time (in ticks) in various power states +system.membus.snoop_filter.tot_requests 389 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 30915500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 308 # Transaction distribution system.membus.trans_dist::ReadExReq 81 # Transaction distribution system.membus.trans_dist::ReadExResp 81 # Transaction distribution @@ -482,6 +488,6 @@ system.membus.snoop_fanout::total 389 # Re system.membus.reqLayer0.occupancy 389500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.3 # Layer utilization (%) system.membus.respLayer1.occupancy 1945000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 6.4 # Layer utilization (%) +system.membus.respLayer1.utilization 6.3 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt index 07049f339..401e565b1 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt @@ -1,43 +1,43 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000021 # Number of seconds simulated -sim_ticks 21273500 # Number of ticks simulated -final_tick 21273500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 21382500 # Number of ticks simulated +final_tick 21382500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 32077 # Simulator instruction rate (inst/s) -host_op_rate 58109 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 126812951 # Simulator tick rate (ticks/s) -host_mem_usage 266996 # Number of bytes of host memory used -host_seconds 0.17 # Real time elapsed on the host +host_inst_rate 21602 # Simulator instruction rate (inst/s) +host_op_rate 39134 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 85845466 # Simulator tick rate (ticks/s) +host_mem_usage 271116 # Number of bytes of host memory used +host_seconds 0.25 # Real time elapsed on the host sim_insts 5380 # Number of instructions simulated sim_ops 9747 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 21273500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 17728 # Number of bytes read from this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 21382500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 17792 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 8896 # Number of bytes read from this memory -system.physmem.bytes_read::total 26624 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 17728 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 17728 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 277 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 26688 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 17792 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 17792 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 278 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 139 # Number of read requests responded to by this memory -system.physmem.num_reads::total 416 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 833337251 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 418172844 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1251510095 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 833337251 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 833337251 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 833337251 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 418172844 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1251510095 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 416 # Number of read requests accepted +system.physmem.num_reads::total 417 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 832082310 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 416041155 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1248123465 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 832082310 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 832082310 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 832082310 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 416041155 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1248123465 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 417 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 416 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 417 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 26624 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 26688 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 26624 # Total read bytes from the system interface side +system.physmem.bytesReadSys 26688 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one @@ -56,7 +56,7 @@ system.physmem.perBankRdBursts::10 64 # Pe system.physmem.perBankRdBursts::11 16 # Per bank write bursts system.physmem.perBankRdBursts::12 2 # Per bank write bursts system.physmem.perBankRdBursts::13 19 # Per bank write bursts -system.physmem.perBankRdBursts::14 6 # Per bank write bursts +system.physmem.perBankRdBursts::14 7 # Per bank write bursts system.physmem.perBankRdBursts::15 17 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts @@ -76,14 +76,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 21151500 # Total gap between requests +system.physmem.totGap 21259500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 416 # Read request sizes (log2) +system.physmem.readPktSize::6 417 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -91,9 +91,9 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 245 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 126 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 39 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 246 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 125 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 40 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 6 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -188,317 +188,317 @@ system.physmem.wrQLenPdf::61 0 # Wh system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see system.physmem.bytesPerActivate::samples 97 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 250.721649 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 162.086023 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 265.276929 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 37 38.14% 38.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 25 25.77% 63.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 18 18.56% 82.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3 3.09% 85.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 248.742268 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 161.877699 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 262.561948 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 36 37.11% 37.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 27 27.84% 64.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 16 16.49% 81.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 4 4.12% 85.57% # Bytes accessed per row activation system.physmem.bytesPerActivate::512-639 2 2.06% 87.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2 2.06% 89.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 4 4.12% 93.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 4 4.12% 91.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 2 2.06% 93.81% # Bytes accessed per row activation system.physmem.bytesPerActivate::896-1023 1 1.03% 94.85% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 5 5.15% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 97 # Bytes accessed per row activation -system.physmem.totQLat 4187000 # Total ticks spent queuing -system.physmem.totMemAccLat 11987000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2080000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10064.90 # Average queueing delay per DRAM burst +system.physmem.totQLat 5040250 # Total ticks spent queuing +system.physmem.totMemAccLat 12859000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2085000 # Total ticks spent in databus transfers +system.physmem.avgQLat 12086.93 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28814.90 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1251.51 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 30836.93 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1248.12 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1251.51 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1248.12 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 9.78 # Data bus utilization in percentage -system.physmem.busUtilRead 9.78 # Data bus utilization in percentage for reads +system.physmem.busUtil 9.75 # Data bus utilization in percentage +system.physmem.busUtilRead 9.75 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.63 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.67 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing system.physmem.readRowHits 309 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 74.28 # Row buffer hit rate for reads +system.physmem.readRowHitRate 74.10 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 50844.95 # Average gap between requests -system.physmem.pageHitRate 74.28 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 181440 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 99000 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 920400 # Energy for read commands per rank (pJ) +system.physmem.avgGap 50982.01 # Average gap between requests +system.physmem.pageHitRate 74.10 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 173880 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 94875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 912600 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) system.physmem_0.actBackEnergy 10792665 # Energy for active background per rank (pJ) system.physmem_0.preBackEnergy 32250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 13042875 # Total energy per rank (pJ) -system.physmem_0.averagePower 823.803884 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 11500 # Time in different power states +system.physmem_0.totalEnergy 13023390 # Total energy per rank (pJ) +system.physmem_0.averagePower 822.573188 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 13750 # Time in different power states system.physmem_0.memoryStateTime::REF 520000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_0.memoryStateTime::ACT 15314750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.physmem_1.actEnergy 415800 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 226875 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1521000 # Energy for read commands per rank (pJ) +system.physmem_1.readEnergy 1497600 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 10696905 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 116250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 13993950 # Total energy per rank (pJ) -system.physmem_1.averagePower 883.874941 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 262750 # Time in different power states +system.physmem_1.actBackEnergy 10696050 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 117000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 13970445 # Total energy per rank (pJ) +system.physmem_1.averagePower 882.390336 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 103000 # Time in different power states system.physmem_1.memoryStateTime::REF 520000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 15224250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 15223250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 21273500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 3510 # Number of BP lookups -system.cpu.branchPred.condPredicted 3510 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 564 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 2934 # Number of BTB lookups +system.pwrStateResidencyTicks::UNDEFINED 21382500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 3511 # Number of BP lookups +system.cpu.branchPred.condPredicted 3511 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 567 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 2933 # Number of BTB lookups system.cpu.branchPred.BTBHits 0 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 413 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 93 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 2934 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 493 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 2441 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 404 # Number of mispredicted indirect branches. +system.cpu.branchPred.usedRAS 414 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 94 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 2933 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 496 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 2437 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 406 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 21273500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 21382500 # Cumulative time (in ticks) in various power states system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 21273500 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 21273500 # Cumulative time (in ticks) in various power states +system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 21382500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 21382500 # Cumulative time (in ticks) in various power states system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 21273500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 42548 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 21382500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 42766 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 11447 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 15916 # Number of instructions fetch has processed -system.cpu.fetch.Branches 3510 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 906 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 9652 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1329 # Number of cycles fetch has spent squashing +system.cpu.fetch.icacheStallCycles 11494 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 15919 # Number of instructions fetch has processed +system.cpu.fetch.Branches 3511 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 910 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 9718 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1335 # Number of cycles fetch has spent squashing system.cpu.fetch.MiscStallCycles 93 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1405 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingTrapStallCycles 1414 # Number of stall cycles due to pending traps system.cpu.fetch.PendingQuiesceStallCycles 15 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 26 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 2036 # Number of cache lines fetched +system.cpu.fetch.IcacheWaitRetryStallCycles 30 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 2042 # Number of cache lines fetched system.cpu.fetch.IcacheSquashes 273 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 23302 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.230495 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.752458 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::samples 23431 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.223593 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.745730 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 19034 81.68% 81.68% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 165 0.71% 82.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 157 0.67% 83.07% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 234 1.00% 84.07% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 217 0.93% 85.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 212 0.91% 85.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 264 1.13% 87.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 172 0.74% 87.78% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 2847 12.22% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 19161 81.78% 81.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 166 0.71% 82.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 156 0.67% 83.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 235 1.00% 84.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 218 0.93% 85.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 215 0.92% 86.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 266 1.14% 87.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 168 0.72% 87.85% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 2846 12.15% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 23302 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.082495 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.374072 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 11533 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 7244 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 3404 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 457 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 664 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 26617 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 664 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 11798 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 1942 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 1135 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 3557 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 4206 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 25098 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 12 # Number of times rename has blocked due to ROB full +system.cpu.fetch.rateDist::total 23431 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.082098 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.372235 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 11586 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 7313 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 3407 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 458 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 667 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 26631 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 667 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 11849 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 2059 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 1032 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 3561 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 4263 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 25112 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 14 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 80 # Number of times rename has blocked due to IQ full -system.cpu.rename.SQFullEvents 4073 # Number of times rename has blocked due to SQ full +system.cpu.rename.SQFullEvents 4127 # Number of times rename has blocked due to SQ full system.cpu.rename.RenamedOperands 28145 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 61205 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 35038 # Number of integer rename lookups +system.cpu.rename.RenameLookups 61260 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 35084 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 4 # Number of floating rename lookups system.cpu.rename.CommittedMaps 11063 # Number of HB maps that are committed system.cpu.rename.UndoneMaps 17082 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 25 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 25 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 1412 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2736 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1550 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 10 # Number of conflicting loads. +system.cpu.rename.serializingInsts 24 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 24 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 1417 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2745 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1552 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 11 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 7 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 21864 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 23 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 18142 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 143 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 12140 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 16726 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 11 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 23302 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.778560 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.752623 # Number of insts issued each cycle +system.cpu.iq.iqInstsAdded 21890 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 22 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 18162 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 138 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 12165 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 16733 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 10 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 23431 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.775127 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.748484 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 18136 77.83% 77.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1211 5.20% 83.03% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 861 3.69% 86.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 568 2.44% 89.16% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 833 3.57% 92.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 596 2.56% 95.29% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 620 2.66% 97.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 343 1.47% 99.42% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 134 0.58% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 18255 77.91% 77.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1208 5.16% 83.07% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 874 3.73% 86.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 566 2.42% 89.21% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 836 3.57% 92.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 600 2.56% 95.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 613 2.62% 97.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 346 1.48% 99.43% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 133 0.57% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 23302 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 23431 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 211 76.17% 76.17% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 76.17% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 76.17% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 76.17% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 76.17% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 76.17% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 76.17% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 76.17% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 76.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 76.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 76.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 76.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 76.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 76.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 76.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 76.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 76.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 76.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 76.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 76.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 76.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 76.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 76.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 76.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 76.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 76.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 76.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 76.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 76.17% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 50 18.05% 94.22% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 16 5.78% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 213 76.07% 76.07% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 76.07% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 76.07% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 76.07% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 76.07% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 76.07% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 76.07% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 76.07% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 76.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 76.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 76.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 76.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 76.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 76.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 76.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 76.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 76.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 76.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 76.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 76.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 76.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 76.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 76.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 76.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 76.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 76.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 76.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 76.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 76.07% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 51 18.21% 94.29% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 16 5.71% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 14465 79.73% 79.74% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 6 0.03% 79.78% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 7 0.04% 79.81% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 79.81% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 79.81% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 79.81% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 79.81% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 79.81% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 79.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 79.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 79.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 79.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 79.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 79.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 79.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 79.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 79.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 79.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 79.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 79.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 79.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 79.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 79.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 79.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 79.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 79.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 79.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 79.81% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 79.81% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2325 12.82% 92.63% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1337 7.37% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 14483 79.74% 79.75% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 6 0.03% 79.79% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 7 0.04% 79.83% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 79.83% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 79.83% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 79.83% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 79.83% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 79.83% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 79.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 79.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 79.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 79.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 79.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 79.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 79.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 79.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 79.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 79.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 79.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 79.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 79.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 79.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 79.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 79.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 79.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 79.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 79.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 79.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 79.83% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2327 12.81% 92.64% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1337 7.36% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 18142 # Type of FU issued -system.cpu.iq.rate 0.426389 # Inst issue rate -system.cpu.iq.fu_busy_cnt 277 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.015268 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 59998 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 34032 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 16436 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 18162 # Type of FU issued +system.cpu.iq.rate 0.424683 # Inst issue rate +system.cpu.iq.fu_busy_cnt 280 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.015417 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 60165 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 34082 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 16453 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 8 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 8 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 4 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 18413 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 18436 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 4 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 190 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 200 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1683 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 11 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.squashedLoads 1692 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 9 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 13 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 615 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 617 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 9 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 664 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1478 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 139 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 21887 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 667 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1486 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 141 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 21912 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 9 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2736 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1550 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 23 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispLoadInsts 2745 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1552 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 22 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 138 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 140 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 13 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 119 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 682 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 801 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 17060 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2081 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1082 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 120 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 685 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 805 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 17078 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2088 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1084 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 3326 # number of memory reference insts executed -system.cpu.iew.exec_branches 1722 # Number of branches executed +system.cpu.iew.exec_refs 3333 # number of memory reference insts executed +system.cpu.iew.exec_branches 1727 # Number of branches executed system.cpu.iew.exec_stores 1245 # Number of stores executed -system.cpu.iew.exec_rate 0.400959 # Inst execution rate -system.cpu.iew.wb_sent 16760 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 16440 # cumulative count of insts written-back -system.cpu.iew.wb_producers 11045 # num instructions producing a value -system.cpu.iew.wb_consumers 17238 # num instructions consuming a value -system.cpu.iew.wb_rate 0.386387 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.640736 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 12139 # The number of squashed insts skipped by commit +system.cpu.iew.exec_rate 0.399336 # Inst execution rate +system.cpu.iew.wb_sent 16776 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 16457 # cumulative count of insts written-back +system.cpu.iew.wb_producers 11050 # num instructions producing a value +system.cpu.iew.wb_consumers 17247 # num instructions consuming a value +system.cpu.iew.wb_rate 0.384815 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.640691 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 12164 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 12 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 652 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 21245 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.458790 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.350767 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 655 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 21365 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.456213 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.347578 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 17995 84.70% 84.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 991 4.66% 89.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 576 2.71% 92.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 726 3.42% 95.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 383 1.80% 97.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 128 0.60% 97.90% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 121 0.57% 98.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 72 0.34% 98.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 253 1.19% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 18118 84.80% 84.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 989 4.63% 89.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 572 2.68% 92.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 729 3.41% 95.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 380 1.78% 97.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 132 0.62% 97.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 120 0.56% 98.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 73 0.34% 98.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 252 1.18% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 21245 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 21365 # Number of insts commited each cycle system.cpu.commit.committedInsts 5380 # Number of instructions committed system.cpu.commit.committedOps 9747 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -544,101 +544,101 @@ system.cpu.commit.op_class_0::MemWrite 935 9.59% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 9747 # Class of committed instruction -system.cpu.commit.bw_lim_events 253 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 42878 # The number of ROB reads -system.cpu.rob.rob_writes 45859 # The number of ROB writes -system.cpu.timesIdled 160 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 19246 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 252 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 43024 # The number of ROB reads +system.cpu.rob.rob_writes 45919 # The number of ROB writes +system.cpu.timesIdled 159 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 19335 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5380 # Number of Instructions Simulated system.cpu.committedOps 9747 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 7.908550 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.908550 # CPI: Total CPI of All Threads -system.cpu.ipc 0.126445 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.126445 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 21687 # number of integer regfile reads -system.cpu.int_regfile_writes 13280 # number of integer regfile writes +system.cpu.cpi 7.949071 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.949071 # CPI: Total CPI of All Threads +system.cpu.ipc 0.125801 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.125801 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 21733 # number of integer regfile reads +system.cpu.int_regfile_writes 13291 # number of integer regfile writes system.cpu.fp_regfile_reads 4 # number of floating regfile reads -system.cpu.cc_regfile_reads 8296 # number of cc regfile reads +system.cpu.cc_regfile_reads 8307 # number of cc regfile reads system.cpu.cc_regfile_writes 5092 # number of cc regfile writes -system.cpu.misc_regfile_reads 7660 # number of misc regfile reads +system.cpu.misc_regfile_reads 7667 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 21273500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 21382500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 81.534494 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 2583 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 81.328051 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 2579 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 139 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 18.582734 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 18.553957 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 81.534494 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.019906 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.019906 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 81.328051 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.019855 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.019855 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 139 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 92 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.033936 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 5685 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 5685 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 21273500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 1723 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1723 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 5679 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 5679 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 21382500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 1719 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1719 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 860 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 860 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2583 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2583 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2583 # number of overall hits -system.cpu.dcache.overall_hits::total 2583 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 115 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 115 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 2579 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2579 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2579 # number of overall hits +system.cpu.dcache.overall_hits::total 2579 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 116 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 116 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 75 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 75 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 190 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 190 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 190 # number of overall misses -system.cpu.dcache.overall_misses::total 190 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 9038500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 9038500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 6225500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 6225500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 15264000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 15264000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 15264000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 15264000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1838 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1838 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 191 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 191 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 191 # number of overall misses +system.cpu.dcache.overall_misses::total 191 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 9465500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 9465500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 6317000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 6317000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 15782500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 15782500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 15782500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 15782500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1835 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1835 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 935 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 935 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2773 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2773 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2773 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2773 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.062568 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.062568 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2770 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2770 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2770 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2770 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.063215 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.063215 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.080214 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.080214 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.068518 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.068518 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.068518 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.068518 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 78595.652174 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 78595.652174 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 83006.666667 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 83006.666667 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 80336.842105 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 80336.842105 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 80336.842105 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 80336.842105 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 122 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.068953 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.068953 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.068953 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.068953 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 81599.137931 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 81599.137931 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 84226.666667 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 84226.666667 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 82630.890052 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 82630.890052 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 82630.890052 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 82630.890052 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 124 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 40.666667 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 41.333333 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 51 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 51 # number of ReadReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 51 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 51 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 51 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 51 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 52 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 52 # number of ReadReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 52 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 52 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 52 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 52 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 64 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 64 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 75 # number of WriteReq MSHR misses @@ -647,88 +647,88 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 139 system.cpu.dcache.demand_mshr_misses::total 139 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 139 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 139 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5459500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5459500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6150500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 6150500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11610000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 11610000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11610000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 11610000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.034820 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.034820 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5739000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5739000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6242000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 6242000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11981000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 11981000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11981000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 11981000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.034877 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.034877 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.080214 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.080214 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.050126 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.050126 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.050126 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.050126 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 85304.687500 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 85304.687500 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 82006.666667 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 82006.666667 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 83525.179856 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 83525.179856 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 83525.179856 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 83525.179856 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 21273500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.050181 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.050181 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.050181 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.050181 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 89671.875000 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 89671.875000 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 83226.666667 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 83226.666667 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 86194.244604 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 86194.244604 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 86194.244604 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 86194.244604 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 21382500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 130.801873 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1651 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 278 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 5.938849 # Average number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 130.610950 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1656 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 279 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 5.935484 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 130.801873 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.063868 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.063868 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 278 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 147 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 130.610950 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.063775 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.063775 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 279 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 148 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 131 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.135742 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 4350 # Number of tag accesses -system.cpu.icache.tags.data_accesses 4350 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 21273500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 1651 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1651 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1651 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1651 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1651 # number of overall hits -system.cpu.icache.overall_hits::total 1651 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 385 # 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number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 2036 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 2036 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 2036 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 2036 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 2036 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.189096 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.189096 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.189096 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.189096 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.189096 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.189096 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 74068.831169 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 74068.831169 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 74068.831169 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 74068.831169 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 74068.831169 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 74068.831169 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 142 # number of cycles access was blocked +system.cpu.icache.tags.occ_task_id_percent::1024 0.136230 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 4363 # Number of tag accesses +system.cpu.icache.tags.data_accesses 4363 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 21382500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 1656 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1656 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1656 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1656 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1656 # number of overall hits +system.cpu.icache.overall_hits::total 1656 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 386 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 386 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 386 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 386 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 386 # number of overall misses +system.cpu.icache.overall_misses::total 386 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 29282500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 29282500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 29282500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 29282500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 29282500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 29282500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 2042 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 2042 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 2042 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 2042 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 2042 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 2042 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.189030 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.189030 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.189030 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.189030 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.189030 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.189030 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75861.398964 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 75861.398964 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 75861.398964 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 75861.398964 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 75861.398964 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 75861.398964 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 121 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 47.333333 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 40.333333 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.ReadReq_mshr_hits::cpu.inst 107 # number of ReadReq MSHR hits system.cpu.icache.ReadReq_mshr_hits::total 107 # number of ReadReq MSHR hits @@ -736,49 +736,49 @@ system.cpu.icache.demand_mshr_hits::cpu.inst 107 system.cpu.icache.demand_mshr_hits::total 107 # number of demand (read+write) MSHR hits system.cpu.icache.overall_mshr_hits::cpu.inst 107 # number of overall MSHR hits system.cpu.icache.overall_mshr_hits::total 107 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 278 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 278 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 278 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 278 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 278 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 278 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 21868500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 21868500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 21868500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 21868500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 21868500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 21868500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.136542 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.136542 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.136542 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.136542 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.136542 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.136542 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 78663.669065 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 78663.669065 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 78663.669065 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 78663.669065 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 78663.669065 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 78663.669065 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 21273500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 279 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 279 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 279 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 279 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 279 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 279 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22839500 # 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mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.136631 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 81862.007168 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 81862.007168 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 81862.007168 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 81862.007168 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 81862.007168 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 81862.007168 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 21382500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 163.058861 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 212.046379 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 341 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.002933 # Average number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 417 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.002398 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 130.841735 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 32.217126 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003993 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.000983 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.004976 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 341 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 179 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 162 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.010406 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 3752 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 3752 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 21273500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.occ_blocks::cpu.inst 130.650071 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 81.396308 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003987 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.002484 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.006471 # 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number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 279 # number of ReadCleanReq accesses(hits+misses) system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 64 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.ReadSharedReq_accesses::total 64 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 278 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 279 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 139 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 417 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 278 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::total 418 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 279 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 139 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 417 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 418 # number of overall (read+write) accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.996403 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.996403 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.996416 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.996416 # miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996403 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996416 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.997602 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996403 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::total 0.997608 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996416 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.997602 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80500 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80500 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 77398.916968 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 77398.916968 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 83789.062500 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 83789.062500 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77398.916968 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 82014.388489 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 78941.105769 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77398.916968 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 82014.388489 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 78941.105769 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.997608 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81720 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81720 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 80607.913669 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 80607.913669 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 88156.250000 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 88156.250000 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80607.913669 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 84683.453237 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 81966.426859 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80607.913669 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 84683.453237 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 81966.426859 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -853,115 +853,121 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 75 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 75 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 277 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 277 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 278 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 278 # number of ReadCleanReq MSHR misses system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 64 # number of ReadSharedReq MSHR misses system.cpu.l2cache.ReadSharedReq_mshr_misses::total 64 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 277 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 278 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 139 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 416 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 277 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 417 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 278 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 139 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 416 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5287500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5287500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 18669500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 18669500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4722500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4722500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18669500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10010000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 28679500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 18669500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10010000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 28679500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::total 417 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5379000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5379000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 19629000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 19629000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5002000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 5002000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19629000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10381000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 30010000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19629000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10381000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 30010000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.996403 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.996403 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.996416 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.996416 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996403 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996416 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.997602 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996403 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.997608 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996416 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.997602 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67398.916968 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67398.916968 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73789.062500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73789.062500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67398.916968 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72014.388489 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68941.105769 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67398.916968 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72014.388489 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68941.105769 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 417 # Total number of requests made to the snoop filter. +system.cpu.l2cache.overall_mshr_miss_rate::total 0.997608 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71720 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71720 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70607.913669 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70607.913669 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 78156.250000 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 78156.250000 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70607.913669 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 74683.453237 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71966.426859 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70607.913669 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 74683.453237 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71966.426859 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 418 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 21273500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 342 # Transaction distribution +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 21382500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 343 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 75 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 75 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 278 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 279 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 64 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 556 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 558 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 278 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 834 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17792 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 836 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17856 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8896 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 26688 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 26752 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 417 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.002398 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.048970 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 418 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.002392 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.048912 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 416 99.76% 99.76% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 417 99.76% 99.76% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 1 0.24% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 417 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 208500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 418 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 209000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 417000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 418500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 2.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 208500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 21273500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 341 # Transaction distribution +system.membus.snoop_filter.tot_requests 417 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 21382500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 342 # Transaction distribution system.membus.trans_dist::ReadExReq 75 # Transaction distribution system.membus.trans_dist::ReadExResp 75 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 341 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 832 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 832 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 832 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26624 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 26624 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 26624 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 342 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 834 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 834 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 834 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26688 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 26688 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 26688 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 416 # Request fanout histogram +system.membus.snoop_fanout::samples 417 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 416 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 417 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 416 # Request fanout histogram -system.membus.reqLayer0.occupancy 502000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 417 # Request fanout histogram +system.membus.reqLayer0.occupancy 503500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.4 # Layer utilization (%) -system.membus.respLayer1.occupancy 2222250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2228500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 10.4 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt index 563e9e0f5..f34005614 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000006 # Nu sim_ticks 5615000 # Number of ticks simulated final_tick 5615000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 290053 # Simulator instruction rate (inst/s) -host_op_rate 524918 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 302085986 # Simulator tick rate (ticks/s) -host_mem_usage 255208 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host +host_inst_rate 127315 # Simulator instruction rate (inst/s) +host_op_rate 230565 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 132772406 # Simulator tick rate (ticks/s) +host_mem_usage 258816 # Number of bytes of host memory used +host_seconds 0.04 # Real time elapsed on the host sim_insts 5381 # Number of instructions simulated sim_ops 9748 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -104,6 +104,12 @@ system.cpu.op_class::MemWrite 935 9.59% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 9748 # Class of executed instruction +system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.pwrStateResidencyTicks::UNDEFINED 5615000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 7917 # Transaction distribution system.membus.trans_dist::ReadResp 7917 # Transaction distribution @@ -122,14 +128,14 @@ system.membus.pkt_size::total 69090 # Cu system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) system.membus.snoop_fanout::samples 8852 # Request fanout histogram -system.membus.snoop_fanout::mean 0.775418 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.417330 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 1988 22.46% 22.46% # Request fanout histogram -system.membus.snoop_fanout::1 6864 77.54% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 8852 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 8852 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt index 9047321d1..afc430970 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000031 # Number of seconds simulated -sim_ticks 30886500 # Number of ticks simulated -final_tick 30886500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 31247500 # Number of ticks simulated +final_tick 31247500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 211795 # Simulator instruction rate (inst/s) -host_op_rate 383429 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1214135841 # Simulator tick rate (ticks/s) -host_mem_usage 263924 # Number of bytes of host memory used -host_seconds 0.03 # Real time elapsed on the host +host_inst_rate 85405 # Simulator instruction rate (inst/s) +host_op_rate 154687 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 495766938 # Simulator tick rate (ticks/s) +host_mem_usage 269328 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host sim_insts 5381 # Number of instructions simulated sim_ops 9748 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 30886500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 31247500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 14528 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 8576 # Number of bytes read from this memory system.physmem.bytes_read::total 23104 # Number of bytes read from this memory @@ -22,23 +22,23 @@ system.physmem.bytes_inst_read::total 14528 # Nu system.physmem.num_reads::cpu.inst 227 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 134 # Number of read requests responded to by this memory system.physmem.num_reads::total 361 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 470367313 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 277661762 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 748029074 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 470367313 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 470367313 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 470367313 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 277661762 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 748029074 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 30886500 # Cumulative time (in ticks) in various power states +system.physmem.bw_read::cpu.inst 464933195 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 274453956 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 739387151 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 464933195 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 464933195 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 464933195 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 274453956 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 739387151 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 31247500 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 30886500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 31247500 # Cumulative time (in ticks) in various power states system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 30886500 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 30886500 # Cumulative time (in ticks) in various power states +system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 31247500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 31247500 # Cumulative time (in ticks) in various power states system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 30886500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 61773 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 31247500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 62495 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 5381 # Number of instructions committed @@ -59,7 +59,7 @@ system.cpu.num_mem_refs 1988 # nu system.cpu.num_load_insts 1053 # Number of load instructions system.cpu.num_store_insts 935 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 61772.998000 # Number of busy cycles +system.cpu.num_busy_cycles 62494.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 1208 # Number of branches fetched @@ -98,23 +98,23 @@ system.cpu.op_class::MemWrite 935 9.59% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 9748 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 30886500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 31247500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 80.558239 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 80.527852 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1854 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 134 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 13.835821 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 80.558239 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.019668 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.019668 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 80.527852 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.019660 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.019660 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 134 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 103 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.032715 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 4110 # Number of tag accesses system.cpu.dcache.tags.data_accesses 4110 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 30886500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 31247500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 998 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 998 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 856 # number of WriteReq hits @@ -131,14 +131,14 @@ system.cpu.dcache.demand_misses::cpu.data 134 # n system.cpu.dcache.demand_misses::total 134 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 134 # number of overall misses system.cpu.dcache.overall_misses::total 134 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 3410000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 3410000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 4898000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 4898000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 8308000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 8308000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 8308000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 8308000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 3465000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 3465000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4977000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4977000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 8442000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 8442000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 8442000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 8442000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1053 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1053 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 935 # number of WriteReq accesses(hits+misses) @@ -155,14 +155,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.067404 system.cpu.dcache.demand_miss_rate::total 0.067404 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.067404 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.067404 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62000 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 62000 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 62000 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 62000 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 62000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 62000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 62000 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 63000 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 63000 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 63000 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 63000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 63000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 63000 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -177,14 +177,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 134 system.cpu.dcache.demand_mshr_misses::total 134 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 134 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3355000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3355000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4819000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4819000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8174000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 8174000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8174000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 8174000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3410000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3410000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4898000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4898000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8308000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 8308000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8308000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 8308000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.052232 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.052232 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084492 # mshr miss rate for WriteReq accesses @@ -193,31 +193,31 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.067404 system.cpu.dcache.demand_mshr_miss_rate::total 0.067404 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.067404 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.067404 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61000 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61000 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 30886500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 62000 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 62000 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62000 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 62000 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 62000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 62000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 62000 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 31247500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 105.267613 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 105.231814 # Cycle average of tags in use system.cpu.icache.tags.total_refs 6636 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 228 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 29.105263 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 105.267613 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.051400 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.051400 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 105.231814 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.051383 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.051383 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 228 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 86 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 142 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 84 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 144 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.111328 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 13956 # Number of tag accesses system.cpu.icache.tags.data_accesses 13956 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 30886500 # Cumulative time (in ticks) in various power states +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 31247500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 6636 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 6636 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 6636 # number of demand (read+write) hits @@ -230,12 +230,12 @@ system.cpu.icache.demand_misses::cpu.inst 228 # n system.cpu.icache.demand_misses::total 228 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 228 # number of overall misses system.cpu.icache.overall_misses::total 228 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 14088500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 14088500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 14088500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 14088500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14088500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14088500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 14315500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 14315500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 14315500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 14315500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 14315500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 14315500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 6864 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 6864 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 6864 # number of demand (read+write) accesses @@ -248,12 +248,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.033217 system.cpu.icache.demand_miss_rate::total 0.033217 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.033217 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.033217 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61791.666667 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 61791.666667 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 61791.666667 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 61791.666667 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 61791.666667 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 61791.666667 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62787.280702 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 62787.280702 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 62787.280702 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 62787.280702 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 62787.280702 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 62787.280702 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -266,43 +266,43 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 228 system.cpu.icache.demand_mshr_misses::total 228 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 228 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 228 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13860500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 13860500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13860500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 13860500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13860500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 13860500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14087500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 14087500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14087500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 14087500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14087500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 14087500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.033217 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.033217 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.033217 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.033217 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.033217 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.033217 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60791.666667 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60791.666667 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60791.666667 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 60791.666667 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60791.666667 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 60791.666667 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 30886500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61787.280702 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61787.280702 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61787.280702 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 61787.280702 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61787.280702 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 61787.280702 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 31247500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 133.672095 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 185.792229 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 282 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.003546 # Average number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 361 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.002770 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.256135 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 28.415959 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003212 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.000867 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.004079 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 282 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 178 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.008606 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.219349 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 80.572880 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003211 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.002459 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.005670 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 361 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 114 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 247 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.011017 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 3257 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 3257 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 30886500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 31247500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1 # number of ReadCleanReq hits system.cpu.l2cache.ReadCleanReq_hits::total 1 # number of ReadCleanReq hits system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits @@ -321,18 +321,18 @@ system.cpu.l2cache.demand_misses::total 361 # nu system.cpu.l2cache.overall_misses::cpu.inst 227 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 134 # number of overall misses system.cpu.l2cache.overall_misses::total 361 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4700500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 4700500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 13507000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 13507000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 3272500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 3272500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 13507000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7973000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 21480000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 13507000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7973000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 21480000 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4779500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 4779500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 13734000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 13734000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 3327500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 3327500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 13734000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 8107000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 21841000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 13734000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 8107000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 21841000 # number of overall miss cycles system.cpu.l2cache.ReadExReq_accesses::cpu.data 79 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 79 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 228 # number of ReadCleanReq accesses(hits+misses) @@ -357,18 +357,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.997238 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.995614 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.997238 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59502.202643 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59502.202643 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59502.202643 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59500 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 59501.385042 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59502.202643 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 59501.385042 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60502.202643 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60502.202643 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60500 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60500 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60502.202643 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60500 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 60501.385042 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60502.202643 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60500 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 60501.385042 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -387,18 +387,18 @@ system.cpu.l2cache.demand_mshr_misses::total 361 system.cpu.l2cache.overall_mshr_misses::cpu.inst 227 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 361 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3910500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3910500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 11237000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 11237000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2722500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2722500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11237000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6633000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 17870000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11237000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6633000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 17870000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3989500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3989500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 11464000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 11464000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2777500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2777500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11464000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6767000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 18231000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11464000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6767000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 18231000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.995614 # mshr miss rate for ReadCleanReq accesses @@ -411,25 +411,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.997238 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.995614 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.997238 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49502.202643 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49502.202643 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49502.202643 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49501.385042 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49502.202643 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49501.385042 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50502.202643 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50502.202643 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50502.202643 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50501.385042 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50502.202643 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50501.385042 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 362 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 30886500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 31247500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 283 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 79 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 79 # Transaction distribution @@ -459,8 +459,14 @@ system.cpu.toL2Bus.reqLayer0.utilization 0.6 # La system.cpu.toL2Bus.respLayer0.occupancy 342000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 1.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 201000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 30886500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.respLayer1.utilization 0.6 # Layer utilization (%) +system.membus.snoop_filter.tot_requests 361 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 31247500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 282 # Transaction distribution system.membus.trans_dist::ReadExReq 79 # Transaction distribution system.membus.trans_dist::ReadExResp 79 # Transaction distribution diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/stats.txt b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/stats.txt index 561952189..ad56ff040 100644 --- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/stats.txt +++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/stats.txt @@ -1,52 +1,52 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000026 # Number of seconds simulated -sim_ticks 25580500 # Number of ticks simulated -final_tick 25580500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 25607000 # Number of ticks simulated +final_tick 25607000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 123264 # Simulator instruction rate (inst/s) -host_op_rate 123250 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 246864911 # Simulator tick rate (ticks/s) -host_mem_usage 250880 # Number of bytes of host memory used -host_seconds 0.10 # Real time elapsed on the host +host_inst_rate 110915 # Simulator instruction rate (inst/s) +host_op_rate 110902 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 222369986 # Simulator tick rate (ticks/s) +host_mem_usage 254744 # Number of bytes of host memory used +host_seconds 0.12 # Real time elapsed on the host sim_insts 12770 # Number of instructions simulated sim_ops 12770 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 25580500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 39680 # Number of bytes read from this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 25607000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 39936 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 21824 # Number of bytes read from this memory -system.physmem.bytes_read::total 61504 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 39680 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 39680 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 620 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 61760 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 39936 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 39936 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 624 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 341 # Number of read requests responded to by this memory -system.physmem.num_reads::total 961 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1551181564 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 853149860 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2404331424 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1551181564 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1551181564 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1551181564 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 853149860 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2404331424 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 962 # Number of read requests accepted +system.physmem.num_reads::total 965 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1559573554 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 852266958 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2411840512 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1559573554 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1559573554 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1559573554 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 852266958 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2411840512 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 966 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 962 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 966 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 61568 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 61824 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 61568 # Total read bytes from the system interface side +system.physmem.bytesReadSys 61824 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 83 # Per bank write bursts +system.physmem.perBankRdBursts::0 84 # Per bank write bursts system.physmem.perBankRdBursts::1 150 # Per bank write bursts -system.physmem.perBankRdBursts::2 78 # Per bank write bursts -system.physmem.perBankRdBursts::3 59 # Per bank write bursts -system.physmem.perBankRdBursts::4 86 # Per bank write bursts +system.physmem.perBankRdBursts::2 77 # Per bank write bursts +system.physmem.perBankRdBursts::3 58 # Per bank write bursts +system.physmem.perBankRdBursts::4 90 # Per bank write bursts system.physmem.perBankRdBursts::5 46 # Per bank write bursts system.physmem.perBankRdBursts::6 32 # Per bank write bursts system.physmem.perBankRdBursts::7 50 # Per bank write bursts @@ -57,7 +57,7 @@ system.physmem.perBankRdBursts::11 34 # Pe system.physmem.perBankRdBursts::12 15 # Per bank write bursts system.physmem.perBankRdBursts::13 120 # Per bank write bursts system.physmem.perBankRdBursts::14 67 # Per bank write bursts -system.physmem.perBankRdBursts::15 36 # Per bank write bursts +system.physmem.perBankRdBursts::15 37 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts system.physmem.perBankWrBursts::2 0 # Per bank write bursts @@ -76,14 +76,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 25549500 # Total gap between requests +system.physmem.totGap 25577000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 962 # Read request sizes (log2) +system.physmem.readPktSize::6 966 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -91,14 +91,14 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 350 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 315 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 188 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 80 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 351 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 323 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 171 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 89 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 23 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 6 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 7 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see @@ -187,105 +187,105 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 209 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 281.722488 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 176.924618 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 290.527007 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 69 33.01% 33.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 64 30.62% 63.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 20 9.57% 73.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 12 5.74% 78.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 11 5.26% 84.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 8 3.83% 88.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 9 4.31% 92.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 4 1.91% 94.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 12 5.74% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 209 # Bytes accessed per row activation -system.physmem.totQLat 12704750 # Total ticks spent queuing -system.physmem.totMemAccLat 30742250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 4810000 # Total ticks spent in databus transfers -system.physmem.avgQLat 13206.60 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 211 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 278.748815 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 172.887192 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 291.495109 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 76 36.02% 36.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 57 27.01% 63.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 23 10.90% 73.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 12 5.69% 79.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 8 3.79% 83.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 11 5.21% 88.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 6 2.84% 91.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 6 2.84% 94.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 12 5.69% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 211 # Bytes accessed per row activation +system.physmem.totQLat 14120500 # Total ticks spent queuing +system.physmem.totMemAccLat 32233000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 4830000 # Total ticks spent in databus transfers +system.physmem.avgQLat 14617.49 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 31956.60 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 2406.83 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 33367.49 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2414.34 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 2406.83 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 2414.34 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 18.80 # Data bus utilization in percentage -system.physmem.busUtilRead 18.80 # Data bus utilization in percentage for reads +system.physmem.busUtil 18.86 # Data bus utilization in percentage +system.physmem.busUtilRead 18.86 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 2.38 # Average read queue length when enqueuing +system.physmem.avgRdQLen 2.46 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 743 # Number of row buffer hits during reads +system.physmem.readRowHits 745 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 77.23 # Row buffer hit rate for reads +system.physmem.readRowHitRate 77.12 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 26558.73 # Average gap between requests -system.physmem.pageHitRate 77.23 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 824040 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 449625 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 4453800 # Energy for read commands per rank (pJ) +system.physmem.avgGap 26477.23 # Average gap between requests +system.physmem.pageHitRate 77.12 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 861840 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 470250 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 4477200 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ) system.physmem_0.actBackEnergy 16092810 # Energy for active background per rank (pJ) system.physmem_0.preBackEnergy 54750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 23400705 # Total energy per rank (pJ) -system.physmem_0.averagePower 990.768140 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 694500 # Time in different power states +system.physmem_0.totalEnergy 23482530 # Total energy per rank (pJ) +system.physmem_0.averagePower 994.232548 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 763000 # Time in different power states system.physmem_0.memoryStateTime::REF 780000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_0.memoryStateTime::ACT 22830000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 733320 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 400125 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 2683200 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 703080 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 383625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 2628600 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 15873930 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 246750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 21463005 # Total energy per rank (pJ) -system.physmem_1.averagePower 908.727388 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 326750 # Time in different power states +system.physmem_1.actBackEnergy 15488325 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 585000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 21314310 # Total energy per rank (pJ) +system.physmem_1.averagePower 902.431754 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 878500 # Time in different power states system.physmem_1.memoryStateTime::REF 780000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 22525750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 21974000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 25580500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 4883 # Number of BP lookups -system.cpu.branchPred.condPredicted 2924 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 790 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 3812 # Number of BTB lookups -system.cpu.branchPred.BTBHits 1143 # Number of BTB hits +system.pwrStateResidencyTicks::UNDEFINED 25607000 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 4896 # Number of BP lookups +system.cpu.branchPred.condPredicted 2917 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 793 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 3827 # Number of BTB lookups +system.cpu.branchPred.BTBHits 1151 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 29.984260 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 681 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 53 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 814 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 150 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 664 # Number of indirect misses. +system.cpu.branchPred.BTBHitPct 30.075777 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 688 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 51 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 820 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 149 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 671 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 136 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 4166 # DTB read hits -system.cpu.dtb.read_misses 75 # DTB read misses +system.cpu.dtb.read_hits 4131 # DTB read hits +system.cpu.dtb.read_misses 80 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 4241 # DTB read accesses -system.cpu.dtb.write_hits 1988 # DTB write hits -system.cpu.dtb.write_misses 49 # DTB write misses +system.cpu.dtb.read_accesses 4211 # DTB read accesses +system.cpu.dtb.write_hits 2002 # DTB write hits +system.cpu.dtb.write_misses 47 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 2037 # DTB write accesses -system.cpu.dtb.data_hits 6154 # DTB hits -system.cpu.dtb.data_misses 124 # DTB misses +system.cpu.dtb.write_accesses 2049 # DTB write accesses +system.cpu.dtb.data_hits 6133 # DTB hits +system.cpu.dtb.data_misses 127 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 6278 # DTB accesses -system.cpu.itb.fetch_hits 3823 # ITB hits -system.cpu.itb.fetch_misses 51 # ITB misses +system.cpu.dtb.data_accesses 6260 # DTB accesses +system.cpu.itb.fetch_hits 3841 # ITB hits +system.cpu.itb.fetch_misses 50 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 3874 # ITB accesses +system.cpu.itb.fetch_accesses 3891 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -300,313 +300,313 @@ system.cpu.itb.data_acv 0 # DT system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload0.num_syscalls 17 # Number of system calls system.cpu.workload1.num_syscalls 17 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 25580500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 51162 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 25607000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 51215 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 749 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 28166 # Number of instructions fetch has processed -system.cpu.fetch.Branches 4883 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 1974 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 9785 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 870 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 559 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.CacheLines 3823 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 565 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 26518 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.062146 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.446390 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 758 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 28344 # Number of instructions fetch has processed +system.cpu.fetch.Branches 4896 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 1988 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 10026 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 873 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 478 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.CacheLines 3841 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 575 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 26635 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.064164 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.464308 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 21410 80.74% 80.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 517 1.95% 82.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 399 1.50% 84.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 426 1.61% 85.80% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 581 2.19% 87.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 343 1.29% 89.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 470 1.77% 91.06% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 262 0.99% 92.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 2110 7.96% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 21569 80.98% 80.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 505 1.90% 82.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 398 1.49% 84.37% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 435 1.63% 86.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 472 1.77% 87.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 332 1.25% 89.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 468 1.76% 90.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 266 1.00% 91.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 2190 8.22% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 26518 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.095442 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.550526 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 35549 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 11706 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 4004 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 486 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 721 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 379 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 151 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 24714 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 389 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 721 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 35923 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 4419 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 1518 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 4115 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 5770 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 23686 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 47 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 451 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 687 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 4626 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 17749 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 29662 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 29644 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 26635 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.095597 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.553432 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 36561 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 11106 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 3971 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 513 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 726 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 381 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 147 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 24763 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 394 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 726 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 36906 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 4191 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 1623 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 4148 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 5283 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 23783 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 30 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 282 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 398 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 4456 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 17841 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 29807 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 29789 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 16 # Number of floating rename lookups system.cpu.rename.CommittedMaps 9154 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 8595 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 8687 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 57 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 45 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 1784 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2582 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1268 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 15 # Number of conflicting loads. +system.cpu.rename.skidInsts 1771 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2529 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1253 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 14 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 4 # Number of conflicting stores. -system.cpu.memDep1.insertedLoads 1972 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep1.insertedStores 1081 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep1.insertedLoads 1973 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep1.insertedStores 1111 # Number of stores inserted to the mem dependence unit. system.cpu.memDep1.conflictingLoads 6 # Number of conflicting loads. system.cpu.memDep1.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 21922 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 21942 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 50 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 19305 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 46 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 9201 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 4899 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 19296 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 47 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 9221 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 4863 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 16 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 26518 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.727996 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.455439 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 26635 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.724460 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.451046 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 19215 72.46% 72.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 2319 8.75% 81.21% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 1762 6.64% 87.85% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 1149 4.33% 92.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 1009 3.80% 95.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 611 2.30% 98.29% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 303 1.14% 99.43% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 94 0.35% 99.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 56 0.21% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 19310 72.50% 72.50% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 2394 8.99% 81.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 1620 6.08% 87.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 1274 4.78% 92.35% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 1030 3.87% 96.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 532 2.00% 98.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 319 1.20% 99.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 102 0.38% 99.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 54 0.20% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 26518 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 26635 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 25 8.33% 8.33% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 8.33% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 8.33% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.33% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 8.33% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 8.33% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 8.33% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 8.33% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 8.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 8.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 8.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 8.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 8.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 8.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 8.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.33% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 198 66.00% 74.33% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 77 25.67% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 28 9.18% 9.18% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 9.18% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 9.18% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 9.18% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 9.18% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 9.18% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 9.18% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 9.18% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 9.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 9.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 9.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 9.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 9.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 9.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 9.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 9.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 9.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 9.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 9.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 9.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 9.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 9.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 9.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 9.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 9.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 9.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 9.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.18% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 201 65.90% 75.08% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 76 24.92% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 6801 65.70% 65.72% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1 0.01% 65.73% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.73% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 65.75% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 65.75% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 65.75% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 65.75% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 65.75% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.75% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2445 23.62% 89.36% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1101 10.64% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 6749 65.93% 65.95% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1 0.01% 65.96% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.96% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 65.98% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 65.98% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 65.98% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 65.98% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 65.98% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.98% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2387 23.32% 89.30% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1095 10.70% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 10352 # Type of FU issued +system.cpu.iq.FU_type_0::total 10236 # Type of FU issued system.cpu.iq.FU_type_1::No_OpClass 2 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_1::IntAlu 5921 66.13% 66.16% # Type of FU issued -system.cpu.iq.FU_type_1::IntMult 1 0.01% 66.17% # Type of FU issued -system.cpu.iq.FU_type_1::IntDiv 0 0.00% 66.17% # Type of FU issued -system.cpu.iq.FU_type_1::FloatAdd 2 0.02% 66.19% # Type of FU issued -system.cpu.iq.FU_type_1::FloatCmp 0 0.00% 66.19% # Type of FU issued -system.cpu.iq.FU_type_1::FloatCvt 0 0.00% 66.19% # Type of FU issued -system.cpu.iq.FU_type_1::FloatMult 0 0.00% 66.19% # Type of FU issued -system.cpu.iq.FU_type_1::FloatDiv 0 0.00% 66.19% # Type of FU issued -system.cpu.iq.FU_type_1::FloatSqrt 0 0.00% 66.19% # Type of FU issued -system.cpu.iq.FU_type_1::SimdAdd 0 0.00% 66.19% # Type of FU issued -system.cpu.iq.FU_type_1::SimdAddAcc 0 0.00% 66.19% # Type of FU issued -system.cpu.iq.FU_type_1::SimdAlu 0 0.00% 66.19% # Type of FU issued -system.cpu.iq.FU_type_1::SimdCmp 0 0.00% 66.19% # Type of FU issued -system.cpu.iq.FU_type_1::SimdCvt 0 0.00% 66.19% # Type of FU issued -system.cpu.iq.FU_type_1::SimdMisc 0 0.00% 66.19% # Type of FU issued -system.cpu.iq.FU_type_1::SimdMult 0 0.00% 66.19% # Type of FU issued -system.cpu.iq.FU_type_1::SimdMultAcc 0 0.00% 66.19% # Type of FU issued -system.cpu.iq.FU_type_1::SimdShift 0 0.00% 66.19% # Type of FU issued -system.cpu.iq.FU_type_1::SimdShiftAcc 0 0.00% 66.19% # Type of FU issued -system.cpu.iq.FU_type_1::SimdSqrt 0 0.00% 66.19% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatAdd 0 0.00% 66.19% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatAlu 0 0.00% 66.19% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatCmp 0 0.00% 66.19% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatCvt 0 0.00% 66.19% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatDiv 0 0.00% 66.19% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatMisc 0 0.00% 66.19% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatMult 0 0.00% 66.19% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatMultAcc 0 0.00% 66.19% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatSqrt 0 0.00% 66.19% # Type of FU issued -system.cpu.iq.FU_type_1::MemRead 2023 22.60% 88.79% # Type of FU issued -system.cpu.iq.FU_type_1::MemWrite 1004 11.21% 100.00% # Type of FU issued +system.cpu.iq.FU_type_1::IntAlu 6020 66.45% 66.47% # Type of FU issued +system.cpu.iq.FU_type_1::IntMult 1 0.01% 66.48% # Type of FU issued +system.cpu.iq.FU_type_1::IntDiv 0 0.00% 66.48% # Type of FU issued +system.cpu.iq.FU_type_1::FloatAdd 2 0.02% 66.50% # Type of FU issued +system.cpu.iq.FU_type_1::FloatCmp 0 0.00% 66.50% # Type of FU issued +system.cpu.iq.FU_type_1::FloatCvt 0 0.00% 66.50% # Type of FU issued +system.cpu.iq.FU_type_1::FloatMult 0 0.00% 66.50% # Type of FU issued +system.cpu.iq.FU_type_1::FloatDiv 0 0.00% 66.50% # Type of FU issued +system.cpu.iq.FU_type_1::FloatSqrt 0 0.00% 66.50% # Type of FU issued +system.cpu.iq.FU_type_1::SimdAdd 0 0.00% 66.50% # Type of FU issued +system.cpu.iq.FU_type_1::SimdAddAcc 0 0.00% 66.50% # Type of FU issued +system.cpu.iq.FU_type_1::SimdAlu 0 0.00% 66.50% # Type of FU issued +system.cpu.iq.FU_type_1::SimdCmp 0 0.00% 66.50% # Type of FU issued +system.cpu.iq.FU_type_1::SimdCvt 0 0.00% 66.50% # Type of FU issued +system.cpu.iq.FU_type_1::SimdMisc 0 0.00% 66.50% # Type of FU issued +system.cpu.iq.FU_type_1::SimdMult 0 0.00% 66.50% # Type of FU issued +system.cpu.iq.FU_type_1::SimdMultAcc 0 0.00% 66.50% # Type of FU issued +system.cpu.iq.FU_type_1::SimdShift 0 0.00% 66.50% # Type of FU issued +system.cpu.iq.FU_type_1::SimdShiftAcc 0 0.00% 66.50% # Type of FU issued +system.cpu.iq.FU_type_1::SimdSqrt 0 0.00% 66.50% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatAdd 0 0.00% 66.50% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatAlu 0 0.00% 66.50% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatCmp 0 0.00% 66.50% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatCvt 0 0.00% 66.50% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatDiv 0 0.00% 66.50% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatMisc 0 0.00% 66.50% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatMult 0 0.00% 66.50% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatMultAcc 0 0.00% 66.50% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatSqrt 0 0.00% 66.50% # Type of FU issued +system.cpu.iq.FU_type_1::MemRead 2019 22.28% 88.79% # Type of FU issued +system.cpu.iq.FU_type_1::MemWrite 1016 11.21% 100.00% # Type of FU issued system.cpu.iq.FU_type_1::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_1::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_1::total 8953 # Type of FU issued -system.cpu.iq.FU_type::total 19305 0.00% 0.00% # Type of FU issued -system.cpu.iq.rate 0.377331 # Inst issue rate -system.cpu.iq.fu_busy_cnt::0 160 # FU busy when requested -system.cpu.iq.fu_busy_cnt::1 140 # FU busy when requested -system.cpu.iq.fu_busy_cnt::total 300 # FU busy when requested -system.cpu.iq.fu_busy_rate::0 0.008288 # FU busy rate (busy events/executed inst) -system.cpu.iq.fu_busy_rate::1 0.007252 # FU busy rate (busy events/executed inst) -system.cpu.iq.fu_busy_rate::total 0.015540 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 65432 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 31184 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 17495 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_1::total 9060 # Type of FU issued +system.cpu.iq.FU_type::total 19296 0.00% 0.00% # Type of FU issued +system.cpu.iq.rate 0.376765 # Inst issue rate +system.cpu.iq.fu_busy_cnt::0 157 # FU busy when requested +system.cpu.iq.fu_busy_cnt::1 148 # FU busy when requested +system.cpu.iq.fu_busy_cnt::total 305 # FU busy when requested +system.cpu.iq.fu_busy_rate::0 0.008136 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_busy_rate::1 0.007670 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_busy_rate::total 0.015806 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 65537 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 31224 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 17544 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 42 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 20 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 20 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 19579 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 19575 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 22 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 93 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1397 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 19 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 403 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1344 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 20 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 388 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 284 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread1.forwLoads 47 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.cacheBlocked 261 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread1.forwLoads 45 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread1.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread1.squashedLoads 787 # Number of loads squashed -system.cpu.iew.lsq.thread1.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread1.memOrderViolation 13 # Number of memory ordering violations -system.cpu.iew.lsq.thread1.squashedStores 216 # Number of stores squashed +system.cpu.iew.lsq.thread1.squashedLoads 788 # Number of loads squashed +system.cpu.iew.lsq.thread1.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread1.memOrderViolation 12 # Number of memory ordering violations +system.cpu.iew.lsq.thread1.squashedStores 246 # Number of stores squashed system.cpu.iew.lsq.thread1.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread1.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread1.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread1.cacheBlocked 280 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread1.cacheBlocked 288 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 721 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 2770 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 755 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 22107 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 169 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 4554 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 2349 # Number of dispatched store instructions +system.cpu.iew.iewSquashCycles 726 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 2949 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 377 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 22125 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 143 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 4502 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 2364 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 50 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 22 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 722 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewIQFullEvents 25 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 340 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 32 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 132 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedTakenIncorrect 130 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 639 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 771 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 18606 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts::0 2294 # Number of load instructions executed -system.cpu.iew.iewExecLoadInsts::1 1956 # Number of load instructions executed -system.cpu.iew.iewExecLoadInsts::total 4250 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 699 # Number of squashed instructions skipped in execute +system.cpu.iew.branchMispredicts 769 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 18625 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts::0 2260 # Number of load instructions executed +system.cpu.iew.iewExecLoadInsts::1 1960 # Number of load instructions executed +system.cpu.iew.iewExecLoadInsts::total 4220 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 671 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp::0 0 # number of swp insts executed system.cpu.iew.exec_swp::1 0 # number of swp insts executed system.cpu.iew.exec_swp::total 0 # number of swp insts executed -system.cpu.iew.exec_nop::0 68 # number of nop insts executed +system.cpu.iew.exec_nop::0 66 # number of nop insts executed system.cpu.iew.exec_nop::1 67 # number of nop insts executed -system.cpu.iew.exec_nop::total 135 # number of nop insts executed -system.cpu.iew.exec_refs::0 3353 # number of memory reference insts executed -system.cpu.iew.exec_refs::1 2946 # number of memory reference insts executed -system.cpu.iew.exec_refs::total 6299 # number of memory reference insts executed -system.cpu.iew.exec_branches::0 1561 # Number of branches executed -system.cpu.iew.exec_branches::1 1400 # Number of branches executed -system.cpu.iew.exec_branches::total 2961 # Number of branches executed -system.cpu.iew.exec_stores::0 1059 # Number of stores executed -system.cpu.iew.exec_stores::1 990 # Number of stores executed -system.cpu.iew.exec_stores::total 2049 # Number of stores executed -system.cpu.iew.exec_rate 0.363668 # Inst execution rate -system.cpu.iew.wb_sent::0 9443 # cumulative count of insts sent to commit -system.cpu.iew.wb_sent::1 8345 # cumulative count of insts sent to commit -system.cpu.iew.wb_sent::total 17788 # cumulative count of insts sent to commit -system.cpu.iew.wb_count::0 9266 # cumulative count of insts written-back -system.cpu.iew.wb_count::1 8249 # cumulative count of insts written-back -system.cpu.iew.wb_count::total 17515 # cumulative count of insts written-back -system.cpu.iew.wb_producers::0 4880 # num instructions producing a value -system.cpu.iew.wb_producers::1 4386 # num instructions producing a value -system.cpu.iew.wb_producers::total 9266 # num instructions producing a value -system.cpu.iew.wb_consumers::0 6580 # num instructions consuming a value -system.cpu.iew.wb_consumers::1 5911 # num instructions consuming a value -system.cpu.iew.wb_consumers::total 12491 # num instructions consuming a value -system.cpu.iew.wb_rate::0 0.181111 # insts written-back per cycle -system.cpu.iew.wb_rate::1 0.161233 # insts written-back per cycle -system.cpu.iew.wb_rate::total 0.342344 # insts written-back per cycle -system.cpu.iew.wb_fanout::0 0.741641 # average fanout of values written-back -system.cpu.iew.wb_fanout::1 0.742006 # average fanout of values written-back -system.cpu.iew.wb_fanout::total 0.741814 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 9276 # The number of squashed insts skipped by commit +system.cpu.iew.exec_nop::total 133 # number of nop insts executed +system.cpu.iew.exec_refs::0 3318 # number of memory reference insts executed +system.cpu.iew.exec_refs::1 2963 # number of memory reference insts executed +system.cpu.iew.exec_refs::total 6281 # number of memory reference insts executed +system.cpu.iew.exec_branches::0 1546 # Number of branches executed +system.cpu.iew.exec_branches::1 1419 # Number of branches executed +system.cpu.iew.exec_branches::total 2965 # Number of branches executed +system.cpu.iew.exec_stores::0 1058 # Number of stores executed +system.cpu.iew.exec_stores::1 1003 # Number of stores executed +system.cpu.iew.exec_stores::total 2061 # Number of stores executed +system.cpu.iew.exec_rate 0.363663 # Inst execution rate +system.cpu.iew.wb_sent::0 9379 # cumulative count of insts sent to commit +system.cpu.iew.wb_sent::1 8440 # cumulative count of insts sent to commit +system.cpu.iew.wb_sent::total 17819 # cumulative count of insts sent to commit +system.cpu.iew.wb_count::0 9213 # cumulative count of insts written-back +system.cpu.iew.wb_count::1 8351 # cumulative count of insts written-back +system.cpu.iew.wb_count::total 17564 # cumulative count of insts written-back +system.cpu.iew.wb_producers::0 4854 # num instructions producing a value +system.cpu.iew.wb_producers::1 4443 # num instructions producing a value +system.cpu.iew.wb_producers::total 9297 # num instructions producing a value +system.cpu.iew.wb_consumers::0 6502 # num instructions consuming a value +system.cpu.iew.wb_consumers::1 5954 # num instructions consuming a value +system.cpu.iew.wb_consumers::total 12456 # num instructions consuming a value +system.cpu.iew.wb_rate::0 0.179889 # insts written-back per cycle +system.cpu.iew.wb_rate::1 0.163058 # insts written-back per cycle +system.cpu.iew.wb_rate::total 0.342946 # insts written-back per cycle +system.cpu.iew.wb_fanout::0 0.746540 # average fanout of values written-back +system.cpu.iew.wb_fanout::1 0.746221 # average fanout of values written-back +system.cpu.iew.wb_fanout::total 0.746387 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 9288 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 34 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 642 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 26498 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.483206 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.376058 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 647 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 26599 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.481371 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.387327 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 21430 80.87% 80.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 2543 9.60% 90.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 900 3.40% 93.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 463 1.75% 95.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 308 1.16% 96.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 165 0.62% 97.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 178 0.67% 98.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 141 0.53% 98.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 370 1.40% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 21475 80.74% 80.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 2692 10.12% 90.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 910 3.42% 94.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 379 1.42% 95.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 247 0.93% 96.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 153 0.58% 97.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 207 0.78% 97.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 128 0.48% 98.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 408 1.53% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 26498 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 26599 # Number of insts commited each cycle system.cpu.commit.committedInsts::0 6402 # Number of instructions committed system.cpu.commit.committedInsts::1 6402 # Number of instructions committed system.cpu.commit.committedInsts::total 12804 # Number of instructions committed @@ -708,256 +708,256 @@ system.cpu.commit.op_class_1::IprAccess 0 0.00% 100.00% # Cl system.cpu.commit.op_class_1::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_1::total 6402 # Class of committed instruction system.cpu.commit.op_class::total 12804 0.00% 0.00% # Class of committed instruction -system.cpu.commit.bw_lim_events 370 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 113336 # The number of ROB reads -system.cpu.rob.rob_writes 45860 # The number of ROB writes -system.cpu.timesIdled 410 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 24644 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 408 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 113983 # The number of ROB reads +system.cpu.rob.rob_writes 45899 # The number of ROB writes +system.cpu.timesIdled 392 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 24580 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts::0 6385 # Number of Instructions Simulated system.cpu.committedInsts::1 6385 # Number of Instructions Simulated system.cpu.committedInsts::total 12770 # Number of Instructions Simulated system.cpu.committedOps::0 6385 # Number of Ops (including micro ops) Simulated system.cpu.committedOps::1 6385 # Number of Ops (including micro ops) Simulated system.cpu.committedOps::total 12770 # Number of Ops (including micro ops) Simulated -system.cpu.cpi::0 8.012843 # CPI: Cycles Per Instruction -system.cpu.cpi::1 8.012843 # CPI: Cycles Per Instruction -system.cpu.cpi_total 4.006421 # CPI: Total CPI of All Threads -system.cpu.ipc::0 0.124800 # IPC: Instructions Per Cycle -system.cpu.ipc::1 0.124800 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.249599 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 23495 # number of integer regfile reads -system.cpu.int_regfile_writes 13160 # number of integer regfile writes +system.cpu.cpi::0 8.021143 # CPI: Cycles Per Instruction +system.cpu.cpi::1 8.021143 # CPI: Cycles Per Instruction +system.cpu.cpi_total 4.010572 # CPI: Total CPI of All Threads +system.cpu.ipc::0 0.124671 # IPC: Instructions Per Cycle +system.cpu.ipc::1 0.124671 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.249341 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 23552 # number of integer regfile reads +system.cpu.int_regfile_writes 13174 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads system.cpu.fp_regfile_writes 4 # number of floating regfile writes system.cpu.misc_regfile_reads 2 # number of misc regfile reads system.cpu.misc_regfile_writes 2 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 25580500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 25607000 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements::0 0 # number of replacements system.cpu.dcache.tags.replacements::1 0 # number of replacements system.cpu.dcache.tags.replacements::total 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 216.394211 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 4263 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 214.351374 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 4238 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 341 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 12.501466 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 12.428152 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 216.394211 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.052831 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.052831 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 214.351374 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.052332 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.052332 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 341 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 72 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 269 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 77 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 264 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.083252 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 10889 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 10889 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 25580500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 3245 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 3245 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 1018 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 1018 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 4263 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 4263 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 4263 # number of overall hits -system.cpu.dcache.overall_hits::total 4263 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 299 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 299 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 712 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 712 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1011 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1011 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1011 # number of overall misses -system.cpu.dcache.overall_misses::total 1011 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 23300000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 23300000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 52494934 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 52494934 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 75794934 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 75794934 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 75794934 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 75794934 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 3544 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 3544 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 10843 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 10843 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 25607000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 3221 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 3221 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 1017 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 1017 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 4238 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 4238 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 4238 # number of overall hits +system.cpu.dcache.overall_hits::total 4238 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 300 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 300 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 713 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 713 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1013 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1013 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1013 # number of overall misses +system.cpu.dcache.overall_misses::total 1013 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 25278500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 25278500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 49654940 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 49654940 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 74933440 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 74933440 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 74933440 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 74933440 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 3521 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 3521 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 1730 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 1730 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 5274 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 5274 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 5274 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 5274 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.084368 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.084368 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.411561 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.411561 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.191695 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.191695 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.191695 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.191695 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 77926.421405 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 77926.421405 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73728.839888 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 73728.839888 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 74970.261128 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 74970.261128 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 74970.261128 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 74970.261128 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 5977 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 5251 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 5251 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 5251 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 5251 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.085203 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.085203 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.412139 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.412139 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.192916 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.192916 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.192916 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.192916 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 84261.666667 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 84261.666667 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69642.272090 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 69642.272090 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 73971.806515 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 73971.806515 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 73971.806515 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 73971.806515 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 6514 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 130 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 137 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 45.976923 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 47.547445 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.ReadReq_mshr_hits::cpu.data 103 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 103 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 566 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 566 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 669 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 669 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 669 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 669 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 196 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 196 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 146 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 146 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 568 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 568 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 671 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 671 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 671 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 671 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 197 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 197 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 145 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 145 # number of WriteReq MSHR misses system.cpu.dcache.demand_mshr_misses::cpu.data 342 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::total 342 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 342 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 342 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17233500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 17233500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12825986 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 12825986 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 30059486 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 30059486 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 30059486 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 30059486 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.055305 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.055305 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.064846 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.064846 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.064846 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.064846 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 87926.020408 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 87926.020408 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 87849.219178 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 87849.219178 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 87893.233918 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 87893.233918 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 87893.233918 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 87893.233918 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 25580500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 18892500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 18892500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12000985 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 12000985 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 30893485 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 30893485 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 30893485 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 30893485 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.055950 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.055950 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.083815 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.083815 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.065130 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.065130 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.065130 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.065130 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 95901.015228 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 95901.015228 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 82765.413793 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 82765.413793 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 90331.827485 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 90331.827485 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 90331.827485 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 90331.827485 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 25607000 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements::0 7 # number of replacements system.cpu.icache.tags.replacements::1 0 # number of replacements system.cpu.icache.tags.replacements::total 7 # number of replacements -system.cpu.icache.tags.tagsinuse 317.276824 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 2916 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 623 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 4.680578 # Average number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 314.192674 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 2931 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 627 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 4.674641 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 317.276824 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.154920 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.154920 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 616 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 237 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 379 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.300781 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 8261 # Number of tag accesses -system.cpu.icache.tags.data_accesses 8261 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 25580500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 2916 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 2916 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 2916 # 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number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 69936495 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 69936495 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 3819 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 3819 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 3819 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 3819 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 3819 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 3819 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.236449 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.236449 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.236449 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.236449 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.236449 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.236449 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 77449.053156 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 77449.053156 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 77449.053156 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 77449.053156 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 77449.053156 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 77449.053156 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 3083 # number of cycles access was blocked +system.cpu.icache.tags.occ_blocks::cpu.inst 314.192674 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.153414 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.153414 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 620 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 246 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 374 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.302734 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 8297 # Number of tag accesses +system.cpu.icache.tags.data_accesses 8297 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 25607000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 2931 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 2931 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 2931 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 2931 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 2931 # number of overall hits +system.cpu.icache.overall_hits::total 2931 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 904 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 904 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 904 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 904 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 904 # number of overall misses +system.cpu.icache.overall_misses::total 904 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 70022492 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 70022492 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 70022492 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 70022492 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 70022492 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 70022492 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 3835 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 3835 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 3835 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 3835 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 3835 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 3835 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.235724 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.235724 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.235724 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.235724 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.235724 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.235724 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 77458.508850 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 77458.508850 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 77458.508850 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 77458.508850 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 77458.508850 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 77458.508850 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 3069 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 55 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 61 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 56.054545 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 50.311475 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.writebacks::writebacks 7 # number of writebacks system.cpu.icache.writebacks::total 7 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 280 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 280 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 280 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 280 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 280 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 280 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 623 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 623 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 623 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 623 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 623 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 623 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 50404995 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 50404995 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 50404995 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 50404995 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 50404995 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 50404995 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.163132 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.163132 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.163132 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.163132 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.163132 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.163132 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 80906.894061 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 80906.894061 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 80906.894061 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 80906.894061 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 80906.894061 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 80906.894061 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 25580500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 277 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 277 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 277 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 277 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 277 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 277 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 627 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 627 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 627 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 627 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 627 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 627 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 52227494 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 52227494 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 52227494 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 52227494 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 52227494 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 52227494 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.163494 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.163494 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.163494 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.163494 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.163494 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.163494 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 83297.438596 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 83297.438596 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 83297.438596 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 83297.438596 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 83297.438596 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 83297.438596 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 25607000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements::0 0 # number of replacements system.cpu.l2cache.tags.replacements::1 0 # number of replacements system.cpu.l2cache.tags.replacements::total 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 438.773475 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 529.119750 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 10 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 815 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.012270 # Average number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 965 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.010363 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 317.771557 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 121.001918 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.009698 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.003693 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.013390 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 815 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 286 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 529 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.024872 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 8737 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 8737 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 25580500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.occ_blocks::cpu.inst 314.628551 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 214.491199 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.009602 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.006546 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.016147 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 965 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 319 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 646 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.029449 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 8773 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 8773 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 25607000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackClean_hits::writebacks 7 # number of WritebackClean hits system.cpu.l2cache.WritebackClean_hits::total 7 # number of WritebackClean hits system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 3 # number of ReadCleanReq hits @@ -966,184 +966,190 @@ system.cpu.l2cache.demand_hits::cpu.inst 3 # nu system.cpu.l2cache.demand_hits::total 3 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 3 # number of overall hits system.cpu.l2cache.overall_hits::total 3 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 146 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 146 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 620 # 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average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 94357.868020 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 94357.868020 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82129.006410 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 88780.701754 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 84483.954451 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82129.006410 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 88780.701754 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 84483.954451 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # 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average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 74494.306418 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 976 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 9 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 25580500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 818 # Transaction distribution +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 25607000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 823 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 7 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 146 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 146 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 623 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 196 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1253 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadExReq 145 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 145 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 627 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 197 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1261 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 683 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 1936 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 40320 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 1944 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 40576 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 21824 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 62144 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 62400 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 965 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.002073 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.045502 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 969 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.002064 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.045408 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 963 99.79% 99.79% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 967 99.79% 99.79% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 2 0.21% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 965 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 493000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 969 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 495000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 934500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 940500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 3.7 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 511500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 2.0 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 25580500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 815 # Transaction distribution -system.membus.trans_dist::ReadExReq 146 # Transaction distribution -system.membus.trans_dist::ReadExResp 146 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 816 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1923 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1923 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 61504 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 61504 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoop_filter.tot_requests 966 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 25607000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 820 # Transaction distribution +system.membus.trans_dist::ReadExReq 145 # Transaction distribution +system.membus.trans_dist::ReadExResp 145 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 821 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1931 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1931 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 61760 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 61760 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 962 # Request fanout histogram +system.membus.snoop_fanout::samples 966 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 962 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 966 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 962 # Request fanout histogram -system.membus.reqLayer0.occupancy 1181000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 966 # Request fanout histogram +system.membus.reqLayer0.occupancy 1177000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 4.6 # Layer utilization (%) -system.membus.respLayer1.occupancy 5115750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 5133750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 20.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt index a74466584..698dda741 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000029 # Number of seconds simulated -sim_ticks 28845500 # Number of ticks simulated -final_tick 28845500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 29089500 # Number of ticks simulated +final_tick 29089500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 66025 # Simulator instruction rate (inst/s) -host_op_rate 66018 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 131902943 # Simulator tick rate (ticks/s) -host_mem_usage 248796 # Number of bytes of host memory used -host_seconds 0.22 # Real time elapsed on the host +host_inst_rate 39190 # Simulator instruction rate (inst/s) +host_op_rate 39188 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 78964807 # Simulator tick rate (ticks/s) +host_mem_usage 252916 # Number of bytes of host memory used +host_seconds 0.37 # Real time elapsed on the host sim_insts 14436 # Number of instructions simulated sim_ops 14436 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 28845500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 29089500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 23232 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 9408 # Number of bytes read from this memory system.physmem.bytes_read::total 32640 # Number of bytes read from this memory @@ -22,14 +22,14 @@ system.physmem.bytes_inst_read::total 23232 # Nu system.physmem.num_reads::cpu.inst 363 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 147 # Number of read requests responded to by this memory system.physmem.num_reads::total 510 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 805394256 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 326151393 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1131545648 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 805394256 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 805394256 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 805394256 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 326151393 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1131545648 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 798638684 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 323415665 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1122054350 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 798638684 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 798638684 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 798638684 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 323415665 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1122054350 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 511 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 511 # Number of DRAM read bursts, including those serviced by the write queue @@ -76,7 +76,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 28814000 # Total gap between requests +system.physmem.totGap 29058000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -188,309 +188,309 @@ system.physmem.wrQLenPdf::61 0 # Wh system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see system.physmem.bytesPerActivate::samples 75 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 412.160000 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 276.286075 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 342.271863 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 411.306667 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 274.853259 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 343.874505 # Bytes accessed per row activation system.physmem.bytesPerActivate::0-127 13 17.33% 17.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 18 24.00% 41.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 12 16.00% 57.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 7 9.33% 66.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 19 25.33% 42.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 12 16.00% 58.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 6 8.00% 66.67% # Bytes accessed per row activation system.physmem.bytesPerActivate::512-639 5 6.67% 73.33% # Bytes accessed per row activation system.physmem.bytesPerActivate::768-895 8 10.67% 84.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::896-1023 1 1.33% 85.33% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 11 14.67% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 75 # Bytes accessed per row activation -system.physmem.totQLat 3584250 # Total ticks spent queuing -system.physmem.totMemAccLat 13165500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 3266500 # Total ticks spent queuing +system.physmem.totMemAccLat 12847750 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2555000 # Total ticks spent in databus transfers -system.physmem.avgQLat 7014.19 # Average queueing delay per DRAM burst +system.physmem.avgQLat 6392.37 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25764.19 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1133.76 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 25142.37 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1124.25 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1133.76 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1124.25 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 8.86 # Data bus utilization in percentage -system.physmem.busUtilRead 8.86 # Data bus utilization in percentage for reads +system.physmem.busUtil 8.78 # Data bus utilization in percentage +system.physmem.busUtilRead 8.78 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.55 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.54 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 428 # Number of row buffer hits during reads +system.physmem.readRowHits 427 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.76 # Row buffer hit rate for reads +system.physmem.readRowHitRate 83.56 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 56387.48 # Average gap between requests -system.physmem.pageHitRate 83.76 # Row buffer hit rate, read and write combined +system.physmem.avgGap 56864.97 # Average gap between requests +system.physmem.pageHitRate 83.56 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 309960 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 169125 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 2121600 # Energy for read commands per rank (pJ) +system.physmem_0.readEnergy 2113800 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 15733710 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 369750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 20229825 # Total energy per rank (pJ) -system.physmem_0.averagePower 856.515480 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 717750 # Time in different power states +system.physmem_0.actBackEnergy 16083405 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 63000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 20264970 # Total energy per rank (pJ) +system.physmem_0.averagePower 858.003493 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 22500 # Time in different power states system.physmem_0.memoryStateTime::REF 780000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 27177750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 22830000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.physmem_1.actEnergy 241920 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 132000 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 1396200 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 15520815 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 556500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 19373115 # Total energy per rank (pJ) -system.physmem_1.averagePower 820.243027 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 4073500 # Time in different power states +system.physmem_1.actBackEnergy 15332715 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 721500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 19350015 # Total energy per rank (pJ) +system.physmem_1.averagePower 819.264991 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 4570750 # Time in different power states system.physmem_1.memoryStateTime::REF 780000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 21995000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 21719750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 28845500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 12618 # Number of BP lookups -system.cpu.branchPred.condPredicted 7653 # Number of conditional branches predicted +system.pwrStateResidencyTicks::UNDEFINED 29089500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 12614 # Number of BP lookups +system.cpu.branchPred.condPredicted 7656 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 1475 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9458 # Number of BTB lookups +system.cpu.branchPred.BTBLookups 9453 # Number of BTB lookups system.cpu.branchPred.BTBHits 0 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage system.cpu.branchPred.usedRAS 736 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 166 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 9458 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectLookups 9453 # Number of indirect predictor lookups. system.cpu.branchPred.indirectHits 1844 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 7614 # Number of indirect misses. +system.cpu.branchPred.indirectMisses 7609 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 897 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.workload.num_syscalls 18 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 28845500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 57692 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 29089500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 58180 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 15531 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 59063 # Number of instructions fetch has processed -system.cpu.fetch.Branches 12618 # Number of branches that fetch encountered +system.cpu.fetch.icacheStallCycles 15554 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 59055 # Number of instructions fetch has processed +system.cpu.fetch.Branches 12614 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 2580 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 17477 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.Cycles 17529 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 3145 # Number of cycles fetch has spent squashing system.cpu.fetch.MiscStallCycles 6 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1084 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingTrapStallCycles 1090 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 25 # Number of stall cycles due to full MSHR system.cpu.fetch.CacheLines 7530 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 719 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 35695 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.654658 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.906598 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheSquashes 720 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 35776 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.650688 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.904189 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 22943 64.28% 64.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 4506 12.62% 76.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 507 1.42% 78.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 451 1.26% 79.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 761 2.13% 81.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 707 1.98% 83.70% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 297 0.83% 84.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 355 0.99% 85.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 5168 14.48% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 23025 64.36% 64.36% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 4506 12.60% 76.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 507 1.42% 78.37% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 451 1.26% 79.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 761 2.13% 81.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 707 1.98% 83.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 297 0.83% 84.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 355 0.99% 85.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 5167 14.44% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 35695 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.218713 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.023764 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 12449 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 12945 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 7933 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 796 # Number of cycles decode is unblocking +system.cpu.fetch.rateDist::total 35776 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.216810 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.015040 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 12463 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 13012 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 7932 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 797 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 1572 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 42061 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 42051 # Number of instructions handled by decode system.cpu.rename.SquashCycles 1572 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 13228 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 1813 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 9713 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 7918 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 1451 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 37021 # Number of instructions processed by rename +system.cpu.rename.IdleCycles 13239 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 1819 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 9760 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 7921 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 1465 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 37034 # Number of instructions processed by rename system.cpu.rename.IQFullEvents 10 # Number of times rename has blocked due to IQ full -system.cpu.rename.SQFullEvents 1034 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 31983 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 66431 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 54837 # Number of integer rename lookups +system.cpu.rename.SQFullEvents 1048 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 31990 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 66442 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 54845 # Number of integer rename lookups system.cpu.rename.CommittedMaps 13819 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 18164 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 18171 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 796 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 801 # count of temporary serializing insts renamed system.cpu.rename.skidInsts 4352 # count of insts added to the skid buffer system.cpu.memDep0.insertedLoads 4576 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 2922 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 2920 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 15 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 11 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 28829 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 28828 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 757 # Number of non-speculative instructions added to the IQ system.cpu.iq.iqInstsIssued 25362 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 117 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 15150 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 11340 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedInstsIssued 118 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 15149 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 11337 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 282 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 35695 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.710520 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.505149 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 35776 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.708911 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.503990 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 26438 74.07% 74.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 3266 9.15% 83.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 1617 4.53% 87.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 1544 4.33% 92.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 1236 3.46% 95.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 754 2.11% 97.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 464 1.30% 98.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 276 0.77% 99.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 26518 74.12% 74.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 3268 9.13% 83.26% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 1619 4.53% 87.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 1541 4.31% 92.09% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 1236 3.45% 95.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 752 2.10% 97.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 465 1.30% 98.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 277 0.77% 99.72% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 100 0.28% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 35695 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 35776 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 153 52.04% 52.04% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 52.04% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 52.04% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 52.04% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 52.04% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 52.04% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 52.04% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 52.04% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 52.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 52.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 52.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 52.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 52.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 52.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 52.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 52.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 52.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 52.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 52.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 52.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 52.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 52.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 52.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 52.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 52.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 52.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 52.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 52.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 52.04% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 53 18.03% 70.07% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 88 29.93% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 154 52.56% 52.56% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 52.56% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 52.56% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 52.56% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 52.56% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 52.56% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 52.56% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 52.56% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 52.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 52.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 52.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 52.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 52.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 52.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 52.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 52.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 52.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 52.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 52.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 52.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 52.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 52.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 52.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 52.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 52.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 52.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 52.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 52.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 52.56% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 51 17.41% 69.97% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 88 30.03% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 18585 73.28% 73.28% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 73.28% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 73.28% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 73.28% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 73.28% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 73.28% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 73.28% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 73.28% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 73.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 73.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 73.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 73.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 73.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 73.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 73.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 73.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 73.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 73.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 73.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 73.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 73.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 73.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 73.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 73.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 73.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 73.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 73.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 73.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 73.28% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 4271 16.84% 90.12% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 18584 73.27% 73.27% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 73.27% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 73.27% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 73.27% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 73.27% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 73.27% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 73.27% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 73.27% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 73.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 73.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 73.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 73.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 73.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 73.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 73.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 73.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 73.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 73.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 73.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 73.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 73.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 73.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 73.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 73.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 73.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 73.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 73.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 73.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 73.27% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 4272 16.84% 90.12% # Type of FU issued system.cpu.iq.FU_type_0::MemWrite 2506 9.88% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::total 25362 # Type of FU issued -system.cpu.iq.rate 0.439610 # Inst issue rate -system.cpu.iq.fu_busy_cnt 294 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.011592 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 86830 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 44763 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 22607 # Number of integer instruction queue wakeup accesses +system.cpu.iq.rate 0.435923 # Inst issue rate +system.cpu.iq.fu_busy_cnt 293 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.011553 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 86911 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 44761 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 22611 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 25656 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 25655 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 33 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread0.squashedLoads 2351 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 28 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1474 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 1472 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 26 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewSquashCycles 1572 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1846 # Number of cycles IEW is blocking +system.cpu.iew.iewBlockCycles 1852 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 15 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 31165 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispatchedInsts 31164 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 242 # Number of squashed instructions skipped by dispatch system.cpu.iew.iewDispLoadInsts 4576 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 2922 # Number of dispatched store instructions +system.cpu.iew.iewDispStoreInsts 2920 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 757 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 7 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 4 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 28 # Number of memory order violations system.cpu.iew.predictedTakenIncorrect 211 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1623 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1834 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 23714 # Number of executed instructions +system.cpu.iew.predictedNotTakenIncorrect 1624 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1835 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 23718 # Number of executed instructions system.cpu.iew.iewExecLoadInsts 3945 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1648 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecSquashedInsts 1644 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 1579 # number of nop insts executed -system.cpu.iew.exec_refs 6244 # number of memory reference insts executed +system.cpu.iew.exec_refs 6245 # number of memory reference insts executed system.cpu.iew.exec_branches 5021 # Number of branches executed -system.cpu.iew.exec_stores 2299 # Number of stores executed -system.cpu.iew.exec_rate 0.411045 # Inst execution rate -system.cpu.iew.wb_sent 23102 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 22607 # cumulative count of insts written-back -system.cpu.iew.wb_producers 10530 # num instructions producing a value -system.cpu.iew.wb_consumers 13790 # num instructions consuming a value -system.cpu.iew.wb_rate 0.391857 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.763597 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 15914 # The number of squashed insts skipped by commit +system.cpu.iew.exec_stores 2300 # Number of stores executed +system.cpu.iew.exec_rate 0.407666 # Inst execution rate +system.cpu.iew.wb_sent 23107 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 22611 # cumulative count of insts written-back +system.cpu.iew.wb_producers 10526 # num instructions producing a value +system.cpu.iew.wb_consumers 13786 # num instructions consuming a value +system.cpu.iew.wb_rate 0.388639 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.763528 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 15913 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 475 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 1475 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 32556 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.465721 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.244675 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 32637 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.464565 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.243420 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 25812 79.28% 79.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 3638 11.17% 90.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 1209 3.71% 94.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 603 1.85% 96.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 337 1.04% 97.06% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 302 0.93% 97.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 25892 79.33% 79.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 3639 11.15% 90.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 1211 3.71% 94.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 601 1.84% 96.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 338 1.04% 97.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 300 0.92% 97.99% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::6 374 1.15% 99.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 53 0.16% 99.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 54 0.17% 99.30% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::8 228 0.70% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 32556 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 32637 # Number of insts commited each cycle system.cpu.commit.committedInsts 15162 # Number of instructions committed system.cpu.commit.committedOps 15162 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -537,37 +537,37 @@ system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Cl system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 15162 # Class of committed instruction system.cpu.commit.bw_lim_events 228 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 62581 # The number of ROB reads -system.cpu.rob.rob_writes 65380 # The number of ROB writes -system.cpu.timesIdled 195 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 21997 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 62661 # The number of ROB reads +system.cpu.rob.rob_writes 65377 # The number of ROB writes +system.cpu.timesIdled 196 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 22404 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 14436 # Number of Instructions Simulated system.cpu.committedOps 14436 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 3.996398 # CPI: Cycles Per Instruction -system.cpu.cpi_total 3.996398 # CPI: Total CPI of All Threads -system.cpu.ipc 0.250225 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.250225 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 36850 # number of integer regfile reads -system.cpu.int_regfile_writes 20548 # number of integer regfile writes -system.cpu.misc_regfile_reads 8142 # number of misc regfile reads +system.cpu.cpi 4.030202 # CPI: Cycles Per Instruction +system.cpu.cpi_total 4.030202 # CPI: Total CPI of All Threads +system.cpu.ipc 0.248127 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.248127 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 36851 # number of integer regfile reads +system.cpu.int_regfile_writes 20552 # number of integer regfile writes +system.cpu.misc_regfile_reads 8143 # number of misc regfile reads system.cpu.misc_regfile_writes 569 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 28845500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 29089500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 99.867537 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 99.825953 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 4648 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 31.835616 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 99.867537 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.024382 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.024382 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 99.825953 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.024372 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.024372 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 21 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 125 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.035645 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 10540 # Number of tag accesses system.cpu.dcache.tags.data_accesses 10540 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 28845500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 29089500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 3609 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 3609 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 1033 # number of WriteReq hits @@ -586,14 +586,14 @@ system.cpu.dcache.demand_misses::cpu.data 549 # n system.cpu.dcache.demand_misses::total 549 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 549 # number of overall misses system.cpu.dcache.overall_misses::total 549 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 9339500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 9339500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 27134481 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 27134481 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 36473981 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 36473981 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 36473981 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 36473981 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 9476500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 9476500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 27259981 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 27259981 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 36736481 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 36736481 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 36736481 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 36736481 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 3749 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 3749 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses) @@ -612,19 +612,19 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.105760 system.cpu.dcache.demand_miss_rate::total 0.105760 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.105760 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.105760 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66710.714286 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 66710.714286 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 66343.474328 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 66343.474328 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 66437.123862 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 66437.123862 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 66437.123862 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 66437.123862 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 1313 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 67689.285714 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 67689.285714 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 66650.320293 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 66650.320293 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 66915.265938 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 66915.265938 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 66915.265938 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 66915.265938 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 1333 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 23 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 57.086957 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 57.956522 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.ReadReq_mshr_hits::cpu.data 75 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 75 # number of ReadReq MSHR hits @@ -642,14 +642,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 148 system.cpu.dcache.demand_mshr_misses::total 148 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 148 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 148 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5108500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5108500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6578000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 6578000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11686500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 11686500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11686500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 11686500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5190500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5190500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6454500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 6454500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11645000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 11645000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11645000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 11645000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017338 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017338 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.057559 # mshr miss rate for WriteReq accesses @@ -658,31 +658,31 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.028511 system.cpu.dcache.demand_mshr_miss_rate::total 0.028511 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.028511 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.028511 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78592.307692 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78592.307692 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79253.012048 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79253.012048 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78962.837838 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 78962.837838 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78962.837838 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 78962.837838 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 28845500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 79853.846154 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 79853.846154 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77765.060241 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77765.060241 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78682.432432 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 78682.432432 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78682.432432 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 78682.432432 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 29089500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 206.414108 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 206.188252 # Cycle average of tags in use system.cpu.icache.tags.total_refs 6949 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 365 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 19.038356 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 206.414108 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.100788 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.100788 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 206.188252 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.100678 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.100678 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 365 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 91 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 274 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 90 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 275 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.178223 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 15425 # Number of tag accesses system.cpu.icache.tags.data_accesses 15425 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 28845500 # Cumulative time (in ticks) in various power states +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 29089500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 6949 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 6949 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 6949 # number of demand (read+write) hits @@ -695,12 +695,12 @@ system.cpu.icache.demand_misses::cpu.inst 581 # n system.cpu.icache.demand_misses::total 581 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 581 # number of overall misses system.cpu.icache.overall_misses::total 581 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 40819000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 40819000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 40819000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 40819000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 40819000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 40819000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 40938500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 40938500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 40938500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 40938500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 40938500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 40938500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 7530 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 7530 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 7530 # number of demand (read+write) accesses @@ -713,17 +713,17 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.077158 system.cpu.icache.demand_miss_rate::total 0.077158 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.077158 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.077158 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70256.454389 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 70256.454389 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 70256.454389 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 70256.454389 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 70256.454389 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 70256.454389 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 190 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70462.134251 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 70462.134251 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 70462.134251 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 70462.134251 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 70462.134251 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 70462.134251 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 194 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 95 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 97 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.ReadReq_mshr_hits::cpu.inst 216 # number of ReadReq MSHR hits system.cpu.icache.ReadReq_mshr_hits::total 216 # number of ReadReq MSHR hits @@ -737,43 +737,43 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 365 system.cpu.icache.demand_mshr_misses::total 365 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 365 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 365 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 27746500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 27746500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 27746500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 27746500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 27746500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 27746500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 27977500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 27977500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 27977500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 27977500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 27977500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 27977500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.048473 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.048473 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.048473 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.048473 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.048473 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.048473 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 76017.808219 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 76017.808219 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 76017.808219 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 76017.808219 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 76017.808219 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 76017.808219 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 28845500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 76650.684932 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 76650.684932 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 76650.684932 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 76650.684932 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 76650.684932 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 76650.684932 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 29089500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 240.923513 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 305.425349 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 426 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.004695 # Average number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 509 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.003929 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 205.773852 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 35.149660 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.006280 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.001073 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.007352 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 426 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 318 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.013000 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_blocks::cpu.inst 205.546698 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 99.878652 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.006273 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.003048 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.009321 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 509 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 110 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 399 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.015533 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 4613 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 4613 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 28845500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 29089500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2 # number of ReadCleanReq hits system.cpu.l2cache.ReadCleanReq_hits::total 2 # number of ReadCleanReq hits system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits @@ -792,18 +792,18 @@ system.cpu.l2cache.demand_misses::total 511 # nu system.cpu.l2cache.overall_misses::cpu.inst 363 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 148 # number of overall misses system.cpu.l2cache.overall_misses::total 511 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6452500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 6452500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 27176000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 27176000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 5013500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 5013500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 27176000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 11466000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 38642000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 27176000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 11466000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 38642000 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6329000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 6329000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 27407000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 27407000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 5095500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 5095500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 27407000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 11424500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 38831500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 27407000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 11424500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 38831500 # number of overall miss cycles system.cpu.l2cache.ReadExReq_accesses::cpu.data 83 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 83 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 365 # number of ReadCleanReq accesses(hits+misses) @@ -828,18 +828,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.996101 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.994521 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.996101 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77740.963855 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77740.963855 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74865.013774 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74865.013774 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 77130.769231 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 77130.769231 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74865.013774 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77472.972973 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 75620.352250 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74865.013774 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77472.972973 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 75620.352250 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76253.012048 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76253.012048 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75501.377410 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75501.377410 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 78392.307692 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 78392.307692 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75501.377410 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77192.567568 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 75991.193738 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75501.377410 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77192.567568 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 75991.193738 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -858,18 +858,18 @@ system.cpu.l2cache.demand_mshr_misses::total 511 system.cpu.l2cache.overall_mshr_misses::cpu.inst 363 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 148 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 511 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5622500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5622500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 23546000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 23546000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4383500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4383500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 23546000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10006000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 33552000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 23546000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10006000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 33552000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5499000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5499000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 23777000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 23777000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4465500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4465500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 23777000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9964500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 33741500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 23777000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9964500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 33741500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.994521 # mshr miss rate for ReadCleanReq accesses @@ -882,25 +882,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.996101 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.994521 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.996101 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67740.963855 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67740.963855 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64865.013774 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64865.013774 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 67438.461538 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 67438.461538 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64865.013774 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67608.108108 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65659.491194 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64865.013774 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67608.108108 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65659.491194 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66253.012048 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66253.012048 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65501.377410 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65501.377410 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 68700 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 68700 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65501.377410 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67327.702703 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66030.332681 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65501.377410 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67327.702703 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66030.332681 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 513 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 2 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 28845500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 29089500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 428 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 83 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 83 # Transaction distribution @@ -931,7 +931,13 @@ system.cpu.toL2Bus.respLayer0.occupancy 547500 # La system.cpu.toL2Bus.respLayer0.utilization 1.9 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 219000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 28845500 # Cumulative time (in ticks) in various power states +system.membus.snoop_filter.tot_requests 511 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 29089500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 426 # Transaction distribution system.membus.trans_dist::ReadExReq 83 # Transaction distribution system.membus.trans_dist::ReadExResp 83 # Transaction distribution @@ -952,9 +958,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 511 # Request fanout histogram -system.membus.reqLayer0.occupancy 623500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 2694000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 623000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.1 # Layer utilization (%) +system.membus.respLayer1.occupancy 2693500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 9.3 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/stats.txt index f98d4e626..3be5d7ce8 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000008 # Nu sim_ticks 7612000 # Number of ticks simulated final_tick 7612000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 348414 # Simulator instruction rate (inst/s) -host_op_rate 348210 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 174731638 # Simulator tick rate (ticks/s) -host_mem_usage 237012 # Number of bytes of host memory used -host_seconds 0.04 # Real time elapsed on the host +host_inst_rate 110250 # Simulator instruction rate (inst/s) +host_op_rate 110244 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 55345027 # Simulator tick rate (ticks/s) +host_mem_usage 240104 # Number of bytes of host memory used +host_seconds 0.14 # Real time elapsed on the host sim_insts 15162 # Number of instructions simulated sim_ops 15162 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -100,6 +100,12 @@ system.cpu.op_class::MemWrite 1452 9.55% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 15207 # Class of executed instruction +system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.pwrStateResidencyTicks::UNDEFINED 7612000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 17432 # Transaction distribution system.membus.trans_dist::ReadResp 17432 # Transaction distribution @@ -116,14 +122,14 @@ system.membus.pkt_size::total 81270 # Cu system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) system.membus.snoop_fanout::samples 18880 # Request fanout histogram -system.membus.snoop_fanout::mean 0.805456 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.395860 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 3673 19.45% 19.45% # Request fanout histogram -system.membus.snoop_fanout::1 15207 80.55% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 18880 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 18880 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt index 28b8d6695..387eea7ee 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000044 # Number of seconds simulated -sim_ticks 44282500 # Number of ticks simulated -final_tick 44282500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000045 # Number of seconds simulated +sim_ticks 44698500 # Number of ticks simulated +final_tick 44698500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 322672 # Simulator instruction rate (inst/s) -host_op_rate 322568 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 941828647 # Simulator tick rate (ticks/s) -host_mem_usage 247000 # Number of bytes of host memory used -host_seconds 0.05 # Real time elapsed on the host +host_inst_rate 128576 # Simulator instruction rate (inst/s) +host_op_rate 128568 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 379003891 # Simulator tick rate (ticks/s) +host_mem_usage 250608 # Number of bytes of host memory used +host_seconds 0.12 # Real time elapsed on the host sim_insts 15162 # Number of instructions simulated sim_ops 15162 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 44282500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 44698500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 17792 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 8832 # Number of bytes read from this memory system.physmem.bytes_read::total 26624 # Number of bytes read from this memory @@ -22,19 +22,19 @@ system.physmem.bytes_inst_read::total 17792 # Nu system.physmem.num_reads::cpu.inst 278 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 138 # Number of read requests responded to by this memory system.physmem.num_reads::total 416 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 401784000 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 199446734 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 601230734 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 401784000 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 401784000 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 401784000 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 199446734 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 601230734 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 44282500 # Cumulative time (in ticks) in various power states +system.physmem.bw_read::cpu.inst 398044677 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 197590523 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 595635200 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 398044677 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 398044677 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 398044677 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 197590523 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 595635200 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 44698500 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.workload.num_syscalls 18 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 44282500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 88565 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 44698500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 89397 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 15162 # Number of instructions committed @@ -53,7 +53,7 @@ system.cpu.num_mem_refs 3683 # nu system.cpu.num_load_insts 2231 # Number of load instructions system.cpu.num_store_insts 1452 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 88564.998000 # Number of busy cycles +system.cpu.num_busy_cycles 89396.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 3363 # Number of branches fetched @@ -92,23 +92,23 @@ system.cpu.op_class::MemWrite 1452 9.55% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 15207 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 44282500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 44698500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 97.148649 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 97.037351 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 3535 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 138 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 25.615942 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 97.148649 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.023718 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.023718 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 97.037351 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.023691 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.023691 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 138 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 127 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.033691 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 7484 # Number of tag accesses system.cpu.dcache.tags.data_accesses 7484 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 44282500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 44698500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 2172 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 2172 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 1357 # number of WriteReq hits @@ -127,14 +127,14 @@ system.cpu.dcache.demand_misses::cpu.data 138 # n system.cpu.dcache.demand_misses::total 138 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 138 # number of overall misses system.cpu.dcache.overall_misses::total 138 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 3286000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 3286000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 5270000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 5270000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 8556000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 8556000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 8556000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 8556000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 3339000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 3339000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 5355000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 5355000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 8694000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 8694000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 8694000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 8694000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 2225 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 2225 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses) @@ -153,14 +153,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.037633 system.cpu.dcache.demand_miss_rate::total 0.037633 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.037633 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.037633 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62000 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 62000 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 62000 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 62000 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 62000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 62000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 62000 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 63000 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 63000 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 63000 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 63000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 63000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 63000 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -175,14 +175,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 138 system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3233000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3233000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5185000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5185000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8418000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 8418000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8418000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 8418000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3286000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3286000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5270000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5270000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8556000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 8556000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8556000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 8556000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.023820 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.023820 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.058946 # mshr miss rate for WriteReq accesses @@ -191,31 +191,31 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.037633 system.cpu.dcache.demand_mshr_miss_rate::total 0.037633 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.037633 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.037633 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61000 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61000 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 44282500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 62000 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 62000 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62000 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 62000 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 62000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 62000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 62000 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 44698500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 151.748662 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 151.480746 # Cycle average of tags in use system.cpu.icache.tags.total_refs 14928 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 280 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 53.314286 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 151.748662 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.074096 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.074096 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 151.480746 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.073965 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.073965 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 280 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 45 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 235 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.136719 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 30696 # Number of tag accesses system.cpu.icache.tags.data_accesses 30696 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 44282500 # Cumulative time (in ticks) in various power states +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 44698500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 14928 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 14928 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 14928 # number of demand (read+write) hits @@ -228,12 +228,12 @@ system.cpu.icache.demand_misses::cpu.inst 280 # n system.cpu.icache.demand_misses::total 280 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 280 # number of overall misses system.cpu.icache.overall_misses::total 280 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 17264500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 17264500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 17264500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 17264500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 17264500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 17264500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 17542500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 17542500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 17542500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 17542500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 17542500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 17542500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 15208 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 15208 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 15208 # number of demand (read+write) accesses @@ -246,12 +246,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.018411 system.cpu.icache.demand_miss_rate::total 0.018411 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.018411 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.018411 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61658.928571 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 61658.928571 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 61658.928571 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 61658.928571 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 61658.928571 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 61658.928571 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62651.785714 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 62651.785714 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 62651.785714 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 62651.785714 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 62651.785714 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 62651.785714 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -264,43 +264,43 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 280 system.cpu.icache.demand_mshr_misses::total 280 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 280 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 280 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16984500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 16984500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16984500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 16984500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16984500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 16984500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17262500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 17262500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17262500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 17262500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17262500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 17262500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.018411 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.018411 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.018411 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.018411 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.018411 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.018411 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60658.928571 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60658.928571 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60658.928571 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 60658.928571 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60658.928571 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 60658.928571 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 44282500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61651.785714 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61651.785714 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61651.785714 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 61651.785714 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61651.785714 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 61651.785714 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 44698500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 182.297739 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 247.870917 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 331 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.006042 # Average number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 416 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.004808 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 151.068800 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 31.228940 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004610 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.000953 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.005563 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 331 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_blocks::cpu.inst 150.801148 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 97.069768 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004602 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.002962 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.007564 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 416 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 276 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.010101 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 361 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012695 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 3760 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 3760 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 44282500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 44698500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2 # number of ReadCleanReq hits system.cpu.l2cache.ReadCleanReq_hits::total 2 # number of ReadCleanReq hits system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits @@ -319,18 +319,18 @@ system.cpu.l2cache.demand_misses::total 416 # nu system.cpu.l2cache.overall_misses::cpu.inst 278 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 138 # number of overall misses system.cpu.l2cache.overall_misses::total 416 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5057500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 5057500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 16541500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 16541500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 3153500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 3153500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 16541500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 8211000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 24752500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 16541500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 8211000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 24752500 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5142500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 5142500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 16819500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 16819500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 3206500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 3206500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 16819500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 8349000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 25168500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 16819500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 8349000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 25168500 # number of overall miss cycles system.cpu.l2cache.ReadExReq_accesses::cpu.data 85 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 85 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 280 # number of ReadCleanReq accesses(hits+misses) @@ -355,18 +355,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.995215 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.992857 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.995215 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59501.798561 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59501.798561 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59501.798561 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59500 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 59501.201923 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59501.798561 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 59501.201923 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60501.798561 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60501.798561 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60500 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60500 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60501.798561 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60500 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 60501.201923 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60501.798561 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60500 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 60501.201923 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -385,18 +385,18 @@ system.cpu.l2cache.demand_mshr_misses::total 416 system.cpu.l2cache.overall_mshr_misses::cpu.inst 278 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 416 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4207500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4207500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 13761500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 13761500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2623500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2623500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 13761500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6831000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 20592500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 13761500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6831000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 20592500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4292500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4292500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 14039500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 14039500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2676500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2676500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 14039500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6969000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 21008500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 14039500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6969000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 21008500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.992857 # mshr miss rate for ReadCleanReq accesses @@ -409,25 +409,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.995215 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.992857 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.995215 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49501.798561 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49501.798561 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49501.798561 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49501.201923 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49501.798561 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49501.201923 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50501.798561 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50501.798561 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50501.798561 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50501.201923 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50501.798561 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50501.201923 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 418 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 2 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 44282500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 44698500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 333 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 85 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 85 # Transaction distribution @@ -458,7 +458,13 @@ system.cpu.toL2Bus.respLayer0.occupancy 420000 # La system.cpu.toL2Bus.respLayer0.utilization 0.9 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 207000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 44282500 # Cumulative time (in ticks) in various power states +system.membus.snoop_filter.tot_requests 416 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 44698500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 331 # Transaction distribution system.membus.trans_dist::ReadExReq 85 # Transaction distribution system.membus.trans_dist::ReadExResp 85 # Transaction distribution diff --git a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/stats.txt b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/stats.txt index 9f33ca572..f8c482cd0 100644 --- a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/stats.txt +++ b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000405 # Number of seconds simulated -sim_ticks 405365000 # Number of ticks simulated -final_tick 405365000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000415 # Number of seconds simulated +sim_ticks 414695000 # Number of ticks simulated +final_tick 414695000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 357720 # Simulator instruction rate (inst/s) -host_op_rate 357500 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 22445039511 # Simulator tick rate (ticks/s) -host_mem_usage 631720 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host +host_inst_rate 187951 # Simulator instruction rate (inst/s) +host_op_rate 187881 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 12069868237 # Simulator tick rate (ticks/s) +host_mem_usage 635076 # Number of bytes of host memory used +host_seconds 0.03 # Real time elapsed on the host sim_insts 6453 # Number of instructions simulated sim_ops 6453 # Number of ops (including micro ops) simulated system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 405365000 # Cumulative time (in ticks) in various power states +system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 414695000 # Cumulative time (in ticks) in various power states system.mem_ctrl.bytes_read::cpu.inst 25852 # Number of bytes read from this memory system.mem_ctrl.bytes_read::cpu.data 8844 # Number of bytes read from this memory system.mem_ctrl.bytes_read::total 34696 # Number of bytes read from this memory @@ -26,63 +26,63 @@ system.mem_ctrl.num_reads::cpu.data 1190 # Nu system.mem_ctrl.num_reads::total 7653 # Number of read requests responded to by this memory system.mem_ctrl.num_writes::cpu.data 865 # Number of write requests responded to by this memory system.mem_ctrl.num_writes::total 865 # Number of write requests responded to by this memory -system.mem_ctrl.bw_read::cpu.inst 63774623 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::cpu.data 21817374 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::total 85591997 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::cpu.inst 63774623 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::total 63774623 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_write::cpu.data 16518446 # Write bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_write::total 16518446 # Write bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.inst 63774623 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.data 38335821 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::total 102110444 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_read::cpu.inst 62339792 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_read::cpu.data 21326517 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_read::total 83666309 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_inst_read::cpu.inst 62339792 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_inst_read::total 62339792 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_write::cpu.data 16146807 # Write bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_write::total 16146807 # Write bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_total::cpu.inst 62339792 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_total::cpu.data 37473324 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_total::total 99813116 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrl.readReqs 7654 # Number of read requests accepted system.mem_ctrl.writeReqs 865 # Number of write requests accepted system.mem_ctrl.readBursts 7654 # Number of DRAM read bursts, including those serviced by the write queue system.mem_ctrl.writeBursts 865 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrl.bytesReadDRAM 477504 # Total number of bytes read from DRAM -system.mem_ctrl.bytesReadWrQ 12352 # Total number of bytes read from write queue +system.mem_ctrl.bytesReadDRAM 478016 # Total number of bytes read from DRAM +system.mem_ctrl.bytesReadWrQ 11840 # Total number of bytes read from write queue system.mem_ctrl.bytesWritten 6144 # Total number of bytes written to DRAM system.mem_ctrl.bytesReadSys 34700 # Total read bytes from the system interface side system.mem_ctrl.bytesWrittenSys 6696 # Total written bytes from the system interface side -system.mem_ctrl.servicedByWrQ 193 # Number of DRAM read bursts serviced by the write queue -system.mem_ctrl.mergedWrBursts 747 # Number of DRAM write bursts merged with an existing one +system.mem_ctrl.servicedByWrQ 185 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrl.mergedWrBursts 746 # Number of DRAM write bursts merged with an existing one system.mem_ctrl.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.mem_ctrl.perBankRdBursts::0 1736 # Per bank write bursts system.mem_ctrl.perBankRdBursts::1 393 # Per bank write bursts system.mem_ctrl.perBankRdBursts::2 768 # Per bank write bursts system.mem_ctrl.perBankRdBursts::3 800 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::4 763 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::4 766 # Per bank write bursts system.mem_ctrl.perBankRdBursts::5 293 # Per bank write bursts system.mem_ctrl.perBankRdBursts::6 6 # Per bank write bursts system.mem_ctrl.perBankRdBursts::7 26 # Per bank write bursts system.mem_ctrl.perBankRdBursts::8 0 # Per bank write bursts system.mem_ctrl.perBankRdBursts::9 1 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::10 253 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::10 257 # Per bank write bursts system.mem_ctrl.perBankRdBursts::11 578 # Per bank write bursts system.mem_ctrl.perBankRdBursts::12 167 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::13 1430 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::13 1431 # Per bank write bursts system.mem_ctrl.perBankRdBursts::14 89 # Per bank write bursts system.mem_ctrl.perBankRdBursts::15 158 # Per bank write bursts system.mem_ctrl.perBankWrBursts::0 0 # Per bank write bursts system.mem_ctrl.perBankWrBursts::1 0 # Per bank write bursts system.mem_ctrl.perBankWrBursts::2 0 # Per bank write bursts system.mem_ctrl.perBankWrBursts::3 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::4 18 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::5 8 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::4 26 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::5 3 # Per bank write bursts system.mem_ctrl.perBankWrBursts::6 0 # Per bank write bursts system.mem_ctrl.perBankWrBursts::7 0 # Per bank write bursts system.mem_ctrl.perBankWrBursts::8 0 # Per bank write bursts system.mem_ctrl.perBankWrBursts::9 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::10 6 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::10 5 # Per bank write bursts system.mem_ctrl.perBankWrBursts::11 0 # Per bank write bursts system.mem_ctrl.perBankWrBursts::12 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::13 21 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::14 43 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::13 18 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::14 44 # Per bank write bursts system.mem_ctrl.perBankWrBursts::15 0 # Per bank write bursts system.mem_ctrl.numRdRetry 0 # Number of times read queue was full causing retry system.mem_ctrl.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrl.totGap 405289000 # Total gap between requests +system.mem_ctrl.totGap 414618000 # Total gap between requests system.mem_ctrl.readPktSize::0 0 # Read request sizes (log2) system.mem_ctrl.readPktSize::1 0 # Read request sizes (log2) system.mem_ctrl.readPktSize::2 6633 # Read request sizes (log2) @@ -97,7 +97,7 @@ system.mem_ctrl.writePktSize::3 809 # Wr system.mem_ctrl.writePktSize::4 0 # Write request sizes (log2) system.mem_ctrl.writePktSize::5 0 # Write request sizes (log2) system.mem_ctrl.writePktSize::6 0 # Write request sizes (log2) -system.mem_ctrl.rdQLenPdf::0 7461 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::0 7469 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::1 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::2 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::3 0 # What read queue length does an incoming req see @@ -151,7 +151,7 @@ system.mem_ctrl.wrQLenPdf::18 7 # Wh system.mem_ctrl.wrQLenPdf::19 7 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::20 7 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::21 7 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::22 6 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::22 7 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::23 6 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::24 6 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::25 6 # What write queue length does an incoming req see @@ -193,86 +193,87 @@ system.mem_ctrl.wrQLenPdf::60 0 # Wh system.mem_ctrl.wrQLenPdf::61 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::62 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrl.bytesPerActivate::samples 762 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::mean 634.288714 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::gmean 419.900652 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::stdev 405.302633 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::0-127 146 19.16% 19.16% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::128-255 69 9.06% 28.22% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::256-383 39 5.12% 33.33% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::384-511 43 5.64% 38.98% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::512-639 44 5.77% 44.75% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::640-767 27 3.54% 48.29% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::768-895 31 4.07% 52.36% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::896-1023 30 3.94% 56.30% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::1024-1151 333 43.70% 100.00% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::total 762 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::samples 765 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::mean 630.044444 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::gmean 420.142008 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::stdev 402.263677 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::0-127 142 18.56% 18.56% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::128-255 72 9.41% 27.97% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::256-383 39 5.10% 33.07% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::384-511 50 6.54% 39.61% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::512-639 49 6.41% 46.01% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::640-767 26 3.40% 49.41% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::768-895 27 3.53% 52.94% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::896-1023 39 5.10% 58.04% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::1024-1151 321 41.96% 100.00% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::total 765 # Bytes accessed per row activation system.mem_ctrl.rdPerTurnAround::samples 6 # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::mean 1203.833333 # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::gmean 1052.985580 # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::stdev 699.444184 # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::512-639 2 33.33% 33.33% # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::896-1023 1 16.67% 50.00% # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::1152-1279 1 16.67% 66.67% # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::1408-1535 1 16.67% 83.33% # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::2432-2559 1 16.67% 100.00% # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::mean 1155.166667 # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::gmean 1053.155116 # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::stdev 490.786070 # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::512-575 1 16.67% 16.67% # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::576-639 1 16.67% 33.33% # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::1152-1215 1 16.67% 50.00% # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::1280-1343 1 16.67% 66.67% # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::1408-1471 1 16.67% 83.33% # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::1728-1791 1 16.67% 100.00% # Reads before turning the bus around for writes system.mem_ctrl.rdPerTurnAround::total 6 # Reads before turning the bus around for writes system.mem_ctrl.wrPerTurnAround::samples 6 # Writes before turning the bus around for reads system.mem_ctrl.wrPerTurnAround::mean 16 # Writes before turning the bus around for reads system.mem_ctrl.wrPerTurnAround::gmean 16.000000 # Writes before turning the bus around for reads system.mem_ctrl.wrPerTurnAround::16 6 100.00% 100.00% # Writes before turning the bus around for reads system.mem_ctrl.wrPerTurnAround::total 6 # Writes before turning the bus around for reads -system.mem_ctrl.totQLat 26088750 # Total ticks spent queuing -system.mem_ctrl.totMemAccLat 165982500 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrl.totBusLat 37305000 # Total ticks spent in databus transfers -system.mem_ctrl.avgQLat 3496.68 # Average queueing delay per DRAM burst +system.mem_ctrl.totQLat 26666250 # Total ticks spent queuing +system.mem_ctrl.totMemAccLat 166710000 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrl.totBusLat 37345000 # Total ticks spent in databus transfers +system.mem_ctrl.avgQLat 3570.26 # Average queueing delay per DRAM burst system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.mem_ctrl.avgMemAccLat 22246.68 # Average memory access latency per DRAM burst -system.mem_ctrl.avgRdBW 1177.96 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrl.avgWrBW 15.16 # Average achieved write bandwidth in MiByte/s -system.mem_ctrl.avgRdBWSys 85.60 # Average system read bandwidth in MiByte/s -system.mem_ctrl.avgWrBWSys 16.52 # Average system write bandwidth in MiByte/s +system.mem_ctrl.avgMemAccLat 22320.26 # Average memory access latency per DRAM burst +system.mem_ctrl.avgRdBW 1152.69 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrl.avgWrBW 14.82 # Average achieved write bandwidth in MiByte/s +system.mem_ctrl.avgRdBWSys 83.68 # Average system read bandwidth in MiByte/s +system.mem_ctrl.avgWrBWSys 16.15 # Average system write bandwidth in MiByte/s system.mem_ctrl.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrl.busUtil 9.32 # Data bus utilization in percentage -system.mem_ctrl.busUtilRead 9.20 # Data bus utilization in percentage for reads +system.mem_ctrl.busUtil 9.12 # Data bus utilization in percentage +system.mem_ctrl.busUtilRead 9.01 # Data bus utilization in percentage for reads system.mem_ctrl.busUtilWrite 0.12 # Data bus utilization in percentage for writes system.mem_ctrl.avgRdQLen 1.00 # Average read queue length when enqueuing -system.mem_ctrl.avgWrQLen 24.34 # Average write queue length when enqueuing -system.mem_ctrl.readRowHits 6706 # Number of row buffer hits during reads +system.mem_ctrl.avgWrQLen 22.92 # Average write queue length when enqueuing +system.mem_ctrl.readRowHits 6707 # Number of row buffer hits during reads system.mem_ctrl.writeRowHits 88 # Number of row buffer hits during writes -system.mem_ctrl.readRowHitRate 89.88 # Row buffer hit rate for reads -system.mem_ctrl.writeRowHitRate 74.58 # Row buffer hit rate for writes -system.mem_ctrl.avgGap 47574.72 # Average gap between requests -system.mem_ctrl.pageHitRate 89.64 # Row buffer hit rate, read and write combined -system.mem_ctrl_0.actEnergy 3333960 # Energy for activate commands per rank (pJ) -system.mem_ctrl_0.preEnergy 1819125 # Energy for precharge commands per rank (pJ) -system.mem_ctrl_0.readEnergy 37284000 # Energy for read commands per rank (pJ) -system.mem_ctrl_0.writeEnergy 168480 # Energy for write commands per rank (pJ) -system.mem_ctrl_0.refreshEnergy 26445120 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_0.actBackEnergy 262765440 # Energy for active background per rank (pJ) -system.mem_ctrl_0.preBackEnergy 12591750 # Energy for precharge background per rank (pJ) -system.mem_ctrl_0.totalEnergy 344407875 # Total energy per rank (pJ) -system.mem_ctrl_0.averagePower 850.082840 # Core power per rank (mW) -system.mem_ctrl_0.memoryStateTime::IDLE 17896000 # Time in different power states -system.mem_ctrl_0.memoryStateTime::REF 13520000 # Time in different power states +system.mem_ctrl.readRowHitRate 89.80 # Row buffer hit rate for reads +system.mem_ctrl.writeRowHitRate 73.95 # Row buffer hit rate for writes +system.mem_ctrl.avgGap 48669.80 # Average gap between requests +system.mem_ctrl.pageHitRate 89.55 # Row buffer hit rate, read and write combined +system.mem_ctrl_0.actEnergy 3409560 # Energy for activate commands per rank (pJ) +system.mem_ctrl_0.preEnergy 1860375 # Energy for precharge commands per rank (pJ) +system.mem_ctrl_0.readEnergy 37159200 # Energy for read commands per rank (pJ) +system.mem_ctrl_0.writeEnergy 187920 # Energy for write commands per rank (pJ) +system.mem_ctrl_0.refreshEnergy 26953680 # Energy for refresh commands per rank (pJ) +system.mem_ctrl_0.actBackEnergy 262129320 # Energy for active background per rank (pJ) +system.mem_ctrl_0.preBackEnergy 17820750 # Energy for precharge background per rank (pJ) +system.mem_ctrl_0.totalEnergy 349520805 # Total energy per rank (pJ) +system.mem_ctrl_0.averagePower 846.438251 # Core power per rank (mW) +system.mem_ctrl_0.memoryStateTime::IDLE 26708250 # Time in different power states +system.mem_ctrl_0.memoryStateTime::REF 13780000 # Time in different power states system.mem_ctrl_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrl_0.memoryStateTime::ACT 373743250 # Time in different power states +system.mem_ctrl_0.memoryStateTime::ACT 372456750 # Time in different power states system.mem_ctrl_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrl_1.actEnergy 2426760 # Energy for activate commands per rank (pJ) -system.mem_ctrl_1.preEnergy 1324125 # Energy for precharge commands per rank (pJ) -system.mem_ctrl_1.readEnergy 20872800 # Energy for read commands per rank (pJ) -system.mem_ctrl_1.writeEnergy 453600 # Energy for write commands per rank (pJ) -system.mem_ctrl_1.refreshEnergy 26445120 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_1.actBackEnergy 229562370 # Energy for active background per rank (pJ) -system.mem_ctrl_1.preBackEnergy 41716500 # Energy for precharge background per rank (pJ) -system.mem_ctrl_1.totalEnergy 322801275 # Total energy per rank (pJ) -system.mem_ctrl_1.averagePower 796.754927 # Core power per rank (mW) -system.mem_ctrl_1.memoryStateTime::IDLE 67586500 # Time in different power states -system.mem_ctrl_1.memoryStateTime::REF 13520000 # Time in different power states +system.mem_ctrl_1.actEnergy 2373840 # Energy for activate commands per rank (pJ) +system.mem_ctrl_1.preEnergy 1295250 # Energy for precharge commands per rank (pJ) +system.mem_ctrl_1.readEnergy 20833800 # Energy for read commands per rank (pJ) +system.mem_ctrl_1.writeEnergy 434160 # Energy for write commands per rank (pJ) +system.mem_ctrl_1.refreshEnergy 26953680 # Energy for refresh commands per rank (pJ) +system.mem_ctrl_1.actBackEnergy 231001335 # Energy for active background per rank (pJ) +system.mem_ctrl_1.preBackEnergy 45144000 # Energy for precharge background per rank (pJ) +system.mem_ctrl_1.totalEnergy 328036065 # Total energy per rank (pJ) +system.mem_ctrl_1.averagePower 794.350717 # Core power per rank (mW) +system.mem_ctrl_1.memoryStateTime::IDLE 73389500 # Time in different power states +system.mem_ctrl_1.memoryStateTime::REF 13780000 # Time in different power states system.mem_ctrl_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrl_1.memoryStateTime::ACT 324052250 # Time in different power states +system.mem_ctrl_1.memoryStateTime::ACT 325838500 # Time in different power states system.mem_ctrl_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 405365000 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 414695000 # Cumulative time (in ticks) in various power states system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -306,8 +307,8 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 405365000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 405365 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 414695000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 414695 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 6453 # Number of instructions committed @@ -326,7 +327,7 @@ system.cpu.num_mem_refs 2065 # nu system.cpu.num_load_insts 1197 # Number of load instructions system.cpu.num_store_insts 868 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 405365 # Number of busy cycles +system.cpu.num_busy_cycles 414695 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 1060 # Number of branches fetched @@ -365,7 +366,13 @@ system.cpu.op_class::MemWrite 868 13.43% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 6463 # Class of executed instruction -system.membus.pwrStateResidencyTicks::UNDEFINED 405365000 # Cumulative time (in ticks) in various power states +system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 414695000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 7654 # Transaction distribution system.membus.trans_dist::ReadResp 7653 # Transaction distribution system.membus.trans_dist::WriteReq 865 # Transaction distribution @@ -379,20 +386,20 @@ system.membus.pkt_size::total 41392 # Cu system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) system.membus.snoop_fanout::samples 8519 # Request fanout histogram -system.membus.snoop_fanout::mean 0.758775 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.427852 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 2055 24.12% 24.12% # Request fanout histogram -system.membus.snoop_fanout::1 6464 75.88% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 8519 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 8519 # Request fanout histogram system.membus.reqLayer0.occupancy 9384000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.3 # Layer utilization (%) -system.membus.respLayer0.occupancy 14690750 # Layer occupancy (ticks) -system.membus.respLayer0.utilization 3.6 # Layer utilization (%) -system.membus.respLayer1.occupancy 3574500 # Layer occupancy (ticks) +system.membus.respLayer0.occupancy 14691750 # Layer occupancy (ticks) +system.membus.respLayer0.utilization 3.5 # Layer utilization (%) +system.membus.respLayer1.occupancy 3578000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.9 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/stats.txt b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/stats.txt index 674c577ef..1f58ca472 100644 --- a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/stats.txt +++ b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000061 # Number of seconds simulated -sim_ticks 61470000 # Number of ticks simulated -final_tick 61470000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000062 # Number of seconds simulated +sim_ticks 62213000 # Number of ticks simulated +final_tick 62213000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 601148 # Simulator instruction rate (inst/s) -host_op_rate 600523 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5715150644 # Simulator tick rate (ticks/s) -host_mem_usage 635816 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host +host_inst_rate 276862 # Simulator instruction rate (inst/s) +host_op_rate 276760 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2667377590 # Simulator tick rate (ticks/s) +host_mem_usage 639424 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host sim_insts 6453 # Number of instructions simulated sim_ops 6453 # Number of ops (including micro ops) simulated system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 61470000 # Cumulative time (in ticks) in various power states +system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 62213000 # Cumulative time (in ticks) in various power states system.mem_ctrl.bytes_read::cpu.inst 17792 # Number of bytes read from this memory system.mem_ctrl.bytes_read::cpu.data 10752 # Number of bytes read from this memory system.mem_ctrl.bytes_read::total 28544 # Number of bytes read from this memory @@ -22,14 +22,14 @@ system.mem_ctrl.bytes_inst_read::total 17792 # Nu system.mem_ctrl.num_reads::cpu.inst 278 # Number of read requests responded to by this memory system.mem_ctrl.num_reads::cpu.data 168 # Number of read requests responded to by this memory system.mem_ctrl.num_reads::total 446 # Number of read requests responded to by this memory -system.mem_ctrl.bw_read::cpu.inst 289442004 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::cpu.data 174914592 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::total 464356597 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::cpu.inst 289442004 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::total 289442004 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.inst 289442004 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.data 174914592 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::total 464356597 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_read::cpu.inst 285985244 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_read::cpu.data 172825615 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_read::total 458810859 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_inst_read::cpu.inst 285985244 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_inst_read::total 285985244 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_total::cpu.inst 285985244 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_total::cpu.data 172825615 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_total::total 458810859 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrl.readReqs 446 # Number of read requests accepted system.mem_ctrl.writeReqs 0 # Number of write requests accepted system.mem_ctrl.readBursts 446 # Number of DRAM read bursts, including those serviced by the write queue @@ -76,7 +76,7 @@ system.mem_ctrl.perBankWrBursts::14 0 # Pe system.mem_ctrl.perBankWrBursts::15 0 # Per bank write bursts system.mem_ctrl.numRdRetry 0 # Number of times read queue was full causing retry system.mem_ctrl.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrl.totGap 61220000 # Total gap between requests +system.mem_ctrl.totGap 61962000 # Total gap between requests system.mem_ctrl.readPktSize::0 0 # Read request sizes (log2) system.mem_ctrl.readPktSize::1 0 # Read request sizes (log2) system.mem_ctrl.readPktSize::2 0 # Read request sizes (log2) @@ -188,69 +188,69 @@ system.mem_ctrl.wrQLenPdf::61 0 # Wh system.mem_ctrl.wrQLenPdf::62 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::63 0 # What write queue length does an incoming req see system.mem_ctrl.bytesPerActivate::samples 95 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::mean 270.821053 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::gmean 180.792132 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::stdev 259.793616 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::0-127 28 29.47% 29.47% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::128-255 29 30.53% 60.00% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::256-383 12 12.63% 72.63% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::384-511 9 9.47% 82.11% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::512-639 5 5.26% 87.37% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::mean 270.147368 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::gmean 185.768755 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::stdev 255.860208 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::0-127 22 23.16% 23.16% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::128-255 36 37.89% 61.05% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::256-383 14 14.74% 75.79% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::384-511 5 5.26% 81.05% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::512-639 6 6.32% 87.37% # Bytes accessed per row activation system.mem_ctrl.bytesPerActivate::640-767 6 6.32% 93.68% # Bytes accessed per row activation system.mem_ctrl.bytesPerActivate::768-895 1 1.05% 94.74% # Bytes accessed per row activation system.mem_ctrl.bytesPerActivate::1024-1151 5 5.26% 100.00% # Bytes accessed per row activation system.mem_ctrl.bytesPerActivate::total 95 # Bytes accessed per row activation -system.mem_ctrl.totQLat 3294500 # Total ticks spent queuing -system.mem_ctrl.totMemAccLat 11657000 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrl.totQLat 3590750 # Total ticks spent queuing +system.mem_ctrl.totMemAccLat 11953250 # Total ticks spent from burst creation until serviced by the DRAM system.mem_ctrl.totBusLat 2230000 # Total ticks spent in databus transfers -system.mem_ctrl.avgQLat 7386.77 # Average queueing delay per DRAM burst +system.mem_ctrl.avgQLat 8051.01 # Average queueing delay per DRAM burst system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.mem_ctrl.avgMemAccLat 26136.77 # Average memory access latency per DRAM burst -system.mem_ctrl.avgRdBW 464.36 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrl.avgMemAccLat 26801.01 # Average memory access latency per DRAM burst +system.mem_ctrl.avgRdBW 458.81 # Average DRAM read bandwidth in MiByte/s system.mem_ctrl.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.mem_ctrl.avgRdBWSys 464.36 # Average system read bandwidth in MiByte/s +system.mem_ctrl.avgRdBWSys 458.81 # Average system read bandwidth in MiByte/s system.mem_ctrl.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.mem_ctrl.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrl.busUtil 3.63 # Data bus utilization in percentage -system.mem_ctrl.busUtilRead 3.63 # Data bus utilization in percentage for reads +system.mem_ctrl.busUtil 3.58 # Data bus utilization in percentage +system.mem_ctrl.busUtilRead 3.58 # Data bus utilization in percentage for reads system.mem_ctrl.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.mem_ctrl.avgRdQLen 1.00 # Average read queue length when enqueuing system.mem_ctrl.avgWrQLen 0.00 # Average write queue length when enqueuing -system.mem_ctrl.readRowHits 341 # Number of row buffer hits during reads +system.mem_ctrl.readRowHits 340 # Number of row buffer hits during reads system.mem_ctrl.writeRowHits 0 # Number of row buffer hits during writes -system.mem_ctrl.readRowHitRate 76.46 # Row buffer hit rate for reads +system.mem_ctrl.readRowHitRate 76.23 # Row buffer hit rate for reads system.mem_ctrl.writeRowHitRate nan # Row buffer hit rate for writes -system.mem_ctrl.avgGap 137264.57 # Average gap between requests -system.mem_ctrl.pageHitRate 76.46 # Row buffer hit rate, read and write combined +system.mem_ctrl.avgGap 138928.25 # Average gap between requests +system.mem_ctrl.pageHitRate 76.23 # Row buffer hit rate, read and write combined system.mem_ctrl_0.actEnergy 309960 # Energy for activate commands per rank (pJ) system.mem_ctrl_0.preEnergy 169125 # Energy for precharge commands per rank (pJ) -system.mem_ctrl_0.readEnergy 1591200 # Energy for read commands per rank (pJ) +system.mem_ctrl_0.readEnergy 1583400 # Energy for read commands per rank (pJ) system.mem_ctrl_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.mem_ctrl_0.refreshEnergy 3559920 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_0.actBackEnergy 37059120 # Energy for active background per rank (pJ) -system.mem_ctrl_0.preBackEnergy 350250 # Energy for precharge background per rank (pJ) -system.mem_ctrl_0.totalEnergy 43039575 # Total energy per rank (pJ) -system.mem_ctrl_0.averagePower 785.913583 # Core power per rank (mW) -system.mem_ctrl_0.memoryStateTime::IDLE 388750 # Time in different power states +system.mem_ctrl_0.actBackEnergy 37021500 # Energy for active background per rank (pJ) +system.mem_ctrl_0.preBackEnergy 383250 # Energy for precharge background per rank (pJ) +system.mem_ctrl_0.totalEnergy 43027155 # Total energy per rank (pJ) +system.mem_ctrl_0.averagePower 785.686791 # Core power per rank (mW) +system.mem_ctrl_0.memoryStateTime::IDLE 966000 # Time in different power states system.mem_ctrl_0.memoryStateTime::REF 1820000 # Time in different power states system.mem_ctrl_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrl_0.memoryStateTime::ACT 52568750 # Time in different power states +system.mem_ctrl_0.memoryStateTime::ACT 52514000 # Time in different power states system.mem_ctrl_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrl_1.actEnergy 385560 # Energy for activate commands per rank (pJ) -system.mem_ctrl_1.preEnergy 210375 # Energy for precharge commands per rank (pJ) -system.mem_ctrl_1.readEnergy 1489800 # Energy for read commands per rank (pJ) +system.mem_ctrl_1.actEnergy 370440 # Energy for activate commands per rank (pJ) +system.mem_ctrl_1.preEnergy 202125 # Energy for precharge commands per rank (pJ) +system.mem_ctrl_1.readEnergy 1466400 # Energy for read commands per rank (pJ) system.mem_ctrl_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.mem_ctrl_1.refreshEnergy 3559920 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_1.actBackEnergy 35948475 # Energy for active background per rank (pJ) -system.mem_ctrl_1.preBackEnergy 1324500 # Energy for precharge background per rank (pJ) -system.mem_ctrl_1.totalEnergy 42918630 # Total energy per rank (pJ) -system.mem_ctrl_1.averagePower 783.705097 # Core power per rank (mW) -system.mem_ctrl_1.memoryStateTime::IDLE 2128500 # Time in different power states +system.mem_ctrl_1.actBackEnergy 35989515 # Energy for active background per rank (pJ) +system.mem_ctrl_1.preBackEnergy 1288500 # Energy for precharge background per rank (pJ) +system.mem_ctrl_1.totalEnergy 42876900 # Total energy per rank (pJ) +system.mem_ctrl_1.averagePower 782.943096 # Core power per rank (mW) +system.mem_ctrl_1.memoryStateTime::IDLE 1815750 # Time in different power states system.mem_ctrl_1.memoryStateTime::REF 1820000 # Time in different power states system.mem_ctrl_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrl_1.memoryStateTime::ACT 51068500 # Time in different power states +system.mem_ctrl_1.memoryStateTime::ACT 51141750 # Time in different power states system.mem_ctrl_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 61470000 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 62213000 # Cumulative time (in ticks) in various power states system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -284,8 +284,8 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 61470000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 61470 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 62213000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 62213 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 6453 # Number of instructions committed @@ -304,7 +304,7 @@ system.cpu.num_mem_refs 2065 # nu system.cpu.num_load_insts 1197 # Number of load instructions system.cpu.num_store_insts 868 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 61470 # Number of busy cycles +system.cpu.num_busy_cycles 62213 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 1060 # Number of branches fetched @@ -343,23 +343,23 @@ system.cpu.op_class::MemWrite 868 13.43% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 6463 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 61470000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 62213000 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 104.645861 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 104.646393 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1887 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 168 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 11.232143 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 104.645861 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.102193 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.102193 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 104.646393 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.102194 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.102194 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 168 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 12 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 156 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.164062 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 4278 # Number of tag accesses system.cpu.dcache.tags.data_accesses 4278 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 61470000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 62213000 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 1095 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1095 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 792 # number of WriteReq hits @@ -376,14 +376,14 @@ system.cpu.dcache.demand_misses::cpu.data 168 # n system.cpu.dcache.demand_misses::total 168 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 168 # number of overall misses system.cpu.dcache.overall_misses::total 168 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 10102000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 10102000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 7278000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 7278000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 17380000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 17380000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 17380000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 17380000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 9887000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 9887000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 7630000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 7630000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 17517000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 17517000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 17517000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 17517000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1190 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1190 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) @@ -400,14 +400,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.081752 system.cpu.dcache.demand_miss_rate::total 0.081752 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.081752 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.081752 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 106336.842105 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 106336.842105 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 99698.630137 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 99698.630137 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 103452.380952 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 103452.380952 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 103452.380952 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 103452.380952 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 104073.684211 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 104073.684211 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 104520.547945 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 104520.547945 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 104267.857143 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 104267.857143 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 104267.857143 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 104267.857143 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -422,14 +422,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 168 system.cpu.dcache.demand_mshr_misses::total 168 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 168 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9912000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 9912000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7132000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 7132000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 17044000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 17044000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 17044000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 17044000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9697000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 9697000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7484000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 7484000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 17181000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 17181000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 17181000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 17181000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.079832 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.079832 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses @@ -438,31 +438,31 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.081752 system.cpu.dcache.demand_mshr_miss_rate::total 0.081752 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.081752 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.081752 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 104336.842105 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 104336.842105 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 97698.630137 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 97698.630137 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 101452.380952 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 101452.380952 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 101452.380952 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 101452.380952 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 61470000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 102073.684211 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 102073.684211 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 102520.547945 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 102520.547945 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 102267.857143 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 102267.857143 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 102267.857143 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 102267.857143 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 62213000 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 62 # number of replacements -system.cpu.icache.tags.tagsinuse 113.715440 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 113.718871 # Cycle average of tags in use system.cpu.icache.tags.total_refs 6183 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 281 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 22.003559 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 113.715440 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.444201 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.444201 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 113.718871 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.444214 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.444214 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 219 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 167 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.855469 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 13209 # Number of tag accesses system.cpu.icache.tags.data_accesses 13209 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 61470000 # Cumulative time (in ticks) in various power states +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 62213000 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 6183 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 6183 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 6183 # number of demand (read+write) hits @@ -475,12 +475,12 @@ system.cpu.icache.demand_misses::cpu.inst 281 # n system.cpu.icache.demand_misses::total 281 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 281 # number of overall misses system.cpu.icache.overall_misses::total 281 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 27952000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 27952000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 27952000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 27952000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 27952000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 27952000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 28558000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 28558000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 28558000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 28558000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 28558000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 28558000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 6464 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 6464 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 6464 # number of demand (read+write) accesses @@ -493,12 +493,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.043472 system.cpu.icache.demand_miss_rate::total 0.043472 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.043472 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.043472 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 99473.309609 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 99473.309609 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 99473.309609 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 99473.309609 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 99473.309609 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 99473.309609 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 101629.893238 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 101629.893238 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 101629.893238 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 101629.893238 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 101629.893238 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 101629.893238 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -511,31 +511,31 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 281 system.cpu.icache.demand_mshr_misses::total 281 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 281 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 281 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 27390000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 27390000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 27390000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 27390000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 27390000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 27390000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 27996000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 27996000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 27996000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 27996000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 27996000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 27996000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.043472 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.043472 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.043472 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.043472 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.043472 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.043472 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 97473.309609 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 97473.309609 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 97473.309609 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 97473.309609 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 97473.309609 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 97473.309609 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 99629.893238 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 99629.893238 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 99629.893238 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 99629.893238 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 99629.893238 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 99629.893238 # average overall mshr miss latency system.l2bus.snoop_filter.tot_requests 511 # Total number of requests made to the snoop filter. system.l2bus.snoop_filter.hit_single_requests 63 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.l2bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.l2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.l2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.l2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.l2bus.pwrStateResidencyTicks::UNDEFINED 61470000 # Cumulative time (in ticks) in various power states +system.l2bus.pwrStateResidencyTicks::UNDEFINED 62213000 # Cumulative time (in ticks) in various power states system.l2bus.trans_dist::ReadResp 376 # Transaction distribution system.l2bus.trans_dist::CleanEvict 62 # Transaction distribution system.l2bus.trans_dist::ReadExReq 73 # Transaction distribution @@ -566,25 +566,25 @@ system.l2bus.respLayer0.occupancy 843000 # La system.l2bus.respLayer0.utilization 1.4 # Layer utilization (%) system.l2bus.respLayer1.occupancy 504000 # Layer occupancy (ticks) system.l2bus.respLayer1.utilization 0.8 # Layer utilization (%) -system.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 61470000 # Cumulative time (in ticks) in various power states +system.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 62213000 # Cumulative time (in ticks) in various power states system.l2cache.tags.replacements 0 # number of replacements -system.l2cache.tags.tagsinuse 185.619069 # Cycle average of tags in use +system.l2cache.tags.tagsinuse 233.175851 # Cycle average of tags in use system.l2cache.tags.total_refs 65 # Total number of references to valid blocks. -system.l2cache.tags.sampled_refs 373 # Sample count of references to valid blocks. -system.l2cache.tags.avg_refs 0.174263 # Average number of references to valid blocks. +system.l2cache.tags.sampled_refs 446 # Sample count of references to valid blocks. +system.l2cache.tags.avg_refs 0.145740 # Average number of references to valid blocks. system.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2cache.tags.occ_blocks::cpu.inst 128.455542 # Average occupied blocks per requestor -system.l2cache.tags.occ_blocks::cpu.data 57.163528 # Average occupied blocks per requestor -system.l2cache.tags.occ_percent::cpu.inst 0.031361 # Average percentage of cache occupancy -system.l2cache.tags.occ_percent::cpu.data 0.013956 # Average percentage of cache occupancy -system.l2cache.tags.occ_percent::total 0.045317 # Average percentage of cache occupancy -system.l2cache.tags.occ_task_id_blocks::1024 373 # Occupied blocks per task id +system.l2cache.tags.occ_blocks::cpu.inst 128.472749 # Average occupied blocks per requestor +system.l2cache.tags.occ_blocks::cpu.data 104.703102 # Average occupied blocks per requestor +system.l2cache.tags.occ_percent::cpu.inst 0.031365 # Average percentage of cache occupancy +system.l2cache.tags.occ_percent::cpu.data 0.025562 # Average percentage of cache occupancy +system.l2cache.tags.occ_percent::total 0.056928 # Average percentage of cache occupancy +system.l2cache.tags.occ_task_id_blocks::1024 446 # Occupied blocks per task id system.l2cache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id -system.l2cache.tags.age_task_id_blocks_1024::1 311 # Occupied blocks per task id -system.l2cache.tags.occ_task_id_percent::1024 0.091064 # Percentage of cache occupancy per task id +system.l2cache.tags.age_task_id_blocks_1024::1 384 # Occupied blocks per task id +system.l2cache.tags.occ_task_id_percent::1024 0.108887 # Percentage of cache occupancy per task id system.l2cache.tags.tag_accesses 4534 # Number of tag accesses system.l2cache.tags.data_accesses 4534 # Number of data accesses -system.l2cache.pwrStateResidencyTicks::UNDEFINED 61470000 # Cumulative time (in ticks) in various power states +system.l2cache.pwrStateResidencyTicks::UNDEFINED 62213000 # Cumulative time (in ticks) in various power states system.l2cache.ReadSharedReq_hits::cpu.inst 3 # number of ReadSharedReq hits system.l2cache.ReadSharedReq_hits::total 3 # number of ReadSharedReq hits system.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits @@ -602,17 +602,17 @@ system.l2cache.demand_misses::total 446 # nu system.l2cache.overall_misses::cpu.inst 278 # number of overall misses system.l2cache.overall_misses::cpu.data 168 # number of overall misses system.l2cache.overall_misses::total 446 # number of overall misses -system.l2cache.ReadExReq_miss_latency::cpu.data 6913000 # number of ReadExReq miss cycles -system.l2cache.ReadExReq_miss_latency::total 6913000 # number of ReadExReq miss cycles -system.l2cache.ReadSharedReq_miss_latency::cpu.inst 26482000 # number of ReadSharedReq miss cycles -system.l2cache.ReadSharedReq_miss_latency::cpu.data 9627000 # number of ReadSharedReq miss cycles -system.l2cache.ReadSharedReq_miss_latency::total 36109000 # number of ReadSharedReq miss cycles -system.l2cache.demand_miss_latency::cpu.inst 26482000 # number of demand (read+write) miss cycles -system.l2cache.demand_miss_latency::cpu.data 16540000 # number of demand (read+write) miss cycles -system.l2cache.demand_miss_latency::total 43022000 # number of demand (read+write) miss cycles -system.l2cache.overall_miss_latency::cpu.inst 26482000 # number of overall miss cycles -system.l2cache.overall_miss_latency::cpu.data 16540000 # number of overall miss cycles -system.l2cache.overall_miss_latency::total 43022000 # number of overall miss cycles +system.l2cache.ReadExReq_miss_latency::cpu.data 7265000 # number of ReadExReq miss cycles +system.l2cache.ReadExReq_miss_latency::total 7265000 # number of ReadExReq miss cycles +system.l2cache.ReadSharedReq_miss_latency::cpu.inst 27088000 # number of ReadSharedReq miss cycles +system.l2cache.ReadSharedReq_miss_latency::cpu.data 9412000 # number of ReadSharedReq miss cycles +system.l2cache.ReadSharedReq_miss_latency::total 36500000 # number of ReadSharedReq miss cycles +system.l2cache.demand_miss_latency::cpu.inst 27088000 # number of demand (read+write) miss cycles +system.l2cache.demand_miss_latency::cpu.data 16677000 # number of demand (read+write) miss cycles +system.l2cache.demand_miss_latency::total 43765000 # number of demand (read+write) miss cycles +system.l2cache.overall_miss_latency::cpu.inst 27088000 # number of overall miss cycles +system.l2cache.overall_miss_latency::cpu.data 16677000 # number of overall miss cycles +system.l2cache.overall_miss_latency::total 43765000 # number of overall miss cycles system.l2cache.ReadExReq_accesses::cpu.data 73 # number of ReadExReq accesses(hits+misses) system.l2cache.ReadExReq_accesses::total 73 # number of ReadExReq accesses(hits+misses) system.l2cache.ReadSharedReq_accesses::cpu.inst 281 # number of ReadSharedReq accesses(hits+misses) @@ -635,17 +635,17 @@ system.l2cache.demand_miss_rate::total 0.993318 # mi system.l2cache.overall_miss_rate::cpu.inst 0.989324 # miss rate for overall accesses system.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.l2cache.overall_miss_rate::total 0.993318 # miss rate for overall accesses -system.l2cache.ReadExReq_avg_miss_latency::cpu.data 94698.630137 # average ReadExReq miss latency -system.l2cache.ReadExReq_avg_miss_latency::total 94698.630137 # average ReadExReq miss latency -system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 95258.992806 # average ReadSharedReq miss latency -system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 101336.842105 # average ReadSharedReq miss latency -system.l2cache.ReadSharedReq_avg_miss_latency::total 96806.970509 # average ReadSharedReq miss latency -system.l2cache.demand_avg_miss_latency::cpu.inst 95258.992806 # average overall miss latency -system.l2cache.demand_avg_miss_latency::cpu.data 98452.380952 # average overall miss latency -system.l2cache.demand_avg_miss_latency::total 96461.883408 # average overall miss latency -system.l2cache.overall_avg_miss_latency::cpu.inst 95258.992806 # average overall miss latency -system.l2cache.overall_avg_miss_latency::cpu.data 98452.380952 # average overall miss latency -system.l2cache.overall_avg_miss_latency::total 96461.883408 # average overall miss latency +system.l2cache.ReadExReq_avg_miss_latency::cpu.data 99520.547945 # average ReadExReq miss latency +system.l2cache.ReadExReq_avg_miss_latency::total 99520.547945 # average ReadExReq miss latency +system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 97438.848921 # average ReadSharedReq miss latency +system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 99073.684211 # average ReadSharedReq miss latency +system.l2cache.ReadSharedReq_avg_miss_latency::total 97855.227882 # average ReadSharedReq miss latency +system.l2cache.demand_avg_miss_latency::cpu.inst 97438.848921 # average overall miss latency +system.l2cache.demand_avg_miss_latency::cpu.data 99267.857143 # average overall miss latency +system.l2cache.demand_avg_miss_latency::total 98127.802691 # average overall miss latency +system.l2cache.overall_avg_miss_latency::cpu.inst 97438.848921 # average overall miss latency +system.l2cache.overall_avg_miss_latency::cpu.data 99267.857143 # average overall miss latency +system.l2cache.overall_avg_miss_latency::total 98127.802691 # average overall miss latency system.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -663,17 +663,17 @@ system.l2cache.demand_mshr_misses::total 446 # nu system.l2cache.overall_mshr_misses::cpu.inst 278 # number of overall MSHR misses system.l2cache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses system.l2cache.overall_mshr_misses::total 446 # number of overall MSHR misses -system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5453000 # number of ReadExReq MSHR miss cycles -system.l2cache.ReadExReq_mshr_miss_latency::total 5453000 # number of ReadExReq MSHR miss cycles -system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 20922000 # number of ReadSharedReq MSHR miss cycles -system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7727000 # number of ReadSharedReq MSHR miss cycles -system.l2cache.ReadSharedReq_mshr_miss_latency::total 28649000 # number of ReadSharedReq MSHR miss cycles -system.l2cache.demand_mshr_miss_latency::cpu.inst 20922000 # number of demand (read+write) MSHR miss cycles -system.l2cache.demand_mshr_miss_latency::cpu.data 13180000 # number of demand (read+write) MSHR miss cycles -system.l2cache.demand_mshr_miss_latency::total 34102000 # number of demand (read+write) MSHR miss cycles -system.l2cache.overall_mshr_miss_latency::cpu.inst 20922000 # number of overall MSHR miss cycles -system.l2cache.overall_mshr_miss_latency::cpu.data 13180000 # number of overall MSHR miss cycles -system.l2cache.overall_mshr_miss_latency::total 34102000 # number of overall MSHR miss cycles +system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5805000 # number of ReadExReq MSHR miss cycles +system.l2cache.ReadExReq_mshr_miss_latency::total 5805000 # number of ReadExReq MSHR miss cycles +system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 21528000 # number of ReadSharedReq MSHR miss cycles +system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7512000 # number of ReadSharedReq MSHR miss cycles +system.l2cache.ReadSharedReq_mshr_miss_latency::total 29040000 # number of ReadSharedReq MSHR miss cycles +system.l2cache.demand_mshr_miss_latency::cpu.inst 21528000 # number of demand (read+write) MSHR miss cycles +system.l2cache.demand_mshr_miss_latency::cpu.data 13317000 # number of demand (read+write) MSHR miss cycles +system.l2cache.demand_mshr_miss_latency::total 34845000 # number of demand (read+write) MSHR miss cycles +system.l2cache.overall_mshr_miss_latency::cpu.inst 21528000 # number of overall MSHR miss cycles +system.l2cache.overall_mshr_miss_latency::cpu.data 13317000 # number of overall MSHR miss cycles +system.l2cache.overall_mshr_miss_latency::total 34845000 # number of overall MSHR miss cycles system.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.inst 0.989324 # mshr miss rate for ReadSharedReq accesses @@ -685,18 +685,24 @@ system.l2cache.demand_mshr_miss_rate::total 0.993318 # system.l2cache.overall_mshr_miss_rate::cpu.inst 0.989324 # mshr miss rate for overall accesses system.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.l2cache.overall_mshr_miss_rate::total 0.993318 # mshr miss rate for overall accesses -system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 74698.630137 # average ReadExReq mshr miss latency -system.l2cache.ReadExReq_avg_mshr_miss_latency::total 74698.630137 # average ReadExReq mshr miss latency -system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 75258.992806 # average ReadSharedReq mshr miss latency -system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 81336.842105 # average ReadSharedReq mshr miss latency -system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76806.970509 # average ReadSharedReq mshr miss latency -system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 75258.992806 # average overall mshr miss latency -system.l2cache.demand_avg_mshr_miss_latency::cpu.data 78452.380952 # average overall mshr miss latency -system.l2cache.demand_avg_mshr_miss_latency::total 76461.883408 # average overall mshr miss latency -system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 75258.992806 # average overall mshr miss latency -system.l2cache.overall_avg_mshr_miss_latency::cpu.data 78452.380952 # average overall mshr miss latency -system.l2cache.overall_avg_mshr_miss_latency::total 76461.883408 # average overall mshr miss latency -system.membus.pwrStateResidencyTicks::UNDEFINED 61470000 # Cumulative time (in ticks) in various power states +system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 79520.547945 # average ReadExReq mshr miss latency +system.l2cache.ReadExReq_avg_mshr_miss_latency::total 79520.547945 # average ReadExReq mshr miss latency +system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 77438.848921 # average ReadSharedReq mshr miss latency +system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79073.684211 # average ReadSharedReq mshr miss latency +system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 77855.227882 # average ReadSharedReq mshr miss latency +system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 77438.848921 # average overall mshr miss latency +system.l2cache.demand_avg_mshr_miss_latency::cpu.data 79267.857143 # average overall mshr miss latency +system.l2cache.demand_avg_mshr_miss_latency::total 78127.802691 # average overall mshr miss latency +system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 77438.848921 # average overall mshr miss latency +system.l2cache.overall_avg_mshr_miss_latency::cpu.data 79267.857143 # average overall mshr miss latency +system.l2cache.overall_avg_mshr_miss_latency::total 78127.802691 # average overall mshr miss latency +system.membus.snoop_filter.tot_requests 446 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 62213000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 373 # Transaction distribution system.membus.trans_dist::ReadExReq 73 # Transaction distribution system.membus.trans_dist::ReadExResp 73 # Transaction distribution @@ -719,7 +725,7 @@ system.membus.snoop_fanout::max_value 0 # Re system.membus.snoop_fanout::total 446 # Request fanout histogram system.membus.reqLayer0.occupancy 446000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.7 # Layer utilization (%) -system.membus.respLayer0.occupancy 2375000 # Layer occupancy (ticks) -system.membus.respLayer0.utilization 3.9 # Layer utilization (%) +system.membus.respLayer0.occupancy 2375750 # Layer occupancy (ticks) +system.membus.respLayer0.utilization 3.8 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/stats.txt b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/stats.txt index b0e38a814..670cfd0c1 100644 --- a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/stats.txt +++ b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000326 # Number of seconds simulated -sim_ticks 325849000 # Number of ticks simulated -final_tick 325849000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000333 # Number of seconds simulated +sim_ticks 332645000 # Number of ticks simulated +final_tick 332645000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 174378 # Simulator instruction rate (inst/s) -host_op_rate 201529 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 11371603109 # Simulator tick rate (ticks/s) -host_mem_usage 647324 # Number of bytes of host memory used -host_seconds 0.03 # Real time elapsed on the host +host_inst_rate 141116 # Simulator instruction rate (inst/s) +host_op_rate 163173 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 9403646091 # Simulator tick rate (ticks/s) +host_mem_usage 651444 # Number of bytes of host memory used +host_seconds 0.04 # Real time elapsed on the host sim_insts 4988 # Number of instructions simulated sim_ops 5770 # Number of ops (including micro ops) simulated system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 325849000 # Cumulative time (in ticks) in various power states +system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 332645000 # Cumulative time (in ticks) in various power states system.mem_ctrl.bytes_read::cpu.inst 20108 # Number of bytes read from this memory system.mem_ctrl.bytes_read::cpu.data 4672 # Number of bytes read from this memory system.mem_ctrl.bytes_read::total 24780 # Number of bytes read from this memory @@ -26,27 +26,27 @@ system.mem_ctrl.num_reads::cpu.data 1061 # Nu system.mem_ctrl.num_reads::total 6088 # Number of read requests responded to by this memory system.mem_ctrl.num_writes::cpu.data 936 # Number of write requests responded to by this memory system.mem_ctrl.num_writes::total 936 # Number of write requests responded to by this memory -system.mem_ctrl.bw_read::cpu.inst 61709565 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::cpu.data 14337930 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::total 76047494 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::cpu.inst 61709565 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::total 61709565 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_write::cpu.data 11342677 # Write bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_write::total 11342677 # Write bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.inst 61709565 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.data 25680607 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::total 87390172 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_read::cpu.inst 60448827 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_read::cpu.data 14045003 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_read::total 74493830 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_inst_read::cpu.inst 60448827 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_inst_read::total 60448827 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_write::cpu.data 11110944 # Write bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_write::total 11110944 # Write bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_total::cpu.inst 60448827 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_total::cpu.data 25155947 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_total::total 85604774 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrl.readReqs 6089 # Number of read requests accepted system.mem_ctrl.writeReqs 936 # Number of write requests accepted system.mem_ctrl.readBursts 6089 # Number of DRAM read bursts, including those serviced by the write queue system.mem_ctrl.writeBursts 936 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrl.bytesReadDRAM 384000 # Total number of bytes read from DRAM -system.mem_ctrl.bytesReadWrQ 5696 # Total number of bytes read from write queue -system.mem_ctrl.bytesWritten 3072 # Total number of bytes written to DRAM +system.mem_ctrl.bytesReadDRAM 383296 # Total number of bytes read from DRAM +system.mem_ctrl.bytesReadWrQ 6400 # Total number of bytes read from write queue +system.mem_ctrl.bytesWritten 4096 # Total number of bytes written to DRAM system.mem_ctrl.bytesReadSys 24784 # Total read bytes from the system interface side system.mem_ctrl.bytesWrittenSys 3696 # Total written bytes from the system interface side -system.mem_ctrl.servicedByWrQ 89 # Number of DRAM read bursts serviced by the write queue -system.mem_ctrl.mergedWrBursts 856 # Number of DRAM write bursts merged with an existing one +system.mem_ctrl.servicedByWrQ 100 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrl.mergedWrBursts 855 # Number of DRAM write bursts merged with an existing one system.mem_ctrl.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.mem_ctrl.perBankRdBursts::0 911 # Per bank write bursts system.mem_ctrl.perBankRdBursts::1 1454 # Per bank write bursts @@ -58,8 +58,8 @@ system.mem_ctrl.perBankRdBursts::6 487 # Pe system.mem_ctrl.perBankRdBursts::7 206 # Per bank write bursts system.mem_ctrl.perBankRdBursts::8 42 # Per bank write bursts system.mem_ctrl.perBankRdBursts::9 155 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::10 194 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::11 431 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::10 192 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::11 422 # Per bank write bursts system.mem_ctrl.perBankRdBursts::12 108 # Per bank write bursts system.mem_ctrl.perBankRdBursts::13 36 # Per bank write bursts system.mem_ctrl.perBankRdBursts::14 0 # Per bank write bursts @@ -75,14 +75,14 @@ system.mem_ctrl.perBankWrBursts::7 0 # Pe system.mem_ctrl.perBankWrBursts::8 0 # Per bank write bursts system.mem_ctrl.perBankWrBursts::9 0 # Per bank write bursts system.mem_ctrl.perBankWrBursts::10 13 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::11 30 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::11 46 # Per bank write bursts system.mem_ctrl.perBankWrBursts::12 5 # Per bank write bursts system.mem_ctrl.perBankWrBursts::13 0 # Per bank write bursts system.mem_ctrl.perBankWrBursts::14 0 # Per bank write bursts system.mem_ctrl.perBankWrBursts::15 0 # Per bank write bursts system.mem_ctrl.numRdRetry 0 # Number of times read queue was full causing retry system.mem_ctrl.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrl.totGap 325773000 # Total gap between requests +system.mem_ctrl.totGap 332568000 # Total gap between requests system.mem_ctrl.readPktSize::0 70 # Read request sizes (log2) system.mem_ctrl.readPktSize::1 1 # Read request sizes (log2) system.mem_ctrl.readPktSize::2 5858 # Read request sizes (log2) @@ -97,7 +97,7 @@ system.mem_ctrl.writePktSize::3 0 # Wr system.mem_ctrl.writePktSize::4 0 # Write request sizes (log2) system.mem_ctrl.writePktSize::5 0 # Write request sizes (log2) system.mem_ctrl.writePktSize::6 0 # Write request sizes (log2) -system.mem_ctrl.rdQLenPdf::0 5991 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::0 5980 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::1 9 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::2 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::3 0 # What read queue length does an incoming req see @@ -161,7 +161,7 @@ system.mem_ctrl.wrQLenPdf::28 4 # Wh system.mem_ctrl.wrQLenPdf::29 4 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::30 4 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::31 4 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::32 3 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::32 4 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::33 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::34 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::35 0 # What write queue length does an incoming req see @@ -193,85 +193,86 @@ system.mem_ctrl.wrQLenPdf::60 0 # Wh system.mem_ctrl.wrQLenPdf::61 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::62 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrl.bytesPerActivate::samples 495 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::mean 775.886869 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::gmean 648.412049 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::stdev 330.044561 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::0-127 19 3.84% 3.84% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::128-255 31 6.26% 10.10% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::256-383 37 7.47% 17.58% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::384-511 33 6.67% 24.24% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::512-639 20 4.04% 28.28% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::640-767 33 6.67% 34.95% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::768-895 27 5.45% 40.40% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::896-1023 25 5.05% 45.45% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::1024-1151 270 54.55% 100.00% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::total 495 # Bytes accessed per row activation -system.mem_ctrl.rdPerTurnAround::samples 3 # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::mean 1299.666667 # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::gmean 1199.462709 # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::stdev 577.403094 # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::640-703 1 33.33% 33.33% # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::1408-1471 1 33.33% 66.67% # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::1792-1855 1 33.33% 100.00% # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::total 3 # Reads before turning the bus around for writes -system.mem_ctrl.wrPerTurnAround::samples 3 # Writes before turning the bus around for reads +system.mem_ctrl.bytesPerActivate::samples 498 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::mean 770.698795 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::gmean 632.685353 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::stdev 340.090332 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::0-127 21 4.22% 4.22% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::128-255 40 8.03% 12.25% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::256-383 36 7.23% 19.48% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::384-511 28 5.62% 25.10% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::512-639 23 4.62% 29.72% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::640-767 25 5.02% 34.74% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::768-895 24 4.82% 39.56% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::896-1023 28 5.62% 45.18% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::1024-1151 273 54.82% 100.00% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::total 498 # Bytes accessed per row activation +system.mem_ctrl.rdPerTurnAround::samples 4 # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::mean 1490.500000 # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::gmean 1373.591360 # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::stdev 606.712727 # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::640-767 1 25.00% 25.00% # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::1408-1535 1 25.00% 50.00% # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::1792-1919 1 25.00% 75.00% # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::2048-2175 1 25.00% 100.00% # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::total 4 # Reads before turning the bus around for writes +system.mem_ctrl.wrPerTurnAround::samples 4 # Writes before turning the bus around for reads system.mem_ctrl.wrPerTurnAround::mean 16 # Writes before turning the bus around for reads system.mem_ctrl.wrPerTurnAround::gmean 16.000000 # Writes before turning the bus around for reads -system.mem_ctrl.wrPerTurnAround::16 3 100.00% 100.00% # Writes before turning the bus around for reads -system.mem_ctrl.wrPerTurnAround::total 3 # Writes before turning the bus around for reads -system.mem_ctrl.totQLat 17801000 # Total ticks spent queuing -system.mem_ctrl.totMemAccLat 130301000 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrl.totBusLat 30000000 # Total ticks spent in databus transfers -system.mem_ctrl.avgQLat 2966.83 # Average queueing delay per DRAM burst +system.mem_ctrl.wrPerTurnAround::16 4 100.00% 100.00% # Writes before turning the bus around for reads +system.mem_ctrl.wrPerTurnAround::total 4 # Writes before turning the bus around for reads +system.mem_ctrl.totQLat 17899250 # Total ticks spent queuing +system.mem_ctrl.totMemAccLat 130193000 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrl.totBusLat 29945000 # Total ticks spent in databus transfers +system.mem_ctrl.avgQLat 2988.69 # Average queueing delay per DRAM burst system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.mem_ctrl.avgMemAccLat 21716.83 # Average memory access latency per DRAM burst -system.mem_ctrl.avgRdBW 1178.46 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrl.avgWrBW 9.43 # Average achieved write bandwidth in MiByte/s -system.mem_ctrl.avgRdBWSys 76.06 # Average system read bandwidth in MiByte/s -system.mem_ctrl.avgWrBWSys 11.34 # Average system write bandwidth in MiByte/s +system.mem_ctrl.avgMemAccLat 21738.69 # Average memory access latency per DRAM burst +system.mem_ctrl.avgRdBW 1152.27 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrl.avgWrBW 12.31 # Average achieved write bandwidth in MiByte/s +system.mem_ctrl.avgRdBWSys 74.51 # Average system read bandwidth in MiByte/s +system.mem_ctrl.avgWrBWSys 11.11 # Average system write bandwidth in MiByte/s system.mem_ctrl.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrl.busUtil 9.28 # Data bus utilization in percentage -system.mem_ctrl.busUtilRead 9.21 # Data bus utilization in percentage for reads -system.mem_ctrl.busUtilWrite 0.07 # Data bus utilization in percentage for writes +system.mem_ctrl.busUtil 9.10 # Data bus utilization in percentage +system.mem_ctrl.busUtilRead 9.00 # Data bus utilization in percentage for reads +system.mem_ctrl.busUtilWrite 0.10 # Data bus utilization in percentage for writes system.mem_ctrl.avgRdQLen 1.00 # Average read queue length when enqueuing -system.mem_ctrl.avgWrQLen 24.64 # Average write queue length when enqueuing -system.mem_ctrl.readRowHits 5504 # Number of row buffer hits during reads -system.mem_ctrl.writeRowHits 44 # Number of row buffer hits during writes -system.mem_ctrl.readRowHitRate 91.73 # Row buffer hit rate for reads -system.mem_ctrl.writeRowHitRate 55.00 # Row buffer hit rate for writes -system.mem_ctrl.avgGap 46373.38 # Average gap between requests -system.mem_ctrl.pageHitRate 91.25 # Row buffer hit rate, read and write combined -system.mem_ctrl_0.actEnergy 2782080 # Energy for activate commands per rank (pJ) -system.mem_ctrl_0.preEnergy 1518000 # Energy for precharge commands per rank (pJ) -system.mem_ctrl_0.readEnergy 37915800 # Energy for read commands per rank (pJ) +system.mem_ctrl.avgWrQLen 24.94 # Average write queue length when enqueuing +system.mem_ctrl.readRowHits 5487 # Number of row buffer hits during reads +system.mem_ctrl.writeRowHits 62 # Number of row buffer hits during writes +system.mem_ctrl.readRowHitRate 91.62 # Row buffer hit rate for reads +system.mem_ctrl.writeRowHitRate 76.54 # Row buffer hit rate for writes +system.mem_ctrl.avgGap 47340.64 # Average gap between requests +system.mem_ctrl.pageHitRate 91.42 # Row buffer hit rate, read and write combined +system.mem_ctrl_0.actEnergy 2812320 # Energy for activate commands per rank (pJ) +system.mem_ctrl_0.preEnergy 1534500 # Energy for precharge commands per rank (pJ) +system.mem_ctrl_0.readEnergy 38048400 # Energy for read commands per rank (pJ) system.mem_ctrl_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.mem_ctrl_0.refreshEnergy 20850960 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_0.actBackEnergy 212134050 # Energy for active background per rank (pJ) -system.mem_ctrl_0.preBackEnergy 5616000 # Energy for precharge background per rank (pJ) -system.mem_ctrl_0.totalEnergy 280816890 # Total energy per rank (pJ) -system.mem_ctrl_0.averagePower 878.932981 # Core power per rank (mW) -system.mem_ctrl_0.memoryStateTime::IDLE 6234500 # Time in different power states -system.mem_ctrl_0.memoryStateTime::REF 10660000 # Time in different power states +system.mem_ctrl_0.refreshEnergy 21359520 # Energy for refresh commands per rank (pJ) +system.mem_ctrl_0.actBackEnergy 216770715 # Energy for active background per rank (pJ) +system.mem_ctrl_0.preBackEnergy 6219750 # Energy for precharge background per rank (pJ) +system.mem_ctrl_0.totalEnergy 286745205 # Total energy per rank (pJ) +system.mem_ctrl_0.averagePower 876.139742 # Core power per rank (mW) +system.mem_ctrl_0.memoryStateTime::IDLE 7265500 # Time in different power states +system.mem_ctrl_0.memoryStateTime::REF 10920000 # Time in different power states system.mem_ctrl_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrl_0.memoryStateTime::ACT 303655500 # Time in different power states +system.mem_ctrl_0.memoryStateTime::ACT 309110750 # Time in different power states system.mem_ctrl_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.mem_ctrl_1.actEnergy 922320 # Energy for activate commands per rank (pJ) system.mem_ctrl_1.preEnergy 503250 # Energy for precharge commands per rank (pJ) -system.mem_ctrl_1.readEnergy 7932600 # Energy for read commands per rank (pJ) +system.mem_ctrl_1.readEnergy 7893600 # Energy for read commands per rank (pJ) system.mem_ctrl_1.writeEnergy 311040 # Energy for write commands per rank (pJ) -system.mem_ctrl_1.refreshEnergy 20850960 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_1.actBackEnergy 182238975 # Energy for active background per rank (pJ) -system.mem_ctrl_1.preBackEnergy 31839000 # Energy for precharge background per rank (pJ) -system.mem_ctrl_1.totalEnergy 244598145 # Total energy per rank (pJ) -system.mem_ctrl_1.averagePower 765.574385 # Core power per rank (mW) -system.mem_ctrl_1.memoryStateTime::IDLE 52679500 # Time in different power states -system.mem_ctrl_1.memoryStateTime::REF 10660000 # Time in different power states +system.mem_ctrl_1.refreshEnergy 21359520 # Energy for refresh commands per rank (pJ) +system.mem_ctrl_1.actBackEnergy 188416350 # Energy for active background per rank (pJ) +system.mem_ctrl_1.preBackEnergy 31092000 # Energy for precharge background per rank (pJ) +system.mem_ctrl_1.totalEnergy 250498080 # Total energy per rank (pJ) +system.mem_ctrl_1.averagePower 765.387945 # Core power per rank (mW) +system.mem_ctrl_1.memoryStateTime::IDLE 51038750 # Time in different power states +system.mem_ctrl_1.memoryStateTime::REF 10920000 # Time in different power states system.mem_ctrl_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrl_1.memoryStateTime::ACT 256888500 # Time in different power states +system.mem_ctrl_1.memoryStateTime::ACT 265729250 # Time in different power states system.mem_ctrl_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 325849000 # Cumulative time (in ticks) in various power states -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 325849000 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 332645000 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 332645000 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -301,7 +302,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 325849000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 332645000 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -331,7 +332,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 325849000 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 332645000 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -361,7 +362,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 325849000 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 332645000 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -392,8 +393,8 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 325849000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 325849 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 332645000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 332645 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 4988 # Number of instructions committed @@ -414,7 +415,7 @@ system.cpu.num_mem_refs 2035 # nu system.cpu.num_load_insts 1085 # Number of load instructions system.cpu.num_store_insts 950 # Number of store instructions system.cpu.num_idle_cycles 0.001000 # Number of idle cycles -system.cpu.num_busy_cycles 325848.999000 # Number of busy cycles +system.cpu.num_busy_cycles 332644.999000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 1107 # Number of branches fetched @@ -453,7 +454,13 @@ system.cpu.op_class::MemWrite 950 16.29% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 5831 # Class of executed instruction -system.membus.pwrStateResidencyTicks::UNDEFINED 325849000 # Cumulative time (in ticks) in various power states +system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 332645000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 6078 # Transaction distribution system.membus.trans_dist::ReadResp 6088 # Transaction distribution system.membus.trans_dist::WriteReq 925 # Transaction distribution @@ -470,20 +477,20 @@ system.membus.pkt_size::total 28476 # Cu system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) system.membus.snoop_fanout::samples 7025 # Request fanout histogram -system.membus.snoop_fanout::mean 0.715730 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.451098 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 1997 28.43% 28.43% # Request fanout histogram -system.membus.snoop_fanout::1 5028 71.57% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 7025 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 7025 # Request fanout histogram system.membus.reqLayer0.occupancy 7961000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.4 # Layer utilization (%) -system.membus.respLayer0.occupancy 11411750 # Layer occupancy (ticks) -system.membus.respLayer0.utilization 3.5 # Layer utilization (%) -system.membus.respLayer1.occupancy 3326000 # Layer occupancy (ticks) +system.membus.respLayer0.occupancy 11412500 # Layer occupancy (ticks) +system.membus.respLayer0.utilization 3.4 # Layer utilization (%) +system.membus.respLayer1.occupancy 3325250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/stats.txt b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/stats.txt index b14eb2f25..005f27b4b 100644 --- a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/stats.txt +++ b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000050 # Number of seconds simulated -sim_ticks 49855000 # Number of ticks simulated -final_tick 49855000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 50074000 # Number of ticks simulated +final_tick 50074000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 256506 # Simulator instruction rate (inst/s) -host_op_rate 296356 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2557788683 # Simulator tick rate (ticks/s) -host_mem_usage 651420 # Number of bytes of host memory used +host_inst_rate 207988 # Simulator instruction rate (inst/s) +host_op_rate 240459 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2085706484 # Simulator tick rate (ticks/s) +host_mem_usage 655032 # Number of bytes of host memory used host_seconds 0.02 # Real time elapsed on the host sim_insts 4988 # Number of instructions simulated sim_ops 5770 # Number of ops (including micro ops) simulated system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 49855000 # Cumulative time (in ticks) in various power states +system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 50074000 # Cumulative time (in ticks) in various power states system.mem_ctrl.bytes_read::cpu.inst 14400 # Number of bytes read from this memory system.mem_ctrl.bytes_read::cpu.data 8064 # Number of bytes read from this memory system.mem_ctrl.bytes_read::total 22464 # Number of bytes read from this memory @@ -22,14 +22,14 @@ system.mem_ctrl.bytes_inst_read::total 14400 # Nu system.mem_ctrl.num_reads::cpu.inst 225 # Number of read requests responded to by this memory system.mem_ctrl.num_reads::cpu.data 126 # Number of read requests responded to by this memory system.mem_ctrl.num_reads::total 351 # Number of read requests responded to by this memory -system.mem_ctrl.bw_read::cpu.inst 288837629 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::cpu.data 161749072 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::total 450586701 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::cpu.inst 288837629 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::total 288837629 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.inst 288837629 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.data 161749072 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::total 450586701 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_read::cpu.inst 287574390 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_read::cpu.data 161041658 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_read::total 448616048 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_inst_read::cpu.inst 287574390 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_inst_read::total 287574390 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_total::cpu.inst 287574390 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_total::cpu.data 161041658 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_total::total 448616048 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrl.readReqs 351 # Number of read requests accepted system.mem_ctrl.writeReqs 0 # Number of write requests accepted system.mem_ctrl.readBursts 351 # Number of DRAM read bursts, including those serviced by the write queue @@ -76,7 +76,7 @@ system.mem_ctrl.perBankWrBursts::14 0 # Pe system.mem_ctrl.perBankWrBursts::15 0 # Per bank write bursts system.mem_ctrl.numRdRetry 0 # Number of times read queue was full causing retry system.mem_ctrl.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrl.totGap 49757000 # Total gap between requests +system.mem_ctrl.totGap 49975000 # Total gap between requests system.mem_ctrl.readPktSize::0 0 # Read request sizes (log2) system.mem_ctrl.readPktSize::1 0 # Read request sizes (log2) system.mem_ctrl.readPktSize::2 0 # Read request sizes (log2) @@ -189,30 +189,30 @@ system.mem_ctrl.wrQLenPdf::62 0 # Wh system.mem_ctrl.wrQLenPdf::63 0 # What write queue length does an incoming req see system.mem_ctrl.bytesPerActivate::samples 73 # Bytes accessed per row activation system.mem_ctrl.bytesPerActivate::mean 300.712329 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::gmean 214.051474 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::stdev 262.513782 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::gmean 213.377798 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::stdev 265.316032 # Bytes accessed per row activation system.mem_ctrl.bytesPerActivate::0-127 14 19.18% 19.18% # Bytes accessed per row activation system.mem_ctrl.bytesPerActivate::128-255 25 34.25% 53.42% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::256-383 13 17.81% 71.23% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::384-511 6 8.22% 79.45% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::256-383 14 19.18% 72.60% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::384-511 5 6.85% 79.45% # Bytes accessed per row activation system.mem_ctrl.bytesPerActivate::512-639 7 9.59% 89.04% # Bytes accessed per row activation system.mem_ctrl.bytesPerActivate::640-767 1 1.37% 90.41% # Bytes accessed per row activation system.mem_ctrl.bytesPerActivate::768-895 2 2.74% 93.15% # Bytes accessed per row activation system.mem_ctrl.bytesPerActivate::1024-1151 5 6.85% 100.00% # Bytes accessed per row activation system.mem_ctrl.bytesPerActivate::total 73 # Bytes accessed per row activation -system.mem_ctrl.totQLat 2474000 # Total ticks spent queuing -system.mem_ctrl.totMemAccLat 9055250 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrl.totQLat 2342250 # Total ticks spent queuing +system.mem_ctrl.totMemAccLat 8923500 # Total ticks spent from burst creation until serviced by the DRAM system.mem_ctrl.totBusLat 1755000 # Total ticks spent in databus transfers -system.mem_ctrl.avgQLat 7048.43 # Average queueing delay per DRAM burst +system.mem_ctrl.avgQLat 6673.08 # Average queueing delay per DRAM burst system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.mem_ctrl.avgMemAccLat 25798.43 # Average memory access latency per DRAM burst -system.mem_ctrl.avgRdBW 450.59 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrl.avgMemAccLat 25423.08 # Average memory access latency per DRAM burst +system.mem_ctrl.avgRdBW 448.62 # Average DRAM read bandwidth in MiByte/s system.mem_ctrl.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.mem_ctrl.avgRdBWSys 450.59 # Average system read bandwidth in MiByte/s +system.mem_ctrl.avgRdBWSys 448.62 # Average system read bandwidth in MiByte/s system.mem_ctrl.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.mem_ctrl.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrl.busUtil 3.52 # Data bus utilization in percentage -system.mem_ctrl.busUtilRead 3.52 # Data bus utilization in percentage for reads +system.mem_ctrl.busUtil 3.50 # Data bus utilization in percentage +system.mem_ctrl.busUtilRead 3.50 # Data bus utilization in percentage for reads system.mem_ctrl.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.mem_ctrl.avgRdQLen 1.00 # Average read queue length when enqueuing system.mem_ctrl.avgWrQLen 0.00 # Average write queue length when enqueuing @@ -220,38 +220,38 @@ system.mem_ctrl.readRowHits 274 # Nu system.mem_ctrl.writeRowHits 0 # Number of row buffer hits during writes system.mem_ctrl.readRowHitRate 78.06 # Row buffer hit rate for reads system.mem_ctrl.writeRowHitRate nan # Row buffer hit rate for writes -system.mem_ctrl.avgGap 141757.83 # Average gap between requests +system.mem_ctrl.avgGap 142378.92 # Average gap between requests system.mem_ctrl.pageHitRate 78.06 # Row buffer hit rate, read and write combined system.mem_ctrl_0.actEnergy 347760 # Energy for activate commands per rank (pJ) system.mem_ctrl_0.preEnergy 189750 # Energy for precharge commands per rank (pJ) -system.mem_ctrl_0.readEnergy 1825200 # Energy for read commands per rank (pJ) +system.mem_ctrl_0.readEnergy 1817400 # Energy for read commands per rank (pJ) system.mem_ctrl_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.mem_ctrl_0.refreshEnergy 3051360 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_0.actBackEnergy 31479390 # Energy for active background per rank (pJ) -system.mem_ctrl_0.preBackEnergy 573750 # Energy for precharge background per rank (pJ) -system.mem_ctrl_0.totalEnergy 37467210 # Total energy per rank (pJ) -system.mem_ctrl_0.averagePower 797.535269 # Core power per rank (mW) -system.mem_ctrl_0.memoryStateTime::IDLE 1052000 # Time in different power states +system.mem_ctrl_0.actBackEnergy 31477680 # Energy for active background per rank (pJ) +system.mem_ctrl_0.preBackEnergy 574500 # Energy for precharge background per rank (pJ) +system.mem_ctrl_0.totalEnergy 37458450 # Total energy per rank (pJ) +system.mem_ctrl_0.averagePower 797.370018 # Core power per rank (mW) +system.mem_ctrl_0.memoryStateTime::IDLE 805250 # Time in different power states system.mem_ctrl_0.memoryStateTime::REF 1560000 # Time in different power states system.mem_ctrl_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrl_0.memoryStateTime::ACT 44629000 # Time in different power states +system.mem_ctrl_0.memoryStateTime::ACT 44626000 # Time in different power states system.mem_ctrl_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.mem_ctrl_1.actEnergy 189000 # Energy for activate commands per rank (pJ) system.mem_ctrl_1.preEnergy 103125 # Energy for precharge commands per rank (pJ) system.mem_ctrl_1.readEnergy 741000 # Energy for read commands per rank (pJ) system.mem_ctrl_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.mem_ctrl_1.refreshEnergy 3051360 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_1.actBackEnergy 30267855 # Energy for active background per rank (pJ) -system.mem_ctrl_1.preBackEnergy 1635750 # Energy for precharge background per rank (pJ) -system.mem_ctrl_1.totalEnergy 35988090 # Total energy per rank (pJ) -system.mem_ctrl_1.averagePower 766.070779 # Core power per rank (mW) -system.mem_ctrl_1.memoryStateTime::IDLE 2558000 # Time in different power states +system.mem_ctrl_1.actBackEnergy 30101985 # Energy for active background per rank (pJ) +system.mem_ctrl_1.preBackEnergy 1781250 # Energy for precharge background per rank (pJ) +system.mem_ctrl_1.totalEnergy 35967720 # Total energy per rank (pJ) +system.mem_ctrl_1.averagePower 765.637167 # Core power per rank (mW) +system.mem_ctrl_1.memoryStateTime::IDLE 3011750 # Time in different power states system.mem_ctrl_1.memoryStateTime::REF 1560000 # Time in different power states system.mem_ctrl_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrl_1.memoryStateTime::ACT 42873250 # Time in different power states +system.mem_ctrl_1.memoryStateTime::ACT 42630250 # Time in different power states system.mem_ctrl_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 49855000 # Cumulative time (in ticks) in various power states -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 49855000 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 50074000 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 50074000 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -281,7 +281,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 49855000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 50074000 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -311,7 +311,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 49855000 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 50074000 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -341,7 +341,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 49855000 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 50074000 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -372,8 +372,8 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 49855000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 49855 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 50074000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 50074 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 4988 # Number of instructions committed @@ -394,7 +394,7 @@ system.cpu.num_mem_refs 2035 # nu system.cpu.num_load_insts 1085 # Number of load instructions system.cpu.num_store_insts 950 # Number of store instructions system.cpu.num_idle_cycles 0.001000 # Number of idle cycles -system.cpu.num_busy_cycles 49854.999000 # Number of busy cycles +system.cpu.num_busy_cycles 50073.999000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 1107 # Number of branches fetched @@ -433,23 +433,23 @@ system.cpu.op_class::MemWrite 950 16.29% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 5831 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 49855000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 50074000 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 84.288257 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 84.375326 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1855 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 142 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 13.063380 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 84.288257 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.082313 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.082313 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 84.375326 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.082398 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.082398 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 142 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 123 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.138672 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 4136 # Number of tag accesses system.cpu.dcache.tags.data_accesses 4136 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 49855000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 50074000 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 951 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 951 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 882 # number of WriteReq hits @@ -470,14 +470,14 @@ system.cpu.dcache.demand_misses::cpu.data 142 # n system.cpu.dcache.demand_misses::total 142 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 142 # number of overall misses system.cpu.dcache.overall_misses::total 142 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 8777000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 8777000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 4411000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 4411000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 13188000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 13188000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 13188000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 13188000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 8615000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 8615000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4388000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4388000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 13003000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 13003000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 13003000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 13003000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1050 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1050 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses) @@ -498,14 +498,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.071899 system.cpu.dcache.demand_miss_rate::total 0.071899 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.071899 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.071899 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 88656.565657 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 88656.565657 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 102581.395349 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 102581.395349 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 92873.239437 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 92873.239437 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 92873.239437 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 92873.239437 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 87020.202020 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 87020.202020 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 102046.511628 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 102046.511628 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 91570.422535 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 91570.422535 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 91570.422535 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 91570.422535 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -520,14 +520,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 142 system.cpu.dcache.demand_mshr_misses::total 142 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 142 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8579000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 8579000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4325000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4325000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12904000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 12904000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12904000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 12904000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8417000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 8417000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4302000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4302000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12719000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 12719000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12719000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 12719000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.094286 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.094286 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046486 # mshr miss rate for WriteReq accesses @@ -536,31 +536,31 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.071899 system.cpu.dcache.demand_mshr_miss_rate::total 0.071899 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.071899 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.071899 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 86656.565657 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 86656.565657 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 100581.395349 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 100581.395349 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 90873.239437 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 90873.239437 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 90873.239437 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 90873.239437 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 49855000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 85020.202020 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 85020.202020 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 100046.511628 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 100046.511628 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 89570.422535 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 89570.422535 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 89570.422535 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 89570.422535 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 50074000 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 70 # number of replacements -system.cpu.icache.tags.tagsinuse 96.468360 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 96.598037 # Cycle average of tags in use system.cpu.icache.tags.total_refs 4779 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 249 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 19.192771 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 96.468360 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.376830 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.376830 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 96.598037 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.377336 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.377336 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 179 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 125 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 128 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.699219 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 10305 # Number of tag accesses system.cpu.icache.tags.data_accesses 10305 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 49855000 # Cumulative time (in ticks) in various power states +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 50074000 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 4779 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 4779 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 4779 # number of demand (read+write) hits @@ -573,12 +573,12 @@ system.cpu.icache.demand_misses::cpu.inst 249 # n system.cpu.icache.demand_misses::total 249 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 249 # number of overall misses system.cpu.icache.overall_misses::total 249 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 23411000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 23411000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 23411000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 23411000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 23411000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 23411000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 23815000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 23815000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 23815000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 23815000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 23815000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 23815000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 5028 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 5028 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 5028 # number of demand (read+write) accesses @@ -591,12 +591,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.049523 system.cpu.icache.demand_miss_rate::total 0.049523 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.049523 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.049523 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 94020.080321 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 94020.080321 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 94020.080321 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 94020.080321 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 94020.080321 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 94020.080321 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 95642.570281 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 95642.570281 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 95642.570281 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 95642.570281 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 95642.570281 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 95642.570281 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -609,31 +609,31 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 249 system.cpu.icache.demand_mshr_misses::total 249 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 249 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 249 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22913000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 22913000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22913000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 22913000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22913000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 22913000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23317000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 23317000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23317000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 23317000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23317000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 23317000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.049523 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.049523 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.049523 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.049523 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.049523 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.049523 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 92020.080321 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 92020.080321 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 92020.080321 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 92020.080321 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 92020.080321 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 92020.080321 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 93642.570281 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 93642.570281 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 93642.570281 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 93642.570281 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 93642.570281 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 93642.570281 # average overall mshr miss latency system.l2bus.snoop_filter.tot_requests 461 # Total number of requests made to the snoop filter. system.l2bus.snoop_filter.hit_single_requests 94 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.l2bus.snoop_filter.hit_multi_requests 10 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.l2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.l2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.l2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.l2bus.pwrStateResidencyTicks::UNDEFINED 49855000 # Cumulative time (in ticks) in various power states +system.l2bus.pwrStateResidencyTicks::UNDEFINED 50074000 # Cumulative time (in ticks) in various power states system.l2bus.trans_dist::ReadResp 348 # Transaction distribution system.l2bus.trans_dist::CleanEvict 70 # Transaction distribution system.l2bus.trans_dist::ReadExReq 43 # Transaction distribution @@ -664,25 +664,25 @@ system.l2bus.respLayer0.occupancy 747000 # La system.l2bus.respLayer0.utilization 1.5 # Layer utilization (%) system.l2bus.respLayer1.occupancy 426000 # Layer occupancy (ticks) system.l2bus.respLayer1.utilization 0.9 # Layer utilization (%) -system.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 49855000 # Cumulative time (in ticks) in various power states +system.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 50074000 # Cumulative time (in ticks) in various power states system.l2cache.tags.replacements 0 # number of replacements -system.l2cache.tags.tagsinuse 156.197536 # Cycle average of tags in use +system.l2cache.tags.tagsinuse 184.338383 # Cycle average of tags in use system.l2cache.tags.total_refs 100 # Total number of references to valid blocks. -system.l2cache.tags.sampled_refs 308 # Sample count of references to valid blocks. -system.l2cache.tags.avg_refs 0.324675 # Average number of references to valid blocks. +system.l2cache.tags.sampled_refs 351 # Sample count of references to valid blocks. +system.l2cache.tags.avg_refs 0.284900 # Average number of references to valid blocks. system.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2cache.tags.occ_blocks::cpu.inst 107.190956 # Average occupied blocks per requestor -system.l2cache.tags.occ_blocks::cpu.data 49.006580 # Average occupied blocks per requestor -system.l2cache.tags.occ_percent::cpu.inst 0.026170 # Average percentage of cache occupancy -system.l2cache.tags.occ_percent::cpu.data 0.011964 # Average percentage of cache occupancy -system.l2cache.tags.occ_percent::total 0.038134 # Average percentage of cache occupancy -system.l2cache.tags.occ_task_id_blocks::1024 308 # Occupied blocks per task id +system.l2cache.tags.occ_blocks::cpu.inst 107.366220 # Average occupied blocks per requestor +system.l2cache.tags.occ_blocks::cpu.data 76.972162 # Average occupied blocks per requestor +system.l2cache.tags.occ_percent::cpu.inst 0.026212 # Average percentage of cache occupancy +system.l2cache.tags.occ_percent::cpu.data 0.018792 # Average percentage of cache occupancy +system.l2cache.tags.occ_percent::total 0.045004 # Average percentage of cache occupancy +system.l2cache.tags.occ_task_id_blocks::1024 351 # Occupied blocks per task id system.l2cache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id -system.l2cache.tags.age_task_id_blocks_1024::1 246 # Occupied blocks per task id -system.l2cache.tags.occ_task_id_percent::1024 0.075195 # Percentage of cache occupancy per task id +system.l2cache.tags.age_task_id_blocks_1024::1 289 # Occupied blocks per task id +system.l2cache.tags.occ_task_id_percent::1024 0.085693 # Percentage of cache occupancy per task id system.l2cache.tags.tag_accesses 3959 # Number of tag accesses system.l2cache.tags.data_accesses 3959 # Number of data accesses -system.l2cache.pwrStateResidencyTicks::UNDEFINED 49855000 # Cumulative time (in ticks) in various power states +system.l2cache.pwrStateResidencyTicks::UNDEFINED 50074000 # Cumulative time (in ticks) in various power states system.l2cache.ReadSharedReq_hits::cpu.inst 24 # number of ReadSharedReq hits system.l2cache.ReadSharedReq_hits::cpu.data 16 # number of ReadSharedReq hits system.l2cache.ReadSharedReq_hits::total 40 # number of ReadSharedReq hits @@ -703,17 +703,17 @@ system.l2cache.demand_misses::total 351 # nu system.l2cache.overall_misses::cpu.inst 225 # number of overall misses system.l2cache.overall_misses::cpu.data 126 # number of overall misses system.l2cache.overall_misses::total 351 # number of overall misses -system.l2cache.ReadExReq_miss_latency::cpu.data 4196000 # number of ReadExReq miss cycles -system.l2cache.ReadExReq_miss_latency::total 4196000 # number of ReadExReq miss cycles -system.l2cache.ReadSharedReq_miss_latency::cpu.inst 21622000 # number of ReadSharedReq miss cycles -system.l2cache.ReadSharedReq_miss_latency::cpu.data 7918000 # number of ReadSharedReq miss cycles -system.l2cache.ReadSharedReq_miss_latency::total 29540000 # number of ReadSharedReq miss cycles -system.l2cache.demand_miss_latency::cpu.inst 21622000 # number of demand (read+write) miss cycles -system.l2cache.demand_miss_latency::cpu.data 12114000 # number of demand (read+write) miss cycles -system.l2cache.demand_miss_latency::total 33736000 # number of demand (read+write) miss cycles -system.l2cache.overall_miss_latency::cpu.inst 21622000 # number of overall miss cycles -system.l2cache.overall_miss_latency::cpu.data 12114000 # number of overall miss cycles -system.l2cache.overall_miss_latency::total 33736000 # number of overall miss cycles +system.l2cache.ReadExReq_miss_latency::cpu.data 4173000 # number of ReadExReq miss cycles +system.l2cache.ReadExReq_miss_latency::total 4173000 # number of ReadExReq miss cycles +system.l2cache.ReadSharedReq_miss_latency::cpu.inst 22026000 # number of ReadSharedReq miss cycles +system.l2cache.ReadSharedReq_miss_latency::cpu.data 7756000 # number of ReadSharedReq miss cycles +system.l2cache.ReadSharedReq_miss_latency::total 29782000 # number of ReadSharedReq miss cycles +system.l2cache.demand_miss_latency::cpu.inst 22026000 # number of demand (read+write) miss cycles +system.l2cache.demand_miss_latency::cpu.data 11929000 # number of demand (read+write) miss cycles +system.l2cache.demand_miss_latency::total 33955000 # number of demand (read+write) miss cycles +system.l2cache.overall_miss_latency::cpu.inst 22026000 # number of overall miss cycles +system.l2cache.overall_miss_latency::cpu.data 11929000 # number of overall miss cycles +system.l2cache.overall_miss_latency::total 33955000 # number of overall miss cycles system.l2cache.ReadExReq_accesses::cpu.data 43 # number of ReadExReq accesses(hits+misses) system.l2cache.ReadExReq_accesses::total 43 # number of ReadExReq accesses(hits+misses) system.l2cache.ReadSharedReq_accesses::cpu.inst 249 # number of ReadSharedReq accesses(hits+misses) @@ -736,17 +736,17 @@ system.l2cache.demand_miss_rate::total 0.897698 # mi system.l2cache.overall_miss_rate::cpu.inst 0.903614 # miss rate for overall accesses system.l2cache.overall_miss_rate::cpu.data 0.887324 # miss rate for overall accesses system.l2cache.overall_miss_rate::total 0.897698 # miss rate for overall accesses -system.l2cache.ReadExReq_avg_miss_latency::cpu.data 97581.395349 # average ReadExReq miss latency -system.l2cache.ReadExReq_avg_miss_latency::total 97581.395349 # average ReadExReq miss latency -system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 96097.777778 # average ReadSharedReq miss latency -system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 95397.590361 # average ReadSharedReq miss latency -system.l2cache.ReadSharedReq_avg_miss_latency::total 95909.090909 # average ReadSharedReq miss latency -system.l2cache.demand_avg_miss_latency::cpu.inst 96097.777778 # average overall miss latency -system.l2cache.demand_avg_miss_latency::cpu.data 96142.857143 # average overall miss latency -system.l2cache.demand_avg_miss_latency::total 96113.960114 # average overall miss latency -system.l2cache.overall_avg_miss_latency::cpu.inst 96097.777778 # average overall miss latency -system.l2cache.overall_avg_miss_latency::cpu.data 96142.857143 # average overall miss latency -system.l2cache.overall_avg_miss_latency::total 96113.960114 # average overall miss latency +system.l2cache.ReadExReq_avg_miss_latency::cpu.data 97046.511628 # average ReadExReq miss latency +system.l2cache.ReadExReq_avg_miss_latency::total 97046.511628 # average ReadExReq miss latency +system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 97893.333333 # average ReadSharedReq miss latency +system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 93445.783133 # average ReadSharedReq miss latency +system.l2cache.ReadSharedReq_avg_miss_latency::total 96694.805195 # average ReadSharedReq miss latency +system.l2cache.demand_avg_miss_latency::cpu.inst 97893.333333 # average overall miss latency +system.l2cache.demand_avg_miss_latency::cpu.data 94674.603175 # average overall miss latency +system.l2cache.demand_avg_miss_latency::total 96737.891738 # average overall miss latency +system.l2cache.overall_avg_miss_latency::cpu.inst 97893.333333 # average overall miss latency +system.l2cache.overall_avg_miss_latency::cpu.data 94674.603175 # average overall miss latency +system.l2cache.overall_avg_miss_latency::total 96737.891738 # average overall miss latency system.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -764,17 +764,17 @@ system.l2cache.demand_mshr_misses::total 351 # nu system.l2cache.overall_mshr_misses::cpu.inst 225 # number of overall MSHR misses system.l2cache.overall_mshr_misses::cpu.data 126 # number of overall MSHR misses system.l2cache.overall_mshr_misses::total 351 # number of overall MSHR misses -system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3336000 # number of ReadExReq MSHR miss cycles -system.l2cache.ReadExReq_mshr_miss_latency::total 3336000 # number of ReadExReq MSHR miss cycles -system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 17122000 # number of ReadSharedReq MSHR miss cycles -system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6258000 # number of ReadSharedReq MSHR miss cycles -system.l2cache.ReadSharedReq_mshr_miss_latency::total 23380000 # number of ReadSharedReq MSHR miss cycles -system.l2cache.demand_mshr_miss_latency::cpu.inst 17122000 # number of demand (read+write) MSHR miss cycles -system.l2cache.demand_mshr_miss_latency::cpu.data 9594000 # number of demand (read+write) MSHR miss cycles -system.l2cache.demand_mshr_miss_latency::total 26716000 # number of demand (read+write) MSHR miss cycles -system.l2cache.overall_mshr_miss_latency::cpu.inst 17122000 # number of overall MSHR miss cycles -system.l2cache.overall_mshr_miss_latency::cpu.data 9594000 # number of overall MSHR miss cycles -system.l2cache.overall_mshr_miss_latency::total 26716000 # number of overall MSHR miss cycles +system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3313000 # number of ReadExReq MSHR miss cycles +system.l2cache.ReadExReq_mshr_miss_latency::total 3313000 # number of ReadExReq MSHR miss cycles +system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 17526000 # number of ReadSharedReq MSHR miss cycles +system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6096000 # number of ReadSharedReq MSHR miss cycles +system.l2cache.ReadSharedReq_mshr_miss_latency::total 23622000 # number of ReadSharedReq MSHR miss cycles +system.l2cache.demand_mshr_miss_latency::cpu.inst 17526000 # number of demand (read+write) MSHR miss cycles +system.l2cache.demand_mshr_miss_latency::cpu.data 9409000 # number of demand (read+write) MSHR miss cycles +system.l2cache.demand_mshr_miss_latency::total 26935000 # number of demand (read+write) MSHR miss cycles +system.l2cache.overall_mshr_miss_latency::cpu.inst 17526000 # number of overall MSHR miss cycles +system.l2cache.overall_mshr_miss_latency::cpu.data 9409000 # number of overall MSHR miss cycles +system.l2cache.overall_mshr_miss_latency::total 26935000 # number of overall MSHR miss cycles system.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.inst 0.903614 # mshr miss rate for ReadSharedReq accesses @@ -786,18 +786,24 @@ system.l2cache.demand_mshr_miss_rate::total 0.897698 # system.l2cache.overall_mshr_miss_rate::cpu.inst 0.903614 # mshr miss rate for overall accesses system.l2cache.overall_mshr_miss_rate::cpu.data 0.887324 # mshr miss rate for overall accesses system.l2cache.overall_mshr_miss_rate::total 0.897698 # mshr miss rate for overall accesses -system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 77581.395349 # average ReadExReq mshr miss latency -system.l2cache.ReadExReq_avg_mshr_miss_latency::total 77581.395349 # average ReadExReq mshr miss latency -system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 76097.777778 # average ReadSharedReq mshr miss latency -system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 75397.590361 # average ReadSharedReq mshr miss latency -system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 75909.090909 # average ReadSharedReq mshr miss latency -system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 76097.777778 # average overall mshr miss latency -system.l2cache.demand_avg_mshr_miss_latency::cpu.data 76142.857143 # average overall mshr miss latency -system.l2cache.demand_avg_mshr_miss_latency::total 76113.960114 # average overall mshr miss latency -system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 76097.777778 # average overall mshr miss latency -system.l2cache.overall_avg_mshr_miss_latency::cpu.data 76142.857143 # average overall mshr miss latency -system.l2cache.overall_avg_mshr_miss_latency::total 76113.960114 # average overall mshr miss latency -system.membus.pwrStateResidencyTicks::UNDEFINED 49855000 # Cumulative time (in ticks) in various power states +system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 77046.511628 # average ReadExReq mshr miss latency +system.l2cache.ReadExReq_avg_mshr_miss_latency::total 77046.511628 # average ReadExReq mshr miss latency +system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 77893.333333 # average ReadSharedReq mshr miss latency +system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73445.783133 # average ReadSharedReq mshr miss latency +system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76694.805195 # average ReadSharedReq mshr miss latency +system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 77893.333333 # average overall mshr miss latency +system.l2cache.demand_avg_mshr_miss_latency::cpu.data 74674.603175 # average overall mshr miss latency +system.l2cache.demand_avg_mshr_miss_latency::total 76737.891738 # average overall mshr miss latency +system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 77893.333333 # average overall mshr miss latency +system.l2cache.overall_avg_mshr_miss_latency::cpu.data 74674.603175 # average overall mshr miss latency +system.l2cache.overall_avg_mshr_miss_latency::total 76737.891738 # average overall mshr miss latency +system.membus.snoop_filter.tot_requests 351 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 50074000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 308 # Transaction distribution system.membus.trans_dist::ReadExReq 43 # Transaction distribution system.membus.trans_dist::ReadExResp 43 # Transaction distribution @@ -820,7 +826,7 @@ system.membus.snoop_fanout::max_value 0 # Re system.membus.snoop_fanout::total 351 # Request fanout histogram system.membus.reqLayer0.occupancy 351000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.7 # Layer utilization (%) -system.membus.respLayer0.occupancy 1865750 # Layer occupancy (ticks) +system.membus.respLayer0.occupancy 1865500 # Layer occupancy (ticks) system.membus.respLayer0.utilization 3.7 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-simple/stats.txt b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-simple/stats.txt index 54ae8e9b7..60c6ac279 100644 --- a/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-simple/stats.txt +++ b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-simple/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000369 # Number of seconds simulated -sim_ticks 368887000 # Number of ticks simulated -final_tick 368887000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000377 # Number of seconds simulated +sim_ticks 376893000 # Number of ticks simulated +final_tick 376893000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 354647 # Simulator instruction rate (inst/s) -host_op_rate 354403 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 23159010384 # Simulator tick rate (ticks/s) -host_mem_usage 629604 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host +host_inst_rate 173660 # Simulator instruction rate (inst/s) +host_op_rate 173583 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 11593149844 # Simulator tick rate (ticks/s) +host_mem_usage 632708 # Number of bytes of host memory used +host_seconds 0.03 # Real time elapsed on the host sim_insts 5641 # Number of instructions simulated sim_ops 5641 # Number of ops (including micro ops) simulated system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 368887000 # Cumulative time (in ticks) in various power states +system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 376893000 # Cumulative time (in ticks) in various power states system.mem_ctrl.bytes_read::cpu.inst 22568 # Number of bytes read from this memory system.mem_ctrl.bytes_read::cpu.data 4301 # Number of bytes read from this memory system.mem_ctrl.bytes_read::total 26869 # Number of bytes read from this memory @@ -26,27 +26,27 @@ system.mem_ctrl.num_reads::cpu.data 1135 # Nu system.mem_ctrl.num_reads::total 6777 # Number of read requests responded to by this memory system.mem_ctrl.num_writes::cpu.data 901 # Number of write requests responded to by this memory system.mem_ctrl.num_writes::total 901 # Number of write requests responded to by this memory -system.mem_ctrl.bw_read::cpu.inst 61178627 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::cpu.data 11659397 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::total 72838024 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::cpu.inst 61178627 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::total 61178627 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_write::cpu.data 9761797 # Write bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_write::total 9761797 # Write bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.inst 61178627 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.data 21421194 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::total 82599821 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_read::cpu.inst 59879064 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_read::cpu.data 11411727 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_read::total 71290791 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_inst_read::cpu.inst 59879064 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_inst_read::total 59879064 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_write::cpu.data 9554436 # Write bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_write::total 9554436 # Write bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_total::cpu.inst 59879064 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_total::cpu.data 20966163 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_total::total 80845227 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrl.readReqs 6778 # Number of read requests accepted system.mem_ctrl.writeReqs 901 # Number of write requests accepted system.mem_ctrl.readBursts 6778 # Number of DRAM read bursts, including those serviced by the write queue system.mem_ctrl.writeBursts 901 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrl.bytesReadDRAM 427648 # Total number of bytes read from DRAM -system.mem_ctrl.bytesReadWrQ 6144 # Total number of bytes read from write queue +system.mem_ctrl.bytesReadDRAM 428096 # Total number of bytes read from DRAM +system.mem_ctrl.bytesReadWrQ 5696 # Total number of bytes read from write queue system.mem_ctrl.bytesWritten 4096 # Total number of bytes written to DRAM system.mem_ctrl.bytesReadSys 26873 # Total read bytes from the system interface side system.mem_ctrl.bytesWrittenSys 3601 # Total written bytes from the system interface side -system.mem_ctrl.servicedByWrQ 96 # Number of DRAM read bursts serviced by the write queue -system.mem_ctrl.mergedWrBursts 807 # Number of DRAM write bursts merged with an existing one +system.mem_ctrl.servicedByWrQ 89 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrl.mergedWrBursts 811 # Number of DRAM write bursts merged with an existing one system.mem_ctrl.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.mem_ctrl.perBankRdBursts::0 275 # Per bank write bursts system.mem_ctrl.perBankRdBursts::1 0 # Per bank write bursts @@ -55,15 +55,15 @@ system.mem_ctrl.perBankRdBursts::3 0 # Pe system.mem_ctrl.perBankRdBursts::4 215 # Per bank write bursts system.mem_ctrl.perBankRdBursts::5 18 # Per bank write bursts system.mem_ctrl.perBankRdBursts::6 105 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::7 518 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::7 519 # Per bank write bursts system.mem_ctrl.perBankRdBursts::8 543 # Per bank write bursts system.mem_ctrl.perBankRdBursts::9 1212 # Per bank write bursts system.mem_ctrl.perBankRdBursts::10 899 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::11 346 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::11 350 # Per bank write bursts system.mem_ctrl.perBankRdBursts::12 677 # Per bank write bursts system.mem_ctrl.perBankRdBursts::13 398 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::14 1426 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::15 50 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::14 1429 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::15 49 # Per bank write bursts system.mem_ctrl.perBankWrBursts::0 0 # Per bank write bursts system.mem_ctrl.perBankWrBursts::1 0 # Per bank write bursts system.mem_ctrl.perBankWrBursts::2 0 # Per bank write bursts @@ -71,18 +71,18 @@ system.mem_ctrl.perBankWrBursts::3 0 # Pe system.mem_ctrl.perBankWrBursts::4 0 # Per bank write bursts system.mem_ctrl.perBankWrBursts::5 0 # Per bank write bursts system.mem_ctrl.perBankWrBursts::6 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::7 6 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::7 8 # Per bank write bursts system.mem_ctrl.perBankWrBursts::8 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::9 8 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::9 7 # Per bank write bursts system.mem_ctrl.perBankWrBursts::10 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::11 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::12 29 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::11 2 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::12 30 # Per bank write bursts system.mem_ctrl.perBankWrBursts::13 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::14 19 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::15 2 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::14 14 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::15 3 # Per bank write bursts system.mem_ctrl.numRdRetry 0 # Number of times read queue was full causing retry system.mem_ctrl.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrl.totGap 368811000 # Total gap between requests +system.mem_ctrl.totGap 376816000 # Total gap between requests system.mem_ctrl.readPktSize::0 79 # Read request sizes (log2) system.mem_ctrl.readPktSize::1 1 # Read request sizes (log2) system.mem_ctrl.readPktSize::2 6698 # Read request sizes (log2) @@ -97,7 +97,7 @@ system.mem_ctrl.writePktSize::3 0 # Wr system.mem_ctrl.writePktSize::4 0 # Write request sizes (log2) system.mem_ctrl.writePktSize::5 0 # Write request sizes (log2) system.mem_ctrl.writePktSize::6 0 # Write request sizes (log2) -system.mem_ctrl.rdQLenPdf::0 6682 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::0 6689 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::1 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::2 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::3 0 # What read queue length does an incoming req see @@ -155,10 +155,10 @@ system.mem_ctrl.wrQLenPdf::22 5 # Wh system.mem_ctrl.wrQLenPdf::23 5 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::24 5 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::25 5 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::26 5 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::27 5 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::28 5 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::29 5 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::26 4 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::27 4 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::28 4 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::29 4 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::30 4 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::31 4 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::32 4 # What write queue length does an incoming req see @@ -193,26 +193,26 @@ system.mem_ctrl.wrQLenPdf::60 0 # Wh system.mem_ctrl.wrQLenPdf::61 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::62 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrl.bytesPerActivate::samples 849 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::mean 506.270907 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::gmean 291.216794 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::stdev 415.367861 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::0-127 272 32.04% 32.04% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::128-255 76 8.95% 40.99% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::256-383 61 7.18% 48.17% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::384-511 46 5.42% 53.59% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::512-639 36 4.24% 57.83% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::640-767 42 4.95% 62.78% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::768-895 24 2.83% 65.61% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::896-1023 15 1.77% 67.37% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::1024-1151 277 32.63% 100.00% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::total 849 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::samples 838 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::mean 513.374702 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::gmean 298.080754 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::stdev 413.335022 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::0-127 263 31.38% 31.38% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::128-255 85 10.14% 41.53% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::256-383 42 5.01% 46.54% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::384-511 43 5.13% 51.67% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::512-639 44 5.25% 56.92% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::640-767 53 6.32% 63.25% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::768-895 15 1.79% 65.04% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::896-1023 22 2.63% 67.66% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::1024-1151 271 32.34% 100.00% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::total 838 # Bytes accessed per row activation system.mem_ctrl.rdPerTurnAround::samples 4 # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::mean 1349.750000 # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::gmean 1262.645152 # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::stdev 506.185325 # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::640-703 1 25.00% 25.00% # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::1216-1279 1 25.00% 50.00% # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::mean 1522.250000 # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::gmean 1505.224255 # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::stdev 263.075876 # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::1216-1279 1 25.00% 25.00% # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::1280-1343 1 25.00% 50.00% # Reads before turning the bus around for writes system.mem_ctrl.rdPerTurnAround::1664-1727 1 25.00% 75.00% # Reads before turning the bus around for writes system.mem_ctrl.rdPerTurnAround::1792-1855 1 25.00% 100.00% # Reads before turning the bus around for writes system.mem_ctrl.rdPerTurnAround::total 4 # Reads before turning the bus around for writes @@ -221,57 +221,57 @@ system.mem_ctrl.wrPerTurnAround::mean 16 # Wr system.mem_ctrl.wrPerTurnAround::gmean 16.000000 # Writes before turning the bus around for reads system.mem_ctrl.wrPerTurnAround::16 4 100.00% 100.00% # Writes before turning the bus around for reads system.mem_ctrl.wrPerTurnAround::total 4 # Writes before turning the bus around for reads -system.mem_ctrl.totQLat 28067250 # Total ticks spent queuing -system.mem_ctrl.totMemAccLat 153354750 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrl.totBusLat 33410000 # Total ticks spent in databus transfers -system.mem_ctrl.avgQLat 4200.43 # Average queueing delay per DRAM burst +system.mem_ctrl.totQLat 28198000 # Total ticks spent queuing +system.mem_ctrl.totMemAccLat 153616750 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrl.totBusLat 33445000 # Total ticks spent in databus transfers +system.mem_ctrl.avgQLat 4215.58 # Average queueing delay per DRAM burst system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.mem_ctrl.avgMemAccLat 22950.43 # Average memory access latency per DRAM burst -system.mem_ctrl.avgRdBW 1159.29 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrl.avgWrBW 11.10 # Average achieved write bandwidth in MiByte/s -system.mem_ctrl.avgRdBWSys 72.85 # Average system read bandwidth in MiByte/s -system.mem_ctrl.avgWrBWSys 9.76 # Average system write bandwidth in MiByte/s +system.mem_ctrl.avgMemAccLat 22965.58 # Average memory access latency per DRAM burst +system.mem_ctrl.avgRdBW 1135.86 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrl.avgWrBW 10.87 # Average achieved write bandwidth in MiByte/s +system.mem_ctrl.avgRdBWSys 71.30 # Average system read bandwidth in MiByte/s +system.mem_ctrl.avgWrBWSys 9.55 # Average system write bandwidth in MiByte/s system.mem_ctrl.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrl.busUtil 9.14 # Data bus utilization in percentage -system.mem_ctrl.busUtilRead 9.06 # Data bus utilization in percentage for reads -system.mem_ctrl.busUtilWrite 0.09 # Data bus utilization in percentage for writes +system.mem_ctrl.busUtil 8.96 # Data bus utilization in percentage +system.mem_ctrl.busUtilRead 8.87 # Data bus utilization in percentage for reads +system.mem_ctrl.busUtilWrite 0.08 # Data bus utilization in percentage for writes system.mem_ctrl.avgRdQLen 1.00 # Average read queue length when enqueuing -system.mem_ctrl.avgWrQLen 23.19 # Average write queue length when enqueuing -system.mem_ctrl.readRowHits 5834 # Number of row buffer hits during reads -system.mem_ctrl.writeRowHits 58 # Number of row buffer hits during writes -system.mem_ctrl.readRowHitRate 87.31 # Row buffer hit rate for reads -system.mem_ctrl.writeRowHitRate 61.70 # Row buffer hit rate for writes -system.mem_ctrl.avgGap 48028.52 # Average gap between requests -system.mem_ctrl.pageHitRate 86.95 # Row buffer hit rate, read and write combined -system.mem_ctrl_0.actEnergy 1058400 # Energy for activate commands per rank (pJ) -system.mem_ctrl_0.preEnergy 577500 # Energy for precharge commands per rank (pJ) +system.mem_ctrl.avgWrQLen 23.23 # Average write queue length when enqueuing +system.mem_ctrl.readRowHits 5853 # Number of row buffer hits during reads +system.mem_ctrl.writeRowHits 57 # Number of row buffer hits during writes +system.mem_ctrl.readRowHitRate 87.50 # Row buffer hit rate for reads +system.mem_ctrl.writeRowHitRate 63.33 # Row buffer hit rate for writes +system.mem_ctrl.avgGap 49070.97 # Average gap between requests +system.mem_ctrl.pageHitRate 87.18 # Row buffer hit rate, read and write combined +system.mem_ctrl_0.actEnergy 1020600 # Energy for activate commands per rank (pJ) +system.mem_ctrl_0.preEnergy 556875 # Energy for precharge commands per rank (pJ) system.mem_ctrl_0.readEnergy 8806200 # Energy for read commands per rank (pJ) -system.mem_ctrl_0.writeEnergy 38880 # Energy for write commands per rank (pJ) -system.mem_ctrl_0.refreshEnergy 23902320 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_0.actBackEnergy 143993115 # Energy for active background per rank (pJ) -system.mem_ctrl_0.preBackEnergy 93418500 # Energy for precharge background per rank (pJ) -system.mem_ctrl_0.totalEnergy 271794915 # Total energy per rank (pJ) -system.mem_ctrl_0.averagePower 742.175615 # Core power per rank (mW) -system.mem_ctrl_0.memoryStateTime::IDLE 153996500 # Time in different power states -system.mem_ctrl_0.memoryStateTime::REF 12220000 # Time in different power states +system.mem_ctrl_0.writeEnergy 51840 # Energy for write commands per rank (pJ) +system.mem_ctrl_0.refreshEnergy 24410880 # Energy for refresh commands per rank (pJ) +system.mem_ctrl_0.actBackEnergy 141780375 # Energy for active background per rank (pJ) +system.mem_ctrl_0.preBackEnergy 100031250 # Energy for precharge background per rank (pJ) +system.mem_ctrl_0.totalEnergy 276658020 # Total energy per rank (pJ) +system.mem_ctrl_0.averagePower 739.727326 # Core power per rank (mW) +system.mem_ctrl_0.memoryStateTime::IDLE 165010500 # Time in different power states +system.mem_ctrl_0.memoryStateTime::REF 12480000 # Time in different power states system.mem_ctrl_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrl_0.memoryStateTime::ACT 200230500 # Time in different power states +system.mem_ctrl_0.memoryStateTime::ACT 196602500 # Time in different power states system.mem_ctrl_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrl_1.actEnergy 5344920 # Energy for activate commands per rank (pJ) -system.mem_ctrl_1.preEnergy 2916375 # Energy for precharge commands per rank (pJ) -system.mem_ctrl_1.readEnergy 42907800 # Energy for read commands per rank (pJ) -system.mem_ctrl_1.writeEnergy 375840 # Energy for write commands per rank (pJ) -system.mem_ctrl_1.refreshEnergy 23902320 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_1.actBackEnergy 246623040 # Energy for active background per rank (pJ) -system.mem_ctrl_1.preBackEnergy 3392250 # Energy for precharge background per rank (pJ) -system.mem_ctrl_1.totalEnergy 325462545 # Total energy per rank (pJ) -system.mem_ctrl_1.averagePower 888.722897 # Core power per rank (mW) -system.mem_ctrl_1.memoryStateTime::IDLE 3452250 # Time in different power states -system.mem_ctrl_1.memoryStateTime::REF 12220000 # Time in different power states +system.mem_ctrl_1.actEnergy 5299560 # Energy for activate commands per rank (pJ) +system.mem_ctrl_1.preEnergy 2891625 # Energy for precharge commands per rank (pJ) +system.mem_ctrl_1.readEnergy 42939000 # Energy for read commands per rank (pJ) +system.mem_ctrl_1.writeEnergy 362880 # Energy for write commands per rank (pJ) +system.mem_ctrl_1.refreshEnergy 24410880 # Energy for refresh commands per rank (pJ) +system.mem_ctrl_1.actBackEnergy 252188235 # Energy for active background per rank (pJ) +system.mem_ctrl_1.preBackEnergy 3192750 # Energy for precharge background per rank (pJ) +system.mem_ctrl_1.totalEnergy 331284930 # Total energy per rank (pJ) +system.mem_ctrl_1.averagePower 885.747138 # Core power per rank (mW) +system.mem_ctrl_1.memoryStateTime::IDLE 2538750 # Time in different power states +system.mem_ctrl_1.memoryStateTime::REF 12480000 # Time in different power states system.mem_ctrl_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrl_1.memoryStateTime::ACT 350555250 # Time in different power states +system.mem_ctrl_1.memoryStateTime::ACT 359011750 # Time in different power states system.mem_ctrl_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 368887000 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 376893000 # Cumulative time (in ticks) in various power states system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses system.cpu.dtb.read_accesses 0 # DTB read accesses @@ -291,8 +291,8 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 7 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 368887000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 368887 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 376893000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 376893 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 5641 # Number of instructions committed @@ -311,7 +311,7 @@ system.cpu.num_mem_refs 2037 # nu system.cpu.num_load_insts 1135 # Number of load instructions system.cpu.num_store_insts 902 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 368887 # Number of busy cycles +system.cpu.num_busy_cycles 376893 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 886 # Number of branches fetched @@ -350,7 +350,13 @@ system.cpu.op_class::MemWrite 902 15.99% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 5642 # Class of executed instruction -system.membus.pwrStateResidencyTicks::UNDEFINED 368887000 # Cumulative time (in ticks) in various power states +system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 376893000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 6778 # Transaction distribution system.membus.trans_dist::ReadResp 6777 # Transaction distribution system.membus.trans_dist::WriteReq 901 # Transaction distribution @@ -364,20 +370,20 @@ system.membus.pkt_size::total 30470 # Cu system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) system.membus.snoop_fanout::samples 7679 # Request fanout histogram -system.membus.snoop_fanout::mean 0.734861 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.441436 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 2036 26.51% 26.51% # Request fanout histogram -system.membus.snoop_fanout::1 5643 73.49% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 7679 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 7679 # Request fanout histogram system.membus.reqLayer0.occupancy 8580000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.3 # Layer utilization (%) -system.membus.respLayer0.occupancy 12857500 # Layer occupancy (ticks) -system.membus.respLayer0.utilization 3.5 # Layer utilization (%) +system.membus.respLayer0.occupancy 12853500 # Layer occupancy (ticks) +system.membus.respLayer0.utilization 3.4 # Layer utilization (%) system.membus.respLayer1.occupancy 3555500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 1.0 # Layer utilization (%) +system.membus.respLayer1.utilization 0.9 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/stats.txt b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/stats.txt index c2c263451..27ea6dc01 100644 --- a/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/stats.txt +++ b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000059 # Number of seconds simulated -sim_ticks 58892000 # Number of ticks simulated -final_tick 58892000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 59115000 # Number of ticks simulated +final_tick 59115000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 557970 # Simulator instruction rate (inst/s) -host_op_rate 557350 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5812791438 # Simulator tick rate (ticks/s) -host_mem_usage 633704 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host +host_inst_rate 219311 # Simulator instruction rate (inst/s) +host_op_rate 219196 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2295881155 # Simulator tick rate (ticks/s) +host_mem_usage 637060 # Number of bytes of host memory used +host_seconds 0.03 # Real time elapsed on the host sim_insts 5641 # Number of instructions simulated sim_ops 5641 # Number of ops (including micro ops) simulated system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 58892000 # Cumulative time (in ticks) in various power states +system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 59115000 # Cumulative time (in ticks) in various power states system.mem_ctrl.bytes_read::cpu.inst 18752 # Number of bytes read from this memory system.mem_ctrl.bytes_read::cpu.data 8768 # Number of bytes read from this memory system.mem_ctrl.bytes_read::total 27520 # Number of bytes read from this memory @@ -22,14 +22,14 @@ system.mem_ctrl.bytes_inst_read::total 18752 # Nu system.mem_ctrl.num_reads::cpu.inst 293 # Number of read requests responded to by this memory system.mem_ctrl.num_reads::cpu.data 137 # Number of read requests responded to by this memory system.mem_ctrl.num_reads::total 430 # Number of read requests responded to by this memory -system.mem_ctrl.bw_read::cpu.inst 318413367 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::cpu.data 148882701 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::total 467296067 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::cpu.inst 318413367 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::total 318413367 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.inst 318413367 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.data 148882701 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::total 467296067 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_read::cpu.inst 317212213 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_read::cpu.data 148321069 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_read::total 465533283 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_inst_read::cpu.inst 317212213 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_inst_read::total 317212213 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_total::cpu.inst 317212213 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_total::cpu.data 148321069 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_total::total 465533283 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrl.readReqs 430 # Number of read requests accepted system.mem_ctrl.writeReqs 0 # Number of write requests accepted system.mem_ctrl.readBursts 430 # Number of DRAM read bursts, including those serviced by the write queue @@ -76,7 +76,7 @@ system.mem_ctrl.perBankWrBursts::14 0 # Pe system.mem_ctrl.perBankWrBursts::15 0 # Per bank write bursts system.mem_ctrl.numRdRetry 0 # Number of times read queue was full causing retry system.mem_ctrl.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrl.totGap 58762000 # Total gap between requests +system.mem_ctrl.totGap 58984000 # Total gap between requests system.mem_ctrl.readPktSize::0 0 # Read request sizes (log2) system.mem_ctrl.readPktSize::1 0 # Read request sizes (log2) system.mem_ctrl.readPktSize::2 0 # Read request sizes (log2) @@ -187,70 +187,70 @@ system.mem_ctrl.wrQLenPdf::60 0 # Wh system.mem_ctrl.wrQLenPdf::61 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::62 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrl.bytesPerActivate::samples 113 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::mean 232.212389 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::gmean 169.054443 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::stdev 210.567831 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::0-127 30 26.55% 26.55% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::128-255 44 38.94% 65.49% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::256-383 17 15.04% 80.53% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::384-511 9 7.96% 88.50% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::512-639 5 4.42% 92.92% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::640-767 4 3.54% 96.46% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::768-895 1 0.88% 97.35% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::1024-1151 3 2.65% 100.00% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::total 113 # Bytes accessed per row activation -system.mem_ctrl.totQLat 3838500 # Total ticks spent queuing -system.mem_ctrl.totMemAccLat 11901000 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrl.bytesPerActivate::samples 110 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::mean 237.963636 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::gmean 174.172417 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::stdev 212.375811 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::0-127 28 25.45% 25.45% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::128-255 42 38.18% 63.64% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::256-383 19 17.27% 80.91% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::384-511 8 7.27% 88.18% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::512-639 4 3.64% 91.82% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::640-767 4 3.64% 95.45% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::768-895 2 1.82% 97.27% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::1024-1151 3 2.73% 100.00% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::total 110 # Bytes accessed per row activation +system.mem_ctrl.totQLat 3632500 # Total ticks spent queuing +system.mem_ctrl.totMemAccLat 11695000 # Total ticks spent from burst creation until serviced by the DRAM system.mem_ctrl.totBusLat 2150000 # Total ticks spent in databus transfers -system.mem_ctrl.avgQLat 8926.74 # Average queueing delay per DRAM burst +system.mem_ctrl.avgQLat 8447.67 # Average queueing delay per DRAM burst system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.mem_ctrl.avgMemAccLat 27676.74 # Average memory access latency per DRAM burst -system.mem_ctrl.avgRdBW 467.30 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrl.avgMemAccLat 27197.67 # Average memory access latency per DRAM burst +system.mem_ctrl.avgRdBW 465.53 # Average DRAM read bandwidth in MiByte/s system.mem_ctrl.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.mem_ctrl.avgRdBWSys 467.30 # Average system read bandwidth in MiByte/s +system.mem_ctrl.avgRdBWSys 465.53 # Average system read bandwidth in MiByte/s system.mem_ctrl.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.mem_ctrl.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrl.busUtil 3.65 # Data bus utilization in percentage -system.mem_ctrl.busUtilRead 3.65 # Data bus utilization in percentage for reads +system.mem_ctrl.busUtil 3.64 # Data bus utilization in percentage +system.mem_ctrl.busUtilRead 3.64 # Data bus utilization in percentage for reads system.mem_ctrl.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.mem_ctrl.avgRdQLen 1.00 # Average read queue length when enqueuing system.mem_ctrl.avgWrQLen 0.00 # Average write queue length when enqueuing -system.mem_ctrl.readRowHits 313 # Number of row buffer hits during reads +system.mem_ctrl.readRowHits 315 # Number of row buffer hits during reads system.mem_ctrl.writeRowHits 0 # Number of row buffer hits during writes -system.mem_ctrl.readRowHitRate 72.79 # Row buffer hit rate for reads +system.mem_ctrl.readRowHitRate 73.26 # Row buffer hit rate for reads system.mem_ctrl.writeRowHitRate nan # Row buffer hit rate for writes -system.mem_ctrl.avgGap 136655.81 # Average gap between requests -system.mem_ctrl.pageHitRate 72.79 # Row buffer hit rate, read and write combined +system.mem_ctrl.avgGap 137172.09 # Average gap between requests +system.mem_ctrl.pageHitRate 73.26 # Row buffer hit rate, read and write combined system.mem_ctrl_0.actEnergy 196560 # Energy for activate commands per rank (pJ) system.mem_ctrl_0.preEnergy 107250 # Energy for precharge commands per rank (pJ) -system.mem_ctrl_0.readEnergy 678600 # Energy for read commands per rank (pJ) +system.mem_ctrl_0.readEnergy 670800 # Energy for read commands per rank (pJ) system.mem_ctrl_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.mem_ctrl_0.refreshEnergy 3559920 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_0.actBackEnergy 26204040 # Energy for active background per rank (pJ) -system.mem_ctrl_0.preBackEnergy 9872250 # Energy for precharge background per rank (pJ) -system.mem_ctrl_0.totalEnergy 40618620 # Total energy per rank (pJ) -system.mem_ctrl_0.averagePower 741.706329 # Core power per rank (mW) -system.mem_ctrl_0.memoryStateTime::IDLE 17140250 # Time in different power states +system.mem_ctrl_0.actBackEnergy 25637175 # Energy for active background per rank (pJ) +system.mem_ctrl_0.preBackEnergy 10369500 # Energy for precharge background per rank (pJ) +system.mem_ctrl_0.totalEnergy 40541205 # Total energy per rank (pJ) +system.mem_ctrl_0.averagePower 740.292712 # Core power per rank (mW) +system.mem_ctrl_0.memoryStateTime::IDLE 17115500 # Time in different power states system.mem_ctrl_0.memoryStateTime::REF 1820000 # Time in different power states system.mem_ctrl_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrl_0.memoryStateTime::ACT 36672750 # Time in different power states +system.mem_ctrl_0.memoryStateTime::ACT 35842000 # Time in different power states system.mem_ctrl_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrl_1.actEnergy 635040 # Energy for activate commands per rank (pJ) -system.mem_ctrl_1.preEnergy 346500 # Energy for precharge commands per rank (pJ) +system.mem_ctrl_1.actEnergy 612360 # Energy for activate commands per rank (pJ) +system.mem_ctrl_1.preEnergy 334125 # Energy for precharge commands per rank (pJ) system.mem_ctrl_1.readEnergy 2425800 # Energy for read commands per rank (pJ) system.mem_ctrl_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.mem_ctrl_1.refreshEnergy 3559920 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_1.actBackEnergy 37227555 # Energy for active background per rank (pJ) -system.mem_ctrl_1.preBackEnergy 202500 # Energy for precharge background per rank (pJ) -system.mem_ctrl_1.totalEnergy 44397315 # Total energy per rank (pJ) -system.mem_ctrl_1.averagePower 810.706261 # Core power per rank (mW) -system.mem_ctrl_1.memoryStateTime::IDLE 145000 # Time in different power states +system.mem_ctrl_1.actBackEnergy 37236105 # Energy for active background per rank (pJ) +system.mem_ctrl_1.preBackEnergy 195000 # Energy for precharge background per rank (pJ) +system.mem_ctrl_1.totalEnergy 44363310 # Total energy per rank (pJ) +system.mem_ctrl_1.averagePower 810.085321 # Core power per rank (mW) +system.mem_ctrl_1.memoryStateTime::IDLE 336500 # Time in different power states system.mem_ctrl_1.memoryStateTime::REF 1820000 # Time in different power states system.mem_ctrl_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrl_1.memoryStateTime::ACT 52812500 # Time in different power states +system.mem_ctrl_1.memoryStateTime::ACT 52811500 # Time in different power states system.mem_ctrl_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 58892000 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 59115000 # Cumulative time (in ticks) in various power states system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses system.cpu.dtb.read_accesses 0 # DTB read accesses @@ -270,8 +270,8 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 7 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 58892000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 58892 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 59115000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 59115 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 5641 # Number of instructions committed @@ -290,7 +290,7 @@ system.cpu.num_mem_refs 2037 # nu system.cpu.num_load_insts 1135 # Number of load instructions system.cpu.num_store_insts 902 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 58892 # Number of busy cycles +system.cpu.num_busy_cycles 59115 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 886 # Number of branches fetched @@ -329,23 +329,23 @@ system.cpu.op_class::MemWrite 902 15.99% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 5642 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 58892000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 59115000 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 86.268662 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 86.123929 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1899 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 137 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 13.861314 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 86.268662 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.084247 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.084247 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 86.123929 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.084105 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.084105 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 137 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 6 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 131 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.133789 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 4209 # Number of tag accesses system.cpu.dcache.tags.data_accesses 4209 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 58892000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 59115000 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 1048 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1048 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 851 # number of WriteReq hits @@ -362,14 +362,14 @@ system.cpu.dcache.demand_misses::cpu.data 137 # n system.cpu.dcache.demand_misses::total 137 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 137 # number of overall misses system.cpu.dcache.overall_misses::total 137 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 8910000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 8910000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 5264000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 5264000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 14174000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 14174000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 14174000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 14174000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 9045000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 9045000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 5476000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 5476000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 14521000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 14521000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 14521000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 14521000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1135 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1135 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 901 # number of WriteReq accesses(hits+misses) @@ -386,14 +386,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.067289 system.cpu.dcache.demand_miss_rate::total 0.067289 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.067289 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.067289 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 102413.793103 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 102413.793103 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 105280 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 105280 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 103459.854015 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 103459.854015 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 103459.854015 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 103459.854015 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 103965.517241 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 103965.517241 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 109520 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 109520 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 105992.700730 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 105992.700730 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 105992.700730 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 105992.700730 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -408,14 +408,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 137 system.cpu.dcache.demand_mshr_misses::total 137 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 137 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 137 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8736000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 8736000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5164000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5164000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13900000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 13900000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13900000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 13900000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8871000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 8871000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5376000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5376000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14247000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 14247000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14247000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 14247000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076652 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076652 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055494 # mshr miss rate for WriteReq accesses @@ -424,31 +424,31 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.067289 system.cpu.dcache.demand_mshr_miss_rate::total 0.067289 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.067289 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.067289 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 100413.793103 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 100413.793103 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 103280 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 103280 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 101459.854015 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 101459.854015 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 101459.854015 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 101459.854015 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 58892000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 101965.517241 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 101965.517241 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 107520 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 107520 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 103992.700730 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 103992.700730 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 103992.700730 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 103992.700730 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 59115000 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 94 # number of replacements -system.cpu.icache.tags.tagsinuse 110.145403 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 109.937395 # Cycle average of tags in use system.cpu.icache.tags.total_refs 5346 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 297 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 18 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 110.145403 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.430255 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.430255 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 109.937395 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.429443 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.429443 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 203 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 139 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 140 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.792969 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 11583 # Number of tag accesses system.cpu.icache.tags.data_accesses 11583 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 58892000 # Cumulative time (in ticks) in various power states +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 59115000 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 5346 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 5346 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 5346 # number of demand (read+write) hits @@ -461,12 +461,12 @@ system.cpu.icache.demand_misses::cpu.inst 297 # n system.cpu.icache.demand_misses::total 297 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 297 # number of overall misses system.cpu.icache.overall_misses::total 297 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 30230000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 30230000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 30230000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 30230000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 30230000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 30230000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 30106000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 30106000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 30106000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 30106000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 30106000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 30106000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 5643 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 5643 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 5643 # number of demand (read+write) accesses @@ -479,12 +479,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.052632 system.cpu.icache.demand_miss_rate::total 0.052632 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.052632 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.052632 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 101784.511785 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 101784.511785 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 101784.511785 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 101784.511785 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 101784.511785 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 101784.511785 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 101367.003367 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 101367.003367 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 101367.003367 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 101367.003367 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 101367.003367 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 101367.003367 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -497,31 +497,31 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 297 system.cpu.icache.demand_mshr_misses::total 297 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 297 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 297 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 29636000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 29636000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 29636000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 29636000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 29636000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 29636000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 29512000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 29512000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 29512000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 29512000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 29512000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 29512000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.052632 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.052632 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.052632 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.052632 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.052632 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.052632 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 99784.511785 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 99784.511785 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 99784.511785 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 99784.511785 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 99784.511785 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 99784.511785 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 99367.003367 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 99367.003367 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 99367.003367 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 99367.003367 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 99367.003367 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 99367.003367 # average overall mshr miss latency system.l2bus.snoop_filter.tot_requests 528 # Total number of requests made to the snoop filter. system.l2bus.snoop_filter.hit_single_requests 94 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.l2bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.l2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.l2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.l2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.l2bus.pwrStateResidencyTicks::UNDEFINED 58892000 # Cumulative time (in ticks) in various power states +system.l2bus.pwrStateResidencyTicks::UNDEFINED 59115000 # Cumulative time (in ticks) in various power states system.l2bus.trans_dist::ReadResp 384 # Transaction distribution system.l2bus.trans_dist::CleanEvict 94 # Transaction distribution system.l2bus.trans_dist::ReadExReq 50 # Transaction distribution @@ -552,25 +552,25 @@ system.l2bus.respLayer0.occupancy 891000 # La system.l2bus.respLayer0.utilization 1.5 # Layer utilization (%) system.l2bus.respLayer1.occupancy 411000 # Layer occupancy (ticks) system.l2bus.respLayer1.utilization 0.7 # Layer utilization (%) -system.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 58892000 # Cumulative time (in ticks) in various power states +system.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 59115000 # Cumulative time (in ticks) in various power states system.l2cache.tags.replacements 0 # number of replacements -system.l2cache.tags.tagsinuse 183.861903 # Cycle average of tags in use +system.l2cache.tags.tagsinuse 216.263710 # Cycle average of tags in use system.l2cache.tags.total_refs 98 # Total number of references to valid blocks. -system.l2cache.tags.sampled_refs 380 # Sample count of references to valid blocks. -system.l2cache.tags.avg_refs 0.257895 # Average number of references to valid blocks. +system.l2cache.tags.sampled_refs 430 # Sample count of references to valid blocks. +system.l2cache.tags.avg_refs 0.227907 # Average number of references to valid blocks. system.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2cache.tags.occ_blocks::cpu.inst 130.345601 # Average occupied blocks per requestor -system.l2cache.tags.occ_blocks::cpu.data 53.516302 # Average occupied blocks per requestor -system.l2cache.tags.occ_percent::cpu.inst 0.031823 # Average percentage of cache occupancy -system.l2cache.tags.occ_percent::cpu.data 0.013066 # Average percentage of cache occupancy -system.l2cache.tags.occ_percent::total 0.044888 # Average percentage of cache occupancy -system.l2cache.tags.occ_task_id_blocks::1024 380 # Occupied blocks per task id -system.l2cache.tags.age_task_id_blocks_1024::0 77 # Occupied blocks per task id -system.l2cache.tags.age_task_id_blocks_1024::1 303 # Occupied blocks per task id -system.l2cache.tags.occ_task_id_percent::1024 0.092773 # Percentage of cache occupancy per task id +system.l2cache.tags.occ_blocks::cpu.inst 130.091113 # Average occupied blocks per requestor +system.l2cache.tags.occ_blocks::cpu.data 86.172597 # Average occupied blocks per requestor +system.l2cache.tags.occ_percent::cpu.inst 0.031761 # Average percentage of cache occupancy +system.l2cache.tags.occ_percent::cpu.data 0.021038 # Average percentage of cache occupancy +system.l2cache.tags.occ_percent::total 0.052799 # Average percentage of cache occupancy +system.l2cache.tags.occ_task_id_blocks::1024 430 # Occupied blocks per task id +system.l2cache.tags.age_task_id_blocks_1024::0 76 # Occupied blocks per task id +system.l2cache.tags.age_task_id_blocks_1024::1 354 # Occupied blocks per task id +system.l2cache.tags.occ_task_id_percent::1024 0.104980 # Percentage of cache occupancy per task id system.l2cache.tags.tag_accesses 4654 # Number of tag accesses system.l2cache.tags.data_accesses 4654 # Number of data accesses -system.l2cache.pwrStateResidencyTicks::UNDEFINED 58892000 # Cumulative time (in ticks) in various power states +system.l2cache.pwrStateResidencyTicks::UNDEFINED 59115000 # Cumulative time (in ticks) in various power states system.l2cache.ReadSharedReq_hits::cpu.inst 4 # number of ReadSharedReq hits system.l2cache.ReadSharedReq_hits::total 4 # number of ReadSharedReq hits system.l2cache.demand_hits::cpu.inst 4 # number of demand (read+write) hits @@ -588,17 +588,17 @@ system.l2cache.demand_misses::total 430 # nu system.l2cache.overall_misses::cpu.inst 293 # number of overall misses system.l2cache.overall_misses::cpu.data 137 # number of overall misses system.l2cache.overall_misses::total 430 # number of overall misses -system.l2cache.ReadExReq_miss_latency::cpu.data 5014000 # number of ReadExReq miss cycles -system.l2cache.ReadExReq_miss_latency::total 5014000 # number of ReadExReq miss cycles -system.l2cache.ReadSharedReq_miss_latency::cpu.inst 28661000 # number of ReadSharedReq miss cycles -system.l2cache.ReadSharedReq_miss_latency::cpu.data 8475000 # number of ReadSharedReq miss cycles -system.l2cache.ReadSharedReq_miss_latency::total 37136000 # number of ReadSharedReq miss cycles -system.l2cache.demand_miss_latency::cpu.inst 28661000 # number of demand (read+write) miss cycles -system.l2cache.demand_miss_latency::cpu.data 13489000 # number of demand (read+write) miss cycles -system.l2cache.demand_miss_latency::total 42150000 # number of demand (read+write) miss cycles -system.l2cache.overall_miss_latency::cpu.inst 28661000 # number of overall miss cycles -system.l2cache.overall_miss_latency::cpu.data 13489000 # number of overall miss cycles -system.l2cache.overall_miss_latency::total 42150000 # number of overall miss cycles +system.l2cache.ReadExReq_miss_latency::cpu.data 5226000 # number of ReadExReq miss cycles +system.l2cache.ReadExReq_miss_latency::total 5226000 # number of ReadExReq miss cycles +system.l2cache.ReadSharedReq_miss_latency::cpu.inst 28537000 # number of ReadSharedReq miss cycles +system.l2cache.ReadSharedReq_miss_latency::cpu.data 8610000 # number of ReadSharedReq miss cycles +system.l2cache.ReadSharedReq_miss_latency::total 37147000 # number of ReadSharedReq miss cycles +system.l2cache.demand_miss_latency::cpu.inst 28537000 # number of demand (read+write) miss cycles +system.l2cache.demand_miss_latency::cpu.data 13836000 # number of demand (read+write) miss cycles +system.l2cache.demand_miss_latency::total 42373000 # number of demand (read+write) miss cycles +system.l2cache.overall_miss_latency::cpu.inst 28537000 # number of overall miss cycles +system.l2cache.overall_miss_latency::cpu.data 13836000 # number of overall miss cycles +system.l2cache.overall_miss_latency::total 42373000 # number of overall miss cycles system.l2cache.ReadExReq_accesses::cpu.data 50 # number of ReadExReq accesses(hits+misses) system.l2cache.ReadExReq_accesses::total 50 # number of ReadExReq accesses(hits+misses) system.l2cache.ReadSharedReq_accesses::cpu.inst 297 # number of ReadSharedReq accesses(hits+misses) @@ -621,17 +621,17 @@ system.l2cache.demand_miss_rate::total 0.990783 # mi system.l2cache.overall_miss_rate::cpu.inst 0.986532 # miss rate for overall accesses system.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.l2cache.overall_miss_rate::total 0.990783 # miss rate for overall accesses -system.l2cache.ReadExReq_avg_miss_latency::cpu.data 100280 # average ReadExReq miss latency -system.l2cache.ReadExReq_avg_miss_latency::total 100280 # average ReadExReq miss latency -system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 97819.112628 # average ReadSharedReq miss latency -system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 97413.793103 # average ReadSharedReq miss latency -system.l2cache.ReadSharedReq_avg_miss_latency::total 97726.315789 # average ReadSharedReq miss latency -system.l2cache.demand_avg_miss_latency::cpu.inst 97819.112628 # average overall miss latency -system.l2cache.demand_avg_miss_latency::cpu.data 98459.854015 # average overall miss latency -system.l2cache.demand_avg_miss_latency::total 98023.255814 # average overall miss latency -system.l2cache.overall_avg_miss_latency::cpu.inst 97819.112628 # average overall miss latency -system.l2cache.overall_avg_miss_latency::cpu.data 98459.854015 # average overall miss latency -system.l2cache.overall_avg_miss_latency::total 98023.255814 # average overall miss latency +system.l2cache.ReadExReq_avg_miss_latency::cpu.data 104520 # average ReadExReq miss latency +system.l2cache.ReadExReq_avg_miss_latency::total 104520 # average ReadExReq miss latency +system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 97395.904437 # average ReadSharedReq miss latency +system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 98965.517241 # average ReadSharedReq miss latency +system.l2cache.ReadSharedReq_avg_miss_latency::total 97755.263158 # average ReadSharedReq miss latency +system.l2cache.demand_avg_miss_latency::cpu.inst 97395.904437 # average overall miss latency +system.l2cache.demand_avg_miss_latency::cpu.data 100992.700730 # average overall miss latency +system.l2cache.demand_avg_miss_latency::total 98541.860465 # average overall miss latency +system.l2cache.overall_avg_miss_latency::cpu.inst 97395.904437 # average overall miss latency +system.l2cache.overall_avg_miss_latency::cpu.data 100992.700730 # average overall miss latency +system.l2cache.overall_avg_miss_latency::total 98541.860465 # average overall miss latency system.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -649,17 +649,17 @@ system.l2cache.demand_mshr_misses::total 430 # nu system.l2cache.overall_mshr_misses::cpu.inst 293 # number of overall MSHR misses system.l2cache.overall_mshr_misses::cpu.data 137 # number of overall MSHR misses system.l2cache.overall_mshr_misses::total 430 # number of overall MSHR misses -system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4014000 # number of ReadExReq MSHR miss cycles -system.l2cache.ReadExReq_mshr_miss_latency::total 4014000 # number of ReadExReq MSHR miss cycles -system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 22801000 # number of ReadSharedReq MSHR miss cycles -system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6735000 # number of ReadSharedReq MSHR miss cycles -system.l2cache.ReadSharedReq_mshr_miss_latency::total 29536000 # number of ReadSharedReq MSHR miss cycles -system.l2cache.demand_mshr_miss_latency::cpu.inst 22801000 # number of demand (read+write) MSHR miss cycles -system.l2cache.demand_mshr_miss_latency::cpu.data 10749000 # number of demand (read+write) MSHR miss cycles -system.l2cache.demand_mshr_miss_latency::total 33550000 # number of demand (read+write) MSHR miss cycles -system.l2cache.overall_mshr_miss_latency::cpu.inst 22801000 # number of overall MSHR miss cycles -system.l2cache.overall_mshr_miss_latency::cpu.data 10749000 # number of overall MSHR miss cycles -system.l2cache.overall_mshr_miss_latency::total 33550000 # number of overall MSHR miss cycles +system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4226000 # number of ReadExReq MSHR miss cycles +system.l2cache.ReadExReq_mshr_miss_latency::total 4226000 # number of ReadExReq MSHR miss cycles +system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 22677000 # number of ReadSharedReq MSHR miss cycles +system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6870000 # number of ReadSharedReq MSHR miss cycles +system.l2cache.ReadSharedReq_mshr_miss_latency::total 29547000 # number of ReadSharedReq MSHR miss cycles +system.l2cache.demand_mshr_miss_latency::cpu.inst 22677000 # number of demand (read+write) MSHR miss cycles +system.l2cache.demand_mshr_miss_latency::cpu.data 11096000 # number of demand (read+write) MSHR miss cycles +system.l2cache.demand_mshr_miss_latency::total 33773000 # number of demand (read+write) MSHR miss cycles +system.l2cache.overall_mshr_miss_latency::cpu.inst 22677000 # number of overall MSHR miss cycles +system.l2cache.overall_mshr_miss_latency::cpu.data 11096000 # number of overall MSHR miss cycles +system.l2cache.overall_mshr_miss_latency::total 33773000 # number of overall MSHR miss cycles system.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.inst 0.986532 # mshr miss rate for ReadSharedReq accesses @@ -671,18 +671,24 @@ system.l2cache.demand_mshr_miss_rate::total 0.990783 # system.l2cache.overall_mshr_miss_rate::cpu.inst 0.986532 # mshr miss rate for overall accesses system.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.l2cache.overall_mshr_miss_rate::total 0.990783 # mshr miss rate for overall accesses -system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80280 # average ReadExReq mshr miss latency -system.l2cache.ReadExReq_avg_mshr_miss_latency::total 80280 # average ReadExReq mshr miss latency -system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 77819.112628 # average ReadSharedReq mshr miss latency -system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 77413.793103 # average ReadSharedReq mshr miss latency -system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 77726.315789 # average ReadSharedReq mshr miss latency -system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 77819.112628 # average overall mshr miss latency -system.l2cache.demand_avg_mshr_miss_latency::cpu.data 78459.854015 # average overall mshr miss latency -system.l2cache.demand_avg_mshr_miss_latency::total 78023.255814 # average overall mshr miss latency -system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 77819.112628 # average overall mshr miss latency -system.l2cache.overall_avg_mshr_miss_latency::cpu.data 78459.854015 # average overall mshr miss latency -system.l2cache.overall_avg_mshr_miss_latency::total 78023.255814 # average overall mshr miss latency -system.membus.pwrStateResidencyTicks::UNDEFINED 58892000 # Cumulative time (in ticks) in various power states +system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 84520 # average ReadExReq mshr miss latency +system.l2cache.ReadExReq_avg_mshr_miss_latency::total 84520 # average ReadExReq mshr miss latency +system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 77395.904437 # average ReadSharedReq mshr miss latency +system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 78965.517241 # average ReadSharedReq mshr miss latency +system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 77755.263158 # average ReadSharedReq mshr miss latency +system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 77395.904437 # average overall mshr miss latency +system.l2cache.demand_avg_mshr_miss_latency::cpu.data 80992.700730 # average overall mshr miss latency +system.l2cache.demand_avg_mshr_miss_latency::total 78541.860465 # average overall mshr miss latency +system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 77395.904437 # average overall mshr miss latency +system.l2cache.overall_avg_mshr_miss_latency::cpu.data 80992.700730 # average overall mshr miss latency +system.l2cache.overall_avg_mshr_miss_latency::total 78541.860465 # average overall mshr miss latency +system.membus.snoop_filter.tot_requests 430 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 59115000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 380 # Transaction distribution system.membus.trans_dist::ReadExReq 50 # Transaction distribution system.membus.trans_dist::ReadExResp 50 # Transaction distribution @@ -705,7 +711,7 @@ system.membus.snoop_fanout::max_value 0 # Re system.membus.snoop_fanout::total 430 # Request fanout histogram system.membus.reqLayer0.occupancy 430000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.7 # Layer utilization (%) -system.membus.respLayer0.occupancy 2299000 # Layer occupancy (ticks) +system.membus.respLayer0.occupancy 2298000 # Layer occupancy (ticks) system.membus.respLayer0.utilization 3.9 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-simple/stats.txt b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-simple/stats.txt index 81f7b029f..9a120d100 100644 --- a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-simple/stats.txt +++ b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-simple/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000333 # Number of seconds simulated -sim_ticks 333033000 # Number of ticks simulated -final_tick 333033000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000340 # Number of seconds simulated +sim_ticks 340278000 # Number of ticks simulated +final_tick 340278000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 341593 # Simulator instruction rate (inst/s) -host_op_rate 341350 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 20477364302 # Simulator tick rate (ticks/s) -host_mem_usage 630048 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host +host_inst_rate 140763 # Simulator instruction rate (inst/s) +host_op_rate 140716 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 8627820590 # Simulator tick rate (ticks/s) +host_mem_usage 633396 # Number of bytes of host memory used +host_seconds 0.04 # Real time elapsed on the host sim_insts 5548 # Number of instructions simulated sim_ops 5548 # Number of ops (including micro ops) simulated system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 333033000 # Cumulative time (in ticks) in various power states +system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 340278000 # Cumulative time (in ticks) in various power states system.mem_ctrl.bytes_read::cpu.inst 22364 # Number of bytes read from this memory system.mem_ctrl.bytes_read::cpu.data 4640 # Number of bytes read from this memory system.mem_ctrl.bytes_read::total 27004 # Number of bytes read from this memory @@ -26,42 +26,42 @@ system.mem_ctrl.num_reads::cpu.data 718 # Nu system.mem_ctrl.num_reads::total 6309 # Number of read requests responded to by this memory system.mem_ctrl.num_writes::cpu.data 673 # Number of write requests responded to by this memory system.mem_ctrl.num_writes::total 673 # Number of write requests responded to by this memory -system.mem_ctrl.bw_read::cpu.inst 67152504 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::cpu.data 13932553 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::total 81085058 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::cpu.inst 67152504 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::total 67152504 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_write::cpu.data 15208703 # Write bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_write::total 15208703 # Write bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.inst 67152504 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.data 29141256 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::total 96293761 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_read::cpu.inst 65722733 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_read::cpu.data 13635909 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_read::total 79358642 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_inst_read::cpu.inst 65722733 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_inst_read::total 65722733 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_write::cpu.data 14884888 # Write bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_write::total 14884888 # Write bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_total::cpu.inst 65722733 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_total::cpu.data 28520798 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_total::total 94243530 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrl.readReqs 6310 # Number of read requests accepted system.mem_ctrl.writeReqs 673 # Number of write requests accepted system.mem_ctrl.readBursts 6310 # Number of DRAM read bursts, including those serviced by the write queue system.mem_ctrl.writeBursts 673 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrl.bytesReadDRAM 397376 # Total number of bytes read from DRAM -system.mem_ctrl.bytesReadWrQ 6464 # Total number of bytes read from write queue +system.mem_ctrl.bytesReadDRAM 397824 # Total number of bytes read from DRAM +system.mem_ctrl.bytesReadWrQ 6016 # Total number of bytes read from write queue system.mem_ctrl.bytesWritten 6144 # Total number of bytes written to DRAM system.mem_ctrl.bytesReadSys 27008 # Total read bytes from the system interface side system.mem_ctrl.bytesWrittenSys 5065 # Total written bytes from the system interface side -system.mem_ctrl.servicedByWrQ 101 # Number of DRAM read bursts serviced by the write queue -system.mem_ctrl.mergedWrBursts 551 # Number of DRAM write bursts merged with an existing one +system.mem_ctrl.servicedByWrQ 94 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrl.mergedWrBursts 548 # Number of DRAM write bursts merged with an existing one system.mem_ctrl.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.mem_ctrl.perBankRdBursts::0 220 # Per bank write bursts system.mem_ctrl.perBankRdBursts::1 84 # Per bank write bursts system.mem_ctrl.perBankRdBursts::2 2 # Per bank write bursts system.mem_ctrl.perBankRdBursts::3 199 # Per bank write bursts system.mem_ctrl.perBankRdBursts::4 0 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::5 1001 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::5 1005 # Per bank write bursts system.mem_ctrl.perBankRdBursts::6 1555 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::7 876 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::7 875 # Per bank write bursts system.mem_ctrl.perBankRdBursts::8 710 # Per bank write bursts system.mem_ctrl.perBankRdBursts::9 348 # Per bank write bursts system.mem_ctrl.perBankRdBursts::10 99 # Per bank write bursts system.mem_ctrl.perBankRdBursts::11 623 # Per bank write bursts system.mem_ctrl.perBankRdBursts::12 56 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::13 158 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::13 162 # Per bank write bursts system.mem_ctrl.perBankRdBursts::14 200 # Per bank write bursts system.mem_ctrl.perBankRdBursts::15 78 # Per bank write bursts system.mem_ctrl.perBankWrBursts::0 0 # Per bank write bursts @@ -69,9 +69,9 @@ system.mem_ctrl.perBankWrBursts::1 0 # Pe system.mem_ctrl.perBankWrBursts::2 0 # Per bank write bursts system.mem_ctrl.perBankWrBursts::3 0 # Per bank write bursts system.mem_ctrl.perBankWrBursts::4 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::5 14 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::6 37 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::7 27 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::5 17 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::6 42 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::7 19 # Per bank write bursts system.mem_ctrl.perBankWrBursts::8 0 # Per bank write bursts system.mem_ctrl.perBankWrBursts::9 5 # Per bank write bursts system.mem_ctrl.perBankWrBursts::10 0 # Per bank write bursts @@ -82,7 +82,7 @@ system.mem_ctrl.perBankWrBursts::14 0 # Pe system.mem_ctrl.perBankWrBursts::15 0 # Per bank write bursts system.mem_ctrl.numRdRetry 0 # Number of times read queue was full causing retry system.mem_ctrl.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrl.totGap 332957000 # Total gap between requests +system.mem_ctrl.totGap 340201000 # Total gap between requests system.mem_ctrl.readPktSize::0 88 # Read request sizes (log2) system.mem_ctrl.readPktSize::1 2 # Read request sizes (log2) system.mem_ctrl.readPktSize::2 5711 # Read request sizes (log2) @@ -97,7 +97,7 @@ system.mem_ctrl.writePktSize::3 604 # Wr system.mem_ctrl.writePktSize::4 0 # Write request sizes (log2) system.mem_ctrl.writePktSize::5 0 # Write request sizes (log2) system.mem_ctrl.writePktSize::6 0 # Write request sizes (log2) -system.mem_ctrl.rdQLenPdf::0 6209 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::0 6216 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::1 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::2 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::3 0 # What read queue length does an incoming req see @@ -155,9 +155,9 @@ system.mem_ctrl.wrQLenPdf::22 7 # Wh system.mem_ctrl.wrQLenPdf::23 7 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::24 7 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::25 7 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::26 6 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::27 6 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::28 6 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::26 7 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::27 7 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::28 7 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::29 6 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::30 6 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::31 6 # What write queue length does an incoming req see @@ -194,23 +194,23 @@ system.mem_ctrl.wrQLenPdf::61 0 # Wh system.mem_ctrl.wrQLenPdf::62 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::63 0 # What write queue length does an incoming req see system.mem_ctrl.bytesPerActivate::samples 569 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::mean 706.024605 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::gmean 523.041408 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::stdev 385.942790 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::0-127 49 8.61% 8.61% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::128-255 76 13.36% 21.97% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::256-383 38 6.68% 28.65% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::384-511 27 4.75% 33.39% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::512-639 21 3.69% 37.08% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::640-767 21 3.69% 40.77% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::768-895 15 2.64% 43.41% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::mean 706.474517 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::gmean 522.857650 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::stdev 386.052257 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::0-127 51 8.96% 8.96% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::128-255 75 13.18% 22.14% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::256-383 39 6.85% 29.00% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::384-511 23 4.04% 33.04% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::512-639 22 3.87% 36.91% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::640-767 18 3.16% 40.07% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::768-895 19 3.34% 43.41% # Bytes accessed per row activation system.mem_ctrl.bytesPerActivate::896-1023 24 4.22% 47.63% # Bytes accessed per row activation system.mem_ctrl.bytesPerActivate::1024-1151 298 52.37% 100.00% # Bytes accessed per row activation system.mem_ctrl.bytesPerActivate::total 569 # Bytes accessed per row activation system.mem_ctrl.rdPerTurnAround::samples 6 # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::mean 772.166667 # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::gmean 643.154197 # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::stdev 524.176084 # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::mean 772.333333 # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::gmean 643.216539 # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::stdev 524.537383 # Reads before turning the bus around for writes system.mem_ctrl.rdPerTurnAround::256-319 2 33.33% 33.33% # Reads before turning the bus around for writes system.mem_ctrl.rdPerTurnAround::640-703 1 16.67% 50.00% # Reads before turning the bus around for writes system.mem_ctrl.rdPerTurnAround::704-767 1 16.67% 66.67% # Reads before turning the bus around for writes @@ -222,60 +222,60 @@ system.mem_ctrl.wrPerTurnAround::mean 16 # Wr system.mem_ctrl.wrPerTurnAround::gmean 16.000000 # Writes before turning the bus around for reads system.mem_ctrl.wrPerTurnAround::16 6 100.00% 100.00% # Writes before turning the bus around for reads system.mem_ctrl.wrPerTurnAround::total 6 # Writes before turning the bus around for reads -system.mem_ctrl.totQLat 19522250 # Total ticks spent queuing -system.mem_ctrl.totMemAccLat 135941000 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrl.totBusLat 31045000 # Total ticks spent in databus transfers -system.mem_ctrl.avgQLat 3144.19 # Average queueing delay per DRAM burst +system.mem_ctrl.totQLat 19583750 # Total ticks spent queuing +system.mem_ctrl.totMemAccLat 136133750 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrl.totBusLat 31080000 # Total ticks spent in databus transfers +system.mem_ctrl.avgQLat 3150.54 # Average queueing delay per DRAM burst system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.mem_ctrl.avgMemAccLat 21894.19 # Average memory access latency per DRAM burst -system.mem_ctrl.avgRdBW 1193.20 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrl.avgWrBW 18.45 # Average achieved write bandwidth in MiByte/s -system.mem_ctrl.avgRdBWSys 81.10 # Average system read bandwidth in MiByte/s -system.mem_ctrl.avgWrBWSys 15.21 # Average system write bandwidth in MiByte/s +system.mem_ctrl.avgMemAccLat 21900.54 # Average memory access latency per DRAM burst +system.mem_ctrl.avgRdBW 1169.11 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrl.avgWrBW 18.06 # Average achieved write bandwidth in MiByte/s +system.mem_ctrl.avgRdBWSys 79.37 # Average system read bandwidth in MiByte/s +system.mem_ctrl.avgWrBWSys 14.88 # Average system write bandwidth in MiByte/s system.mem_ctrl.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrl.busUtil 9.47 # Data bus utilization in percentage -system.mem_ctrl.busUtilRead 9.32 # Data bus utilization in percentage for reads +system.mem_ctrl.busUtil 9.27 # Data bus utilization in percentage +system.mem_ctrl.busUtilRead 9.13 # Data bus utilization in percentage for reads system.mem_ctrl.busUtilWrite 0.14 # Data bus utilization in percentage for writes system.mem_ctrl.avgRdQLen 1.00 # Average read queue length when enqueuing -system.mem_ctrl.avgWrQLen 22.95 # Average write queue length when enqueuing -system.mem_ctrl.readRowHits 5646 # Number of row buffer hits during reads -system.mem_ctrl.writeRowHits 86 # Number of row buffer hits during writes -system.mem_ctrl.readRowHitRate 90.93 # Row buffer hit rate for reads -system.mem_ctrl.writeRowHitRate 70.49 # Row buffer hit rate for writes -system.mem_ctrl.avgGap 47681.08 # Average gap between requests -system.mem_ctrl.pageHitRate 90.54 # Row buffer hit rate, read and write combined -system.mem_ctrl_0.actEnergy 2676240 # Energy for activate commands per rank (pJ) -system.mem_ctrl_0.preEnergy 1460250 # Energy for precharge commands per rank (pJ) -system.mem_ctrl_0.readEnergy 29983200 # Energy for read commands per rank (pJ) +system.mem_ctrl.avgWrQLen 23.19 # Average write queue length when enqueuing +system.mem_ctrl.readRowHits 5657 # Number of row buffer hits during reads +system.mem_ctrl.writeRowHits 82 # Number of row buffer hits during writes +system.mem_ctrl.readRowHitRate 91.01 # Row buffer hit rate for reads +system.mem_ctrl.writeRowHitRate 65.60 # Row buffer hit rate for writes +system.mem_ctrl.avgGap 48718.46 # Average gap between requests +system.mem_ctrl.pageHitRate 90.51 # Row buffer hit rate, read and write combined +system.mem_ctrl_0.actEnergy 2653560 # Energy for activate commands per rank (pJ) +system.mem_ctrl_0.preEnergy 1447875 # Energy for precharge commands per rank (pJ) +system.mem_ctrl_0.readEnergy 30108000 # Energy for read commands per rank (pJ) system.mem_ctrl_0.writeEnergy 505440 # Energy for write commands per rank (pJ) -system.mem_ctrl_0.refreshEnergy 21359520 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_0.actBackEnergy 211046490 # Energy for active background per rank (pJ) -system.mem_ctrl_0.preBackEnergy 11241000 # Energy for precharge background per rank (pJ) -system.mem_ctrl_0.totalEnergy 278272140 # Total energy per rank (pJ) -system.mem_ctrl_0.averagePower 850.250594 # Core power per rank (mW) -system.mem_ctrl_0.memoryStateTime::IDLE 16881000 # Time in different power states -system.mem_ctrl_0.memoryStateTime::REF 10920000 # Time in different power states +system.mem_ctrl_0.refreshEnergy 21868080 # Energy for refresh commands per rank (pJ) +system.mem_ctrl_0.actBackEnergy 217242675 # Energy for active background per rank (pJ) +system.mem_ctrl_0.preBackEnergy 10477500 # Energy for precharge background per rank (pJ) +system.mem_ctrl_0.totalEnergy 284303130 # Total energy per rank (pJ) +system.mem_ctrl_0.averagePower 848.491929 # Core power per rank (mW) +system.mem_ctrl_0.memoryStateTime::IDLE 15805250 # Time in different power states +system.mem_ctrl_0.memoryStateTime::REF 11180000 # Time in different power states system.mem_ctrl_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrl_0.memoryStateTime::ACT 299495250 # Time in different power states +system.mem_ctrl_0.memoryStateTime::ACT 311151750 # Time in different power states system.mem_ctrl_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrl_1.actEnergy 1587600 # Energy for activate commands per rank (pJ) -system.mem_ctrl_1.preEnergy 866250 # Energy for precharge commands per rank (pJ) -system.mem_ctrl_1.readEnergy 17604600 # Energy for read commands per rank (pJ) +system.mem_ctrl_1.actEnergy 1617840 # Energy for activate commands per rank (pJ) +system.mem_ctrl_1.preEnergy 882750 # Energy for precharge commands per rank (pJ) +system.mem_ctrl_1.readEnergy 17635800 # Energy for read commands per rank (pJ) system.mem_ctrl_1.writeEnergy 116640 # Energy for write commands per rank (pJ) -system.mem_ctrl_1.refreshEnergy 21359520 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_1.actBackEnergy 163497375 # Energy for active background per rank (pJ) -system.mem_ctrl_1.preBackEnergy 52950750 # Energy for precharge background per rank (pJ) -system.mem_ctrl_1.totalEnergy 257982735 # Total energy per rank (pJ) -system.mem_ctrl_1.averagePower 788.257041 # Core power per rank (mW) -system.mem_ctrl_1.memoryStateTime::IDLE 88704750 # Time in different power states -system.mem_ctrl_1.memoryStateTime::REF 10920000 # Time in different power states +system.mem_ctrl_1.refreshEnergy 21868080 # Energy for refresh commands per rank (pJ) +system.mem_ctrl_1.actBackEnergy 174520890 # Energy for active background per rank (pJ) +system.mem_ctrl_1.preBackEnergy 47944500 # Energy for precharge background per rank (pJ) +system.mem_ctrl_1.totalEnergy 264586500 # Total energy per rank (pJ) +system.mem_ctrl_1.averagePower 789.680799 # Core power per rank (mW) +system.mem_ctrl_1.memoryStateTime::IDLE 79696000 # Time in different power states +system.mem_ctrl_1.memoryStateTime::REF 11180000 # Time in different power states system.mem_ctrl_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrl_1.memoryStateTime::ACT 229634250 # Time in different power states +system.mem_ctrl_1.memoryStateTime::ACT 245540000 # Time in different power states system.mem_ctrl_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 333033000 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 340278000 # Cumulative time (in ticks) in various power states system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 333033000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 333033 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 340278000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 340278 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 5548 # Number of instructions committed @@ -294,7 +294,7 @@ system.cpu.num_mem_refs 1404 # nu system.cpu.num_load_insts 726 # Number of load instructions system.cpu.num_store_insts 678 # Number of store instructions system.cpu.num_idle_cycles 0.001000 # Number of idle cycles -system.cpu.num_busy_cycles 333032.999000 # Number of busy cycles +system.cpu.num_busy_cycles 340277.999000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 1187 # Number of branches fetched @@ -333,7 +333,13 @@ system.cpu.op_class::MemWrite 678 12.13% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 5591 # Class of executed instruction -system.membus.pwrStateResidencyTicks::UNDEFINED 333033000 # Cumulative time (in ticks) in various power states +system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 340278000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 6310 # Transaction distribution system.membus.trans_dist::ReadResp 6309 # Transaction distribution system.membus.trans_dist::WriteReq 673 # Transaction distribution @@ -347,19 +353,19 @@ system.membus.pkt_size::total 32069 # Cu system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) system.membus.snoop_fanout::samples 6983 # Request fanout histogram -system.membus.snoop_fanout::mean 0.800802 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.399426 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 1391 19.92% 19.92% # Request fanout histogram -system.membus.snoop_fanout::1 5592 80.08% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 6983 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 6983 # Request fanout histogram system.membus.reqLayer0.occupancy 7656000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.3 # Layer utilization (%) -system.membus.respLayer0.occupancy 12692250 # Layer occupancy (ticks) -system.membus.respLayer0.utilization 3.8 # Layer utilization (%) +system.membus.reqLayer0.utilization 2.2 # Layer utilization (%) +system.membus.respLayer0.occupancy 12692500 # Layer occupancy (ticks) +system.membus.respLayer0.utilization 3.7 # Layer utilization (%) system.membus.respLayer1.occupancy 2298500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.7 # Layer utilization (%) diff --git a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/stats.txt b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/stats.txt index 6107833ad..563f4d9b3 100644 --- a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/stats.txt +++ b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000053 # Number of seconds simulated -sim_ticks 53334000 # Number of ticks simulated -final_tick 53334000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000054 # Number of seconds simulated +sim_ticks 53605000 # Number of ticks simulated +final_tick 53605000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 532040 # Simulator instruction rate (inst/s) -host_op_rate 531414 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5103257870 # Simulator tick rate (ticks/s) -host_mem_usage 634140 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host +host_inst_rate 205629 # Simulator instruction rate (inst/s) +host_op_rate 205519 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1984690430 # Simulator tick rate (ticks/s) +host_mem_usage 637752 # Number of bytes of host memory used +host_seconds 0.03 # Real time elapsed on the host sim_insts 5548 # Number of instructions simulated sim_ops 5548 # Number of ops (including micro ops) simulated system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 53334000 # Cumulative time (in ticks) in various power states +system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 53605000 # Cumulative time (in ticks) in various power states system.mem_ctrl.bytes_read::cpu.inst 16448 # Number of bytes read from this memory system.mem_ctrl.bytes_read::cpu.data 8768 # Number of bytes read from this memory system.mem_ctrl.bytes_read::total 25216 # Number of bytes read from this memory @@ -22,14 +22,14 @@ system.mem_ctrl.bytes_inst_read::total 16448 # Nu system.mem_ctrl.num_reads::cpu.inst 257 # Number of read requests responded to by this memory system.mem_ctrl.num_reads::cpu.data 137 # Number of read requests responded to by this memory system.mem_ctrl.num_reads::total 394 # Number of read requests responded to by this memory -system.mem_ctrl.bw_read::cpu.inst 308396145 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::cpu.data 164397945 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::total 472794090 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::cpu.inst 308396145 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::total 308396145 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.inst 308396145 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.data 164397945 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::total 472794090 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_read::cpu.inst 306837049 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_read::cpu.data 163566831 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_read::total 470403880 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_inst_read::cpu.inst 306837049 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_inst_read::total 306837049 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_total::cpu.inst 306837049 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_total::cpu.data 163566831 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_total::total 470403880 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrl.readReqs 394 # Number of read requests accepted system.mem_ctrl.writeReqs 0 # Number of write requests accepted system.mem_ctrl.readBursts 394 # Number of DRAM read bursts, including those serviced by the write queue @@ -76,7 +76,7 @@ system.mem_ctrl.perBankWrBursts::14 0 # Pe system.mem_ctrl.perBankWrBursts::15 0 # Per bank write bursts system.mem_ctrl.numRdRetry 0 # Number of times read queue was full causing retry system.mem_ctrl.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrl.totGap 53238000 # Total gap between requests +system.mem_ctrl.totGap 53508000 # Total gap between requests system.mem_ctrl.readPktSize::0 0 # Read request sizes (log2) system.mem_ctrl.readPktSize::1 0 # Read request sizes (log2) system.mem_ctrl.readPktSize::2 0 # Read request sizes (log2) @@ -187,78 +187,77 @@ system.mem_ctrl.wrQLenPdf::60 0 # Wh system.mem_ctrl.wrQLenPdf::61 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::62 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrl.bytesPerActivate::samples 93 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::mean 243.612903 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::gmean 174.394567 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::stdev 202.881901 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::64-127 29 31.18% 31.18% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::128-191 15 16.13% 47.31% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::192-255 11 11.83% 59.14% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::256-319 8 8.60% 67.74% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::320-383 6 6.45% 74.19% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::384-447 8 8.60% 82.80% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::448-511 2 2.15% 84.95% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::512-575 3 3.23% 88.17% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::576-639 6 6.45% 94.62% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::640-703 2 2.15% 96.77% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::704-767 1 1.08% 97.85% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::896-959 1 1.08% 98.92% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::960-1023 1 1.08% 100.00% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::total 93 # Bytes accessed per row activation -system.mem_ctrl.totQLat 3010250 # Total ticks spent queuing -system.mem_ctrl.totMemAccLat 10397750 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrl.bytesPerActivate::samples 92 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::mean 246.260870 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::gmean 176.635417 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::stdev 203.037423 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::64-127 28 30.43% 30.43% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::128-191 15 16.30% 46.74% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::192-255 11 11.96% 58.70% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::256-319 8 8.70% 67.39% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::320-383 6 6.52% 73.91% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::384-447 7 7.61% 81.52% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::448-511 3 3.26% 84.78% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::512-575 3 3.26% 88.04% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::576-639 6 6.52% 94.57% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::640-703 2 2.17% 96.74% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::768-831 1 1.09% 97.83% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::896-959 2 2.17% 100.00% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::total 92 # Bytes accessed per row activation +system.mem_ctrl.totQLat 2887500 # Total ticks spent queuing +system.mem_ctrl.totMemAccLat 10275000 # Total ticks spent from burst creation until serviced by the DRAM system.mem_ctrl.totBusLat 1970000 # Total ticks spent in databus transfers -system.mem_ctrl.avgQLat 7640.23 # Average queueing delay per DRAM burst +system.mem_ctrl.avgQLat 7328.68 # Average queueing delay per DRAM burst system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.mem_ctrl.avgMemAccLat 26390.23 # Average memory access latency per DRAM burst -system.mem_ctrl.avgRdBW 472.79 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrl.avgMemAccLat 26078.68 # Average memory access latency per DRAM burst +system.mem_ctrl.avgRdBW 470.40 # Average DRAM read bandwidth in MiByte/s system.mem_ctrl.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.mem_ctrl.avgRdBWSys 472.79 # Average system read bandwidth in MiByte/s +system.mem_ctrl.avgRdBWSys 470.40 # Average system read bandwidth in MiByte/s system.mem_ctrl.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.mem_ctrl.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrl.busUtil 3.69 # Data bus utilization in percentage -system.mem_ctrl.busUtilRead 3.69 # Data bus utilization in percentage for reads +system.mem_ctrl.busUtil 3.68 # Data bus utilization in percentage +system.mem_ctrl.busUtilRead 3.68 # Data bus utilization in percentage for reads system.mem_ctrl.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.mem_ctrl.avgRdQLen 1.00 # Average read queue length when enqueuing system.mem_ctrl.avgWrQLen 0.00 # Average write queue length when enqueuing -system.mem_ctrl.readRowHits 295 # Number of row buffer hits during reads +system.mem_ctrl.readRowHits 296 # Number of row buffer hits during reads system.mem_ctrl.writeRowHits 0 # Number of row buffer hits during writes -system.mem_ctrl.readRowHitRate 74.87 # Row buffer hit rate for reads +system.mem_ctrl.readRowHitRate 75.13 # Row buffer hit rate for reads system.mem_ctrl.writeRowHitRate nan # Row buffer hit rate for writes -system.mem_ctrl.avgGap 135121.83 # Average gap between requests -system.mem_ctrl.pageHitRate 74.87 # Row buffer hit rate, read and write combined -system.mem_ctrl_0.actEnergy 385560 # Energy for activate commands per rank (pJ) -system.mem_ctrl_0.preEnergy 210375 # Energy for precharge commands per rank (pJ) -system.mem_ctrl_0.readEnergy 1622400 # Energy for read commands per rank (pJ) +system.mem_ctrl.avgGap 135807.11 # Average gap between requests +system.mem_ctrl.pageHitRate 75.13 # Row buffer hit rate, read and write combined +system.mem_ctrl_0.actEnergy 378000 # Energy for activate commands per rank (pJ) +system.mem_ctrl_0.preEnergy 206250 # Energy for precharge commands per rank (pJ) +system.mem_ctrl_0.readEnergy 1614600 # Energy for read commands per rank (pJ) system.mem_ctrl_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.mem_ctrl_0.refreshEnergy 3051360 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_0.actBackEnergy 30540600 # Energy for active background per rank (pJ) -system.mem_ctrl_0.preBackEnergy 1396500 # Energy for precharge background per rank (pJ) -system.mem_ctrl_0.totalEnergy 37206795 # Total energy per rank (pJ) -system.mem_ctrl_0.averagePower 792.013091 # Core power per rank (mW) -system.mem_ctrl_0.memoryStateTime::IDLE 2174750 # Time in different power states +system.mem_ctrl_0.actBackEnergy 30461940 # Energy for active background per rank (pJ) +system.mem_ctrl_0.preBackEnergy 1478250 # Energy for precharge background per rank (pJ) +system.mem_ctrl_0.totalEnergy 37190400 # Total energy per rank (pJ) +system.mem_ctrl_0.averagePower 791.306152 # Core power per rank (mW) +system.mem_ctrl_0.memoryStateTime::IDLE 2310750 # Time in different power states system.mem_ctrl_0.memoryStateTime::REF 1560000 # Time in different power states system.mem_ctrl_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrl_0.memoryStateTime::ACT 43256500 # Time in different power states +system.mem_ctrl_0.memoryStateTime::ACT 43141000 # Time in different power states system.mem_ctrl_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrl_1.actEnergy 279720 # Energy for activate commands per rank (pJ) -system.mem_ctrl_1.preEnergy 152625 # Energy for precharge commands per rank (pJ) +system.mem_ctrl_1.actEnergy 272160 # Energy for activate commands per rank (pJ) +system.mem_ctrl_1.preEnergy 148500 # Energy for precharge commands per rank (pJ) system.mem_ctrl_1.readEnergy 1053000 # Energy for read commands per rank (pJ) system.mem_ctrl_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.mem_ctrl_1.refreshEnergy 3051360 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_1.actBackEnergy 29447910 # Energy for active background per rank (pJ) -system.mem_ctrl_1.preBackEnergy 2355000 # Energy for precharge background per rank (pJ) -system.mem_ctrl_1.totalEnergy 36339615 # Total energy per rank (pJ) -system.mem_ctrl_1.averagePower 773.553616 # Core power per rank (mW) -system.mem_ctrl_1.memoryStateTime::IDLE 4798500 # Time in different power states +system.mem_ctrl_1.actBackEnergy 29252115 # Energy for active background per rank (pJ) +system.mem_ctrl_1.preBackEnergy 2526750 # Energy for precharge background per rank (pJ) +system.mem_ctrl_1.totalEnergy 36303885 # Total energy per rank (pJ) +system.mem_ctrl_1.averagePower 772.793039 # Core power per rank (mW) +system.mem_ctrl_1.memoryStateTime::IDLE 5312750 # Time in different power states system.mem_ctrl_1.memoryStateTime::REF 1560000 # Time in different power states system.mem_ctrl_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrl_1.memoryStateTime::ACT 41660500 # Time in different power states +system.mem_ctrl_1.memoryStateTime::ACT 41373250 # Time in different power states system.mem_ctrl_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 53334000 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 53605000 # Cumulative time (in ticks) in various power states system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 53334000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 53334 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 53605000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 53605 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 5548 # Number of instructions committed @@ -277,7 +276,7 @@ system.cpu.num_mem_refs 1404 # nu system.cpu.num_load_insts 726 # Number of load instructions system.cpu.num_store_insts 678 # Number of store instructions system.cpu.num_idle_cycles 0.001000 # Number of idle cycles -system.cpu.num_busy_cycles 53333.999000 # Number of busy cycles +system.cpu.num_busy_cycles 53604.999000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 1187 # Number of branches fetched @@ -316,23 +315,23 @@ system.cpu.op_class::MemWrite 678 12.13% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 5591 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 53334000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 53605000 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 83.743129 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 83.787726 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1253 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 138 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 9.079710 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 83.743129 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.081780 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.081780 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 83.787726 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.081824 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.081824 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 138 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 10 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 128 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.134766 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 2920 # Number of tag accesses system.cpu.dcache.tags.data_accesses 2920 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 53334000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 53605000 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 662 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 662 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 591 # number of WriteReq hits @@ -349,14 +348,14 @@ system.cpu.dcache.demand_misses::cpu.data 138 # n system.cpu.dcache.demand_misses::total 138 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 138 # number of overall misses system.cpu.dcache.overall_misses::total 138 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5534000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5534000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 8431000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 8431000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 13965000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 13965000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 13965000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 13965000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5756000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5756000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 8522000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 8522000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 14278000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 14278000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 14278000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 14278000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 718 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 718 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 673 # number of WriteReq accesses(hits+misses) @@ -373,14 +372,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.099209 system.cpu.dcache.demand_miss_rate::total 0.099209 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.099209 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.099209 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 98821.428571 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 98821.428571 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 102817.073171 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 102817.073171 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 101195.652174 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 101195.652174 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 101195.652174 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 101195.652174 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 102785.714286 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 102785.714286 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 103926.829268 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 103926.829268 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 103463.768116 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 103463.768116 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 103463.768116 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 103463.768116 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -395,14 +394,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 138 system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5422000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5422000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8267000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8267000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13689000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 13689000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13689000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 13689000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5644000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5644000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8358000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8358000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14002000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 14002000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14002000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 14002000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.077994 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.077994 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.121842 # mshr miss rate for WriteReq accesses @@ -411,31 +410,31 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.099209 system.cpu.dcache.demand_mshr_miss_rate::total 0.099209 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.099209 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.099209 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 96821.428571 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 96821.428571 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 100817.073171 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 100817.073171 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 99195.652174 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 99195.652174 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 99195.652174 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 99195.652174 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 53334000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 100785.714286 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 100785.714286 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 101926.829268 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 101926.829268 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 101463.768116 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 101463.768116 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 101463.768116 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 101463.768116 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 53605000 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 71 # number of replacements -system.cpu.icache.tags.tagsinuse 98.062907 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 98.163046 # Cycle average of tags in use system.cpu.icache.tags.total_refs 5333 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 259 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 20.590734 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 98.062907 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.383058 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.383058 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 98.163046 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.383449 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.383449 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 188 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 60 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 128 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 129 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.734375 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 11443 # Number of tag accesses system.cpu.icache.tags.data_accesses 11443 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 53334000 # Cumulative time (in ticks) in various power states +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 53605000 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 5333 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 5333 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 5333 # number of demand (read+write) hits @@ -448,12 +447,12 @@ system.cpu.icache.demand_misses::cpu.inst 259 # n system.cpu.icache.demand_misses::total 259 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 259 # number of overall misses system.cpu.icache.overall_misses::total 259 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 26199000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 26199000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 26199000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 26199000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 26199000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 26199000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 26157000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 26157000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 26157000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 26157000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 26157000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 26157000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 5592 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 5592 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 5592 # number of demand (read+write) accesses @@ -466,12 +465,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.046316 system.cpu.icache.demand_miss_rate::total 0.046316 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.046316 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.046316 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 101154.440154 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 101154.440154 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 101154.440154 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 101154.440154 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 101154.440154 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 101154.440154 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 100992.277992 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 100992.277992 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 100992.277992 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 100992.277992 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 100992.277992 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 100992.277992 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -484,31 +483,31 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 259 system.cpu.icache.demand_mshr_misses::total 259 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 259 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 259 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 25681000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 25681000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 25681000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 25681000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 25681000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 25681000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 25639000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 25639000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 25639000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 25639000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 25639000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 25639000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.046316 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.046316 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.046316 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.046316 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.046316 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.046316 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 99154.440154 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 99154.440154 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 99154.440154 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 99154.440154 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 99154.440154 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 99154.440154 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 98992.277992 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 98992.277992 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 98992.277992 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 98992.277992 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 98992.277992 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 98992.277992 # average overall mshr miss latency system.l2bus.snoop_filter.tot_requests 468 # Total number of requests made to the snoop filter. system.l2bus.snoop_filter.hit_single_requests 73 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.l2bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.l2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.l2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.l2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.l2bus.pwrStateResidencyTicks::UNDEFINED 53334000 # Cumulative time (in ticks) in various power states +system.l2bus.pwrStateResidencyTicks::UNDEFINED 53605000 # Cumulative time (in ticks) in various power states system.l2bus.trans_dist::ReadResp 315 # Transaction distribution system.l2bus.trans_dist::CleanEvict 71 # Transaction distribution system.l2bus.trans_dist::ReadExReq 82 # Transaction distribution @@ -536,28 +535,28 @@ system.l2bus.snoop_fanout::total 397 # Re system.l2bus.reqLayer0.occupancy 468000 # Layer occupancy (ticks) system.l2bus.reqLayer0.utilization 0.9 # Layer utilization (%) system.l2bus.respLayer0.occupancy 777000 # Layer occupancy (ticks) -system.l2bus.respLayer0.utilization 1.5 # Layer utilization (%) +system.l2bus.respLayer0.utilization 1.4 # Layer utilization (%) system.l2bus.respLayer1.occupancy 414000 # Layer occupancy (ticks) system.l2bus.respLayer1.utilization 0.8 # Layer utilization (%) -system.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 53334000 # Cumulative time (in ticks) in various power states +system.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 53605000 # Cumulative time (in ticks) in various power states system.l2cache.tags.replacements 0 # number of replacements -system.l2cache.tags.tagsinuse 144.000978 # Cycle average of tags in use +system.l2cache.tags.tagsinuse 200.697345 # Cycle average of tags in use system.l2cache.tags.total_refs 73 # Total number of references to valid blocks. -system.l2cache.tags.sampled_refs 312 # Sample count of references to valid blocks. -system.l2cache.tags.avg_refs 0.233974 # Average number of references to valid blocks. +system.l2cache.tags.sampled_refs 394 # Sample count of references to valid blocks. +system.l2cache.tags.avg_refs 0.185279 # Average number of references to valid blocks. system.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2cache.tags.occ_blocks::cpu.inst 117.700213 # Average occupied blocks per requestor -system.l2cache.tags.occ_blocks::cpu.data 26.300766 # Average occupied blocks per requestor -system.l2cache.tags.occ_percent::cpu.inst 0.028735 # Average percentage of cache occupancy -system.l2cache.tags.occ_percent::cpu.data 0.006421 # Average percentage of cache occupancy -system.l2cache.tags.occ_percent::total 0.035156 # Average percentage of cache occupancy -system.l2cache.tags.occ_task_id_blocks::1024 312 # Occupied blocks per task id +system.l2cache.tags.occ_blocks::cpu.inst 117.835895 # Average occupied blocks per requestor +system.l2cache.tags.occ_blocks::cpu.data 82.861451 # Average occupied blocks per requestor +system.l2cache.tags.occ_percent::cpu.inst 0.028769 # Average percentage of cache occupancy +system.l2cache.tags.occ_percent::cpu.data 0.020230 # Average percentage of cache occupancy +system.l2cache.tags.occ_percent::total 0.048998 # Average percentage of cache occupancy +system.l2cache.tags.occ_task_id_blocks::1024 394 # Occupied blocks per task id system.l2cache.tags.age_task_id_blocks_1024::0 68 # Occupied blocks per task id -system.l2cache.tags.age_task_id_blocks_1024::1 244 # Occupied blocks per task id -system.l2cache.tags.occ_task_id_percent::1024 0.076172 # Percentage of cache occupancy per task id +system.l2cache.tags.age_task_id_blocks_1024::1 326 # Occupied blocks per task id +system.l2cache.tags.occ_task_id_percent::1024 0.096191 # Percentage of cache occupancy per task id system.l2cache.tags.tag_accesses 4130 # Number of tag accesses system.l2cache.tags.data_accesses 4130 # Number of data accesses -system.l2cache.pwrStateResidencyTicks::UNDEFINED 53334000 # Cumulative time (in ticks) in various power states +system.l2cache.pwrStateResidencyTicks::UNDEFINED 53605000 # Cumulative time (in ticks) in various power states system.l2cache.ReadSharedReq_hits::cpu.inst 2 # number of ReadSharedReq hits system.l2cache.ReadSharedReq_hits::cpu.data 1 # number of ReadSharedReq hits system.l2cache.ReadSharedReq_hits::total 3 # number of ReadSharedReq hits @@ -578,17 +577,17 @@ system.l2cache.demand_misses::total 394 # nu system.l2cache.overall_misses::cpu.inst 257 # number of overall misses system.l2cache.overall_misses::cpu.data 137 # number of overall misses system.l2cache.overall_misses::total 394 # number of overall misses -system.l2cache.ReadExReq_miss_latency::cpu.data 8021000 # number of ReadExReq miss cycles -system.l2cache.ReadExReq_miss_latency::total 8021000 # number of ReadExReq miss cycles -system.l2cache.ReadSharedReq_miss_latency::cpu.inst 24858000 # number of ReadSharedReq miss cycles -system.l2cache.ReadSharedReq_miss_latency::cpu.data 5231000 # number of ReadSharedReq miss cycles -system.l2cache.ReadSharedReq_miss_latency::total 30089000 # number of ReadSharedReq miss cycles -system.l2cache.demand_miss_latency::cpu.inst 24858000 # number of demand (read+write) miss cycles -system.l2cache.demand_miss_latency::cpu.data 13252000 # number of demand (read+write) miss cycles -system.l2cache.demand_miss_latency::total 38110000 # number of demand (read+write) miss cycles -system.l2cache.overall_miss_latency::cpu.inst 24858000 # number of overall miss cycles -system.l2cache.overall_miss_latency::cpu.data 13252000 # number of overall miss cycles -system.l2cache.overall_miss_latency::total 38110000 # number of overall miss cycles +system.l2cache.ReadExReq_miss_latency::cpu.data 8112000 # number of ReadExReq miss cycles +system.l2cache.ReadExReq_miss_latency::total 8112000 # number of ReadExReq miss cycles +system.l2cache.ReadSharedReq_miss_latency::cpu.inst 24816000 # number of ReadSharedReq miss cycles +system.l2cache.ReadSharedReq_miss_latency::cpu.data 5453000 # number of ReadSharedReq miss cycles +system.l2cache.ReadSharedReq_miss_latency::total 30269000 # number of ReadSharedReq miss cycles +system.l2cache.demand_miss_latency::cpu.inst 24816000 # number of demand (read+write) miss cycles +system.l2cache.demand_miss_latency::cpu.data 13565000 # number of demand (read+write) miss cycles +system.l2cache.demand_miss_latency::total 38381000 # number of demand (read+write) miss cycles +system.l2cache.overall_miss_latency::cpu.inst 24816000 # number of overall miss cycles +system.l2cache.overall_miss_latency::cpu.data 13565000 # number of overall miss cycles +system.l2cache.overall_miss_latency::total 38381000 # number of overall miss cycles system.l2cache.ReadExReq_accesses::cpu.data 82 # number of ReadExReq accesses(hits+misses) system.l2cache.ReadExReq_accesses::total 82 # number of ReadExReq accesses(hits+misses) system.l2cache.ReadSharedReq_accesses::cpu.inst 259 # number of ReadSharedReq accesses(hits+misses) @@ -611,17 +610,17 @@ system.l2cache.demand_miss_rate::total 0.992443 # mi system.l2cache.overall_miss_rate::cpu.inst 0.992278 # miss rate for overall accesses system.l2cache.overall_miss_rate::cpu.data 0.992754 # miss rate for overall accesses system.l2cache.overall_miss_rate::total 0.992443 # miss rate for overall accesses -system.l2cache.ReadExReq_avg_miss_latency::cpu.data 97817.073171 # average ReadExReq miss latency -system.l2cache.ReadExReq_avg_miss_latency::total 97817.073171 # average ReadExReq miss latency -system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 96723.735409 # average ReadSharedReq miss latency -system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 95109.090909 # average ReadSharedReq miss latency -system.l2cache.ReadSharedReq_avg_miss_latency::total 96439.102564 # average ReadSharedReq miss latency -system.l2cache.demand_avg_miss_latency::cpu.inst 96723.735409 # average overall miss latency -system.l2cache.demand_avg_miss_latency::cpu.data 96729.927007 # average overall miss latency -system.l2cache.demand_avg_miss_latency::total 96725.888325 # average overall miss latency -system.l2cache.overall_avg_miss_latency::cpu.inst 96723.735409 # average overall miss latency -system.l2cache.overall_avg_miss_latency::cpu.data 96729.927007 # average overall miss latency -system.l2cache.overall_avg_miss_latency::total 96725.888325 # average overall miss latency +system.l2cache.ReadExReq_avg_miss_latency::cpu.data 98926.829268 # average ReadExReq miss latency +system.l2cache.ReadExReq_avg_miss_latency::total 98926.829268 # average ReadExReq miss latency +system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 96560.311284 # average ReadSharedReq miss latency +system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 99145.454545 # average ReadSharedReq miss latency +system.l2cache.ReadSharedReq_avg_miss_latency::total 97016.025641 # average ReadSharedReq miss latency +system.l2cache.demand_avg_miss_latency::cpu.inst 96560.311284 # average overall miss latency +system.l2cache.demand_avg_miss_latency::cpu.data 99014.598540 # average overall miss latency +system.l2cache.demand_avg_miss_latency::total 97413.705584 # average overall miss latency +system.l2cache.overall_avg_miss_latency::cpu.inst 96560.311284 # average overall miss latency +system.l2cache.overall_avg_miss_latency::cpu.data 99014.598540 # average overall miss latency +system.l2cache.overall_avg_miss_latency::total 97413.705584 # average overall miss latency system.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -639,17 +638,17 @@ system.l2cache.demand_mshr_misses::total 394 # nu system.l2cache.overall_mshr_misses::cpu.inst 257 # number of overall MSHR misses system.l2cache.overall_mshr_misses::cpu.data 137 # number of overall MSHR misses system.l2cache.overall_mshr_misses::total 394 # number of overall MSHR misses -system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6381000 # number of ReadExReq MSHR miss cycles -system.l2cache.ReadExReq_mshr_miss_latency::total 6381000 # number of ReadExReq MSHR miss cycles -system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 19718000 # number of ReadSharedReq MSHR miss cycles -system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4131000 # number of ReadSharedReq MSHR miss cycles -system.l2cache.ReadSharedReq_mshr_miss_latency::total 23849000 # number of ReadSharedReq MSHR miss cycles -system.l2cache.demand_mshr_miss_latency::cpu.inst 19718000 # number of demand (read+write) MSHR miss cycles -system.l2cache.demand_mshr_miss_latency::cpu.data 10512000 # number of demand (read+write) MSHR miss cycles -system.l2cache.demand_mshr_miss_latency::total 30230000 # number of demand (read+write) MSHR miss cycles -system.l2cache.overall_mshr_miss_latency::cpu.inst 19718000 # number of overall MSHR miss cycles -system.l2cache.overall_mshr_miss_latency::cpu.data 10512000 # number of overall MSHR miss cycles -system.l2cache.overall_mshr_miss_latency::total 30230000 # number of overall MSHR miss cycles +system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6472000 # number of ReadExReq MSHR miss cycles +system.l2cache.ReadExReq_mshr_miss_latency::total 6472000 # number of ReadExReq MSHR miss cycles +system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 19676000 # number of ReadSharedReq MSHR miss cycles +system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4353000 # number of ReadSharedReq MSHR miss cycles +system.l2cache.ReadSharedReq_mshr_miss_latency::total 24029000 # number of ReadSharedReq MSHR miss cycles +system.l2cache.demand_mshr_miss_latency::cpu.inst 19676000 # number of demand (read+write) MSHR miss cycles +system.l2cache.demand_mshr_miss_latency::cpu.data 10825000 # number of demand (read+write) MSHR miss cycles +system.l2cache.demand_mshr_miss_latency::total 30501000 # number of demand (read+write) MSHR miss cycles +system.l2cache.overall_mshr_miss_latency::cpu.inst 19676000 # number of overall MSHR miss cycles +system.l2cache.overall_mshr_miss_latency::cpu.data 10825000 # number of overall MSHR miss cycles +system.l2cache.overall_mshr_miss_latency::total 30501000 # number of overall MSHR miss cycles system.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.inst 0.992278 # mshr miss rate for ReadSharedReq accesses @@ -661,18 +660,24 @@ system.l2cache.demand_mshr_miss_rate::total 0.992443 # system.l2cache.overall_mshr_miss_rate::cpu.inst 0.992278 # mshr miss rate for overall accesses system.l2cache.overall_mshr_miss_rate::cpu.data 0.992754 # mshr miss rate for overall accesses system.l2cache.overall_mshr_miss_rate::total 0.992443 # mshr miss rate for overall accesses -system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 77817.073171 # average ReadExReq mshr miss latency -system.l2cache.ReadExReq_avg_mshr_miss_latency::total 77817.073171 # average ReadExReq mshr miss latency -system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 76723.735409 # average ReadSharedReq mshr miss latency -system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 75109.090909 # average ReadSharedReq mshr miss latency -system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76439.102564 # average ReadSharedReq mshr miss latency -system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 76723.735409 # average overall mshr miss latency -system.l2cache.demand_avg_mshr_miss_latency::cpu.data 76729.927007 # average overall mshr miss latency -system.l2cache.demand_avg_mshr_miss_latency::total 76725.888325 # average overall mshr miss latency -system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 76723.735409 # average overall mshr miss latency -system.l2cache.overall_avg_mshr_miss_latency::cpu.data 76729.927007 # average overall mshr miss latency -system.l2cache.overall_avg_mshr_miss_latency::total 76725.888325 # average overall mshr miss latency -system.membus.pwrStateResidencyTicks::UNDEFINED 53334000 # Cumulative time (in ticks) in various power states +system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 78926.829268 # average ReadExReq mshr miss latency +system.l2cache.ReadExReq_avg_mshr_miss_latency::total 78926.829268 # average ReadExReq mshr miss latency +system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 76560.311284 # average ReadSharedReq mshr miss latency +system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79145.454545 # average ReadSharedReq mshr miss latency +system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 77016.025641 # average ReadSharedReq mshr miss latency +system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 76560.311284 # average overall mshr miss latency +system.l2cache.demand_avg_mshr_miss_latency::cpu.data 79014.598540 # average overall mshr miss latency +system.l2cache.demand_avg_mshr_miss_latency::total 77413.705584 # average overall mshr miss latency +system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 76560.311284 # average overall mshr miss latency +system.l2cache.overall_avg_mshr_miss_latency::cpu.data 79014.598540 # average overall mshr miss latency +system.l2cache.overall_avg_mshr_miss_latency::total 77413.705584 # average overall mshr miss latency +system.membus.snoop_filter.tot_requests 394 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 53605000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 312 # Transaction distribution system.membus.trans_dist::ReadExReq 82 # Transaction distribution system.membus.trans_dist::ReadExResp 82 # Transaction distribution @@ -695,7 +700,7 @@ system.membus.snoop_fanout::max_value 0 # Re system.membus.snoop_fanout::total 394 # Request fanout histogram system.membus.reqLayer0.occupancy 394000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.7 # Layer utilization (%) -system.membus.respLayer0.occupancy 2102250 # Layer occupancy (ticks) +system.membus.respLayer0.occupancy 2102000 # Layer occupancy (ticks) system.membus.respLayer0.utilization 3.9 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/stats.txt b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/stats.txt index f9a903a5e..7312a839d 100644 --- a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/stats.txt +++ b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000445 # Number of seconds simulated -sim_ticks 445082000 # Number of ticks simulated -final_tick 445082000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000455 # Number of seconds simulated +sim_ticks 454507000 # Number of ticks simulated +final_tick 454507000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 125099 # Simulator instruction rate (inst/s) -host_op_rate 225788 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 9739384878 # Simulator tick rate (ticks/s) -host_mem_usage 648172 # Number of bytes of host memory used -host_seconds 0.05 # Real time elapsed on the host +host_inst_rate 76712 # Simulator instruction rate (inst/s) +host_op_rate 138489 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 6101741543 # Simulator tick rate (ticks/s) +host_mem_usage 651776 # Number of bytes of host memory used +host_seconds 0.07 # Real time elapsed on the host sim_insts 5712 # Number of instructions simulated sim_ops 10314 # Number of ops (including micro ops) simulated system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 445082000 # Cumulative time (in ticks) in various power states +system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 454507000 # Cumulative time (in ticks) in various power states system.mem_ctrl.bytes_read::cpu.inst 58264 # Number of bytes read from this memory system.mem_ctrl.bytes_read::cpu.data 7167 # Number of bytes read from this memory system.mem_ctrl.bytes_read::total 65431 # Number of bytes read from this memory @@ -26,29 +26,29 @@ system.mem_ctrl.num_reads::cpu.data 1084 # Nu system.mem_ctrl.num_reads::total 8367 # Number of read requests responded to by this memory system.mem_ctrl.num_writes::cpu.data 941 # Number of write requests responded to by this memory system.mem_ctrl.num_writes::total 941 # Number of write requests responded to by this memory -system.mem_ctrl.bw_read::cpu.inst 130906215 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::cpu.data 16102651 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::total 147008866 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::cpu.inst 130906215 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::total 130906215 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_write::cpu.data 16086923 # Write bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_write::total 16086923 # Write bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.inst 130906215 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.data 32189574 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::total 163095789 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_read::cpu.inst 128191645 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_read::cpu.data 15768734 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_read::total 143960379 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_inst_read::cpu.inst 128191645 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_inst_read::total 128191645 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_write::cpu.data 15753333 # Write bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_write::total 15753333 # Write bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_total::cpu.inst 128191645 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_total::cpu.data 31522067 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_total::total 159713712 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrl.readReqs 8367 # Number of read requests accepted system.mem_ctrl.writeReqs 941 # Number of write requests accepted system.mem_ctrl.readBursts 8367 # Number of DRAM read bursts, including those serviced by the write queue system.mem_ctrl.writeBursts 941 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrl.bytesReadDRAM 525184 # Total number of bytes read from DRAM -system.mem_ctrl.bytesReadWrQ 10304 # Total number of bytes read from write queue -system.mem_ctrl.bytesWritten 7168 # Total number of bytes written to DRAM +system.mem_ctrl.bytesReadDRAM 524736 # Total number of bytes read from DRAM +system.mem_ctrl.bytesReadWrQ 10752 # Total number of bytes read from write queue +system.mem_ctrl.bytesWritten 6144 # Total number of bytes written to DRAM system.mem_ctrl.bytesReadSys 65431 # Total read bytes from the system interface side system.mem_ctrl.bytesWrittenSys 7160 # Total written bytes from the system interface side -system.mem_ctrl.servicedByWrQ 161 # Number of DRAM read bursts serviced by the write queue -system.mem_ctrl.mergedWrBursts 810 # Number of DRAM write bursts merged with an existing one +system.mem_ctrl.servicedByWrQ 168 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrl.mergedWrBursts 819 # Number of DRAM write bursts merged with an existing one system.mem_ctrl.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.mem_ctrl.perBankRdBursts::0 277 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::0 273 # Per bank write bursts system.mem_ctrl.perBankRdBursts::1 4 # Per bank write bursts system.mem_ctrl.perBankRdBursts::2 227 # Per bank write bursts system.mem_ctrl.perBankRdBursts::3 102 # Per bank write bursts @@ -58,13 +58,13 @@ system.mem_ctrl.perBankRdBursts::6 1103 # Pe system.mem_ctrl.perBankRdBursts::7 906 # Per bank write bursts system.mem_ctrl.perBankRdBursts::8 703 # Per bank write bursts system.mem_ctrl.perBankRdBursts::9 490 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::10 1059 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::10 1055 # Per bank write bursts system.mem_ctrl.perBankRdBursts::11 59 # Per bank write bursts system.mem_ctrl.perBankRdBursts::12 11 # Per bank write bursts system.mem_ctrl.perBankRdBursts::13 489 # Per bank write bursts system.mem_ctrl.perBankRdBursts::14 78 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::15 114 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::0 12 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::15 115 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::0 6 # Per bank write bursts system.mem_ctrl.perBankWrBursts::1 0 # Per bank write bursts system.mem_ctrl.perBankWrBursts::2 0 # Per bank write bursts system.mem_ctrl.perBankWrBursts::3 0 # Per bank write bursts @@ -72,17 +72,17 @@ system.mem_ctrl.perBankWrBursts::4 0 # Pe system.mem_ctrl.perBankWrBursts::5 0 # Per bank write bursts system.mem_ctrl.perBankWrBursts::6 0 # Per bank write bursts system.mem_ctrl.perBankWrBursts::7 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::8 3 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::9 55 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::10 29 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::8 2 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::9 53 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::10 23 # Per bank write bursts system.mem_ctrl.perBankWrBursts::11 7 # Per bank write bursts system.mem_ctrl.perBankWrBursts::12 0 # Per bank write bursts system.mem_ctrl.perBankWrBursts::13 0 # Per bank write bursts system.mem_ctrl.perBankWrBursts::14 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::15 6 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::15 5 # Per bank write bursts system.mem_ctrl.numRdRetry 0 # Number of times read queue was full causing retry system.mem_ctrl.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrl.totGap 444958000 # Total gap between requests +system.mem_ctrl.totGap 454381000 # Total gap between requests system.mem_ctrl.readPktSize::0 135 # Read request sizes (log2) system.mem_ctrl.readPktSize::1 14 # Read request sizes (log2) system.mem_ctrl.readPktSize::2 119 # Read request sizes (log2) @@ -97,7 +97,7 @@ system.mem_ctrl.writePktSize::3 861 # Wr system.mem_ctrl.writePktSize::4 0 # Write request sizes (log2) system.mem_ctrl.writePktSize::5 0 # Write request sizes (log2) system.mem_ctrl.writePktSize::6 0 # Write request sizes (log2) -system.mem_ctrl.rdQLenPdf::0 8206 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::0 8199 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::1 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::2 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::3 0 # What read queue length does an incoming req see @@ -146,8 +146,8 @@ system.mem_ctrl.wrQLenPdf::13 1 # Wh system.mem_ctrl.wrQLenPdf::14 1 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::15 1 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::16 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::17 8 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::18 8 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::17 7 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::18 7 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::19 7 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::20 7 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::21 7 # What write queue length does an incoming req see @@ -155,13 +155,13 @@ system.mem_ctrl.wrQLenPdf::22 7 # Wh system.mem_ctrl.wrQLenPdf::23 7 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::24 7 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::25 7 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::26 7 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::27 7 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::28 7 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::29 7 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::30 7 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::31 7 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::32 7 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::26 6 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::27 6 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::28 6 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::29 6 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::30 6 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::31 6 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::32 6 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::33 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::34 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::35 0 # What write queue length does an incoming req see @@ -194,94 +194,93 @@ system.mem_ctrl.wrQLenPdf::61 0 # Wh system.mem_ctrl.wrQLenPdf::62 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::63 0 # What write queue length does an incoming req see system.mem_ctrl.bytesPerActivate::samples 849 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::mean 625.677267 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::gmean 430.153995 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::stdev 392.580114 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::0-127 141 16.61% 16.61% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::128-255 68 8.01% 24.62% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::256-383 71 8.36% 32.98% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::384-511 65 7.66% 40.64% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::512-639 53 6.24% 46.88% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::640-767 45 5.30% 52.18% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::768-895 35 4.12% 56.30% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::896-1023 15 1.77% 58.07% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::1024-1151 356 41.93% 100.00% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::mean 622.812721 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::gmean 426.803074 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::stdev 394.306776 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::0-127 142 16.73% 16.73% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::128-255 69 8.13% 24.85% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::256-383 77 9.07% 33.92% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::384-511 63 7.42% 41.34% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::512-639 55 6.48% 47.82% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::640-767 39 4.59% 52.41% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::768-895 28 3.30% 55.71% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::896-1023 21 2.47% 58.19% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::1024-1151 355 41.81% 100.00% # Bytes accessed per row activation system.mem_ctrl.bytesPerActivate::total 849 # Bytes accessed per row activation -system.mem_ctrl.rdPerTurnAround::samples 7 # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::mean 1165.285714 # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::gmean 941.793638 # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::stdev 714.559471 # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::256-383 1 14.29% 14.29% # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::384-511 1 14.29% 28.57% # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::640-767 1 14.29% 42.86% # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::1280-1407 1 14.29% 57.14% # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::1408-1535 1 14.29% 71.43% # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::1920-2047 1 14.29% 85.71% # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::2048-2175 1 14.29% 100.00% # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::total 7 # Reads before turning the bus around for writes -system.mem_ctrl.wrPerTurnAround::samples 7 # Writes before turning the bus around for reads +system.mem_ctrl.rdPerTurnAround::samples 6 # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::mean 1282.333333 # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::gmean 1020.532539 # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::stdev 764.587906 # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::256-383 1 16.67% 16.67% # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::384-511 1 16.67% 33.33% # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::1280-1407 1 16.67% 50.00% # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::1408-1535 1 16.67% 66.67% # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::1920-2047 1 16.67% 83.33% # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::2048-2175 1 16.67% 100.00% # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::total 6 # Reads before turning the bus around for writes +system.mem_ctrl.wrPerTurnAround::samples 6 # Writes before turning the bus around for reads system.mem_ctrl.wrPerTurnAround::mean 16 # Writes before turning the bus around for reads system.mem_ctrl.wrPerTurnAround::gmean 16.000000 # Writes before turning the bus around for reads -system.mem_ctrl.wrPerTurnAround::16 7 100.00% 100.00% # Writes before turning the bus around for reads -system.mem_ctrl.wrPerTurnAround::total 7 # Writes before turning the bus around for reads -system.mem_ctrl.totQLat 29060250 # Total ticks spent queuing -system.mem_ctrl.totMemAccLat 182922750 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrl.totBusLat 41030000 # Total ticks spent in databus transfers -system.mem_ctrl.avgQLat 3541.34 # Average queueing delay per DRAM burst +system.mem_ctrl.wrPerTurnAround::16 6 100.00% 100.00% # Writes before turning the bus around for reads +system.mem_ctrl.wrPerTurnAround::total 6 # Writes before turning the bus around for reads +system.mem_ctrl.totQLat 29381000 # Total ticks spent queuing +system.mem_ctrl.totMemAccLat 183112250 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrl.totBusLat 40995000 # Total ticks spent in databus transfers +system.mem_ctrl.avgQLat 3583.49 # Average queueing delay per DRAM burst system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.mem_ctrl.avgMemAccLat 22291.34 # Average memory access latency per DRAM burst -system.mem_ctrl.avgRdBW 1179.97 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrl.avgWrBW 16.10 # Average achieved write bandwidth in MiByte/s -system.mem_ctrl.avgRdBWSys 147.01 # Average system read bandwidth in MiByte/s -system.mem_ctrl.avgWrBWSys 16.09 # Average system write bandwidth in MiByte/s +system.mem_ctrl.avgMemAccLat 22333.49 # Average memory access latency per DRAM burst +system.mem_ctrl.avgRdBW 1154.52 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrl.avgWrBW 13.52 # Average achieved write bandwidth in MiByte/s +system.mem_ctrl.avgRdBWSys 143.96 # Average system read bandwidth in MiByte/s +system.mem_ctrl.avgWrBWSys 15.75 # Average system write bandwidth in MiByte/s system.mem_ctrl.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrl.busUtil 9.34 # Data bus utilization in percentage -system.mem_ctrl.busUtilRead 9.22 # Data bus utilization in percentage for reads -system.mem_ctrl.busUtilWrite 0.13 # Data bus utilization in percentage for writes +system.mem_ctrl.busUtil 9.13 # Data bus utilization in percentage +system.mem_ctrl.busUtilRead 9.02 # Data bus utilization in percentage for reads +system.mem_ctrl.busUtilWrite 0.11 # Data bus utilization in percentage for writes system.mem_ctrl.avgRdQLen 1.00 # Average read queue length when enqueuing -system.mem_ctrl.avgWrQLen 23.76 # Average write queue length when enqueuing -system.mem_ctrl.readRowHits 7369 # Number of row buffer hits during reads -system.mem_ctrl.writeRowHits 98 # Number of row buffer hits during writes -system.mem_ctrl.readRowHitRate 89.80 # Row buffer hit rate for reads -system.mem_ctrl.writeRowHitRate 74.81 # Row buffer hit rate for writes -system.mem_ctrl.avgGap 47803.82 # Average gap between requests -system.mem_ctrl.pageHitRate 89.56 # Row buffer hit rate, read and write combined -system.mem_ctrl_0.actEnergy 3265920 # Energy for activate commands per rank (pJ) -system.mem_ctrl_0.preEnergy 1782000 # Energy for precharge commands per rank (pJ) -system.mem_ctrl_0.readEnergy 40552200 # Energy for read commands per rank (pJ) -system.mem_ctrl_0.writeEnergy 77760 # Energy for write commands per rank (pJ) -system.mem_ctrl_0.refreshEnergy 28987920 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_0.actBackEnergy 242604540 # Energy for active background per rank (pJ) -system.mem_ctrl_0.preBackEnergy 53634750 # Energy for precharge background per rank (pJ) -system.mem_ctrl_0.totalEnergy 370905090 # Total energy per rank (pJ) -system.mem_ctrl_0.averagePower 835.228387 # Core power per rank (mW) -system.mem_ctrl_0.memoryStateTime::IDLE 86580500 # Time in different power states -system.mem_ctrl_0.memoryStateTime::REF 14820000 # Time in different power states +system.mem_ctrl.avgWrQLen 23.84 # Average write queue length when enqueuing +system.mem_ctrl.readRowHits 7356 # Number of row buffer hits during reads +system.mem_ctrl.writeRowHits 85 # Number of row buffer hits during writes +system.mem_ctrl.readRowHitRate 89.72 # Row buffer hit rate for reads +system.mem_ctrl.writeRowHitRate 69.67 # Row buffer hit rate for writes +system.mem_ctrl.avgGap 48816.18 # Average gap between requests +system.mem_ctrl.pageHitRate 89.42 # Row buffer hit rate, read and write combined +system.mem_ctrl_0.actEnergy 3281040 # Energy for activate commands per rank (pJ) +system.mem_ctrl_0.preEnergy 1790250 # Energy for precharge commands per rank (pJ) +system.mem_ctrl_0.readEnergy 40294800 # Energy for read commands per rank (pJ) +system.mem_ctrl_0.writeEnergy 38880 # Energy for write commands per rank (pJ) +system.mem_ctrl_0.refreshEnergy 29496480 # Energy for refresh commands per rank (pJ) +system.mem_ctrl_0.actBackEnergy 248297130 # Energy for active background per rank (pJ) +system.mem_ctrl_0.preBackEnergy 53313000 # Energy for precharge background per rank (pJ) +system.mem_ctrl_0.totalEnergy 376511580 # Total energy per rank (pJ) +system.mem_ctrl_0.averagePower 833.243697 # Core power per rank (mW) +system.mem_ctrl_0.memoryStateTime::IDLE 86206500 # Time in different power states +system.mem_ctrl_0.memoryStateTime::REF 15080000 # Time in different power states system.mem_ctrl_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrl_0.memoryStateTime::ACT 342689500 # Time in different power states +system.mem_ctrl_0.memoryStateTime::ACT 350589750 # Time in different power states system.mem_ctrl_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrl_1.actEnergy 3152520 # Energy for activate commands per rank (pJ) -system.mem_ctrl_1.preEnergy 1720125 # Energy for precharge commands per rank (pJ) -system.mem_ctrl_1.readEnergy 23314200 # Energy for read commands per rank (pJ) -system.mem_ctrl_1.writeEnergy 648000 # Energy for write commands per rank (pJ) -system.mem_ctrl_1.refreshEnergy 28987920 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_1.actBackEnergy 267116535 # Energy for active background per rank (pJ) -system.mem_ctrl_1.preBackEnergy 32133000 # Energy for precharge background per rank (pJ) -system.mem_ctrl_1.totalEnergy 357072300 # Total energy per rank (pJ) -system.mem_ctrl_1.averagePower 804.078804 # Core power per rank (mW) -system.mem_ctrl_1.memoryStateTime::IDLE 51572750 # Time in different power states -system.mem_ctrl_1.memoryStateTime::REF 14820000 # Time in different power states +system.mem_ctrl_1.actEnergy 3129840 # Energy for activate commands per rank (pJ) +system.mem_ctrl_1.preEnergy 1707750 # Energy for precharge commands per rank (pJ) +system.mem_ctrl_1.readEnergy 23275200 # Energy for read commands per rank (pJ) +system.mem_ctrl_1.writeEnergy 583200 # Energy for write commands per rank (pJ) +system.mem_ctrl_1.refreshEnergy 29496480 # Energy for refresh commands per rank (pJ) +system.mem_ctrl_1.actBackEnergy 273625650 # Energy for active background per rank (pJ) +system.mem_ctrl_1.preBackEnergy 31095000 # Energy for precharge background per rank (pJ) +system.mem_ctrl_1.totalEnergy 362913120 # Total energy per rank (pJ) +system.mem_ctrl_1.averagePower 803.149454 # Core power per rank (mW) +system.mem_ctrl_1.memoryStateTime::IDLE 50725000 # Time in different power states +system.mem_ctrl_1.memoryStateTime::REF 15080000 # Time in different power states system.mem_ctrl_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrl_1.memoryStateTime::ACT 377923250 # Time in different power states +system.mem_ctrl_1.memoryStateTime::ACT 387261000 # Time in different power states system.mem_ctrl_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 445082000 # Cumulative time (in ticks) in various power states -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 445082000 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 454507000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 454507000 # Cumulative time (in ticks) in various power states system.cpu.apic_clk_domain.clock 16000 # Clock period in ticks -system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 445082000 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 445082000 # Cumulative time (in ticks) in various power states +system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 454507000 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 454507000 # Cumulative time (in ticks) in various power states system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 445082000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 445082 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 454507000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 454507 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 5712 # Number of instructions committed @@ -302,7 +301,7 @@ system.cpu.num_mem_refs 2025 # nu system.cpu.num_load_insts 1084 # Number of load instructions system.cpu.num_store_insts 941 # Number of store instructions system.cpu.num_idle_cycles 0.001000 # Number of idle cycles -system.cpu.num_busy_cycles 445081.999000 # Number of busy cycles +system.cpu.num_busy_cycles 454506.999000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 1306 # Number of branches fetched @@ -341,7 +340,13 @@ system.cpu.op_class::MemWrite 941 9.12% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 10314 # Class of executed instruction -system.membus.pwrStateResidencyTicks::UNDEFINED 445082000 # Cumulative time (in ticks) in various power states +system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 454507000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 8367 # Transaction distribution system.membus.trans_dist::ReadResp 8367 # Transaction distribution system.membus.trans_dist::WriteReq 941 # Transaction distribution @@ -359,20 +364,20 @@ system.membus.pkt_size::total 72591 # Cu system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) system.membus.snoop_fanout::samples 9308 # Request fanout histogram -system.membus.snoop_fanout::mean 0.782445 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.412605 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 2025 21.76% 21.76% # Request fanout histogram -system.membus.snoop_fanout::1 7283 78.24% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 9308 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 9308 # Request fanout histogram system.membus.reqLayer2.occupancy 10249000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 2.3 # Layer utilization (%) -system.membus.respLayer0.occupancy 16547500 # Layer occupancy (ticks) -system.membus.respLayer0.utilization 3.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 3433750 # Layer occupancy (ticks) +system.membus.respLayer0.occupancy 16547250 # Layer occupancy (ticks) +system.membus.respLayer0.utilization 3.6 # Layer utilization (%) +system.membus.respLayer1.occupancy 3431500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.8 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/stats.txt b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/stats.txt index 7d909cf8e..a74924642 100644 --- a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/stats.txt +++ b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000056 # Number of seconds simulated -sim_ticks 55844000 # Number of ticks simulated -final_tick 55844000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 56435000 # Number of ticks simulated +final_tick 56435000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 197644 # Simulator instruction rate (inst/s) -host_op_rate 356622 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1929610808 # Simulator tick rate (ticks/s) -host_mem_usage 652268 # Number of bytes of host memory used -host_seconds 0.03 # Real time elapsed on the host +host_inst_rate 125605 # Simulator instruction rate (inst/s) +host_op_rate 226732 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1240265940 # Simulator tick rate (ticks/s) +host_mem_usage 656384 # Number of bytes of host memory used +host_seconds 0.05 # Real time elapsed on the host sim_insts 5712 # Number of instructions simulated sim_ops 10314 # Number of ops (including micro ops) simulated system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 55844000 # Cumulative time (in ticks) in various power states +system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 56435000 # Cumulative time (in ticks) in various power states system.mem_ctrl.bytes_read::cpu.inst 14656 # Number of bytes read from this memory system.mem_ctrl.bytes_read::cpu.data 8640 # Number of bytes read from this memory system.mem_ctrl.bytes_read::total 23296 # Number of bytes read from this memory @@ -22,14 +22,14 @@ system.mem_ctrl.bytes_inst_read::total 14656 # Nu system.mem_ctrl.num_reads::cpu.inst 229 # Number of read requests responded to by this memory system.mem_ctrl.num_reads::cpu.data 135 # Number of read requests responded to by this memory system.mem_ctrl.num_reads::total 364 # Number of read requests responded to by this memory -system.mem_ctrl.bw_read::cpu.inst 262445384 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::cpu.data 154716711 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::total 417162094 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::cpu.inst 262445384 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::total 262445384 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.inst 262445384 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.data 154716711 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::total 417162094 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_read::cpu.inst 259696997 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_read::cpu.data 153096483 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_read::total 412793479 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_inst_read::cpu.inst 259696997 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_inst_read::total 259696997 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_total::cpu.inst 259696997 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_total::cpu.data 153096483 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_total::total 412793479 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrl.readReqs 364 # Number of read requests accepted system.mem_ctrl.writeReqs 0 # Number of write requests accepted system.mem_ctrl.readBursts 364 # Number of DRAM read bursts, including those serviced by the write queue @@ -76,7 +76,7 @@ system.mem_ctrl.perBankWrBursts::14 0 # Pe system.mem_ctrl.perBankWrBursts::15 0 # Per bank write bursts system.mem_ctrl.numRdRetry 0 # Number of times read queue was full causing retry system.mem_ctrl.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrl.totGap 55714000 # Total gap between requests +system.mem_ctrl.totGap 56304000 # Total gap between requests system.mem_ctrl.readPktSize::0 0 # Read request sizes (log2) system.mem_ctrl.readPktSize::1 0 # Read request sizes (log2) system.mem_ctrl.readPktSize::2 0 # Read request sizes (log2) @@ -187,78 +187,77 @@ system.mem_ctrl.wrQLenPdf::60 0 # Wh system.mem_ctrl.wrQLenPdf::61 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::62 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrl.bytesPerActivate::samples 115 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::mean 199.234783 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::gmean 135.588464 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::stdev 217.243914 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::0-127 49 42.61% 42.61% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::128-255 34 29.57% 72.17% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::256-383 16 13.91% 86.09% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::384-511 6 5.22% 91.30% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::512-639 2 1.74% 93.04% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::640-767 2 1.74% 94.78% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::768-895 2 1.74% 96.52% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::896-1023 1 0.87% 97.39% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::1024-1151 3 2.61% 100.00% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::total 115 # Bytes accessed per row activation -system.mem_ctrl.totQLat 3552250 # Total ticks spent queuing -system.mem_ctrl.totMemAccLat 10377250 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrl.bytesPerActivate::samples 117 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::mean 193.094017 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::gmean 128.926887 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::stdev 215.889898 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::0-127 57 48.72% 48.72% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::128-255 28 23.93% 72.65% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::256-383 16 13.68% 86.32% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::384-511 6 5.13% 91.45% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::512-639 2 1.71% 93.16% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::640-767 2 1.71% 94.87% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::768-895 3 2.56% 97.44% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::1024-1151 3 2.56% 100.00% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::total 117 # Bytes accessed per row activation +system.mem_ctrl.totQLat 3777750 # Total ticks spent queuing +system.mem_ctrl.totMemAccLat 10602750 # Total ticks spent from burst creation until serviced by the DRAM system.mem_ctrl.totBusLat 1820000 # Total ticks spent in databus transfers -system.mem_ctrl.avgQLat 9758.93 # Average queueing delay per DRAM burst +system.mem_ctrl.avgQLat 10378.43 # Average queueing delay per DRAM burst system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.mem_ctrl.avgMemAccLat 28508.93 # Average memory access latency per DRAM burst -system.mem_ctrl.avgRdBW 417.16 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrl.avgMemAccLat 29128.43 # Average memory access latency per DRAM burst +system.mem_ctrl.avgRdBW 412.79 # Average DRAM read bandwidth in MiByte/s system.mem_ctrl.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.mem_ctrl.avgRdBWSys 417.16 # Average system read bandwidth in MiByte/s +system.mem_ctrl.avgRdBWSys 412.79 # Average system read bandwidth in MiByte/s system.mem_ctrl.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.mem_ctrl.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrl.busUtil 3.26 # Data bus utilization in percentage -system.mem_ctrl.busUtilRead 3.26 # Data bus utilization in percentage for reads +system.mem_ctrl.busUtil 3.22 # Data bus utilization in percentage +system.mem_ctrl.busUtilRead 3.22 # Data bus utilization in percentage for reads system.mem_ctrl.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.mem_ctrl.avgRdQLen 1.00 # Average read queue length when enqueuing system.mem_ctrl.avgWrQLen 0.00 # Average write queue length when enqueuing -system.mem_ctrl.readRowHits 244 # Number of row buffer hits during reads +system.mem_ctrl.readRowHits 241 # Number of row buffer hits during reads system.mem_ctrl.writeRowHits 0 # Number of row buffer hits during writes -system.mem_ctrl.readRowHitRate 67.03 # Row buffer hit rate for reads +system.mem_ctrl.readRowHitRate 66.21 # Row buffer hit rate for reads system.mem_ctrl.writeRowHitRate nan # Row buffer hit rate for writes -system.mem_ctrl.avgGap 153060.44 # Average gap between requests -system.mem_ctrl.pageHitRate 67.03 # Row buffer hit rate, read and write combined -system.mem_ctrl_0.actEnergy 302400 # Energy for activate commands per rank (pJ) -system.mem_ctrl_0.preEnergy 165000 # Energy for precharge commands per rank (pJ) -system.mem_ctrl_0.readEnergy 1240200 # Energy for read commands per rank (pJ) +system.mem_ctrl.avgGap 154681.32 # Average gap between requests +system.mem_ctrl.pageHitRate 66.21 # Row buffer hit rate, read and write combined +system.mem_ctrl_0.actEnergy 309960 # Energy for activate commands per rank (pJ) +system.mem_ctrl_0.preEnergy 169125 # Energy for precharge commands per rank (pJ) +system.mem_ctrl_0.readEnergy 1201200 # Energy for read commands per rank (pJ) system.mem_ctrl_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.mem_ctrl_0.refreshEnergy 3559920 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_0.actBackEnergy 32401080 # Energy for active background per rank (pJ) -system.mem_ctrl_0.preBackEnergy 4436250 # Energy for precharge background per rank (pJ) -system.mem_ctrl_0.totalEnergy 42104850 # Total energy per rank (pJ) -system.mem_ctrl_0.averagePower 768.845267 # Core power per rank (mW) -system.mem_ctrl_0.memoryStateTime::IDLE 7212250 # Time in different power states +system.mem_ctrl_0.actBackEnergy 32277105 # Energy for active background per rank (pJ) +system.mem_ctrl_0.preBackEnergy 4545000 # Energy for precharge background per rank (pJ) +system.mem_ctrl_0.totalEnergy 42062310 # Total energy per rank (pJ) +system.mem_ctrl_0.averagePower 768.068476 # Core power per rank (mW) +system.mem_ctrl_0.memoryStateTime::IDLE 7392500 # Time in different power states system.mem_ctrl_0.memoryStateTime::REF 1820000 # Time in different power states system.mem_ctrl_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrl_0.memoryStateTime::ACT 45745250 # Time in different power states +system.mem_ctrl_0.memoryStateTime::ACT 45565000 # Time in different power states system.mem_ctrl_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrl_1.actEnergy 567000 # Energy for activate commands per rank (pJ) -system.mem_ctrl_1.preEnergy 309375 # Energy for precharge commands per rank (pJ) +system.mem_ctrl_1.actEnergy 574560 # Energy for activate commands per rank (pJ) +system.mem_ctrl_1.preEnergy 313500 # Energy for precharge commands per rank (pJ) system.mem_ctrl_1.readEnergy 1552200 # Energy for read commands per rank (pJ) system.mem_ctrl_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.mem_ctrl_1.refreshEnergy 3559920 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_1.actBackEnergy 36016020 # Energy for active background per rank (pJ) -system.mem_ctrl_1.preBackEnergy 1265250 # Energy for precharge background per rank (pJ) -system.mem_ctrl_1.totalEnergy 43269765 # Total energy per rank (pJ) -system.mem_ctrl_1.averagePower 790.116911 # Core power per rank (mW) -system.mem_ctrl_1.memoryStateTime::IDLE 2847000 # Time in different power states +system.mem_ctrl_1.actBackEnergy 36915480 # Energy for active background per rank (pJ) +system.mem_ctrl_1.preBackEnergy 476250 # Energy for precharge background per rank (pJ) +system.mem_ctrl_1.totalEnergy 43391910 # Total energy per rank (pJ) +system.mem_ctrl_1.averagePower 792.347310 # Core power per rank (mW) +system.mem_ctrl_1.memoryStateTime::IDLE 2122500 # Time in different power states system.mem_ctrl_1.memoryStateTime::REF 1820000 # Time in different power states system.mem_ctrl_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrl_1.memoryStateTime::ACT 51070000 # Time in different power states +system.mem_ctrl_1.memoryStateTime::ACT 52384500 # Time in different power states system.mem_ctrl_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 55844000 # Cumulative time (in ticks) in various power states -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 55844000 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 56435000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 56435000 # Cumulative time (in ticks) in various power states system.cpu.apic_clk_domain.clock 16000 # Clock period in ticks -system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 55844000 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 55844000 # Cumulative time (in ticks) in various power states +system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 56435000 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 56435000 # Cumulative time (in ticks) in various power states system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 55844000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 55844 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 56435000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 56435 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 5712 # Number of instructions committed @@ -279,7 +278,7 @@ system.cpu.num_mem_refs 2025 # nu system.cpu.num_load_insts 1084 # Number of load instructions system.cpu.num_store_insts 941 # Number of store instructions system.cpu.num_idle_cycles 0.001000 # Number of idle cycles -system.cpu.num_busy_cycles 55843.999000 # Number of busy cycles +system.cpu.num_busy_cycles 56434.999000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 1306 # Number of branches fetched @@ -318,23 +317,23 @@ system.cpu.op_class::MemWrite 941 9.12% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 10314 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 55844000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 56435000 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 81.671640 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 81.661133 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1890 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 135 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 14 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 81.671640 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.079757 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.079757 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 81.661133 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.079747 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.079747 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 135 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 12 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 123 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.131836 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 4185 # Number of tag accesses system.cpu.dcache.tags.data_accesses 4185 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 55844000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 56435000 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 1028 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1028 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 862 # number of WriteReq hits @@ -351,14 +350,14 @@ system.cpu.dcache.demand_misses::cpu.data 135 # n system.cpu.dcache.demand_misses::total 135 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 135 # number of overall misses system.cpu.dcache.overall_misses::total 135 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 6006000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 6006000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 8260000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 8260000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 14266000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 14266000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 14266000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 14266000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 6076000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 6076000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 8376000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 8376000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 14452000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 14452000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 14452000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 14452000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1084 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1084 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 941 # number of WriteReq accesses(hits+misses) @@ -375,14 +374,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.066667 system.cpu.dcache.demand_miss_rate::total 0.066667 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.066667 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.066667 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 107250 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 107250 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 104556.962025 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 104556.962025 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 105674.074074 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 105674.074074 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 105674.074074 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 105674.074074 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 108500 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 108500 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 106025.316456 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 106025.316456 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 107051.851852 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 107051.851852 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 107051.851852 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 107051.851852 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -397,14 +396,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 135 system.cpu.dcache.demand_mshr_misses::total 135 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 135 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 135 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5894000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5894000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8102000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8102000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13996000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 13996000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13996000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 13996000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5964000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5964000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8218000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8218000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14182000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 14182000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14182000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 14182000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.051661 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.051661 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.083953 # mshr miss rate for WriteReq accesses @@ -413,31 +412,31 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.066667 system.cpu.dcache.demand_mshr_miss_rate::total 0.066667 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.066667 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.066667 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 105250 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 105250 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 102556.962025 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 102556.962025 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 103674.074074 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 103674.074074 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 103674.074074 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 103674.074074 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 55844000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 106500 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 106500 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 104025.316456 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 104025.316456 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 105051.851852 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 105051.851852 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 105051.851852 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 105051.851852 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 56435000 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 58 # number of replacements -system.cpu.icache.tags.tagsinuse 91.239705 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 91.248553 # Cycle average of tags in use system.cpu.icache.tags.total_refs 7048 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 235 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 29.991489 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 91.239705 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.356405 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.356405 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 91.248553 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.356440 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.356440 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 177 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 133 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 43 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 134 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.691406 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 14801 # Number of tag accesses system.cpu.icache.tags.data_accesses 14801 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 55844000 # Cumulative time (in ticks) in various power states +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 56435000 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 7048 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 7048 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 7048 # number of demand (read+write) hits @@ -450,12 +449,12 @@ system.cpu.icache.demand_misses::cpu.inst 235 # n system.cpu.icache.demand_misses::total 235 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 235 # number of overall misses system.cpu.icache.overall_misses::total 235 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 23702000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 23702000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 23702000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 23702000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 23702000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 23702000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 24107000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 24107000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 24107000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 24107000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 24107000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 24107000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 7283 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 7283 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 7283 # number of demand (read+write) accesses @@ -468,12 +467,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.032267 system.cpu.icache.demand_miss_rate::total 0.032267 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.032267 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.032267 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 100859.574468 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 100859.574468 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 100859.574468 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 100859.574468 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 100859.574468 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 100859.574468 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 102582.978723 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 102582.978723 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 102582.978723 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 102582.978723 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 102582.978723 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 102582.978723 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -486,31 +485,31 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 235 system.cpu.icache.demand_mshr_misses::total 235 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 235 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 235 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23232000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 23232000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23232000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 23232000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23232000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 23232000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23637000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 23637000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23637000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 23637000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23637000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 23637000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.032267 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.032267 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.032267 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.032267 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.032267 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.032267 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 98859.574468 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 98859.574468 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 98859.574468 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 98859.574468 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 98859.574468 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 98859.574468 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 100582.978723 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 100582.978723 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 100582.978723 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 100582.978723 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 100582.978723 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 100582.978723 # average overall mshr miss latency system.l2bus.snoop_filter.tot_requests 428 # Total number of requests made to the snoop filter. system.l2bus.snoop_filter.hit_single_requests 59 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.l2bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.l2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.l2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.l2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.l2bus.pwrStateResidencyTicks::UNDEFINED 55844000 # Cumulative time (in ticks) in various power states +system.l2bus.pwrStateResidencyTicks::UNDEFINED 56435000 # Cumulative time (in ticks) in various power states system.l2bus.trans_dist::ReadResp 291 # Transaction distribution system.l2bus.trans_dist::CleanEvict 58 # Transaction distribution system.l2bus.trans_dist::ReadExReq 79 # Transaction distribution @@ -538,28 +537,28 @@ system.l2bus.snoop_fanout::total 370 # Re system.l2bus.reqLayer0.occupancy 428000 # Layer occupancy (ticks) system.l2bus.reqLayer0.utilization 0.8 # Layer utilization (%) system.l2bus.respLayer0.occupancy 705000 # Layer occupancy (ticks) -system.l2bus.respLayer0.utilization 1.3 # Layer utilization (%) +system.l2bus.respLayer0.utilization 1.2 # Layer utilization (%) system.l2bus.respLayer1.occupancy 405000 # Layer occupancy (ticks) system.l2bus.respLayer1.utilization 0.7 # Layer utilization (%) -system.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 55844000 # Cumulative time (in ticks) in various power states +system.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 56435000 # Cumulative time (in ticks) in various power states system.l2cache.tags.replacements 0 # number of replacements -system.l2cache.tags.tagsinuse 135.848259 # Cycle average of tags in use +system.l2cache.tags.tagsinuse 188.623694 # Cycle average of tags in use system.l2cache.tags.total_refs 64 # Total number of references to valid blocks. -system.l2cache.tags.sampled_refs 285 # Sample count of references to valid blocks. -system.l2cache.tags.avg_refs 0.224561 # Average number of references to valid blocks. +system.l2cache.tags.sampled_refs 364 # Sample count of references to valid blocks. +system.l2cache.tags.avg_refs 0.175824 # Average number of references to valid blocks. system.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2cache.tags.occ_blocks::cpu.inst 106.898398 # Average occupied blocks per requestor -system.l2cache.tags.occ_blocks::cpu.data 28.949861 # Average occupied blocks per requestor -system.l2cache.tags.occ_percent::cpu.inst 0.026098 # Average percentage of cache occupancy -system.l2cache.tags.occ_percent::cpu.data 0.007068 # Average percentage of cache occupancy -system.l2cache.tags.occ_percent::total 0.033166 # Average percentage of cache occupancy -system.l2cache.tags.occ_task_id_blocks::1024 285 # Occupied blocks per task id -system.l2cache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id -system.l2cache.tags.age_task_id_blocks_1024::1 231 # Occupied blocks per task id -system.l2cache.tags.occ_task_id_percent::1024 0.069580 # Percentage of cache occupancy per task id +system.l2cache.tags.occ_blocks::cpu.inst 106.912326 # Average occupied blocks per requestor +system.l2cache.tags.occ_blocks::cpu.data 81.711368 # Average occupied blocks per requestor +system.l2cache.tags.occ_percent::cpu.inst 0.026102 # Average percentage of cache occupancy +system.l2cache.tags.occ_percent::cpu.data 0.019949 # Average percentage of cache occupancy +system.l2cache.tags.occ_percent::total 0.046051 # Average percentage of cache occupancy +system.l2cache.tags.occ_task_id_blocks::1024 364 # Occupied blocks per task id +system.l2cache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id +system.l2cache.tags.age_task_id_blocks_1024::1 309 # Occupied blocks per task id +system.l2cache.tags.occ_task_id_percent::1024 0.088867 # Percentage of cache occupancy per task id system.l2cache.tags.tag_accesses 3788 # Number of tag accesses system.l2cache.tags.data_accesses 3788 # Number of data accesses -system.l2cache.pwrStateResidencyTicks::UNDEFINED 55844000 # Cumulative time (in ticks) in various power states +system.l2cache.pwrStateResidencyTicks::UNDEFINED 56435000 # Cumulative time (in ticks) in various power states system.l2cache.ReadSharedReq_hits::cpu.inst 6 # number of ReadSharedReq hits system.l2cache.ReadSharedReq_hits::total 6 # number of ReadSharedReq hits system.l2cache.demand_hits::cpu.inst 6 # number of demand (read+write) hits @@ -577,17 +576,17 @@ system.l2cache.demand_misses::total 364 # nu system.l2cache.overall_misses::cpu.inst 229 # number of overall misses system.l2cache.overall_misses::cpu.data 135 # number of overall misses system.l2cache.overall_misses::total 364 # number of overall misses -system.l2cache.ReadExReq_miss_latency::cpu.data 7865000 # number of ReadExReq miss cycles -system.l2cache.ReadExReq_miss_latency::total 7865000 # number of ReadExReq miss cycles -system.l2cache.ReadSharedReq_miss_latency::cpu.inst 22399000 # number of ReadSharedReq miss cycles -system.l2cache.ReadSharedReq_miss_latency::cpu.data 5726000 # number of ReadSharedReq miss cycles -system.l2cache.ReadSharedReq_miss_latency::total 28125000 # number of ReadSharedReq miss cycles -system.l2cache.demand_miss_latency::cpu.inst 22399000 # number of demand (read+write) miss cycles -system.l2cache.demand_miss_latency::cpu.data 13591000 # number of demand (read+write) miss cycles -system.l2cache.demand_miss_latency::total 35990000 # number of demand (read+write) miss cycles -system.l2cache.overall_miss_latency::cpu.inst 22399000 # number of overall miss cycles -system.l2cache.overall_miss_latency::cpu.data 13591000 # number of overall miss cycles -system.l2cache.overall_miss_latency::total 35990000 # number of overall miss cycles +system.l2cache.ReadExReq_miss_latency::cpu.data 7981000 # number of ReadExReq miss cycles +system.l2cache.ReadExReq_miss_latency::total 7981000 # number of ReadExReq miss cycles +system.l2cache.ReadSharedReq_miss_latency::cpu.inst 22804000 # number of ReadSharedReq miss cycles +system.l2cache.ReadSharedReq_miss_latency::cpu.data 5796000 # number of ReadSharedReq miss cycles +system.l2cache.ReadSharedReq_miss_latency::total 28600000 # number of ReadSharedReq miss cycles +system.l2cache.demand_miss_latency::cpu.inst 22804000 # number of demand (read+write) miss cycles +system.l2cache.demand_miss_latency::cpu.data 13777000 # number of demand (read+write) miss cycles +system.l2cache.demand_miss_latency::total 36581000 # number of demand (read+write) miss cycles +system.l2cache.overall_miss_latency::cpu.inst 22804000 # number of overall miss cycles +system.l2cache.overall_miss_latency::cpu.data 13777000 # number of overall miss cycles +system.l2cache.overall_miss_latency::total 36581000 # number of overall miss cycles system.l2cache.ReadExReq_accesses::cpu.data 79 # number of ReadExReq accesses(hits+misses) system.l2cache.ReadExReq_accesses::total 79 # number of ReadExReq accesses(hits+misses) system.l2cache.ReadSharedReq_accesses::cpu.inst 235 # number of ReadSharedReq accesses(hits+misses) @@ -610,17 +609,17 @@ system.l2cache.demand_miss_rate::total 0.983784 # mi system.l2cache.overall_miss_rate::cpu.inst 0.974468 # miss rate for overall accesses system.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.l2cache.overall_miss_rate::total 0.983784 # miss rate for overall accesses -system.l2cache.ReadExReq_avg_miss_latency::cpu.data 99556.962025 # average ReadExReq miss latency -system.l2cache.ReadExReq_avg_miss_latency::total 99556.962025 # average ReadExReq miss latency -system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 97812.227074 # average ReadSharedReq miss latency -system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 102250 # average ReadSharedReq miss latency -system.l2cache.ReadSharedReq_avg_miss_latency::total 98684.210526 # average ReadSharedReq miss latency -system.l2cache.demand_avg_miss_latency::cpu.inst 97812.227074 # average overall miss latency -system.l2cache.demand_avg_miss_latency::cpu.data 100674.074074 # average overall miss latency -system.l2cache.demand_avg_miss_latency::total 98873.626374 # average overall miss latency -system.l2cache.overall_avg_miss_latency::cpu.inst 97812.227074 # average overall miss latency -system.l2cache.overall_avg_miss_latency::cpu.data 100674.074074 # average overall miss latency -system.l2cache.overall_avg_miss_latency::total 98873.626374 # average overall miss latency +system.l2cache.ReadExReq_avg_miss_latency::cpu.data 101025.316456 # average ReadExReq miss latency +system.l2cache.ReadExReq_avg_miss_latency::total 101025.316456 # average ReadExReq miss latency +system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 99580.786026 # average ReadSharedReq miss latency +system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 103500 # average ReadSharedReq miss latency +system.l2cache.ReadSharedReq_avg_miss_latency::total 100350.877193 # average ReadSharedReq miss latency +system.l2cache.demand_avg_miss_latency::cpu.inst 99580.786026 # average overall miss latency +system.l2cache.demand_avg_miss_latency::cpu.data 102051.851852 # average overall miss latency +system.l2cache.demand_avg_miss_latency::total 100497.252747 # average overall miss latency +system.l2cache.overall_avg_miss_latency::cpu.inst 99580.786026 # average overall miss latency +system.l2cache.overall_avg_miss_latency::cpu.data 102051.851852 # average overall miss latency +system.l2cache.overall_avg_miss_latency::total 100497.252747 # average overall miss latency system.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -638,17 +637,17 @@ system.l2cache.demand_mshr_misses::total 364 # nu system.l2cache.overall_mshr_misses::cpu.inst 229 # number of overall MSHR misses system.l2cache.overall_mshr_misses::cpu.data 135 # number of overall MSHR misses system.l2cache.overall_mshr_misses::total 364 # number of overall MSHR misses -system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6285000 # number of ReadExReq MSHR miss cycles -system.l2cache.ReadExReq_mshr_miss_latency::total 6285000 # number of ReadExReq MSHR miss cycles -system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 17819000 # number of ReadSharedReq MSHR miss cycles -system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4606000 # number of ReadSharedReq MSHR miss cycles -system.l2cache.ReadSharedReq_mshr_miss_latency::total 22425000 # number of ReadSharedReq MSHR miss cycles -system.l2cache.demand_mshr_miss_latency::cpu.inst 17819000 # number of demand (read+write) MSHR miss cycles -system.l2cache.demand_mshr_miss_latency::cpu.data 10891000 # number of demand (read+write) MSHR miss cycles -system.l2cache.demand_mshr_miss_latency::total 28710000 # number of demand (read+write) MSHR miss cycles -system.l2cache.overall_mshr_miss_latency::cpu.inst 17819000 # number of overall MSHR miss cycles -system.l2cache.overall_mshr_miss_latency::cpu.data 10891000 # number of overall MSHR miss cycles -system.l2cache.overall_mshr_miss_latency::total 28710000 # number of overall MSHR miss cycles +system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6401000 # number of ReadExReq MSHR miss cycles +system.l2cache.ReadExReq_mshr_miss_latency::total 6401000 # number of ReadExReq MSHR miss cycles +system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 18224000 # number of ReadSharedReq MSHR miss cycles +system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4676000 # number of ReadSharedReq MSHR miss cycles +system.l2cache.ReadSharedReq_mshr_miss_latency::total 22900000 # number of ReadSharedReq MSHR miss cycles +system.l2cache.demand_mshr_miss_latency::cpu.inst 18224000 # number of demand (read+write) MSHR miss cycles +system.l2cache.demand_mshr_miss_latency::cpu.data 11077000 # number of demand (read+write) MSHR miss cycles +system.l2cache.demand_mshr_miss_latency::total 29301000 # number of demand (read+write) MSHR miss cycles +system.l2cache.overall_mshr_miss_latency::cpu.inst 18224000 # number of overall MSHR miss cycles +system.l2cache.overall_mshr_miss_latency::cpu.data 11077000 # number of overall MSHR miss cycles +system.l2cache.overall_mshr_miss_latency::total 29301000 # number of overall MSHR miss cycles system.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.inst 0.974468 # mshr miss rate for ReadSharedReq accesses @@ -660,18 +659,24 @@ system.l2cache.demand_mshr_miss_rate::total 0.983784 # system.l2cache.overall_mshr_miss_rate::cpu.inst 0.974468 # mshr miss rate for overall accesses system.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.l2cache.overall_mshr_miss_rate::total 0.983784 # mshr miss rate for overall accesses -system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 79556.962025 # average ReadExReq mshr miss latency -system.l2cache.ReadExReq_avg_mshr_miss_latency::total 79556.962025 # average ReadExReq mshr miss latency -system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 77812.227074 # average ReadSharedReq mshr miss latency -system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 82250 # average ReadSharedReq mshr miss latency -system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 78684.210526 # average ReadSharedReq mshr miss latency -system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 77812.227074 # average overall mshr miss latency -system.l2cache.demand_avg_mshr_miss_latency::cpu.data 80674.074074 # average overall mshr miss latency -system.l2cache.demand_avg_mshr_miss_latency::total 78873.626374 # average overall mshr miss latency -system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 77812.227074 # average overall mshr miss latency -system.l2cache.overall_avg_mshr_miss_latency::cpu.data 80674.074074 # average overall mshr miss latency -system.l2cache.overall_avg_mshr_miss_latency::total 78873.626374 # average overall mshr miss latency -system.membus.pwrStateResidencyTicks::UNDEFINED 55844000 # Cumulative time (in ticks) in various power states +system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 81025.316456 # average ReadExReq mshr miss latency +system.l2cache.ReadExReq_avg_mshr_miss_latency::total 81025.316456 # average ReadExReq mshr miss latency +system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 79580.786026 # average ReadSharedReq mshr miss latency +system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 83500 # average ReadSharedReq mshr miss latency +system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 80350.877193 # average ReadSharedReq mshr miss latency +system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 79580.786026 # average overall mshr miss latency +system.l2cache.demand_avg_mshr_miss_latency::cpu.data 82051.851852 # average overall mshr miss latency +system.l2cache.demand_avg_mshr_miss_latency::total 80497.252747 # average overall mshr miss latency +system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 79580.786026 # average overall mshr miss latency +system.l2cache.overall_avg_mshr_miss_latency::cpu.data 82051.851852 # average overall mshr miss latency +system.l2cache.overall_avg_mshr_miss_latency::total 80497.252747 # average overall mshr miss latency +system.membus.snoop_filter.tot_requests 364 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 56435000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 285 # Transaction distribution system.membus.trans_dist::ReadExReq 79 # Transaction distribution system.membus.trans_dist::ReadExResp 79 # Transaction distribution @@ -695,8 +700,8 @@ system.membus.snoop_fanout::min_value 0 # Re system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 364 # Request fanout histogram system.membus.reqLayer2.occupancy 364000 # Layer occupancy (ticks) -system.membus.reqLayer2.utilization 0.7 # Layer utilization (%) -system.membus.respLayer0.occupancy 1952750 # Layer occupancy (ticks) +system.membus.reqLayer2.utilization 0.6 # Layer utilization (%) +system.membus.respLayer0.occupancy 1954250 # Layer occupancy (ticks) system.membus.respLayer0.utilization 3.5 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt b/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt index 5d52b3854..96e0c0f43 100644 --- a/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.054141 # Nu sim_ticks 54141000500 # Number of ticks simulated final_tick 54141000500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1047421 # Simulator instruction rate (inst/s) -host_op_rate 1052637 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 625903844 # Simulator tick rate (ticks/s) -host_mem_usage 389680 # Number of bytes of host memory used -host_seconds 86.50 # Real time elapsed on the host +host_inst_rate 1173010 # Simulator instruction rate (inst/s) +host_op_rate 1178851 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 700951539 # Simulator tick rate (ticks/s) +host_mem_usage 393548 # Number of bytes of host memory used +host_seconds 77.24 # Real time elapsed on the host sim_insts 90602408 # Number of instructions simulated sim_ops 91053639 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -220,6 +220,12 @@ system.cpu.op_class::MemWrite 4744844 5.21% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 91054081 # Class of executed instruction +system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.pwrStateResidencyTicks::UNDEFINED 54141000500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 130287906 # Transaction distribution system.membus.trans_dist::ReadResp 130291793 # Transaction distribution @@ -239,14 +245,14 @@ system.membus.pkt_size::total 540247820 # Cu system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) system.membus.snoop_fanout::samples 135031171 # Request fanout histogram -system.membus.snoop_fanout::mean 0.798562 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.401074 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 27200400 20.14% 20.14% # Request fanout histogram -system.membus.snoop_fanout::1 107830771 79.86% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 135031171 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 135031171 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/stats.txt index 6dcb559f6..699231bfd 100644 --- a/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/stats.txt +++ b/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.147149 # Number of seconds simulated -sim_ticks 147148719500 # Number of ticks simulated -final_tick 147148719500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.147164 # Number of seconds simulated +sim_ticks 147164058500 # Number of ticks simulated +final_tick 147164058500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 664401 # Simulator instruction rate (inst/s) -host_op_rate 667702 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1079367051 # Simulator tick rate (ticks/s) -host_mem_usage 398392 # Number of bytes of host memory used -host_seconds 136.33 # Real time elapsed on the host +host_inst_rate 748296 # Simulator instruction rate (inst/s) +host_op_rate 752015 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1215788381 # Simulator tick rate (ticks/s) +host_mem_usage 404056 # Number of bytes of host memory used +host_seconds 121.04 # Real time elapsed on the host sim_insts 90576862 # Number of instructions simulated sim_ops 91026991 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 147148719500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 147164058500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 36928 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 944832 # Number of bytes read from this memory system.physmem.bytes_read::total 981760 # Number of bytes read from this memory @@ -22,17 +22,17 @@ system.physmem.bytes_inst_read::total 36928 # Nu system.physmem.num_reads::cpu.inst 577 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 14763 # Number of read requests responded to by this memory system.physmem.num_reads::total 15340 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 250957 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 6420933 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 6671890 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 250957 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 250957 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 250957 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 6420933 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6671890 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 147148719500 # Cumulative time (in ticks) in various power states +system.physmem.bw_read::cpu.inst 250931 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 6420263 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 6671194 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 250931 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 250931 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 250931 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 6420263 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6671194 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 147164058500 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 147148719500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 147164058500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -62,7 +62,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 147148719500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 147164058500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -92,7 +92,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 147148719500 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 147164058500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -122,7 +122,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 147148719500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 147164058500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -153,8 +153,8 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 442 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 147148719500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 294297439 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 147164058500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 294328117 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 90576862 # Number of instructions committed @@ -175,7 +175,7 @@ system.cpu.num_mem_refs 27220755 # nu system.cpu.num_load_insts 22475911 # Number of load instructions system.cpu.num_store_insts 4744844 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 294297438.998000 # Number of busy cycles +system.cpu.num_busy_cycles 294328116.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 18732305 # Number of branches fetched @@ -214,25 +214,25 @@ system.cpu.op_class::MemWrite 4744844 5.21% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 91054081 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 147148719500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 147164058500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 942702 # number of replacements -system.cpu.dcache.tags.tagsinuse 3565.478025 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 3565.461526 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 26253601 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 946798 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 27.728830 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 54453325500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3565.478025 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.870478 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.870478 # Average percentage of cache occupancy +system.cpu.dcache.tags.warmup_cycle 54459450500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 3565.461526 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.870474 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.870474 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 120 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 1357 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 2563 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 118 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 1358 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2564 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 56 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 55347598 # Number of tag accesses system.cpu.dcache.tags.data_accesses 55347598 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 147148719500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 147164058500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 21556948 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 21556948 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 4688372 # number of WriteReq hits @@ -257,14 +257,14 @@ system.cpu.dcache.demand_misses::cpu.data 946796 # n system.cpu.dcache.demand_misses::total 946796 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 946799 # number of overall misses system.cpu.dcache.overall_misses::total 946799 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11713009000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11713009000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 1319019500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 1319019500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 13032028500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 13032028500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 13032028500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 13032028500 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11713223000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11713223000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 1333567500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 1333567500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 13046790500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 13046790500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 13046790500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 13046790500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 22457135 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 22457135 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) @@ -289,14 +289,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.034819 system.cpu.dcache.demand_miss_rate::total 0.034819 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.034818 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.034818 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13011.750892 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13011.750892 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28299.673883 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 28299.673883 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 13764.346808 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 13764.346808 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 13764.303194 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 13764.303194 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13011.988620 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13011.988620 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28611.802442 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 28611.802442 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 13779.938339 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 13779.938339 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 13779.894677 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 13779.894677 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -321,16 +321,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 946795 system.cpu.dcache.demand_mshr_misses::total 946795 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 946798 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 946798 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10812776000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 10812776000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1272410500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1272410500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 134000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 134000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12085186500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 12085186500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12085320500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 12085320500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10812989000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 10812989000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1286958500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1286958500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 136000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 136000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12099947500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 12099947500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12100083500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 12100083500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.040085 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040085 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009844 # mshr miss rate for WriteReq accesses @@ -341,26 +341,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.034819 system.cpu.dcache.demand_mshr_miss_rate::total 0.034819 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034818 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.034818 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12011.713135 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12011.713135 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27299.673883 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27299.673883 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 44666.666667 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 44666.666667 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12764.311704 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 12764.311704 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12764.412789 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 12764.412789 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 147148719500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12011.949753 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12011.949753 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27611.802442 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27611.802442 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 45333.333333 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 45333.333333 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12779.902196 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 12779.902196 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12780.005344 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 12780.005344 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 147164058500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 2 # number of replacements -system.cpu.icache.tags.tagsinuse 510.111710 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 510.110453 # Cycle average of tags in use system.cpu.icache.tags.total_refs 107830173 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 599 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 180016.983306 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.111710 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.249078 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.249078 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 510.110453 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.249077 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.249077 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 597 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 35 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id @@ -369,7 +369,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 552 system.cpu.icache.tags.occ_task_id_percent::1024 0.291504 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 215662143 # Number of tag accesses system.cpu.icache.tags.data_accesses 215662143 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 147148719500 # Cumulative time (in ticks) in various power states +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 147164058500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 107830173 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 107830173 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 107830173 # number of demand (read+write) hits @@ -382,12 +382,12 @@ system.cpu.icache.demand_misses::cpu.inst 599 # n system.cpu.icache.demand_misses::total 599 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 599 # number of overall misses system.cpu.icache.overall_misses::total 599 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 36093000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 36093000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 36093000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 36093000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 36093000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 36093000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 36670000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 36670000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 36670000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 36670000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 36670000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 36670000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 107830772 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 107830772 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 107830772 # number of demand (read+write) accesses @@ -400,12 +400,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000006 system.cpu.icache.demand_miss_rate::total 0.000006 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000006 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000006 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 60255.425710 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 60255.425710 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 60255.425710 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 60255.425710 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 60255.425710 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 60255.425710 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61218.697830 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 61218.697830 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 61218.697830 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 61218.697830 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 61218.697830 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 61218.697830 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -420,48 +420,46 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 599 system.cpu.icache.demand_mshr_misses::total 599 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 599 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 599 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 35494000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 35494000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 35494000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 35494000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 35494000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 35494000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 36071000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 36071000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 36071000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 36071000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 36071000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 36071000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000006 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000006 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000006 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000006 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000006 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000006 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 59255.425710 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 59255.425710 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 59255.425710 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 59255.425710 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 59255.425710 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 59255.425710 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 147148719500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60218.697830 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60218.697830 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60218.697830 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 60218.697830 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60218.697830 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 60218.697830 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 147164058500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 9564.658425 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1827433 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 15323 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 119.260784 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 10666.571104 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1874647 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 15340 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 122.206454 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 8876.269803 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 494.164592 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 194.224030 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.270882 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 494.163402 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 10172.407702 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.015081 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.005927 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.291890 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 15323 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_percent::cpu.data 0.310437 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.325518 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 15340 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 4 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 100 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1473 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13704 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.467621 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 15181828 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 15181828 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 147148719500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 59 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 15229 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.468140 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 15135236 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 15135236 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 147164058500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 942334 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 942334 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 1 # number of WritebackClean hits @@ -490,18 +488,18 @@ system.cpu.l2cache.demand_misses::total 15340 # nu system.cpu.l2cache.overall_misses::cpu.inst 577 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 14763 # number of overall misses system.cpu.l2cache.overall_misses::total 15340 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 865856500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 865856500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 34343500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 34343500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 12794500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 12794500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 34343500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 878651000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 912994500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 34343500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 878651000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 912994500 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 880404500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 880404500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 34920500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 34920500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 13009500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 13009500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 34920500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 893414000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 928334500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 34920500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 893414000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 928334500 # number of overall miss cycles system.cpu.l2cache.WritebackDirty_accesses::writebacks 942334 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackDirty_accesses::total 942334 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::writebacks 1 # number of WritebackClean accesses(hits+misses) @@ -530,18 +528,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.016192 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.963272 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.015593 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.016192 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59517.218862 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59517.218862 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59520.797227 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59520.797227 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59509.302326 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59509.302326 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59520.797227 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59517.103570 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 59517.242503 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59520.797227 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59517.103570 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 59517.242503 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60517.218862 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60517.218862 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60520.797227 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60520.797227 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60509.302326 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60509.302326 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60520.797227 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60517.103570 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 60517.242503 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60520.797227 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60517.103570 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 60517.242503 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -560,18 +558,18 @@ system.cpu.l2cache.demand_mshr_misses::total 15340 system.cpu.l2cache.overall_mshr_misses::cpu.inst 577 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 14763 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 15340 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 720376500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 720376500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 28573500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 28573500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 10644500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 10644500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 28573500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 731021000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 759594500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 28573500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 731021000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 759594500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 734924500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 734924500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 29150500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 29150500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 10859500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 10859500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 29150500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 745784000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 774934500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 29150500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 745784000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 774934500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.312129 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.312129 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.963272 # mshr miss rate for ReadCleanReq accesses @@ -584,25 +582,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.016192 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.963272 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015593 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.016192 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49517.218862 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49517.218862 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49520.797227 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49520.797227 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49509.302326 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49509.302326 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49520.797227 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49517.103570 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49517.242503 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49520.797227 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49517.103570 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49517.242503 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50517.218862 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50517.218862 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50520.797227 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50520.797227 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50509.302326 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50509.302326 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50520.797227 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50517.103570 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50517.242503 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50520.797227 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50517.103570 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50517.242503 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 1890101 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 942715 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 114 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 147148719500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 147164058500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 900788 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 942334 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 2 # Transaction distribution @@ -636,7 +634,13 @@ system.cpu.toL2Bus.respLayer0.occupancy 898500 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 1420197000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 147148719500 # Cumulative time (in ticks) in various power states +system.membus.snoop_filter.tot_requests 15340 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 147164058500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 792 # Transaction distribution system.membus.trans_dist::ReadExReq 14548 # Transaction distribution system.membus.trans_dist::ReadExResp 14548 # Transaction distribution diff --git a/tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt b/tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt index 7bb62e016..878a32205 100644 --- a/tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.122216 # Nu sim_ticks 122215823500 # Number of ticks simulated final_tick 122215823500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2052281 # Simulator instruction rate (inst/s) -host_op_rate 2052366 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1028692544 # Simulator tick rate (ticks/s) -host_mem_usage 371448 # Number of bytes of host memory used -host_seconds 118.81 # Real time elapsed on the host +host_inst_rate 2878876 # Simulator instruction rate (inst/s) +host_op_rate 2878995 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1443018123 # Simulator tick rate (ticks/s) +host_mem_usage 374552 # Number of bytes of host memory used +host_seconds 84.69 # Real time elapsed on the host sim_insts 243825150 # Number of instructions simulated sim_ops 243835265 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -100,6 +100,12 @@ system.cpu.op_class::MemWrite 22907920 9.37% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 244431613 # Class of executed instruction +system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.pwrStateResidencyTicks::UNDEFINED 122215823500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 326641931 # Transaction distribution system.membus.trans_dist::ReadResp 326641931 # Transaction distribution @@ -116,14 +122,14 @@ system.membus.pkt_size::total 1397997177 # Cu system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) system.membus.snoop_fanout::samples 349547768 # Request fanout histogram -system.membus.snoop_fanout::mean 0.699251 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.458584 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 105126270 30.07% 30.07% # Request fanout histogram -system.membus.snoop_fanout::1 244421498 69.93% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 349547768 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 349547768 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt b/tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt index 20d186f41..f30c65448 100644 --- a/tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.168950 # Nu sim_ticks 168950040000 # Number of ticks simulated final_tick 168950040000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 780506 # Simulator instruction rate (inst/s) -host_op_rate 1374345 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 834658386 # Simulator tick rate (ticks/s) -host_mem_usage 397512 # Number of bytes of host memory used -host_seconds 202.42 # Real time elapsed on the host +host_inst_rate 1086071 # Simulator instruction rate (inst/s) +host_op_rate 1912397 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1161424459 # Simulator tick rate (ticks/s) +host_mem_usage 401896 # Number of bytes of host memory used +host_seconds 145.47 # Real time elapsed on the host sim_insts 157988548 # Number of instructions simulated sim_ops 278192465 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -104,6 +104,12 @@ system.cpu.op_class::MemWrite 31439752 11.30% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 278192465 # Class of executed instruction +system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.pwrStateResidencyTicks::UNDEFINED 168950040000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 308475611 # Transaction distribution system.membus.trans_dist::ReadResp 308475611 # Transaction distribution @@ -122,14 +128,14 @@ system.membus.pkt_size::total 2701988442 # Cu system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) system.membus.snoop_fanout::samples 339915363 # Request fanout histogram -system.membus.snoop_fanout::mean 0.640442 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.479871 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 122219199 35.96% 35.96% # Request fanout histogram -system.membus.snoop_fanout::1 217696164 64.04% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 339915363 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 339915363 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/30.eon/ref/alpha/tru64/simple-atomic/stats.txt b/tests/quick/se/30.eon/ref/alpha/tru64/simple-atomic/stats.txt index 5fb1fafd0..cd3aa922b 100644 --- a/tests/quick/se/30.eon/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/quick/se/30.eon/ref/alpha/tru64/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.199332 # Nu sim_ticks 199332411500 # Number of ticks simulated final_tick 199332411500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1645472 # Simulator instruction rate (inst/s) -host_op_rate 1645472 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 822736272 # Simulator tick rate (ticks/s) -host_mem_usage 245476 # Number of bytes of host memory used -host_seconds 242.28 # Real time elapsed on the host +host_inst_rate 1644868 # Simulator instruction rate (inst/s) +host_op_rate 1644867 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 822434164 # Simulator tick rate (ticks/s) +host_mem_usage 249080 # Number of bytes of host memory used +host_seconds 242.37 # Real time elapsed on the host sim_insts 398664595 # Number of instructions simulated sim_ops 398664595 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -130,6 +130,12 @@ system.cpu.op_class::MemWrite 73520764 18.44% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 398664651 # Class of executed instruction +system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.pwrStateResidencyTicks::UNDEFINED 199332411500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 493419140 # Transaction distribution system.membus.trans_dist::ReadResp 493419140 # Transaction distribution @@ -144,14 +150,14 @@ system.membus.pkt_size::total 2749464673 # Cu system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) system.membus.snoop_fanout::samples 566939869 # Request fanout histogram -system.membus.snoop_fanout::mean 0.703187 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.456853 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 168275218 29.68% 29.68% # Request fanout histogram -system.membus.snoop_fanout::1 398664651 70.32% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 566939869 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 566939869 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt index 8c3fa74c7..10d3d1f6f 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt @@ -1,79 +1,79 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000125 # Number of seconds simulated -sim_ticks 124523000 # Number of ticks simulated -final_tick 124523000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000124 # Number of seconds simulated +sim_ticks 123936000 # Number of ticks simulated +final_tick 123936000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 143029 # Simulator instruction rate (inst/s) -host_op_rate 143029 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 15434351 # Simulator tick rate (ticks/s) -host_mem_usage 263456 # Number of bytes of host memory used -host_seconds 8.07 # Real time elapsed on the host -sim_insts 1153943 # Number of instructions simulated -sim_ops 1153943 # Number of ops (including micro ops) simulated +host_inst_rate 188054 # Simulator instruction rate (inst/s) +host_op_rate 188053 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 20091950 # Simulator tick rate (ticks/s) +host_mem_usage 268856 # Number of bytes of host memory used +host_seconds 6.17 # Real time elapsed on the host +sim_insts 1159992 # Number of instructions simulated +sim_ops 1159992 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 124523000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu0.inst 24000 # Number of bytes read from this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 123936000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu0.inst 24064 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.data 10880 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 5888 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 1408 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 5696 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 1344 # Number of bytes read from this memory system.physmem.bytes_read::cpu2.inst 896 # Number of bytes read from this memory system.physmem.bytes_read::cpu2.data 960 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.inst 704 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.inst 640 # Number of bytes read from this memory system.physmem.bytes_read::cpu3.data 896 # Number of bytes read from this memory -system.physmem.bytes_read::total 45632 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 24000 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 5888 # Number of instructions bytes read from this memory +system.physmem.bytes_read::total 45376 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 24064 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 5696 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::cpu2.inst 896 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu3.inst 704 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 31488 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu0.inst 375 # Number of read requests responded to by this memory +system.physmem.bytes_inst_read::cpu3.inst 640 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 31296 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu0.inst 376 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.data 170 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 92 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 22 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 89 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 21 # Number of read requests responded to by this memory system.physmem.num_reads::cpu2.inst 14 # Number of read requests responded to by this memory system.physmem.num_reads::cpu2.data 15 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.inst 11 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.inst 10 # Number of read requests responded to by this memory system.physmem.num_reads::cpu3.data 14 # Number of read requests responded to by this memory -system.physmem.num_reads::total 713 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu0.inst 192735479 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 87373417 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 47284437 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 11307148 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 7195458 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 7709419 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.inst 5653574 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.data 7195458 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 366454390 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 192735479 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 47284437 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 7195458 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu3.inst 5653574 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 252868948 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 192735479 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 87373417 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 47284437 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 11307148 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 7195458 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 7709419 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.inst 5653574 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.data 7195458 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 366454390 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 713 # Number of read requests accepted +system.physmem.num_reads::total 709 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu0.inst 194164730 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 87787245 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 45959205 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 10844307 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 7229538 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 7745933 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.inst 5163956 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.data 7229538 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 366124451 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 194164730 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 45959205 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 7229538 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu3.inst 5163956 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 252517428 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 194164730 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 87787245 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 45959205 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 10844307 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 7229538 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 7745933 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.inst 5163956 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.data 7229538 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 366124451 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 709 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 713 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 709 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 45632 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 45376 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 45632 # Total read bytes from the system interface side +system.physmem.bytesReadSys 45376 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 120 # Per bank write bursts -system.physmem.perBankRdBursts::1 45 # Per bank write bursts +system.physmem.perBankRdBursts::1 44 # Per bank write bursts system.physmem.perBankRdBursts::2 31 # Per bank write bursts system.physmem.perBankRdBursts::3 62 # Per bank write bursts system.physmem.perBankRdBursts::4 69 # Per bank write bursts @@ -84,8 +84,8 @@ system.physmem.perBankRdBursts::8 7 # Pe system.physmem.perBankRdBursts::9 31 # Per bank write bursts system.physmem.perBankRdBursts::10 23 # Per bank write bursts system.physmem.perBankRdBursts::11 13 # Per bank write bursts -system.physmem.perBankRdBursts::12 70 # Per bank write bursts -system.physmem.perBankRdBursts::13 47 # Per bank write bursts +system.physmem.perBankRdBursts::12 69 # Per bank write bursts +system.physmem.perBankRdBursts::13 45 # Per bank write bursts system.physmem.perBankRdBursts::14 19 # Per bank write bursts system.physmem.perBankRdBursts::15 101 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts @@ -106,14 +106,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 124288000 # Total gap between requests +system.physmem.totGap 123701000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 713 # Read request sizes (log2) +system.physmem.readPktSize::6 709 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -121,8 +121,8 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 433 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 204 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 430 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 203 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 55 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 16 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see @@ -217,29 +217,29 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 171 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 249.637427 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 165.941235 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 244.016459 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 63 36.84% 36.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 41 23.98% 60.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 28 16.37% 77.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 13 7.60% 84.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 8 4.68% 89.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 8 4.68% 94.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 3 1.75% 95.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1 0.58% 96.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 6 3.51% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 171 # Bytes accessed per row activation -system.physmem.totQLat 6387250 # Total ticks spent queuing -system.physmem.totMemAccLat 19756000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 3565000 # Total ticks spent in databus transfers -system.physmem.avgQLat 8958.27 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 169 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 251.076923 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 166.451829 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 245.101340 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 63 37.28% 37.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 39 23.08% 60.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 28 16.57% 76.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 13 7.69% 84.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 8 4.73% 89.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 8 4.73% 94.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 3 1.78% 95.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1 0.59% 96.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 6 3.55% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 169 # Bytes accessed per row activation +system.physmem.totQLat 6766000 # Total ticks spent queuing +system.physmem.totMemAccLat 20059750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 3545000 # Total ticks spent in databus transfers +system.physmem.avgQLat 9543.02 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 27708.27 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 366.45 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 28293.02 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 366.12 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 366.45 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 366.12 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 2.86 # Data bus utilization in percentage @@ -247,296 +247,297 @@ system.physmem.busUtilRead 2.86 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.23 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 530 # Number of row buffer hits during reads +system.physmem.readRowHits 528 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 74.33 # Row buffer hit rate for reads +system.physmem.readRowHitRate 74.47 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 174316.97 # Average gap between requests -system.physmem.pageHitRate 74.33 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 816480 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 445500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 2917200 # Energy for read commands per rank (pJ) +system.physmem.avgGap 174472.50 # Average gap between requests +system.physmem.pageHitRate 74.47 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 831600 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 453750 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 2925000 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 7628400 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 46677870 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 29286750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 87772200 # Total energy per rank (pJ) -system.physmem_0.averagePower 749.845263 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 50196500 # Time in different power states +system.physmem_0.actBackEnergy 49377960 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 26918250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 88134960 # Total energy per rank (pJ) +system.physmem_0.averagePower 752.944352 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 47288500 # Time in different power states system.physmem_0.memoryStateTime::REF 3900000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 64717500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 68692500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 430920 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 235125 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 2215200 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 408240 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 222750 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 2184000 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 7628400 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 50794695 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 25675500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 86979840 # Total energy per rank (pJ) -system.physmem_1.averagePower 743.076065 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 46915750 # Time in different power states +system.physmem_1.actBackEnergy 42901335 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 32591250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 85935975 # Total energy per rank (pJ) +system.physmem_1.averagePower 734.244489 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 54352750 # Time in different power states system.physmem_1.memoryStateTime::REF 3900000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 70805750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 59251250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 124523000 # Cumulative time (in ticks) in various power states -system.cpu0.branchPred.lookups 98739 # Number of BP lookups -system.cpu0.branchPred.condPredicted 94242 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 1562 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 96047 # Number of BTB lookups +system.pwrStateResidencyTicks::UNDEFINED 123936000 # Cumulative time (in ticks) in various power states +system.cpu0.branchPred.lookups 98531 # Number of BP lookups +system.cpu0.branchPred.condPredicted 94014 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 1575 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 95788 # Number of BTB lookups system.cpu0.branchPred.BTBHits 0 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu0.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 1131 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.usedRAS 1142 # Number of times the RAS was used to get a target. system.cpu0.branchPred.RASInCorrect 128 # Number of incorrect RAS predictions. -system.cpu0.branchPred.indirectLookups 96047 # Number of indirect predictor lookups. -system.cpu0.branchPred.indirectHits 88694 # Number of indirect target hits. -system.cpu0.branchPred.indirectMisses 7353 # Number of indirect misses. -system.cpu0.branchPredindirectMispredicted 1035 # Number of mispredicted indirect branches. +system.cpu0.branchPred.indirectLookups 95788 # Number of indirect predictor lookups. +system.cpu0.branchPred.indirectHits 88519 # Number of indirect target hits. +system.cpu0.branchPred.indirectMisses 7269 # Number of indirect misses. +system.cpu0.branchPredindirectMispredicted 1054 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.workload.num_syscalls 89 # Number of system calls -system.cpu0.pwrStateResidencyTicks::ON 124523000 # Cumulative time (in ticks) in various power states -system.cpu0.numCycles 249047 # number of cpu cycles simulated +system.cpu0.pwrStateResidencyTicks::ON 123936000 # Cumulative time (in ticks) in various power states +system.cpu0.numCycles 247873 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 23160 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 582455 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 98739 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 89825 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 194593 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 3423 # Number of cycles fetch has spent squashing +system.cpu0.fetch.icacheStallCycles 23367 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 581451 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 98531 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 89661 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 193123 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 3449 # Number of cycles fetch has spent squashing system.cpu0.fetch.TlbCycles 66 # Number of cycles fetch has spent waiting for tlb system.cpu0.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 2218 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingTrapStallCycles 2208 # Number of stall cycles due to pending traps system.cpu0.fetch.IcacheWaitRetryStallCycles 8 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 7952 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 853 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.CacheLines 7997 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 861 # Number of outstanding Icache misses that were squashed system.cpu0.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 221760 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 2.626511 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.263155 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::samples 220500 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 2.636966 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.261585 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 34377 15.50% 15.50% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 91683 41.34% 56.85% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 679 0.31% 57.15% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 1006 0.45% 57.61% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 517 0.23% 57.84% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 87238 39.34% 97.18% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 730 0.33% 97.51% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 482 0.22% 97.72% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 5048 2.28% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 33425 15.16% 15.16% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 91538 41.51% 56.67% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 694 0.31% 56.99% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 1015 0.46% 57.45% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 497 0.23% 57.67% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 87060 39.48% 97.16% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 731 0.33% 97.49% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 514 0.23% 97.72% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 5026 2.28% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 221760 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.396467 # Number of branch fetches per cycle -system.cpu0.fetch.rate 2.338735 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 17619 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 19820 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 181778 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 832 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1711 # Number of cycles decode is squashing -system.cpu0.decode.DecodedInsts 564879 # Number of instructions handled by decode -system.cpu0.rename.SquashCycles 1711 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 18296 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 2376 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 16107 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 181922 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 1348 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 559910 # Number of instructions processed by rename +system.cpu0.fetch.rateDist::total 220500 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.397506 # Number of branch fetches per cycle +system.cpu0.fetch.rate 2.345762 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 17843 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 18591 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 181526 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 816 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1724 # Number of cycles decode is squashing +system.cpu0.decode.DecodedInsts 563984 # Number of instructions handled by decode +system.cpu0.rename.SquashCycles 1724 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 18505 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 1935 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 15328 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 181668 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 1340 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 558880 # Number of instructions processed by rename system.cpu0.rename.IQFullEvents 11 # Number of times rename has blocked due to IQ full system.cpu0.rename.LQFullEvents 11 # Number of times rename has blocked due to LQ full system.cpu0.rename.SQFullEvents 869 # Number of times rename has blocked due to SQ full -system.cpu0.rename.RenamedOperands 383145 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 1115796 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 842870 # Number of integer rename lookups -system.cpu0.rename.CommittedMaps 364171 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 18974 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 1067 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 1095 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 5253 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 178633 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 90222 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 87104 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 86835 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 467056 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1095 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 463006 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 118 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 16506 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 13395 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 536 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 221760 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 2.087870 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.110825 # Number of insts issued each cycle +system.cpu0.rename.RenamedOperands 382489 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 1113780 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 841332 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 2 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 363591 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 18898 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 1094 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 1121 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 5347 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 178321 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 90063 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 86944 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 86670 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 466208 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1118 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 462266 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 112 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 16406 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 13115 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 559 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 220500 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 2.096444 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.103875 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 37234 16.79% 16.79% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 4446 2.00% 18.80% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 88426 39.87% 58.67% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 88102 39.73% 98.40% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 1676 0.76% 99.15% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 983 0.44% 99.60% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 568 0.26% 99.85% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 225 0.10% 99.95% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 100 0.05% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 36239 16.43% 16.43% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 4459 2.02% 18.46% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 88275 40.03% 58.49% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 87972 39.90% 98.39% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 1699 0.77% 99.16% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 988 0.45% 99.61% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 572 0.26% 99.87% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 195 0.09% 99.95% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 101 0.05% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 221760 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 220500 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 134 40.48% 40.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 0 0.00% 40.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 40.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 40.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 40.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 40.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 40.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 40.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 40.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 40.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 40.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 40.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 40.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 40.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 40.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 40.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 40.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 40.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 40.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 40.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 40.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 40.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 40.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 40.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 40.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 40.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 40.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 40.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 40.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 76 22.96% 63.44% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 121 36.56% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 126 38.77% 38.77% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 0 0.00% 38.77% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 38.77% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 38.77% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 38.77% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 38.77% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 38.77% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 38.77% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 38.77% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 38.77% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 38.77% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 38.77% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 38.77% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 38.77% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 38.77% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 38.77% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 38.77% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 38.77% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 38.77% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 38.77% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 38.77% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 38.77% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 38.77% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 38.77% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 38.77% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 38.77% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 38.77% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 38.77% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 38.77% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 78 24.00% 62.77% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 121 37.23% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 195503 42.22% 42.22% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.22% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.22% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.22% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.22% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.22% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.22% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.22% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 42.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 42.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 42.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 42.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 42.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 42.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 42.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 42.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 42.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 42.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 42.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.22% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 178044 38.45% 80.68% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 89459 19.32% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 195215 42.23% 42.23% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.23% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.23% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.23% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.23% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.23% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.23% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.23% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 42.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 42.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 42.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 42.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 42.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 42.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 42.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 42.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 42.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 42.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 42.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.23% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 177740 38.45% 80.68% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 89311 19.32% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 463006 # Type of FU issued -system.cpu0.iq.rate 1.859111 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 331 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.000715 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 1148221 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 484707 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 460421 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.FU_type_0::total 462266 # Type of FU issued +system.cpu0.iq.rate 1.864931 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 325 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.000703 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 1145469 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 483779 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 459725 # Number of integer instruction queue wakeup accesses system.cpu0.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_writes 4 # Number of floating instruction queue writes system.cpu0.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 463337 # Number of integer alu accesses +system.cpu0.iq.int_alu_accesses 462591 # Number of integer alu accesses system.cpu0.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 86583 # Number of loads that had data forwarded from stores +system.cpu0.iew.lsq.thread0.forwLoads 86430 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 2958 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 9 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 52 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 1878 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 2936 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 13 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 53 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 1864 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu0.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu0.iew.lsq.thread0.cacheBlocked 11 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1711 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 2375 # Number of cycles IEW is blocking +system.cpu0.iew.iewSquashCycles 1724 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 1933 # Number of cycles IEW is blocking system.cpu0.iew.iewUnblockCycles 27 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 555874 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 119 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 178633 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 90222 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 980 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewDispatchedInsts 554898 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 123 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 178321 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 90063 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 1001 # Number of dispatched non-speculative instructions system.cpu0.iew.iewIQFullEvents 27 # Number of times the IQ has become full, causing a stall system.cpu0.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 52 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 232 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 1679 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 1911 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 461536 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 177679 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 1470 # Number of squashed instructions skipped in execute +system.cpu0.iew.memOrderViolationEvents 53 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 229 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 1693 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 1922 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 460834 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 177384 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 1432 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 87723 # number of nop insts executed -system.cpu0.iew.exec_refs 266935 # number of memory reference insts executed -system.cpu0.iew.exec_branches 91696 # Number of branches executed -system.cpu0.iew.exec_stores 89256 # Number of stores executed -system.cpu0.iew.exec_rate 1.853208 # Inst execution rate -system.cpu0.iew.wb_sent 460886 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 460421 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 273043 # num instructions producing a value -system.cpu0.iew.wb_consumers 276596 # num instructions consuming a value -system.cpu0.iew.wb_rate 1.848731 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.987155 # average fanout of values written-back -system.cpu0.commit.commitSquashedInsts 17182 # The number of squashed insts skipped by commit +system.cpu0.iew.exec_nop 87572 # number of nop insts executed +system.cpu0.iew.exec_refs 266499 # number of memory reference insts executed +system.cpu0.iew.exec_branches 91565 # Number of branches executed +system.cpu0.iew.exec_stores 89115 # Number of stores executed +system.cpu0.iew.exec_rate 1.859154 # Inst execution rate +system.cpu0.iew.wb_sent 460184 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 459725 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 272583 # num instructions producing a value +system.cpu0.iew.wb_consumers 276120 # num instructions consuming a value +system.cpu0.iew.wb_rate 1.854680 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.987190 # average fanout of values written-back +system.cpu0.commit.commitSquashedInsts 17076 # The number of squashed insts skipped by commit system.cpu0.commit.commitNonSpecStalls 559 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 1562 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 218398 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 2.466176 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 2.142349 # Number of insts commited each cycle +system.cpu0.commit.branchMispredicts 1575 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 217161 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 2.476218 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 2.140669 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 37197 17.03% 17.03% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 90473 41.43% 58.46% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 2051 0.94% 59.40% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 612 0.28% 59.68% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 499 0.23% 59.91% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 86381 39.55% 99.46% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 448 0.21% 99.66% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 288 0.13% 99.79% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 449 0.21% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 36214 16.68% 16.68% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 90367 41.61% 58.29% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 2049 0.94% 59.23% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 624 0.29% 59.52% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 510 0.23% 59.75% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 86212 39.70% 99.45% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 445 0.20% 99.66% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 289 0.13% 99.79% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 451 0.21% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 218398 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 538608 # Number of instructions committed -system.cpu0.commit.committedOps 538608 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 217161 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 537738 # Number of instructions committed +system.cpu0.commit.committedOps 537738 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 264019 # Number of memory references committed -system.cpu0.commit.loads 175675 # Number of loads committed +system.cpu0.commit.refs 263584 # Number of memory references committed +system.cpu0.commit.loads 175385 # Number of loads committed system.cpu0.commit.membars 84 # Number of memory barriers committed -system.cpu0.commit.branches 90231 # Number of branches committed +system.cpu0.commit.branches 90086 # Number of branches committed system.cpu0.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 362502 # Number of committed integer instructions. +system.cpu0.commit.int_insts 361922 # Number of committed integer instructions. system.cpu0.commit.function_calls 223 # Number of function calls committed. -system.cpu0.commit.op_class_0::No_OpClass 86963 16.15% 16.15% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 187542 34.82% 50.97% # Class of committed instruction +system.cpu0.commit.op_class_0::No_OpClass 86818 16.15% 16.15% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 187252 34.82% 50.97% # Class of committed instruction system.cpu0.commit.op_class_0::IntMult 0 0.00% 50.97% # Class of committed instruction system.cpu0.commit.op_class_0::IntDiv 0 0.00% 50.97% # Class of committed instruction system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 50.97% # Class of committed instruction @@ -565,105 +566,105 @@ system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 50.97% system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 50.97% # Class of committed instruction system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 50.97% # Class of committed instruction system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 50.97% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 175759 32.63% 83.60% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 88344 16.40% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 175469 32.63% 83.60% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 88199 16.40% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 538608 # Class of committed instruction -system.cpu0.commit.bw_lim_events 449 # number cycles where commit BW limit reached -system.cpu0.rob.rob_reads 772578 # The number of ROB reads -system.cpu0.rob.rob_writes 1114998 # The number of ROB writes -system.cpu0.timesIdled 315 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 27287 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.committedInsts 451561 # Number of Instructions Simulated -system.cpu0.committedOps 451561 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 0.551525 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 0.551525 # CPI: Total CPI of All Threads -system.cpu0.ipc 1.813156 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 1.813156 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 825039 # number of integer regfile reads -system.cpu0.int_regfile_writes 371919 # number of integer regfile writes +system.cpu0.commit.op_class_0::total 537738 # Class of committed instruction +system.cpu0.commit.bw_lim_events 451 # number cycles where commit BW limit reached +system.cpu0.rob.rob_reads 770363 # The number of ROB reads +system.cpu0.rob.rob_writes 1113018 # The number of ROB writes +system.cpu0.timesIdled 321 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 27373 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.committedInsts 450836 # Number of Instructions Simulated +system.cpu0.committedOps 450836 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 0.549807 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 0.549807 # CPI: Total CPI of All Threads +system.cpu0.ipc 1.818819 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 1.818819 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 823745 # number of integer regfile reads +system.cpu0.int_regfile_writes 371341 # number of integer regfile writes system.cpu0.fp_regfile_reads 192 # number of floating regfile reads -system.cpu0.misc_regfile_reads 269052 # number of misc regfile reads +system.cpu0.misc_regfile_reads 268638 # number of misc regfile reads system.cpu0.misc_regfile_writes 564 # number of misc regfile writes -system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 124523000 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 123936000 # Cumulative time (in ticks) in various power states system.cpu0.dcache.tags.replacements 2 # number of replacements -system.cpu0.dcache.tags.tagsinuse 142.724931 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 178078 # Total number of references to valid blocks. +system.cpu0.dcache.tags.tagsinuse 142.669467 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 177790 # Total number of references to valid blocks. system.cpu0.dcache.tags.sampled_refs 172 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 1035.337209 # Average number of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 1033.662791 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 142.724931 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.278760 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.278760 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 142.669467 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.278651 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.278651 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 170 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 143 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 0.332031 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 717658 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 717658 # Number of data accesses -system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 124523000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.ReadReq_hits::cpu0.data 90413 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 90413 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 87748 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 87748 # number of WriteReq hits -system.cpu0.dcache.SwapReq_hits::cpu0.data 23 # number of SwapReq hits -system.cpu0.dcache.SwapReq_hits::total 23 # number of SwapReq hits -system.cpu0.dcache.demand_hits::cpu0.data 178161 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 178161 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 178161 # number of overall hits -system.cpu0.dcache.overall_hits::total 178161 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 578 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 578 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 554 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 554 # number of WriteReq misses -system.cpu0.dcache.SwapReq_misses::cpu0.data 19 # number of SwapReq misses -system.cpu0.dcache.SwapReq_misses::total 19 # number of SwapReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1132 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1132 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1132 # number of overall misses -system.cpu0.dcache.overall_misses::total 1132 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 18168000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 18168000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 36152490 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 36152490 # number of WriteReq miss cycles -system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 521000 # number of SwapReq miss cycles -system.cpu0.dcache.SwapReq_miss_latency::total 521000 # number of SwapReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 54320490 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 54320490 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 54320490 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 54320490 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 90991 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 90991 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 88302 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 88302 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.tags.tag_accesses 716504 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 716504 # Number of data accesses +system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 123936000 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.ReadReq_hits::cpu0.data 90267 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 90267 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 87606 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 87606 # number of WriteReq hits +system.cpu0.dcache.SwapReq_hits::cpu0.data 22 # number of SwapReq hits +system.cpu0.dcache.SwapReq_hits::total 22 # number of SwapReq hits +system.cpu0.dcache.demand_hits::cpu0.data 177873 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 177873 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 177873 # number of overall hits +system.cpu0.dcache.overall_hits::total 177873 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 580 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 580 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 551 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 551 # number of WriteReq misses +system.cpu0.dcache.SwapReq_misses::cpu0.data 20 # number of SwapReq misses +system.cpu0.dcache.SwapReq_misses::total 20 # number of SwapReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1131 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1131 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1131 # number of overall misses +system.cpu0.dcache.overall_misses::total 1131 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 15004000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 15004000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 35761990 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 35761990 # number of WriteReq miss cycles +system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 487500 # number of SwapReq miss cycles +system.cpu0.dcache.SwapReq_miss_latency::total 487500 # number of SwapReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 50765990 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 50765990 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 50765990 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 50765990 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 90847 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 90847 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 88157 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 88157 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses) system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 179293 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 179293 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 179293 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 179293 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.006352 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.006352 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.006274 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.006274 # miss rate for WriteReq accesses -system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.452381 # miss rate for SwapReq accesses -system.cpu0.dcache.SwapReq_miss_rate::total 0.452381 # miss rate for SwapReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.006314 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.006314 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.006314 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.006314 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 31432.525952 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 31432.525952 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 65257.202166 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 65257.202166 # average WriteReq miss latency -system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 27421.052632 # average SwapReq miss latency -system.cpu0.dcache.SwapReq_avg_miss_latency::total 27421.052632 # average SwapReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 47986.298587 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 47986.298587 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 47986.298587 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 47986.298587 # average overall miss latency +system.cpu0.dcache.demand_accesses::cpu0.data 179004 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 179004 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 179004 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 179004 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.006384 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.006384 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.006250 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.006250 # miss rate for WriteReq accesses +system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.476190 # miss rate for SwapReq accesses +system.cpu0.dcache.SwapReq_miss_rate::total 0.476190 # miss rate for SwapReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.006318 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.006318 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.006318 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.006318 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 25868.965517 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 25868.965517 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 64903.793103 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 64903.793103 # average WriteReq miss latency +system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 24375 # average SwapReq miss latency +system.cpu0.dcache.SwapReq_avg_miss_latency::total 24375 # average SwapReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 44885.932803 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 44885.932803 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 44885.932803 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 44885.932803 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 832 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 22 # number of cycles access was blocked @@ -672,2233 +673,2195 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs 37.818182 system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks system.cpu0.dcache.writebacks::total 1 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 385 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 385 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 387 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 387 # number of WriteReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 772 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 772 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 772 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 772 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 193 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 193 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 167 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 167 # number of WriteReq MSHR misses -system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 19 # number of SwapReq MSHR misses -system.cpu0.dcache.SwapReq_mshr_misses::total 19 # number of SwapReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 360 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 360 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 360 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 360 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 7230000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 7230000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 8425000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8425000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 502000 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.SwapReq_mshr_miss_latency::total 502000 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 15655000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 15655000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 15655000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 15655000 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002121 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002121 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.001891 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.001891 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.452381 # mshr miss rate for SwapReq accesses -system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.452381 # mshr miss rate for SwapReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002008 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.002008 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002008 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.002008 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 37461.139896 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 37461.139896 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 50449.101796 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 50449.101796 # average WriteReq mshr miss latency -system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 26421.052632 # average SwapReq mshr miss latency -system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 26421.052632 # average SwapReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 43486.111111 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 43486.111111 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 43486.111111 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 43486.111111 # average overall mshr miss latency -system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 124523000 # Cumulative time (in ticks) in various power states -system.cpu0.icache.tags.replacements 394 # number of replacements -system.cpu0.icache.tags.tagsinuse 248.905102 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 7041 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 695 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 10.130935 # Average number of references to valid blocks. +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 378 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 378 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 383 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 383 # number of WriteReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 761 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 761 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 761 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 761 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 202 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 202 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 168 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 168 # number of WriteReq MSHR misses +system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 20 # number of SwapReq MSHR misses +system.cpu0.dcache.SwapReq_mshr_misses::total 20 # number of SwapReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 370 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 370 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 370 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 370 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 6835500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6835500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 8076500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8076500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 467500 # number of SwapReq MSHR miss cycles +system.cpu0.dcache.SwapReq_mshr_miss_latency::total 467500 # number of SwapReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 14912000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 14912000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 14912000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 14912000 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002224 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002224 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.001906 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.001906 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.476190 # mshr miss rate for SwapReq accesses +system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.476190 # mshr miss rate for SwapReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002067 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.002067 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002067 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.002067 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 33839.108911 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 33839.108911 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 48074.404762 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 48074.404762 # average WriteReq mshr miss latency +system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 23375 # average SwapReq mshr miss latency +system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 23375 # average SwapReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 40302.702703 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 40302.702703 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 40302.702703 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 40302.702703 # average overall mshr miss latency +system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 123936000 # Cumulative time (in ticks) in various power states +system.cpu0.icache.tags.replacements 413 # number of replacements +system.cpu0.icache.tags.tagsinuse 250.106503 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 7058 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 712 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 9.912921 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 248.905102 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.486143 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.486143 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_task_id_blocks::1024 301 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 70 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 39 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 192 # Occupied blocks per task id -system.cpu0.icache.tags.occ_task_id_percent::1024 0.587891 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 8647 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 8647 # Number of data accesses -system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 124523000 # Cumulative time (in ticks) in various power states -system.cpu0.icache.ReadReq_hits::cpu0.inst 7041 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 7041 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 7041 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 7041 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 7041 # number of overall hits -system.cpu0.icache.overall_hits::total 7041 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 911 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 911 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 911 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 911 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 911 # number of overall misses -system.cpu0.icache.overall_misses::total 911 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 43691000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 43691000 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 43691000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 43691000 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 43691000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 43691000 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 7952 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 7952 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 7952 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 7952 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 7952 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 7952 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.114562 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.114562 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.114562 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.114562 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.114562 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.114562 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 47959.385291 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 47959.385291 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 47959.385291 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 47959.385291 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 47959.385291 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 47959.385291 # average overall miss latency +system.cpu0.icache.tags.occ_blocks::cpu0.inst 250.106503 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.488489 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.488489 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_task_id_blocks::1024 299 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 68 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 41 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 190 # Occupied blocks per task id +system.cpu0.icache.tags.occ_task_id_percent::1024 0.583984 # Percentage of cache occupancy per task id +system.cpu0.icache.tags.tag_accesses 8709 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 8709 # Number of data accesses +system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 123936000 # Cumulative time (in ticks) in various power states +system.cpu0.icache.ReadReq_hits::cpu0.inst 7058 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 7058 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 7058 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 7058 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 7058 # number of overall hits +system.cpu0.icache.overall_hits::total 7058 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 939 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 939 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 939 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 939 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 939 # number of overall misses +system.cpu0.icache.overall_misses::total 939 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 44243500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 44243500 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 44243500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 44243500 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 44243500 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 44243500 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 7997 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 7997 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 7997 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 7997 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 7997 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 7997 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.117419 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.117419 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.117419 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.117419 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.117419 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.117419 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 47117.678381 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 47117.678381 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 47117.678381 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 47117.678381 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 47117.678381 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 47117.678381 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 117 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 4 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.icache.avg_blocked_cycles::no_mshrs 29.250000 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.writebacks::writebacks 394 # number of writebacks -system.cpu0.icache.writebacks::total 394 # number of writebacks -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 215 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 215 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 215 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 215 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 215 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 215 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 696 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 696 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 696 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 696 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 696 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 696 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 33693000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 33693000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 33693000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 33693000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 33693000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 33693000 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.087525 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.087525 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.087525 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.087525 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.087525 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.087525 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 48409.482759 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 48409.482759 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 48409.482759 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 48409.482759 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 48409.482759 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 48409.482759 # average overall mshr miss latency -system.cpu1.branchPred.lookups 70381 # Number of BP lookups -system.cpu1.branchPred.condPredicted 62763 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 2321 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 62113 # Number of BTB lookups +system.cpu0.icache.writebacks::writebacks 413 # number of writebacks +system.cpu0.icache.writebacks::total 413 # number of writebacks +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 226 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 226 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 226 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 226 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 226 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 226 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 713 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 713 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 713 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 713 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 713 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 713 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 34164500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 34164500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 34164500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 34164500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 34164500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 34164500 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.089158 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.089158 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.089158 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.089158 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.089158 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.089158 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 47916.549790 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 47916.549790 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 47916.549790 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 47916.549790 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 47916.549790 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 47916.549790 # average overall mshr miss latency +system.cpu1.branchPred.lookups 73042 # Number of BP lookups +system.cpu1.branchPred.condPredicted 65659 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 2238 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 64943 # Number of BTB lookups system.cpu1.branchPred.BTBHits 0 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu1.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 1978 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.usedRAS 1989 # Number of times the RAS was used to get a target. system.cpu1.branchPred.RASInCorrect 231 # Number of incorrect RAS predictions. -system.cpu1.branchPred.indirectLookups 62113 # Number of indirect predictor lookups. -system.cpu1.branchPred.indirectHits 52196 # Number of indirect target hits. -system.cpu1.branchPred.indirectMisses 9917 # Number of indirect misses. -system.cpu1.branchPredindirectMispredicted 1232 # Number of mispredicted indirect branches. -system.cpu1.pwrStateResidencyTicks::ON 124523000 # Cumulative time (in ticks) in various power states -system.cpu1.numCycles 193493 # number of cpu cycles simulated +system.cpu1.branchPred.indirectLookups 64943 # Number of indirect predictor lookups. +system.cpu1.branchPred.indirectHits 55241 # Number of indirect target hits. +system.cpu1.branchPred.indirectMisses 9702 # Number of indirect misses. +system.cpu1.branchPredindirectMispredicted 1128 # Number of mispredicted indirect branches. +system.cpu1.pwrStateResidencyTicks::ON 123936000 # Cumulative time (in ticks) in various power states +system.cpu1.numCycles 192502 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 35625 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 388406 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 70381 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 54174 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 147522 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 4799 # Number of cycles fetch has spent squashing +system.cpu1.fetch.icacheStallCycles 33710 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 406560 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 73042 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 57230 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 148689 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 4633 # Number of cycles fetch has spent squashing system.cpu1.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu1.fetch.NoActiveThreadStallCycles 10 # Number of stall cycles due to no active thread to fetch from -system.cpu1.fetch.PendingTrapStallCycles 1696 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingTrapStallCycles 1669 # Number of stall cycles due to pending traps system.cpu1.fetch.IcacheWaitRetryStallCycles 15 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 23532 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 933 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 187271 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 2.074032 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.377312 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.CacheLines 22180 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 918 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 186413 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 2.180964 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.381342 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 61181 32.67% 32.67% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 61333 32.75% 65.42% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 6091 3.25% 68.67% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 3354 1.79% 70.46% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 663 0.35% 70.82% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 43826 23.40% 94.22% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 1093 0.58% 94.80% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 1351 0.72% 95.53% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 8379 4.47% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 54977 29.49% 29.49% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 63721 34.18% 63.67% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 5493 2.95% 66.62% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 3499 1.88% 68.50% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 651 0.35% 68.85% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 47493 25.48% 94.32% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 995 0.53% 94.86% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 1355 0.73% 95.59% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 8229 4.41% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 187271 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.363739 # Number of branch fetches per cycle -system.cpu1.fetch.rate 2.007339 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 22629 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 55115 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 103585 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 3533 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 2399 # Number of cycles decode is squashing -system.cpu1.decode.DecodedInsts 358317 # Number of instructions handled by decode -system.cpu1.rename.SquashCycles 2399 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 23637 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 25102 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 14378 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 104390 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 17355 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 351725 # Number of instructions processed by rename -system.cpu1.rename.IQFullEvents 14900 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 17 # Number of times rename has blocked due to LQ full +system.cpu1.fetch.rateDist::total 186413 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.379435 # Number of branch fetches per cycle +system.cpu1.fetch.rate 2.111978 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 22012 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 48189 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 110683 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 3203 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 2316 # Number of cycles decode is squashing +system.cpu1.decode.DecodedInsts 375249 # Number of instructions handled by decode +system.cpu1.rename.SquashCycles 2316 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 23003 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 21046 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 13565 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 110960 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 15513 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 369118 # Number of instructions processed by rename +system.cpu1.rename.IQFullEvents 12808 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 18 # Number of times rename has blocked due to LQ full system.cpu1.rename.FullRegisterEvents 3 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 247787 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 679105 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 526513 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 34 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 220167 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 27620 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 1612 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 1735 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 22764 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 99432 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 48003 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 46782 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 41727 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 289849 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 6510 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 288395 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 111 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 24134 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 20047 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 1135 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 187271 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 1.539988 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.388620 # Number of insts issued each cycle +system.cpu1.rename.RenamedOperands 260404 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 717496 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 555302 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 32 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 234261 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 26143 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 1622 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 1759 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 20875 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 105786 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 51568 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 49714 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 45358 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 305985 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 5880 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 304555 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 84 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 23105 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 18122 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 1124 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 186413 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 1.633765 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.368784 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 65886 35.18% 35.18% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 21449 11.45% 46.64% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 46526 24.84% 71.48% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 46214 24.68% 96.16% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 3599 1.92% 98.08% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1752 0.94% 99.01% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 1124 0.60% 99.61% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 416 0.22% 99.84% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 305 0.16% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 59464 31.90% 31.90% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 19554 10.49% 42.39% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 50315 26.99% 69.38% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 50093 26.87% 96.25% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 3572 1.92% 98.17% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1698 0.91% 99.08% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 1008 0.54% 99.62% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 406 0.22% 99.84% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 303 0.16% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 187271 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 186413 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 198 39.68% 39.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 39.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 39.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 39.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 39.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 39.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 39.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 39.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 39.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 39.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 39.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 39.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 39.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 39.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 39.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 39.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 39.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 39.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 39.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 39.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 39.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 39.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 39.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 39.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 39.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 39.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 39.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 39.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 39.68% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 73 14.63% 54.31% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 228 45.69% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 182 38.89% 38.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 38.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 38.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 38.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 38.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 38.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 38.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 38.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 38.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 38.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 38.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 38.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 38.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 38.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 38.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 38.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 38.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 38.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 38.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 38.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 38.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 38.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 38.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 38.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 38.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 38.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 38.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 38.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 38.89% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 58 12.39% 51.28% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 228 48.72% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 138505 48.03% 48.03% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 0 0.00% 48.03% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 48.03% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 48.03% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 48.03% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 48.03% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 48.03% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 48.03% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 48.03% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 48.03% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 48.03% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 48.03% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 48.03% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 48.03% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 48.03% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 48.03% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 48.03% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 48.03% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.03% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 48.03% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.03% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.03% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.03% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.03% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.03% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.03% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 48.03% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.03% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.03% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 102963 35.70% 83.73% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 46927 16.27% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 145063 47.63% 47.63% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 0 0.00% 47.63% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.63% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.63% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.63% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 47.63% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 47.63% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 47.63% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 47.63% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 47.63% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.63% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 47.63% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 47.63% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 47.63% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 47.63% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.63% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.63% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 47.63% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 47.63% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.63% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.63% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.63% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.63% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.63% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.63% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 47.63% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.63% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.63% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.63% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 108861 35.74% 83.38% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 50631 16.62% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 288395 # Type of FU issued -system.cpu1.iq.rate 1.490467 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 499 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.001730 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 764671 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 320465 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 284383 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.FU_type_0::total 304555 # Type of FU issued +system.cpu1.iq.rate 1.582087 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 468 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.001537 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 796075 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 334945 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 300973 # Number of integer instruction queue wakeup accesses system.cpu1.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 68 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_writes 64 # Number of floating instruction queue writes system.cpu1.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 288894 # Number of integer alu accesses +system.cpu1.iq.int_alu_accesses 305023 # Number of integer alu accesses system.cpu1.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 41593 # Number of loads that had data forwarded from stores +system.cpu1.iew.lsq.thread0.forwLoads 45252 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 4579 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 38 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 40 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 2647 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 4194 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 25 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 39 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 2536 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu1.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu1.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 2399 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 8044 # Number of cycles IEW is blocking +system.cpu1.iew.iewSquashCycles 2316 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 6366 # Number of cycles IEW is blocking system.cpu1.iew.iewUnblockCycles 55 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 344307 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 270 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 99432 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 48003 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 1487 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 36 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewDispatchedInsts 362764 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 272 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 105786 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 51568 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 1528 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 40 # Number of times the IQ has become full, causing a stall system.cpu1.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 40 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 446 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 2454 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 2900 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 285809 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 97701 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 2586 # Number of squashed instructions skipped in execute +system.cpu1.iew.memOrderViolationEvents 39 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 443 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 2397 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 2840 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 302276 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 104291 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 2279 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 47948 # number of nop insts executed -system.cpu1.iew.exec_refs 144318 # number of memory reference insts executed -system.cpu1.iew.exec_branches 58093 # Number of branches executed -system.cpu1.iew.exec_stores 46617 # Number of stores executed -system.cpu1.iew.exec_rate 1.477103 # Inst execution rate -system.cpu1.iew.wb_sent 284919 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 284383 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 161989 # num instructions producing a value -system.cpu1.iew.wb_consumers 169394 # num instructions consuming a value -system.cpu1.iew.wb_rate 1.469733 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.956285 # average fanout of values written-back -system.cpu1.commit.commitSquashedInsts 25278 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 5375 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 2321 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 182469 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 1.748204 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 2.087021 # Number of insts commited each cycle +system.cpu1.iew.exec_nop 50899 # number of nop insts executed +system.cpu1.iew.exec_refs 154635 # number of memory reference insts executed +system.cpu1.iew.exec_branches 61121 # Number of branches executed +system.cpu1.iew.exec_stores 50344 # Number of stores executed +system.cpu1.iew.exec_rate 1.570249 # Inst execution rate +system.cpu1.iew.wb_sent 301460 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 300973 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 172395 # num instructions producing a value +system.cpu1.iew.wb_consumers 179828 # num instructions consuming a value +system.cpu1.iew.wb_rate 1.563480 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.958666 # average fanout of values written-back +system.cpu1.commit.commitSquashedInsts 24140 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 4756 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 2238 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 181815 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 1.862272 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 2.110451 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 70580 38.68% 38.68% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 54368 29.80% 68.48% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 5362 2.94% 71.41% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 6062 3.32% 74.74% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1316 0.72% 75.46% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 41726 22.87% 98.33% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 809 0.44% 98.77% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 1001 0.55% 99.32% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1245 0.68% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 63682 35.03% 35.03% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 57506 31.63% 66.65% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 5445 2.99% 69.65% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 5412 2.98% 72.63% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1312 0.72% 73.35% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 45472 25.01% 98.36% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 770 0.42% 98.78% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 999 0.55% 99.33% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1217 0.67% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 182469 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 318993 # Number of instructions committed -system.cpu1.commit.committedOps 318993 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 181815 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 338589 # Number of instructions committed +system.cpu1.commit.committedOps 338589 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 140209 # Number of memory references committed -system.cpu1.commit.loads 94853 # Number of loads committed -system.cpu1.commit.membars 4659 # Number of memory barriers committed -system.cpu1.commit.branches 55980 # Number of branches committed +system.cpu1.commit.refs 150624 # Number of memory references committed +system.cpu1.commit.loads 101592 # Number of loads committed +system.cpu1.commit.membars 4041 # Number of memory barriers committed +system.cpu1.commit.branches 59040 # Number of branches committed system.cpu1.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 218308 # Number of committed integer instructions. +system.cpu1.commit.int_insts 231783 # Number of committed integer instructions. system.cpu1.commit.function_calls 322 # Number of function calls committed. -system.cpu1.commit.op_class_0::No_OpClass 46768 14.66% 14.66% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 127357 39.92% 54.59% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 0 0.00% 54.59% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 0 0.00% 54.59% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 54.59% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 54.59% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 54.59% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 54.59% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 54.59% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 54.59% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 54.59% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 54.59% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 54.59% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 54.59% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 54.59% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 54.59% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 54.59% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 54.59% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 54.59% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 54.59% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 54.59% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 54.59% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 54.59% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 54.59% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 54.59% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 54.59% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 54.59% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 54.59% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 54.59% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 54.59% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 99512 31.20% 85.78% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 45356 14.22% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::No_OpClass 49829 14.72% 14.72% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 134095 39.60% 54.32% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 0 0.00% 54.32% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 0 0.00% 54.32% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 54.32% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 54.32% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 54.32% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 54.32% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 54.32% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 54.32% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 54.32% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 54.32% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 54.32% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 54.32% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 54.32% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 54.32% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 54.32% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 54.32% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 54.32% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 54.32% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 54.32% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 54.32% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 54.32% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 54.32% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 54.32% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 54.32% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 54.32% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 54.32% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 54.32% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 54.32% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 105633 31.20% 85.52% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 49032 14.48% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 318993 # Class of committed instruction -system.cpu1.commit.bw_lim_events 1245 # number cycles where commit BW limit reached -system.cpu1.rob.rob_reads 524909 # The number of ROB reads -system.cpu1.rob.rob_writes 693389 # The number of ROB writes -system.cpu1.timesIdled 247 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 6222 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.commit.op_class_0::total 338589 # Class of committed instruction +system.cpu1.commit.bw_lim_events 1217 # number cycles where commit BW limit reached +system.cpu1.rob.rob_reads 542741 # The number of ROB reads +system.cpu1.rob.rob_writes 730091 # The number of ROB writes +system.cpu1.timesIdled 236 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 6089 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu1.quiesceCycles 47433 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 267566 # Number of Instructions Simulated -system.cpu1.committedOps 267566 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 0.723160 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 0.723160 # CPI: Total CPI of All Threads -system.cpu1.ipc 1.382820 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 1.382820 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 496242 # number of integer regfile reads -system.cpu1.int_regfile_writes 230976 # number of integer regfile writes +system.cpu1.committedInsts 284719 # Number of Instructions Simulated +system.cpu1.committedOps 284719 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 0.676112 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 0.676112 # CPI: Total CPI of All Threads +system.cpu1.ipc 1.479044 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 1.479044 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 527704 # number of integer regfile reads +system.cpu1.int_regfile_writes 245054 # number of integer regfile writes system.cpu1.fp_regfile_writes 64 # number of floating regfile writes -system.cpu1.misc_regfile_reads 146210 # number of misc regfile reads +system.cpu1.misc_regfile_reads 156484 # number of misc regfile reads system.cpu1.misc_regfile_writes 648 # number of misc regfile writes -system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 124523000 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 123936000 # Cumulative time (in ticks) in various power states system.cpu1.dcache.tags.replacements 0 # number of replacements -system.cpu1.dcache.tags.tagsinuse 26.604916 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 52484 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 31 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 1693.032258 # Average number of references to valid blocks. +system.cpu1.dcache.tags.tagsinuse 26.869792 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 56025 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 1931.896552 # Average number of references to valid blocks. system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 26.604916 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.051963 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.051963 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 31 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 24 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.060547 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 405985 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 405985 # Number of data accesses -system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 124523000 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.ReadReq_hits::cpu1.data 55568 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 55568 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 45140 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 45140 # number of WriteReq hits -system.cpu1.dcache.SwapReq_hits::cpu1.data 12 # number of SwapReq hits -system.cpu1.dcache.SwapReq_hits::total 12 # number of SwapReq hits -system.cpu1.dcache.demand_hits::cpu1.data 100708 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 100708 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 100708 # number of overall hits -system.cpu1.dcache.overall_hits::total 100708 # number of overall hits +system.cpu1.dcache.tags.occ_blocks::cpu1.data 26.869792 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.052480 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.052480 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 27 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 432447 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 432447 # Number of data accesses +system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 123936000 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.ReadReq_hits::cpu1.data 58508 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 58508 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 48814 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 48814 # number of WriteReq hits +system.cpu1.dcache.SwapReq_hits::cpu1.data 11 # number of SwapReq hits +system.cpu1.dcache.SwapReq_hits::total 11 # number of SwapReq hits +system.cpu1.dcache.demand_hits::cpu1.data 107322 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 107322 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 107322 # number of overall hits +system.cpu1.dcache.overall_hits::total 107322 # number of overall hits system.cpu1.dcache.ReadReq_misses::cpu1.data 507 # number of ReadReq misses system.cpu1.dcache.ReadReq_misses::total 507 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 146 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 146 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 149 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 149 # number of WriteReq misses system.cpu1.dcache.SwapReq_misses::cpu1.data 58 # number of SwapReq misses system.cpu1.dcache.SwapReq_misses::total 58 # number of SwapReq misses -system.cpu1.dcache.demand_misses::cpu1.data 653 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 653 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 653 # number of overall misses -system.cpu1.dcache.overall_misses::total 653 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 9264000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 9264000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3726500 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 3726500 # number of WriteReq miss cycles -system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 796000 # number of SwapReq miss cycles -system.cpu1.dcache.SwapReq_miss_latency::total 796000 # number of SwapReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 12990500 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 12990500 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 12990500 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 12990500 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 56075 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 56075 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 45286 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 45286 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SwapReq_accesses::cpu1.data 70 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.SwapReq_accesses::total 70 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 101361 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 101361 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 101361 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 101361 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.009041 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.009041 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.003224 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.003224 # miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.828571 # miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_miss_rate::total 0.828571 # miss rate for SwapReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.006442 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.006442 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.006442 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.006442 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 18272.189349 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 18272.189349 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 25523.972603 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 25523.972603 # average WriteReq miss latency -system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 13724.137931 # average SwapReq miss latency -system.cpu1.dcache.SwapReq_avg_miss_latency::total 13724.137931 # average SwapReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19893.568147 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 19893.568147 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 19893.568147 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 19893.568147 # average overall miss latency +system.cpu1.dcache.demand_misses::cpu1.data 656 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 656 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 656 # number of overall misses +system.cpu1.dcache.overall_misses::total 656 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 4815500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 4815500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3532500 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 3532500 # number of WriteReq miss cycles +system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 364000 # number of SwapReq miss cycles +system.cpu1.dcache.SwapReq_miss_latency::total 364000 # number of SwapReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 8348000 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 8348000 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 8348000 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 8348000 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 59015 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 59015 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 48963 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 48963 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_accesses::cpu1.data 69 # number of SwapReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_accesses::total 69 # number of SwapReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 107978 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 107978 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 107978 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 107978 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.008591 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.008591 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.003043 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.003043 # miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.840580 # miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_miss_rate::total 0.840580 # miss rate for SwapReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.006075 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.006075 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.006075 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.006075 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 9498.027613 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 9498.027613 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 23708.053691 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 23708.053691 # average WriteReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 6275.862069 # average SwapReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::total 6275.862069 # average SwapReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 12725.609756 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 12725.609756 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 12725.609756 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 12725.609756 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 341 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 341 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 40 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 40 # number of WriteReq MSHR hits -system.cpu1.dcache.SwapReq_mshr_hits::cpu1.data 2 # number of SwapReq MSHR hits -system.cpu1.dcache.SwapReq_mshr_hits::total 2 # number of SwapReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 381 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 381 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 381 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 381 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 166 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 166 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 344 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 344 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 43 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 43 # number of WriteReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 387 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 387 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 387 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 387 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 163 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 163 # number of ReadReq MSHR misses system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 106 # number of WriteReq MSHR misses system.cpu1.dcache.WriteReq_mshr_misses::total 106 # number of WriteReq MSHR misses -system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 56 # number of SwapReq MSHR misses -system.cpu1.dcache.SwapReq_mshr_misses::total 56 # number of SwapReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 272 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 272 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 272 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 272 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2098000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2098000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1657500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1657500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 738000 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::total 738000 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3755500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 3755500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3755500 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 3755500 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.002960 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.002960 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.002341 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.002341 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.800000 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.800000 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.002683 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.002683 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.002683 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.002683 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12638.554217 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12638.554217 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 15636.792453 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 15636.792453 # average WriteReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 13178.571429 # average SwapReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 13178.571429 # average SwapReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 13806.985294 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 13806.985294 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 13806.985294 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 13806.985294 # average overall mshr miss latency -system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 124523000 # Cumulative time (in ticks) in various power states -system.cpu1.icache.tags.replacements 579 # number of replacements -system.cpu1.icache.tags.tagsinuse 98.515696 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 22662 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 713 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 31.784011 # Average number of references to valid blocks. +system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 58 # number of SwapReq MSHR misses +system.cpu1.dcache.SwapReq_mshr_misses::total 58 # number of SwapReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 269 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 269 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 269 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 269 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1494500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1494500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1455500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1455500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 306000 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::total 306000 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2950000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 2950000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2950000 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 2950000 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.002762 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.002762 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.002165 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.002165 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.840580 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.840580 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.002491 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.002491 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.002491 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.002491 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 9168.711656 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 9168.711656 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 13731.132075 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 13731.132075 # average WriteReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 5275.862069 # average SwapReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 5275.862069 # average SwapReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 10966.542751 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 10966.542751 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 10966.542751 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 10966.542751 # average overall mshr miss latency +system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 123936000 # Cumulative time (in ticks) in various power states +system.cpu1.icache.tags.replacements 556 # number of replacements +system.cpu1.icache.tags.tagsinuse 97.374754 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 21335 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 687 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 31.055313 # Average number of references to valid blocks. system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 98.515696 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.192413 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.192413 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_task_id_blocks::1024 134 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 20 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 106 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 8 # Occupied blocks per task id -system.cpu1.icache.tags.occ_task_id_percent::1024 0.261719 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 24245 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 24245 # Number of data accesses -system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 124523000 # Cumulative time (in ticks) in various power states -system.cpu1.icache.ReadReq_hits::cpu1.inst 22662 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 22662 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 22662 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 22662 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 22662 # number of overall hits -system.cpu1.icache.overall_hits::total 22662 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 870 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 870 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 870 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 870 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 870 # number of overall misses -system.cpu1.icache.overall_misses::total 870 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 19533000 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 19533000 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 19533000 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 19533000 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 19533000 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 19533000 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 23532 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 23532 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 23532 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 23532 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 23532 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 23532 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.036971 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.036971 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.036971 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.036971 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.036971 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.036971 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 22451.724138 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 22451.724138 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 22451.724138 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 22451.724138 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 22451.724138 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 22451.724138 # average overall miss latency +system.cpu1.icache.tags.occ_blocks::cpu1.inst 97.374754 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.190185 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.190185 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_task_id_blocks::1024 131 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 111 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id +system.cpu1.icache.tags.occ_task_id_percent::1024 0.255859 # Percentage of cache occupancy per task id +system.cpu1.icache.tags.tag_accesses 22867 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 22867 # Number of data accesses +system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 123936000 # Cumulative time (in ticks) in various power states +system.cpu1.icache.ReadReq_hits::cpu1.inst 21335 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 21335 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 21335 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 21335 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 21335 # number of overall hits +system.cpu1.icache.overall_hits::total 21335 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 845 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 845 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 845 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 845 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 845 # number of overall misses +system.cpu1.icache.overall_misses::total 845 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 18952000 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 18952000 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 18952000 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 18952000 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 18952000 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 18952000 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 22180 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 22180 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 22180 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 22180 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 22180 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 22180 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.038097 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.038097 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.038097 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.038097 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.038097 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.038097 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 22428.402367 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 22428.402367 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 22428.402367 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 22428.402367 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 22428.402367 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 22428.402367 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 141 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 4 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.icache.avg_blocked_cycles::no_mshrs 35.250000 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.icache.writebacks::writebacks 579 # number of writebacks -system.cpu1.icache.writebacks::total 579 # number of writebacks -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 157 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 157 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 157 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 157 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 157 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 157 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 713 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 713 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 713 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 713 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 713 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 713 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 15250000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 15250000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 15250000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 15250000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 15250000 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 15250000 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.030299 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.030299 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.030299 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.030299 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.030299 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.030299 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 21388.499299 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 21388.499299 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 21388.499299 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 21388.499299 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 21388.499299 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 21388.499299 # average overall mshr miss latency -system.cpu2.branchPred.lookups 63667 # Number of BP lookups -system.cpu2.branchPred.condPredicted 55684 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 2455 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 55606 # Number of BTB lookups +system.cpu1.icache.writebacks::writebacks 556 # number of writebacks +system.cpu1.icache.writebacks::total 556 # number of writebacks +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 158 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 158 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 158 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 158 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 158 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 158 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 687 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 687 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 687 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 687 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 687 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 687 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 14723000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 14723000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 14723000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 14723000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 14723000 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 14723000 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.030974 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.030974 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.030974 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.030974 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.030974 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.030974 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 21430.858806 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 21430.858806 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 21430.858806 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 21430.858806 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 21430.858806 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 21430.858806 # average overall mshr miss latency +system.cpu2.branchPred.lookups 66096 # Number of BP lookups +system.cpu2.branchPred.condPredicted 57926 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 2486 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 57464 # Number of BTB lookups system.cpu2.branchPred.BTBHits 0 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu2.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 2018 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.usedRAS 2115 # Number of times the RAS was used to get a target. system.cpu2.branchPred.RASInCorrect 231 # Number of incorrect RAS predictions. -system.cpu2.branchPred.indirectLookups 55606 # Number of indirect predictor lookups. -system.cpu2.branchPred.indirectHits 44645 # Number of indirect target hits. -system.cpu2.branchPred.indirectMisses 10961 # Number of indirect misses. -system.cpu2.branchPredindirectMispredicted 1342 # Number of mispredicted indirect branches. -system.cpu2.pwrStateResidencyTicks::ON 124523000 # Cumulative time (in ticks) in various power states -system.cpu2.numCycles 193104 # number of cpu cycles simulated +system.cpu2.branchPred.indirectLookups 57464 # Number of indirect predictor lookups. +system.cpu2.branchPred.indirectHits 46751 # Number of indirect target hits. +system.cpu2.branchPred.indirectMisses 10713 # Number of indirect misses. +system.cpu2.branchPredindirectMispredicted 1349 # Number of mispredicted indirect branches. +system.cpu2.pwrStateResidencyTicks::ON 123936000 # Cumulative time (in ticks) in various power states +system.cpu2.numCycles 192112 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 40968 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 342539 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 63667 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 46663 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 146022 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 5067 # Number of cycles fetch has spent squashing +system.cpu2.fetch.icacheStallCycles 39817 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 356778 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 66096 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 48866 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 146191 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 5129 # Number of cycles fetch has spent squashing system.cpu2.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu2.fetch.NoActiveThreadStallCycles 10 # Number of stall cycles due to no active thread to fetch from -system.cpu2.fetch.PendingTrapStallCycles 1848 # Number of stall cycles due to pending traps -system.cpu2.fetch.IcacheWaitRetryStallCycles 13 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 29416 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 951 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.rateDist::samples 191398 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.789669 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.326327 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.PendingTrapStallCycles 1920 # Number of stall cycles due to pending traps +system.cpu2.fetch.IcacheWaitRetryStallCycles 3 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 28579 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 972 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.rateDist::samples 190509 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.872762 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.344982 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 76889 40.17% 40.17% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 56601 29.57% 69.74% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 8825 4.61% 74.36% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 3447 1.80% 76.16% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 694 0.36% 76.52% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 33672 17.59% 94.11% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 980 0.51% 94.62% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 1389 0.73% 95.35% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 8901 4.65% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 72004 37.80% 37.80% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 58377 30.64% 68.44% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 8422 4.42% 72.86% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 3406 1.79% 74.65% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 670 0.35% 75.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 36267 19.04% 94.04% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 1053 0.55% 94.59% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 1474 0.77% 95.36% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 8836 4.64% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 191398 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.329703 # Number of branch fetches per cycle -system.cpu2.fetch.rate 1.773858 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 22836 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 76803 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 84446 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 4770 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 2533 # Number of cycles decode is squashing -system.cpu2.decode.DecodedInsts 310490 # Number of instructions handled by decode -system.cpu2.rename.SquashCycles 2533 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 23870 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 37657 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 14813 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 85216 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 27299 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 303538 # Number of instructions processed by rename -system.cpu2.rename.IQFullEvents 23577 # Number of times rename has blocked due to IQ full +system.cpu2.fetch.rateDist::total 190509 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.344049 # Number of branch fetches per cycle +system.cpu2.fetch.rate 1.857135 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 22990 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 70899 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 89451 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 4595 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 2564 # Number of cycles decode is squashing +system.cpu2.decode.DecodedInsts 324452 # Number of instructions handled by decode +system.cpu2.rename.SquashCycles 2564 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 24019 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 34614 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 13407 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 89996 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 25899 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 317685 # Number of instructions processed by rename +system.cpu2.rename.IQFullEvents 22128 # Number of times rename has blocked due to IQ full system.cpu2.rename.LQFullEvents 16 # Number of times rename has blocked due to LQ full system.cpu2.rename.FullRegisterEvents 2 # Number of times there has been no free registers -system.cpu2.rename.RenamedOperands 211726 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 571973 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 446566 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 26 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 182781 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 28945 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 1674 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 1822 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 33085 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 82000 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 37987 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 39268 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 31634 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 245836 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 9182 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 247097 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 85 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 25038 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 19372 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 1244 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 191398 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 1.291011 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.381781 # Number of insts issued each cycle +system.cpu2.rename.RenamedOperands 221990 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 601950 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 469192 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 40 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 192480 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 29510 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 1686 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 1819 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 31415 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 86703 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 40578 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 41384 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 34173 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 258235 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 8782 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 258833 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 83 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 25653 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 20039 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 1265 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 190509 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 1.358639 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.384430 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 81765 42.72% 42.72% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 29268 15.29% 58.01% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 36754 19.20% 77.21% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 36522 19.08% 96.30% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 3555 1.86% 98.15% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 1723 0.90% 99.05% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 1061 0.55% 99.61% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 446 0.23% 99.84% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 304 0.16% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 76931 40.38% 40.38% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 28046 14.72% 55.10% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 39341 20.65% 75.75% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 39028 20.49% 96.24% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 3604 1.89% 98.13% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 1759 0.92% 99.06% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 1073 0.56% 99.62% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 444 0.23% 99.85% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 283 0.15% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 191398 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 190509 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 203 40.76% 40.76% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 0 0.00% 40.76% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 40.76% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 40.76% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 40.76% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 40.76% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 40.76% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 40.76% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 40.76% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 40.76% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 40.76% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 40.76% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 40.76% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 40.76% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 40.76% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 40.76% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 40.76% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 40.76% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 40.76% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 40.76% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 40.76% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 40.76% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 40.76% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 40.76% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 40.76% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 40.76% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 40.76% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 40.76% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 40.76% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 64 12.85% 53.61% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 231 46.39% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 204 42.15% 42.15% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 0 0.00% 42.15% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 42.15% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 42.15% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 42.15% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 42.15% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 42.15% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 42.15% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 42.15% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 42.15% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 42.15% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 42.15% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 42.15% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 42.15% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 42.15% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 42.15% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 42.15% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 42.15% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 42.15% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 42.15% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 42.15% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 42.15% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 42.15% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 42.15% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 42.15% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 42.15% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 42.15% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 42.15% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 42.15% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 51 10.54% 52.69% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 229 47.31% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 121951 49.35% 49.35% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 0 0.00% 49.35% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 49.35% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 49.35% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 49.35% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 49.35% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 49.35% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 49.35% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 49.35% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 49.35% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 49.35% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 49.35% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 49.35% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 49.35% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 49.35% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 49.35% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 49.35% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 49.35% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.35% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 49.35% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.35% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.35% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.35% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.35% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.35% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.35% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 49.35% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.35% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.35% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 88101 35.65% 85.01% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 37045 14.99% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 126867 49.02% 49.02% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 0 0.00% 49.02% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 49.02% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 49.02% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 49.02% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 49.02% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 49.02% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 49.02% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 49.02% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 49.02% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 49.02% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 49.02% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 49.02% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 49.02% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 49.02% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 49.02% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 49.02% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 49.02% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.02% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 49.02% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.02% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.02% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.02% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.02% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.02% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.02% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 49.02% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.02% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.02% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 92395 35.70% 84.71% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 39571 15.29% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 247097 # Type of FU issued -system.cpu2.iq.rate 1.279606 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 498 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.002015 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 686175 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 280041 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 243170 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.FU_type_0::total 258833 # Type of FU issued +system.cpu2.iq.rate 1.347303 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 484 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.001870 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 708742 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 292626 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 254835 # Number of integer instruction queue wakeup accesses system.cpu2.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 52 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_writes 80 # Number of floating instruction queue writes system.cpu2.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 247595 # Number of integer alu accesses +system.cpu2.iq.int_alu_accesses 259317 # Number of integer alu accesses system.cpu2.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 31591 # Number of loads that had data forwarded from stores +system.cpu2.iew.lsq.thread0.forwLoads 34129 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 4554 # Number of loads squashed +system.cpu2.iew.lsq.thread0.squashedLoads 4624 # Number of loads squashed system.cpu2.iew.lsq.thread0.ignoredResponses 33 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 37 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 2621 # Number of stores squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 36 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 2677 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu2.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu2.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 2533 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 10681 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 58 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 295617 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 336 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 82000 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 37987 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 1539 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewSquashCycles 2564 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 9290 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 55 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 309688 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 288 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 86703 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 40578 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 1561 # Number of dispatched non-speculative instructions system.cpu2.iew.iewIQFullEvents 34 # Number of times the IQ has become full, causing a stall system.cpu2.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 37 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 446 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 2642 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 3088 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 244561 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 80330 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 2536 # Number of squashed instructions skipped in execute +system.cpu2.iew.memOrderViolationEvents 36 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 443 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 2684 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 3127 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 256258 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 85016 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 2575 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 40599 # number of nop insts executed -system.cpu2.iew.exec_refs 117071 # number of memory reference insts executed -system.cpu2.iew.exec_branches 50931 # Number of branches executed -system.cpu2.iew.exec_stores 36741 # Number of stores executed -system.cpu2.iew.exec_rate 1.266473 # Inst execution rate -system.cpu2.iew.wb_sent 243660 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 243170 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 134852 # num instructions producing a value -system.cpu2.iew.wb_consumers 142392 # num instructions consuming a value -system.cpu2.iew.wb_rate 1.259270 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.947048 # average fanout of values written-back -system.cpu2.commit.commitSquashedInsts 26266 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 7938 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 2455 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 186363 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 1.445163 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 1.976076 # Number of insts commited each cycle +system.cpu2.iew.exec_nop 42671 # number of nop insts executed +system.cpu2.iew.exec_refs 124288 # number of memory reference insts executed +system.cpu2.iew.exec_branches 53042 # Number of branches executed +system.cpu2.iew.exec_stores 39272 # Number of stores executed +system.cpu2.iew.exec_rate 1.333899 # Inst execution rate +system.cpu2.iew.wb_sent 255341 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 254835 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 142252 # num instructions producing a value +system.cpu2.iew.wb_consumers 149928 # num instructions consuming a value +system.cpu2.iew.wb_rate 1.326492 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.948802 # average fanout of values written-back +system.cpu2.commit.commitSquashedInsts 26847 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 7517 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 2486 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 185379 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 1.525604 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 2.006612 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 89147 47.84% 47.84% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 47087 25.27% 73.10% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 5442 2.92% 76.02% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 8636 4.63% 80.66% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 1280 0.69% 81.34% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 31787 17.06% 98.40% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 722 0.39% 98.79% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 1037 0.56% 99.34% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 1225 0.66% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 83888 45.25% 45.25% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 49216 26.55% 71.80% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 5545 2.99% 74.79% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 8151 4.40% 79.19% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 1274 0.69% 79.88% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 34338 18.52% 98.40% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 700 0.38% 98.78% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 1066 0.58% 99.35% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 1201 0.65% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 186363 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 269325 # Number of instructions committed -system.cpu2.commit.committedOps 269325 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 185379 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 282815 # Number of instructions committed +system.cpu2.commit.committedOps 282815 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 112812 # Number of memory references committed -system.cpu2.commit.loads 77446 # Number of loads committed -system.cpu2.commit.membars 7225 # Number of memory barriers committed -system.cpu2.commit.branches 48554 # Number of branches committed +system.cpu2.commit.refs 119980 # Number of memory references committed +system.cpu2.commit.loads 82079 # Number of loads committed +system.cpu2.commit.membars 6800 # Number of memory barriers committed +system.cpu2.commit.branches 50664 # Number of branches committed system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 183489 # Number of committed integer instructions. +system.cpu2.commit.int_insts 192763 # Number of committed integer instructions. system.cpu2.commit.function_calls 322 # Number of function calls committed. -system.cpu2.commit.op_class_0::No_OpClass 39345 14.61% 14.61% # Class of committed instruction -system.cpu2.commit.op_class_0::IntAlu 109943 40.82% 55.43% # Class of committed instruction -system.cpu2.commit.op_class_0::IntMult 0 0.00% 55.43% # Class of committed instruction -system.cpu2.commit.op_class_0::IntDiv 0 0.00% 55.43% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 55.43% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 55.43% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 55.43% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatMult 0 0.00% 55.43% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 55.43% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 55.43% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 55.43% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 55.43% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 55.43% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 55.43% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 55.43% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 55.43% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMult 0 0.00% 55.43% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 55.43% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShift 0 0.00% 55.43% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 55.43% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 55.43% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 55.43% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 55.43% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 55.43% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 55.43% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 55.43% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 55.43% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 55.43% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 55.43% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 55.43% # Class of committed instruction -system.cpu2.commit.op_class_0::MemRead 84671 31.44% 86.87% # Class of committed instruction -system.cpu2.commit.op_class_0::MemWrite 35366 13.13% 100.00% # Class of committed instruction +system.cpu2.commit.op_class_0::No_OpClass 41451 14.66% 14.66% # Class of committed instruction +system.cpu2.commit.op_class_0::IntAlu 114584 40.52% 55.17% # Class of committed instruction +system.cpu2.commit.op_class_0::IntMult 0 0.00% 55.17% # Class of committed instruction +system.cpu2.commit.op_class_0::IntDiv 0 0.00% 55.17% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 55.17% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 55.17% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 55.17% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatMult 0 0.00% 55.17% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 55.17% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 55.17% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 55.17% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 55.17% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 55.17% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 55.17% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 55.17% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 55.17% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMult 0 0.00% 55.17% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 55.17% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShift 0 0.00% 55.17% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 55.17% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 55.17% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 55.17% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 55.17% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 55.17% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 55.17% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 55.17% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 55.17% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 55.17% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 55.17% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 55.17% # Class of committed instruction +system.cpu2.commit.op_class_0::MemRead 88879 31.43% 86.60% # Class of committed instruction +system.cpu2.commit.op_class_0::MemWrite 37901 13.40% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu2.commit.op_class_0::total 269325 # Class of committed instruction -system.cpu2.commit.bw_lim_events 1225 # number cycles where commit BW limit reached -system.cpu2.rob.rob_reads 480143 # The number of ROB reads -system.cpu2.rob.rob_writes 596277 # The number of ROB writes -system.cpu2.timesIdled 226 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 1706 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.commit.op_class_0::total 282815 # Class of committed instruction +system.cpu2.commit.bw_lim_events 1201 # number cycles where commit BW limit reached +system.cpu2.rob.rob_reads 493254 # The number of ROB reads +system.cpu2.rob.rob_writes 624500 # The number of ROB writes +system.cpu2.timesIdled 220 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 1603 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu2.quiesceCycles 47823 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 222755 # Number of Instructions Simulated -system.cpu2.committedOps 222755 # Number of Ops (including micro ops) Simulated -system.cpu2.cpi 0.866890 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 0.866890 # CPI: Total CPI of All Threads -system.cpu2.ipc 1.153549 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 1.153549 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 415553 # number of integer regfile reads -system.cpu2.int_regfile_writes 194388 # number of integer regfile writes +system.cpu2.committedInsts 234564 # Number of Instructions Simulated +system.cpu2.committedOps 234564 # Number of Ops (including micro ops) Simulated +system.cpu2.cpi 0.819017 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 0.819017 # CPI: Total CPI of All Threads +system.cpu2.ipc 1.220975 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 1.220975 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 437605 # number of integer regfile reads +system.cpu2.int_regfile_writes 204427 # number of integer regfile writes system.cpu2.fp_regfile_writes 64 # number of floating regfile writes -system.cpu2.misc_regfile_reads 119022 # number of misc regfile reads +system.cpu2.misc_regfile_reads 126238 # number of misc regfile reads system.cpu2.misc_regfile_writes 648 # number of misc regfile writes -system.cpu2.dcache.tags.pwrStateResidencyTicks::UNDEFINED 124523000 # Cumulative time (in ticks) in various power states +system.cpu2.dcache.tags.pwrStateResidencyTicks::UNDEFINED 123936000 # Cumulative time (in ticks) in various power states system.cpu2.dcache.tags.replacements 0 # number of replacements -system.cpu2.dcache.tags.tagsinuse 25.641689 # Cycle average of tags in use -system.cpu2.dcache.tags.total_refs 42500 # Total number of references to valid blocks. +system.cpu2.dcache.tags.tagsinuse 26.114184 # Cycle average of tags in use +system.cpu2.dcache.tags.total_refs 45075 # Total number of references to valid blocks. system.cpu2.dcache.tags.sampled_refs 30 # Sample count of references to valid blocks. -system.cpu2.dcache.tags.avg_refs 1416.666667 # Average number of references to valid blocks. +system.cpu2.dcache.tags.avg_refs 1502.500000 # Average number of references to valid blocks. system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.dcache.tags.occ_blocks::cpu2.data 25.641689 # Average occupied blocks per requestor -system.cpu2.dcache.tags.occ_percent::cpu2.data 0.050081 # Average percentage of cache occupancy -system.cpu2.dcache.tags.occ_percent::total 0.050081 # Average percentage of cache occupancy +system.cpu2.dcache.tags.occ_blocks::cpu2.data 26.114184 # Average occupied blocks per requestor +system.cpu2.dcache.tags.occ_percent::cpu2.data 0.051004 # Average percentage of cache occupancy +system.cpu2.dcache.tags.occ_percent::total 0.051004 # Average percentage of cache occupancy system.cpu2.dcache.tags.occ_task_id_blocks::1024 30 # Occupied blocks per task id -system.cpu2.dcache.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id -system.cpu2.dcache.tags.age_task_id_blocks_1024::1 25 # Occupied blocks per task id -system.cpu2.dcache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id +system.cpu2.dcache.tags.age_task_id_blocks_1024::1 30 # Occupied blocks per task id system.cpu2.dcache.tags.occ_task_id_percent::1024 0.058594 # Percentage of cache occupancy per task id -system.cpu2.dcache.tags.tag_accesses 336580 # Number of tag accesses -system.cpu2.dcache.tags.data_accesses 336580 # Number of data accesses -system.cpu2.dcache.pwrStateResidencyTicks::UNDEFINED 124523000 # Cumulative time (in ticks) in various power states -system.cpu2.dcache.ReadReq_hits::cpu2.data 48215 # number of ReadReq hits -system.cpu2.dcache.ReadReq_hits::total 48215 # number of ReadReq hits -system.cpu2.dcache.WriteReq_hits::cpu2.data 35154 # number of WriteReq hits -system.cpu2.dcache.WriteReq_hits::total 35154 # number of WriteReq hits +system.cpu2.dcache.tags.tag_accesses 355312 # Number of tag accesses +system.cpu2.dcache.tags.data_accesses 355312 # Number of data accesses +system.cpu2.dcache.pwrStateResidencyTicks::UNDEFINED 123936000 # Cumulative time (in ticks) in various power states +system.cpu2.dcache.ReadReq_hits::cpu2.data 50364 # number of ReadReq hits +system.cpu2.dcache.ReadReq_hits::total 50364 # number of ReadReq hits +system.cpu2.dcache.WriteReq_hits::cpu2.data 37691 # number of WriteReq hits +system.cpu2.dcache.WriteReq_hits::total 37691 # number of WriteReq hits system.cpu2.dcache.SwapReq_hits::cpu2.data 13 # number of SwapReq hits system.cpu2.dcache.SwapReq_hits::total 13 # number of SwapReq hits -system.cpu2.dcache.demand_hits::cpu2.data 83369 # number of demand (read+write) hits -system.cpu2.dcache.demand_hits::total 83369 # number of demand (read+write) hits -system.cpu2.dcache.overall_hits::cpu2.data 83369 # number of overall hits -system.cpu2.dcache.overall_hits::total 83369 # number of overall hits -system.cpu2.dcache.ReadReq_misses::cpu2.data 500 # number of ReadReq misses -system.cpu2.dcache.ReadReq_misses::total 500 # number of ReadReq misses -system.cpu2.dcache.WriteReq_misses::cpu2.data 145 # number of WriteReq misses -system.cpu2.dcache.WriteReq_misses::total 145 # number of WriteReq misses -system.cpu2.dcache.SwapReq_misses::cpu2.data 54 # number of SwapReq misses -system.cpu2.dcache.SwapReq_misses::total 54 # number of SwapReq misses -system.cpu2.dcache.demand_misses::cpu2.data 645 # number of demand (read+write) misses -system.cpu2.dcache.demand_misses::total 645 # number of demand (read+write) misses -system.cpu2.dcache.overall_misses::cpu2.data 645 # number of overall misses -system.cpu2.dcache.overall_misses::total 645 # number of overall misses -system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 8163500 # number of ReadReq miss cycles -system.cpu2.dcache.ReadReq_miss_latency::total 8163500 # number of ReadReq miss cycles -system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 3144500 # number of WriteReq miss cycles -system.cpu2.dcache.WriteReq_miss_latency::total 3144500 # number of WriteReq miss cycles -system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 806000 # number of SwapReq miss cycles -system.cpu2.dcache.SwapReq_miss_latency::total 806000 # number of SwapReq miss cycles -system.cpu2.dcache.demand_miss_latency::cpu2.data 11308000 # number of demand (read+write) miss cycles -system.cpu2.dcache.demand_miss_latency::total 11308000 # number of demand (read+write) miss cycles -system.cpu2.dcache.overall_miss_latency::cpu2.data 11308000 # number of overall miss cycles -system.cpu2.dcache.overall_miss_latency::total 11308000 # number of overall miss cycles -system.cpu2.dcache.ReadReq_accesses::cpu2.data 48715 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.ReadReq_accesses::total 48715 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_accesses::cpu2.data 35299 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_accesses::total 35299 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.SwapReq_accesses::cpu2.data 67 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.SwapReq_accesses::total 67 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.demand_accesses::cpu2.data 84014 # number of demand (read+write) accesses -system.cpu2.dcache.demand_accesses::total 84014 # number of demand (read+write) accesses -system.cpu2.dcache.overall_accesses::cpu2.data 84014 # number of overall (read+write) accesses -system.cpu2.dcache.overall_accesses::total 84014 # number of overall (read+write) accesses -system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.010264 # miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_miss_rate::total 0.010264 # miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.004108 # miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_miss_rate::total 0.004108 # miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.805970 # miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_miss_rate::total 0.805970 # miss rate for SwapReq accesses -system.cpu2.dcache.demand_miss_rate::cpu2.data 0.007677 # miss rate for demand accesses -system.cpu2.dcache.demand_miss_rate::total 0.007677 # miss rate for demand accesses -system.cpu2.dcache.overall_miss_rate::cpu2.data 0.007677 # miss rate for overall accesses -system.cpu2.dcache.overall_miss_rate::total 0.007677 # miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 16327 # average ReadReq miss latency -system.cpu2.dcache.ReadReq_avg_miss_latency::total 16327 # average ReadReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 21686.206897 # average WriteReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency::total 21686.206897 # average WriteReq miss latency -system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 14925.925926 # average SwapReq miss latency -system.cpu2.dcache.SwapReq_avg_miss_latency::total 14925.925926 # average SwapReq miss latency -system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 17531.782946 # average overall miss latency -system.cpu2.dcache.demand_avg_miss_latency::total 17531.782946 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 17531.782946 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::total 17531.782946 # average overall miss latency +system.cpu2.dcache.demand_hits::cpu2.data 88055 # number of demand (read+write) hits +system.cpu2.dcache.demand_hits::total 88055 # number of demand (read+write) hits +system.cpu2.dcache.overall_hits::cpu2.data 88055 # number of overall hits +system.cpu2.dcache.overall_hits::total 88055 # number of overall hits +system.cpu2.dcache.ReadReq_misses::cpu2.data 498 # number of ReadReq misses +system.cpu2.dcache.ReadReq_misses::total 498 # number of ReadReq misses +system.cpu2.dcache.WriteReq_misses::cpu2.data 139 # number of WriteReq misses +system.cpu2.dcache.WriteReq_misses::total 139 # number of WriteReq misses +system.cpu2.dcache.SwapReq_misses::cpu2.data 58 # number of SwapReq misses +system.cpu2.dcache.SwapReq_misses::total 58 # number of SwapReq misses +system.cpu2.dcache.demand_misses::cpu2.data 637 # number of demand (read+write) misses +system.cpu2.dcache.demand_misses::total 637 # number of demand (read+write) misses +system.cpu2.dcache.overall_misses::cpu2.data 637 # number of overall misses +system.cpu2.dcache.overall_misses::total 637 # number of overall misses +system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 3990000 # number of ReadReq miss cycles +system.cpu2.dcache.ReadReq_miss_latency::total 3990000 # number of ReadReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 2835500 # number of WriteReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::total 2835500 # number of WriteReq miss cycles +system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 366500 # number of SwapReq miss cycles +system.cpu2.dcache.SwapReq_miss_latency::total 366500 # number of SwapReq miss cycles +system.cpu2.dcache.demand_miss_latency::cpu2.data 6825500 # number of demand (read+write) miss cycles +system.cpu2.dcache.demand_miss_latency::total 6825500 # number of demand (read+write) miss cycles +system.cpu2.dcache.overall_miss_latency::cpu2.data 6825500 # number of overall miss cycles +system.cpu2.dcache.overall_miss_latency::total 6825500 # number of overall miss cycles +system.cpu2.dcache.ReadReq_accesses::cpu2.data 50862 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.ReadReq_accesses::total 50862 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses::cpu2.data 37830 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses::total 37830 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.SwapReq_accesses::cpu2.data 71 # number of SwapReq accesses(hits+misses) +system.cpu2.dcache.SwapReq_accesses::total 71 # number of SwapReq accesses(hits+misses) +system.cpu2.dcache.demand_accesses::cpu2.data 88692 # number of demand (read+write) accesses +system.cpu2.dcache.demand_accesses::total 88692 # number of demand (read+write) accesses +system.cpu2.dcache.overall_accesses::cpu2.data 88692 # number of overall (read+write) accesses +system.cpu2.dcache.overall_accesses::total 88692 # number of overall (read+write) accesses +system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.009791 # miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_miss_rate::total 0.009791 # miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.003674 # miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_miss_rate::total 0.003674 # miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.816901 # miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_miss_rate::total 0.816901 # miss rate for SwapReq accesses +system.cpu2.dcache.demand_miss_rate::cpu2.data 0.007182 # miss rate for demand accesses +system.cpu2.dcache.demand_miss_rate::total 0.007182 # miss rate for demand accesses +system.cpu2.dcache.overall_miss_rate::cpu2.data 0.007182 # miss rate for overall accesses +system.cpu2.dcache.overall_miss_rate::total 0.007182 # miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 8012.048193 # average ReadReq miss latency +system.cpu2.dcache.ReadReq_avg_miss_latency::total 8012.048193 # average ReadReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 20399.280576 # average WriteReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::total 20399.280576 # average WriteReq miss latency +system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 6318.965517 # average SwapReq miss latency +system.cpu2.dcache.SwapReq_avg_miss_latency::total 6318.965517 # average SwapReq miss latency +system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 10715.070644 # average overall miss latency +system.cpu2.dcache.demand_avg_miss_latency::total 10715.070644 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 10715.070644 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::total 10715.070644 # average overall miss latency system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 338 # number of ReadReq MSHR hits -system.cpu2.dcache.ReadReq_mshr_hits::total 338 # number of ReadReq MSHR hits -system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 39 # number of WriteReq MSHR hits -system.cpu2.dcache.WriteReq_mshr_hits::total 39 # number of WriteReq MSHR hits -system.cpu2.dcache.SwapReq_mshr_hits::cpu2.data 2 # number of SwapReq MSHR hits -system.cpu2.dcache.SwapReq_mshr_hits::total 2 # number of SwapReq MSHR hits -system.cpu2.dcache.demand_mshr_hits::cpu2.data 377 # number of demand (read+write) MSHR hits -system.cpu2.dcache.demand_mshr_hits::total 377 # number of demand (read+write) MSHR hits -system.cpu2.dcache.overall_mshr_hits::cpu2.data 377 # number of overall MSHR hits -system.cpu2.dcache.overall_mshr_hits::total 377 # number of overall MSHR hits -system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 162 # number of ReadReq MSHR misses -system.cpu2.dcache.ReadReq_mshr_misses::total 162 # number of ReadReq MSHR misses -system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 106 # number of WriteReq MSHR misses -system.cpu2.dcache.WriteReq_mshr_misses::total 106 # number of WriteReq MSHR misses -system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 52 # number of SwapReq MSHR misses -system.cpu2.dcache.SwapReq_mshr_misses::total 52 # number of SwapReq MSHR misses -system.cpu2.dcache.demand_mshr_misses::cpu2.data 268 # number of demand (read+write) MSHR misses -system.cpu2.dcache.demand_mshr_misses::total 268 # number of demand (read+write) MSHR misses -system.cpu2.dcache.overall_mshr_misses::cpu2.data 268 # number of overall MSHR misses -system.cpu2.dcache.overall_mshr_misses::total 268 # number of overall MSHR misses -system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1730500 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1730500 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1679500 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1679500 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 752000 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency::total 752000 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3410000 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::total 3410000 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3410000 # number of overall MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::total 3410000 # number of overall MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003325 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003325 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.003003 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.003003 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.776119 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.776119 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.003190 # mshr miss rate for demand accesses -system.cpu2.dcache.demand_mshr_miss_rate::total 0.003190 # mshr miss rate for demand accesses -system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.003190 # mshr miss rate for overall accesses -system.cpu2.dcache.overall_mshr_miss_rate::total 0.003190 # mshr miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 10682.098765 # average ReadReq mshr miss latency -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 10682.098765 # average ReadReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 15844.339623 # average WriteReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 15844.339623 # average WriteReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 14461.538462 # average SwapReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 14461.538462 # average SwapReq mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 12723.880597 # average overall mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::total 12723.880597 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 12723.880597 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::total 12723.880597 # average overall mshr miss latency -system.cpu2.icache.tags.pwrStateResidencyTicks::UNDEFINED 124523000 # Cumulative time (in ticks) in various power states -system.cpu2.icache.tags.replacements 598 # number of replacements -system.cpu2.icache.tags.tagsinuse 95.853337 # Cycle average of tags in use -system.cpu2.icache.tags.total_refs 28564 # Total number of references to valid blocks. -system.cpu2.icache.tags.sampled_refs 733 # Sample count of references to valid blocks. -system.cpu2.icache.tags.avg_refs 38.968622 # Average number of references to valid blocks. +system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 331 # number of ReadReq MSHR hits +system.cpu2.dcache.ReadReq_mshr_hits::total 331 # number of ReadReq MSHR hits +system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 34 # number of WriteReq MSHR hits +system.cpu2.dcache.WriteReq_mshr_hits::total 34 # number of WriteReq MSHR hits +system.cpu2.dcache.demand_mshr_hits::cpu2.data 365 # number of demand (read+write) MSHR hits +system.cpu2.dcache.demand_mshr_hits::total 365 # number of demand (read+write) MSHR hits +system.cpu2.dcache.overall_mshr_hits::cpu2.data 365 # number of overall MSHR hits +system.cpu2.dcache.overall_mshr_hits::total 365 # number of overall MSHR hits +system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 167 # number of ReadReq MSHR misses +system.cpu2.dcache.ReadReq_mshr_misses::total 167 # number of ReadReq MSHR misses +system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 105 # number of WriteReq MSHR misses +system.cpu2.dcache.WriteReq_mshr_misses::total 105 # number of WriteReq MSHR misses +system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 58 # number of SwapReq MSHR misses +system.cpu2.dcache.SwapReq_mshr_misses::total 58 # number of SwapReq MSHR misses +system.cpu2.dcache.demand_mshr_misses::cpu2.data 272 # number of demand (read+write) MSHR misses +system.cpu2.dcache.demand_mshr_misses::total 272 # number of demand (read+write) MSHR misses +system.cpu2.dcache.overall_mshr_misses::cpu2.data 272 # number of overall MSHR misses +system.cpu2.dcache.overall_mshr_misses::total 272 # number of overall MSHR misses +system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1193000 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1193000 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1388000 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1388000 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 308500 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::total 308500 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 2581000 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::total 2581000 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 2581000 # number of overall MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::total 2581000 # number of overall MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003283 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003283 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.002776 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.002776 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.816901 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.816901 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.003067 # mshr miss rate for demand accesses +system.cpu2.dcache.demand_mshr_miss_rate::total 0.003067 # mshr miss rate for demand accesses +system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.003067 # mshr miss rate for overall accesses +system.cpu2.dcache.overall_mshr_miss_rate::total 0.003067 # mshr miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 7143.712575 # average ReadReq mshr miss latency +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 7143.712575 # average ReadReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 13219.047619 # average WriteReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 13219.047619 # average WriteReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 5318.965517 # average SwapReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 5318.965517 # average SwapReq mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 9488.970588 # average overall mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::total 9488.970588 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 9488.970588 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::total 9488.970588 # average overall mshr miss latency +system.cpu2.icache.tags.pwrStateResidencyTicks::UNDEFINED 123936000 # Cumulative time (in ticks) in various power states +system.cpu2.icache.tags.replacements 578 # number of replacements +system.cpu2.icache.tags.tagsinuse 95.404705 # Cycle average of tags in use +system.cpu2.icache.tags.total_refs 27742 # Total number of references to valid blocks. +system.cpu2.icache.tags.sampled_refs 710 # Sample count of references to valid blocks. +system.cpu2.icache.tags.avg_refs 39.073239 # Average number of references to valid blocks. system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.icache.tags.occ_blocks::cpu2.inst 95.853337 # Average occupied blocks per requestor -system.cpu2.icache.tags.occ_percent::cpu2.inst 0.187214 # Average percentage of cache occupancy -system.cpu2.icache.tags.occ_percent::total 0.187214 # Average percentage of cache occupancy -system.cpu2.icache.tags.occ_task_id_blocks::1024 135 # Occupied blocks per task id -system.cpu2.icache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id -system.cpu2.icache.tags.age_task_id_blocks_1024::1 105 # Occupied blocks per task id -system.cpu2.icache.tags.age_task_id_blocks_1024::2 11 # Occupied blocks per task id -system.cpu2.icache.tags.occ_task_id_percent::1024 0.263672 # Percentage of cache occupancy per task id -system.cpu2.icache.tags.tag_accesses 30149 # Number of tag accesses -system.cpu2.icache.tags.data_accesses 30149 # Number of data accesses -system.cpu2.icache.pwrStateResidencyTicks::UNDEFINED 124523000 # Cumulative time (in ticks) in various power states -system.cpu2.icache.ReadReq_hits::cpu2.inst 28564 # number of ReadReq hits -system.cpu2.icache.ReadReq_hits::total 28564 # number of ReadReq hits -system.cpu2.icache.demand_hits::cpu2.inst 28564 # number of demand (read+write) hits -system.cpu2.icache.demand_hits::total 28564 # number of demand (read+write) hits -system.cpu2.icache.overall_hits::cpu2.inst 28564 # number of overall hits -system.cpu2.icache.overall_hits::total 28564 # number of overall hits -system.cpu2.icache.ReadReq_misses::cpu2.inst 852 # number of ReadReq misses -system.cpu2.icache.ReadReq_misses::total 852 # number of ReadReq misses -system.cpu2.icache.demand_misses::cpu2.inst 852 # number of demand (read+write) misses -system.cpu2.icache.demand_misses::total 852 # number of demand (read+write) misses -system.cpu2.icache.overall_misses::cpu2.inst 852 # number of overall misses -system.cpu2.icache.overall_misses::total 852 # number of overall misses -system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 12789500 # number of ReadReq miss cycles -system.cpu2.icache.ReadReq_miss_latency::total 12789500 # number of ReadReq miss cycles -system.cpu2.icache.demand_miss_latency::cpu2.inst 12789500 # number of demand (read+write) miss cycles -system.cpu2.icache.demand_miss_latency::total 12789500 # number of demand (read+write) miss cycles -system.cpu2.icache.overall_miss_latency::cpu2.inst 12789500 # number of overall miss cycles -system.cpu2.icache.overall_miss_latency::total 12789500 # number of overall miss cycles -system.cpu2.icache.ReadReq_accesses::cpu2.inst 29416 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.ReadReq_accesses::total 29416 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.demand_accesses::cpu2.inst 29416 # number of demand (read+write) accesses -system.cpu2.icache.demand_accesses::total 29416 # number of demand (read+write) accesses -system.cpu2.icache.overall_accesses::cpu2.inst 29416 # number of overall (read+write) accesses -system.cpu2.icache.overall_accesses::total 29416 # number of overall (read+write) accesses -system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.028964 # miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_miss_rate::total 0.028964 # miss rate for ReadReq accesses -system.cpu2.icache.demand_miss_rate::cpu2.inst 0.028964 # miss rate for demand accesses -system.cpu2.icache.demand_miss_rate::total 0.028964 # miss rate for demand accesses -system.cpu2.icache.overall_miss_rate::cpu2.inst 0.028964 # miss rate for overall accesses -system.cpu2.icache.overall_miss_rate::total 0.028964 # miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 15011.150235 # average ReadReq miss latency -system.cpu2.icache.ReadReq_avg_miss_latency::total 15011.150235 # average ReadReq miss latency -system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 15011.150235 # average overall miss latency -system.cpu2.icache.demand_avg_miss_latency::total 15011.150235 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 15011.150235 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::total 15011.150235 # average overall miss latency -system.cpu2.icache.blocked_cycles::no_mshrs 111 # number of cycles access was blocked +system.cpu2.icache.tags.occ_blocks::cpu2.inst 95.404705 # Average occupied blocks per requestor +system.cpu2.icache.tags.occ_percent::cpu2.inst 0.186337 # Average percentage of cache occupancy +system.cpu2.icache.tags.occ_percent::total 0.186337 # Average percentage of cache occupancy +system.cpu2.icache.tags.occ_task_id_blocks::1024 132 # Occupied blocks per task id +system.cpu2.icache.tags.age_task_id_blocks_1024::0 13 # Occupied blocks per task id +system.cpu2.icache.tags.age_task_id_blocks_1024::1 119 # Occupied blocks per task id +system.cpu2.icache.tags.occ_task_id_percent::1024 0.257812 # Percentage of cache occupancy per task id +system.cpu2.icache.tags.tag_accesses 29289 # Number of tag accesses +system.cpu2.icache.tags.data_accesses 29289 # Number of data accesses +system.cpu2.icache.pwrStateResidencyTicks::UNDEFINED 123936000 # Cumulative time (in ticks) in various power states +system.cpu2.icache.ReadReq_hits::cpu2.inst 27742 # number of ReadReq hits +system.cpu2.icache.ReadReq_hits::total 27742 # number of ReadReq hits +system.cpu2.icache.demand_hits::cpu2.inst 27742 # number of demand (read+write) hits +system.cpu2.icache.demand_hits::total 27742 # number of demand (read+write) hits +system.cpu2.icache.overall_hits::cpu2.inst 27742 # number of overall hits +system.cpu2.icache.overall_hits::total 27742 # number of overall hits +system.cpu2.icache.ReadReq_misses::cpu2.inst 837 # number of ReadReq misses +system.cpu2.icache.ReadReq_misses::total 837 # number of ReadReq misses +system.cpu2.icache.demand_misses::cpu2.inst 837 # number of demand (read+write) misses +system.cpu2.icache.demand_misses::total 837 # number of demand (read+write) misses +system.cpu2.icache.overall_misses::cpu2.inst 837 # number of overall misses +system.cpu2.icache.overall_misses::total 837 # number of overall misses +system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 12852000 # number of ReadReq miss cycles +system.cpu2.icache.ReadReq_miss_latency::total 12852000 # number of ReadReq miss cycles +system.cpu2.icache.demand_miss_latency::cpu2.inst 12852000 # number of demand (read+write) miss cycles +system.cpu2.icache.demand_miss_latency::total 12852000 # number of demand (read+write) miss cycles +system.cpu2.icache.overall_miss_latency::cpu2.inst 12852000 # number of overall miss cycles +system.cpu2.icache.overall_miss_latency::total 12852000 # number of overall miss cycles +system.cpu2.icache.ReadReq_accesses::cpu2.inst 28579 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.ReadReq_accesses::total 28579 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.demand_accesses::cpu2.inst 28579 # number of demand (read+write) accesses +system.cpu2.icache.demand_accesses::total 28579 # number of demand (read+write) accesses +system.cpu2.icache.overall_accesses::cpu2.inst 28579 # number of overall (read+write) accesses +system.cpu2.icache.overall_accesses::total 28579 # number of overall (read+write) accesses +system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.029287 # miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_miss_rate::total 0.029287 # miss rate for ReadReq accesses +system.cpu2.icache.demand_miss_rate::cpu2.inst 0.029287 # miss rate for demand accesses +system.cpu2.icache.demand_miss_rate::total 0.029287 # miss rate for demand accesses +system.cpu2.icache.overall_miss_rate::cpu2.inst 0.029287 # miss rate for overall accesses +system.cpu2.icache.overall_miss_rate::total 0.029287 # miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 15354.838710 # average ReadReq miss latency +system.cpu2.icache.ReadReq_avg_miss_latency::total 15354.838710 # average ReadReq miss latency +system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 15354.838710 # average overall miss latency +system.cpu2.icache.demand_avg_miss_latency::total 15354.838710 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 15354.838710 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::total 15354.838710 # average overall miss latency +system.cpu2.icache.blocked_cycles::no_mshrs 69 # number of cycles access was blocked system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu2.icache.blocked::no_mshrs 5 # number of cycles access was blocked +system.cpu2.icache.blocked::no_mshrs 3 # number of cycles access was blocked system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu2.icache.avg_blocked_cycles::no_mshrs 22.200000 # average number of cycles each access was blocked +system.cpu2.icache.avg_blocked_cycles::no_mshrs 23 # average number of cycles each access was blocked system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu2.icache.writebacks::writebacks 598 # number of writebacks -system.cpu2.icache.writebacks::total 598 # number of writebacks -system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst 119 # number of ReadReq MSHR hits -system.cpu2.icache.ReadReq_mshr_hits::total 119 # number of ReadReq MSHR hits -system.cpu2.icache.demand_mshr_hits::cpu2.inst 119 # number of demand (read+write) MSHR hits -system.cpu2.icache.demand_mshr_hits::total 119 # number of demand (read+write) MSHR hits -system.cpu2.icache.overall_mshr_hits::cpu2.inst 119 # number of overall MSHR hits -system.cpu2.icache.overall_mshr_hits::total 119 # number of overall MSHR hits -system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 733 # number of ReadReq MSHR misses -system.cpu2.icache.ReadReq_mshr_misses::total 733 # number of ReadReq MSHR misses -system.cpu2.icache.demand_mshr_misses::cpu2.inst 733 # number of demand (read+write) MSHR misses -system.cpu2.icache.demand_mshr_misses::total 733 # number of demand (read+write) MSHR misses -system.cpu2.icache.overall_mshr_misses::cpu2.inst 733 # number of overall MSHR misses -system.cpu2.icache.overall_mshr_misses::total 733 # number of overall MSHR misses -system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 10899500 # number of ReadReq MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_latency::total 10899500 # number of ReadReq MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 10899500 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::total 10899500 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 10899500 # number of overall MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::total 10899500 # number of overall MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.024918 # mshr miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.024918 # mshr miss rate for ReadReq accesses -system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.024918 # mshr miss rate for demand accesses -system.cpu2.icache.demand_mshr_miss_rate::total 0.024918 # mshr miss rate for demand accesses -system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.024918 # mshr miss rate for overall accesses -system.cpu2.icache.overall_mshr_miss_rate::total 0.024918 # mshr miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 14869.713506 # average ReadReq mshr miss latency -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 14869.713506 # average ReadReq mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 14869.713506 # average overall mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::total 14869.713506 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 14869.713506 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::total 14869.713506 # average overall mshr miss latency -system.cpu3.branchPred.lookups 61800 # Number of BP lookups -system.cpu3.branchPred.condPredicted 53939 # Number of conditional branches predicted -system.cpu3.branchPred.condIncorrect 2339 # Number of conditional branches incorrect -system.cpu3.branchPred.BTBLookups 53501 # Number of BTB lookups +system.cpu2.icache.writebacks::writebacks 578 # number of writebacks +system.cpu2.icache.writebacks::total 578 # number of writebacks +system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst 127 # number of ReadReq MSHR hits +system.cpu2.icache.ReadReq_mshr_hits::total 127 # number of ReadReq MSHR hits +system.cpu2.icache.demand_mshr_hits::cpu2.inst 127 # number of demand (read+write) MSHR hits +system.cpu2.icache.demand_mshr_hits::total 127 # number of demand (read+write) MSHR hits +system.cpu2.icache.overall_mshr_hits::cpu2.inst 127 # number of overall MSHR hits +system.cpu2.icache.overall_mshr_hits::total 127 # number of overall MSHR hits +system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 710 # number of ReadReq MSHR misses +system.cpu2.icache.ReadReq_mshr_misses::total 710 # number of ReadReq MSHR misses +system.cpu2.icache.demand_mshr_misses::cpu2.inst 710 # number of demand (read+write) MSHR misses +system.cpu2.icache.demand_mshr_misses::total 710 # number of demand (read+write) MSHR misses +system.cpu2.icache.overall_mshr_misses::cpu2.inst 710 # number of overall MSHR misses +system.cpu2.icache.overall_mshr_misses::total 710 # number of overall MSHR misses +system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 10853000 # number of ReadReq MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_latency::total 10853000 # number of ReadReq MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 10853000 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::total 10853000 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 10853000 # number of overall MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::total 10853000 # number of overall MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.024843 # mshr miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.024843 # mshr miss rate for ReadReq accesses +system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.024843 # mshr miss rate for demand accesses +system.cpu2.icache.demand_mshr_miss_rate::total 0.024843 # mshr miss rate for demand accesses +system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.024843 # mshr miss rate for overall accesses +system.cpu2.icache.overall_mshr_miss_rate::total 0.024843 # mshr miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 15285.915493 # average ReadReq mshr miss latency +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 15285.915493 # average ReadReq mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 15285.915493 # average overall mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::total 15285.915493 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 15285.915493 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::total 15285.915493 # average overall mshr miss latency +system.cpu3.branchPred.lookups 58058 # Number of BP lookups +system.cpu3.branchPred.condPredicted 50256 # Number of conditional branches predicted +system.cpu3.branchPred.condIncorrect 2406 # Number of conditional branches incorrect +system.cpu3.branchPred.BTBLookups 50211 # Number of BTB lookups system.cpu3.branchPred.BTBHits 0 # Number of BTB hits system.cpu3.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu3.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage -system.cpu3.branchPred.usedRAS 1989 # Number of times the RAS was used to get a target. +system.cpu3.branchPred.usedRAS 1984 # Number of times the RAS was used to get a target. system.cpu3.branchPred.RASInCorrect 231 # Number of incorrect RAS predictions. -system.cpu3.branchPred.indirectLookups 53501 # Number of indirect predictor lookups. -system.cpu3.branchPred.indirectHits 43109 # Number of indirect target hits. -system.cpu3.branchPred.indirectMisses 10392 # Number of indirect misses. -system.cpu3.branchPredindirectMispredicted 1225 # Number of mispredicted indirect branches. -system.cpu3.pwrStateResidencyTicks::ON 124523000 # Cumulative time (in ticks) in various power states -system.cpu3.numCycles 192748 # number of cpu cycles simulated +system.cpu3.branchPred.indirectLookups 50211 # Number of indirect predictor lookups. +system.cpu3.branchPred.indirectHits 39339 # Number of indirect target hits. +system.cpu3.branchPred.indirectMisses 10872 # Number of indirect misses. +system.cpu3.branchPredindirectMispredicted 1290 # Number of mispredicted indirect branches. +system.cpu3.pwrStateResidencyTicks::ON 123936000 # Cumulative time (in ticks) in various power states +system.cpu3.numCycles 191755 # number of cpu cycles simulated system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu3.fetch.icacheStallCycles 41262 # Number of cycles fetch is stalled on an Icache miss -system.cpu3.fetch.Insts 329189 # Number of instructions fetch has processed -system.cpu3.fetch.Branches 61800 # Number of branches that fetch encountered -system.cpu3.fetch.predictedBranches 45098 # Number of branches that fetch has predicted taken -system.cpu3.fetch.Cycles 145688 # Number of cycles fetch has run and was not squashing or blocked -system.cpu3.fetch.SquashCycles 4833 # Number of cycles fetch has spent squashing +system.cpu3.fetch.icacheStallCycles 44345 # Number of cycles fetch is stalled on an Icache miss +system.cpu3.fetch.Insts 305380 # Number of instructions fetch has processed +system.cpu3.fetch.Branches 58058 # Number of branches that fetch encountered +system.cpu3.fetch.predictedBranches 41323 # Number of branches that fetch has predicted taken +system.cpu3.fetch.Cycles 141573 # Number of cycles fetch has run and was not squashing or blocked +system.cpu3.fetch.SquashCycles 4965 # Number of cycles fetch has spent squashing system.cpu3.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu3.fetch.NoActiveThreadStallCycles 10 # Number of stall cycles due to no active thread to fetch from -system.cpu3.fetch.PendingTrapStallCycles 1762 # Number of stall cycles due to pending traps -system.cpu3.fetch.CacheLines 30337 # Number of cache lines fetched -system.cpu3.fetch.IcacheSquashes 926 # Number of outstanding Icache misses that were squashed -system.cpu3.fetch.rateDist::samples 191141 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::mean 1.722231 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::stdev 2.297340 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.PendingTrapStallCycles 1720 # Number of stall cycles due to pending traps +system.cpu3.fetch.CacheLines 32940 # Number of cache lines fetched +system.cpu3.fetch.IcacheSquashes 916 # Number of outstanding Icache misses that were squashed +system.cpu3.fetch.rateDist::samples 190133 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::mean 1.606139 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::stdev 2.261267 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::0 79632 41.66% 41.66% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::1 55527 29.05% 70.71% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::2 9457 4.95% 75.66% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::3 3401 1.78% 77.44% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::4 679 0.36% 77.79% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::5 31347 16.40% 94.19% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::6 1154 0.60% 94.80% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::7 1382 0.72% 95.52% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::8 8562 4.48% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::0 84706 44.55% 44.55% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::1 53051 27.90% 72.45% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::2 10689 5.62% 78.07% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::3 3433 1.81% 79.88% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::4 679 0.36% 80.24% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::5 26352 13.86% 94.10% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::6 1085 0.57% 94.67% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::7 1438 0.76% 95.42% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::8 8700 4.58% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::total 191141 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.branchRate 0.320626 # Number of branch fetches per cycle -system.cpu3.fetch.rate 1.707872 # Number of inst fetches per cycle -system.cpu3.decode.IdleCycles 22425 # Number of cycles decode is idle -system.cpu3.decode.BlockedCycles 81552 # Number of cycles decode is blocked -system.cpu3.decode.RunCycles 79630 # Number of cycles decode is running -system.cpu3.decode.UnblockCycles 5108 # Number of cycles decode is unblocking -system.cpu3.decode.SquashCycles 2416 # Number of cycles decode is squashing -system.cpu3.decode.DecodedInsts 297344 # Number of instructions handled by decode -system.cpu3.rename.SquashCycles 2416 # Number of cycles rename is squashing -system.cpu3.rename.IdleCycles 23427 # Number of cycles rename is idle -system.cpu3.rename.BlockCycles 40476 # Number of cycles rename is blocking -system.cpu3.rename.serializeStallCycles 14673 # count of cycles rename stalled for serializing inst -system.cpu3.rename.RunCycles 80471 # Number of cycles rename is running -system.cpu3.rename.UnblockCycles 29668 # Number of cycles rename is unblocking -system.cpu3.rename.RenamedInsts 290876 # Number of instructions processed by rename -system.cpu3.rename.IQFullEvents 25659 # Number of times rename has blocked due to IQ full -system.cpu3.rename.LQFullEvents 14 # Number of times rename has blocked due to LQ full -system.cpu3.rename.RenamedOperands 201895 # Number of destination operands rename has renamed -system.cpu3.rename.RenameLookups 544124 # Number of register rename lookups that rename has made -system.cpu3.rename.int_rename_lookups 425656 # Number of integer rename lookups -system.cpu3.rename.fp_rename_lookups 36 # Number of floating rename lookups -system.cpu3.rename.CommittedMaps 173837 # Number of HB maps that are committed -system.cpu3.rename.UndoneMaps 28058 # Number of HB maps that are undone due to squashing -system.cpu3.rename.serializingInsts 1657 # count of serializing insts renamed -system.cpu3.rename.tempSerializingInsts 1795 # count of temporary serializing insts renamed -system.cpu3.rename.skidInsts 35428 # count of insts added to the skid buffer -system.cpu3.memDep0.insertedLoads 77674 # Number of loads inserted to the mem dependence unit. -system.cpu3.memDep0.insertedStores 35638 # Number of stores inserted to the mem dependence unit. -system.cpu3.memDep0.conflictingLoads 37571 # Number of conflicting loads. -system.cpu3.memDep0.conflictingStores 29275 # Number of conflicting stores. -system.cpu3.iq.iqInstsAdded 234657 # Number of instructions added to the IQ (excludes non-spec) -system.cpu3.iq.iqNonSpecInstsAdded 9848 # Number of non-speculative instructions added to the IQ -system.cpu3.iq.iqInstsIssued 236528 # Number of instructions issued -system.cpu3.iq.iqSquashedInstsIssued 68 # Number of squashed instructions issued -system.cpu3.iq.iqSquashedInstsExamined 24579 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu3.iq.iqSquashedOperandsExamined 19470 # Number of squashed operands that are examined and possibly removed from graph -system.cpu3.iq.iqSquashedNonSpecRemoved 1266 # Number of squashed non-spec instructions that were removed -system.cpu3.iq.issued_per_cycle::samples 191141 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::mean 1.237453 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::stdev 1.372875 # Number of insts issued each cycle +system.cpu3.fetch.rateDist::total 190133 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.branchRate 0.302772 # Number of branch fetches per cycle +system.cpu3.fetch.rate 1.592553 # Number of inst fetches per cycle +system.cpu3.decode.IdleCycles 22846 # Number of cycles decode is idle +system.cpu3.decode.BlockedCycles 89002 # Number of cycles decode is blocked +system.cpu3.decode.RunCycles 70141 # Number of cycles decode is running +system.cpu3.decode.UnblockCycles 5652 # Number of cycles decode is unblocking +system.cpu3.decode.SquashCycles 2482 # Number of cycles decode is squashing +system.cpu3.decode.DecodedInsts 273868 # Number of instructions handled by decode +system.cpu3.rename.SquashCycles 2482 # Number of cycles rename is squashing +system.cpu3.rename.IdleCycles 23847 # Number of cycles rename is idle +system.cpu3.rename.BlockCycles 45287 # Number of cycles rename is blocking +system.cpu3.rename.serializeStallCycles 13384 # count of cycles rename stalled for serializing inst +system.cpu3.rename.RunCycles 70737 # Number of cycles rename is running +system.cpu3.rename.UnblockCycles 34386 # Number of cycles rename is unblocking +system.cpu3.rename.RenamedInsts 267452 # Number of instructions processed by rename +system.cpu3.rename.IQFullEvents 29592 # Number of times rename has blocked due to IQ full +system.cpu3.rename.LQFullEvents 13 # Number of times rename has blocked due to LQ full +system.cpu3.rename.RenamedOperands 184677 # Number of destination operands rename has renamed +system.cpu3.rename.RenameLookups 492576 # Number of register rename lookups that rename has made +system.cpu3.rename.int_rename_lookups 387264 # Number of integer rename lookups +system.cpu3.rename.fp_rename_lookups 20 # Number of floating rename lookups +system.cpu3.rename.CommittedMaps 155405 # Number of HB maps that are committed +system.cpu3.rename.UndoneMaps 29272 # Number of HB maps that are undone due to squashing +system.cpu3.rename.serializingInsts 1682 # count of serializing insts renamed +system.cpu3.rename.tempSerializingInsts 1811 # count of temporary serializing insts renamed +system.cpu3.rename.skidInsts 39856 # count of insts added to the skid buffer +system.cpu3.memDep0.insertedLoads 69050 # Number of loads inserted to the mem dependence unit. +system.cpu3.memDep0.insertedStores 30771 # Number of stores inserted to the mem dependence unit. +system.cpu3.memDep0.conflictingLoads 33750 # Number of conflicting loads. +system.cpu3.memDep0.conflictingStores 24332 # Number of conflicting stores. +system.cpu3.iq.iqInstsAdded 213083 # Number of instructions added to the IQ (excludes non-spec) +system.cpu3.iq.iqNonSpecInstsAdded 11008 # Number of non-speculative instructions added to the IQ +system.cpu3.iq.iqInstsIssued 216315 # Number of instructions issued +system.cpu3.iq.iqSquashedInstsIssued 53 # Number of squashed instructions issued +system.cpu3.iq.iqSquashedInstsExamined 25213 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu3.iq.iqSquashedOperandsExamined 19048 # Number of squashed operands that are examined and possibly removed from graph +system.cpu3.iq.iqSquashedNonSpecRemoved 1289 # Number of squashed non-spec instructions that were removed +system.cpu3.iq.issued_per_cycle::samples 190133 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::mean 1.137704 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::stdev 1.357547 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::0 84630 44.28% 44.28% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::1 31019 16.23% 60.50% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::2 34273 17.93% 78.44% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::3 34156 17.87% 96.30% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::4 3613 1.89% 98.20% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::5 1675 0.88% 99.07% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::6 1066 0.56% 99.63% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::7 400 0.21% 99.84% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::8 309 0.16% 100.00% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::0 89784 47.22% 47.22% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::1 34463 18.13% 65.35% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::2 29348 15.44% 80.78% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::3 29336 15.43% 96.21% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::4 3681 1.94% 98.15% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::5 1744 0.92% 99.07% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::6 1040 0.55% 99.61% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::7 432 0.23% 99.84% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::8 305 0.16% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::total 191141 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::total 190133 # Number of insts issued each cycle system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntAlu 176 38.18% 38.18% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntMult 0 0.00% 38.18% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntDiv 0 0.00% 38.18% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatAdd 0 0.00% 38.18% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCmp 0 0.00% 38.18% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCvt 0 0.00% 38.18% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatMult 0 0.00% 38.18% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatDiv 0 0.00% 38.18% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 38.18% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAdd 0 0.00% 38.18% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 38.18% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAlu 0 0.00% 38.18% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCmp 0 0.00% 38.18% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCvt 0 0.00% 38.18% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMisc 0 0.00% 38.18% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMult 0 0.00% 38.18% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 38.18% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShift 0 0.00% 38.18% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 38.18% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 38.18% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 38.18% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 38.18% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 38.18% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 38.18% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 38.18% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 38.18% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 38.18% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 38.18% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 38.18% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemRead 50 10.85% 49.02% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemWrite 235 50.98% 100.00% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntAlu 189 39.38% 39.38% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntMult 0 0.00% 39.38% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntDiv 0 0.00% 39.38% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatAdd 0 0.00% 39.38% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCmp 0 0.00% 39.38% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCvt 0 0.00% 39.38% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatMult 0 0.00% 39.38% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatDiv 0 0.00% 39.38% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 39.38% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAdd 0 0.00% 39.38% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 39.38% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAlu 0 0.00% 39.38% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCmp 0 0.00% 39.38% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCvt 0 0.00% 39.38% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMisc 0 0.00% 39.38% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMult 0 0.00% 39.38% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 39.38% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShift 0 0.00% 39.38% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 39.38% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 39.38% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 39.38% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 39.38% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 39.38% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 39.38% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 39.38% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 39.38% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 39.38% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 39.38% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 39.38% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemRead 53 11.04% 50.42% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemWrite 238 49.58% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu3.iq.FU_type_0::IntAlu 117496 49.68% 49.68% # Type of FU issued -system.cpu3.iq.FU_type_0::IntMult 0 0.00% 49.68% # Type of FU issued -system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 49.68% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 49.68% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 49.68% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 49.68% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 49.68% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 49.68% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 49.68% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 49.68% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 49.68% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 49.68% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 49.68% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 49.68% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 49.68% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 49.68% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 49.68% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 49.68% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.68% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 49.68% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.68% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.68% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.68% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.68% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.68% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.68% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 49.68% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.68% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.68% # Type of FU issued -system.cpu3.iq.FU_type_0::MemRead 84415 35.69% 85.36% # Type of FU issued -system.cpu3.iq.FU_type_0::MemWrite 34617 14.64% 100.00% # Type of FU issued +system.cpu3.iq.FU_type_0::IntAlu 109511 50.63% 50.63% # Type of FU issued +system.cpu3.iq.FU_type_0::IntMult 0 0.00% 50.63% # Type of FU issued +system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 50.63% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 50.63% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 50.63% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 50.63% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 50.63% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 50.63% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 50.63% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 50.63% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 50.63% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 50.63% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 50.63% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 50.63% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 50.63% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 50.63% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 50.63% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 50.63% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 50.63% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 50.63% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 50.63% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 50.63% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 50.63% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 50.63% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 50.63% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 50.63% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 50.63% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 50.63% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 50.63% # Type of FU issued +system.cpu3.iq.FU_type_0::MemRead 77010 35.60% 86.23% # Type of FU issued +system.cpu3.iq.FU_type_0::MemWrite 29794 13.77% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu3.iq.FU_type_0::total 236528 # Type of FU issued -system.cpu3.iq.rate 1.227136 # Inst issue rate -system.cpu3.iq.fu_busy_cnt 461 # FU busy when requested -system.cpu3.iq.fu_busy_rate 0.001949 # FU busy rate (busy events/executed inst) -system.cpu3.iq.int_inst_queue_reads 664726 # Number of integer instruction queue reads -system.cpu3.iq.int_inst_queue_writes 269047 # Number of integer instruction queue writes -system.cpu3.iq.int_inst_queue_wakeup_accesses 232596 # Number of integer instruction queue wakeup accesses +system.cpu3.iq.FU_type_0::total 216315 # Type of FU issued +system.cpu3.iq.rate 1.128080 # Inst issue rate +system.cpu3.iq.fu_busy_cnt 480 # FU busy when requested +system.cpu3.iq.fu_busy_rate 0.002219 # FU busy rate (busy events/executed inst) +system.cpu3.iq.int_inst_queue_reads 623296 # Number of integer instruction queue reads +system.cpu3.iq.int_inst_queue_writes 249298 # Number of integer instruction queue writes +system.cpu3.iq.int_inst_queue_wakeup_accesses 212257 # Number of integer instruction queue wakeup accesses system.cpu3.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads -system.cpu3.iq.fp_inst_queue_writes 72 # Number of floating instruction queue writes +system.cpu3.iq.fp_inst_queue_writes 40 # Number of floating instruction queue writes system.cpu3.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu3.iq.int_alu_accesses 236989 # Number of integer alu accesses +system.cpu3.iq.int_alu_accesses 216795 # Number of integer alu accesses system.cpu3.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu3.iew.lsq.thread0.forwLoads 29180 # Number of loads that had data forwarded from stores +system.cpu3.iew.lsq.thread0.forwLoads 24283 # Number of loads that had data forwarded from stores system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu3.iew.lsq.thread0.squashedLoads 4384 # Number of loads squashed -system.cpu3.iew.lsq.thread0.ignoredResponses 23 # Number of memory responses ignored because the instruction is squashed -system.cpu3.iew.lsq.thread0.memOrderViolation 35 # Number of memory ordering violations -system.cpu3.iew.lsq.thread0.squashedStores 2661 # Number of stores squashed +system.cpu3.iew.lsq.thread0.squashedLoads 4403 # Number of loads squashed +system.cpu3.iew.lsq.thread0.ignoredResponses 27 # Number of memory responses ignored because the instruction is squashed +system.cpu3.iew.lsq.thread0.memOrderViolation 34 # Number of memory ordering violations +system.cpu3.iew.lsq.thread0.squashedStores 2689 # Number of stores squashed system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu3.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu3.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu3.iew.iewSquashCycles 2416 # Number of cycles IEW is squashing -system.cpu3.iew.iewBlockCycles 11113 # Number of cycles IEW is blocking -system.cpu3.iew.iewUnblockCycles 50 # Number of cycles IEW is unblocking -system.cpu3.iew.iewDispatchedInsts 283276 # Number of instructions dispatched to IQ -system.cpu3.iew.iewDispSquashedInsts 304 # Number of squashed instructions skipped by dispatch -system.cpu3.iew.iewDispLoadInsts 77674 # Number of dispatched load instructions -system.cpu3.iew.iewDispStoreInsts 35638 # Number of dispatched store instructions -system.cpu3.iew.iewDispNonSpecInsts 1522 # Number of dispatched non-speculative instructions -system.cpu3.iew.iewIQFullEvents 28 # Number of times the IQ has become full, causing a stall +system.cpu3.iew.iewSquashCycles 2482 # Number of cycles IEW is squashing +system.cpu3.iew.iewBlockCycles 11408 # Number of cycles IEW is blocking +system.cpu3.iew.iewUnblockCycles 53 # Number of cycles IEW is unblocking +system.cpu3.iew.iewDispatchedInsts 259073 # Number of instructions dispatched to IQ +system.cpu3.iew.iewDispSquashedInsts 473 # Number of squashed instructions skipped by dispatch +system.cpu3.iew.iewDispLoadInsts 69050 # Number of dispatched load instructions +system.cpu3.iew.iewDispStoreInsts 30771 # Number of dispatched store instructions +system.cpu3.iew.iewDispNonSpecInsts 1541 # Number of dispatched non-speculative instructions +system.cpu3.iew.iewIQFullEvents 26 # Number of times the IQ has become full, causing a stall system.cpu3.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu3.iew.memOrderViolationEvents 35 # Number of memory order violations -system.cpu3.iew.predictedTakenIncorrect 471 # Number of branches that were predicted taken incorrectly -system.cpu3.iew.predictedNotTakenIncorrect 2483 # Number of branches that were predicted not taken incorrectly -system.cpu3.iew.branchMispredicts 2954 # Number of branch mispredicts detected at execute -system.cpu3.iew.iewExecutedInsts 233943 # Number of executed instructions -system.cpu3.iew.iewExecLoadInsts 76012 # Number of load instructions executed -system.cpu3.iew.iewExecSquashedInsts 2585 # Number of squashed instructions skipped in execute +system.cpu3.iew.memOrderViolationEvents 34 # Number of memory order violations +system.cpu3.iew.predictedTakenIncorrect 490 # Number of branches that were predicted taken incorrectly +system.cpu3.iew.predictedNotTakenIncorrect 2580 # Number of branches that were predicted not taken incorrectly +system.cpu3.iew.branchMispredicts 3070 # Number of branch mispredicts detected at execute +system.cpu3.iew.iewExecutedInsts 213662 # Number of executed instructions +system.cpu3.iew.iewExecLoadInsts 67471 # Number of load instructions executed +system.cpu3.iew.iewExecSquashedInsts 2653 # Number of squashed instructions skipped in execute system.cpu3.iew.exec_swp 0 # number of swp insts executed -system.cpu3.iew.exec_nop 38771 # number of nop insts executed -system.cpu3.iew.exec_refs 110309 # number of memory reference insts executed -system.cpu3.iew.exec_branches 49060 # Number of branches executed -system.cpu3.iew.exec_stores 34297 # Number of stores executed -system.cpu3.iew.exec_rate 1.213725 # Inst execution rate -system.cpu3.iew.wb_sent 233093 # cumulative count of insts sent to commit -system.cpu3.iew.wb_count 232596 # cumulative count of insts written-back -system.cpu3.iew.wb_producers 128296 # num instructions producing a value -system.cpu3.iew.wb_consumers 135910 # num instructions consuming a value -system.cpu3.iew.wb_rate 1.206736 # insts written-back per cycle -system.cpu3.iew.wb_fanout 0.943978 # average fanout of values written-back -system.cpu3.commit.commitSquashedInsts 25736 # The number of squashed insts skipped by commit -system.cpu3.commit.commitNonSpecStalls 8582 # The number of times commit has been forced to stall to communicate backwards -system.cpu3.commit.branchMispredicts 2339 # The number of times a branch was mispredicted -system.cpu3.commit.committed_per_cycle::samples 186297 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::mean 1.382277 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::stdev 1.944418 # Number of insts commited each cycle +system.cpu3.iew.exec_nop 34982 # number of nop insts executed +system.cpu3.iew.exec_refs 96956 # number of memory reference insts executed +system.cpu3.iew.exec_branches 45328 # Number of branches executed +system.cpu3.iew.exec_stores 29485 # Number of stores executed +system.cpu3.iew.exec_rate 1.114245 # Inst execution rate +system.cpu3.iew.wb_sent 212766 # cumulative count of insts sent to commit +system.cpu3.iew.wb_count 212257 # cumulative count of insts written-back +system.cpu3.iew.wb_producers 115033 # num instructions producing a value +system.cpu3.iew.wb_consumers 122695 # num instructions consuming a value +system.cpu3.iew.wb_rate 1.106918 # insts written-back per cycle +system.cpu3.iew.wb_fanout 0.937552 # average fanout of values written-back +system.cpu3.commit.commitSquashedInsts 26335 # The number of squashed insts skipped by commit +system.cpu3.commit.commitNonSpecStalls 9719 # The number of times commit has been forced to stall to communicate backwards +system.cpu3.commit.branchMispredicts 2406 # The number of times a branch was mispredicted +system.cpu3.commit.committed_per_cycle::samples 185183 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::mean 1.256660 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::stdev 1.878907 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::0 92574 49.69% 49.69% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::1 45329 24.33% 74.02% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::2 5460 2.93% 76.95% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::3 9239 4.96% 81.91% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::4 1287 0.69% 82.60% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::5 29468 15.82% 98.42% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::6 712 0.38% 98.80% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::7 1036 0.56% 99.36% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::8 1192 0.64% 100.00% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::0 99076 53.50% 53.50% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::1 41559 22.44% 75.94% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::2 5388 2.91% 78.85% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::3 10319 5.57% 84.43% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::4 1252 0.68% 85.10% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::5 24567 13.27% 98.37% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::6 787 0.42% 98.79% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::7 1025 0.55% 99.35% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::8 1210 0.65% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::total 186297 # Number of insts commited each cycle -system.cpu3.commit.committedInsts 257514 # Number of instructions committed -system.cpu3.commit.committedOps 257514 # Number of ops (including micro ops) committed +system.cpu3.commit.committed_per_cycle::total 185183 # Number of insts commited each cycle +system.cpu3.commit.committedInsts 232712 # Number of instructions committed +system.cpu3.commit.committedOps 232712 # Number of ops (including micro ops) committed system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu3.commit.refs 106267 # Number of memory references committed -system.cpu3.commit.loads 73290 # Number of loads committed -system.cpu3.commit.membars 7865 # Number of memory barriers committed -system.cpu3.commit.branches 46801 # Number of branches committed +system.cpu3.commit.refs 92729 # Number of memory references committed +system.cpu3.commit.loads 64647 # Number of loads committed +system.cpu3.commit.membars 9005 # Number of memory barriers committed +system.cpu3.commit.branches 43044 # Number of branches committed system.cpu3.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu3.commit.int_insts 175188 # Number of committed integer instructions. +system.cpu3.commit.int_insts 157897 # Number of committed integer instructions. system.cpu3.commit.function_calls 322 # Number of function calls committed. -system.cpu3.commit.op_class_0::No_OpClass 37588 14.60% 14.60% # Class of committed instruction -system.cpu3.commit.op_class_0::IntAlu 105794 41.08% 55.68% # Class of committed instruction -system.cpu3.commit.op_class_0::IntMult 0 0.00% 55.68% # Class of committed instruction -system.cpu3.commit.op_class_0::IntDiv 0 0.00% 55.68% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 55.68% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 55.68% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 55.68% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatMult 0 0.00% 55.68% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 55.68% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 55.68% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 55.68% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 55.68% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdAlu 0 0.00% 55.68% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdCmp 0 0.00% 55.68% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdCvt 0 0.00% 55.68% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdMisc 0 0.00% 55.68% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdMult 0 0.00% 55.68% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 55.68% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdShift 0 0.00% 55.68% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 55.68% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 55.68% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 55.68% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 55.68% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 55.68% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 55.68% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 55.68% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatMisc 0 0.00% 55.68% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 55.68% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 55.68% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 55.68% # Class of committed instruction -system.cpu3.commit.op_class_0::MemRead 81155 31.51% 87.19% # Class of committed instruction -system.cpu3.commit.op_class_0::MemWrite 32977 12.81% 100.00% # Class of committed instruction +system.cpu3.commit.op_class_0::No_OpClass 33834 14.54% 14.54% # Class of committed instruction +system.cpu3.commit.op_class_0::IntAlu 97144 41.74% 56.28% # Class of committed instruction +system.cpu3.commit.op_class_0::IntMult 0 0.00% 56.28% # Class of committed instruction +system.cpu3.commit.op_class_0::IntDiv 0 0.00% 56.28% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 56.28% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 56.28% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 56.28% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatMult 0 0.00% 56.28% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 56.28% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 56.28% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 56.28% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 56.28% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdAlu 0 0.00% 56.28% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdCmp 0 0.00% 56.28% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdCvt 0 0.00% 56.28% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdMisc 0 0.00% 56.28% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdMult 0 0.00% 56.28% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 56.28% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdShift 0 0.00% 56.28% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 56.28% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 56.28% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 56.28% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 56.28% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 56.28% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 56.28% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 56.28% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMisc 0 0.00% 56.28% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 56.28% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 56.28% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 56.28% # Class of committed instruction +system.cpu3.commit.op_class_0::MemRead 73652 31.65% 87.93% # Class of committed instruction +system.cpu3.commit.op_class_0::MemWrite 28082 12.07% 100.00% # Class of committed instruction system.cpu3.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu3.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu3.commit.op_class_0::total 257514 # Class of committed instruction -system.cpu3.commit.bw_lim_events 1192 # number cycles where commit BW limit reached -system.cpu3.rob.rob_reads 467769 # The number of ROB reads -system.cpu3.rob.rob_writes 571412 # The number of ROB writes -system.cpu3.timesIdled 219 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu3.idleCycles 1607 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu3.commit.op_class_0::total 232712 # Class of committed instruction +system.cpu3.commit.bw_lim_events 1210 # number cycles where commit BW limit reached +system.cpu3.rob.rob_reads 442434 # The number of ROB reads +system.cpu3.rob.rob_writes 523106 # The number of ROB writes +system.cpu3.timesIdled 214 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu3.idleCycles 1622 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu3.quiesceCycles 48179 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu3.committedInsts 212061 # Number of Instructions Simulated -system.cpu3.committedOps 212061 # Number of Ops (including micro ops) Simulated -system.cpu3.cpi 0.908927 # CPI: Cycles Per Instruction -system.cpu3.cpi_total 0.908927 # CPI: Total CPI of All Threads -system.cpu3.ipc 1.100198 # IPC: Instructions Per Cycle -system.cpu3.ipc_total 1.100198 # IPC: Total IPC of All Threads -system.cpu3.int_regfile_reads 395124 # number of integer regfile reads -system.cpu3.int_regfile_writes 185063 # number of integer regfile writes +system.cpu3.committedInsts 189873 # Number of Instructions Simulated +system.cpu3.committedOps 189873 # Number of Ops (including micro ops) Simulated +system.cpu3.cpi 1.009912 # CPI: Cycles Per Instruction +system.cpu3.cpi_total 1.009912 # CPI: Total CPI of All Threads +system.cpu3.ipc 0.990185 # IPC: Instructions Per Cycle +system.cpu3.ipc_total 0.990185 # IPC: Total IPC of All Threads +system.cpu3.int_regfile_reads 355771 # number of integer regfile reads +system.cpu3.int_regfile_writes 167240 # number of integer regfile writes system.cpu3.fp_regfile_writes 64 # number of floating regfile writes -system.cpu3.misc_regfile_reads 112177 # number of misc regfile reads +system.cpu3.misc_regfile_reads 98845 # number of misc regfile reads system.cpu3.misc_regfile_writes 648 # number of misc regfile writes -system.cpu3.dcache.tags.pwrStateResidencyTicks::UNDEFINED 124523000 # Cumulative time (in ticks) in various power states +system.cpu3.dcache.tags.pwrStateResidencyTicks::UNDEFINED 123936000 # Cumulative time (in ticks) in various power states system.cpu3.dcache.tags.replacements 0 # number of replacements -system.cpu3.dcache.tags.tagsinuse 24.465247 # Cycle average of tags in use -system.cpu3.dcache.tags.total_refs 40069 # Total number of references to valid blocks. -system.cpu3.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. -system.cpu3.dcache.tags.avg_refs 1381.689655 # Average number of references to valid blocks. +system.cpu3.dcache.tags.tagsinuse 24.519752 # Cycle average of tags in use +system.cpu3.dcache.tags.total_refs 35385 # Total number of references to valid blocks. +system.cpu3.dcache.tags.sampled_refs 30 # Sample count of references to valid blocks. +system.cpu3.dcache.tags.avg_refs 1179.500000 # Average number of references to valid blocks. system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.dcache.tags.occ_blocks::cpu3.data 24.465247 # Average occupied blocks per requestor -system.cpu3.dcache.tags.occ_percent::cpu3.data 0.047784 # Average percentage of cache occupancy -system.cpu3.dcache.tags.occ_percent::total 0.047784 # Average percentage of cache occupancy -system.cpu3.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id -system.cpu3.dcache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id -system.cpu3.dcache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id -system.cpu3.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id -system.cpu3.dcache.tags.tag_accesses 319388 # Number of tag accesses -system.cpu3.dcache.tags.data_accesses 319388 # Number of data accesses -system.cpu3.dcache.pwrStateResidencyTicks::UNDEFINED 124523000 # Cumulative time (in ticks) in various power states -system.cpu3.dcache.ReadReq_hits::cpu3.data 46353 # number of ReadReq hits -system.cpu3.dcache.ReadReq_hits::total 46353 # number of ReadReq hits -system.cpu3.dcache.WriteReq_hits::cpu3.data 32769 # number of WriteReq hits -system.cpu3.dcache.WriteReq_hits::total 32769 # number of WriteReq hits -system.cpu3.dcache.SwapReq_hits::cpu3.data 15 # number of SwapReq hits -system.cpu3.dcache.SwapReq_hits::total 15 # number of SwapReq hits -system.cpu3.dcache.demand_hits::cpu3.data 79122 # number of demand (read+write) hits -system.cpu3.dcache.demand_hits::total 79122 # number of demand (read+write) hits -system.cpu3.dcache.overall_hits::cpu3.data 79122 # number of overall hits -system.cpu3.dcache.overall_hits::total 79122 # number of overall hits -system.cpu3.dcache.ReadReq_misses::cpu3.data 454 # number of ReadReq misses -system.cpu3.dcache.ReadReq_misses::total 454 # number of ReadReq misses +system.cpu3.dcache.tags.occ_blocks::cpu3.data 24.519752 # Average occupied blocks per requestor +system.cpu3.dcache.tags.occ_percent::cpu3.data 0.047890 # Average percentage of cache occupancy +system.cpu3.dcache.tags.occ_percent::total 0.047890 # Average percentage of cache occupancy +system.cpu3.dcache.tags.occ_task_id_blocks::1024 30 # Occupied blocks per task id +system.cpu3.dcache.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id +system.cpu3.dcache.tags.age_task_id_blocks_1024::1 29 # Occupied blocks per task id +system.cpu3.dcache.tags.occ_task_id_percent::1024 0.058594 # Percentage of cache occupancy per task id +system.cpu3.dcache.tags.tag_accesses 285185 # Number of tag accesses +system.cpu3.dcache.tags.data_accesses 285185 # Number of data accesses +system.cpu3.dcache.pwrStateResidencyTicks::UNDEFINED 123936000 # Cumulative time (in ticks) in various power states +system.cpu3.dcache.ReadReq_hits::cpu3.data 42713 # number of ReadReq hits +system.cpu3.dcache.ReadReq_hits::total 42713 # number of ReadReq hits +system.cpu3.dcache.WriteReq_hits::cpu3.data 27877 # number of WriteReq hits +system.cpu3.dcache.WriteReq_hits::total 27877 # number of WriteReq hits +system.cpu3.dcache.SwapReq_hits::cpu3.data 16 # number of SwapReq hits +system.cpu3.dcache.SwapReq_hits::total 16 # number of SwapReq hits +system.cpu3.dcache.demand_hits::cpu3.data 70590 # number of demand (read+write) hits +system.cpu3.dcache.demand_hits::total 70590 # number of demand (read+write) hits +system.cpu3.dcache.overall_hits::cpu3.data 70590 # number of overall hits +system.cpu3.dcache.overall_hits::total 70590 # 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number of WriteReq accesses(hits+misses) -system.cpu3.dcache.SwapReq_accesses::cpu3.data 71 # number of SwapReq accesses(hits+misses) -system.cpu3.dcache.SwapReq_accesses::total 71 # number of SwapReq accesses(hits+misses) -system.cpu3.dcache.demand_accesses::cpu3.data 79713 # number of demand (read+write) accesses -system.cpu3.dcache.demand_accesses::total 79713 # number of demand (read+write) accesses -system.cpu3.dcache.overall_accesses::cpu3.data 79713 # number of overall (read+write) accesses -system.cpu3.dcache.overall_accesses::total 79713 # number of overall (read+write) accesses -system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.009699 # miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_miss_rate::total 0.009699 # miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.004163 # miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_miss_rate::total 0.004163 # miss rate for WriteReq accesses -system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.788732 # 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number of ReadReq miss cycles +system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 2743000 # number of WriteReq miss cycles +system.cpu3.dcache.WriteReq_miss_latency::total 2743000 # number of WriteReq miss cycles +system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 334000 # number of SwapReq miss cycles +system.cpu3.dcache.SwapReq_miss_latency::total 334000 # number of SwapReq miss cycles +system.cpu3.dcache.demand_miss_latency::cpu3.data 5928500 # number of demand (read+write) miss cycles +system.cpu3.dcache.demand_miss_latency::total 5928500 # number of demand (read+write) miss cycles +system.cpu3.dcache.overall_miss_latency::cpu3.data 5928500 # number of overall miss cycles +system.cpu3.dcache.overall_miss_latency::total 5928500 # number of overall miss cycles +system.cpu3.dcache.ReadReq_accesses::cpu3.data 43152 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.ReadReq_accesses::total 43152 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_accesses::cpu3.data 28014 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_accesses::total 28014 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.SwapReq_accesses::cpu3.data 68 # number of SwapReq accesses(hits+misses) +system.cpu3.dcache.SwapReq_accesses::total 68 # number of SwapReq accesses(hits+misses) +system.cpu3.dcache.demand_accesses::cpu3.data 71166 # number of demand (read+write) accesses +system.cpu3.dcache.demand_accesses::total 71166 # number of demand (read+write) accesses +system.cpu3.dcache.overall_accesses::cpu3.data 71166 # number of overall (read+write) accesses +system.cpu3.dcache.overall_accesses::total 71166 # number of overall (read+write) accesses +system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.010173 # miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_miss_rate::total 0.010173 # miss rate for ReadReq accesses +system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.004890 # miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_miss_rate::total 0.004890 # miss rate for WriteReq accesses +system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.764706 # miss rate for SwapReq accesses +system.cpu3.dcache.SwapReq_miss_rate::total 0.764706 # miss rate for SwapReq accesses +system.cpu3.dcache.demand_miss_rate::cpu3.data 0.008094 # miss rate for demand accesses +system.cpu3.dcache.demand_miss_rate::total 0.008094 # miss rate for demand accesses +system.cpu3.dcache.overall_miss_rate::cpu3.data 0.008094 # miss rate for overall accesses +system.cpu3.dcache.overall_miss_rate::total 0.008094 # miss rate for overall accesses +system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 7256.264237 # average ReadReq miss latency +system.cpu3.dcache.ReadReq_avg_miss_latency::total 7256.264237 # average ReadReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 20021.897810 # average WriteReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::total 20021.897810 # average WriteReq miss latency +system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 6423.076923 # average SwapReq miss latency +system.cpu3.dcache.SwapReq_avg_miss_latency::total 6423.076923 # average SwapReq miss latency +system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 10292.534722 # average overall miss latency +system.cpu3.dcache.demand_avg_miss_latency::total 10292.534722 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 10292.534722 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::total 10292.534722 # average overall miss latency system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data 292 # number of ReadReq MSHR hits -system.cpu3.dcache.ReadReq_mshr_hits::total 292 # number of ReadReq MSHR hits -system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data 35 # number of WriteReq MSHR hits -system.cpu3.dcache.WriteReq_mshr_hits::total 35 # number of WriteReq MSHR hits -system.cpu3.dcache.SwapReq_mshr_hits::cpu3.data 3 # number of SwapReq MSHR hits -system.cpu3.dcache.SwapReq_mshr_hits::total 3 # number of SwapReq MSHR hits -system.cpu3.dcache.demand_mshr_hits::cpu3.data 327 # number of demand (read+write) MSHR hits -system.cpu3.dcache.demand_mshr_hits::total 327 # number of demand (read+write) MSHR hits -system.cpu3.dcache.overall_mshr_hits::cpu3.data 327 # number of overall MSHR hits -system.cpu3.dcache.overall_mshr_hits::total 327 # number of overall MSHR hits -system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 162 # number of ReadReq MSHR misses -system.cpu3.dcache.ReadReq_mshr_misses::total 162 # number of ReadReq MSHR misses -system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 102 # number of WriteReq MSHR misses -system.cpu3.dcache.WriteReq_mshr_misses::total 102 # number of WriteReq MSHR misses -system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 53 # number of SwapReq MSHR misses -system.cpu3.dcache.SwapReq_mshr_misses::total 53 # number of SwapReq MSHR misses -system.cpu3.dcache.demand_mshr_misses::cpu3.data 264 # number of demand (read+write) MSHR misses -system.cpu3.dcache.demand_mshr_misses::total 264 # number of demand (read+write) MSHR misses -system.cpu3.dcache.overall_mshr_misses::cpu3.data 264 # number of overall MSHR misses -system.cpu3.dcache.overall_mshr_misses::total 264 # number of overall MSHR misses -system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 1605500 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_latency::total 1605500 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1601500 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1601500 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 714500 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.SwapReq_mshr_miss_latency::total 714500 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 3207000 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::total 3207000 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 3207000 # number of overall MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::total 3207000 # number of overall MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003461 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003461 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.003100 # mshr miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.003100 # mshr miss rate for WriteReq accesses -system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.746479 # mshr miss rate for SwapReq accesses -system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.746479 # mshr miss rate for SwapReq accesses -system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.003312 # mshr miss rate for demand accesses -system.cpu3.dcache.demand_mshr_miss_rate::total 0.003312 # mshr miss rate for demand accesses -system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.003312 # mshr miss rate for overall accesses -system.cpu3.dcache.overall_mshr_miss_rate::total 0.003312 # mshr miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 9910.493827 # average ReadReq mshr miss latency -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 9910.493827 # average ReadReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 15700.980392 # average WriteReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 15700.980392 # average WriteReq mshr miss latency -system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 13481.132075 # average SwapReq mshr miss latency -system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 13481.132075 # average SwapReq mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 12147.727273 # average overall mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency::total 12147.727273 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 12147.727273 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::total 12147.727273 # average overall mshr miss latency -system.cpu3.icache.tags.pwrStateResidencyTicks::UNDEFINED 124523000 # Cumulative time (in ticks) in various power states -system.cpu3.icache.tags.replacements 563 # number of replacements -system.cpu3.icache.tags.tagsinuse 93.764815 # Cycle average of tags in use -system.cpu3.icache.tags.total_refs 29516 # Total number of references to valid blocks. -system.cpu3.icache.tags.sampled_refs 701 # Sample count of references to valid blocks. -system.cpu3.icache.tags.avg_refs 42.105563 # Average number of references to valid blocks. +system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data 281 # number of ReadReq MSHR hits +system.cpu3.dcache.ReadReq_mshr_hits::total 281 # number of ReadReq MSHR hits +system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data 33 # number of WriteReq MSHR hits +system.cpu3.dcache.WriteReq_mshr_hits::total 33 # number of WriteReq MSHR hits +system.cpu3.dcache.SwapReq_mshr_hits::cpu3.data 1 # number of SwapReq MSHR hits +system.cpu3.dcache.SwapReq_mshr_hits::total 1 # number of SwapReq MSHR hits +system.cpu3.dcache.demand_mshr_hits::cpu3.data 314 # number of demand (read+write) MSHR hits +system.cpu3.dcache.demand_mshr_hits::total 314 # number of demand (read+write) MSHR hits +system.cpu3.dcache.overall_mshr_hits::cpu3.data 314 # number of overall MSHR hits +system.cpu3.dcache.overall_mshr_hits::total 314 # number of overall MSHR hits +system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 158 # number of ReadReq MSHR misses +system.cpu3.dcache.ReadReq_mshr_misses::total 158 # number of ReadReq MSHR misses +system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 104 # number of WriteReq MSHR misses +system.cpu3.dcache.WriteReq_mshr_misses::total 104 # number of WriteReq MSHR misses +system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 51 # number of SwapReq MSHR misses +system.cpu3.dcache.SwapReq_mshr_misses::total 51 # number of SwapReq MSHR misses +system.cpu3.dcache.demand_mshr_misses::cpu3.data 262 # number of demand (read+write) MSHR misses +system.cpu3.dcache.demand_mshr_misses::total 262 # number of demand (read+write) MSHR misses +system.cpu3.dcache.overall_mshr_misses::cpu3.data 262 # number of overall MSHR misses +system.cpu3.dcache.overall_mshr_misses::total 262 # number of overall MSHR misses +system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 1084000 # number of ReadReq MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_latency::total 1084000 # number of ReadReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1390500 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1390500 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 282000 # number of SwapReq MSHR miss cycles +system.cpu3.dcache.SwapReq_mshr_miss_latency::total 282000 # number of SwapReq MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 2474500 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_latency::total 2474500 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 2474500 # number of overall MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::total 2474500 # number of overall MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003661 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003661 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.003712 # mshr miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.003712 # mshr miss rate for WriteReq accesses +system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.750000 # mshr miss rate for SwapReq accesses +system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.750000 # mshr miss rate for SwapReq accesses +system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.003682 # mshr miss rate for demand accesses +system.cpu3.dcache.demand_mshr_miss_rate::total 0.003682 # mshr miss rate for demand accesses +system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.003682 # mshr miss rate for overall accesses +system.cpu3.dcache.overall_mshr_miss_rate::total 0.003682 # mshr miss rate for overall accesses +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 6860.759494 # average ReadReq mshr miss latency +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 6860.759494 # average ReadReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 13370.192308 # average WriteReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 13370.192308 # average WriteReq mshr miss latency +system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 5529.411765 # average SwapReq mshr miss latency +system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 5529.411765 # average SwapReq mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 9444.656489 # average overall mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency::total 9444.656489 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 9444.656489 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency::total 9444.656489 # average overall mshr miss latency +system.cpu3.icache.tags.pwrStateResidencyTicks::UNDEFINED 123936000 # Cumulative time (in ticks) in various power states +system.cpu3.icache.tags.replacements 578 # number of replacements +system.cpu3.icache.tags.tagsinuse 92.680953 # Cycle average of tags in use +system.cpu3.icache.tags.total_refs 32101 # Total number of references to valid blocks. +system.cpu3.icache.tags.sampled_refs 713 # Sample count of references to valid blocks. +system.cpu3.icache.tags.avg_refs 45.022440 # Average number of references to valid blocks. system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.icache.tags.occ_blocks::cpu3.inst 93.764815 # Average occupied blocks per requestor -system.cpu3.icache.tags.occ_percent::cpu3.inst 0.183134 # Average percentage of cache occupancy -system.cpu3.icache.tags.occ_percent::total 0.183134 # Average percentage of cache occupancy -system.cpu3.icache.tags.occ_task_id_blocks::1024 138 # Occupied blocks per task id -system.cpu3.icache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id +system.cpu3.icache.tags.occ_blocks::cpu3.inst 92.680953 # Average occupied blocks per requestor +system.cpu3.icache.tags.occ_percent::cpu3.inst 0.181017 # Average percentage of cache occupancy +system.cpu3.icache.tags.occ_percent::total 0.181017 # Average percentage of cache occupancy +system.cpu3.icache.tags.occ_task_id_blocks::1024 135 # Occupied blocks per task id +system.cpu3.icache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id system.cpu3.icache.tags.age_task_id_blocks_1024::1 117 # Occupied blocks per task id -system.cpu3.icache.tags.age_task_id_blocks_1024::2 10 # Occupied blocks per task id -system.cpu3.icache.tags.occ_task_id_percent::1024 0.269531 # Percentage of cache occupancy per task id -system.cpu3.icache.tags.tag_accesses 31038 # Number of tag accesses -system.cpu3.icache.tags.data_accesses 31038 # Number of data accesses -system.cpu3.icache.pwrStateResidencyTicks::UNDEFINED 124523000 # Cumulative time (in ticks) in various power states -system.cpu3.icache.ReadReq_hits::cpu3.inst 29516 # number of ReadReq hits -system.cpu3.icache.ReadReq_hits::total 29516 # number of ReadReq hits -system.cpu3.icache.demand_hits::cpu3.inst 29516 # number of demand (read+write) hits -system.cpu3.icache.demand_hits::total 29516 # number of demand (read+write) hits -system.cpu3.icache.overall_hits::cpu3.inst 29516 # number of overall hits -system.cpu3.icache.overall_hits::total 29516 # number of overall hits -system.cpu3.icache.ReadReq_misses::cpu3.inst 821 # number of ReadReq misses -system.cpu3.icache.ReadReq_misses::total 821 # number of ReadReq misses -system.cpu3.icache.demand_misses::cpu3.inst 821 # number of demand (read+write) misses -system.cpu3.icache.demand_misses::total 821 # number of demand (read+write) misses -system.cpu3.icache.overall_misses::cpu3.inst 821 # number of overall misses -system.cpu3.icache.overall_misses::total 821 # number of overall misses -system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 11709000 # number of ReadReq miss cycles -system.cpu3.icache.ReadReq_miss_latency::total 11709000 # number of ReadReq miss cycles -system.cpu3.icache.demand_miss_latency::cpu3.inst 11709000 # number of demand (read+write) miss cycles -system.cpu3.icache.demand_miss_latency::total 11709000 # number of demand (read+write) miss cycles -system.cpu3.icache.overall_miss_latency::cpu3.inst 11709000 # number of overall miss cycles -system.cpu3.icache.overall_miss_latency::total 11709000 # number of overall miss cycles -system.cpu3.icache.ReadReq_accesses::cpu3.inst 30337 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.ReadReq_accesses::total 30337 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.demand_accesses::cpu3.inst 30337 # number of demand (read+write) accesses -system.cpu3.icache.demand_accesses::total 30337 # number of demand (read+write) accesses -system.cpu3.icache.overall_accesses::cpu3.inst 30337 # number of overall (read+write) accesses -system.cpu3.icache.overall_accesses::total 30337 # number of overall (read+write) accesses -system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.027063 # miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_miss_rate::total 0.027063 # miss rate for ReadReq accesses -system.cpu3.icache.demand_miss_rate::cpu3.inst 0.027063 # miss rate for demand accesses -system.cpu3.icache.demand_miss_rate::total 0.027063 # miss rate for demand accesses -system.cpu3.icache.overall_miss_rate::cpu3.inst 0.027063 # miss rate for overall accesses -system.cpu3.icache.overall_miss_rate::total 0.027063 # miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 14261.875761 # average ReadReq miss latency -system.cpu3.icache.ReadReq_avg_miss_latency::total 14261.875761 # average ReadReq miss latency -system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 14261.875761 # average overall miss latency -system.cpu3.icache.demand_avg_miss_latency::total 14261.875761 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 14261.875761 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::total 14261.875761 # average overall miss latency +system.cpu3.icache.tags.occ_task_id_percent::1024 0.263672 # Percentage of cache occupancy per task id +system.cpu3.icache.tags.tag_accesses 33653 # Number of tag accesses +system.cpu3.icache.tags.data_accesses 33653 # Number of data accesses +system.cpu3.icache.pwrStateResidencyTicks::UNDEFINED 123936000 # Cumulative time (in ticks) in various power states +system.cpu3.icache.ReadReq_hits::cpu3.inst 32101 # number of ReadReq hits +system.cpu3.icache.ReadReq_hits::total 32101 # number of ReadReq hits +system.cpu3.icache.demand_hits::cpu3.inst 32101 # number of demand (read+write) hits +system.cpu3.icache.demand_hits::total 32101 # number of demand (read+write) hits +system.cpu3.icache.overall_hits::cpu3.inst 32101 # number of overall hits +system.cpu3.icache.overall_hits::total 32101 # number of overall hits +system.cpu3.icache.ReadReq_misses::cpu3.inst 839 # number of ReadReq misses +system.cpu3.icache.ReadReq_misses::total 839 # number of ReadReq misses +system.cpu3.icache.demand_misses::cpu3.inst 839 # number of demand (read+write) misses +system.cpu3.icache.demand_misses::total 839 # number of demand (read+write) misses +system.cpu3.icache.overall_misses::cpu3.inst 839 # number of overall misses +system.cpu3.icache.overall_misses::total 839 # number of overall misses +system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 11633500 # number of ReadReq miss cycles +system.cpu3.icache.ReadReq_miss_latency::total 11633500 # number of ReadReq miss cycles +system.cpu3.icache.demand_miss_latency::cpu3.inst 11633500 # number of demand (read+write) miss cycles +system.cpu3.icache.demand_miss_latency::total 11633500 # number of demand (read+write) miss cycles +system.cpu3.icache.overall_miss_latency::cpu3.inst 11633500 # number of overall miss cycles +system.cpu3.icache.overall_miss_latency::total 11633500 # number of overall miss cycles +system.cpu3.icache.ReadReq_accesses::cpu3.inst 32940 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.ReadReq_accesses::total 32940 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.demand_accesses::cpu3.inst 32940 # number of demand (read+write) accesses +system.cpu3.icache.demand_accesses::total 32940 # number of demand (read+write) accesses +system.cpu3.icache.overall_accesses::cpu3.inst 32940 # number of overall (read+write) accesses +system.cpu3.icache.overall_accesses::total 32940 # number of overall (read+write) accesses +system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.025471 # miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_miss_rate::total 0.025471 # miss rate for ReadReq accesses +system.cpu3.icache.demand_miss_rate::cpu3.inst 0.025471 # miss rate for demand accesses +system.cpu3.icache.demand_miss_rate::total 0.025471 # miss rate for demand accesses +system.cpu3.icache.overall_miss_rate::cpu3.inst 0.025471 # miss rate for overall accesses +system.cpu3.icache.overall_miss_rate::total 0.025471 # miss rate for overall accesses +system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 13865.911800 # average ReadReq miss latency +system.cpu3.icache.ReadReq_avg_miss_latency::total 13865.911800 # average ReadReq miss latency +system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 13865.911800 # average overall miss latency +system.cpu3.icache.demand_avg_miss_latency::total 13865.911800 # average overall miss latency +system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13865.911800 # average overall miss latency +system.cpu3.icache.overall_avg_miss_latency::total 13865.911800 # average overall miss latency system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu3.icache.writebacks::writebacks 563 # number of writebacks -system.cpu3.icache.writebacks::total 563 # number of writebacks -system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst 120 # number of ReadReq MSHR hits -system.cpu3.icache.ReadReq_mshr_hits::total 120 # number of ReadReq MSHR hits -system.cpu3.icache.demand_mshr_hits::cpu3.inst 120 # number of demand (read+write) MSHR hits -system.cpu3.icache.demand_mshr_hits::total 120 # number of demand (read+write) MSHR hits -system.cpu3.icache.overall_mshr_hits::cpu3.inst 120 # number of overall MSHR hits -system.cpu3.icache.overall_mshr_hits::total 120 # number of overall MSHR hits -system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 701 # number of ReadReq MSHR misses -system.cpu3.icache.ReadReq_mshr_misses::total 701 # number of ReadReq MSHR misses -system.cpu3.icache.demand_mshr_misses::cpu3.inst 701 # number of demand (read+write) MSHR misses -system.cpu3.icache.demand_mshr_misses::total 701 # number of demand (read+write) MSHR misses -system.cpu3.icache.overall_mshr_misses::cpu3.inst 701 # number of overall MSHR misses -system.cpu3.icache.overall_mshr_misses::total 701 # number of overall MSHR misses -system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 10046500 # number of ReadReq MSHR miss cycles -system.cpu3.icache.ReadReq_mshr_miss_latency::total 10046500 # number of ReadReq MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 10046500 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_latency::total 10046500 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 10046500 # number of overall MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_latency::total 10046500 # number of overall MSHR miss cycles -system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.023107 # mshr miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.023107 # mshr miss rate for ReadReq accesses -system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.023107 # mshr miss rate for demand accesses -system.cpu3.icache.demand_mshr_miss_rate::total 0.023107 # mshr miss rate for demand accesses -system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.023107 # mshr miss rate for overall accesses -system.cpu3.icache.overall_mshr_miss_rate::total 0.023107 # mshr miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 14331.669044 # average ReadReq mshr miss latency -system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 14331.669044 # average ReadReq mshr miss latency -system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 14331.669044 # average overall mshr miss latency -system.cpu3.icache.demand_avg_mshr_miss_latency::total 14331.669044 # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 14331.669044 # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency::total 14331.669044 # average overall mshr miss latency -system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 124523000 # Cumulative time (in ticks) in various power states +system.cpu3.icache.writebacks::writebacks 578 # number of writebacks +system.cpu3.icache.writebacks::total 578 # number of writebacks +system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst 126 # number of ReadReq MSHR hits +system.cpu3.icache.ReadReq_mshr_hits::total 126 # number of ReadReq MSHR hits +system.cpu3.icache.demand_mshr_hits::cpu3.inst 126 # number of demand (read+write) MSHR hits +system.cpu3.icache.demand_mshr_hits::total 126 # number of demand (read+write) MSHR hits +system.cpu3.icache.overall_mshr_hits::cpu3.inst 126 # number of overall MSHR hits +system.cpu3.icache.overall_mshr_hits::total 126 # number of overall MSHR hits +system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 713 # number of ReadReq MSHR misses +system.cpu3.icache.ReadReq_mshr_misses::total 713 # number of ReadReq MSHR misses +system.cpu3.icache.demand_mshr_misses::cpu3.inst 713 # number of demand (read+write) MSHR misses +system.cpu3.icache.demand_mshr_misses::total 713 # number of demand (read+write) MSHR misses +system.cpu3.icache.overall_mshr_misses::cpu3.inst 713 # number of overall MSHR misses +system.cpu3.icache.overall_mshr_misses::total 713 # number of overall MSHR misses +system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 10107000 # number of ReadReq MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_latency::total 10107000 # number of ReadReq MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 10107000 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_latency::total 10107000 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 10107000 # number of overall MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_latency::total 10107000 # number of overall MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.021645 # mshr miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.021645 # mshr miss rate for ReadReq accesses +system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.021645 # mshr miss rate for demand accesses +system.cpu3.icache.demand_mshr_miss_rate::total 0.021645 # mshr miss rate for demand accesses +system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.021645 # mshr miss rate for overall accesses +system.cpu3.icache.overall_mshr_miss_rate::total 0.021645 # mshr miss rate for overall accesses +system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 14175.315568 # average ReadReq mshr miss latency +system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 14175.315568 # average ReadReq mshr miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 14175.315568 # average overall mshr miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency::total 14175.315568 # average overall mshr miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 14175.315568 # average overall mshr miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency::total 14175.315568 # average overall mshr miss latency +system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 123936000 # Cumulative time (in ticks) in various power states system.l2c.tags.replacements 0 # number of replacements -system.l2c.tags.tagsinuse 455.287968 # Cycle average of tags in use -system.l2c.tags.total_refs 3075 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 580 # 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Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 1.286758 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.inst 5.637625 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.data 1.160677 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.000012 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.004616 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.000898 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.001070 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.000085 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.000143 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.000020 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.inst 0.000086 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.data 0.000018 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.006947 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 580 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 116 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 408 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.008850 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 31874 # Number of tag accesses -system.l2c.tags.data_accesses 31874 # Number of data accesses -system.l2c.pwrStateResidencyTicks::UNDEFINED 124523000 # Cumulative time (in ticks) in various power states +system.l2c.tags.occ_blocks::cpu0.inst 303.185096 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 145.120224 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 69.165941 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 16.093016 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 8.947029 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 10.727803 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.inst 4.254567 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.data 9.793531 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::cpu0.inst 0.004626 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.002214 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.001055 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.000246 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.inst 0.000137 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.data 0.000164 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3.inst 0.000065 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3.data 0.000149 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.008656 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1024 709 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 167 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 487 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1024 0.010818 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 31781 # Number of tag accesses +system.l2c.tags.data_accesses 31781 # Number of data accesses +system.l2c.pwrStateResidencyTicks::UNDEFINED 123936000 # Cumulative time (in ticks) in various power states system.l2c.WritebackDirty_hits::writebacks 1 # number of WritebackDirty hits system.l2c.WritebackDirty_hits::total 1 # number of WritebackDirty hits -system.l2c.WritebackClean_hits::writebacks 709 # number of WritebackClean hits -system.l2c.WritebackClean_hits::total 709 # number of WritebackClean hits -system.l2c.UpgradeReq_hits::cpu0.data 3 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 3 # number of UpgradeReq hits -system.l2c.ReadCleanReq_hits::cpu0.inst 319 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu1.inst 617 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu2.inst 711 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu3.inst 686 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::total 2333 # number of ReadCleanReq hits +system.l2c.WritebackClean_hits::writebacks 719 # number of WritebackClean hits +system.l2c.WritebackClean_hits::total 719 # number of WritebackClean hits +system.l2c.UpgradeReq_hits::cpu0.data 24 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 19 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu2.data 22 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu3.data 23 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 88 # number of UpgradeReq hits +system.l2c.ReadCleanReq_hits::cpu0.inst 334 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu1.inst 594 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu2.inst 687 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu3.inst 700 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::total 2315 # number of ReadCleanReq hits system.l2c.ReadSharedReq_hits::cpu0.data 5 # number of ReadSharedReq hits system.l2c.ReadSharedReq_hits::cpu1.data 5 # number of ReadSharedReq hits system.l2c.ReadSharedReq_hits::cpu2.data 11 # number of ReadSharedReq hits system.l2c.ReadSharedReq_hits::cpu3.data 11 # number of ReadSharedReq hits system.l2c.ReadSharedReq_hits::total 32 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0.inst 319 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 334 # number of demand (read+write) hits system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 617 # 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number of overall hits +system.l2c.overall_hits::cpu1.inst 594 # number of overall hits system.l2c.overall_hits::cpu1.data 5 # number of overall hits -system.l2c.overall_hits::cpu2.inst 711 # number of overall hits +system.l2c.overall_hits::cpu2.inst 687 # number of overall hits system.l2c.overall_hits::cpu2.data 11 # number of overall hits -system.l2c.overall_hits::cpu3.inst 686 # number of overall hits +system.l2c.overall_hits::cpu3.inst 700 # number of overall hits system.l2c.overall_hits::cpu3.data 11 # number of overall hits -system.l2c.overall_hits::total 2365 # number of overall hits -system.l2c.UpgradeReq_misses::cpu0.data 21 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 20 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2.data 24 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu3.data 20 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 85 # number of UpgradeReq misses +system.l2c.overall_hits::total 2347 # number of overall hits system.l2c.ReadExReq_misses::cpu0.data 94 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu1.data 13 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu2.data 12 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu3.data 12 # number of ReadExReq misses system.l2c.ReadExReq_misses::total 131 # number of ReadExReq misses -system.l2c.ReadCleanReq_misses::cpu0.inst 377 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::cpu1.inst 96 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::cpu2.inst 22 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::cpu3.inst 15 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::total 510 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::cpu0.inst 379 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::cpu1.inst 93 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::cpu2.inst 23 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::cpu3.inst 13 # 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number of ReadSharedReq accesses(hits+misses) system.l2c.ReadSharedReq_accesses::cpu2.data 14 # number of ReadSharedReq accesses(hits+misses) system.l2c.ReadSharedReq_accesses::cpu3.data 13 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::total 122 # number of ReadSharedReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.inst 696 # number of demand (read+write) accesses +system.l2c.ReadSharedReq_accesses::total 121 # number of ReadSharedReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.inst 713 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu0.data 175 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 713 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 27 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.inst 733 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 687 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 26 # 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Number of requests hitting in the snoop filter with a single holder of the requested data. +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 67790.450928 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 65696.629213 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 94071.428571 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 76450 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 68337.755102 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 70519.736842 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 72312.500000 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 78333.333333 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 80500 # 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average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 67790.450928 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 72035.294118 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 65696.629213 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 70857.142857 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 94071.428571 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 70333.333333 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 76450 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.data 69857.142857 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 69369.718310 # average overall mshr miss latency +system.membus.snoop_filter.tot_requests 957 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 248 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 124523000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 582 # Transaction distribution -system.membus.trans_dist::UpgradeReq 274 # Transaction distribution -system.membus.trans_dist::ReadExReq 186 # Transaction distribution +system.membus.pwrStateResidencyTicks::UNDEFINED 123936000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 578 # Transaction distribution +system.membus.trans_dist::UpgradeReq 196 # Transaction distribution +system.membus.trans_dist::ReadExReq 183 # Transaction distribution system.membus.trans_dist::ReadExResp 131 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 582 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1755 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1755 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 45632 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 45632 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 244 # Total snoops (count) +system.membus.trans_dist::ReadSharedReq 578 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1666 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1666 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 45376 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 45376 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 248 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 1042 # Request fanout histogram +system.membus.snoop_fanout::samples 957 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 1042 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 957 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 1042 # Request fanout histogram -system.membus.reqLayer0.occupancy 989502 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 3800250 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 3.1 # Layer utilization (%) -system.toL2Bus.snoop_filter.tot_requests 6343 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 1724 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 3317 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_fanout::total 957 # Request fanout histogram +system.membus.reqLayer0.occupancy 877500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.7 # Layer utilization (%) +system.membus.respLayer1.occupancy 3778750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 3.0 # Layer utilization (%) +system.toL2Bus.snoop_filter.tot_requests 6322 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 1727 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 3289 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 124523000 # Cumulative time (in ticks) in various power states -system.toL2Bus.trans_dist::ReadResp 3517 # Transaction distribution -system.toL2Bus.trans_dist::ReadRespWithInvalidate 9 # Transaction distribution +system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 123936000 # Cumulative time (in ticks) in various power states +system.toL2Bus.trans_dist::ReadResp 3509 # Transaction distribution +system.toL2Bus.trans_dist::ReadRespWithInvalidate 3 # Transaction distribution system.toL2Bus.trans_dist::WritebackDirty 1 # Transaction distribution -system.toL2Bus.trans_dist::WritebackClean 2134 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 2125 # Transaction distribution system.toL2Bus.trans_dist::CleanEvict 1 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 277 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 277 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 403 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 403 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 2843 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 684 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1785 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 593 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 2005 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 377 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 2064 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 372 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 1965 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 365 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 9526 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 69696 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.trans_dist::UpgradeReq 284 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 284 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 398 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 398 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 2823 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 690 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1838 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 602 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1930 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 372 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 1998 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 378 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 2004 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 362 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 9484 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 72000 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 11264 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 82688 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1728 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 85184 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 79552 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1664 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 82432 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 1664 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 80896 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 82624 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 334720 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 1023 # Total snoops (count) -system.toL2Bus.snoopTraffic 53376 # Total snoop traffic (bytes) -system.toL2Bus.snoop_fanout::samples 4207 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.289042 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 1.099056 # Request fanout histogram +system.toL2Bus.pkt_size::total 332800 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 1032 # Total snoops (count) +system.toL2Bus.snoopTraffic 53504 # Total snoop traffic (bytes) +system.toL2Bus.snoop_fanout::samples 4195 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.291538 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 1.103863 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 1302 30.95% 30.95% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 1193 28.36% 59.31% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 906 21.54% 80.84% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 806 19.16% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 1306 31.13% 31.13% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 1176 28.03% 59.17% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 897 21.38% 80.55% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 816 19.45% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::5 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram @@ -2907,24 +2870,24 @@ system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Re system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 4207 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 5321969 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 4195 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 5296980 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 4.3 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1043498 # Layer occupancy (ticks) -system.toL2Bus.respLayer0.utilization 0.8 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 522987 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 1068997 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 0.9 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 528987 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 1072493 # Layer occupancy (ticks) -system.toL2Bus.respLayer2.utilization 0.9 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 443462 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 1032995 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.utilization 0.8 # Layer utilization (%) +system.toL2Bus.respLayer3.occupancy 438456 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.4 # Layer utilization (%) -system.toL2Bus.respLayer4.occupancy 1103489 # Layer occupancy (ticks) +system.toL2Bus.respLayer4.occupancy 1069486 # Layer occupancy (ticks) system.toL2Bus.respLayer4.utilization 0.9 # Layer utilization (%) -system.toL2Bus.respLayer5.occupancy 430971 # Layer occupancy (ticks) -system.toL2Bus.respLayer5.utilization 0.3 # Layer utilization (%) -system.toL2Bus.respLayer6.occupancy 1053495 # Layer occupancy (ticks) -system.toL2Bus.respLayer6.utilization 0.8 # Layer utilization (%) -system.toL2Bus.respLayer7.occupancy 426466 # Layer occupancy (ticks) +system.toL2Bus.respLayer5.occupancy 439965 # Layer occupancy (ticks) +system.toL2Bus.respLayer5.utilization 0.4 # Layer utilization (%) +system.toL2Bus.respLayer6.occupancy 1070997 # Layer occupancy (ticks) +system.toL2Bus.respLayer6.utilization 0.9 # Layer utilization (%) +system.toL2Bus.respLayer7.occupancy 415480 # Layer occupancy (ticks) system.toL2Bus.respLayer7.utilization 0.3 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt index 5019ecb02..fb2ceaeb2 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000088 # Nu sim_ticks 87707000 # Number of ticks simulated final_tick 87707000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 807732 # Simulator instruction rate (inst/s) -host_op_rate 807715 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 104588000 # Simulator tick rate (ticks/s) -host_mem_usage 259108 # Number of bytes of host memory used -host_seconds 0.84 # Real time elapsed on the host +host_inst_rate 428563 # Simulator instruction rate (inst/s) +host_op_rate 428559 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 55493138 # Simulator tick rate (ticks/s) +host_mem_usage 263740 # Number of bytes of host memory used +host_seconds 1.58 # Real time elapsed on the host sim_insts 677333 # Number of instructions simulated sim_ops 677333 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -749,43 +749,44 @@ system.cpu3.icache.writebacks::writebacks 279 # n system.cpu3.icache.writebacks::total 279 # number of writebacks system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states system.l2c.tags.replacements 0 # number of replacements -system.l2c.tags.tagsinuse 367.545675 # Cycle average of tags in use -system.l2c.tags.total_refs 1716 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 422 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 4.066351 # Average number of references to valid blocks. +system.l2c.tags.tagsinuse 498.606697 # Cycle average of tags in use +system.l2c.tags.total_refs 1799 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 559 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 3.218247 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 0.966439 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.inst 239.426226 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 56.170311 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 153.517433 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu1.inst 59.512205 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 6.721185 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 19.205787 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu2.inst 1.942787 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 0.935416 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 12.182505 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu3.inst 0.965459 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.data 0.905646 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.000015 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::cpu3.data 11.854293 # Average occupied blocks per requestor system.l2c.tags.occ_percent::cpu0.inst 0.003653 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.000857 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.002342 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.inst 0.000908 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.000103 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.000293 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu2.inst 0.000030 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.000014 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.data 0.000186 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu3.inst 0.000015 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.data 0.000014 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.005608 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 422 # Occupied blocks per task id +system.l2c.tags.occ_percent::cpu3.data 0.000181 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.007608 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1024 559 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 374 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.006439 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 19424 # Number of tag accesses -system.l2c.tags.data_accesses 19424 # Number of data accesses +system.l2c.tags.age_task_id_blocks_1024::1 511 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1024 0.008530 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 19423 # Number of tag accesses +system.l2c.tags.data_accesses 19423 # Number of data accesses system.l2c.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states system.l2c.WritebackDirty_hits::writebacks 1 # number of WritebackDirty hits system.l2c.WritebackDirty_hits::total 1 # number of WritebackDirty hits system.l2c.WritebackClean_hits::writebacks 495 # number of WritebackClean hits system.l2c.WritebackClean_hits::total 495 # number of WritebackClean hits -system.l2c.UpgradeReq_hits::cpu0.data 2 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 2 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu0.data 30 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 16 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu2.data 17 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu3.data 19 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 82 # number of UpgradeReq hits system.l2c.ReadCleanReq_hits::cpu0.inst 185 # number of ReadCleanReq hits system.l2c.ReadCleanReq_hits::cpu1.inst 296 # number of ReadCleanReq hits system.l2c.ReadCleanReq_hits::cpu2.inst 355 # number of ReadCleanReq hits @@ -814,11 +815,6 @@ system.l2c.overall_hits::cpu2.data 9 # nu system.l2c.overall_hits::cpu3.inst 358 # number of overall hits system.l2c.overall_hits::cpu3.data 9 # number of overall hits system.l2c.overall_hits::total 1220 # number of overall hits -system.l2c.UpgradeReq_misses::cpu0.data 28 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 16 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2.data 17 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu3.data 19 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 80 # number of UpgradeReq misses system.l2c.ReadExReq_misses::cpu0.data 99 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu1.data 13 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu2.data 12 # number of ReadExReq misses @@ -894,11 +890,6 @@ system.l2c.overall_accesses::cpu2.data 22 # nu system.l2c.overall_accesses::cpu3.inst 359 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu3.data 22 # number of overall (read+write) accesses system.l2c.overall_accesses::total 1779 # number of overall (read+write) accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.933333 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.975610 # miss rate for UpgradeReq accesses system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses @@ -938,35 +929,34 @@ system.l2c.blocked::no_mshrs 0 # nu system.l2c.blocked::no_targets 0 # number of cycles access was blocked system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.membus.snoop_filter.tot_requests 879 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 320 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 799 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 240 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 423 # Transaction distribution -system.membus.trans_dist::UpgradeReq 273 # Transaction distribution -system.membus.trans_dist::UpgradeResp 80 # Transaction distribution +system.membus.trans_dist::UpgradeReq 193 # Transaction distribution system.membus.trans_dist::ReadExReq 183 # Transaction distribution system.membus.trans_dist::ReadExResp 136 # Transaction distribution system.membus.trans_dist::ReadSharedReq 423 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1518 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1518 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1358 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1358 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 35776 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size::total 35776 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 879 # Request fanout histogram +system.membus.snoop_fanout::samples 799 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 879 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 799 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 879 # Request fanout histogram +system.membus.snoop_fanout::total 799 # Request fanout histogram system.toL2Bus.snoop_filter.tot_requests 3918 # Total number of requests made to the snoop filter. system.toL2Bus.snoop_filter.hit_single_requests 1221 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_requests 1709 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt index 78f5a0ee7..c1353f29d 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt @@ -1,94 +1,94 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000264 # Number of seconds simulated -sim_ticks 264174500 # Number of ticks simulated -final_tick 264174500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000263 # Number of seconds simulated +sim_ticks 263409500 # Number of ticks simulated +final_tick 263409500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 538178 # Simulator instruction rate (inst/s) -host_op_rate 538161 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 214299964 # Simulator tick rate (ticks/s) -host_mem_usage 259104 # Number of bytes of host memory used -host_seconds 1.23 # Real time elapsed on the host -sim_insts 663394 # Number of instructions simulated -sim_ops 663394 # Number of ops (including micro ops) simulated +host_inst_rate 389943 # Simulator instruction rate (inst/s) +host_op_rate 389940 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 154718592 # Simulator tick rate (ticks/s) +host_mem_usage 263736 # Number of bytes of host memory used +host_seconds 1.70 # Real time elapsed on the host +sim_insts 663871 # Number of instructions simulated +sim_ops 663871 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 264174500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu0.inst 18240 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.data 10560 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 448 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 640 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.data 960 # Number of bytes read from this memory system.physmem.bytes_read::cpu2.inst 3712 # Number of bytes read from this memory system.physmem.bytes_read::cpu2.data 1472 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.inst 256 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.inst 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu3.data 960 # Number of bytes read from this memory system.physmem.bytes_read::total 36608 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu0.inst 18240 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 448 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 640 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::cpu2.inst 3712 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu3.inst 256 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu3.inst 64 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 22656 # Number of instructions bytes read from this memory system.physmem.num_reads::cpu0.inst 285 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.data 165 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 7 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 10 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.data 15 # Number of read requests responded to by this memory system.physmem.num_reads::cpu2.inst 58 # Number of read requests responded to by this memory system.physmem.num_reads::cpu2.data 23 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.inst 4 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.inst 1 # Number of read requests responded to by this memory system.physmem.num_reads::cpu3.data 15 # Number of read requests responded to by this memory system.physmem.num_reads::total 572 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu0.inst 69045271 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 39973578 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 1695849 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 3633962 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 14051318 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 5572075 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.inst 969056 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.data 3633962 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 138575071 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 69045271 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 1695849 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 14051318 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu3.inst 969056 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 85761495 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 69045271 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 39973578 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 1695849 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 3633962 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 14051318 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 5572075 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.inst 969056 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.data 3633962 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 138575071 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 264174500 # Cumulative time (in ticks) in various power states +system.physmem.bw_read::cpu0.inst 69245794 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 40089670 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 2429677 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 3644515 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 14092127 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 5588257 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.inst 242968 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.data 3644515 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 138977524 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 69245794 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 2429677 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 14092127 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu3.inst 242968 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 86010565 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 69245794 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 40089670 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 2429677 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 3644515 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 14092127 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 5588257 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.inst 242968 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.data 3644515 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 138977524 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.workload.num_syscalls 89 # Number of system calls -system.cpu0.pwrStateResidencyTicks::ON 264174500 # Cumulative time (in ticks) in various power states -system.cpu0.numCycles 528349 # number of cpu cycles simulated +system.cpu0.pwrStateResidencyTicks::ON 263409500 # Cumulative time (in ticks) in various power states +system.cpu0.numCycles 526819 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 158268 # Number of instructions committed -system.cpu0.committedOps 158268 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 109004 # Number of integer alu accesses +system.cpu0.committedInsts 158244 # Number of instructions committed +system.cpu0.committedOps 158244 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 108988 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu0.num_func_calls 390 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 25981 # number of instructions that are conditional controls -system.cpu0.num_int_insts 109004 # number of integer instructions +system.cpu0.num_conditional_control_insts 25977 # number of instructions that are conditional controls +system.cpu0.num_int_insts 108988 # number of integer instructions system.cpu0.num_fp_insts 0 # number of float instructions -system.cpu0.num_int_register_reads 315170 # number of times the integer registers were read -system.cpu0.num_int_register_writes 110610 # number of times the integer registers were written +system.cpu0.num_int_register_reads 315122 # number of times the integer registers were read +system.cpu0.num_int_register_writes 110594 # number of times the integer registers were written system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu0.num_mem_refs 73868 # number of memory refs -system.cpu0.num_load_insts 48905 # Number of load instructions -system.cpu0.num_store_insts 24963 # Number of store instructions +system.cpu0.num_mem_refs 73856 # number of memory refs +system.cpu0.num_load_insts 48897 # Number of load instructions +system.cpu0.num_store_insts 24959 # Number of store instructions system.cpu0.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu0.num_busy_cycles 528348.998000 # Number of busy cycles +system.cpu0.num_busy_cycles 526818.998000 # Number of busy cycles system.cpu0.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu0.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu0.Branches 26846 # Number of branches fetched -system.cpu0.op_class::No_OpClass 23573 14.89% 14.89% # Class of executed instruction -system.cpu0.op_class::IntAlu 60805 38.40% 53.29% # Class of executed instruction +system.cpu0.Branches 26842 # Number of branches fetched +system.cpu0.op_class::No_OpClass 23569 14.89% 14.89% # Class of executed instruction +system.cpu0.op_class::IntAlu 60797 38.40% 53.29% # Class of executed instruction system.cpu0.op_class::IntMult 0 0.00% 53.29% # Class of executed instruction system.cpu0.op_class::IntDiv 0 0.00% 53.29% # Class of executed instruction system.cpu0.op_class::FloatAdd 0 0.00% 53.29% # Class of executed instruction @@ -117,38 +117,38 @@ system.cpu0.op_class::SimdFloatMisc 0 0.00% 53.29% # Cl system.cpu0.op_class::SimdFloatMult 0 0.00% 53.29% # Class of executed instruction system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 53.29% # Class of executed instruction system.cpu0.op_class::SimdFloatSqrt 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::MemRead 48989 30.94% 84.23% # Class of executed instruction -system.cpu0.op_class::MemWrite 24963 15.77% 100.00% # Class of executed instruction +system.cpu0.op_class::MemRead 48981 30.94% 84.23% # Class of executed instruction +system.cpu0.op_class::MemWrite 24959 15.77% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 158330 # Class of executed instruction -system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 264174500 # Cumulative time (in ticks) in various power states +system.cpu0.op_class::total 158306 # Class of executed instruction +system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states system.cpu0.dcache.tags.replacements 2 # number of replacements -system.cpu0.dcache.tags.tagsinuse 144.970648 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 73336 # Total number of references to valid blocks. +system.cpu0.dcache.tags.tagsinuse 144.946606 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 73324 # Total number of references to valid blocks. system.cpu0.dcache.tags.sampled_refs 167 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 439.137725 # Average number of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 439.065868 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 144.970648 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.283146 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.283146 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 144.946606 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.283099 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.283099 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 165 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 149 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 0.322266 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 295705 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 295705 # Number of data accesses -system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 264174500 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.ReadReq_hits::cpu0.data 48725 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 48725 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 24729 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 24729 # number of WriteReq hits +system.cpu0.dcache.tags.tag_accesses 295657 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 295657 # Number of data accesses +system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.ReadReq_hits::cpu0.data 48717 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 48717 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 24725 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 24725 # number of WriteReq hits system.cpu0.dcache.SwapReq_hits::cpu0.data 16 # number of SwapReq hits system.cpu0.dcache.SwapReq_hits::total 16 # number of SwapReq hits -system.cpu0.dcache.demand_hits::cpu0.data 73454 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 73454 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 73454 # number of overall hits -system.cpu0.dcache.overall_hits::total 73454 # number of overall hits +system.cpu0.dcache.demand_hits::cpu0.data 73442 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 73442 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 73442 # number of overall hits +system.cpu0.dcache.overall_hits::total 73442 # number of overall hits system.cpu0.dcache.ReadReq_misses::cpu0.data 170 # number of ReadReq misses system.cpu0.dcache.ReadReq_misses::total 170 # number of ReadReq misses system.cpu0.dcache.WriteReq_misses::cpu0.data 183 # number of WriteReq misses @@ -159,46 +159,46 @@ system.cpu0.dcache.demand_misses::cpu0.data 353 # system.cpu0.dcache.demand_misses::total 353 # number of demand (read+write) misses system.cpu0.dcache.overall_misses::cpu0.data 353 # number of overall misses system.cpu0.dcache.overall_misses::total 353 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 4908500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 4908500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 7106500 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 7106500 # number of WriteReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 4701000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 4701000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 6585500 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 6585500 # number of WriteReq miss cycles system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 400000 # number of SwapReq miss cycles system.cpu0.dcache.SwapReq_miss_latency::total 400000 # number of SwapReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 12015000 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 12015000 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 12015000 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 12015000 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 48895 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 48895 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 24912 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 24912 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.demand_miss_latency::cpu0.data 11286500 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 11286500 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 11286500 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 11286500 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 48887 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 48887 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 24908 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 24908 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses) system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 73807 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 73807 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 73807 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 73807 # number of overall (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu0.data 73795 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 73795 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 73795 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 73795 # number of overall (read+write) accesses system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.003477 # miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_miss_rate::total 0.003477 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007346 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.007346 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007347 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.007347 # miss rate for WriteReq accesses system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.619048 # miss rate for SwapReq accesses system.cpu0.dcache.SwapReq_miss_rate::total 0.619048 # miss rate for SwapReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.004783 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.004783 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.004783 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.004783 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 28873.529412 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 28873.529412 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38833.333333 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 38833.333333 # average WriteReq miss latency +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.004784 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.004784 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.004784 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.004784 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 27652.941176 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 27652.941176 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 35986.338798 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 35986.338798 # average WriteReq miss latency system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 15384.615385 # average SwapReq miss latency system.cpu0.dcache.SwapReq_avg_miss_latency::total 15384.615385 # average SwapReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 34036.827195 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 34036.827195 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 34036.827195 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 34036.827195 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 31973.087819 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 31973.087819 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 31973.087819 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 31973.087819 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -217,89 +217,89 @@ system.cpu0.dcache.demand_mshr_misses::cpu0.data 353 system.cpu0.dcache.demand_mshr_misses::total 353 # number of demand (read+write) MSHR misses system.cpu0.dcache.overall_mshr_misses::cpu0.data 353 # number of overall MSHR misses system.cpu0.dcache.overall_mshr_misses::total 353 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4738500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4738500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6923500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6923500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4531000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4531000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6402500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6402500 # number of WriteReq MSHR miss cycles system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 374000 # number of SwapReq MSHR miss cycles system.cpu0.dcache.SwapReq_mshr_miss_latency::total 374000 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11662000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 11662000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 11662000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 11662000 # number of overall MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10933500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 10933500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10933500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 10933500 # number of overall MSHR miss cycles system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.003477 # mshr miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.003477 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.007346 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.007346 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.007347 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.007347 # mshr miss rate for WriteReq accesses system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.619048 # mshr miss rate for SwapReq accesses system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.619048 # mshr miss rate for SwapReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.004783 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.004783 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.004783 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.004783 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 27873.529412 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 27873.529412 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 37833.333333 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 37833.333333 # average WriteReq mshr miss latency +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.004784 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.004784 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.004784 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.004784 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26652.941176 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26652.941176 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 34986.338798 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 34986.338798 # average WriteReq mshr miss latency system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 14384.615385 # average SwapReq mshr miss latency system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 14384.615385 # average SwapReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 33036.827195 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 33036.827195 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 33036.827195 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 33036.827195 # average overall mshr miss latency -system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 264174500 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 30973.087819 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 30973.087819 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 30973.087819 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 30973.087819 # average overall mshr miss latency +system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states system.cpu0.icache.tags.replacements 215 # number of replacements -system.cpu0.icache.tags.tagsinuse 211.220090 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 157864 # Total number of references to valid blocks. +system.cpu0.icache.tags.tagsinuse 211.173601 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 157840 # Total number of references to valid blocks. system.cpu0.icache.tags.sampled_refs 467 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 338.038544 # Average number of references to valid blocks. +system.cpu0.icache.tags.avg_refs 337.987152 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 211.220090 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.412539 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.412539 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_blocks::cpu0.inst 211.173601 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.412448 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.412448 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 252 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::2 199 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 0.492188 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 158798 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 158798 # Number of data accesses -system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 264174500 # Cumulative time (in ticks) in various power states -system.cpu0.icache.ReadReq_hits::cpu0.inst 157864 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 157864 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 157864 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 157864 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 157864 # number of overall hits -system.cpu0.icache.overall_hits::total 157864 # number of overall hits +system.cpu0.icache.tags.tag_accesses 158774 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 158774 # Number of data accesses +system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states +system.cpu0.icache.ReadReq_hits::cpu0.inst 157840 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 157840 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 157840 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 157840 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 157840 # number of overall hits +system.cpu0.icache.overall_hits::total 157840 # number of overall hits system.cpu0.icache.ReadReq_misses::cpu0.inst 467 # number of ReadReq misses system.cpu0.icache.ReadReq_misses::total 467 # number of ReadReq misses system.cpu0.icache.demand_misses::cpu0.inst 467 # number of demand (read+write) misses system.cpu0.icache.demand_misses::total 467 # number of demand (read+write) misses system.cpu0.icache.overall_misses::cpu0.inst 467 # number of overall misses system.cpu0.icache.overall_misses::total 467 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 20426500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 20426500 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 20426500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 20426500 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 20426500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 20426500 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 158331 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 158331 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 158331 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 158331 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 158331 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 158331 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 20426000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 20426000 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 20426000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 20426000 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 20426000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 20426000 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 158307 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 158307 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 158307 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 158307 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 158307 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 158307 # number of overall (read+write) accesses system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.002950 # miss rate for ReadReq accesses system.cpu0.icache.ReadReq_miss_rate::total 0.002950 # miss rate for ReadReq accesses system.cpu0.icache.demand_miss_rate::cpu0.inst 0.002950 # miss rate for demand accesses system.cpu0.icache.demand_miss_rate::total 0.002950 # miss rate for demand accesses system.cpu0.icache.overall_miss_rate::cpu0.inst 0.002950 # miss rate for overall accesses system.cpu0.icache.overall_miss_rate::total 0.002950 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 43739.828694 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 43739.828694 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 43739.828694 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 43739.828694 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 43739.828694 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 43739.828694 # average overall miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 43738.758030 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 43738.758030 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 43738.758030 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 43738.758030 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 43738.758030 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 43738.758030 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -314,260 +314,260 @@ system.cpu0.icache.demand_mshr_misses::cpu0.inst 467 system.cpu0.icache.demand_mshr_misses::total 467 # number of demand (read+write) MSHR misses system.cpu0.icache.overall_mshr_misses::cpu0.inst 467 # number of overall MSHR misses system.cpu0.icache.overall_mshr_misses::total 467 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 19959500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 19959500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 19959500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 19959500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 19959500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 19959500 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 19959000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 19959000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 19959000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 19959000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 19959000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 19959000 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.002950 # mshr miss rate for ReadReq accesses system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.002950 # mshr miss rate for ReadReq accesses system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.002950 # mshr miss rate for demand accesses system.cpu0.icache.demand_mshr_miss_rate::total 0.002950 # mshr miss rate for demand accesses system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.002950 # mshr miss rate for overall accesses system.cpu0.icache.overall_mshr_miss_rate::total 0.002950 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 42739.828694 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 42739.828694 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 42739.828694 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 42739.828694 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 42739.828694 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 42739.828694 # average overall mshr miss latency -system.cpu1.pwrStateResidencyTicks::ON 264174500 # Cumulative time (in ticks) in various power states -system.cpu1.numCycles 528348 # number of cpu cycles simulated +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 42738.758030 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 42738.758030 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 42738.758030 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 42738.758030 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 42738.758030 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 42738.758030 # average overall mshr miss latency +system.cpu1.pwrStateResidencyTicks::ON 263409500 # Cumulative time (in ticks) in various power states +system.cpu1.numCycles 526818 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 170000 # Number of instructions committed -system.cpu1.committedOps 170000 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 111041 # Number of integer alu accesses +system.cpu1.committedInsts 169340 # Number of instructions committed +system.cpu1.committedOps 169340 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 111465 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu1.num_func_calls 637 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 33487 # number of instructions that are conditional controls -system.cpu1.num_int_insts 111041 # number of integer instructions +system.cpu1.num_conditional_control_insts 32946 # number of instructions that are conditional controls +system.cpu1.num_int_insts 111465 # number of integer instructions system.cpu1.num_fp_insts 0 # number of float instructions -system.cpu1.num_int_register_reads 272446 # number of times the integer registers were read -system.cpu1.num_int_register_writes 102959 # number of times the integer registers were written +system.cpu1.num_int_register_reads 276307 # number of times the integer registers were read +system.cpu1.num_int_register_writes 104671 # number of times the integer registers were written system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu1.num_mem_refs 53722 # number of memory refs -system.cpu1.num_load_insts 41185 # Number of load instructions -system.cpu1.num_store_insts 12537 # Number of store instructions -system.cpu1.num_idle_cycles 74693.860345 # Number of idle cycles -system.cpu1.num_busy_cycles 453654.139655 # Number of busy cycles -system.cpu1.not_idle_fraction 0.858628 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.141372 # Percentage of idle cycles -system.cpu1.Branches 35142 # Number of branches fetched -system.cpu1.op_class::No_OpClass 25921 15.24% 15.24% # Class of executed instruction -system.cpu1.op_class::IntAlu 74786 43.98% 59.23% # Class of executed instruction -system.cpu1.op_class::IntMult 0 0.00% 59.23% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 59.23% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 59.23% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 59.23% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 59.23% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 59.23% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 59.23% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 59.23% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 59.23% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 59.23% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 59.23% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 59.23% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 59.23% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 59.23% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 59.23% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 59.23% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 59.23% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 59.23% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 59.23% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 59.23% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 59.23% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 59.23% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 59.23% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 59.23% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 0 0.00% 59.23% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 59.23% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 59.23% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 59.23% # Class of executed instruction -system.cpu1.op_class::MemRead 56788 33.40% 92.63% # Class of executed instruction -system.cpu1.op_class::MemWrite 12537 7.37% 100.00% # Class of executed instruction +system.cpu1.num_mem_refs 54688 # number of memory refs +system.cpu1.num_load_insts 41399 # Number of load instructions +system.cpu1.num_store_insts 13289 # Number of store instructions +system.cpu1.num_idle_cycles 74658.860000 # Number of idle cycles +system.cpu1.num_busy_cycles 452159.140000 # Number of busy cycles +system.cpu1.not_idle_fraction 0.858283 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.141717 # Percentage of idle cycles +system.cpu1.Branches 34599 # Number of branches fetched +system.cpu1.op_class::No_OpClass 25380 14.98% 14.98% # Class of executed instruction +system.cpu1.op_class::IntAlu 74993 44.28% 59.26% # Class of executed instruction +system.cpu1.op_class::IntMult 0 0.00% 59.26% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 59.26% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 59.26% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 59.26% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 59.26% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 59.26% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 59.26% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 59.26% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 59.26% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 59.26% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 59.26% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 59.26% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 59.26% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 59.26% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 59.26% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 59.26% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 59.26% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 59.26% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 59.26% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 59.26% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 59.26% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 59.26% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 59.26% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 59.26% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 0 0.00% 59.26% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 59.26% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 59.26% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 59.26% # Class of executed instruction +system.cpu1.op_class::MemRead 55710 32.89% 92.15% # Class of executed instruction +system.cpu1.op_class::MemWrite 13289 7.85% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 170032 # Class of executed instruction -system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 264174500 # Cumulative time (in ticks) in various power states +system.cpu1.op_class::total 169372 # Class of executed instruction +system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states system.cpu1.dcache.tags.replacements 0 # number of replacements -system.cpu1.dcache.tags.tagsinuse 26.444551 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 27473 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 30 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 915.766667 # Average number of references to valid blocks. +system.cpu1.dcache.tags.tagsinuse 26.434544 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 28854 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 994.965517 # Average number of references to valid blocks. system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 26.444551 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.051650 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.051650 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 30 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_blocks::cpu1.data 26.434544 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.051630 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.051630 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.058594 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 215113 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 215113 # Number of data accesses -system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 264174500 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.ReadReq_hits::cpu1.data 41008 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 41008 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 12359 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 12359 # number of WriteReq hits +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 218970 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 218970 # Number of data accesses +system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.ReadReq_hits::cpu1.data 41227 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 41227 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 13113 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 13113 # number of WriteReq hits system.cpu1.dcache.SwapReq_hits::cpu1.data 13 # number of SwapReq hits system.cpu1.dcache.SwapReq_hits::total 13 # number of SwapReq hits -system.cpu1.dcache.demand_hits::cpu1.data 53367 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 53367 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 53367 # number of overall hits -system.cpu1.dcache.overall_hits::total 53367 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 169 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 169 # number of ReadReq misses +system.cpu1.dcache.demand_hits::cpu1.data 54340 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 54340 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 54340 # number of overall hits +system.cpu1.dcache.overall_hits::total 54340 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 164 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 164 # number of ReadReq misses system.cpu1.dcache.WriteReq_misses::cpu1.data 105 # number of WriteReq misses system.cpu1.dcache.WriteReq_misses::total 105 # number of WriteReq misses -system.cpu1.dcache.SwapReq_misses::cpu1.data 58 # number of SwapReq misses -system.cpu1.dcache.SwapReq_misses::total 58 # number of SwapReq misses -system.cpu1.dcache.demand_misses::cpu1.data 274 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 274 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 274 # number of overall misses -system.cpu1.dcache.overall_misses::total 274 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1910000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 1910000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1724000 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 1724000 # number of WriteReq miss cycles -system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 260500 # number of SwapReq miss cycles -system.cpu1.dcache.SwapReq_miss_latency::total 260500 # number of SwapReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 3634000 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 3634000 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 3634000 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 3634000 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 41177 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 41177 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 12464 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 12464 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SwapReq_accesses::cpu1.data 71 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.SwapReq_accesses::total 71 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 53641 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 53641 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 53641 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 53641 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.004104 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.004104 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.008424 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.008424 # miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.816901 # miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_miss_rate::total 0.816901 # miss rate for SwapReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.005108 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.005108 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.005108 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.005108 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 11301.775148 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 11301.775148 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 16419.047619 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 16419.047619 # average WriteReq miss latency -system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 4491.379310 # average SwapReq miss latency -system.cpu1.dcache.SwapReq_avg_miss_latency::total 4491.379310 # average SwapReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 13262.773723 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 13262.773723 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 13262.773723 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 13262.773723 # average overall miss latency +system.cpu1.dcache.SwapReq_misses::cpu1.data 56 # number of SwapReq misses +system.cpu1.dcache.SwapReq_misses::total 56 # number of SwapReq misses +system.cpu1.dcache.demand_misses::cpu1.data 269 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 269 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 269 # number of overall misses +system.cpu1.dcache.overall_misses::total 269 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1132500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 1132500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1426000 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 1426000 # number of WriteReq miss cycles +system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 250000 # number of SwapReq miss cycles +system.cpu1.dcache.SwapReq_miss_latency::total 250000 # number of SwapReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 2558500 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 2558500 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 2558500 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 2558500 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 41391 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 41391 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 13218 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 13218 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_accesses::cpu1.data 69 # number of SwapReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_accesses::total 69 # number of SwapReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 54609 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 54609 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 54609 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 54609 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.003962 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.003962 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.007944 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.007944 # miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.811594 # miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_miss_rate::total 0.811594 # miss rate for SwapReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.004926 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.004926 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.004926 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.004926 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 6905.487805 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 6905.487805 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 13580.952381 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 13580.952381 # average WriteReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 4464.285714 # average SwapReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::total 4464.285714 # average SwapReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 9511.152416 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 9511.152416 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 9511.152416 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 9511.152416 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 169 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 169 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 164 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 164 # number of ReadReq MSHR misses system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 105 # number of WriteReq MSHR misses system.cpu1.dcache.WriteReq_mshr_misses::total 105 # number of WriteReq MSHR misses -system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 58 # number of SwapReq MSHR misses -system.cpu1.dcache.SwapReq_mshr_misses::total 58 # number of SwapReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 274 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 274 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 274 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 274 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1741000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1741000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1619000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1619000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 202500 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::total 202500 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3360000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 3360000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3360000 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 3360000 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.004104 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.004104 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.008424 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.008424 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.816901 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.816901 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.005108 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.005108 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.005108 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.005108 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10301.775148 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10301.775148 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 15419.047619 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 15419.047619 # average WriteReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 3491.379310 # average SwapReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 3491.379310 # average SwapReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12262.773723 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12262.773723 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 12262.773723 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12262.773723 # average overall mshr miss latency -system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 264174500 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 56 # number of SwapReq MSHR misses +system.cpu1.dcache.SwapReq_mshr_misses::total 56 # number of SwapReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 269 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 269 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 269 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 269 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 968500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 968500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1321000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1321000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 194000 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::total 194000 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2289500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 2289500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2289500 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 2289500 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003962 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003962 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.007944 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.007944 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.811594 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.811594 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.004926 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.004926 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.004926 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.004926 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 5905.487805 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 5905.487805 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 12580.952381 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 12580.952381 # average WriteReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 3464.285714 # average SwapReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 3464.285714 # average SwapReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 8511.152416 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 8511.152416 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 8511.152416 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 8511.152416 # average overall mshr miss latency +system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states system.cpu1.icache.tags.replacements 280 # number of replacements -system.cpu1.icache.tags.tagsinuse 66.843295 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 169667 # Total number of references to valid blocks. +system.cpu1.icache.tags.tagsinuse 66.813763 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 169007 # Total number of references to valid blocks. system.cpu1.icache.tags.sampled_refs 366 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 463.571038 # Average number of references to valid blocks. +system.cpu1.icache.tags.avg_refs 461.767760 # Average number of references to valid blocks. system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 66.843295 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.130553 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.130553 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_blocks::cpu1.inst 66.813763 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.130496 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.130496 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 86 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 0.167969 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 170399 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 170399 # Number of data accesses -system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 264174500 # Cumulative time (in ticks) in various power states -system.cpu1.icache.ReadReq_hits::cpu1.inst 169667 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 169667 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 169667 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 169667 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 169667 # number of overall hits -system.cpu1.icache.overall_hits::total 169667 # number of overall hits +system.cpu1.icache.tags.tag_accesses 169739 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 169739 # Number of data accesses +system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states +system.cpu1.icache.ReadReq_hits::cpu1.inst 169007 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 169007 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 169007 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 169007 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 169007 # number of overall hits +system.cpu1.icache.overall_hits::total 169007 # number of overall hits system.cpu1.icache.ReadReq_misses::cpu1.inst 366 # number of ReadReq misses system.cpu1.icache.ReadReq_misses::total 366 # number of ReadReq misses system.cpu1.icache.demand_misses::cpu1.inst 366 # number of demand (read+write) misses system.cpu1.icache.demand_misses::total 366 # number of demand (read+write) misses system.cpu1.icache.overall_misses::cpu1.inst 366 # number of overall misses system.cpu1.icache.overall_misses::total 366 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5695000 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 5695000 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 5695000 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 5695000 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 5695000 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 5695000 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 170033 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 170033 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 170033 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 170033 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 170033 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 170033 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.002153 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.002153 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.002153 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.002153 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.002153 # 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number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 5703000 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 5703000 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 169373 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 169373 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 169373 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 169373 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 169373 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 169373 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.002161 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.002161 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.002161 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.002161 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.002161 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.002161 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15581.967213 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 15581.967213 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15581.967213 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 15581.967213 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15581.967213 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 15581.967213 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -582,260 +582,260 @@ system.cpu1.icache.demand_mshr_misses::cpu1.inst 366 system.cpu1.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses system.cpu1.icache.overall_mshr_misses::cpu1.inst 366 # number of overall MSHR misses system.cpu1.icache.overall_mshr_misses::total 366 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5329000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 5329000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5329000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 5329000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5329000 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 5329000 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.002153 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.002153 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.002153 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.002153 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.002153 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.002153 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 14560.109290 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 14560.109290 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 14560.109290 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 14560.109290 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 14560.109290 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 14560.109290 # average overall mshr miss latency -system.cpu2.pwrStateResidencyTicks::ON 264174500 # Cumulative time (in ticks) in various power states -system.cpu2.numCycles 528349 # number of cpu cycles simulated +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5337000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 5337000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5337000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 5337000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5337000 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 5337000 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.002161 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.002161 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.002161 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.002161 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.002161 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.002161 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 14581.967213 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 14581.967213 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 14581.967213 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 14581.967213 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 14581.967213 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 14581.967213 # average overall mshr miss latency +system.cpu2.pwrStateResidencyTicks::ON 263409500 # Cumulative time (in ticks) in various power states +system.cpu2.numCycles 526819 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.committedInsts 165687 # Number of instructions committed -system.cpu2.committedOps 165687 # Number of ops (including micro ops) committed -system.cpu2.num_int_alu_accesses 110528 # Number of integer alu accesses +system.cpu2.committedInsts 165892 # Number of instructions committed +system.cpu2.committedOps 165892 # Number of ops (including micro ops) committed +system.cpu2.num_int_alu_accesses 110657 # Number of integer alu accesses system.cpu2.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu2.num_func_calls 637 # number of times a function call or return occured -system.cpu2.num_conditional_control_insts 31586 # number of instructions that are conditional controls -system.cpu2.num_int_insts 110528 # number of integer instructions +system.cpu2.num_conditional_control_insts 31626 # number of instructions that are conditional controls +system.cpu2.num_int_insts 110657 # number of integer instructions system.cpu2.num_fp_insts 0 # number of float instructions -system.cpu2.num_int_register_reads 278004 # number of times the integer registers were read -system.cpu2.num_int_register_writes 105995 # number of times the integer registers were written +system.cpu2.num_int_register_reads 278357 # number of times the integer registers were read +system.cpu2.num_int_register_writes 106099 # number of times the integer registers were written system.cpu2.num_fp_register_reads 0 # number of times the floating registers were read system.cpu2.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu2.num_mem_refs 55111 # number of memory refs -system.cpu2.num_load_insts 40928 # Number of load instructions -system.cpu2.num_store_insts 14183 # Number of store instructions -system.cpu2.num_idle_cycles 74966.001716 # Number of idle cycles -system.cpu2.num_busy_cycles 453382.998284 # Number of busy cycles -system.cpu2.not_idle_fraction 0.858113 # Percentage of non-idle cycles -system.cpu2.idle_fraction 0.141887 # Percentage of idle cycles -system.cpu2.Branches 33243 # Number of branches fetched -system.cpu2.op_class::No_OpClass 24020 14.49% 14.49% # Class of executed instruction -system.cpu2.op_class::IntAlu 74533 44.98% 59.47% # Class of executed instruction -system.cpu2.op_class::IntMult 0 0.00% 59.47% # Class of executed instruction -system.cpu2.op_class::IntDiv 0 0.00% 59.47% # Class of executed instruction -system.cpu2.op_class::FloatAdd 0 0.00% 59.47% # Class of executed instruction -system.cpu2.op_class::FloatCmp 0 0.00% 59.47% # Class of executed instruction -system.cpu2.op_class::FloatCvt 0 0.00% 59.47% # Class of executed instruction -system.cpu2.op_class::FloatMult 0 0.00% 59.47% # Class of executed instruction -system.cpu2.op_class::FloatDiv 0 0.00% 59.47% # Class of executed instruction -system.cpu2.op_class::FloatSqrt 0 0.00% 59.47% # Class of executed instruction -system.cpu2.op_class::SimdAdd 0 0.00% 59.47% # Class of executed instruction -system.cpu2.op_class::SimdAddAcc 0 0.00% 59.47% # Class of executed instruction -system.cpu2.op_class::SimdAlu 0 0.00% 59.47% # Class of executed instruction -system.cpu2.op_class::SimdCmp 0 0.00% 59.47% # Class of executed instruction -system.cpu2.op_class::SimdCvt 0 0.00% 59.47% # Class of executed instruction -system.cpu2.op_class::SimdMisc 0 0.00% 59.47% # Class of executed instruction -system.cpu2.op_class::SimdMult 0 0.00% 59.47% # Class of executed instruction -system.cpu2.op_class::SimdMultAcc 0 0.00% 59.47% # Class of executed instruction -system.cpu2.op_class::SimdShift 0 0.00% 59.47% # Class of executed instruction -system.cpu2.op_class::SimdShiftAcc 0 0.00% 59.47% # Class of executed instruction -system.cpu2.op_class::SimdSqrt 0 0.00% 59.47% # Class of executed instruction -system.cpu2.op_class::SimdFloatAdd 0 0.00% 59.47% # Class of executed instruction -system.cpu2.op_class::SimdFloatAlu 0 0.00% 59.47% # Class of executed instruction -system.cpu2.op_class::SimdFloatCmp 0 0.00% 59.47% # Class of executed instruction -system.cpu2.op_class::SimdFloatCvt 0 0.00% 59.47% # Class of executed instruction -system.cpu2.op_class::SimdFloatDiv 0 0.00% 59.47% # Class of executed instruction -system.cpu2.op_class::SimdFloatMisc 0 0.00% 59.47% # Class of executed instruction -system.cpu2.op_class::SimdFloatMult 0 0.00% 59.47% # Class of executed instruction -system.cpu2.op_class::SimdFloatMultAcc 0 0.00% 59.47% # Class of executed instruction -system.cpu2.op_class::SimdFloatSqrt 0 0.00% 59.47% # Class of executed instruction -system.cpu2.op_class::MemRead 52983 31.97% 91.44% # Class of executed instruction -system.cpu2.op_class::MemWrite 14183 8.56% 100.00% # Class of executed instruction +system.cpu2.num_mem_refs 55200 # number of memory refs +system.cpu2.num_load_insts 40995 # Number of load instructions +system.cpu2.num_store_insts 14205 # Number of store instructions +system.cpu2.num_idle_cycles 74930.001716 # Number of idle cycles +system.cpu2.num_busy_cycles 451888.998284 # Number of busy cycles +system.cpu2.not_idle_fraction 0.857769 # Percentage of non-idle cycles +system.cpu2.idle_fraction 0.142231 # Percentage of idle cycles +system.cpu2.Branches 33279 # Number of branches fetched +system.cpu2.op_class::No_OpClass 24060 14.50% 14.50% # Class of executed instruction +system.cpu2.op_class::IntAlu 74589 44.95% 59.45% # Class of executed instruction +system.cpu2.op_class::IntMult 0 0.00% 59.45% # Class of executed instruction +system.cpu2.op_class::IntDiv 0 0.00% 59.45% # Class of executed instruction +system.cpu2.op_class::FloatAdd 0 0.00% 59.45% # Class of executed instruction +system.cpu2.op_class::FloatCmp 0 0.00% 59.45% # Class of executed instruction +system.cpu2.op_class::FloatCvt 0 0.00% 59.45% # Class of executed instruction +system.cpu2.op_class::FloatMult 0 0.00% 59.45% # Class of executed instruction +system.cpu2.op_class::FloatDiv 0 0.00% 59.45% # Class of executed instruction +system.cpu2.op_class::FloatSqrt 0 0.00% 59.45% # Class of executed instruction +system.cpu2.op_class::SimdAdd 0 0.00% 59.45% # Class of executed instruction +system.cpu2.op_class::SimdAddAcc 0 0.00% 59.45% # Class of executed instruction +system.cpu2.op_class::SimdAlu 0 0.00% 59.45% # Class of executed instruction +system.cpu2.op_class::SimdCmp 0 0.00% 59.45% # Class of executed instruction +system.cpu2.op_class::SimdCvt 0 0.00% 59.45% # Class of executed instruction +system.cpu2.op_class::SimdMisc 0 0.00% 59.45% # Class of executed instruction +system.cpu2.op_class::SimdMult 0 0.00% 59.45% # Class of executed instruction +system.cpu2.op_class::SimdMultAcc 0 0.00% 59.45% # Class of executed instruction +system.cpu2.op_class::SimdShift 0 0.00% 59.45% # Class of executed instruction +system.cpu2.op_class::SimdShiftAcc 0 0.00% 59.45% # Class of executed instruction +system.cpu2.op_class::SimdSqrt 0 0.00% 59.45% # Class of executed instruction +system.cpu2.op_class::SimdFloatAdd 0 0.00% 59.45% # Class of executed instruction +system.cpu2.op_class::SimdFloatAlu 0 0.00% 59.45% # Class of executed instruction +system.cpu2.op_class::SimdFloatCmp 0 0.00% 59.45% # Class of executed instruction +system.cpu2.op_class::SimdFloatCvt 0 0.00% 59.45% # Class of executed instruction +system.cpu2.op_class::SimdFloatDiv 0 0.00% 59.45% # Class of executed instruction +system.cpu2.op_class::SimdFloatMisc 0 0.00% 59.45% # Class of executed instruction +system.cpu2.op_class::SimdFloatMult 0 0.00% 59.45% # Class of executed instruction +system.cpu2.op_class::SimdFloatMultAcc 0 0.00% 59.45% # Class of executed instruction +system.cpu2.op_class::SimdFloatSqrt 0 0.00% 59.45% # Class of executed instruction +system.cpu2.op_class::MemRead 53070 31.98% 91.44% # Class of executed instruction +system.cpu2.op_class::MemWrite 14205 8.56% 100.00% # Class of executed instruction system.cpu2.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu2.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu2.op_class::total 165719 # Class of executed instruction -system.cpu2.dcache.tags.pwrStateResidencyTicks::UNDEFINED 264174500 # Cumulative time (in ticks) in various power states +system.cpu2.op_class::total 165924 # Class of executed instruction +system.cpu2.dcache.tags.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states system.cpu2.dcache.tags.replacements 0 # number of replacements -system.cpu2.dcache.tags.tagsinuse 27.447331 # Cycle average of tags in use -system.cpu2.dcache.tags.total_refs 30642 # Total number of references to valid blocks. +system.cpu2.dcache.tags.tagsinuse 27.420509 # Cycle average of tags in use +system.cpu2.dcache.tags.total_refs 30687 # Total number of references to valid blocks. system.cpu2.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. -system.cpu2.dcache.tags.avg_refs 1056.620690 # Average number of references to valid blocks. +system.cpu2.dcache.tags.avg_refs 1058.172414 # Average number of references to valid blocks. system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.dcache.tags.occ_blocks::cpu2.data 27.447331 # Average occupied blocks per requestor -system.cpu2.dcache.tags.occ_percent::cpu2.data 0.053608 # Average percentage of cache occupancy -system.cpu2.dcache.tags.occ_percent::total 0.053608 # Average percentage of cache occupancy +system.cpu2.dcache.tags.occ_blocks::cpu2.data 27.420509 # Average occupied blocks per requestor +system.cpu2.dcache.tags.occ_percent::cpu2.data 0.053556 # Average percentage of cache occupancy +system.cpu2.dcache.tags.occ_percent::total 0.053556 # Average percentage of cache occupancy system.cpu2.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id system.cpu2.dcache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id system.cpu2.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id system.cpu2.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id -system.cpu2.dcache.tags.tag_accesses 220669 # Number of tag accesses -system.cpu2.dcache.tags.data_accesses 220669 # Number of data accesses -system.cpu2.dcache.pwrStateResidencyTicks::UNDEFINED 264174500 # Cumulative time (in ticks) in various power states -system.cpu2.dcache.ReadReq_hits::cpu2.data 40751 # number of ReadReq hits -system.cpu2.dcache.ReadReq_hits::total 40751 # number of ReadReq hits -system.cpu2.dcache.WriteReq_hits::cpu2.data 14004 # number of WriteReq hits -system.cpu2.dcache.WriteReq_hits::total 14004 # number of WriteReq hits -system.cpu2.dcache.SwapReq_hits::cpu2.data 12 # number of SwapReq hits -system.cpu2.dcache.SwapReq_hits::total 12 # number of SwapReq hits -system.cpu2.dcache.demand_hits::cpu2.data 54755 # number of demand (read+write) hits -system.cpu2.dcache.demand_hits::total 54755 # number of demand (read+write) hits -system.cpu2.dcache.overall_hits::cpu2.data 54755 # number of overall hits -system.cpu2.dcache.overall_hits::total 54755 # number of overall hits -system.cpu2.dcache.ReadReq_misses::cpu2.data 169 # number of ReadReq misses -system.cpu2.dcache.ReadReq_misses::total 169 # number of ReadReq misses +system.cpu2.dcache.tags.tag_accesses 221019 # Number of tag accesses +system.cpu2.dcache.tags.data_accesses 221019 # Number of data accesses +system.cpu2.dcache.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states +system.cpu2.dcache.ReadReq_hits::cpu2.data 40826 # number of ReadReq hits +system.cpu2.dcache.ReadReq_hits::total 40826 # number of ReadReq hits +system.cpu2.dcache.WriteReq_hits::cpu2.data 14029 # number of WriteReq hits +system.cpu2.dcache.WriteReq_hits::total 14029 # number of WriteReq hits +system.cpu2.dcache.SwapReq_hits::cpu2.data 13 # number of SwapReq hits +system.cpu2.dcache.SwapReq_hits::total 13 # number of SwapReq hits +system.cpu2.dcache.demand_hits::cpu2.data 54855 # number of demand (read+write) hits +system.cpu2.dcache.demand_hits::total 54855 # number of demand (read+write) hits +system.cpu2.dcache.overall_hits::cpu2.data 54855 # number of overall hits +system.cpu2.dcache.overall_hits::total 54855 # number of overall hits +system.cpu2.dcache.ReadReq_misses::cpu2.data 162 # number of ReadReq misses +system.cpu2.dcache.ReadReq_misses::total 162 # number of ReadReq misses system.cpu2.dcache.WriteReq_misses::cpu2.data 105 # number of WriteReq misses system.cpu2.dcache.WriteReq_misses::total 105 # number of WriteReq misses -system.cpu2.dcache.SwapReq_misses::cpu2.data 60 # number of SwapReq misses -system.cpu2.dcache.SwapReq_misses::total 60 # number of SwapReq misses -system.cpu2.dcache.demand_misses::cpu2.data 274 # number of demand (read+write) misses -system.cpu2.dcache.demand_misses::total 274 # number of demand (read+write) misses -system.cpu2.dcache.overall_misses::cpu2.data 274 # number of overall misses -system.cpu2.dcache.overall_misses::total 274 # number of overall misses -system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 2144500 # number of ReadReq miss cycles -system.cpu2.dcache.ReadReq_miss_latency::total 2144500 # number of ReadReq miss cycles -system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 1802500 # number of WriteReq miss cycles -system.cpu2.dcache.WriteReq_miss_latency::total 1802500 # number of WriteReq miss cycles -system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 267500 # number of SwapReq miss cycles -system.cpu2.dcache.SwapReq_miss_latency::total 267500 # number of SwapReq miss cycles -system.cpu2.dcache.demand_miss_latency::cpu2.data 3947000 # number of demand (read+write) miss cycles -system.cpu2.dcache.demand_miss_latency::total 3947000 # number of demand (read+write) miss cycles -system.cpu2.dcache.overall_miss_latency::cpu2.data 3947000 # number of overall miss cycles -system.cpu2.dcache.overall_miss_latency::total 3947000 # number of overall miss cycles -system.cpu2.dcache.ReadReq_accesses::cpu2.data 40920 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.ReadReq_accesses::total 40920 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_accesses::cpu2.data 14109 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_accesses::total 14109 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.SwapReq_accesses::cpu2.data 72 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.SwapReq_accesses::total 72 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.demand_accesses::cpu2.data 55029 # number of demand (read+write) accesses -system.cpu2.dcache.demand_accesses::total 55029 # number of demand (read+write) accesses -system.cpu2.dcache.overall_accesses::cpu2.data 55029 # number of overall (read+write) accesses -system.cpu2.dcache.overall_accesses::total 55029 # number of overall (read+write) accesses -system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.004130 # miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_miss_rate::total 0.004130 # miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.007442 # miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_miss_rate::total 0.007442 # miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.833333 # miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_miss_rate::total 0.833333 # miss rate for SwapReq accesses -system.cpu2.dcache.demand_miss_rate::cpu2.data 0.004979 # miss rate for demand accesses -system.cpu2.dcache.demand_miss_rate::total 0.004979 # miss rate for demand accesses -system.cpu2.dcache.overall_miss_rate::cpu2.data 0.004979 # miss rate for overall accesses -system.cpu2.dcache.overall_miss_rate::total 0.004979 # miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 12689.349112 # average ReadReq miss latency -system.cpu2.dcache.ReadReq_avg_miss_latency::total 12689.349112 # average ReadReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 17166.666667 # average WriteReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency::total 17166.666667 # average WriteReq miss latency -system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 4458.333333 # average SwapReq miss latency -system.cpu2.dcache.SwapReq_avg_miss_latency::total 4458.333333 # average SwapReq miss latency -system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 14405.109489 # average overall miss latency -system.cpu2.dcache.demand_avg_miss_latency::total 14405.109489 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 14405.109489 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::total 14405.109489 # average overall miss latency +system.cpu2.dcache.SwapReq_misses::cpu2.data 56 # number of SwapReq misses +system.cpu2.dcache.SwapReq_misses::total 56 # number of SwapReq misses +system.cpu2.dcache.demand_misses::cpu2.data 267 # number of demand (read+write) misses +system.cpu2.dcache.demand_misses::total 267 # number of demand (read+write) misses +system.cpu2.dcache.overall_misses::cpu2.data 267 # number of overall misses +system.cpu2.dcache.overall_misses::total 267 # number of overall misses +system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 1409000 # number of ReadReq miss cycles +system.cpu2.dcache.ReadReq_miss_latency::total 1409000 # number of ReadReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 1485000 # number of WriteReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::total 1485000 # number of WriteReq miss cycles +system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 251000 # number of SwapReq miss cycles +system.cpu2.dcache.SwapReq_miss_latency::total 251000 # number of SwapReq miss cycles +system.cpu2.dcache.demand_miss_latency::cpu2.data 2894000 # number of demand (read+write) miss cycles +system.cpu2.dcache.demand_miss_latency::total 2894000 # number of demand (read+write) miss cycles +system.cpu2.dcache.overall_miss_latency::cpu2.data 2894000 # number of overall miss cycles +system.cpu2.dcache.overall_miss_latency::total 2894000 # number of overall miss cycles +system.cpu2.dcache.ReadReq_accesses::cpu2.data 40988 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.ReadReq_accesses::total 40988 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses::cpu2.data 14134 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses::total 14134 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.SwapReq_accesses::cpu2.data 69 # number of SwapReq accesses(hits+misses) +system.cpu2.dcache.SwapReq_accesses::total 69 # number of SwapReq accesses(hits+misses) +system.cpu2.dcache.demand_accesses::cpu2.data 55122 # number of demand (read+write) accesses +system.cpu2.dcache.demand_accesses::total 55122 # number of demand (read+write) accesses +system.cpu2.dcache.overall_accesses::cpu2.data 55122 # number of overall (read+write) accesses +system.cpu2.dcache.overall_accesses::total 55122 # number of overall (read+write) accesses +system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.003952 # miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_miss_rate::total 0.003952 # miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.007429 # miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_miss_rate::total 0.007429 # miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.811594 # miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_miss_rate::total 0.811594 # miss rate for SwapReq accesses +system.cpu2.dcache.demand_miss_rate::cpu2.data 0.004844 # miss rate for demand accesses +system.cpu2.dcache.demand_miss_rate::total 0.004844 # miss rate for demand accesses +system.cpu2.dcache.overall_miss_rate::cpu2.data 0.004844 # miss rate for overall accesses +system.cpu2.dcache.overall_miss_rate::total 0.004844 # miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 8697.530864 # average ReadReq miss latency +system.cpu2.dcache.ReadReq_avg_miss_latency::total 8697.530864 # average ReadReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 14142.857143 # average WriteReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::total 14142.857143 # average WriteReq miss latency +system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 4482.142857 # average SwapReq miss latency +system.cpu2.dcache.SwapReq_avg_miss_latency::total 4482.142857 # average SwapReq miss latency +system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 10838.951311 # average overall miss latency +system.cpu2.dcache.demand_avg_miss_latency::total 10838.951311 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 10838.951311 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::total 10838.951311 # average overall miss latency system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 169 # number of ReadReq MSHR misses -system.cpu2.dcache.ReadReq_mshr_misses::total 169 # number of ReadReq MSHR misses +system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 162 # number of ReadReq MSHR misses +system.cpu2.dcache.ReadReq_mshr_misses::total 162 # number of ReadReq MSHR misses system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 105 # number of WriteReq MSHR misses system.cpu2.dcache.WriteReq_mshr_misses::total 105 # number of WriteReq MSHR misses -system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 60 # number of SwapReq MSHR misses -system.cpu2.dcache.SwapReq_mshr_misses::total 60 # number of SwapReq MSHR misses -system.cpu2.dcache.demand_mshr_misses::cpu2.data 274 # number of demand (read+write) MSHR misses -system.cpu2.dcache.demand_mshr_misses::total 274 # number of demand (read+write) MSHR misses -system.cpu2.dcache.overall_mshr_misses::cpu2.data 274 # number of overall MSHR misses -system.cpu2.dcache.overall_mshr_misses::total 274 # number of overall MSHR misses -system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1975500 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1975500 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1697500 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1697500 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 207500 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency::total 207500 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3673000 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::total 3673000 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3673000 # number of overall MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::total 3673000 # number of overall MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.004130 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.004130 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.007442 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.007442 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.833333 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.833333 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.004979 # mshr miss rate for demand accesses -system.cpu2.dcache.demand_mshr_miss_rate::total 0.004979 # mshr miss rate for demand accesses -system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.004979 # mshr miss rate for overall accesses -system.cpu2.dcache.overall_mshr_miss_rate::total 0.004979 # mshr miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 11689.349112 # average ReadReq mshr miss latency -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 11689.349112 # average ReadReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 16166.666667 # average WriteReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 16166.666667 # average WriteReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 3458.333333 # average SwapReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 3458.333333 # average SwapReq mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 13405.109489 # average overall mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::total 13405.109489 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 13405.109489 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::total 13405.109489 # average overall mshr miss latency -system.cpu2.icache.tags.pwrStateResidencyTicks::UNDEFINED 264174500 # Cumulative time (in ticks) in various power states +system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 56 # number of SwapReq MSHR misses +system.cpu2.dcache.SwapReq_mshr_misses::total 56 # number of SwapReq MSHR misses +system.cpu2.dcache.demand_mshr_misses::cpu2.data 267 # number of demand (read+write) MSHR misses +system.cpu2.dcache.demand_mshr_misses::total 267 # number of demand (read+write) MSHR misses +system.cpu2.dcache.overall_mshr_misses::cpu2.data 267 # number of overall MSHR misses +system.cpu2.dcache.overall_mshr_misses::total 267 # number of overall MSHR misses +system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1247000 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1247000 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1380000 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1380000 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 195000 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::total 195000 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 2627000 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::total 2627000 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 2627000 # number of overall MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::total 2627000 # number of overall MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003952 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003952 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.007429 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.007429 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.811594 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.811594 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.004844 # mshr miss rate for demand accesses +system.cpu2.dcache.demand_mshr_miss_rate::total 0.004844 # mshr miss rate for demand accesses +system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.004844 # mshr miss rate for overall accesses +system.cpu2.dcache.overall_mshr_miss_rate::total 0.004844 # mshr miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 7697.530864 # average ReadReq mshr miss latency +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 7697.530864 # average ReadReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 13142.857143 # average WriteReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 13142.857143 # average WriteReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 3482.142857 # average SwapReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 3482.142857 # average SwapReq mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 9838.951311 # average overall mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::total 9838.951311 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 9838.951311 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::total 9838.951311 # average overall mshr miss latency +system.cpu2.icache.tags.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states system.cpu2.icache.tags.replacements 280 # number of replacements -system.cpu2.icache.tags.tagsinuse 69.258301 # Cycle average of tags in use -system.cpu2.icache.tags.total_refs 165354 # Total number of references to valid blocks. +system.cpu2.icache.tags.tagsinuse 69.231273 # Cycle average of tags in use +system.cpu2.icache.tags.total_refs 165559 # Total number of references to valid blocks. system.cpu2.icache.tags.sampled_refs 366 # Sample count of references to valid blocks. -system.cpu2.icache.tags.avg_refs 451.786885 # Average number of references to valid blocks. +system.cpu2.icache.tags.avg_refs 452.346995 # Average number of references to valid blocks. system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.icache.tags.occ_blocks::cpu2.inst 69.258301 # Average occupied blocks per requestor -system.cpu2.icache.tags.occ_percent::cpu2.inst 0.135270 # Average percentage of cache occupancy -system.cpu2.icache.tags.occ_percent::total 0.135270 # Average percentage of cache occupancy +system.cpu2.icache.tags.occ_blocks::cpu2.inst 69.231273 # Average occupied blocks per requestor +system.cpu2.icache.tags.occ_percent::cpu2.inst 0.135217 # Average percentage of cache occupancy +system.cpu2.icache.tags.occ_percent::total 0.135217 # Average percentage of cache occupancy system.cpu2.icache.tags.occ_task_id_blocks::1024 86 # Occupied blocks per task id system.cpu2.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id system.cpu2.icache.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id system.cpu2.icache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id system.cpu2.icache.tags.occ_task_id_percent::1024 0.167969 # Percentage of cache occupancy per task id -system.cpu2.icache.tags.tag_accesses 166086 # Number of tag accesses -system.cpu2.icache.tags.data_accesses 166086 # Number of data accesses -system.cpu2.icache.pwrStateResidencyTicks::UNDEFINED 264174500 # Cumulative time (in ticks) in various power states -system.cpu2.icache.ReadReq_hits::cpu2.inst 165354 # number of ReadReq hits -system.cpu2.icache.ReadReq_hits::total 165354 # number of ReadReq hits -system.cpu2.icache.demand_hits::cpu2.inst 165354 # number of demand (read+write) hits -system.cpu2.icache.demand_hits::total 165354 # number of demand (read+write) hits -system.cpu2.icache.overall_hits::cpu2.inst 165354 # number of overall hits -system.cpu2.icache.overall_hits::total 165354 # number of overall hits +system.cpu2.icache.tags.tag_accesses 166291 # Number of tag accesses +system.cpu2.icache.tags.data_accesses 166291 # Number of data accesses +system.cpu2.icache.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states +system.cpu2.icache.ReadReq_hits::cpu2.inst 165559 # number of ReadReq hits +system.cpu2.icache.ReadReq_hits::total 165559 # number of ReadReq hits +system.cpu2.icache.demand_hits::cpu2.inst 165559 # number of demand (read+write) hits +system.cpu2.icache.demand_hits::total 165559 # number of demand (read+write) hits +system.cpu2.icache.overall_hits::cpu2.inst 165559 # number of overall hits +system.cpu2.icache.overall_hits::total 165559 # number of overall hits system.cpu2.icache.ReadReq_misses::cpu2.inst 366 # number of ReadReq misses system.cpu2.icache.ReadReq_misses::total 366 # number of ReadReq misses system.cpu2.icache.demand_misses::cpu2.inst 366 # number of demand (read+write) misses system.cpu2.icache.demand_misses::total 366 # number of demand (read+write) misses system.cpu2.icache.overall_misses::cpu2.inst 366 # number of overall misses system.cpu2.icache.overall_misses::total 366 # number of overall misses -system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 8165500 # number of ReadReq miss cycles -system.cpu2.icache.ReadReq_miss_latency::total 8165500 # number of ReadReq miss cycles -system.cpu2.icache.demand_miss_latency::cpu2.inst 8165500 # number of demand (read+write) miss cycles -system.cpu2.icache.demand_miss_latency::total 8165500 # number of demand (read+write) miss cycles -system.cpu2.icache.overall_miss_latency::cpu2.inst 8165500 # number of overall miss cycles -system.cpu2.icache.overall_miss_latency::total 8165500 # number of overall miss cycles -system.cpu2.icache.ReadReq_accesses::cpu2.inst 165720 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.ReadReq_accesses::total 165720 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.demand_accesses::cpu2.inst 165720 # number of demand (read+write) accesses -system.cpu2.icache.demand_accesses::total 165720 # number of demand (read+write) accesses -system.cpu2.icache.overall_accesses::cpu2.inst 165720 # number of overall (read+write) accesses -system.cpu2.icache.overall_accesses::total 165720 # number of overall (read+write) accesses -system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.002209 # miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_miss_rate::total 0.002209 # miss rate for ReadReq accesses -system.cpu2.icache.demand_miss_rate::cpu2.inst 0.002209 # miss rate for demand accesses -system.cpu2.icache.demand_miss_rate::total 0.002209 # miss rate for demand accesses -system.cpu2.icache.overall_miss_rate::cpu2.inst 0.002209 # miss rate for overall accesses -system.cpu2.icache.overall_miss_rate::total 0.002209 # miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 22310.109290 # average ReadReq miss latency -system.cpu2.icache.ReadReq_avg_miss_latency::total 22310.109290 # average ReadReq miss latency -system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 22310.109290 # average overall miss latency -system.cpu2.icache.demand_avg_miss_latency::total 22310.109290 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 22310.109290 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::total 22310.109290 # average overall miss latency +system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 8164000 # number of ReadReq miss cycles +system.cpu2.icache.ReadReq_miss_latency::total 8164000 # number of ReadReq miss cycles +system.cpu2.icache.demand_miss_latency::cpu2.inst 8164000 # number of demand (read+write) miss cycles +system.cpu2.icache.demand_miss_latency::total 8164000 # number of demand (read+write) miss cycles +system.cpu2.icache.overall_miss_latency::cpu2.inst 8164000 # number of overall miss cycles +system.cpu2.icache.overall_miss_latency::total 8164000 # number of overall miss cycles +system.cpu2.icache.ReadReq_accesses::cpu2.inst 165925 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.ReadReq_accesses::total 165925 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.demand_accesses::cpu2.inst 165925 # number of demand (read+write) accesses +system.cpu2.icache.demand_accesses::total 165925 # number of demand (read+write) accesses +system.cpu2.icache.overall_accesses::cpu2.inst 165925 # number of overall (read+write) accesses +system.cpu2.icache.overall_accesses::total 165925 # number of overall (read+write) accesses +system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.002206 # miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_miss_rate::total 0.002206 # miss rate for ReadReq accesses +system.cpu2.icache.demand_miss_rate::cpu2.inst 0.002206 # miss rate for demand accesses +system.cpu2.icache.demand_miss_rate::total 0.002206 # miss rate for demand accesses +system.cpu2.icache.overall_miss_rate::cpu2.inst 0.002206 # miss rate for overall accesses +system.cpu2.icache.overall_miss_rate::total 0.002206 # miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 22306.010929 # average ReadReq miss latency +system.cpu2.icache.ReadReq_avg_miss_latency::total 22306.010929 # average ReadReq miss latency +system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 22306.010929 # average overall miss latency +system.cpu2.icache.demand_avg_miss_latency::total 22306.010929 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 22306.010929 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::total 22306.010929 # average overall miss latency system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -850,260 +850,260 @@ system.cpu2.icache.demand_mshr_misses::cpu2.inst 366 system.cpu2.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses system.cpu2.icache.overall_mshr_misses::cpu2.inst 366 # number of overall MSHR misses system.cpu2.icache.overall_mshr_misses::total 366 # number of overall MSHR misses -system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 7799500 # number of ReadReq MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_latency::total 7799500 # number of ReadReq MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 7799500 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::total 7799500 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 7799500 # number of overall MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::total 7799500 # number of overall MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.002209 # mshr miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.002209 # mshr miss rate for ReadReq accesses -system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.002209 # mshr miss rate for demand accesses -system.cpu2.icache.demand_mshr_miss_rate::total 0.002209 # mshr miss rate for demand accesses -system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.002209 # mshr miss rate for overall accesses -system.cpu2.icache.overall_mshr_miss_rate::total 0.002209 # mshr miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 21310.109290 # average ReadReq mshr miss latency -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 21310.109290 # average ReadReq mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 21310.109290 # average overall mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::total 21310.109290 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 21310.109290 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::total 21310.109290 # average overall mshr miss latency -system.cpu3.pwrStateResidencyTicks::ON 264174500 # Cumulative time (in ticks) in various power states -system.cpu3.numCycles 528348 # number of cpu cycles simulated +system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 7798000 # number of ReadReq MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_latency::total 7798000 # number of ReadReq MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 7798000 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::total 7798000 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 7798000 # number of overall MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::total 7798000 # number of overall MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.002206 # mshr miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.002206 # mshr miss rate for ReadReq accesses +system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.002206 # mshr miss rate for demand accesses +system.cpu2.icache.demand_mshr_miss_rate::total 0.002206 # mshr miss rate for demand accesses +system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.002206 # mshr miss rate for overall accesses +system.cpu2.icache.overall_mshr_miss_rate::total 0.002206 # mshr miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 21306.010929 # average ReadReq mshr miss latency +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 21306.010929 # average ReadReq mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 21306.010929 # average overall mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::total 21306.010929 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 21306.010929 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::total 21306.010929 # average overall mshr miss latency +system.cpu3.pwrStateResidencyTicks::ON 263409500 # Cumulative time (in ticks) in various power states +system.cpu3.numCycles 526818 # number of cpu cycles simulated system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu3.committedInsts 169439 # Number of instructions committed -system.cpu3.committedOps 169439 # Number of ops (including micro ops) committed -system.cpu3.num_int_alu_accesses 111342 # Number of integer alu accesses +system.cpu3.committedInsts 170395 # Number of instructions committed +system.cpu3.committedOps 170395 # Number of ops (including micro ops) committed +system.cpu3.num_int_alu_accesses 111057 # Number of integer alu accesses system.cpu3.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu3.num_func_calls 637 # number of times a function call or return occured -system.cpu3.num_conditional_control_insts 33059 # number of instructions that are conditional controls -system.cpu3.num_int_insts 111342 # number of integer instructions +system.cpu3.num_conditional_control_insts 33676 # number of instructions that are conditional controls +system.cpu3.num_int_insts 111057 # number of integer instructions system.cpu3.num_fp_insts 0 # number of float instructions -system.cpu3.num_int_register_reads 275359 # number of times the integer registers were read -system.cpu3.num_int_register_writes 104262 # number of times the integer registers were written +system.cpu3.num_int_register_reads 271753 # number of times the integer registers were read +system.cpu3.num_int_register_writes 102596 # number of times the integer registers were written system.cpu3.num_fp_register_reads 0 # number of times the floating registers were read system.cpu3.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu3.num_mem_refs 54451 # number of memory refs -system.cpu3.num_load_insts 41338 # Number of load instructions -system.cpu3.num_store_insts 13113 # Number of store instructions -system.cpu3.num_idle_cycles 75238.859311 # Number of idle cycles -system.cpu3.num_busy_cycles 453109.140689 # Number of busy cycles -system.cpu3.not_idle_fraction 0.857596 # Percentage of non-idle cycles -system.cpu3.idle_fraction 0.142404 # Percentage of idle cycles -system.cpu3.Branches 34709 # Number of branches fetched -system.cpu3.op_class::No_OpClass 25492 15.04% 15.04% # Class of executed instruction -system.cpu3.op_class::IntAlu 74930 44.21% 59.26% # Class of executed instruction -system.cpu3.op_class::IntMult 0 0.00% 59.26% # Class of executed instruction -system.cpu3.op_class::IntDiv 0 0.00% 59.26% # Class of executed instruction -system.cpu3.op_class::FloatAdd 0 0.00% 59.26% # Class of executed instruction -system.cpu3.op_class::FloatCmp 0 0.00% 59.26% # Class of executed instruction -system.cpu3.op_class::FloatCvt 0 0.00% 59.26% # Class of executed instruction -system.cpu3.op_class::FloatMult 0 0.00% 59.26% # Class of executed instruction -system.cpu3.op_class::FloatDiv 0 0.00% 59.26% # Class of executed instruction -system.cpu3.op_class::FloatSqrt 0 0.00% 59.26% # Class of executed instruction -system.cpu3.op_class::SimdAdd 0 0.00% 59.26% # Class of executed instruction -system.cpu3.op_class::SimdAddAcc 0 0.00% 59.26% # Class of executed instruction -system.cpu3.op_class::SimdAlu 0 0.00% 59.26% # Class of executed instruction -system.cpu3.op_class::SimdCmp 0 0.00% 59.26% # Class of executed instruction -system.cpu3.op_class::SimdCvt 0 0.00% 59.26% # Class of executed instruction -system.cpu3.op_class::SimdMisc 0 0.00% 59.26% # Class of executed instruction -system.cpu3.op_class::SimdMult 0 0.00% 59.26% # Class of executed instruction -system.cpu3.op_class::SimdMultAcc 0 0.00% 59.26% # Class of executed instruction -system.cpu3.op_class::SimdShift 0 0.00% 59.26% # Class of executed instruction -system.cpu3.op_class::SimdShiftAcc 0 0.00% 59.26% # Class of executed instruction -system.cpu3.op_class::SimdSqrt 0 0.00% 59.26% # Class of executed instruction -system.cpu3.op_class::SimdFloatAdd 0 0.00% 59.26% # Class of executed instruction -system.cpu3.op_class::SimdFloatAlu 0 0.00% 59.26% # Class of executed instruction -system.cpu3.op_class::SimdFloatCmp 0 0.00% 59.26% # Class of executed instruction -system.cpu3.op_class::SimdFloatCvt 0 0.00% 59.26% # Class of executed instruction -system.cpu3.op_class::SimdFloatDiv 0 0.00% 59.26% # Class of executed instruction -system.cpu3.op_class::SimdFloatMisc 0 0.00% 59.26% # Class of executed instruction -system.cpu3.op_class::SimdFloatMult 0 0.00% 59.26% # Class of executed instruction -system.cpu3.op_class::SimdFloatMultAcc 0 0.00% 59.26% # Class of executed instruction -system.cpu3.op_class::SimdFloatSqrt 0 0.00% 59.26% # Class of executed instruction -system.cpu3.op_class::MemRead 55936 33.01% 92.26% # Class of executed instruction -system.cpu3.op_class::MemWrite 13113 7.74% 100.00% # Class of executed instruction +system.cpu3.num_mem_refs 53550 # number of memory refs +system.cpu3.num_load_insts 41191 # Number of load instructions +system.cpu3.num_store_insts 12359 # Number of store instructions +system.cpu3.num_idle_cycles 75201.858967 # Number of idle cycles +system.cpu3.num_busy_cycles 451616.141033 # Number of busy cycles +system.cpu3.not_idle_fraction 0.857253 # Percentage of non-idle cycles +system.cpu3.idle_fraction 0.142747 # Percentage of idle cycles +system.cpu3.Branches 35332 # Number of branches fetched +system.cpu3.op_class::No_OpClass 26110 15.32% 15.32% # Class of executed instruction +system.cpu3.op_class::IntAlu 74791 43.88% 59.20% # Class of executed instruction +system.cpu3.op_class::IntMult 0 0.00% 59.20% # Class of executed instruction +system.cpu3.op_class::IntDiv 0 0.00% 59.20% # Class of executed instruction +system.cpu3.op_class::FloatAdd 0 0.00% 59.20% # Class of executed instruction +system.cpu3.op_class::FloatCmp 0 0.00% 59.20% # Class of executed instruction +system.cpu3.op_class::FloatCvt 0 0.00% 59.20% # Class of executed instruction +system.cpu3.op_class::FloatMult 0 0.00% 59.20% # Class of executed instruction +system.cpu3.op_class::FloatDiv 0 0.00% 59.20% # Class of executed instruction +system.cpu3.op_class::FloatSqrt 0 0.00% 59.20% # Class of executed instruction +system.cpu3.op_class::SimdAdd 0 0.00% 59.20% # Class of executed instruction +system.cpu3.op_class::SimdAddAcc 0 0.00% 59.20% # Class of executed instruction +system.cpu3.op_class::SimdAlu 0 0.00% 59.20% # Class of executed instruction +system.cpu3.op_class::SimdCmp 0 0.00% 59.20% # Class of executed instruction +system.cpu3.op_class::SimdCvt 0 0.00% 59.20% # Class of executed instruction +system.cpu3.op_class::SimdMisc 0 0.00% 59.20% # Class of executed instruction +system.cpu3.op_class::SimdMult 0 0.00% 59.20% # Class of executed instruction +system.cpu3.op_class::SimdMultAcc 0 0.00% 59.20% # Class of executed instruction +system.cpu3.op_class::SimdShift 0 0.00% 59.20% # Class of executed instruction +system.cpu3.op_class::SimdShiftAcc 0 0.00% 59.20% # Class of executed instruction +system.cpu3.op_class::SimdSqrt 0 0.00% 59.20% # Class of executed instruction +system.cpu3.op_class::SimdFloatAdd 0 0.00% 59.20% # Class of executed instruction +system.cpu3.op_class::SimdFloatAlu 0 0.00% 59.20% # Class of executed instruction +system.cpu3.op_class::SimdFloatCmp 0 0.00% 59.20% # Class of executed instruction +system.cpu3.op_class::SimdFloatCvt 0 0.00% 59.20% # Class of executed instruction +system.cpu3.op_class::SimdFloatDiv 0 0.00% 59.20% # Class of executed instruction +system.cpu3.op_class::SimdFloatMisc 0 0.00% 59.20% # Class of executed instruction +system.cpu3.op_class::SimdFloatMult 0 0.00% 59.20% # Class of executed instruction +system.cpu3.op_class::SimdFloatMultAcc 0 0.00% 59.20% # Class of executed instruction +system.cpu3.op_class::SimdFloatSqrt 0 0.00% 59.20% # Class of executed instruction +system.cpu3.op_class::MemRead 57167 33.54% 92.75% # Class of executed instruction +system.cpu3.op_class::MemWrite 12359 7.25% 100.00% # Class of executed instruction system.cpu3.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu3.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu3.op_class::total 169471 # Class of executed instruction -system.cpu3.dcache.tags.pwrStateResidencyTicks::UNDEFINED 264174500 # Cumulative time (in ticks) in various power states +system.cpu3.op_class::total 170427 # Class of executed instruction +system.cpu3.dcache.tags.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states system.cpu3.dcache.tags.replacements 0 # number of replacements -system.cpu3.dcache.tags.tagsinuse 25.601960 # Cycle average of tags in use -system.cpu3.dcache.tags.total_refs 28504 # Total number of references to valid blocks. -system.cpu3.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. -system.cpu3.dcache.tags.avg_refs 982.896552 # Average number of references to valid blocks. +system.cpu3.dcache.tags.tagsinuse 25.613981 # Cycle average of tags in use +system.cpu3.dcache.tags.total_refs 27108 # Total number of references to valid blocks. +system.cpu3.dcache.tags.sampled_refs 30 # Sample count of references to valid blocks. +system.cpu3.dcache.tags.avg_refs 903.600000 # Average number of references to valid blocks. system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.dcache.tags.occ_blocks::cpu3.data 25.601960 # Average occupied blocks per requestor -system.cpu3.dcache.tags.occ_percent::cpu3.data 0.050004 # Average percentage of cache occupancy -system.cpu3.dcache.tags.occ_percent::total 0.050004 # Average percentage of cache occupancy -system.cpu3.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id -system.cpu3.dcache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id +system.cpu3.dcache.tags.occ_blocks::cpu3.data 25.613981 # Average occupied blocks per requestor +system.cpu3.dcache.tags.occ_percent::cpu3.data 0.050027 # Average percentage of cache occupancy +system.cpu3.dcache.tags.occ_percent::total 0.050027 # Average percentage of cache occupancy +system.cpu3.dcache.tags.occ_task_id_blocks::1024 30 # Occupied blocks per task id +system.cpu3.dcache.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id system.cpu3.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id -system.cpu3.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id -system.cpu3.dcache.tags.tag_accesses 218004 # Number of tag accesses -system.cpu3.dcache.tags.data_accesses 218004 # Number of data accesses -system.cpu3.dcache.pwrStateResidencyTicks::UNDEFINED 264174500 # Cumulative time (in ticks) in various power states -system.cpu3.dcache.ReadReq_hits::cpu3.data 41179 # number of ReadReq hits -system.cpu3.dcache.ReadReq_hits::total 41179 # number of ReadReq hits -system.cpu3.dcache.WriteReq_hits::cpu3.data 12939 # number of WriteReq hits -system.cpu3.dcache.WriteReq_hits::total 12939 # number of WriteReq hits -system.cpu3.dcache.SwapReq_hits::cpu3.data 15 # number of SwapReq hits -system.cpu3.dcache.SwapReq_hits::total 15 # number of SwapReq hits -system.cpu3.dcache.demand_hits::cpu3.data 54118 # number of demand (read+write) hits -system.cpu3.dcache.demand_hits::total 54118 # number of demand (read+write) hits -system.cpu3.dcache.overall_hits::cpu3.data 54118 # number of overall hits -system.cpu3.dcache.overall_hits::total 54118 # number of overall hits -system.cpu3.dcache.ReadReq_misses::cpu3.data 151 # number of ReadReq misses -system.cpu3.dcache.ReadReq_misses::total 151 # number of ReadReq misses +system.cpu3.dcache.tags.occ_task_id_percent::1024 0.058594 # Percentage of cache occupancy per task id +system.cpu3.dcache.tags.tag_accesses 214417 # Number of tag accesses +system.cpu3.dcache.tags.data_accesses 214417 # Number of data accesses +system.cpu3.dcache.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states +system.cpu3.dcache.ReadReq_hits::cpu3.data 41020 # number of ReadReq hits +system.cpu3.dcache.ReadReq_hits::total 41020 # number of ReadReq hits +system.cpu3.dcache.WriteReq_hits::cpu3.data 12180 # number of WriteReq hits +system.cpu3.dcache.WriteReq_hits::total 12180 # number of WriteReq hits +system.cpu3.dcache.SwapReq_hits::cpu3.data 14 # number of SwapReq hits +system.cpu3.dcache.SwapReq_hits::total 14 # number of SwapReq hits +system.cpu3.dcache.demand_hits::cpu3.data 53200 # number of demand (read+write) hits +system.cpu3.dcache.demand_hits::total 53200 # number of demand (read+write) hits +system.cpu3.dcache.overall_hits::cpu3.data 53200 # number of overall hits +system.cpu3.dcache.overall_hits::total 53200 # number of overall hits +system.cpu3.dcache.ReadReq_misses::cpu3.data 163 # number of ReadReq misses +system.cpu3.dcache.ReadReq_misses::total 163 # number of ReadReq misses system.cpu3.dcache.WriteReq_misses::cpu3.data 105 # number of WriteReq misses system.cpu3.dcache.WriteReq_misses::total 105 # number of WriteReq misses -system.cpu3.dcache.SwapReq_misses::cpu3.data 52 # number of SwapReq misses -system.cpu3.dcache.SwapReq_misses::total 52 # number of SwapReq misses -system.cpu3.dcache.demand_misses::cpu3.data 256 # number of demand (read+write) misses -system.cpu3.dcache.demand_misses::total 256 # number of demand (read+write) misses -system.cpu3.dcache.overall_misses::cpu3.data 256 # number of overall misses -system.cpu3.dcache.overall_misses::total 256 # number of overall misses -system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 1675000 # number of ReadReq miss cycles -system.cpu3.dcache.ReadReq_miss_latency::total 1675000 # number of ReadReq miss cycles -system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 1736000 # number of WriteReq miss cycles -system.cpu3.dcache.WriteReq_miss_latency::total 1736000 # number of WriteReq miss cycles -system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 234000 # number of SwapReq miss cycles -system.cpu3.dcache.SwapReq_miss_latency::total 234000 # number of SwapReq miss cycles -system.cpu3.dcache.demand_miss_latency::cpu3.data 3411000 # number of demand (read+write) miss cycles -system.cpu3.dcache.demand_miss_latency::total 3411000 # number of demand (read+write) miss cycles -system.cpu3.dcache.overall_miss_latency::cpu3.data 3411000 # number of overall miss cycles -system.cpu3.dcache.overall_miss_latency::total 3411000 # number of overall miss cycles -system.cpu3.dcache.ReadReq_accesses::cpu3.data 41330 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.ReadReq_accesses::total 41330 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_accesses::cpu3.data 13044 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_accesses::total 13044 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.SwapReq_accesses::cpu3.data 67 # number of SwapReq accesses(hits+misses) -system.cpu3.dcache.SwapReq_accesses::total 67 # number of SwapReq accesses(hits+misses) -system.cpu3.dcache.demand_accesses::cpu3.data 54374 # number of demand (read+write) accesses -system.cpu3.dcache.demand_accesses::total 54374 # number of demand (read+write) accesses -system.cpu3.dcache.overall_accesses::cpu3.data 54374 # number of overall (read+write) accesses -system.cpu3.dcache.overall_accesses::total 54374 # number of overall (read+write) accesses -system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.003654 # miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_miss_rate::total 0.003654 # miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.008050 # miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_miss_rate::total 0.008050 # miss rate for WriteReq accesses -system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.776119 # miss rate for SwapReq accesses -system.cpu3.dcache.SwapReq_miss_rate::total 0.776119 # miss rate for SwapReq accesses -system.cpu3.dcache.demand_miss_rate::cpu3.data 0.004708 # miss rate for demand accesses -system.cpu3.dcache.demand_miss_rate::total 0.004708 # miss rate for demand accesses -system.cpu3.dcache.overall_miss_rate::cpu3.data 0.004708 # miss rate for overall accesses -system.cpu3.dcache.overall_miss_rate::total 0.004708 # miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 11092.715232 # average ReadReq miss latency -system.cpu3.dcache.ReadReq_avg_miss_latency::total 11092.715232 # average ReadReq miss latency -system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 16533.333333 # average WriteReq miss latency -system.cpu3.dcache.WriteReq_avg_miss_latency::total 16533.333333 # average WriteReq miss latency -system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 4500 # average SwapReq miss latency -system.cpu3.dcache.SwapReq_avg_miss_latency::total 4500 # average SwapReq miss latency -system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 13324.218750 # average overall miss latency -system.cpu3.dcache.demand_avg_miss_latency::total 13324.218750 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 13324.218750 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency::total 13324.218750 # average overall miss latency +system.cpu3.dcache.SwapReq_misses::cpu3.data 58 # number of SwapReq misses +system.cpu3.dcache.SwapReq_misses::total 58 # number of SwapReq misses +system.cpu3.dcache.demand_misses::cpu3.data 268 # number of demand (read+write) misses +system.cpu3.dcache.demand_misses::total 268 # number of demand (read+write) misses +system.cpu3.dcache.overall_misses::cpu3.data 268 # number of overall misses +system.cpu3.dcache.overall_misses::total 268 # number of overall misses +system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 1141000 # number of ReadReq miss cycles +system.cpu3.dcache.ReadReq_miss_latency::total 1141000 # number of ReadReq miss cycles +system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 1445000 # number of WriteReq miss cycles +system.cpu3.dcache.WriteReq_miss_latency::total 1445000 # number of WriteReq miss cycles +system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 263000 # number of SwapReq miss cycles +system.cpu3.dcache.SwapReq_miss_latency::total 263000 # number of SwapReq miss cycles +system.cpu3.dcache.demand_miss_latency::cpu3.data 2586000 # number of demand (read+write) miss cycles +system.cpu3.dcache.demand_miss_latency::total 2586000 # number of demand (read+write) miss cycles +system.cpu3.dcache.overall_miss_latency::cpu3.data 2586000 # number of overall miss cycles +system.cpu3.dcache.overall_miss_latency::total 2586000 # number of overall miss cycles +system.cpu3.dcache.ReadReq_accesses::cpu3.data 41183 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.ReadReq_accesses::total 41183 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_accesses::cpu3.data 12285 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_accesses::total 12285 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.SwapReq_accesses::cpu3.data 72 # number of SwapReq accesses(hits+misses) +system.cpu3.dcache.SwapReq_accesses::total 72 # number of SwapReq accesses(hits+misses) +system.cpu3.dcache.demand_accesses::cpu3.data 53468 # number of demand (read+write) accesses +system.cpu3.dcache.demand_accesses::total 53468 # number of demand (read+write) accesses +system.cpu3.dcache.overall_accesses::cpu3.data 53468 # number of overall (read+write) accesses +system.cpu3.dcache.overall_accesses::total 53468 # number of overall (read+write) accesses +system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.003958 # miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_miss_rate::total 0.003958 # miss rate for ReadReq accesses +system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.008547 # miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_miss_rate::total 0.008547 # miss rate for WriteReq accesses +system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.805556 # miss rate for SwapReq accesses +system.cpu3.dcache.SwapReq_miss_rate::total 0.805556 # miss rate for SwapReq accesses +system.cpu3.dcache.demand_miss_rate::cpu3.data 0.005012 # miss rate for demand accesses +system.cpu3.dcache.demand_miss_rate::total 0.005012 # miss rate for demand accesses +system.cpu3.dcache.overall_miss_rate::cpu3.data 0.005012 # miss rate for overall accesses +system.cpu3.dcache.overall_miss_rate::total 0.005012 # miss rate for overall accesses +system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 7000 # average ReadReq miss latency +system.cpu3.dcache.ReadReq_avg_miss_latency::total 7000 # average ReadReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 13761.904762 # average WriteReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::total 13761.904762 # average WriteReq miss latency +system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 4534.482759 # average SwapReq miss latency +system.cpu3.dcache.SwapReq_avg_miss_latency::total 4534.482759 # average SwapReq miss latency +system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 9649.253731 # average overall miss latency +system.cpu3.dcache.demand_avg_miss_latency::total 9649.253731 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 9649.253731 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::total 9649.253731 # average overall miss latency system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 151 # number of ReadReq MSHR misses -system.cpu3.dcache.ReadReq_mshr_misses::total 151 # number of ReadReq MSHR misses +system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 163 # number of ReadReq MSHR misses +system.cpu3.dcache.ReadReq_mshr_misses::total 163 # number of ReadReq MSHR misses system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 105 # number of WriteReq MSHR misses system.cpu3.dcache.WriteReq_mshr_misses::total 105 # number of WriteReq MSHR misses -system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 52 # number of SwapReq MSHR misses -system.cpu3.dcache.SwapReq_mshr_misses::total 52 # number of SwapReq MSHR misses -system.cpu3.dcache.demand_mshr_misses::cpu3.data 256 # number of demand (read+write) MSHR misses -system.cpu3.dcache.demand_mshr_misses::total 256 # number of demand (read+write) MSHR misses -system.cpu3.dcache.overall_mshr_misses::cpu3.data 256 # number of overall MSHR misses -system.cpu3.dcache.overall_mshr_misses::total 256 # number of overall MSHR misses -system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 1524000 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_latency::total 1524000 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1631000 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1631000 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 182000 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.SwapReq_mshr_miss_latency::total 182000 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 3155000 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::total 3155000 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 3155000 # number of overall MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::total 3155000 # number of overall MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003654 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003654 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.008050 # mshr miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.008050 # mshr miss rate for WriteReq accesses -system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.776119 # mshr miss rate for SwapReq accesses -system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.776119 # mshr miss rate for SwapReq accesses -system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.004708 # mshr miss rate for demand accesses -system.cpu3.dcache.demand_mshr_miss_rate::total 0.004708 # mshr miss rate for demand accesses -system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.004708 # mshr miss rate for overall accesses -system.cpu3.dcache.overall_mshr_miss_rate::total 0.004708 # mshr miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 10092.715232 # average ReadReq mshr miss latency -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 10092.715232 # average ReadReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 15533.333333 # average WriteReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 15533.333333 # average WriteReq mshr miss latency -system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 3500 # average SwapReq mshr miss latency -system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 3500 # average SwapReq mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 12324.218750 # average overall mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency::total 12324.218750 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 12324.218750 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::total 12324.218750 # average overall mshr miss latency -system.cpu3.icache.tags.pwrStateResidencyTicks::UNDEFINED 264174500 # Cumulative time (in ticks) in various power states +system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 58 # number of SwapReq MSHR misses +system.cpu3.dcache.SwapReq_mshr_misses::total 58 # number of SwapReq MSHR misses +system.cpu3.dcache.demand_mshr_misses::cpu3.data 268 # number of demand (read+write) MSHR misses +system.cpu3.dcache.demand_mshr_misses::total 268 # number of demand (read+write) MSHR misses +system.cpu3.dcache.overall_mshr_misses::cpu3.data 268 # number of overall MSHR misses +system.cpu3.dcache.overall_mshr_misses::total 268 # number of overall MSHR misses +system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 978000 # number of ReadReq MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_latency::total 978000 # number of ReadReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1340000 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1340000 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 205000 # number of SwapReq MSHR miss cycles +system.cpu3.dcache.SwapReq_mshr_miss_latency::total 205000 # number of SwapReq MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 2318000 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_latency::total 2318000 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 2318000 # number of overall MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::total 2318000 # number of overall MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003958 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003958 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.008547 # mshr miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.008547 # mshr miss rate for WriteReq accesses +system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.805556 # mshr miss rate for SwapReq accesses +system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.805556 # mshr miss rate for SwapReq accesses +system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.005012 # mshr miss rate for demand accesses +system.cpu3.dcache.demand_mshr_miss_rate::total 0.005012 # mshr miss rate for demand accesses +system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.005012 # mshr miss rate for overall accesses +system.cpu3.dcache.overall_mshr_miss_rate::total 0.005012 # mshr miss rate for overall accesses +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 6000 # average ReadReq mshr miss latency +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 6000 # average ReadReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 12761.904762 # average WriteReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 12761.904762 # average WriteReq mshr miss latency +system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 3534.482759 # average SwapReq mshr miss latency +system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 3534.482759 # average SwapReq mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 8649.253731 # average overall mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency::total 8649.253731 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 8649.253731 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency::total 8649.253731 # average overall mshr miss latency +system.cpu3.icache.tags.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states system.cpu3.icache.tags.replacements 281 # number of replacements -system.cpu3.icache.tags.tagsinuse 64.834449 # Cycle average of tags in use -system.cpu3.icache.tags.total_refs 169105 # Total number of references to valid blocks. +system.cpu3.icache.tags.tagsinuse 64.803703 # Cycle average of tags in use +system.cpu3.icache.tags.total_refs 170061 # Total number of references to valid blocks. system.cpu3.icache.tags.sampled_refs 367 # Sample count of references to valid blocks. -system.cpu3.icache.tags.avg_refs 460.776567 # Average number of references to valid blocks. +system.cpu3.icache.tags.avg_refs 463.381471 # Average number of references to valid blocks. system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.icache.tags.occ_blocks::cpu3.inst 64.834449 # Average occupied blocks per requestor -system.cpu3.icache.tags.occ_percent::cpu3.inst 0.126630 # Average percentage of cache occupancy -system.cpu3.icache.tags.occ_percent::total 0.126630 # Average percentage of cache occupancy +system.cpu3.icache.tags.occ_blocks::cpu3.inst 64.803703 # Average occupied blocks per requestor +system.cpu3.icache.tags.occ_percent::cpu3.inst 0.126570 # Average percentage of cache occupancy +system.cpu3.icache.tags.occ_percent::total 0.126570 # Average percentage of cache occupancy system.cpu3.icache.tags.occ_task_id_blocks::1024 86 # Occupied blocks per task id -system.cpu3.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id -system.cpu3.icache.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id +system.cpu3.icache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id +system.cpu3.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id system.cpu3.icache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id system.cpu3.icache.tags.occ_task_id_percent::1024 0.167969 # Percentage of cache occupancy per task id -system.cpu3.icache.tags.tag_accesses 169839 # Number of tag accesses -system.cpu3.icache.tags.data_accesses 169839 # Number of data accesses -system.cpu3.icache.pwrStateResidencyTicks::UNDEFINED 264174500 # Cumulative time (in ticks) in various power states -system.cpu3.icache.ReadReq_hits::cpu3.inst 169105 # number of ReadReq hits -system.cpu3.icache.ReadReq_hits::total 169105 # number of ReadReq hits -system.cpu3.icache.demand_hits::cpu3.inst 169105 # number of demand (read+write) hits -system.cpu3.icache.demand_hits::total 169105 # number of demand (read+write) hits -system.cpu3.icache.overall_hits::cpu3.inst 169105 # number of overall hits -system.cpu3.icache.overall_hits::total 169105 # number of overall hits +system.cpu3.icache.tags.tag_accesses 170795 # Number of tag accesses +system.cpu3.icache.tags.data_accesses 170795 # Number of data accesses +system.cpu3.icache.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states +system.cpu3.icache.ReadReq_hits::cpu3.inst 170061 # number of ReadReq hits +system.cpu3.icache.ReadReq_hits::total 170061 # number of ReadReq hits +system.cpu3.icache.demand_hits::cpu3.inst 170061 # number of demand (read+write) hits +system.cpu3.icache.demand_hits::total 170061 # number of demand (read+write) hits +system.cpu3.icache.overall_hits::cpu3.inst 170061 # number of overall hits +system.cpu3.icache.overall_hits::total 170061 # number of overall hits system.cpu3.icache.ReadReq_misses::cpu3.inst 367 # number of ReadReq misses system.cpu3.icache.ReadReq_misses::total 367 # number of ReadReq misses system.cpu3.icache.demand_misses::cpu3.inst 367 # number of demand (read+write) misses system.cpu3.icache.demand_misses::total 367 # number of demand (read+write) misses system.cpu3.icache.overall_misses::cpu3.inst 367 # number of overall misses system.cpu3.icache.overall_misses::total 367 # number of overall misses -system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 5481500 # number of ReadReq miss cycles -system.cpu3.icache.ReadReq_miss_latency::total 5481500 # number of ReadReq miss cycles -system.cpu3.icache.demand_miss_latency::cpu3.inst 5481500 # number of demand (read+write) miss cycles -system.cpu3.icache.demand_miss_latency::total 5481500 # number of demand (read+write) miss cycles -system.cpu3.icache.overall_miss_latency::cpu3.inst 5481500 # number of overall miss cycles -system.cpu3.icache.overall_miss_latency::total 5481500 # number of overall miss cycles -system.cpu3.icache.ReadReq_accesses::cpu3.inst 169472 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.ReadReq_accesses::total 169472 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.demand_accesses::cpu3.inst 169472 # number of demand (read+write) accesses -system.cpu3.icache.demand_accesses::total 169472 # number of demand (read+write) accesses -system.cpu3.icache.overall_accesses::cpu3.inst 169472 # number of overall (read+write) accesses -system.cpu3.icache.overall_accesses::total 169472 # number of overall (read+write) accesses -system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.002166 # miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_miss_rate::total 0.002166 # miss rate for ReadReq accesses -system.cpu3.icache.demand_miss_rate::cpu3.inst 0.002166 # miss rate for demand accesses -system.cpu3.icache.demand_miss_rate::total 0.002166 # miss rate for demand accesses -system.cpu3.icache.overall_miss_rate::cpu3.inst 0.002166 # miss rate for overall accesses -system.cpu3.icache.overall_miss_rate::total 0.002166 # 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number of overall miss cycles +system.cpu3.icache.overall_miss_latency::total 5475500 # number of overall miss cycles +system.cpu3.icache.ReadReq_accesses::cpu3.inst 170428 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.ReadReq_accesses::total 170428 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.demand_accesses::cpu3.inst 170428 # number of demand (read+write) accesses +system.cpu3.icache.demand_accesses::total 170428 # number of demand (read+write) accesses +system.cpu3.icache.overall_accesses::cpu3.inst 170428 # number of overall (read+write) accesses +system.cpu3.icache.overall_accesses::total 170428 # number of overall (read+write) accesses +system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.002153 # miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_miss_rate::total 0.002153 # miss rate for ReadReq accesses +system.cpu3.icache.demand_miss_rate::cpu3.inst 0.002153 # miss rate for demand accesses +system.cpu3.icache.demand_miss_rate::total 0.002153 # miss rate for demand accesses +system.cpu3.icache.overall_miss_rate::cpu3.inst 0.002153 # miss rate for overall accesses +system.cpu3.icache.overall_miss_rate::total 0.002153 # miss rate for overall accesses +system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 14919.618529 # average ReadReq miss latency +system.cpu3.icache.ReadReq_avg_miss_latency::total 14919.618529 # average ReadReq miss latency +system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 14919.618529 # average overall miss latency +system.cpu3.icache.demand_avg_miss_latency::total 14919.618529 # average overall miss latency +system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 14919.618529 # average overall miss latency +system.cpu3.icache.overall_avg_miss_latency::total 14919.618529 # average overall miss latency system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1118,63 +1118,64 @@ system.cpu3.icache.demand_mshr_misses::cpu3.inst 367 system.cpu3.icache.demand_mshr_misses::total 367 # number of demand (read+write) MSHR misses system.cpu3.icache.overall_mshr_misses::cpu3.inst 367 # number of overall MSHR misses system.cpu3.icache.overall_mshr_misses::total 367 # number of overall MSHR misses -system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 5114500 # number of ReadReq MSHR miss cycles -system.cpu3.icache.ReadReq_mshr_miss_latency::total 5114500 # number of ReadReq MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 5114500 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_latency::total 5114500 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 5114500 # number of overall MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_latency::total 5114500 # number of overall MSHR miss cycles -system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.002166 # mshr miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.002166 # mshr miss rate for ReadReq accesses -system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.002166 # mshr miss rate for demand accesses -system.cpu3.icache.demand_mshr_miss_rate::total 0.002166 # mshr miss rate for demand accesses -system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.002166 # mshr miss rate for overall accesses -system.cpu3.icache.overall_mshr_miss_rate::total 0.002166 # mshr miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 13935.967302 # average ReadReq mshr miss latency -system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 13935.967302 # average ReadReq mshr miss latency -system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 13935.967302 # average overall mshr miss latency -system.cpu3.icache.demand_avg_mshr_miss_latency::total 13935.967302 # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 13935.967302 # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency::total 13935.967302 # average overall mshr miss latency -system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 264174500 # Cumulative time (in ticks) in various power states +system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 5108500 # number of ReadReq MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_latency::total 5108500 # number of ReadReq MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 5108500 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_latency::total 5108500 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 5108500 # number of overall MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_latency::total 5108500 # number of overall MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.002153 # mshr miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.002153 # mshr miss rate for ReadReq accesses +system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.002153 # mshr miss rate for demand accesses +system.cpu3.icache.demand_mshr_miss_rate::total 0.002153 # mshr miss rate for demand accesses +system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.002153 # mshr miss rate for overall accesses +system.cpu3.icache.overall_mshr_miss_rate::total 0.002153 # mshr miss rate for overall accesses +system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 13919.618529 # average ReadReq mshr miss latency +system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 13919.618529 # average ReadReq mshr miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 13919.618529 # average overall mshr miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency::total 13919.618529 # average overall mshr miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 13919.618529 # average overall mshr miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency::total 13919.618529 # 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Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 53.975789 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 6.154320 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 0.833705 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 46.678374 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 6.077199 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.inst 0.942850 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.data 0.802119 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.000013 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.003518 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.000824 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.000094 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.000013 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::cpu0.inst 230.500098 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 147.566608 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 6.217156 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 10.908895 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 46.660458 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 17.373358 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.inst 0.877256 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.data 10.560130 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::cpu0.inst 0.003517 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.002252 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.000095 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.000166 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu2.inst 0.000712 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.000093 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.inst 0.000014 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.data 0.000012 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.005293 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 429 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 374 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.006546 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 19677 # Number of tag accesses -system.l2c.tags.data_accesses 19677 # Number of data accesses -system.l2c.pwrStateResidencyTicks::UNDEFINED 264174500 # Cumulative time (in ticks) in various power states +system.l2c.tags.occ_percent::cpu2.data 0.000265 # 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number of overall hits -system.l2c.UpgradeReq_misses::cpu0.data 28 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 16 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2.data 17 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu3.data 16 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 77 # number of UpgradeReq misses system.l2c.ReadExReq_misses::cpu0.data 99 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu1.data 14 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu2.data 15 # number of ReadExReq misses @@ -1242,46 +1238,46 @@ system.l2c.overall_misses::cpu3.inst 10 # nu system.l2c.overall_misses::cpu3.data 16 # number of overall misses system.l2c.overall_misses::total 594 # number of overall misses system.l2c.ReadExReq_miss_latency::cpu0.data 5991000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 856000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 851500 # 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number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu1.data 16 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu2.data 17 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu3.data 16 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu2.data 16 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu3.data 17 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::total 79 # number of UpgradeReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu0.data 99 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu1.data 14 # number of ReadExReq accesses(hits+misses) @@ -1316,11 +1312,6 @@ system.l2c.overall_accesses::cpu2.data 26 # nu system.l2c.overall_accesses::cpu3.inst 367 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu3.data 25 # number of overall (read+write) accesses system.l2c.overall_accesses::total 1812 # number of overall (read+write) accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.933333 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.974684 # miss rate for UpgradeReq accesses system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses @@ -1355,77 +1346,72 @@ system.l2c.overall_miss_rate::cpu3.inst 0.027248 # mi system.l2c.overall_miss_rate::cpu3.data 0.640000 # miss rate for overall accesses system.l2c.overall_miss_rate::total 0.327815 # miss rate for overall accesses system.l2c.ReadExReq_avg_miss_latency::cpu0.data 60515.151515 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 61142.857143 # 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mshr miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.019126 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.027322 # mshr miss rate for ReadCleanReq accesses system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst 0.158470 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::cpu3.inst 0.010899 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu3.inst 0.002725 # mshr miss rate for ReadCleanReq accesses system.l2c.ReadCleanReq_mshr_miss_rate::total 0.226054 # mshr miss rate for ReadCleanReq accesses system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.929577 # mshr miss rate for ReadSharedReq accesses system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.090909 # mshr miss rate for ReadSharedReq accesses @@ -1510,99 +1486,94 @@ system.l2c.ReadSharedReq_mshr_miss_rate::cpu3.data 0.090909 system.l2c.ReadSharedReq_mshr_miss_rate::total 0.730769 # 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average overall mshr miss latency -system.membus.snoop_filter.tot_requests 916 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 338 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 50500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.data 51433.333333 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 50566.433566 # average overall mshr miss latency +system.membus.snoop_filter.tot_requests 839 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 261 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 264174500 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 430 # Transaction distribution -system.membus.trans_dist::UpgradeReq 272 # Transaction distribution +system.membus.trans_dist::UpgradeReq 195 # Transaction distribution system.membus.trans_dist::ReadExReq 208 # Transaction distribution system.membus.trans_dist::ReadExResp 142 # Transaction distribution system.membus.trans_dist::ReadSharedReq 430 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1482 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1482 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1405 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1405 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 36608 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size::total 36608 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 261 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 916 # Request fanout histogram +system.membus.snoop_fanout::samples 839 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 916 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 839 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 916 # Request fanout histogram -system.membus.reqLayer0.occupancy 683633 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) +system.membus.snoop_fanout::total 839 # Request fanout histogram +system.membus.reqLayer0.occupancy 587124 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) system.membus.respLayer1.occupancy 2860000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.1 # Layer utilization (%) system.toL2Bus.snoop_filter.tot_requests 3977 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 1110 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 1865 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.hit_single_requests 1097 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 1878 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 264174500 # Cumulative time (in ticks) in various power states +system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states system.toL2Bus.trans_dist::ReadResp 2225 # Transaction distribution system.toL2Bus.trans_dist::WritebackDirty 1 # Transaction distribution system.toL2Bus.trans_dist::WritebackClean 1056 # Transaction distribution @@ -1616,11 +1587,11 @@ system.toL2Bus.trans_dist::ReadSharedReq 659 # Tr system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1149 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 581 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1012 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 373 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 366 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 1012 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 377 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 365 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 1015 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 349 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 368 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count::total 5868 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 43648 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 10944 # Cumulative packet size per connected master and slave (bytes) @@ -1634,13 +1605,13 @@ system.toL2Bus.pkt_size::total 183616 # Cu system.toL2Bus.snoops 1028 # Total snoops (count) system.toL2Bus.snoopTraffic 53312 # Total snoop traffic (bytes) system.toL2Bus.snoop_fanout::samples 2919 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.272011 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 1.157273 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.282631 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 1.164624 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 1002 34.33% 34.33% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 784 26.86% 61.19% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 470 16.10% 77.29% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 663 22.71% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 771 26.41% 60.74% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 465 15.93% 76.67% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 681 23.33% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::5 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram @@ -1650,23 +1621,23 @@ system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram system.toL2Bus.snoop_fanout::total 2919 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 3051987 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.occupancy 3053983 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) system.toL2Bus.respLayer0.occupancy 700500 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.3 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 501494 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 499498 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 552489 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 550995 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 440975 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 431976 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.2 # Layer utilization (%) system.toL2Bus.respLayer4.occupancy 552491 # Layer occupancy (ticks) system.toL2Bus.respLayer4.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer5.occupancy 442472 # Layer occupancy (ticks) +system.toL2Bus.respLayer5.occupancy 427974 # Layer occupancy (ticks) system.toL2Bus.respLayer5.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer6.occupancy 553492 # Layer occupancy (ticks) +system.toL2Bus.respLayer6.occupancy 554986 # Layer occupancy (ticks) system.toL2Bus.respLayer6.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer7.occupancy 403476 # Layer occupancy (ticks) +system.toL2Bus.respLayer7.occupancy 431477 # Layer occupancy (ticks) system.toL2Bus.respLayer7.utilization 0.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt b/tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt index a994433c5..4b7a057ad 100644 --- a/tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt +++ b/tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt @@ -1,1771 +1,1777 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000502 # Number of seconds simulated -sim_ticks 501584000 # Number of ticks simulated -final_tick 501584000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000520 # Number of seconds simulated +sim_ticks 519755500 # Number of ticks simulated +final_tick 519755500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_tick_rate 67567713 # Simulator tick rate (ticks/s) -host_mem_usage 232512 # Number of bytes of host memory used -host_seconds 7.42 # Real time elapsed on the host +host_tick_rate 97602781 # Simulator tick rate (ticks/s) +host_mem_usage 236356 # Number of bytes of host memory used +host_seconds 5.33 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 501584000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu0 77173 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1 79943 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2 80467 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3 80557 # Number of bytes read from this memory -system.physmem.bytes_read::cpu4 77449 # Number of bytes read from this memory -system.physmem.bytes_read::cpu5 81573 # Number of bytes read from this memory -system.physmem.bytes_read::cpu6 79541 # Number of bytes read from this memory -system.physmem.bytes_read::cpu7 76446 # Number of bytes read from this memory -system.physmem.bytes_read::total 633149 # Number of bytes read from this memory -system.physmem.bytes_written::writebacks 399616 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0 5376 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1 5525 # Number of bytes written to this memory -system.physmem.bytes_written::cpu2 5482 # Number of bytes written to this memory -system.physmem.bytes_written::cpu3 5537 # Number of bytes written to this memory -system.physmem.bytes_written::cpu4 5496 # Number of bytes written to this memory -system.physmem.bytes_written::cpu5 5409 # Number of bytes written to this memory -system.physmem.bytes_written::cpu6 5437 # Number of bytes written to this memory -system.physmem.bytes_written::cpu7 5416 # Number of bytes written to this memory -system.physmem.bytes_written::total 443294 # Number of bytes written to this memory -system.physmem.num_reads::cpu0 10960 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1 10958 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2 11104 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3 10879 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu4 10858 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu5 10887 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu6 10871 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu7 10989 # Number of read requests responded to by this memory -system.physmem.num_reads::total 87506 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 6244 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0 5376 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1 5525 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu2 5482 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu3 5537 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu4 5496 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu5 5409 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu6 5437 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu7 5416 # Number of write requests responded to by this memory -system.physmem.num_writes::total 49922 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0 153858576 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1 159381081 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2 160425771 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3 160605203 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu4 154408833 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu5 162630786 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu6 158579620 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu7 152409168 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1262299037 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 796708029 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0 10718045 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1 11015104 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu2 10929376 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu3 11039028 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu4 10957287 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu5 10783837 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu6 10839660 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu7 10797793 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 883788159 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 796708029 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0 164576621 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1 170396185 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2 171355147 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3 171644231 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu4 165366120 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu5 173414622 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu6 169419280 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu7 163206960 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2146087196 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 501584000 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 519755500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu0 252685 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1 258147 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2 248443 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3 257431 # Number of bytes read from this memory +system.physmem.bytes_read::cpu4 256206 # Number of bytes read from this memory +system.physmem.bytes_read::cpu5 249786 # Number of bytes read from this memory +system.physmem.bytes_read::cpu6 257817 # Number of bytes read from this memory +system.physmem.bytes_read::cpu7 255503 # Number of bytes read from this memory +system.physmem.bytes_read::total 2036018 # Number of bytes read from this memory +system.physmem.bytes_written::writebacks 1421696 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0 5545 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1 5403 # Number of bytes written to this memory +system.physmem.bytes_written::cpu2 5468 # Number of bytes written to this memory +system.physmem.bytes_written::cpu3 5504 # Number of bytes written to this memory +system.physmem.bytes_written::cpu4 5430 # Number of bytes written to this memory +system.physmem.bytes_written::cpu5 5362 # Number of bytes written to this memory +system.physmem.bytes_written::cpu6 5562 # Number of bytes written to this memory +system.physmem.bytes_written::cpu7 5554 # Number of bytes written to this memory +system.physmem.bytes_written::total 1465524 # Number of bytes written to this memory +system.physmem.num_reads::cpu0 13663 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1 13833 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2 13579 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3 13621 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu4 13782 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu5 13599 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu6 13692 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu7 13646 # Number of read requests responded to by this memory +system.physmem.num_reads::total 109415 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 22214 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0 5545 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1 5403 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu2 5468 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu3 5504 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu4 5430 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu5 5362 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu6 5562 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu7 5554 # Number of write requests responded to by this memory +system.physmem.num_writes::total 66042 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0 486161282 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1 496670069 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2 477999752 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3 495292498 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu4 492935621 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu5 480583659 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu6 496035155 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu7 491583062 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3917261097 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2735316894 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0 10668478 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1 10395272 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu2 10520331 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu3 10589595 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu4 10447220 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu5 10316389 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu6 10701185 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu7 10685794 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2819641158 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2735316894 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0 496829759 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1 507065341 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2 488520083 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3 505882093 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu4 503382841 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu5 490900048 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu6 506736340 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu7 502268855 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6736902255 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 519755500 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu0.pwrStateResidencyTicks::UNDEFINED 501584000 # Cumulative time (in ticks) in various power states -system.cpu0.num_reads 99682 # number of read accesses completed -system.cpu0.num_writes 55240 # number of write accesses completed -system.cpu0.l1c.tags.pwrStateResidencyTicks::UNDEFINED 501584000 # Cumulative time (in ticks) in various power states -system.cpu0.l1c.tags.replacements 22392 # number of replacements -system.cpu0.l1c.tags.tagsinuse 393.390751 # Cycle average of tags in use -system.cpu0.l1c.tags.total_refs 13565 # Total number of references to valid blocks. -system.cpu0.l1c.tags.sampled_refs 22785 # Sample count of references to valid blocks. -system.cpu0.l1c.tags.avg_refs 0.595348 # Average number of references to valid blocks. +system.cpu0.pwrStateResidencyTicks::UNDEFINED 519755500 # Cumulative time (in ticks) in various power states +system.cpu0.num_reads 99523 # number of read accesses completed +system.cpu0.num_writes 55175 # number of write accesses completed +system.cpu0.l1c.tags.pwrStateResidencyTicks::UNDEFINED 519755500 # Cumulative time (in ticks) in various power states +system.cpu0.l1c.tags.replacements 22190 # number of replacements +system.cpu0.l1c.tags.tagsinuse 391.732266 # Cycle average of tags in use +system.cpu0.l1c.tags.total_refs 13637 # Total number of references to valid blocks. +system.cpu0.l1c.tags.sampled_refs 22577 # Sample count of references to valid blocks. +system.cpu0.l1c.tags.avg_refs 0.604022 # Average number of references to valid blocks. system.cpu0.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.l1c.tags.occ_blocks::cpu0 393.390751 # Average occupied blocks per requestor -system.cpu0.l1c.tags.occ_percent::cpu0 0.768341 # Average percentage of cache occupancy -system.cpu0.l1c.tags.occ_percent::total 0.768341 # Average percentage of cache occupancy -system.cpu0.l1c.tags.occ_task_id_blocks::1024 393 # Occupied blocks per task id -system.cpu0.l1c.tags.age_task_id_blocks_1024::0 383 # Occupied blocks per task id +system.cpu0.l1c.tags.occ_blocks::cpu0 391.732266 # Average occupied blocks per requestor +system.cpu0.l1c.tags.occ_percent::cpu0 0.765102 # Average percentage of cache occupancy +system.cpu0.l1c.tags.occ_percent::total 0.765102 # Average percentage of cache occupancy +system.cpu0.l1c.tags.occ_task_id_blocks::1024 387 # Occupied blocks per task id +system.cpu0.l1c.tags.age_task_id_blocks_1024::0 377 # Occupied blocks per task id system.cpu0.l1c.tags.age_task_id_blocks_1024::1 10 # Occupied blocks per task id -system.cpu0.l1c.tags.occ_task_id_percent::1024 0.767578 # Percentage of cache occupancy per task id -system.cpu0.l1c.tags.tag_accesses 339133 # Number of tag accesses -system.cpu0.l1c.tags.data_accesses 339133 # Number of data accesses -system.cpu0.l1c.pwrStateResidencyTicks::UNDEFINED 501584000 # Cumulative time (in ticks) in various power states -system.cpu0.l1c.ReadReq_hits::cpu0 8847 # number of ReadReq hits -system.cpu0.l1c.ReadReq_hits::total 8847 # number of ReadReq hits -system.cpu0.l1c.WriteReq_hits::cpu0 1120 # number of WriteReq hits -system.cpu0.l1c.WriteReq_hits::total 1120 # number of WriteReq hits -system.cpu0.l1c.demand_hits::cpu0 9967 # number of demand (read+write) hits -system.cpu0.l1c.demand_hits::total 9967 # number of demand (read+write) hits -system.cpu0.l1c.overall_hits::cpu0 9967 # number of overall hits -system.cpu0.l1c.overall_hits::total 9967 # number of overall hits -system.cpu0.l1c.ReadReq_misses::cpu0 36618 # number of ReadReq misses -system.cpu0.l1c.ReadReq_misses::total 36618 # number of ReadReq misses -system.cpu0.l1c.WriteReq_misses::cpu0 23969 # number of WriteReq misses -system.cpu0.l1c.WriteReq_misses::total 23969 # number of WriteReq misses -system.cpu0.l1c.demand_misses::cpu0 60587 # number of demand (read+write) misses -system.cpu0.l1c.demand_misses::total 60587 # number of demand (read+write) misses -system.cpu0.l1c.overall_misses::cpu0 60587 # number of overall misses -system.cpu0.l1c.overall_misses::total 60587 # number of overall misses -system.cpu0.l1c.ReadReq_miss_latency::cpu0 672506192 # number of ReadReq miss cycles -system.cpu0.l1c.ReadReq_miss_latency::total 672506192 # number of ReadReq miss cycles -system.cpu0.l1c.WriteReq_miss_latency::cpu0 563028530 # number of WriteReq miss cycles -system.cpu0.l1c.WriteReq_miss_latency::total 563028530 # number of WriteReq miss cycles -system.cpu0.l1c.demand_miss_latency::cpu0 1235534722 # number of demand (read+write) miss cycles -system.cpu0.l1c.demand_miss_latency::total 1235534722 # number of demand (read+write) miss cycles -system.cpu0.l1c.overall_miss_latency::cpu0 1235534722 # number of overall miss cycles -system.cpu0.l1c.overall_miss_latency::total 1235534722 # number of overall miss cycles -system.cpu0.l1c.ReadReq_accesses::cpu0 45465 # number of ReadReq accesses(hits+misses) -system.cpu0.l1c.ReadReq_accesses::total 45465 # number of ReadReq accesses(hits+misses) -system.cpu0.l1c.WriteReq_accesses::cpu0 25089 # number of WriteReq accesses(hits+misses) -system.cpu0.l1c.WriteReq_accesses::total 25089 # number of WriteReq accesses(hits+misses) -system.cpu0.l1c.demand_accesses::cpu0 70554 # number of demand (read+write) accesses -system.cpu0.l1c.demand_accesses::total 70554 # number of demand (read+write) accesses -system.cpu0.l1c.overall_accesses::cpu0 70554 # number of overall (read+write) accesses -system.cpu0.l1c.overall_accesses::total 70554 # number of overall (read+write) accesses -system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.805411 # miss rate for ReadReq accesses -system.cpu0.l1c.ReadReq_miss_rate::total 0.805411 # miss rate for ReadReq accesses -system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.955359 # miss rate for WriteReq accesses -system.cpu0.l1c.WriteReq_miss_rate::total 0.955359 # miss rate for WriteReq accesses -system.cpu0.l1c.demand_miss_rate::cpu0 0.858732 # miss rate for demand accesses -system.cpu0.l1c.demand_miss_rate::total 0.858732 # miss rate for demand accesses -system.cpu0.l1c.overall_miss_rate::cpu0 0.858732 # miss rate for overall accesses -system.cpu0.l1c.overall_miss_rate::total 0.858732 # miss rate for overall accesses -system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 18365.453930 # average ReadReq miss latency -system.cpu0.l1c.ReadReq_avg_miss_latency::total 18365.453930 # average ReadReq miss latency -system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 23489.863157 # average WriteReq miss latency -system.cpu0.l1c.WriteReq_avg_miss_latency::total 23489.863157 # average WriteReq miss latency -system.cpu0.l1c.demand_avg_miss_latency::cpu0 20392.736429 # average overall miss latency -system.cpu0.l1c.demand_avg_miss_latency::total 20392.736429 # average overall miss latency -system.cpu0.l1c.overall_avg_miss_latency::cpu0 20392.736429 # average overall miss latency -system.cpu0.l1c.overall_avg_miss_latency::total 20392.736429 # average overall miss latency -system.cpu0.l1c.blocked_cycles::no_mshrs 823442 # number of cycles access was blocked +system.cpu0.l1c.tags.occ_task_id_percent::1024 0.755859 # Percentage of cache occupancy per task id +system.cpu0.l1c.tags.tag_accesses 338094 # Number of tag accesses +system.cpu0.l1c.tags.data_accesses 338094 # Number of data accesses +system.cpu0.l1c.pwrStateResidencyTicks::UNDEFINED 519755500 # Cumulative time (in ticks) in various power states +system.cpu0.l1c.ReadReq_hits::cpu0 8745 # number of ReadReq hits +system.cpu0.l1c.ReadReq_hits::total 8745 # number of ReadReq hits +system.cpu0.l1c.WriteReq_hits::cpu0 1203 # number of WriteReq hits +system.cpu0.l1c.WriteReq_hits::total 1203 # number of WriteReq hits +system.cpu0.l1c.demand_hits::cpu0 9948 # number of demand (read+write) hits +system.cpu0.l1c.demand_hits::total 9948 # number of demand (read+write) hits +system.cpu0.l1c.overall_hits::cpu0 9948 # number of overall hits +system.cpu0.l1c.overall_hits::total 9948 # number of overall hits +system.cpu0.l1c.ReadReq_misses::cpu0 36338 # number of ReadReq misses +system.cpu0.l1c.ReadReq_misses::total 36338 # number of ReadReq misses +system.cpu0.l1c.WriteReq_misses::cpu0 24073 # number of WriteReq misses +system.cpu0.l1c.WriteReq_misses::total 24073 # number of WriteReq misses +system.cpu0.l1c.demand_misses::cpu0 60411 # number of demand (read+write) misses +system.cpu0.l1c.demand_misses::total 60411 # number of demand (read+write) misses +system.cpu0.l1c.overall_misses::cpu0 60411 # number of overall misses +system.cpu0.l1c.overall_misses::total 60411 # number of overall misses +system.cpu0.l1c.ReadReq_miss_latency::cpu0 720327390 # number of ReadReq miss cycles +system.cpu0.l1c.ReadReq_miss_latency::total 720327390 # number of ReadReq miss cycles +system.cpu0.l1c.WriteReq_miss_latency::cpu0 585363499 # number of WriteReq miss cycles +system.cpu0.l1c.WriteReq_miss_latency::total 585363499 # number of WriteReq miss cycles +system.cpu0.l1c.demand_miss_latency::cpu0 1305690889 # number of demand (read+write) miss cycles +system.cpu0.l1c.demand_miss_latency::total 1305690889 # number of demand (read+write) miss cycles +system.cpu0.l1c.overall_miss_latency::cpu0 1305690889 # number of overall miss cycles +system.cpu0.l1c.overall_miss_latency::total 1305690889 # number of overall miss cycles +system.cpu0.l1c.ReadReq_accesses::cpu0 45083 # number of ReadReq accesses(hits+misses) +system.cpu0.l1c.ReadReq_accesses::total 45083 # number of ReadReq accesses(hits+misses) +system.cpu0.l1c.WriteReq_accesses::cpu0 25276 # number of WriteReq accesses(hits+misses) +system.cpu0.l1c.WriteReq_accesses::total 25276 # number of WriteReq accesses(hits+misses) +system.cpu0.l1c.demand_accesses::cpu0 70359 # number of demand (read+write) accesses +system.cpu0.l1c.demand_accesses::total 70359 # number of demand (read+write) accesses +system.cpu0.l1c.overall_accesses::cpu0 70359 # number of overall (read+write) accesses +system.cpu0.l1c.overall_accesses::total 70359 # number of overall (read+write) accesses +system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.806024 # miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_miss_rate::total 0.806024 # miss rate for ReadReq accesses +system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.952405 # miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_miss_rate::total 0.952405 # miss rate for WriteReq accesses +system.cpu0.l1c.demand_miss_rate::cpu0 0.858611 # miss rate for demand accesses +system.cpu0.l1c.demand_miss_rate::total 0.858611 # miss rate for demand accesses +system.cpu0.l1c.overall_miss_rate::cpu0 0.858611 # miss rate for overall accesses +system.cpu0.l1c.overall_miss_rate::total 0.858611 # miss rate for overall accesses +system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 19822.978425 # average ReadReq miss latency +system.cpu0.l1c.ReadReq_avg_miss_latency::total 19822.978425 # average ReadReq miss latency +system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 24316.184065 # average WriteReq miss latency +system.cpu0.l1c.WriteReq_avg_miss_latency::total 24316.184065 # average WriteReq miss latency +system.cpu0.l1c.demand_avg_miss_latency::cpu0 21613.462598 # average overall miss latency +system.cpu0.l1c.demand_avg_miss_latency::total 21613.462598 # average overall miss latency +system.cpu0.l1c.overall_avg_miss_latency::cpu0 21613.462598 # average overall miss latency +system.cpu0.l1c.overall_avg_miss_latency::total 21613.462598 # average overall miss latency +system.cpu0.l1c.blocked_cycles::no_mshrs 881814 # number of cycles access was blocked system.cpu0.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.l1c.blocked::no_mshrs 66357 # number of cycles access was blocked +system.cpu0.l1c.blocked::no_mshrs 67116 # number of cycles access was blocked system.cpu0.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.l1c.avg_blocked_cycles::no_mshrs 12.409271 # average number of cycles each access was blocked +system.cpu0.l1c.avg_blocked_cycles::no_mshrs 13.138655 # average number of cycles each access was blocked system.cpu0.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.l1c.writebacks::writebacks 9844 # number of writebacks -system.cpu0.l1c.writebacks::total 9844 # number of writebacks -system.cpu0.l1c.ReadReq_mshr_misses::cpu0 36618 # number of ReadReq MSHR misses -system.cpu0.l1c.ReadReq_mshr_misses::total 36618 # number of ReadReq MSHR misses -system.cpu0.l1c.WriteReq_mshr_misses::cpu0 23969 # number of WriteReq MSHR misses -system.cpu0.l1c.WriteReq_mshr_misses::total 23969 # number of WriteReq MSHR misses -system.cpu0.l1c.demand_mshr_misses::cpu0 60587 # number of demand (read+write) MSHR misses -system.cpu0.l1c.demand_mshr_misses::total 60587 # number of demand (read+write) MSHR misses -system.cpu0.l1c.overall_mshr_misses::cpu0 60587 # number of overall MSHR misses -system.cpu0.l1c.overall_mshr_misses::total 60587 # number of overall MSHR misses -system.cpu0.l1c.ReadReq_mshr_uncacheable::cpu0 9910 # number of ReadReq MSHR uncacheable -system.cpu0.l1c.ReadReq_mshr_uncacheable::total 9910 # number of ReadReq MSHR uncacheable -system.cpu0.l1c.WriteReq_mshr_uncacheable::cpu0 5376 # number of WriteReq MSHR uncacheable -system.cpu0.l1c.WriteReq_mshr_uncacheable::total 5376 # number of WriteReq MSHR uncacheable -system.cpu0.l1c.overall_mshr_uncacheable_misses::cpu0 15286 # number of overall MSHR uncacheable misses -system.cpu0.l1c.overall_mshr_uncacheable_misses::total 15286 # number of overall MSHR uncacheable misses -system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0 635888192 # number of ReadReq MSHR miss cycles -system.cpu0.l1c.ReadReq_mshr_miss_latency::total 635888192 # number of ReadReq MSHR miss cycles -system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0 539061530 # number of WriteReq MSHR miss cycles -system.cpu0.l1c.WriteReq_mshr_miss_latency::total 539061530 # number of WriteReq MSHR miss cycles -system.cpu0.l1c.demand_mshr_miss_latency::cpu0 1174949722 # number of demand (read+write) MSHR miss cycles -system.cpu0.l1c.demand_mshr_miss_latency::total 1174949722 # number of demand (read+write) MSHR miss cycles -system.cpu0.l1c.overall_mshr_miss_latency::cpu0 1174949722 # number of overall MSHR miss cycles -system.cpu0.l1c.overall_mshr_miss_latency::total 1174949722 # number of overall MSHR miss cycles -system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 753971133 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 753971133 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 753971133 # number of overall MSHR uncacheable cycles -system.cpu0.l1c.overall_mshr_uncacheable_latency::total 753971133 # number of overall MSHR uncacheable cycles -system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.805411 # mshr miss rate for ReadReq accesses -system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.805411 # mshr miss rate for ReadReq accesses -system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.955359 # mshr miss rate for WriteReq accesses -system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.955359 # mshr miss rate for WriteReq accesses -system.cpu0.l1c.demand_mshr_miss_rate::cpu0 0.858732 # mshr miss rate for demand accesses -system.cpu0.l1c.demand_mshr_miss_rate::total 0.858732 # mshr miss rate for demand accesses -system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.858732 # mshr miss rate for overall accesses -system.cpu0.l1c.overall_mshr_miss_rate::total 0.858732 # mshr miss rate for overall accesses -system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 17365.453930 # average ReadReq mshr miss latency -system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 17365.453930 # average ReadReq mshr miss latency -system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 22489.946598 # average WriteReq mshr miss latency -system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 22489.946598 # average WriteReq mshr miss latency -system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 19392.769439 # average overall mshr miss latency -system.cpu0.l1c.demand_avg_mshr_miss_latency::total 19392.769439 # average overall mshr miss latency -system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 19392.769439 # average overall mshr miss latency -system.cpu0.l1c.overall_avg_mshr_miss_latency::total 19392.769439 # average overall mshr miss latency -system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0 76081.849950 # average ReadReq mshr uncacheable latency -system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total 76081.849950 # average ReadReq mshr uncacheable latency -system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 49324.292359 # average overall mshr uncacheable latency -system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total 49324.292359 # average overall mshr uncacheable latency -system.cpu1.pwrStateResidencyTicks::UNDEFINED 501584000 # Cumulative time (in ticks) in various power states -system.cpu1.num_reads 99541 # number of read accesses completed -system.cpu1.num_writes 55028 # number of write accesses completed -system.cpu1.l1c.tags.pwrStateResidencyTicks::UNDEFINED 501584000 # Cumulative time (in ticks) in various power states -system.cpu1.l1c.tags.replacements 22314 # number of replacements -system.cpu1.l1c.tags.tagsinuse 393.210618 # Cycle average of tags in use -system.cpu1.l1c.tags.total_refs 13573 # Total number of references to valid blocks. -system.cpu1.l1c.tags.sampled_refs 22722 # Sample count of references to valid blocks. -system.cpu1.l1c.tags.avg_refs 0.597351 # Average number of references to valid blocks. +system.cpu0.l1c.writebacks::writebacks 9797 # number of writebacks +system.cpu0.l1c.writebacks::total 9797 # number of writebacks +system.cpu0.l1c.ReadReq_mshr_misses::cpu0 36338 # number of ReadReq MSHR misses +system.cpu0.l1c.ReadReq_mshr_misses::total 36338 # number of ReadReq MSHR misses +system.cpu0.l1c.WriteReq_mshr_misses::cpu0 24073 # number of WriteReq MSHR misses +system.cpu0.l1c.WriteReq_mshr_misses::total 24073 # number of WriteReq MSHR misses +system.cpu0.l1c.demand_mshr_misses::cpu0 60411 # number of demand (read+write) MSHR misses +system.cpu0.l1c.demand_mshr_misses::total 60411 # number of demand (read+write) MSHR misses +system.cpu0.l1c.overall_mshr_misses::cpu0 60411 # number of overall MSHR misses +system.cpu0.l1c.overall_mshr_misses::total 60411 # number of overall MSHR misses +system.cpu0.l1c.ReadReq_mshr_uncacheable::cpu0 9869 # number of ReadReq MSHR uncacheable +system.cpu0.l1c.ReadReq_mshr_uncacheable::total 9869 # number of ReadReq MSHR uncacheable +system.cpu0.l1c.WriteReq_mshr_uncacheable::cpu0 5547 # number of WriteReq MSHR uncacheable +system.cpu0.l1c.WriteReq_mshr_uncacheable::total 5547 # number of WriteReq MSHR uncacheable +system.cpu0.l1c.overall_mshr_uncacheable_misses::cpu0 15416 # number of overall MSHR uncacheable misses +system.cpu0.l1c.overall_mshr_uncacheable_misses::total 15416 # number of overall MSHR uncacheable misses +system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0 683989390 # number of ReadReq MSHR miss cycles +system.cpu0.l1c.ReadReq_mshr_miss_latency::total 683989390 # number of ReadReq MSHR miss cycles +system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0 561290499 # number of WriteReq MSHR miss cycles +system.cpu0.l1c.WriteReq_mshr_miss_latency::total 561290499 # number of WriteReq MSHR miss cycles +system.cpu0.l1c.demand_mshr_miss_latency::cpu0 1245279889 # number of demand (read+write) MSHR miss cycles +system.cpu0.l1c.demand_mshr_miss_latency::total 1245279889 # number of demand (read+write) MSHR miss cycles +system.cpu0.l1c.overall_mshr_miss_latency::cpu0 1245279889 # number of overall MSHR miss cycles +system.cpu0.l1c.overall_mshr_miss_latency::total 1245279889 # number of overall MSHR miss cycles +system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 771084187 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 771084187 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 771084187 # number of overall MSHR uncacheable cycles +system.cpu0.l1c.overall_mshr_uncacheable_latency::total 771084187 # number of overall MSHR uncacheable cycles +system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.806024 # mshr miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.806024 # mshr miss rate for ReadReq accesses +system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.952405 # mshr miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.952405 # mshr miss rate for WriteReq accesses +system.cpu0.l1c.demand_mshr_miss_rate::cpu0 0.858611 # mshr miss rate for demand accesses +system.cpu0.l1c.demand_mshr_miss_rate::total 0.858611 # mshr miss rate for demand accesses +system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.858611 # mshr miss rate for overall accesses +system.cpu0.l1c.overall_mshr_miss_rate::total 0.858611 # mshr miss rate for overall accesses +system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 18822.978425 # average ReadReq mshr miss latency +system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 18822.978425 # average ReadReq mshr miss latency +system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 23316.184065 # average WriteReq mshr miss latency +system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 23316.184065 # average WriteReq mshr miss latency +system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 20613.462598 # average overall mshr miss latency +system.cpu0.l1c.demand_avg_mshr_miss_latency::total 20613.462598 # average overall mshr miss latency +system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 20613.462598 # average overall mshr miss latency +system.cpu0.l1c.overall_avg_mshr_miss_latency::total 20613.462598 # average overall mshr miss latency +system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0 78131.947208 # average ReadReq mshr uncacheable latency +system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total 78131.947208 # average ReadReq mshr uncacheable latency +system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 50018.434549 # average overall mshr uncacheable latency +system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total 50018.434549 # average overall mshr uncacheable latency +system.cpu1.pwrStateResidencyTicks::UNDEFINED 519755500 # Cumulative time (in ticks) in various power states +system.cpu1.num_reads 99560 # number of read accesses completed +system.cpu1.num_writes 54738 # number of write accesses completed +system.cpu1.l1c.tags.pwrStateResidencyTicks::UNDEFINED 519755500 # Cumulative time (in ticks) in various power states +system.cpu1.l1c.tags.replacements 22160 # number of replacements +system.cpu1.l1c.tags.tagsinuse 392.166928 # Cycle average of tags in use +system.cpu1.l1c.tags.total_refs 13521 # Total number of references to valid blocks. +system.cpu1.l1c.tags.sampled_refs 22561 # Sample count of references to valid blocks. +system.cpu1.l1c.tags.avg_refs 0.599309 # Average number of references to valid blocks. system.cpu1.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l1c.tags.occ_blocks::cpu1 393.210618 # Average occupied blocks per requestor -system.cpu1.l1c.tags.occ_percent::cpu1 0.767989 # Average percentage of cache occupancy -system.cpu1.l1c.tags.occ_percent::total 0.767989 # Average percentage of cache occupancy -system.cpu1.l1c.tags.occ_task_id_blocks::1024 408 # Occupied blocks per task id -system.cpu1.l1c.tags.age_task_id_blocks_1024::0 399 # Occupied blocks per task id -system.cpu1.l1c.tags.age_task_id_blocks_1024::1 9 # Occupied blocks per task id -system.cpu1.l1c.tags.occ_task_id_percent::1024 0.796875 # Percentage of cache occupancy per task id -system.cpu1.l1c.tags.tag_accesses 338638 # Number of tag accesses -system.cpu1.l1c.tags.data_accesses 338638 # Number of data accesses -system.cpu1.l1c.pwrStateResidencyTicks::UNDEFINED 501584000 # Cumulative time (in ticks) in various power states -system.cpu1.l1c.ReadReq_hits::cpu1 8704 # number of ReadReq hits -system.cpu1.l1c.ReadReq_hits::total 8704 # number of ReadReq hits -system.cpu1.l1c.WriteReq_hits::cpu1 1149 # number of WriteReq hits -system.cpu1.l1c.WriteReq_hits::total 1149 # number of WriteReq hits -system.cpu1.l1c.demand_hits::cpu1 9853 # number of demand (read+write) hits -system.cpu1.l1c.demand_hits::total 9853 # number of demand (read+write) hits -system.cpu1.l1c.overall_hits::cpu1 9853 # number of overall hits -system.cpu1.l1c.overall_hits::total 9853 # number of overall hits -system.cpu1.l1c.ReadReq_misses::cpu1 36652 # number of ReadReq misses -system.cpu1.l1c.ReadReq_misses::total 36652 # number of ReadReq misses -system.cpu1.l1c.WriteReq_misses::cpu1 23946 # number of WriteReq misses -system.cpu1.l1c.WriteReq_misses::total 23946 # number of WriteReq misses -system.cpu1.l1c.demand_misses::cpu1 60598 # number of demand (read+write) misses -system.cpu1.l1c.demand_misses::total 60598 # number of demand (read+write) misses -system.cpu1.l1c.overall_misses::cpu1 60598 # number of overall misses -system.cpu1.l1c.overall_misses::total 60598 # number of overall misses -system.cpu1.l1c.ReadReq_miss_latency::cpu1 672762640 # number of ReadReq miss cycles -system.cpu1.l1c.ReadReq_miss_latency::total 672762640 # number of ReadReq miss cycles -system.cpu1.l1c.WriteReq_miss_latency::cpu1 564762705 # number of WriteReq miss cycles -system.cpu1.l1c.WriteReq_miss_latency::total 564762705 # number of WriteReq miss cycles -system.cpu1.l1c.demand_miss_latency::cpu1 1237525345 # number of demand (read+write) miss cycles -system.cpu1.l1c.demand_miss_latency::total 1237525345 # number of demand (read+write) miss cycles -system.cpu1.l1c.overall_miss_latency::cpu1 1237525345 # number of overall miss cycles -system.cpu1.l1c.overall_miss_latency::total 1237525345 # number of overall miss cycles -system.cpu1.l1c.ReadReq_accesses::cpu1 45356 # number of ReadReq accesses(hits+misses) -system.cpu1.l1c.ReadReq_accesses::total 45356 # number of ReadReq accesses(hits+misses) -system.cpu1.l1c.WriteReq_accesses::cpu1 25095 # number of WriteReq accesses(hits+misses) -system.cpu1.l1c.WriteReq_accesses::total 25095 # number of WriteReq accesses(hits+misses) -system.cpu1.l1c.demand_accesses::cpu1 70451 # number of demand (read+write) accesses -system.cpu1.l1c.demand_accesses::total 70451 # number of demand (read+write) accesses -system.cpu1.l1c.overall_accesses::cpu1 70451 # number of overall (read+write) accesses -system.cpu1.l1c.overall_accesses::total 70451 # number of overall (read+write) accesses -system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.808096 # miss rate for ReadReq accesses -system.cpu1.l1c.ReadReq_miss_rate::total 0.808096 # miss rate for ReadReq accesses -system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.954214 # miss rate for WriteReq accesses -system.cpu1.l1c.WriteReq_miss_rate::total 0.954214 # miss rate for WriteReq accesses -system.cpu1.l1c.demand_miss_rate::cpu1 0.860144 # miss rate for demand accesses -system.cpu1.l1c.demand_miss_rate::total 0.860144 # miss rate for demand accesses -system.cpu1.l1c.overall_miss_rate::cpu1 0.860144 # miss rate for overall accesses -system.cpu1.l1c.overall_miss_rate::total 0.860144 # miss rate for overall accesses -system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 18355.414166 # average ReadReq miss latency -system.cpu1.l1c.ReadReq_avg_miss_latency::total 18355.414166 # average ReadReq miss latency -system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 23584.845277 # average WriteReq miss latency -system.cpu1.l1c.WriteReq_avg_miss_latency::total 23584.845277 # average WriteReq miss latency -system.cpu1.l1c.demand_avg_miss_latency::cpu1 20421.884303 # average overall miss latency -system.cpu1.l1c.demand_avg_miss_latency::total 20421.884303 # average overall miss latency -system.cpu1.l1c.overall_avg_miss_latency::cpu1 20421.884303 # average overall miss latency -system.cpu1.l1c.overall_avg_miss_latency::total 20421.884303 # average overall miss latency -system.cpu1.l1c.blocked_cycles::no_mshrs 822356 # number of cycles access was blocked +system.cpu1.l1c.tags.occ_blocks::cpu1 392.166928 # Average occupied blocks per requestor +system.cpu1.l1c.tags.occ_percent::cpu1 0.765951 # Average percentage of cache occupancy +system.cpu1.l1c.tags.occ_percent::total 0.765951 # Average percentage of cache occupancy +system.cpu1.l1c.tags.occ_task_id_blocks::1024 401 # Occupied blocks per task id +system.cpu1.l1c.tags.age_task_id_blocks_1024::0 386 # Occupied blocks per task id +system.cpu1.l1c.tags.age_task_id_blocks_1024::1 15 # Occupied blocks per task id +system.cpu1.l1c.tags.occ_task_id_percent::1024 0.783203 # Percentage of cache occupancy per task id +system.cpu1.l1c.tags.tag_accesses 337076 # Number of tag accesses +system.cpu1.l1c.tags.data_accesses 337076 # Number of data accesses +system.cpu1.l1c.pwrStateResidencyTicks::UNDEFINED 519755500 # Cumulative time (in ticks) in various power states +system.cpu1.l1c.ReadReq_hits::cpu1 8807 # number of ReadReq hits +system.cpu1.l1c.ReadReq_hits::total 8807 # number of ReadReq hits +system.cpu1.l1c.WriteReq_hits::cpu1 1218 # number of WriteReq hits +system.cpu1.l1c.WriteReq_hits::total 1218 # number of WriteReq hits +system.cpu1.l1c.demand_hits::cpu1 10025 # number of demand (read+write) hits +system.cpu1.l1c.demand_hits::total 10025 # number of demand (read+write) hits +system.cpu1.l1c.overall_hits::cpu1 10025 # number of overall hits +system.cpu1.l1c.overall_hits::total 10025 # number of overall hits +system.cpu1.l1c.ReadReq_misses::cpu1 36399 # number of ReadReq misses +system.cpu1.l1c.ReadReq_misses::total 36399 # number of ReadReq misses +system.cpu1.l1c.WriteReq_misses::cpu1 23708 # number of WriteReq misses +system.cpu1.l1c.WriteReq_misses::total 23708 # number of WriteReq misses +system.cpu1.l1c.demand_misses::cpu1 60107 # number of demand (read+write) misses +system.cpu1.l1c.demand_misses::total 60107 # number of demand (read+write) misses +system.cpu1.l1c.overall_misses::cpu1 60107 # number of overall misses +system.cpu1.l1c.overall_misses::total 60107 # number of overall misses +system.cpu1.l1c.ReadReq_miss_latency::cpu1 728138208 # number of ReadReq miss cycles +system.cpu1.l1c.ReadReq_miss_latency::total 728138208 # number of ReadReq miss cycles +system.cpu1.l1c.WriteReq_miss_latency::cpu1 572668423 # number of WriteReq miss cycles +system.cpu1.l1c.WriteReq_miss_latency::total 572668423 # number of WriteReq miss cycles +system.cpu1.l1c.demand_miss_latency::cpu1 1300806631 # number of demand (read+write) miss cycles +system.cpu1.l1c.demand_miss_latency::total 1300806631 # number of demand (read+write) miss cycles +system.cpu1.l1c.overall_miss_latency::cpu1 1300806631 # number of overall miss cycles +system.cpu1.l1c.overall_miss_latency::total 1300806631 # number of overall miss cycles +system.cpu1.l1c.ReadReq_accesses::cpu1 45206 # number of ReadReq accesses(hits+misses) +system.cpu1.l1c.ReadReq_accesses::total 45206 # number of ReadReq accesses(hits+misses) +system.cpu1.l1c.WriteReq_accesses::cpu1 24926 # number of WriteReq accesses(hits+misses) +system.cpu1.l1c.WriteReq_accesses::total 24926 # number of WriteReq accesses(hits+misses) +system.cpu1.l1c.demand_accesses::cpu1 70132 # number of demand (read+write) accesses +system.cpu1.l1c.demand_accesses::total 70132 # number of demand (read+write) accesses +system.cpu1.l1c.overall_accesses::cpu1 70132 # number of overall (read+write) accesses +system.cpu1.l1c.overall_accesses::total 70132 # number of overall (read+write) accesses +system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.805181 # miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_miss_rate::total 0.805181 # miss rate for ReadReq accesses +system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.951135 # miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_miss_rate::total 0.951135 # miss rate for WriteReq accesses +system.cpu1.l1c.demand_miss_rate::cpu1 0.857055 # miss rate for demand accesses +system.cpu1.l1c.demand_miss_rate::total 0.857055 # miss rate for demand accesses +system.cpu1.l1c.overall_miss_rate::cpu1 0.857055 # miss rate for overall accesses +system.cpu1.l1c.overall_miss_rate::total 0.857055 # miss rate for overall accesses +system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 20004.346493 # average ReadReq miss latency +system.cpu1.l1c.ReadReq_avg_miss_latency::total 20004.346493 # average ReadReq miss latency +system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 24155.070989 # average WriteReq miss latency +system.cpu1.l1c.WriteReq_avg_miss_latency::total 24155.070989 # average WriteReq miss latency +system.cpu1.l1c.demand_avg_miss_latency::cpu1 21641.516479 # average overall miss latency +system.cpu1.l1c.demand_avg_miss_latency::total 21641.516479 # average overall miss latency +system.cpu1.l1c.overall_avg_miss_latency::cpu1 21641.516479 # average overall miss latency +system.cpu1.l1c.overall_avg_miss_latency::total 21641.516479 # average overall miss latency +system.cpu1.l1c.blocked_cycles::no_mshrs 883013 # number of cycles access was blocked system.cpu1.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.l1c.blocked::no_mshrs 66159 # number of cycles access was blocked +system.cpu1.l1c.blocked::no_mshrs 66936 # number of cycles access was blocked system.cpu1.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.l1c.avg_blocked_cycles::no_mshrs 12.429994 # average number of cycles each access was blocked +system.cpu1.l1c.avg_blocked_cycles::no_mshrs 13.191900 # average number of cycles each access was blocked system.cpu1.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.l1c.writebacks::writebacks 9894 # number of writebacks -system.cpu1.l1c.writebacks::total 9894 # number of writebacks -system.cpu1.l1c.ReadReq_mshr_misses::cpu1 36652 # number of ReadReq MSHR misses -system.cpu1.l1c.ReadReq_mshr_misses::total 36652 # number of ReadReq MSHR misses -system.cpu1.l1c.WriteReq_mshr_misses::cpu1 23946 # number of WriteReq MSHR misses -system.cpu1.l1c.WriteReq_mshr_misses::total 23946 # number of WriteReq MSHR misses -system.cpu1.l1c.demand_mshr_misses::cpu1 60598 # number of demand (read+write) MSHR misses -system.cpu1.l1c.demand_mshr_misses::total 60598 # number of demand (read+write) MSHR misses -system.cpu1.l1c.overall_mshr_misses::cpu1 60598 # number of overall MSHR misses -system.cpu1.l1c.overall_mshr_misses::total 60598 # number of overall MSHR misses -system.cpu1.l1c.ReadReq_mshr_uncacheable::cpu1 9864 # number of ReadReq MSHR uncacheable -system.cpu1.l1c.ReadReq_mshr_uncacheable::total 9864 # number of ReadReq MSHR uncacheable -system.cpu1.l1c.WriteReq_mshr_uncacheable::cpu1 5527 # number of WriteReq MSHR uncacheable -system.cpu1.l1c.WriteReq_mshr_uncacheable::total 5527 # number of WriteReq MSHR uncacheable -system.cpu1.l1c.overall_mshr_uncacheable_misses::cpu1 15391 # number of overall MSHR uncacheable misses -system.cpu1.l1c.overall_mshr_uncacheable_misses::total 15391 # number of overall MSHR uncacheable misses -system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1 636111640 # number of ReadReq MSHR miss cycles -system.cpu1.l1c.ReadReq_mshr_miss_latency::total 636111640 # number of ReadReq MSHR miss cycles -system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 540817705 # number of WriteReq MSHR miss cycles -system.cpu1.l1c.WriteReq_mshr_miss_latency::total 540817705 # number of WriteReq MSHR miss cycles -system.cpu1.l1c.demand_mshr_miss_latency::cpu1 1176929345 # number of demand (read+write) MSHR miss cycles -system.cpu1.l1c.demand_mshr_miss_latency::total 1176929345 # number of demand (read+write) MSHR miss cycles -system.cpu1.l1c.overall_mshr_miss_latency::cpu1 1176929345 # number of overall MSHR miss cycles -system.cpu1.l1c.overall_mshr_miss_latency::total 1176929345 # number of overall MSHR miss cycles -system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 750538193 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 750538193 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 750538193 # number of overall MSHR uncacheable cycles -system.cpu1.l1c.overall_mshr_uncacheable_latency::total 750538193 # number of overall MSHR uncacheable cycles -system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.808096 # mshr miss rate for ReadReq accesses -system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.808096 # mshr miss rate for ReadReq accesses -system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.954214 # mshr miss rate for WriteReq accesses -system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.954214 # mshr miss rate for WriteReq accesses -system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.860144 # mshr miss rate for demand accesses -system.cpu1.l1c.demand_mshr_miss_rate::total 0.860144 # mshr miss rate for demand accesses -system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.860144 # mshr miss rate for overall accesses -system.cpu1.l1c.overall_mshr_miss_rate::total 0.860144 # mshr miss rate for overall accesses -system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 17355.441449 # average ReadReq mshr miss latency -system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 17355.441449 # average ReadReq mshr miss latency -system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 22584.887038 # average WriteReq mshr miss latency -system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 22584.887038 # average WriteReq mshr miss latency -system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 19421.917308 # average overall mshr miss latency -system.cpu1.l1c.demand_avg_mshr_miss_latency::total 19421.917308 # average overall mshr miss latency -system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 19421.917308 # average overall mshr miss latency -system.cpu1.l1c.overall_avg_mshr_miss_latency::total 19421.917308 # average overall mshr miss latency -system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 76088.624594 # average ReadReq mshr uncacheable latency -system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total 76088.624594 # average ReadReq mshr uncacheable latency -system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 48764.745176 # average overall mshr uncacheable latency -system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total 48764.745176 # average overall mshr uncacheable latency -system.cpu2.pwrStateResidencyTicks::UNDEFINED 501584000 # Cumulative time (in ticks) in various power states -system.cpu2.num_reads 99993 # number of read accesses completed -system.cpu2.num_writes 55211 # number of write accesses completed -system.cpu2.l1c.tags.pwrStateResidencyTicks::UNDEFINED 501584000 # Cumulative time (in ticks) in various power states -system.cpu2.l1c.tags.replacements 22333 # number of replacements -system.cpu2.l1c.tags.tagsinuse 392.533782 # Cycle average of tags in use -system.cpu2.l1c.tags.total_refs 13552 # Total number of references to valid blocks. -system.cpu2.l1c.tags.sampled_refs 22757 # Sample count of references to valid blocks. -system.cpu2.l1c.tags.avg_refs 0.595509 # Average number of references to valid blocks. +system.cpu1.l1c.writebacks::writebacks 9595 # number of writebacks +system.cpu1.l1c.writebacks::total 9595 # number of writebacks +system.cpu1.l1c.ReadReq_mshr_misses::cpu1 36399 # number of ReadReq MSHR misses +system.cpu1.l1c.ReadReq_mshr_misses::total 36399 # number of ReadReq MSHR misses +system.cpu1.l1c.WriteReq_mshr_misses::cpu1 23708 # number of WriteReq MSHR misses +system.cpu1.l1c.WriteReq_mshr_misses::total 23708 # number of WriteReq MSHR misses +system.cpu1.l1c.demand_mshr_misses::cpu1 60107 # number of demand (read+write) MSHR misses +system.cpu1.l1c.demand_mshr_misses::total 60107 # number of demand (read+write) MSHR misses +system.cpu1.l1c.overall_mshr_misses::cpu1 60107 # number of overall MSHR misses +system.cpu1.l1c.overall_mshr_misses::total 60107 # number of overall MSHR misses +system.cpu1.l1c.ReadReq_mshr_uncacheable::cpu1 9955 # number of ReadReq MSHR uncacheable +system.cpu1.l1c.ReadReq_mshr_uncacheable::total 9955 # number of ReadReq MSHR uncacheable +system.cpu1.l1c.WriteReq_mshr_uncacheable::cpu1 5404 # number of WriteReq MSHR uncacheable +system.cpu1.l1c.WriteReq_mshr_uncacheable::total 5404 # number of WriteReq MSHR uncacheable +system.cpu1.l1c.overall_mshr_uncacheable_misses::cpu1 15359 # number of overall MSHR uncacheable misses +system.cpu1.l1c.overall_mshr_uncacheable_misses::total 15359 # number of overall MSHR uncacheable misses +system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1 691742208 # number of ReadReq MSHR miss cycles +system.cpu1.l1c.ReadReq_mshr_miss_latency::total 691742208 # number of ReadReq MSHR miss cycles +system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 548961423 # number of WriteReq MSHR miss cycles +system.cpu1.l1c.WriteReq_mshr_miss_latency::total 548961423 # number of WriteReq MSHR miss cycles +system.cpu1.l1c.demand_mshr_miss_latency::cpu1 1240703631 # number of demand (read+write) MSHR miss cycles +system.cpu1.l1c.demand_mshr_miss_latency::total 1240703631 # number of demand (read+write) MSHR miss cycles +system.cpu1.l1c.overall_mshr_miss_latency::cpu1 1240703631 # number of overall MSHR miss cycles +system.cpu1.l1c.overall_mshr_miss_latency::total 1240703631 # number of overall MSHR miss cycles +system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 776683501 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 776683501 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 776683501 # number of overall MSHR uncacheable cycles +system.cpu1.l1c.overall_mshr_uncacheable_latency::total 776683501 # number of overall MSHR uncacheable cycles +system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.805181 # mshr miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.805181 # mshr miss rate for ReadReq accesses +system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.951135 # mshr miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.951135 # mshr miss rate for WriteReq accesses +system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.857055 # mshr miss rate for demand accesses +system.cpu1.l1c.demand_mshr_miss_rate::total 0.857055 # mshr miss rate for demand accesses +system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.857055 # mshr miss rate for overall accesses +system.cpu1.l1c.overall_mshr_miss_rate::total 0.857055 # mshr miss rate for overall accesses +system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 19004.428913 # average ReadReq mshr miss latency +system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 19004.428913 # average ReadReq mshr miss latency +system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 23155.113169 # average WriteReq mshr miss latency +system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 23155.113169 # average WriteReq mshr miss latency +system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 20641.583027 # average overall mshr miss latency +system.cpu1.l1c.demand_avg_mshr_miss_latency::total 20641.583027 # average overall mshr miss latency +system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 20641.583027 # average overall mshr miss latency +system.cpu1.l1c.overall_avg_mshr_miss_latency::total 20641.583027 # average overall mshr miss latency +system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 78019.437569 # average ReadReq mshr uncacheable latency +system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total 78019.437569 # average ReadReq mshr uncacheable latency +system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 50568.624325 # average overall mshr uncacheable latency +system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total 50568.624325 # average overall mshr uncacheable latency +system.cpu2.pwrStateResidencyTicks::UNDEFINED 519755500 # Cumulative time (in ticks) in various power states +system.cpu2.num_reads 98983 # number of read accesses completed +system.cpu2.num_writes 55204 # number of write accesses completed +system.cpu2.l1c.tags.pwrStateResidencyTicks::UNDEFINED 519755500 # Cumulative time (in ticks) in various power states +system.cpu2.l1c.tags.replacements 22113 # number of replacements +system.cpu2.l1c.tags.tagsinuse 391.892697 # Cycle average of tags in use +system.cpu2.l1c.tags.total_refs 13532 # Total number of references to valid blocks. +system.cpu2.l1c.tags.sampled_refs 22515 # Sample count of references to valid blocks. +system.cpu2.l1c.tags.avg_refs 0.601022 # Average number of references to valid blocks. system.cpu2.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.l1c.tags.occ_blocks::cpu2 392.533782 # Average occupied blocks per requestor -system.cpu2.l1c.tags.occ_percent::cpu2 0.766668 # Average percentage of cache occupancy -system.cpu2.l1c.tags.occ_percent::total 0.766668 # Average percentage of cache occupancy -system.cpu2.l1c.tags.occ_task_id_blocks::1024 424 # Occupied blocks per task id -system.cpu2.l1c.tags.age_task_id_blocks_1024::0 419 # Occupied blocks per task id -system.cpu2.l1c.tags.age_task_id_blocks_1024::1 5 # Occupied blocks per task id -system.cpu2.l1c.tags.occ_task_id_percent::1024 0.828125 # Percentage of cache occupancy per task id -system.cpu2.l1c.tags.tag_accesses 338842 # Number of tag accesses -system.cpu2.l1c.tags.data_accesses 338842 # Number of data accesses -system.cpu2.l1c.pwrStateResidencyTicks::UNDEFINED 501584000 # Cumulative time (in ticks) in various power states -system.cpu2.l1c.ReadReq_hits::cpu2 8700 # number of ReadReq hits -system.cpu2.l1c.ReadReq_hits::total 8700 # number of ReadReq hits -system.cpu2.l1c.WriteReq_hits::cpu2 1131 # number of WriteReq hits -system.cpu2.l1c.WriteReq_hits::total 1131 # number of WriteReq hits -system.cpu2.l1c.demand_hits::cpu2 9831 # number of demand (read+write) hits -system.cpu2.l1c.demand_hits::total 9831 # number of demand (read+write) hits -system.cpu2.l1c.overall_hits::cpu2 9831 # number of overall hits -system.cpu2.l1c.overall_hits::total 9831 # number of overall hits -system.cpu2.l1c.ReadReq_misses::cpu2 36743 # number of ReadReq misses -system.cpu2.l1c.ReadReq_misses::total 36743 # number of ReadReq misses -system.cpu2.l1c.WriteReq_misses::cpu2 23917 # number of WriteReq misses -system.cpu2.l1c.WriteReq_misses::total 23917 # number of WriteReq misses -system.cpu2.l1c.demand_misses::cpu2 60660 # number of demand (read+write) misses -system.cpu2.l1c.demand_misses::total 60660 # number of demand (read+write) misses -system.cpu2.l1c.overall_misses::cpu2 60660 # number of overall misses -system.cpu2.l1c.overall_misses::total 60660 # number of overall misses -system.cpu2.l1c.ReadReq_miss_latency::cpu2 667892138 # number of ReadReq miss cycles -system.cpu2.l1c.ReadReq_miss_latency::total 667892138 # number of ReadReq miss cycles -system.cpu2.l1c.WriteReq_miss_latency::cpu2 561829218 # number of WriteReq miss cycles -system.cpu2.l1c.WriteReq_miss_latency::total 561829218 # number of WriteReq miss cycles -system.cpu2.l1c.demand_miss_latency::cpu2 1229721356 # number of demand (read+write) miss cycles -system.cpu2.l1c.demand_miss_latency::total 1229721356 # number of demand (read+write) miss cycles -system.cpu2.l1c.overall_miss_latency::cpu2 1229721356 # number of overall miss cycles -system.cpu2.l1c.overall_miss_latency::total 1229721356 # number of overall miss cycles -system.cpu2.l1c.ReadReq_accesses::cpu2 45443 # number of ReadReq accesses(hits+misses) -system.cpu2.l1c.ReadReq_accesses::total 45443 # number of ReadReq accesses(hits+misses) -system.cpu2.l1c.WriteReq_accesses::cpu2 25048 # number of WriteReq accesses(hits+misses) -system.cpu2.l1c.WriteReq_accesses::total 25048 # number of WriteReq accesses(hits+misses) -system.cpu2.l1c.demand_accesses::cpu2 70491 # number of demand (read+write) accesses -system.cpu2.l1c.demand_accesses::total 70491 # number of demand (read+write) accesses -system.cpu2.l1c.overall_accesses::cpu2 70491 # number of overall (read+write) accesses -system.cpu2.l1c.overall_accesses::total 70491 # number of overall (read+write) accesses -system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.808551 # miss rate for ReadReq accesses -system.cpu2.l1c.ReadReq_miss_rate::total 0.808551 # miss rate for ReadReq accesses -system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.954847 # miss rate for WriteReq accesses -system.cpu2.l1c.WriteReq_miss_rate::total 0.954847 # miss rate for WriteReq accesses -system.cpu2.l1c.demand_miss_rate::cpu2 0.860535 # miss rate for demand accesses -system.cpu2.l1c.demand_miss_rate::total 0.860535 # miss rate for demand accesses -system.cpu2.l1c.overall_miss_rate::cpu2 0.860535 # miss rate for overall accesses -system.cpu2.l1c.overall_miss_rate::total 0.860535 # miss rate for overall accesses -system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 18177.398089 # average ReadReq miss latency -system.cpu2.l1c.ReadReq_avg_miss_latency::total 18177.398089 # average ReadReq miss latency -system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 23490.789731 # average WriteReq miss latency -system.cpu2.l1c.WriteReq_avg_miss_latency::total 23490.789731 # average WriteReq miss latency -system.cpu2.l1c.demand_avg_miss_latency::cpu2 20272.359974 # average overall miss latency -system.cpu2.l1c.demand_avg_miss_latency::total 20272.359974 # average overall miss latency -system.cpu2.l1c.overall_avg_miss_latency::cpu2 20272.359974 # average overall miss latency -system.cpu2.l1c.overall_avg_miss_latency::total 20272.359974 # average overall miss latency -system.cpu2.l1c.blocked_cycles::no_mshrs 824101 # number of cycles access was blocked +system.cpu2.l1c.tags.occ_blocks::cpu2 391.892697 # Average occupied blocks per requestor +system.cpu2.l1c.tags.occ_percent::cpu2 0.765415 # Average percentage of cache occupancy +system.cpu2.l1c.tags.occ_percent::total 0.765415 # Average percentage of cache occupancy +system.cpu2.l1c.tags.occ_task_id_blocks::1024 402 # Occupied blocks per task id +system.cpu2.l1c.tags.age_task_id_blocks_1024::0 395 # Occupied blocks per task id +system.cpu2.l1c.tags.age_task_id_blocks_1024::1 7 # Occupied blocks per task id +system.cpu2.l1c.tags.occ_task_id_percent::1024 0.785156 # Percentage of cache occupancy per task id +system.cpu2.l1c.tags.tag_accesses 337818 # Number of tag accesses +system.cpu2.l1c.tags.data_accesses 337818 # Number of data accesses +system.cpu2.l1c.pwrStateResidencyTicks::UNDEFINED 519755500 # Cumulative time (in ticks) in various power states +system.cpu2.l1c.ReadReq_hits::cpu2 8790 # number of ReadReq hits +system.cpu2.l1c.ReadReq_hits::total 8790 # number of ReadReq hits +system.cpu2.l1c.WriteReq_hits::cpu2 1144 # number of WriteReq hits +system.cpu2.l1c.WriteReq_hits::total 1144 # number of WriteReq hits +system.cpu2.l1c.demand_hits::cpu2 9934 # number of demand (read+write) hits +system.cpu2.l1c.demand_hits::total 9934 # number of demand (read+write) hits +system.cpu2.l1c.overall_hits::cpu2 9934 # number of overall hits +system.cpu2.l1c.overall_hits::total 9934 # number of overall hits +system.cpu2.l1c.ReadReq_misses::cpu2 36176 # number of ReadReq misses +system.cpu2.l1c.ReadReq_misses::total 36176 # number of ReadReq misses +system.cpu2.l1c.WriteReq_misses::cpu2 24169 # number of WriteReq misses +system.cpu2.l1c.WriteReq_misses::total 24169 # number of WriteReq misses +system.cpu2.l1c.demand_misses::cpu2 60345 # number of demand (read+write) misses +system.cpu2.l1c.demand_misses::total 60345 # number of demand (read+write) misses +system.cpu2.l1c.overall_misses::cpu2 60345 # number of overall misses +system.cpu2.l1c.overall_misses::total 60345 # number of overall misses +system.cpu2.l1c.ReadReq_miss_latency::cpu2 716181593 # number of ReadReq miss cycles +system.cpu2.l1c.ReadReq_miss_latency::total 716181593 # number of ReadReq miss cycles +system.cpu2.l1c.WriteReq_miss_latency::cpu2 589266088 # number of WriteReq miss cycles +system.cpu2.l1c.WriteReq_miss_latency::total 589266088 # number of WriteReq miss cycles +system.cpu2.l1c.demand_miss_latency::cpu2 1305447681 # number of demand (read+write) miss cycles +system.cpu2.l1c.demand_miss_latency::total 1305447681 # number of demand (read+write) miss cycles +system.cpu2.l1c.overall_miss_latency::cpu2 1305447681 # number of overall miss cycles +system.cpu2.l1c.overall_miss_latency::total 1305447681 # number of overall miss cycles +system.cpu2.l1c.ReadReq_accesses::cpu2 44966 # number of ReadReq accesses(hits+misses) +system.cpu2.l1c.ReadReq_accesses::total 44966 # number of ReadReq accesses(hits+misses) +system.cpu2.l1c.WriteReq_accesses::cpu2 25313 # number of WriteReq accesses(hits+misses) +system.cpu2.l1c.WriteReq_accesses::total 25313 # number of WriteReq accesses(hits+misses) +system.cpu2.l1c.demand_accesses::cpu2 70279 # number of demand (read+write) accesses +system.cpu2.l1c.demand_accesses::total 70279 # number of demand (read+write) accesses +system.cpu2.l1c.overall_accesses::cpu2 70279 # number of overall (read+write) accesses +system.cpu2.l1c.overall_accesses::total 70279 # number of overall (read+write) accesses +system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.804519 # miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_miss_rate::total 0.804519 # miss rate for ReadReq accesses +system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.954806 # miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_miss_rate::total 0.954806 # miss rate for WriteReq accesses +system.cpu2.l1c.demand_miss_rate::cpu2 0.858649 # miss rate for demand accesses +system.cpu2.l1c.demand_miss_rate::total 0.858649 # miss rate for demand accesses +system.cpu2.l1c.overall_miss_rate::cpu2 0.858649 # miss rate for overall accesses +system.cpu2.l1c.overall_miss_rate::total 0.858649 # miss rate for overall accesses +system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 19797.147086 # average ReadReq miss latency +system.cpu2.l1c.ReadReq_avg_miss_latency::total 19797.147086 # average ReadReq miss latency +system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 24381.070297 # average WriteReq miss latency +system.cpu2.l1c.WriteReq_avg_miss_latency::total 24381.070297 # average WriteReq miss latency +system.cpu2.l1c.demand_avg_miss_latency::cpu2 21633.071191 # average overall miss latency +system.cpu2.l1c.demand_avg_miss_latency::total 21633.071191 # average overall miss latency +system.cpu2.l1c.overall_avg_miss_latency::cpu2 21633.071191 # average overall miss latency +system.cpu2.l1c.overall_avg_miss_latency::total 21633.071191 # average overall miss latency +system.cpu2.l1c.blocked_cycles::no_mshrs 879879 # number of cycles access was blocked system.cpu2.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu2.l1c.blocked::no_mshrs 66507 # number of cycles access was blocked +system.cpu2.l1c.blocked::no_mshrs 66865 # number of cycles access was blocked system.cpu2.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu2.l1c.avg_blocked_cycles::no_mshrs 12.391192 # average number of cycles each access was blocked +system.cpu2.l1c.avg_blocked_cycles::no_mshrs 13.159037 # average number of cycles each access was blocked system.cpu2.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu2.l1c.writebacks::writebacks 9742 # number of writebacks -system.cpu2.l1c.writebacks::total 9742 # number of writebacks -system.cpu2.l1c.ReadReq_mshr_misses::cpu2 36743 # number of ReadReq MSHR misses -system.cpu2.l1c.ReadReq_mshr_misses::total 36743 # number of ReadReq MSHR misses -system.cpu2.l1c.WriteReq_mshr_misses::cpu2 23917 # number of WriteReq MSHR misses -system.cpu2.l1c.WriteReq_mshr_misses::total 23917 # number of WriteReq MSHR misses -system.cpu2.l1c.demand_mshr_misses::cpu2 60660 # number of demand (read+write) MSHR misses -system.cpu2.l1c.demand_mshr_misses::total 60660 # number of demand (read+write) MSHR misses -system.cpu2.l1c.overall_mshr_misses::cpu2 60660 # number of overall MSHR misses -system.cpu2.l1c.overall_mshr_misses::total 60660 # number of overall MSHR misses -system.cpu2.l1c.ReadReq_mshr_uncacheable::cpu2 10005 # number of ReadReq MSHR uncacheable -system.cpu2.l1c.ReadReq_mshr_uncacheable::total 10005 # number of ReadReq MSHR uncacheable -system.cpu2.l1c.WriteReq_mshr_uncacheable::cpu2 5482 # number of WriteReq MSHR uncacheable -system.cpu2.l1c.WriteReq_mshr_uncacheable::total 5482 # number of WriteReq MSHR uncacheable -system.cpu2.l1c.overall_mshr_uncacheable_misses::cpu2 15487 # number of overall MSHR uncacheable misses -system.cpu2.l1c.overall_mshr_uncacheable_misses::total 15487 # number of overall MSHR uncacheable misses -system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2 631149138 # number of ReadReq MSHR miss cycles -system.cpu2.l1c.ReadReq_mshr_miss_latency::total 631149138 # number of ReadReq MSHR miss cycles -system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 537912218 # number of WriteReq MSHR miss cycles -system.cpu2.l1c.WriteReq_mshr_miss_latency::total 537912218 # number of WriteReq MSHR miss cycles -system.cpu2.l1c.demand_mshr_miss_latency::cpu2 1169061356 # number of demand (read+write) MSHR miss cycles -system.cpu2.l1c.demand_mshr_miss_latency::total 1169061356 # number of demand (read+write) MSHR miss cycles -system.cpu2.l1c.overall_mshr_miss_latency::cpu2 1169061356 # number of overall MSHR miss cycles -system.cpu2.l1c.overall_mshr_miss_latency::total 1169061356 # number of overall MSHR miss cycles -system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 759988155 # number of ReadReq MSHR uncacheable cycles -system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 759988155 # number of ReadReq MSHR uncacheable cycles -system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 759988155 # number of overall MSHR uncacheable cycles -system.cpu2.l1c.overall_mshr_uncacheable_latency::total 759988155 # number of overall MSHR uncacheable cycles -system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.808551 # mshr miss rate for ReadReq accesses -system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.808551 # mshr miss rate for ReadReq accesses -system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.954847 # mshr miss rate for WriteReq accesses -system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.954847 # mshr miss rate for WriteReq accesses -system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.860535 # mshr miss rate for demand accesses -system.cpu2.l1c.demand_mshr_miss_rate::total 0.860535 # mshr miss rate for demand accesses -system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.860535 # mshr miss rate for overall accesses -system.cpu2.l1c.overall_mshr_miss_rate::total 0.860535 # mshr miss rate for overall accesses -system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 17177.398089 # average ReadReq mshr miss latency -system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 17177.398089 # average ReadReq mshr miss latency -system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 22490.789731 # average WriteReq mshr miss latency -system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 22490.789731 # average WriteReq mshr miss latency -system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 19272.359974 # average overall mshr miss latency -system.cpu2.l1c.demand_avg_mshr_miss_latency::total 19272.359974 # average overall mshr miss latency -system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 19272.359974 # average overall mshr miss latency -system.cpu2.l1c.overall_avg_mshr_miss_latency::total 19272.359974 # average overall mshr miss latency -system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2 75960.835082 # average ReadReq mshr uncacheable latency -system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total 75960.835082 # average ReadReq mshr uncacheable latency -system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 49072.651579 # average overall mshr uncacheable latency -system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total 49072.651579 # average overall mshr uncacheable latency -system.cpu3.pwrStateResidencyTicks::UNDEFINED 501584000 # Cumulative time (in ticks) in various power states -system.cpu3.num_reads 99085 # number of read accesses completed -system.cpu3.num_writes 55606 # number of write accesses completed -system.cpu3.l1c.tags.pwrStateResidencyTicks::UNDEFINED 501584000 # Cumulative time (in ticks) in various power states -system.cpu3.l1c.tags.replacements 22528 # number of replacements -system.cpu3.l1c.tags.tagsinuse 391.624901 # Cycle average of tags in use -system.cpu3.l1c.tags.total_refs 13493 # Total number of references to valid blocks. -system.cpu3.l1c.tags.sampled_refs 22909 # Sample count of references to valid blocks. -system.cpu3.l1c.tags.avg_refs 0.588982 # Average number of references to valid blocks. +system.cpu2.l1c.writebacks::writebacks 9745 # number of writebacks +system.cpu2.l1c.writebacks::total 9745 # number of writebacks +system.cpu2.l1c.ReadReq_mshr_misses::cpu2 36176 # number of ReadReq MSHR misses +system.cpu2.l1c.ReadReq_mshr_misses::total 36176 # number of ReadReq MSHR misses +system.cpu2.l1c.WriteReq_mshr_misses::cpu2 24169 # number of WriteReq MSHR misses +system.cpu2.l1c.WriteReq_mshr_misses::total 24169 # number of WriteReq MSHR misses +system.cpu2.l1c.demand_mshr_misses::cpu2 60345 # number of demand (read+write) MSHR misses +system.cpu2.l1c.demand_mshr_misses::total 60345 # number of demand (read+write) MSHR misses +system.cpu2.l1c.overall_mshr_misses::cpu2 60345 # number of overall MSHR misses +system.cpu2.l1c.overall_mshr_misses::total 60345 # number of overall MSHR misses +system.cpu2.l1c.ReadReq_mshr_uncacheable::cpu2 9851 # number of ReadReq MSHR uncacheable +system.cpu2.l1c.ReadReq_mshr_uncacheable::total 9851 # number of ReadReq MSHR uncacheable +system.cpu2.l1c.WriteReq_mshr_uncacheable::cpu2 5469 # number of WriteReq MSHR uncacheable +system.cpu2.l1c.WriteReq_mshr_uncacheable::total 5469 # number of WriteReq MSHR uncacheable +system.cpu2.l1c.overall_mshr_uncacheable_misses::cpu2 15320 # number of overall MSHR uncacheable misses +system.cpu2.l1c.overall_mshr_uncacheable_misses::total 15320 # number of overall MSHR uncacheable misses +system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2 680005593 # number of ReadReq MSHR miss cycles +system.cpu2.l1c.ReadReq_mshr_miss_latency::total 680005593 # number of ReadReq MSHR miss cycles +system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 565098088 # number of WriteReq MSHR miss cycles +system.cpu2.l1c.WriteReq_mshr_miss_latency::total 565098088 # number of WriteReq MSHR miss cycles +system.cpu2.l1c.demand_mshr_miss_latency::cpu2 1245103681 # number of demand (read+write) MSHR miss cycles +system.cpu2.l1c.demand_mshr_miss_latency::total 1245103681 # number of demand (read+write) MSHR miss cycles +system.cpu2.l1c.overall_mshr_miss_latency::cpu2 1245103681 # number of overall MSHR miss cycles +system.cpu2.l1c.overall_mshr_miss_latency::total 1245103681 # number of overall MSHR miss cycles +system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 769729433 # number of ReadReq MSHR uncacheable cycles +system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 769729433 # number of ReadReq MSHR uncacheable cycles +system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 769729433 # number of overall MSHR uncacheable cycles +system.cpu2.l1c.overall_mshr_uncacheable_latency::total 769729433 # number of overall MSHR uncacheable cycles +system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.804519 # mshr miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.804519 # mshr miss rate for ReadReq accesses +system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.954806 # mshr miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.954806 # mshr miss rate for WriteReq accesses +system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.858649 # mshr miss rate for demand accesses +system.cpu2.l1c.demand_mshr_miss_rate::total 0.858649 # mshr miss rate for demand accesses +system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.858649 # mshr miss rate for overall accesses +system.cpu2.l1c.overall_mshr_miss_rate::total 0.858649 # mshr miss rate for overall accesses +system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 18797.147086 # average ReadReq mshr miss latency +system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 18797.147086 # average ReadReq mshr miss latency +system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 23381.111672 # average WriteReq mshr miss latency +system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 23381.111672 # average WriteReq mshr miss latency +system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 20633.087762 # average overall mshr miss latency +system.cpu2.l1c.demand_avg_mshr_miss_latency::total 20633.087762 # average overall mshr miss latency +system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 20633.087762 # average overall mshr miss latency +system.cpu2.l1c.overall_avg_mshr_miss_latency::total 20633.087762 # average overall mshr miss latency +system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2 78137.187392 # average ReadReq mshr uncacheable latency +system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total 78137.187392 # average ReadReq mshr uncacheable latency +system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 50243.435574 # average overall mshr uncacheable latency +system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total 50243.435574 # average overall mshr uncacheable latency +system.cpu3.pwrStateResidencyTicks::UNDEFINED 519755500 # Cumulative time (in ticks) in various power states +system.cpu3.num_reads 100000 # number of read accesses completed +system.cpu3.num_writes 55136 # number of write accesses completed +system.cpu3.l1c.tags.pwrStateResidencyTicks::UNDEFINED 519755500 # Cumulative time (in ticks) in various power states +system.cpu3.l1c.tags.replacements 22201 # number of replacements +system.cpu3.l1c.tags.tagsinuse 392.334218 # Cycle average of tags in use +system.cpu3.l1c.tags.total_refs 13633 # Total number of references to valid blocks. +system.cpu3.l1c.tags.sampled_refs 22606 # Sample count of references to valid blocks. +system.cpu3.l1c.tags.avg_refs 0.603070 # Average number of references to valid blocks. system.cpu3.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.l1c.tags.occ_blocks::cpu3 391.624901 # Average occupied blocks per requestor -system.cpu3.l1c.tags.occ_percent::cpu3 0.764892 # Average percentage of cache occupancy -system.cpu3.l1c.tags.occ_percent::total 0.764892 # Average percentage of cache occupancy -system.cpu3.l1c.tags.occ_task_id_blocks::1024 381 # Occupied blocks per task id -system.cpu3.l1c.tags.age_task_id_blocks_1024::0 374 # Occupied blocks per task id -system.cpu3.l1c.tags.age_task_id_blocks_1024::1 7 # Occupied blocks per task id -system.cpu3.l1c.tags.occ_task_id_percent::1024 0.744141 # Percentage of cache occupancy per task id -system.cpu3.l1c.tags.tag_accesses 339302 # Number of tag accesses -system.cpu3.l1c.tags.data_accesses 339302 # Number of data accesses -system.cpu3.l1c.pwrStateResidencyTicks::UNDEFINED 501584000 # Cumulative time (in ticks) in various power states -system.cpu3.l1c.ReadReq_hits::cpu3 8770 # number of ReadReq hits -system.cpu3.l1c.ReadReq_hits::total 8770 # number of ReadReq hits -system.cpu3.l1c.WriteReq_hits::cpu3 1134 # number of WriteReq hits -system.cpu3.l1c.WriteReq_hits::total 1134 # number of WriteReq hits -system.cpu3.l1c.demand_hits::cpu3 9904 # number of demand (read+write) hits -system.cpu3.l1c.demand_hits::total 9904 # number of demand (read+write) hits -system.cpu3.l1c.overall_hits::cpu3 9904 # number of overall hits -system.cpu3.l1c.overall_hits::total 9904 # number of overall hits -system.cpu3.l1c.ReadReq_misses::cpu3 36439 # number of ReadReq misses -system.cpu3.l1c.ReadReq_misses::total 36439 # number of ReadReq misses -system.cpu3.l1c.WriteReq_misses::cpu3 24225 # number of WriteReq misses -system.cpu3.l1c.WriteReq_misses::total 24225 # number of WriteReq misses -system.cpu3.l1c.demand_misses::cpu3 60664 # number of demand (read+write) misses -system.cpu3.l1c.demand_misses::total 60664 # number of demand (read+write) misses -system.cpu3.l1c.overall_misses::cpu3 60664 # number of overall misses -system.cpu3.l1c.overall_misses::total 60664 # number of overall misses -system.cpu3.l1c.ReadReq_miss_latency::cpu3 671429109 # number of ReadReq miss cycles -system.cpu3.l1c.ReadReq_miss_latency::total 671429109 # number of ReadReq miss cycles -system.cpu3.l1c.WriteReq_miss_latency::cpu3 572133441 # number of WriteReq miss cycles -system.cpu3.l1c.WriteReq_miss_latency::total 572133441 # number of WriteReq miss cycles -system.cpu3.l1c.demand_miss_latency::cpu3 1243562550 # number of demand (read+write) miss cycles -system.cpu3.l1c.demand_miss_latency::total 1243562550 # number of demand (read+write) miss cycles -system.cpu3.l1c.overall_miss_latency::cpu3 1243562550 # number of overall miss cycles -system.cpu3.l1c.overall_miss_latency::total 1243562550 # number of overall miss cycles -system.cpu3.l1c.ReadReq_accesses::cpu3 45209 # number of ReadReq accesses(hits+misses) -system.cpu3.l1c.ReadReq_accesses::total 45209 # number of ReadReq accesses(hits+misses) -system.cpu3.l1c.WriteReq_accesses::cpu3 25359 # number of WriteReq accesses(hits+misses) -system.cpu3.l1c.WriteReq_accesses::total 25359 # number of WriteReq accesses(hits+misses) -system.cpu3.l1c.demand_accesses::cpu3 70568 # number of demand (read+write) accesses -system.cpu3.l1c.demand_accesses::total 70568 # number of demand (read+write) accesses -system.cpu3.l1c.overall_accesses::cpu3 70568 # number of overall (read+write) accesses -system.cpu3.l1c.overall_accesses::total 70568 # number of overall (read+write) accesses -system.cpu3.l1c.ReadReq_miss_rate::cpu3 0.806012 # miss rate for ReadReq accesses -system.cpu3.l1c.ReadReq_miss_rate::total 0.806012 # miss rate for ReadReq accesses -system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.955282 # miss rate for WriteReq accesses -system.cpu3.l1c.WriteReq_miss_rate::total 0.955282 # miss rate for WriteReq accesses -system.cpu3.l1c.demand_miss_rate::cpu3 0.859653 # miss rate for demand accesses -system.cpu3.l1c.demand_miss_rate::total 0.859653 # miss rate for demand accesses -system.cpu3.l1c.overall_miss_rate::cpu3 0.859653 # miss rate for overall accesses -system.cpu3.l1c.overall_miss_rate::total 0.859653 # miss rate for overall accesses -system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 18426.112380 # average ReadReq miss latency -system.cpu3.l1c.ReadReq_avg_miss_latency::total 18426.112380 # average ReadReq miss latency -system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 23617.479505 # average WriteReq miss latency -system.cpu3.l1c.WriteReq_avg_miss_latency::total 23617.479505 # average WriteReq miss latency -system.cpu3.l1c.demand_avg_miss_latency::cpu3 20499.184854 # average overall miss latency -system.cpu3.l1c.demand_avg_miss_latency::total 20499.184854 # average overall miss latency -system.cpu3.l1c.overall_avg_miss_latency::cpu3 20499.184854 # average overall miss latency -system.cpu3.l1c.overall_avg_miss_latency::total 20499.184854 # average overall miss latency -system.cpu3.l1c.blocked_cycles::no_mshrs 821290 # number of cycles access was blocked +system.cpu3.l1c.tags.occ_blocks::cpu3 392.334218 # Average occupied blocks per requestor +system.cpu3.l1c.tags.occ_percent::cpu3 0.766278 # Average percentage of cache occupancy +system.cpu3.l1c.tags.occ_percent::total 0.766278 # Average percentage of cache occupancy +system.cpu3.l1c.tags.occ_task_id_blocks::1024 405 # Occupied blocks per task id +system.cpu3.l1c.tags.age_task_id_blocks_1024::0 397 # Occupied blocks per task id +system.cpu3.l1c.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id +system.cpu3.l1c.tags.occ_task_id_percent::1024 0.791016 # Percentage of cache occupancy per task id +system.cpu3.l1c.tags.tag_accesses 339332 # Number of tag accesses +system.cpu3.l1c.tags.data_accesses 339332 # Number of data accesses +system.cpu3.l1c.pwrStateResidencyTicks::UNDEFINED 519755500 # Cumulative time (in ticks) in various power states +system.cpu3.l1c.ReadReq_hits::cpu3 8805 # number of ReadReq hits +system.cpu3.l1c.ReadReq_hits::total 8805 # number of ReadReq hits +system.cpu3.l1c.WriteReq_hits::cpu3 1190 # number of WriteReq hits +system.cpu3.l1c.WriteReq_hits::total 1190 # number of WriteReq hits +system.cpu3.l1c.demand_hits::cpu3 9995 # number of demand (read+write) hits +system.cpu3.l1c.demand_hits::total 9995 # number of demand (read+write) hits +system.cpu3.l1c.overall_hits::cpu3 9995 # number of overall hits +system.cpu3.l1c.overall_hits::total 9995 # number of overall hits +system.cpu3.l1c.ReadReq_misses::cpu3 36852 # number of ReadReq misses +system.cpu3.l1c.ReadReq_misses::total 36852 # number of ReadReq misses +system.cpu3.l1c.WriteReq_misses::cpu3 23757 # number of WriteReq misses +system.cpu3.l1c.WriteReq_misses::total 23757 # number of WriteReq misses +system.cpu3.l1c.demand_misses::cpu3 60609 # number of demand (read+write) misses +system.cpu3.l1c.demand_misses::total 60609 # number of demand (read+write) misses +system.cpu3.l1c.overall_misses::cpu3 60609 # number of overall misses +system.cpu3.l1c.overall_misses::total 60609 # number of overall misses +system.cpu3.l1c.ReadReq_miss_latency::cpu3 737200497 # number of ReadReq miss cycles +system.cpu3.l1c.ReadReq_miss_latency::total 737200497 # number of ReadReq miss cycles +system.cpu3.l1c.WriteReq_miss_latency::cpu3 577684792 # number of WriteReq miss cycles +system.cpu3.l1c.WriteReq_miss_latency::total 577684792 # number of WriteReq miss cycles +system.cpu3.l1c.demand_miss_latency::cpu3 1314885289 # number of demand (read+write) miss cycles +system.cpu3.l1c.demand_miss_latency::total 1314885289 # number of demand (read+write) miss cycles +system.cpu3.l1c.overall_miss_latency::cpu3 1314885289 # number of overall miss cycles +system.cpu3.l1c.overall_miss_latency::total 1314885289 # number of overall miss cycles +system.cpu3.l1c.ReadReq_accesses::cpu3 45657 # number of ReadReq accesses(hits+misses) +system.cpu3.l1c.ReadReq_accesses::total 45657 # number of ReadReq accesses(hits+misses) +system.cpu3.l1c.WriteReq_accesses::cpu3 24947 # number of WriteReq accesses(hits+misses) +system.cpu3.l1c.WriteReq_accesses::total 24947 # number of WriteReq accesses(hits+misses) +system.cpu3.l1c.demand_accesses::cpu3 70604 # number of demand (read+write) accesses +system.cpu3.l1c.demand_accesses::total 70604 # number of demand (read+write) accesses +system.cpu3.l1c.overall_accesses::cpu3 70604 # number of overall (read+write) accesses +system.cpu3.l1c.overall_accesses::total 70604 # number of overall (read+write) accesses +system.cpu3.l1c.ReadReq_miss_rate::cpu3 0.807149 # miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_miss_rate::total 0.807149 # miss rate for ReadReq accesses +system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.952299 # miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_miss_rate::total 0.952299 # miss rate for WriteReq accesses +system.cpu3.l1c.demand_miss_rate::cpu3 0.858436 # miss rate for demand accesses +system.cpu3.l1c.demand_miss_rate::total 0.858436 # miss rate for demand accesses +system.cpu3.l1c.overall_miss_rate::cpu3 0.858436 # miss rate for overall accesses +system.cpu3.l1c.overall_miss_rate::total 0.858436 # miss rate for overall accesses +system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 20004.355177 # average ReadReq miss latency +system.cpu3.l1c.ReadReq_avg_miss_latency::total 20004.355177 # average ReadReq miss latency +system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 24316.403250 # average WriteReq miss latency +system.cpu3.l1c.WriteReq_avg_miss_latency::total 24316.403250 # average WriteReq miss latency +system.cpu3.l1c.demand_avg_miss_latency::cpu3 21694.555083 # average overall miss latency +system.cpu3.l1c.demand_avg_miss_latency::total 21694.555083 # average overall miss latency +system.cpu3.l1c.overall_avg_miss_latency::cpu3 21694.555083 # average overall miss latency +system.cpu3.l1c.overall_avg_miss_latency::total 21694.555083 # average overall miss latency +system.cpu3.l1c.blocked_cycles::no_mshrs 880663 # number of cycles access was blocked system.cpu3.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu3.l1c.blocked::no_mshrs 66174 # number of cycles access was blocked +system.cpu3.l1c.blocked::no_mshrs 67164 # number of cycles access was blocked system.cpu3.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu3.l1c.avg_blocked_cycles::no_mshrs 12.411068 # average number of cycles each access was blocked +system.cpu3.l1c.avg_blocked_cycles::no_mshrs 13.112129 # average number of cycles each access was blocked system.cpu3.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu3.l1c.writebacks::writebacks 10017 # number of writebacks -system.cpu3.l1c.writebacks::total 10017 # number of writebacks -system.cpu3.l1c.ReadReq_mshr_misses::cpu3 36439 # number of ReadReq MSHR misses -system.cpu3.l1c.ReadReq_mshr_misses::total 36439 # number of ReadReq MSHR misses -system.cpu3.l1c.WriteReq_mshr_misses::cpu3 24225 # number of WriteReq MSHR misses -system.cpu3.l1c.WriteReq_mshr_misses::total 24225 # number of WriteReq MSHR misses -system.cpu3.l1c.demand_mshr_misses::cpu3 60664 # number of demand (read+write) MSHR misses -system.cpu3.l1c.demand_mshr_misses::total 60664 # number of demand (read+write) MSHR misses -system.cpu3.l1c.overall_mshr_misses::cpu3 60664 # number of overall MSHR misses -system.cpu3.l1c.overall_mshr_misses::total 60664 # number of overall MSHR misses -system.cpu3.l1c.ReadReq_mshr_uncacheable::cpu3 9773 # number of ReadReq MSHR uncacheable -system.cpu3.l1c.ReadReq_mshr_uncacheable::total 9773 # number of ReadReq MSHR uncacheable -system.cpu3.l1c.WriteReq_mshr_uncacheable::cpu3 5538 # number of WriteReq MSHR uncacheable -system.cpu3.l1c.WriteReq_mshr_uncacheable::total 5538 # number of WriteReq MSHR uncacheable -system.cpu3.l1c.overall_mshr_uncacheable_misses::cpu3 15311 # number of overall MSHR uncacheable misses -system.cpu3.l1c.overall_mshr_uncacheable_misses::total 15311 # number of overall MSHR uncacheable misses -system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3 634992109 # number of ReadReq MSHR miss cycles -system.cpu3.l1c.ReadReq_mshr_miss_latency::total 634992109 # number of ReadReq MSHR miss cycles -system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 547908441 # number of WriteReq MSHR miss cycles -system.cpu3.l1c.WriteReq_mshr_miss_latency::total 547908441 # number of WriteReq MSHR miss cycles -system.cpu3.l1c.demand_mshr_miss_latency::cpu3 1182900550 # number of demand (read+write) MSHR miss cycles -system.cpu3.l1c.demand_mshr_miss_latency::total 1182900550 # number of demand (read+write) MSHR miss cycles -system.cpu3.l1c.overall_mshr_miss_latency::cpu3 1182900550 # number of overall MSHR miss cycles -system.cpu3.l1c.overall_mshr_miss_latency::total 1182900550 # number of overall MSHR miss cycles -system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 743773245 # number of ReadReq MSHR uncacheable cycles -system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 743773245 # number of ReadReq MSHR uncacheable cycles -system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 743773245 # number of overall MSHR uncacheable cycles -system.cpu3.l1c.overall_mshr_uncacheable_latency::total 743773245 # number of overall MSHR uncacheable cycles -system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.806012 # mshr miss rate for ReadReq accesses -system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.806012 # mshr miss rate for ReadReq accesses -system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.955282 # mshr miss rate for WriteReq accesses -system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.955282 # mshr miss rate for WriteReq accesses -system.cpu3.l1c.demand_mshr_miss_rate::cpu3 0.859653 # mshr miss rate for demand accesses -system.cpu3.l1c.demand_mshr_miss_rate::total 0.859653 # mshr miss rate for demand accesses -system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.859653 # mshr miss rate for overall accesses -system.cpu3.l1c.overall_mshr_miss_rate::total 0.859653 # mshr miss rate for overall accesses -system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 17426.167266 # average ReadReq mshr miss latency -system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 17426.167266 # average ReadReq mshr miss latency -system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 22617.479505 # average WriteReq mshr miss latency -system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 22617.479505 # average WriteReq mshr miss latency -system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 19499.217823 # average overall mshr miss latency -system.cpu3.l1c.demand_avg_mshr_miss_latency::total 19499.217823 # average overall mshr miss latency -system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 19499.217823 # average overall mshr miss latency -system.cpu3.l1c.overall_avg_mshr_miss_latency::total 19499.217823 # average overall mshr miss latency -system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3 76104.905863 # average ReadReq mshr uncacheable latency -system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total 76104.905863 # average ReadReq mshr uncacheable latency -system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 48577.705245 # average overall mshr uncacheable latency -system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total 48577.705245 # average overall mshr uncacheable latency -system.cpu4.pwrStateResidencyTicks::UNDEFINED 501584000 # Cumulative time (in ticks) in various power states -system.cpu4.num_reads 99978 # number of read accesses completed -system.cpu4.num_writes 55474 # number of write accesses completed -system.cpu4.l1c.tags.pwrStateResidencyTicks::UNDEFINED 501584000 # Cumulative time (in ticks) in various power states -system.cpu4.l1c.tags.replacements 22223 # number of replacements -system.cpu4.l1c.tags.tagsinuse 391.899958 # Cycle average of tags in use -system.cpu4.l1c.tags.total_refs 13858 # Total number of references to valid blocks. -system.cpu4.l1c.tags.sampled_refs 22628 # Sample count of references to valid blocks. -system.cpu4.l1c.tags.avg_refs 0.612427 # Average number of references to valid blocks. +system.cpu3.l1c.writebacks::writebacks 9556 # number of writebacks +system.cpu3.l1c.writebacks::total 9556 # number of writebacks +system.cpu3.l1c.ReadReq_mshr_misses::cpu3 36852 # number of ReadReq MSHR misses +system.cpu3.l1c.ReadReq_mshr_misses::total 36852 # number of ReadReq MSHR misses +system.cpu3.l1c.WriteReq_mshr_misses::cpu3 23757 # number of WriteReq MSHR misses +system.cpu3.l1c.WriteReq_mshr_misses::total 23757 # number of WriteReq MSHR misses +system.cpu3.l1c.demand_mshr_misses::cpu3 60609 # number of demand (read+write) MSHR misses +system.cpu3.l1c.demand_mshr_misses::total 60609 # number of demand (read+write) MSHR misses +system.cpu3.l1c.overall_mshr_misses::cpu3 60609 # number of overall MSHR misses +system.cpu3.l1c.overall_mshr_misses::total 60609 # number of overall MSHR misses +system.cpu3.l1c.ReadReq_mshr_uncacheable::cpu3 9752 # number of ReadReq MSHR uncacheable +system.cpu3.l1c.ReadReq_mshr_uncacheable::total 9752 # number of ReadReq MSHR uncacheable +system.cpu3.l1c.WriteReq_mshr_uncacheable::cpu3 5506 # number of WriteReq MSHR uncacheable +system.cpu3.l1c.WriteReq_mshr_uncacheable::total 5506 # number of WriteReq MSHR uncacheable +system.cpu3.l1c.overall_mshr_uncacheable_misses::cpu3 15258 # number of overall MSHR uncacheable misses +system.cpu3.l1c.overall_mshr_uncacheable_misses::total 15258 # number of overall MSHR uncacheable misses +system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3 700349497 # number of ReadReq MSHR miss cycles +system.cpu3.l1c.ReadReq_mshr_miss_latency::total 700349497 # number of ReadReq MSHR miss cycles +system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 553928792 # number of WriteReq MSHR miss cycles +system.cpu3.l1c.WriteReq_mshr_miss_latency::total 553928792 # number of WriteReq MSHR miss cycles +system.cpu3.l1c.demand_mshr_miss_latency::cpu3 1254278289 # number of demand (read+write) MSHR miss cycles +system.cpu3.l1c.demand_mshr_miss_latency::total 1254278289 # number of demand (read+write) MSHR miss cycles +system.cpu3.l1c.overall_mshr_miss_latency::cpu3 1254278289 # number of overall MSHR miss cycles +system.cpu3.l1c.overall_mshr_miss_latency::total 1254278289 # number of overall MSHR miss cycles +system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 761853080 # number of ReadReq MSHR uncacheable cycles +system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 761853080 # number of ReadReq MSHR uncacheable cycles +system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 761853080 # number of overall MSHR uncacheable cycles +system.cpu3.l1c.overall_mshr_uncacheable_latency::total 761853080 # number of overall MSHR uncacheable cycles +system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.807149 # mshr miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.807149 # mshr miss rate for ReadReq accesses +system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.952299 # mshr miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.952299 # mshr miss rate for WriteReq accesses +system.cpu3.l1c.demand_mshr_miss_rate::cpu3 0.858436 # mshr miss rate for demand accesses +system.cpu3.l1c.demand_mshr_miss_rate::total 0.858436 # mshr miss rate for demand accesses +system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.858436 # mshr miss rate for overall accesses +system.cpu3.l1c.overall_mshr_miss_rate::total 0.858436 # mshr miss rate for overall accesses +system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 19004.382313 # average ReadReq mshr miss latency +system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 19004.382313 # average ReadReq mshr miss latency +system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 23316.445342 # average WriteReq mshr miss latency +system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 23316.445342 # average WriteReq mshr miss latency +system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 20694.588081 # average overall mshr miss latency +system.cpu3.l1c.demand_avg_mshr_miss_latency::total 20694.588081 # average overall mshr miss latency +system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 20694.588081 # average overall mshr miss latency +system.cpu3.l1c.overall_avg_mshr_miss_latency::total 20694.588081 # average overall mshr miss latency +system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3 78122.752256 # average ReadReq mshr uncacheable latency +system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total 78122.752256 # average ReadReq mshr uncacheable latency +system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 49931.385503 # average overall mshr uncacheable latency +system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total 49931.385503 # average overall mshr uncacheable latency +system.cpu4.pwrStateResidencyTicks::UNDEFINED 519755500 # Cumulative time (in ticks) in various power states +system.cpu4.num_reads 99808 # number of read accesses completed +system.cpu4.num_writes 55157 # number of write accesses completed +system.cpu4.l1c.tags.pwrStateResidencyTicks::UNDEFINED 519755500 # Cumulative time (in ticks) in various power states +system.cpu4.l1c.tags.replacements 22030 # number of replacements +system.cpu4.l1c.tags.tagsinuse 392.026241 # Cycle average of tags in use +system.cpu4.l1c.tags.total_refs 13726 # Total number of references to valid blocks. +system.cpu4.l1c.tags.sampled_refs 22418 # Sample count of references to valid blocks. +system.cpu4.l1c.tags.avg_refs 0.612276 # Average number of references to valid blocks. system.cpu4.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu4.l1c.tags.occ_blocks::cpu4 391.899958 # Average occupied blocks per requestor -system.cpu4.l1c.tags.occ_percent::cpu4 0.765430 # Average percentage of cache occupancy -system.cpu4.l1c.tags.occ_percent::total 0.765430 # Average percentage of cache occupancy -system.cpu4.l1c.tags.occ_task_id_blocks::1024 405 # Occupied blocks per task id -system.cpu4.l1c.tags.age_task_id_blocks_1024::0 396 # Occupied blocks per task id -system.cpu4.l1c.tags.age_task_id_blocks_1024::1 9 # Occupied blocks per task id -system.cpu4.l1c.tags.occ_task_id_percent::1024 0.791016 # Percentage of cache occupancy per task id -system.cpu4.l1c.tags.tag_accesses 340964 # Number of tag accesses -system.cpu4.l1c.tags.data_accesses 340964 # Number of data accesses -system.cpu4.l1c.pwrStateResidencyTicks::UNDEFINED 501584000 # Cumulative time (in ticks) in various power states -system.cpu4.l1c.ReadReq_hits::cpu4 8890 # number of ReadReq hits -system.cpu4.l1c.ReadReq_hits::total 8890 # number of ReadReq hits -system.cpu4.l1c.WriteReq_hits::cpu4 1171 # number of WriteReq hits -system.cpu4.l1c.WriteReq_hits::total 1171 # number of WriteReq hits -system.cpu4.l1c.demand_hits::cpu4 10061 # number of demand (read+write) hits -system.cpu4.l1c.demand_hits::total 10061 # number of demand (read+write) hits -system.cpu4.l1c.overall_hits::cpu4 10061 # number of overall hits -system.cpu4.l1c.overall_hits::total 10061 # number of overall hits -system.cpu4.l1c.ReadReq_misses::cpu4 36725 # number of ReadReq misses -system.cpu4.l1c.ReadReq_misses::total 36725 # number of ReadReq misses -system.cpu4.l1c.WriteReq_misses::cpu4 24186 # number of WriteReq misses -system.cpu4.l1c.WriteReq_misses::total 24186 # number of WriteReq misses -system.cpu4.l1c.demand_misses::cpu4 60911 # number of demand (read+write) misses -system.cpu4.l1c.demand_misses::total 60911 # number of demand (read+write) misses -system.cpu4.l1c.overall_misses::cpu4 60911 # number of overall misses -system.cpu4.l1c.overall_misses::total 60911 # number of overall misses -system.cpu4.l1c.ReadReq_miss_latency::cpu4 668441602 # number of ReadReq miss cycles -system.cpu4.l1c.ReadReq_miss_latency::total 668441602 # number of ReadReq miss cycles -system.cpu4.l1c.WriteReq_miss_latency::cpu4 573535032 # number of WriteReq miss cycles -system.cpu4.l1c.WriteReq_miss_latency::total 573535032 # number of WriteReq miss cycles -system.cpu4.l1c.demand_miss_latency::cpu4 1241976634 # number of demand (read+write) miss cycles -system.cpu4.l1c.demand_miss_latency::total 1241976634 # number of demand (read+write) miss cycles -system.cpu4.l1c.overall_miss_latency::cpu4 1241976634 # number of overall miss cycles -system.cpu4.l1c.overall_miss_latency::total 1241976634 # number of overall miss cycles -system.cpu4.l1c.ReadReq_accesses::cpu4 45615 # number of ReadReq accesses(hits+misses) -system.cpu4.l1c.ReadReq_accesses::total 45615 # number of ReadReq accesses(hits+misses) -system.cpu4.l1c.WriteReq_accesses::cpu4 25357 # number of WriteReq accesses(hits+misses) -system.cpu4.l1c.WriteReq_accesses::total 25357 # number of WriteReq accesses(hits+misses) -system.cpu4.l1c.demand_accesses::cpu4 70972 # number of demand (read+write) accesses -system.cpu4.l1c.demand_accesses::total 70972 # number of demand (read+write) accesses -system.cpu4.l1c.overall_accesses::cpu4 70972 # number of overall (read+write) accesses -system.cpu4.l1c.overall_accesses::total 70972 # number of overall (read+write) accesses -system.cpu4.l1c.ReadReq_miss_rate::cpu4 0.805108 # miss rate for ReadReq accesses -system.cpu4.l1c.ReadReq_miss_rate::total 0.805108 # miss rate for ReadReq accesses -system.cpu4.l1c.WriteReq_miss_rate::cpu4 0.953819 # miss rate for WriteReq accesses -system.cpu4.l1c.WriteReq_miss_rate::total 0.953819 # miss rate for WriteReq accesses -system.cpu4.l1c.demand_miss_rate::cpu4 0.858240 # miss rate for demand accesses -system.cpu4.l1c.demand_miss_rate::total 0.858240 # miss rate for demand accesses -system.cpu4.l1c.overall_miss_rate::cpu4 0.858240 # miss rate for overall accesses -system.cpu4.l1c.overall_miss_rate::total 0.858240 # miss rate for overall accesses -system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 18201.268945 # average ReadReq miss latency -system.cpu4.l1c.ReadReq_avg_miss_latency::total 18201.268945 # average ReadReq miss latency -system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 23713.513272 # average WriteReq miss latency -system.cpu4.l1c.WriteReq_avg_miss_latency::total 23713.513272 # average WriteReq miss latency -system.cpu4.l1c.demand_avg_miss_latency::cpu4 20390.022065 # average overall miss latency -system.cpu4.l1c.demand_avg_miss_latency::total 20390.022065 # average overall miss latency -system.cpu4.l1c.overall_avg_miss_latency::cpu4 20390.022065 # average overall miss latency -system.cpu4.l1c.overall_avg_miss_latency::total 20390.022065 # average overall miss latency -system.cpu4.l1c.blocked_cycles::no_mshrs 823668 # number of cycles access was blocked +system.cpu4.l1c.tags.occ_blocks::cpu4 392.026241 # Average occupied blocks per requestor +system.cpu4.l1c.tags.occ_percent::cpu4 0.765676 # Average percentage of cache occupancy +system.cpu4.l1c.tags.occ_percent::total 0.765676 # Average percentage of cache occupancy +system.cpu4.l1c.tags.occ_task_id_blocks::1024 388 # Occupied blocks per task id +system.cpu4.l1c.tags.age_task_id_blocks_1024::0 372 # Occupied blocks per task id +system.cpu4.l1c.tags.age_task_id_blocks_1024::1 16 # Occupied blocks per task id +system.cpu4.l1c.tags.occ_task_id_percent::1024 0.757812 # Percentage of cache occupancy per task id +system.cpu4.l1c.tags.tag_accesses 338084 # Number of tag accesses +system.cpu4.l1c.tags.data_accesses 338084 # Number of data accesses +system.cpu4.l1c.pwrStateResidencyTicks::UNDEFINED 519755500 # Cumulative time (in ticks) in various power states +system.cpu4.l1c.ReadReq_hits::cpu4 8869 # number of ReadReq hits +system.cpu4.l1c.ReadReq_hits::total 8869 # number of ReadReq hits +system.cpu4.l1c.WriteReq_hits::cpu4 1181 # number of WriteReq hits +system.cpu4.l1c.WriteReq_hits::total 1181 # number of WriteReq hits +system.cpu4.l1c.demand_hits::cpu4 10050 # number of demand (read+write) hits +system.cpu4.l1c.demand_hits::total 10050 # number of demand (read+write) hits +system.cpu4.l1c.overall_hits::cpu4 10050 # number of overall hits +system.cpu4.l1c.overall_hits::total 10050 # number of overall hits +system.cpu4.l1c.ReadReq_misses::cpu4 36458 # number of ReadReq misses +system.cpu4.l1c.ReadReq_misses::total 36458 # number of ReadReq misses +system.cpu4.l1c.WriteReq_misses::cpu4 23868 # number of WriteReq misses +system.cpu4.l1c.WriteReq_misses::total 23868 # number of WriteReq misses +system.cpu4.l1c.demand_misses::cpu4 60326 # number of demand (read+write) misses +system.cpu4.l1c.demand_misses::total 60326 # number of demand (read+write) misses +system.cpu4.l1c.overall_misses::cpu4 60326 # number of overall misses +system.cpu4.l1c.overall_misses::total 60326 # number of overall misses +system.cpu4.l1c.ReadReq_miss_latency::cpu4 723342269 # number of ReadReq miss cycles +system.cpu4.l1c.ReadReq_miss_latency::total 723342269 # number of ReadReq miss cycles +system.cpu4.l1c.WriteReq_miss_latency::cpu4 578669341 # number of WriteReq miss cycles +system.cpu4.l1c.WriteReq_miss_latency::total 578669341 # number of WriteReq miss cycles +system.cpu4.l1c.demand_miss_latency::cpu4 1302011610 # number of demand (read+write) miss cycles +system.cpu4.l1c.demand_miss_latency::total 1302011610 # number of demand (read+write) miss cycles +system.cpu4.l1c.overall_miss_latency::cpu4 1302011610 # number of overall miss cycles +system.cpu4.l1c.overall_miss_latency::total 1302011610 # number of overall miss cycles +system.cpu4.l1c.ReadReq_accesses::cpu4 45327 # number of ReadReq accesses(hits+misses) +system.cpu4.l1c.ReadReq_accesses::total 45327 # number of ReadReq accesses(hits+misses) +system.cpu4.l1c.WriteReq_accesses::cpu4 25049 # number of WriteReq accesses(hits+misses) +system.cpu4.l1c.WriteReq_accesses::total 25049 # number of WriteReq accesses(hits+misses) +system.cpu4.l1c.demand_accesses::cpu4 70376 # number of demand (read+write) accesses +system.cpu4.l1c.demand_accesses::total 70376 # number of demand (read+write) accesses +system.cpu4.l1c.overall_accesses::cpu4 70376 # number of overall (read+write) accesses +system.cpu4.l1c.overall_accesses::total 70376 # number of overall (read+write) accesses +system.cpu4.l1c.ReadReq_miss_rate::cpu4 0.804333 # miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_miss_rate::total 0.804333 # miss rate for ReadReq accesses +system.cpu4.l1c.WriteReq_miss_rate::cpu4 0.952852 # miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_miss_rate::total 0.952852 # miss rate for WriteReq accesses +system.cpu4.l1c.demand_miss_rate::cpu4 0.857196 # miss rate for demand accesses +system.cpu4.l1c.demand_miss_rate::total 0.857196 # miss rate for demand accesses +system.cpu4.l1c.overall_miss_rate::cpu4 0.857196 # miss rate for overall accesses +system.cpu4.l1c.overall_miss_rate::total 0.857196 # miss rate for overall accesses +system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 19840.426491 # average ReadReq miss latency +system.cpu4.l1c.ReadReq_avg_miss_latency::total 19840.426491 # average ReadReq miss latency +system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 24244.567664 # average WriteReq miss latency +system.cpu4.l1c.WriteReq_avg_miss_latency::total 24244.567664 # average WriteReq miss latency +system.cpu4.l1c.demand_avg_miss_latency::cpu4 21582.926267 # average overall miss latency +system.cpu4.l1c.demand_avg_miss_latency::total 21582.926267 # average overall miss latency +system.cpu4.l1c.overall_avg_miss_latency::cpu4 21582.926267 # average overall miss latency +system.cpu4.l1c.overall_avg_miss_latency::total 21582.926267 # average overall miss latency +system.cpu4.l1c.blocked_cycles::no_mshrs 883463 # number of cycles access was blocked system.cpu4.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu4.l1c.blocked::no_mshrs 66629 # number of cycles access was blocked +system.cpu4.l1c.blocked::no_mshrs 67109 # number of cycles access was blocked system.cpu4.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu4.l1c.avg_blocked_cycles::no_mshrs 12.362005 # average number of cycles each access was blocked +system.cpu4.l1c.avg_blocked_cycles::no_mshrs 13.164598 # average number of cycles each access was blocked system.cpu4.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu4.l1c.writebacks::writebacks 9699 # number of writebacks -system.cpu4.l1c.writebacks::total 9699 # number of writebacks -system.cpu4.l1c.ReadReq_mshr_misses::cpu4 36725 # number of ReadReq MSHR misses -system.cpu4.l1c.ReadReq_mshr_misses::total 36725 # number of ReadReq MSHR misses -system.cpu4.l1c.WriteReq_mshr_misses::cpu4 24186 # number of WriteReq MSHR misses -system.cpu4.l1c.WriteReq_mshr_misses::total 24186 # number of WriteReq MSHR misses -system.cpu4.l1c.demand_mshr_misses::cpu4 60911 # number of demand (read+write) MSHR misses -system.cpu4.l1c.demand_mshr_misses::total 60911 # number of demand (read+write) MSHR misses -system.cpu4.l1c.overall_mshr_misses::cpu4 60911 # number of overall MSHR misses -system.cpu4.l1c.overall_mshr_misses::total 60911 # number of overall MSHR misses -system.cpu4.l1c.ReadReq_mshr_uncacheable::cpu4 9801 # number of ReadReq MSHR uncacheable -system.cpu4.l1c.ReadReq_mshr_uncacheable::total 9801 # number of ReadReq MSHR uncacheable -system.cpu4.l1c.WriteReq_mshr_uncacheable::cpu4 5498 # number of WriteReq MSHR uncacheable -system.cpu4.l1c.WriteReq_mshr_uncacheable::total 5498 # number of WriteReq MSHR uncacheable -system.cpu4.l1c.overall_mshr_uncacheable_misses::cpu4 15299 # number of overall MSHR uncacheable misses -system.cpu4.l1c.overall_mshr_uncacheable_misses::total 15299 # number of overall MSHR uncacheable misses -system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4 631717602 # number of ReadReq MSHR miss cycles -system.cpu4.l1c.ReadReq_mshr_miss_latency::total 631717602 # number of ReadReq MSHR miss cycles -system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4 549351032 # number of WriteReq MSHR miss cycles -system.cpu4.l1c.WriteReq_mshr_miss_latency::total 549351032 # number of WriteReq MSHR miss cycles -system.cpu4.l1c.demand_mshr_miss_latency::cpu4 1181068634 # number of demand (read+write) MSHR miss cycles -system.cpu4.l1c.demand_mshr_miss_latency::total 1181068634 # number of demand (read+write) MSHR miss cycles -system.cpu4.l1c.overall_mshr_miss_latency::cpu4 1181068634 # number of overall MSHR miss cycles -system.cpu4.l1c.overall_mshr_miss_latency::total 1181068634 # number of overall MSHR miss cycles -system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4 748050214 # number of ReadReq MSHR uncacheable cycles -system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 748050214 # number of ReadReq MSHR uncacheable cycles -system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4 748050214 # number of overall MSHR uncacheable cycles -system.cpu4.l1c.overall_mshr_uncacheable_latency::total 748050214 # number of overall MSHR uncacheable cycles -system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4 0.805108 # mshr miss rate for ReadReq accesses -system.cpu4.l1c.ReadReq_mshr_miss_rate::total 0.805108 # mshr miss rate for ReadReq accesses -system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4 0.953819 # mshr miss rate for WriteReq accesses -system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.953819 # mshr miss rate for WriteReq accesses -system.cpu4.l1c.demand_mshr_miss_rate::cpu4 0.858240 # mshr miss rate for demand accesses -system.cpu4.l1c.demand_mshr_miss_rate::total 0.858240 # mshr miss rate for demand accesses -system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.858240 # mshr miss rate for overall accesses -system.cpu4.l1c.overall_mshr_miss_rate::total 0.858240 # mshr miss rate for overall accesses -system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 17201.296174 # average ReadReq mshr miss latency -system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 17201.296174 # average ReadReq mshr miss latency -system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 22713.595965 # average WriteReq mshr miss latency -system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 22713.595965 # average WriteReq mshr miss latency -system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 19390.071317 # average overall mshr miss latency -system.cpu4.l1c.demand_avg_mshr_miss_latency::total 19390.071317 # average overall mshr miss latency -system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 19390.071317 # average overall mshr miss latency -system.cpu4.l1c.overall_avg_mshr_miss_latency::total 19390.071317 # average overall mshr miss latency -system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4 76323.866340 # average ReadReq mshr uncacheable latency -system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total 76323.866340 # average ReadReq mshr uncacheable latency -system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 48895.366625 # average overall mshr uncacheable latency -system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total 48895.366625 # average overall mshr uncacheable latency -system.cpu5.pwrStateResidencyTicks::UNDEFINED 501584000 # Cumulative time (in ticks) in various power states -system.cpu5.num_reads 100000 # number of read accesses completed -system.cpu5.num_writes 55110 # number of write accesses completed -system.cpu5.l1c.tags.pwrStateResidencyTicks::UNDEFINED 501584000 # Cumulative time (in ticks) in various power states -system.cpu5.l1c.tags.replacements 22358 # number of replacements -system.cpu5.l1c.tags.tagsinuse 391.816568 # Cycle average of tags in use -system.cpu5.l1c.tags.total_refs 13630 # Total number of references to valid blocks. -system.cpu5.l1c.tags.sampled_refs 22751 # Sample count of references to valid blocks. -system.cpu5.l1c.tags.avg_refs 0.599095 # Average number of references to valid blocks. +system.cpu4.l1c.writebacks::writebacks 9613 # number of writebacks +system.cpu4.l1c.writebacks::total 9613 # number of writebacks +system.cpu4.l1c.ReadReq_mshr_misses::cpu4 36458 # number of ReadReq MSHR misses +system.cpu4.l1c.ReadReq_mshr_misses::total 36458 # number of ReadReq MSHR misses +system.cpu4.l1c.WriteReq_mshr_misses::cpu4 23868 # number of WriteReq MSHR misses +system.cpu4.l1c.WriteReq_mshr_misses::total 23868 # number of WriteReq MSHR misses +system.cpu4.l1c.demand_mshr_misses::cpu4 60326 # number of demand (read+write) MSHR misses +system.cpu4.l1c.demand_mshr_misses::total 60326 # number of demand (read+write) MSHR misses +system.cpu4.l1c.overall_mshr_misses::cpu4 60326 # number of overall MSHR misses +system.cpu4.l1c.overall_mshr_misses::total 60326 # number of overall MSHR misses +system.cpu4.l1c.ReadReq_mshr_uncacheable::cpu4 9934 # number of ReadReq MSHR uncacheable +system.cpu4.l1c.ReadReq_mshr_uncacheable::total 9934 # number of ReadReq MSHR uncacheable +system.cpu4.l1c.WriteReq_mshr_uncacheable::cpu4 5430 # number of WriteReq MSHR uncacheable +system.cpu4.l1c.WriteReq_mshr_uncacheable::total 5430 # number of WriteReq MSHR uncacheable +system.cpu4.l1c.overall_mshr_uncacheable_misses::cpu4 15364 # number of overall MSHR uncacheable misses +system.cpu4.l1c.overall_mshr_uncacheable_misses::total 15364 # number of overall MSHR uncacheable misses +system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4 686885269 # number of ReadReq MSHR miss cycles +system.cpu4.l1c.ReadReq_mshr_miss_latency::total 686885269 # number of ReadReq MSHR miss cycles +system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4 554802341 # number of WriteReq MSHR miss cycles +system.cpu4.l1c.WriteReq_mshr_miss_latency::total 554802341 # number of WriteReq MSHR miss cycles +system.cpu4.l1c.demand_mshr_miss_latency::cpu4 1241687610 # number of demand (read+write) MSHR miss cycles +system.cpu4.l1c.demand_mshr_miss_latency::total 1241687610 # number of demand (read+write) MSHR miss cycles +system.cpu4.l1c.overall_mshr_miss_latency::cpu4 1241687610 # number of overall MSHR miss cycles +system.cpu4.l1c.overall_mshr_miss_latency::total 1241687610 # number of overall MSHR miss cycles +system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4 775754665 # number of ReadReq MSHR uncacheable cycles +system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 775754665 # number of ReadReq MSHR uncacheable cycles +system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4 775754665 # number of overall MSHR uncacheable cycles +system.cpu4.l1c.overall_mshr_uncacheable_latency::total 775754665 # number of overall MSHR uncacheable cycles +system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4 0.804333 # mshr miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_mshr_miss_rate::total 0.804333 # mshr miss rate for ReadReq accesses +system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4 0.952852 # mshr miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.952852 # mshr miss rate for WriteReq accesses +system.cpu4.l1c.demand_mshr_miss_rate::cpu4 0.857196 # mshr miss rate for demand accesses +system.cpu4.l1c.demand_mshr_miss_rate::total 0.857196 # mshr miss rate for demand accesses +system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.857196 # mshr miss rate for overall accesses +system.cpu4.l1c.overall_mshr_miss_rate::total 0.857196 # mshr miss rate for overall accesses +system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 18840.453920 # average ReadReq mshr miss latency +system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 18840.453920 # average ReadReq mshr miss latency +system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 23244.609561 # average WriteReq mshr miss latency +system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 23244.609561 # average WriteReq mshr miss latency +system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 20582.959420 # average overall mshr miss latency +system.cpu4.l1c.demand_avg_mshr_miss_latency::total 20582.959420 # average overall mshr miss latency +system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 20582.959420 # average overall mshr miss latency +system.cpu4.l1c.overall_avg_mshr_miss_latency::total 20582.959420 # average overall mshr miss latency +system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4 78090.866217 # average ReadReq mshr uncacheable latency +system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total 78090.866217 # average ReadReq mshr uncacheable latency +system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 50491.712119 # average overall mshr uncacheable latency +system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total 50491.712119 # average overall mshr uncacheable latency +system.cpu5.pwrStateResidencyTicks::UNDEFINED 519755500 # Cumulative time (in ticks) in various power states +system.cpu5.num_reads 99404 # number of read accesses completed +system.cpu5.num_writes 55162 # number of write accesses completed +system.cpu5.l1c.tags.pwrStateResidencyTicks::UNDEFINED 519755500 # Cumulative time (in ticks) in various power states +system.cpu5.l1c.tags.replacements 22439 # number of replacements +system.cpu5.l1c.tags.tagsinuse 391.788419 # Cycle average of tags in use +system.cpu5.l1c.tags.total_refs 13514 # Total number of references to valid blocks. +system.cpu5.l1c.tags.sampled_refs 22846 # Sample count of references to valid blocks. +system.cpu5.l1c.tags.avg_refs 0.591526 # Average number of references to valid blocks. system.cpu5.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu5.l1c.tags.occ_blocks::cpu5 391.816568 # Average occupied blocks per requestor -system.cpu5.l1c.tags.occ_percent::cpu5 0.765267 # Average percentage of cache occupancy -system.cpu5.l1c.tags.occ_percent::total 0.765267 # Average percentage of cache occupancy -system.cpu5.l1c.tags.occ_task_id_blocks::1024 393 # Occupied blocks per task id -system.cpu5.l1c.tags.age_task_id_blocks_1024::0 388 # Occupied blocks per task id -system.cpu5.l1c.tags.age_task_id_blocks_1024::1 5 # Occupied blocks per task id -system.cpu5.l1c.tags.occ_task_id_percent::1024 0.767578 # Percentage of cache occupancy per task id -system.cpu5.l1c.tags.tag_accesses 340100 # Number of tag accesses -system.cpu5.l1c.tags.data_accesses 340100 # Number of data accesses -system.cpu5.l1c.pwrStateResidencyTicks::UNDEFINED 501584000 # Cumulative time (in ticks) in various power states -system.cpu5.l1c.ReadReq_hits::cpu5 8821 # number of ReadReq hits -system.cpu5.l1c.ReadReq_hits::total 8821 # number of ReadReq hits -system.cpu5.l1c.WriteReq_hits::cpu5 1107 # number of WriteReq hits -system.cpu5.l1c.WriteReq_hits::total 1107 # number of WriteReq hits -system.cpu5.l1c.demand_hits::cpu5 9928 # number of demand (read+write) hits -system.cpu5.l1c.demand_hits::total 9928 # number of demand (read+write) hits -system.cpu5.l1c.overall_hits::cpu5 9928 # number of overall hits -system.cpu5.l1c.overall_hits::total 9928 # number of overall hits -system.cpu5.l1c.ReadReq_misses::cpu5 36801 # number of ReadReq misses -system.cpu5.l1c.ReadReq_misses::total 36801 # number of ReadReq misses -system.cpu5.l1c.WriteReq_misses::cpu5 24029 # number of WriteReq misses -system.cpu5.l1c.WriteReq_misses::total 24029 # number of WriteReq misses -system.cpu5.l1c.demand_misses::cpu5 60830 # number of demand (read+write) misses -system.cpu5.l1c.demand_misses::total 60830 # number of demand (read+write) misses -system.cpu5.l1c.overall_misses::cpu5 60830 # number of overall misses -system.cpu5.l1c.overall_misses::total 60830 # number of overall misses -system.cpu5.l1c.ReadReq_miss_latency::cpu5 677475643 # number of ReadReq miss cycles -system.cpu5.l1c.ReadReq_miss_latency::total 677475643 # number of ReadReq miss cycles -system.cpu5.l1c.WriteReq_miss_latency::cpu5 566244558 # number of WriteReq miss cycles -system.cpu5.l1c.WriteReq_miss_latency::total 566244558 # number of WriteReq miss cycles -system.cpu5.l1c.demand_miss_latency::cpu5 1243720201 # number of demand (read+write) miss cycles -system.cpu5.l1c.demand_miss_latency::total 1243720201 # number of demand (read+write) miss cycles -system.cpu5.l1c.overall_miss_latency::cpu5 1243720201 # number of overall miss cycles -system.cpu5.l1c.overall_miss_latency::total 1243720201 # number of overall miss cycles -system.cpu5.l1c.ReadReq_accesses::cpu5 45622 # number of ReadReq accesses(hits+misses) -system.cpu5.l1c.ReadReq_accesses::total 45622 # number of ReadReq accesses(hits+misses) -system.cpu5.l1c.WriteReq_accesses::cpu5 25136 # number of WriteReq accesses(hits+misses) -system.cpu5.l1c.WriteReq_accesses::total 25136 # number of WriteReq accesses(hits+misses) -system.cpu5.l1c.demand_accesses::cpu5 70758 # number of demand (read+write) accesses -system.cpu5.l1c.demand_accesses::total 70758 # number of demand (read+write) accesses -system.cpu5.l1c.overall_accesses::cpu5 70758 # number of overall (read+write) accesses -system.cpu5.l1c.overall_accesses::total 70758 # number of overall (read+write) accesses -system.cpu5.l1c.ReadReq_miss_rate::cpu5 0.806650 # miss rate for ReadReq accesses -system.cpu5.l1c.ReadReq_miss_rate::total 0.806650 # miss rate for ReadReq accesses -system.cpu5.l1c.WriteReq_miss_rate::cpu5 0.955960 # miss rate for WriteReq accesses -system.cpu5.l1c.WriteReq_miss_rate::total 0.955960 # miss rate for WriteReq accesses -system.cpu5.l1c.demand_miss_rate::cpu5 0.859691 # miss rate for demand accesses -system.cpu5.l1c.demand_miss_rate::total 0.859691 # miss rate for demand accesses -system.cpu5.l1c.overall_miss_rate::cpu5 0.859691 # miss rate for overall accesses -system.cpu5.l1c.overall_miss_rate::total 0.859691 # miss rate for overall accesses -system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 18409.163963 # average ReadReq miss latency -system.cpu5.l1c.ReadReq_avg_miss_latency::total 18409.163963 # average ReadReq miss latency -system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 23565.048816 # average WriteReq miss latency -system.cpu5.l1c.WriteReq_avg_miss_latency::total 23565.048816 # average WriteReq miss latency -system.cpu5.l1c.demand_avg_miss_latency::cpu5 20445.835953 # average overall miss latency -system.cpu5.l1c.demand_avg_miss_latency::total 20445.835953 # average overall miss latency -system.cpu5.l1c.overall_avg_miss_latency::cpu5 20445.835953 # average overall miss latency -system.cpu5.l1c.overall_avg_miss_latency::total 20445.835953 # average overall miss latency -system.cpu5.l1c.blocked_cycles::no_mshrs 821580 # number of cycles access was blocked +system.cpu5.l1c.tags.occ_blocks::cpu5 391.788419 # Average occupied blocks per requestor +system.cpu5.l1c.tags.occ_percent::cpu5 0.765212 # Average percentage of cache occupancy +system.cpu5.l1c.tags.occ_percent::total 0.765212 # Average percentage of cache occupancy +system.cpu5.l1c.tags.occ_task_id_blocks::1024 407 # Occupied blocks per task id +system.cpu5.l1c.tags.age_task_id_blocks_1024::0 401 # Occupied blocks per task id +system.cpu5.l1c.tags.age_task_id_blocks_1024::1 6 # Occupied blocks per task id +system.cpu5.l1c.tags.occ_task_id_percent::1024 0.794922 # Percentage of cache occupancy per task id +system.cpu5.l1c.tags.tag_accesses 338295 # Number of tag accesses +system.cpu5.l1c.tags.data_accesses 338295 # Number of data accesses +system.cpu5.l1c.pwrStateResidencyTicks::UNDEFINED 519755500 # Cumulative time (in ticks) in various power states +system.cpu5.l1c.ReadReq_hits::cpu5 8686 # number of ReadReq hits +system.cpu5.l1c.ReadReq_hits::total 8686 # number of ReadReq hits +system.cpu5.l1c.WriteReq_hits::cpu5 1223 # number of WriteReq hits +system.cpu5.l1c.WriteReq_hits::total 1223 # number of WriteReq hits +system.cpu5.l1c.demand_hits::cpu5 9909 # number of demand (read+write) hits +system.cpu5.l1c.demand_hits::total 9909 # number of demand (read+write) hits +system.cpu5.l1c.overall_hits::cpu5 9909 # number of overall hits +system.cpu5.l1c.overall_hits::total 9909 # number of overall hits +system.cpu5.l1c.ReadReq_misses::cpu5 36676 # number of ReadReq misses +system.cpu5.l1c.ReadReq_misses::total 36676 # number of ReadReq misses +system.cpu5.l1c.WriteReq_misses::cpu5 23788 # number of WriteReq misses +system.cpu5.l1c.WriteReq_misses::total 23788 # number of WriteReq misses +system.cpu5.l1c.demand_misses::cpu5 60464 # number of demand (read+write) misses +system.cpu5.l1c.demand_misses::total 60464 # number of demand (read+write) misses +system.cpu5.l1c.overall_misses::cpu5 60464 # number of overall misses +system.cpu5.l1c.overall_misses::total 60464 # number of overall misses +system.cpu5.l1c.ReadReq_miss_latency::cpu5 728782621 # number of ReadReq miss cycles +system.cpu5.l1c.ReadReq_miss_latency::total 728782621 # number of ReadReq miss cycles +system.cpu5.l1c.WriteReq_miss_latency::cpu5 575848202 # number of WriteReq miss cycles +system.cpu5.l1c.WriteReq_miss_latency::total 575848202 # number of WriteReq miss cycles +system.cpu5.l1c.demand_miss_latency::cpu5 1304630823 # number of demand (read+write) miss cycles +system.cpu5.l1c.demand_miss_latency::total 1304630823 # number of demand (read+write) miss cycles +system.cpu5.l1c.overall_miss_latency::cpu5 1304630823 # number of overall miss cycles +system.cpu5.l1c.overall_miss_latency::total 1304630823 # number of overall miss cycles +system.cpu5.l1c.ReadReq_accesses::cpu5 45362 # number of ReadReq accesses(hits+misses) +system.cpu5.l1c.ReadReq_accesses::total 45362 # number of ReadReq accesses(hits+misses) +system.cpu5.l1c.WriteReq_accesses::cpu5 25011 # number of WriteReq accesses(hits+misses) +system.cpu5.l1c.WriteReq_accesses::total 25011 # number of WriteReq accesses(hits+misses) +system.cpu5.l1c.demand_accesses::cpu5 70373 # number of demand (read+write) accesses +system.cpu5.l1c.demand_accesses::total 70373 # number of demand (read+write) accesses +system.cpu5.l1c.overall_accesses::cpu5 70373 # number of overall (read+write) accesses +system.cpu5.l1c.overall_accesses::total 70373 # number of overall (read+write) accesses +system.cpu5.l1c.ReadReq_miss_rate::cpu5 0.808518 # miss rate for ReadReq accesses +system.cpu5.l1c.ReadReq_miss_rate::total 0.808518 # miss rate for ReadReq accesses +system.cpu5.l1c.WriteReq_miss_rate::cpu5 0.951102 # miss rate for WriteReq accesses +system.cpu5.l1c.WriteReq_miss_rate::total 0.951102 # miss rate for WriteReq accesses +system.cpu5.l1c.demand_miss_rate::cpu5 0.859193 # miss rate for demand accesses +system.cpu5.l1c.demand_miss_rate::total 0.859193 # miss rate for demand accesses +system.cpu5.l1c.overall_miss_rate::cpu5 0.859193 # miss rate for overall accesses +system.cpu5.l1c.overall_miss_rate::total 0.859193 # miss rate for overall accesses +system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 19870.831634 # average ReadReq miss latency +system.cpu5.l1c.ReadReq_avg_miss_latency::total 19870.831634 # average ReadReq miss latency +system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 24207.508071 # average WriteReq miss latency +system.cpu5.l1c.WriteReq_avg_miss_latency::total 24207.508071 # average WriteReq miss latency +system.cpu5.l1c.demand_avg_miss_latency::cpu5 21576.985032 # average overall miss latency +system.cpu5.l1c.demand_avg_miss_latency::total 21576.985032 # average overall miss latency +system.cpu5.l1c.overall_avg_miss_latency::cpu5 21576.985032 # average overall miss latency +system.cpu5.l1c.overall_avg_miss_latency::total 21576.985032 # average overall miss latency +system.cpu5.l1c.blocked_cycles::no_mshrs 880240 # number of cycles access was blocked system.cpu5.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu5.l1c.blocked::no_mshrs 66406 # number of cycles access was blocked +system.cpu5.l1c.blocked::no_mshrs 67028 # number of cycles access was blocked system.cpu5.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu5.l1c.avg_blocked_cycles::no_mshrs 12.372075 # average number of cycles each access was blocked +system.cpu5.l1c.avg_blocked_cycles::no_mshrs 13.132422 # average number of cycles each access was blocked system.cpu5.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu5.l1c.writebacks::writebacks 10004 # number of writebacks -system.cpu5.l1c.writebacks::total 10004 # number of writebacks -system.cpu5.l1c.ReadReq_mshr_misses::cpu5 36801 # number of ReadReq MSHR misses -system.cpu5.l1c.ReadReq_mshr_misses::total 36801 # number of ReadReq MSHR misses -system.cpu5.l1c.WriteReq_mshr_misses::cpu5 24029 # number of WriteReq MSHR misses -system.cpu5.l1c.WriteReq_mshr_misses::total 24029 # number of WriteReq MSHR misses -system.cpu5.l1c.demand_mshr_misses::cpu5 60830 # number of demand (read+write) MSHR misses -system.cpu5.l1c.demand_mshr_misses::total 60830 # number of demand (read+write) MSHR misses -system.cpu5.l1c.overall_mshr_misses::cpu5 60830 # number of overall MSHR misses -system.cpu5.l1c.overall_mshr_misses::total 60830 # number of overall MSHR misses -system.cpu5.l1c.ReadReq_mshr_uncacheable::cpu5 9765 # number of ReadReq MSHR uncacheable -system.cpu5.l1c.ReadReq_mshr_uncacheable::total 9765 # number of ReadReq MSHR uncacheable -system.cpu5.l1c.WriteReq_mshr_uncacheable::cpu5 5412 # number of WriteReq MSHR uncacheable -system.cpu5.l1c.WriteReq_mshr_uncacheable::total 5412 # number of WriteReq MSHR uncacheable -system.cpu5.l1c.overall_mshr_uncacheable_misses::cpu5 15177 # number of overall MSHR uncacheable misses -system.cpu5.l1c.overall_mshr_uncacheable_misses::total 15177 # number of overall MSHR uncacheable misses -system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5 640675643 # number of ReadReq MSHR miss cycles -system.cpu5.l1c.ReadReq_mshr_miss_latency::total 640675643 # number of ReadReq MSHR miss cycles -system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5 542215558 # number of WriteReq MSHR miss cycles -system.cpu5.l1c.WriteReq_mshr_miss_latency::total 542215558 # number of WriteReq MSHR miss cycles -system.cpu5.l1c.demand_mshr_miss_latency::cpu5 1182891201 # number of demand (read+write) MSHR miss cycles -system.cpu5.l1c.demand_mshr_miss_latency::total 1182891201 # number of demand (read+write) MSHR miss cycles -system.cpu5.l1c.overall_mshr_miss_latency::cpu5 1182891201 # number of overall MSHR miss cycles -system.cpu5.l1c.overall_mshr_miss_latency::total 1182891201 # number of overall MSHR miss cycles -system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5 744215663 # number of ReadReq MSHR uncacheable cycles -system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 744215663 # number of ReadReq MSHR uncacheable cycles -system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5 744215663 # number of overall MSHR uncacheable cycles -system.cpu5.l1c.overall_mshr_uncacheable_latency::total 744215663 # number of overall MSHR uncacheable cycles -system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5 0.806650 # mshr miss rate for ReadReq accesses -system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.806650 # mshr miss rate for ReadReq accesses -system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.955960 # mshr miss rate for WriteReq accesses -system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.955960 # mshr miss rate for WriteReq accesses -system.cpu5.l1c.demand_mshr_miss_rate::cpu5 0.859691 # mshr miss rate for demand accesses -system.cpu5.l1c.demand_mshr_miss_rate::total 0.859691 # mshr miss rate for demand accesses -system.cpu5.l1c.overall_mshr_miss_rate::cpu5 0.859691 # mshr miss rate for overall accesses -system.cpu5.l1c.overall_mshr_miss_rate::total 0.859691 # mshr miss rate for overall accesses -system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 17409.191136 # average ReadReq mshr miss latency -system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 17409.191136 # average ReadReq mshr miss latency -system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 22565.048816 # average WriteReq mshr miss latency -system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 22565.048816 # average WriteReq mshr miss latency -system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 19445.852392 # average overall mshr miss latency -system.cpu5.l1c.demand_avg_mshr_miss_latency::total 19445.852392 # average overall mshr miss latency -system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 19445.852392 # average overall mshr miss latency -system.cpu5.l1c.overall_avg_mshr_miss_latency::total 19445.852392 # average overall mshr miss latency -system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5 76212.561495 # average ReadReq mshr uncacheable latency -system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total 76212.561495 # average ReadReq mshr uncacheable latency -system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 49035.755617 # average overall mshr uncacheable latency -system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total 49035.755617 # average overall mshr uncacheable latency -system.cpu6.pwrStateResidencyTicks::UNDEFINED 501584000 # Cumulative time (in ticks) in various power states -system.cpu6.num_reads 99774 # number of read accesses completed -system.cpu6.num_writes 55185 # number of write accesses completed -system.cpu6.l1c.tags.pwrStateResidencyTicks::UNDEFINED 501584000 # Cumulative time (in ticks) in various power states -system.cpu6.l1c.tags.replacements 22542 # number of replacements -system.cpu6.l1c.tags.tagsinuse 391.726459 # Cycle average of tags in use -system.cpu6.l1c.tags.total_refs 13419 # Total number of references to valid blocks. -system.cpu6.l1c.tags.sampled_refs 22929 # Sample count of references to valid blocks. -system.cpu6.l1c.tags.avg_refs 0.585241 # Average number of references to valid blocks. +system.cpu5.l1c.writebacks::writebacks 9753 # number of writebacks +system.cpu5.l1c.writebacks::total 9753 # number of writebacks +system.cpu5.l1c.ReadReq_mshr_misses::cpu5 36676 # number of ReadReq MSHR misses +system.cpu5.l1c.ReadReq_mshr_misses::total 36676 # number of ReadReq MSHR misses +system.cpu5.l1c.WriteReq_mshr_misses::cpu5 23788 # number of WriteReq MSHR misses +system.cpu5.l1c.WriteReq_mshr_misses::total 23788 # number of WriteReq MSHR misses +system.cpu5.l1c.demand_mshr_misses::cpu5 60464 # number of demand (read+write) MSHR misses +system.cpu5.l1c.demand_mshr_misses::total 60464 # number of demand (read+write) MSHR misses +system.cpu5.l1c.overall_mshr_misses::cpu5 60464 # number of overall MSHR misses +system.cpu5.l1c.overall_mshr_misses::total 60464 # number of overall MSHR misses +system.cpu5.l1c.ReadReq_mshr_uncacheable::cpu5 9850 # number of ReadReq MSHR uncacheable +system.cpu5.l1c.ReadReq_mshr_uncacheable::total 9850 # number of ReadReq MSHR uncacheable +system.cpu5.l1c.WriteReq_mshr_uncacheable::cpu5 5362 # number of WriteReq MSHR uncacheable +system.cpu5.l1c.WriteReq_mshr_uncacheable::total 5362 # number of WriteReq MSHR uncacheable +system.cpu5.l1c.overall_mshr_uncacheable_misses::cpu5 15212 # number of overall MSHR uncacheable misses +system.cpu5.l1c.overall_mshr_uncacheable_misses::total 15212 # number of overall MSHR uncacheable misses +system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5 692108621 # number of ReadReq MSHR miss cycles +system.cpu5.l1c.ReadReq_mshr_miss_latency::total 692108621 # number of ReadReq MSHR miss cycles +system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5 552061202 # number of WriteReq MSHR miss cycles +system.cpu5.l1c.WriteReq_mshr_miss_latency::total 552061202 # number of WriteReq MSHR miss cycles +system.cpu5.l1c.demand_mshr_miss_latency::cpu5 1244169823 # number of demand (read+write) MSHR miss cycles +system.cpu5.l1c.demand_mshr_miss_latency::total 1244169823 # number of demand (read+write) MSHR miss cycles +system.cpu5.l1c.overall_mshr_miss_latency::cpu5 1244169823 # number of overall MSHR miss cycles +system.cpu5.l1c.overall_mshr_miss_latency::total 1244169823 # number of overall MSHR miss cycles +system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5 771042075 # number of ReadReq MSHR uncacheable cycles +system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 771042075 # number of ReadReq MSHR uncacheable cycles +system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5 771042075 # number of overall MSHR uncacheable cycles +system.cpu5.l1c.overall_mshr_uncacheable_latency::total 771042075 # number of overall MSHR uncacheable cycles +system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5 0.808518 # mshr miss rate for ReadReq accesses +system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.808518 # mshr miss rate for ReadReq accesses +system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.951102 # mshr miss rate for WriteReq accesses +system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.951102 # mshr miss rate for WriteReq accesses +system.cpu5.l1c.demand_mshr_miss_rate::cpu5 0.859193 # mshr miss rate for demand accesses +system.cpu5.l1c.demand_mshr_miss_rate::total 0.859193 # mshr miss rate for demand accesses +system.cpu5.l1c.overall_mshr_miss_rate::cpu5 0.859193 # mshr miss rate for overall accesses +system.cpu5.l1c.overall_mshr_miss_rate::total 0.859193 # mshr miss rate for overall accesses +system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 18870.886165 # average ReadReq mshr miss latency +system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 18870.886165 # average ReadReq mshr miss latency +system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 23207.550109 # average WriteReq mshr miss latency +system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 23207.550109 # average WriteReq mshr miss latency +system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 20577.034649 # average overall mshr miss latency +system.cpu5.l1c.demand_avg_mshr_miss_latency::total 20577.034649 # average overall mshr miss latency +system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 20577.034649 # average overall mshr miss latency +system.cpu5.l1c.overall_avg_mshr_miss_latency::total 20577.034649 # average overall mshr miss latency +system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5 78278.383249 # average ReadReq mshr uncacheable latency +system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total 78278.383249 # average ReadReq mshr uncacheable latency +system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 50686.436695 # average overall mshr uncacheable latency +system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total 50686.436695 # average overall mshr uncacheable latency +system.cpu6.pwrStateResidencyTicks::UNDEFINED 519755500 # Cumulative time (in ticks) in various power states +system.cpu6.num_reads 99584 # number of read accesses completed +system.cpu6.num_writes 55158 # number of write accesses completed +system.cpu6.l1c.tags.pwrStateResidencyTicks::UNDEFINED 519755500 # Cumulative time (in ticks) in various power states +system.cpu6.l1c.tags.replacements 22137 # number of replacements +system.cpu6.l1c.tags.tagsinuse 391.593819 # Cycle average of tags in use +system.cpu6.l1c.tags.total_refs 13609 # Total number of references to valid blocks. +system.cpu6.l1c.tags.sampled_refs 22548 # Sample count of references to valid blocks. +system.cpu6.l1c.tags.avg_refs 0.603557 # Average number of references to valid blocks. system.cpu6.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu6.l1c.tags.occ_blocks::cpu6 391.726459 # Average occupied blocks per requestor -system.cpu6.l1c.tags.occ_percent::cpu6 0.765091 # Average percentage of cache occupancy -system.cpu6.l1c.tags.occ_percent::total 0.765091 # Average percentage of cache occupancy -system.cpu6.l1c.tags.occ_task_id_blocks::1024 387 # Occupied blocks per task id -system.cpu6.l1c.tags.age_task_id_blocks_1024::0 375 # Occupied blocks per task id +system.cpu6.l1c.tags.occ_blocks::cpu6 391.593819 # Average occupied blocks per requestor +system.cpu6.l1c.tags.occ_percent::cpu6 0.764832 # Average percentage of cache occupancy +system.cpu6.l1c.tags.occ_percent::total 0.764832 # Average percentage of cache occupancy +system.cpu6.l1c.tags.occ_task_id_blocks::1024 411 # Occupied blocks per task id +system.cpu6.l1c.tags.age_task_id_blocks_1024::0 399 # Occupied blocks per task id system.cpu6.l1c.tags.age_task_id_blocks_1024::1 12 # Occupied blocks per task id -system.cpu6.l1c.tags.occ_task_id_percent::1024 0.755859 # Percentage of cache occupancy per task id -system.cpu6.l1c.tags.tag_accesses 339673 # Number of tag accesses -system.cpu6.l1c.tags.data_accesses 339673 # Number of data accesses -system.cpu6.l1c.pwrStateResidencyTicks::UNDEFINED 501584000 # Cumulative time (in ticks) in various power states -system.cpu6.l1c.ReadReq_hits::cpu6 8710 # number of ReadReq hits -system.cpu6.l1c.ReadReq_hits::total 8710 # number of ReadReq hits -system.cpu6.l1c.WriteReq_hits::cpu6 1147 # number of WriteReq hits -system.cpu6.l1c.WriteReq_hits::total 1147 # number of WriteReq hits -system.cpu6.l1c.demand_hits::cpu6 9857 # number of demand (read+write) hits -system.cpu6.l1c.demand_hits::total 9857 # number of demand (read+write) hits -system.cpu6.l1c.overall_hits::cpu6 9857 # number of overall hits -system.cpu6.l1c.overall_hits::total 9857 # number of overall hits -system.cpu6.l1c.ReadReq_misses::cpu6 36696 # number of ReadReq misses -system.cpu6.l1c.ReadReq_misses::total 36696 # number of ReadReq misses -system.cpu6.l1c.WriteReq_misses::cpu6 24079 # number of WriteReq misses -system.cpu6.l1c.WriteReq_misses::total 24079 # number of WriteReq misses -system.cpu6.l1c.demand_misses::cpu6 60775 # number of demand (read+write) misses -system.cpu6.l1c.demand_misses::total 60775 # number of demand (read+write) misses -system.cpu6.l1c.overall_misses::cpu6 60775 # number of overall misses -system.cpu6.l1c.overall_misses::total 60775 # number of overall misses -system.cpu6.l1c.ReadReq_miss_latency::cpu6 672502171 # number of ReadReq miss cycles -system.cpu6.l1c.ReadReq_miss_latency::total 672502171 # number of ReadReq miss cycles -system.cpu6.l1c.WriteReq_miss_latency::cpu6 571063447 # number of WriteReq miss cycles -system.cpu6.l1c.WriteReq_miss_latency::total 571063447 # number of WriteReq miss cycles -system.cpu6.l1c.demand_miss_latency::cpu6 1243565618 # number of demand (read+write) miss cycles -system.cpu6.l1c.demand_miss_latency::total 1243565618 # number of demand (read+write) miss cycles -system.cpu6.l1c.overall_miss_latency::cpu6 1243565618 # number of overall miss cycles -system.cpu6.l1c.overall_miss_latency::total 1243565618 # number of overall miss cycles -system.cpu6.l1c.ReadReq_accesses::cpu6 45406 # number of ReadReq accesses(hits+misses) -system.cpu6.l1c.ReadReq_accesses::total 45406 # number of ReadReq accesses(hits+misses) -system.cpu6.l1c.WriteReq_accesses::cpu6 25226 # number of WriteReq accesses(hits+misses) -system.cpu6.l1c.WriteReq_accesses::total 25226 # number of WriteReq accesses(hits+misses) -system.cpu6.l1c.demand_accesses::cpu6 70632 # number of demand (read+write) accesses -system.cpu6.l1c.demand_accesses::total 70632 # number of demand (read+write) accesses -system.cpu6.l1c.overall_accesses::cpu6 70632 # number of overall (read+write) accesses -system.cpu6.l1c.overall_accesses::total 70632 # number of overall (read+write) accesses -system.cpu6.l1c.ReadReq_miss_rate::cpu6 0.808175 # miss rate for ReadReq accesses -system.cpu6.l1c.ReadReq_miss_rate::total 0.808175 # miss rate for ReadReq accesses -system.cpu6.l1c.WriteReq_miss_rate::cpu6 0.954531 # miss rate for WriteReq accesses -system.cpu6.l1c.WriteReq_miss_rate::total 0.954531 # miss rate for WriteReq accesses -system.cpu6.l1c.demand_miss_rate::cpu6 0.860446 # miss rate for demand accesses -system.cpu6.l1c.demand_miss_rate::total 0.860446 # miss rate for demand accesses -system.cpu6.l1c.overall_miss_rate::cpu6 0.860446 # miss rate for overall accesses -system.cpu6.l1c.overall_miss_rate::total 0.860446 # miss rate for overall accesses -system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 18326.307254 # average ReadReq miss latency -system.cpu6.l1c.ReadReq_avg_miss_latency::total 18326.307254 # average ReadReq miss latency -system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 23716.244321 # average WriteReq miss latency -system.cpu6.l1c.WriteReq_avg_miss_latency::total 23716.244321 # average WriteReq miss latency -system.cpu6.l1c.demand_avg_miss_latency::cpu6 20461.795442 # average overall miss latency -system.cpu6.l1c.demand_avg_miss_latency::total 20461.795442 # average overall miss latency -system.cpu6.l1c.overall_avg_miss_latency::cpu6 20461.795442 # average overall miss latency -system.cpu6.l1c.overall_avg_miss_latency::total 20461.795442 # average overall miss latency -system.cpu6.l1c.blocked_cycles::no_mshrs 822508 # number of cycles access was blocked +system.cpu6.l1c.tags.occ_task_id_percent::1024 0.802734 # Percentage of cache occupancy per task id +system.cpu6.l1c.tags.tag_accesses 338403 # Number of tag accesses +system.cpu6.l1c.tags.data_accesses 338403 # Number of data accesses +system.cpu6.l1c.pwrStateResidencyTicks::UNDEFINED 519755500 # Cumulative time (in ticks) in various power states +system.cpu6.l1c.ReadReq_hits::cpu6 8781 # number of ReadReq hits +system.cpu6.l1c.ReadReq_hits::total 8781 # number of ReadReq hits +system.cpu6.l1c.WriteReq_hits::cpu6 1188 # number of WriteReq hits +system.cpu6.l1c.WriteReq_hits::total 1188 # number of WriteReq hits +system.cpu6.l1c.demand_hits::cpu6 9969 # number of demand (read+write) hits +system.cpu6.l1c.demand_hits::total 9969 # number of demand (read+write) hits +system.cpu6.l1c.overall_hits::cpu6 9969 # number of overall hits +system.cpu6.l1c.overall_hits::total 9969 # number of overall hits +system.cpu6.l1c.ReadReq_misses::cpu6 36497 # number of ReadReq misses +system.cpu6.l1c.ReadReq_misses::total 36497 # number of ReadReq misses +system.cpu6.l1c.WriteReq_misses::cpu6 23948 # number of WriteReq misses +system.cpu6.l1c.WriteReq_misses::total 23948 # number of WriteReq misses +system.cpu6.l1c.demand_misses::cpu6 60445 # number of demand (read+write) misses +system.cpu6.l1c.demand_misses::total 60445 # number of demand (read+write) misses +system.cpu6.l1c.overall_misses::cpu6 60445 # number of overall misses +system.cpu6.l1c.overall_misses::total 60445 # number of overall misses +system.cpu6.l1c.ReadReq_miss_latency::cpu6 730258004 # number of ReadReq miss cycles +system.cpu6.l1c.ReadReq_miss_latency::total 730258004 # number of ReadReq miss cycles +system.cpu6.l1c.WriteReq_miss_latency::cpu6 580007386 # number of WriteReq miss cycles +system.cpu6.l1c.WriteReq_miss_latency::total 580007386 # number of WriteReq miss cycles +system.cpu6.l1c.demand_miss_latency::cpu6 1310265390 # number of demand (read+write) miss cycles +system.cpu6.l1c.demand_miss_latency::total 1310265390 # number of demand (read+write) miss cycles +system.cpu6.l1c.overall_miss_latency::cpu6 1310265390 # number of overall miss cycles +system.cpu6.l1c.overall_miss_latency::total 1310265390 # number of overall miss cycles +system.cpu6.l1c.ReadReq_accesses::cpu6 45278 # number of ReadReq accesses(hits+misses) +system.cpu6.l1c.ReadReq_accesses::total 45278 # number of ReadReq accesses(hits+misses) +system.cpu6.l1c.WriteReq_accesses::cpu6 25136 # number of WriteReq accesses(hits+misses) +system.cpu6.l1c.WriteReq_accesses::total 25136 # number of WriteReq accesses(hits+misses) +system.cpu6.l1c.demand_accesses::cpu6 70414 # number of demand (read+write) accesses +system.cpu6.l1c.demand_accesses::total 70414 # number of demand (read+write) accesses +system.cpu6.l1c.overall_accesses::cpu6 70414 # number of overall (read+write) accesses +system.cpu6.l1c.overall_accesses::total 70414 # number of overall (read+write) accesses +system.cpu6.l1c.ReadReq_miss_rate::cpu6 0.806065 # miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_miss_rate::total 0.806065 # miss rate for ReadReq accesses +system.cpu6.l1c.WriteReq_miss_rate::cpu6 0.952737 # miss rate for WriteReq accesses +system.cpu6.l1c.WriteReq_miss_rate::total 0.952737 # miss rate for WriteReq accesses +system.cpu6.l1c.demand_miss_rate::cpu6 0.858423 # miss rate for demand accesses +system.cpu6.l1c.demand_miss_rate::total 0.858423 # miss rate for demand accesses +system.cpu6.l1c.overall_miss_rate::cpu6 0.858423 # miss rate for overall accesses +system.cpu6.l1c.overall_miss_rate::total 0.858423 # miss rate for overall accesses +system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 20008.713155 # average ReadReq miss latency +system.cpu6.l1c.ReadReq_avg_miss_latency::total 20008.713155 # average ReadReq miss latency +system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 24219.449891 # average WriteReq miss latency +system.cpu6.l1c.WriteReq_avg_miss_latency::total 24219.449891 # average WriteReq miss latency +system.cpu6.l1c.demand_avg_miss_latency::cpu6 21676.985524 # average overall miss latency +system.cpu6.l1c.demand_avg_miss_latency::total 21676.985524 # average overall miss latency +system.cpu6.l1c.overall_avg_miss_latency::cpu6 21676.985524 # average overall miss latency +system.cpu6.l1c.overall_avg_miss_latency::total 21676.985524 # average overall miss latency +system.cpu6.l1c.blocked_cycles::no_mshrs 882368 # number of cycles access was blocked system.cpu6.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu6.l1c.blocked::no_mshrs 66430 # number of cycles access was blocked +system.cpu6.l1c.blocked::no_mshrs 67127 # number of cycles access was blocked system.cpu6.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu6.l1c.avg_blocked_cycles::no_mshrs 12.381575 # average number of cycles each access was blocked +system.cpu6.l1c.avg_blocked_cycles::no_mshrs 13.144755 # average number of cycles each access was blocked system.cpu6.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu6.l1c.writebacks::writebacks 9969 # number of writebacks -system.cpu6.l1c.writebacks::total 9969 # number of writebacks -system.cpu6.l1c.ReadReq_mshr_misses::cpu6 36696 # number of ReadReq MSHR misses -system.cpu6.l1c.ReadReq_mshr_misses::total 36696 # number of ReadReq MSHR misses -system.cpu6.l1c.WriteReq_mshr_misses::cpu6 24079 # number of WriteReq MSHR misses -system.cpu6.l1c.WriteReq_mshr_misses::total 24079 # number of WriteReq MSHR misses -system.cpu6.l1c.demand_mshr_misses::cpu6 60775 # number of demand (read+write) MSHR misses -system.cpu6.l1c.demand_mshr_misses::total 60775 # number of demand (read+write) MSHR misses -system.cpu6.l1c.overall_mshr_misses::cpu6 60775 # number of overall MSHR misses -system.cpu6.l1c.overall_mshr_misses::total 60775 # number of overall MSHR misses -system.cpu6.l1c.ReadReq_mshr_uncacheable::cpu6 9782 # number of ReadReq MSHR uncacheable -system.cpu6.l1c.ReadReq_mshr_uncacheable::total 9782 # number of ReadReq MSHR uncacheable -system.cpu6.l1c.WriteReq_mshr_uncacheable::cpu6 5438 # number of WriteReq MSHR uncacheable -system.cpu6.l1c.WriteReq_mshr_uncacheable::total 5438 # number of WriteReq MSHR uncacheable -system.cpu6.l1c.overall_mshr_uncacheable_misses::cpu6 15220 # number of overall MSHR uncacheable misses -system.cpu6.l1c.overall_mshr_uncacheable_misses::total 15220 # number of overall MSHR uncacheable misses -system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6 635806171 # number of ReadReq MSHR miss cycles -system.cpu6.l1c.ReadReq_mshr_miss_latency::total 635806171 # number of ReadReq MSHR miss cycles -system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6 546984447 # number of WriteReq MSHR miss cycles -system.cpu6.l1c.WriteReq_mshr_miss_latency::total 546984447 # number of WriteReq MSHR miss cycles -system.cpu6.l1c.demand_mshr_miss_latency::cpu6 1182790618 # number of demand (read+write) MSHR miss cycles -system.cpu6.l1c.demand_mshr_miss_latency::total 1182790618 # number of demand (read+write) MSHR miss cycles -system.cpu6.l1c.overall_mshr_miss_latency::cpu6 1182790618 # number of overall MSHR miss cycles -system.cpu6.l1c.overall_mshr_miss_latency::total 1182790618 # number of overall MSHR miss cycles -system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6 745377162 # number of ReadReq MSHR uncacheable cycles -system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total 745377162 # number of ReadReq MSHR uncacheable cycles -system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6 745377162 # number of overall MSHR uncacheable cycles -system.cpu6.l1c.overall_mshr_uncacheable_latency::total 745377162 # number of overall MSHR uncacheable cycles -system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6 0.808175 # mshr miss rate for ReadReq accesses -system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.808175 # mshr miss rate for ReadReq accesses -system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6 0.954531 # mshr miss rate for WriteReq accesses -system.cpu6.l1c.WriteReq_mshr_miss_rate::total 0.954531 # mshr miss rate for WriteReq accesses -system.cpu6.l1c.demand_mshr_miss_rate::cpu6 0.860446 # mshr miss rate for demand accesses -system.cpu6.l1c.demand_mshr_miss_rate::total 0.860446 # mshr miss rate for demand accesses -system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.860446 # mshr miss rate for overall accesses -system.cpu6.l1c.overall_mshr_miss_rate::total 0.860446 # mshr miss rate for overall accesses -system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 17326.307254 # average ReadReq mshr miss latency -system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 17326.307254 # average ReadReq mshr miss latency -system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 22716.244321 # average WriteReq mshr miss latency -system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 22716.244321 # average WriteReq mshr miss latency -system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 19461.795442 # average overall mshr miss latency -system.cpu6.l1c.demand_avg_mshr_miss_latency::total 19461.795442 # average overall mshr miss latency -system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 19461.795442 # average overall mshr miss latency -system.cpu6.l1c.overall_avg_mshr_miss_latency::total 19461.795442 # average overall mshr miss latency -system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 76198.851155 # average ReadReq mshr uncacheable latency -system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total 76198.851155 # average ReadReq mshr uncacheable latency -system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 48973.532326 # average overall mshr uncacheable latency -system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total 48973.532326 # average overall mshr uncacheable latency -system.cpu7.pwrStateResidencyTicks::UNDEFINED 501584000 # Cumulative time (in ticks) in various power states -system.cpu7.num_reads 99703 # number of read accesses completed -system.cpu7.num_writes 55656 # number of write accesses completed -system.cpu7.l1c.tags.pwrStateResidencyTicks::UNDEFINED 501584000 # Cumulative time (in ticks) in various power states -system.cpu7.l1c.tags.replacements 22447 # number of replacements -system.cpu7.l1c.tags.tagsinuse 392.675740 # Cycle average of tags in use -system.cpu7.l1c.tags.total_refs 13542 # Total number of references to valid blocks. -system.cpu7.l1c.tags.sampled_refs 22845 # Sample count of references to valid blocks. -system.cpu7.l1c.tags.avg_refs 0.592777 # Average number of references to valid blocks. +system.cpu6.l1c.writebacks::writebacks 9587 # number of writebacks +system.cpu6.l1c.writebacks::total 9587 # number of writebacks +system.cpu6.l1c.ReadReq_mshr_misses::cpu6 36497 # number of ReadReq MSHR misses +system.cpu6.l1c.ReadReq_mshr_misses::total 36497 # number of ReadReq MSHR misses +system.cpu6.l1c.WriteReq_mshr_misses::cpu6 23948 # number of WriteReq MSHR misses +system.cpu6.l1c.WriteReq_mshr_misses::total 23948 # number of WriteReq MSHR misses +system.cpu6.l1c.demand_mshr_misses::cpu6 60445 # number of demand (read+write) MSHR misses +system.cpu6.l1c.demand_mshr_misses::total 60445 # number of demand (read+write) MSHR misses +system.cpu6.l1c.overall_mshr_misses::cpu6 60445 # number of overall MSHR misses +system.cpu6.l1c.overall_mshr_misses::total 60445 # number of overall MSHR misses +system.cpu6.l1c.ReadReq_mshr_uncacheable::cpu6 9817 # number of ReadReq MSHR uncacheable +system.cpu6.l1c.ReadReq_mshr_uncacheable::total 9817 # number of ReadReq MSHR uncacheable +system.cpu6.l1c.WriteReq_mshr_uncacheable::cpu6 5564 # number of WriteReq MSHR uncacheable +system.cpu6.l1c.WriteReq_mshr_uncacheable::total 5564 # number of WriteReq MSHR uncacheable +system.cpu6.l1c.overall_mshr_uncacheable_misses::cpu6 15381 # number of overall MSHR uncacheable misses +system.cpu6.l1c.overall_mshr_uncacheable_misses::total 15381 # number of overall MSHR uncacheable misses +system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6 693763004 # number of ReadReq MSHR miss cycles +system.cpu6.l1c.ReadReq_mshr_miss_latency::total 693763004 # number of ReadReq MSHR miss cycles +system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6 556061386 # number of WriteReq MSHR miss cycles +system.cpu6.l1c.WriteReq_mshr_miss_latency::total 556061386 # number of WriteReq MSHR miss cycles +system.cpu6.l1c.demand_mshr_miss_latency::cpu6 1249824390 # number of demand (read+write) MSHR miss cycles +system.cpu6.l1c.demand_mshr_miss_latency::total 1249824390 # number of demand (read+write) MSHR miss cycles +system.cpu6.l1c.overall_mshr_miss_latency::cpu6 1249824390 # number of overall MSHR miss cycles +system.cpu6.l1c.overall_mshr_miss_latency::total 1249824390 # number of overall MSHR miss cycles +system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6 767059984 # number of ReadReq MSHR uncacheable cycles +system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total 767059984 # number of ReadReq MSHR uncacheable cycles +system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6 767059984 # number of overall MSHR uncacheable cycles +system.cpu6.l1c.overall_mshr_uncacheable_latency::total 767059984 # number of overall MSHR uncacheable cycles +system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6 0.806065 # mshr miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.806065 # mshr miss rate for ReadReq accesses +system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6 0.952737 # mshr miss rate for WriteReq accesses +system.cpu6.l1c.WriteReq_mshr_miss_rate::total 0.952737 # mshr miss rate for WriteReq accesses +system.cpu6.l1c.demand_mshr_miss_rate::cpu6 0.858423 # mshr miss rate for demand accesses +system.cpu6.l1c.demand_mshr_miss_rate::total 0.858423 # mshr miss rate for demand accesses +system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.858423 # mshr miss rate for overall accesses +system.cpu6.l1c.overall_mshr_miss_rate::total 0.858423 # mshr miss rate for overall accesses +system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 19008.767954 # average ReadReq mshr miss latency +system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 19008.767954 # average ReadReq mshr miss latency +system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 23219.533406 # average WriteReq mshr miss latency +system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 23219.533406 # average WriteReq mshr miss latency +system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 20677.051700 # average overall mshr miss latency +system.cpu6.l1c.demand_avg_mshr_miss_latency::total 20677.051700 # average overall mshr miss latency +system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 20677.051700 # average overall mshr miss latency +system.cpu6.l1c.overall_avg_mshr_miss_latency::total 20677.051700 # average overall mshr miss latency +system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 78135.885097 # average ReadReq mshr uncacheable latency +system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total 78135.885097 # average ReadReq mshr uncacheable latency +system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 49870.618555 # average overall mshr uncacheable latency +system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total 49870.618555 # average overall mshr uncacheable latency +system.cpu7.pwrStateResidencyTicks::UNDEFINED 519755500 # Cumulative time (in ticks) in various power states +system.cpu7.num_reads 98890 # number of read accesses completed +system.cpu7.num_writes 55602 # number of write accesses completed +system.cpu7.l1c.tags.pwrStateResidencyTicks::UNDEFINED 519755500 # Cumulative time (in ticks) in various power states +system.cpu7.l1c.tags.replacements 22121 # number of replacements +system.cpu7.l1c.tags.tagsinuse 391.886114 # Cycle average of tags in use +system.cpu7.l1c.tags.total_refs 13491 # Total number of references to valid blocks. +system.cpu7.l1c.tags.sampled_refs 22504 # Sample count of references to valid blocks. +system.cpu7.l1c.tags.avg_refs 0.599493 # Average number of references to valid blocks. system.cpu7.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu7.l1c.tags.occ_blocks::cpu7 392.675740 # Average occupied blocks per requestor -system.cpu7.l1c.tags.occ_percent::cpu7 0.766945 # Average percentage of cache occupancy -system.cpu7.l1c.tags.occ_percent::total 0.766945 # Average percentage of cache occupancy -system.cpu7.l1c.tags.occ_task_id_blocks::1024 398 # Occupied blocks per task id -system.cpu7.l1c.tags.age_task_id_blocks_1024::0 391 # Occupied blocks per task id -system.cpu7.l1c.tags.age_task_id_blocks_1024::1 7 # Occupied blocks per task id -system.cpu7.l1c.tags.occ_task_id_percent::1024 0.777344 # Percentage of cache occupancy per task id -system.cpu7.l1c.tags.tag_accesses 338950 # Number of tag accesses -system.cpu7.l1c.tags.data_accesses 338950 # Number of data accesses -system.cpu7.l1c.pwrStateResidencyTicks::UNDEFINED 501584000 # Cumulative time (in ticks) in various power states -system.cpu7.l1c.ReadReq_hits::cpu7 8682 # number of ReadReq hits -system.cpu7.l1c.ReadReq_hits::total 8682 # number of ReadReq hits -system.cpu7.l1c.WriteReq_hits::cpu7 1173 # number of WriteReq hits -system.cpu7.l1c.WriteReq_hits::total 1173 # number of WriteReq hits -system.cpu7.l1c.demand_hits::cpu7 9855 # number of demand (read+write) hits -system.cpu7.l1c.demand_hits::total 9855 # number of demand (read+write) hits -system.cpu7.l1c.overall_hits::cpu7 9855 # number of overall hits -system.cpu7.l1c.overall_hits::total 9855 # number of overall hits -system.cpu7.l1c.ReadReq_misses::cpu7 36511 # number of ReadReq misses -system.cpu7.l1c.ReadReq_misses::total 36511 # number of ReadReq misses -system.cpu7.l1c.WriteReq_misses::cpu7 24145 # number of WriteReq misses -system.cpu7.l1c.WriteReq_misses::total 24145 # number of WriteReq misses -system.cpu7.l1c.demand_misses::cpu7 60656 # number of demand (read+write) misses -system.cpu7.l1c.demand_misses::total 60656 # number of demand (read+write) misses -system.cpu7.l1c.overall_misses::cpu7 60656 # number of overall misses -system.cpu7.l1c.overall_misses::total 60656 # number of overall misses -system.cpu7.l1c.ReadReq_miss_latency::cpu7 668215285 # number of ReadReq miss cycles -system.cpu7.l1c.ReadReq_miss_latency::total 668215285 # number of ReadReq miss cycles -system.cpu7.l1c.WriteReq_miss_latency::cpu7 564137498 # number of WriteReq miss cycles -system.cpu7.l1c.WriteReq_miss_latency::total 564137498 # number of WriteReq miss cycles -system.cpu7.l1c.demand_miss_latency::cpu7 1232352783 # number of demand (read+write) miss cycles -system.cpu7.l1c.demand_miss_latency::total 1232352783 # number of demand (read+write) miss cycles -system.cpu7.l1c.overall_miss_latency::cpu7 1232352783 # number of overall miss cycles -system.cpu7.l1c.overall_miss_latency::total 1232352783 # number of overall miss cycles -system.cpu7.l1c.ReadReq_accesses::cpu7 45193 # number of ReadReq accesses(hits+misses) -system.cpu7.l1c.ReadReq_accesses::total 45193 # number of ReadReq accesses(hits+misses) -system.cpu7.l1c.WriteReq_accesses::cpu7 25318 # number of WriteReq accesses(hits+misses) -system.cpu7.l1c.WriteReq_accesses::total 25318 # number of WriteReq accesses(hits+misses) -system.cpu7.l1c.demand_accesses::cpu7 70511 # number of demand (read+write) accesses -system.cpu7.l1c.demand_accesses::total 70511 # number of demand (read+write) accesses -system.cpu7.l1c.overall_accesses::cpu7 70511 # number of overall (read+write) accesses -system.cpu7.l1c.overall_accesses::total 70511 # number of overall (read+write) accesses -system.cpu7.l1c.ReadReq_miss_rate::cpu7 0.807891 # miss rate for ReadReq accesses -system.cpu7.l1c.ReadReq_miss_rate::total 0.807891 # miss rate for ReadReq accesses -system.cpu7.l1c.WriteReq_miss_rate::cpu7 0.953669 # miss rate for WriteReq accesses -system.cpu7.l1c.WriteReq_miss_rate::total 0.953669 # miss rate for WriteReq accesses -system.cpu7.l1c.demand_miss_rate::cpu7 0.860235 # miss rate for demand accesses -system.cpu7.l1c.demand_miss_rate::total 0.860235 # miss rate for demand accesses -system.cpu7.l1c.overall_miss_rate::cpu7 0.860235 # miss rate for overall accesses -system.cpu7.l1c.overall_miss_rate::total 0.860235 # miss rate for overall accesses -system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 18301.752486 # average ReadReq miss latency -system.cpu7.l1c.ReadReq_avg_miss_latency::total 18301.752486 # average ReadReq miss latency -system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 23364.568151 # average WriteReq miss latency -system.cpu7.l1c.WriteReq_avg_miss_latency::total 23364.568151 # average WriteReq miss latency -system.cpu7.l1c.demand_avg_miss_latency::cpu7 20317.079646 # average overall miss latency -system.cpu7.l1c.demand_avg_miss_latency::total 20317.079646 # average overall miss latency -system.cpu7.l1c.overall_avg_miss_latency::cpu7 20317.079646 # average overall miss latency -system.cpu7.l1c.overall_avg_miss_latency::total 20317.079646 # average overall miss latency -system.cpu7.l1c.blocked_cycles::no_mshrs 824059 # number of cycles access was blocked +system.cpu7.l1c.tags.occ_blocks::cpu7 391.886114 # Average occupied blocks per requestor +system.cpu7.l1c.tags.occ_percent::cpu7 0.765403 # Average percentage of cache occupancy +system.cpu7.l1c.tags.occ_percent::total 0.765403 # Average percentage of cache occupancy +system.cpu7.l1c.tags.occ_task_id_blocks::1024 383 # Occupied blocks per task id +system.cpu7.l1c.tags.age_task_id_blocks_1024::0 374 # Occupied blocks per task id +system.cpu7.l1c.tags.age_task_id_blocks_1024::1 9 # Occupied blocks per task id +system.cpu7.l1c.tags.occ_task_id_percent::1024 0.748047 # Percentage of cache occupancy per task id +system.cpu7.l1c.tags.tag_accesses 336547 # Number of tag accesses +system.cpu7.l1c.tags.data_accesses 336547 # Number of data accesses +system.cpu7.l1c.pwrStateResidencyTicks::UNDEFINED 519755500 # Cumulative time (in ticks) in various power states +system.cpu7.l1c.ReadReq_hits::cpu7 8615 # number of ReadReq hits +system.cpu7.l1c.ReadReq_hits::total 8615 # number of ReadReq hits +system.cpu7.l1c.WriteReq_hits::cpu7 1223 # number of WriteReq hits +system.cpu7.l1c.WriteReq_hits::total 1223 # number of WriteReq hits +system.cpu7.l1c.demand_hits::cpu7 9838 # number of demand (read+write) hits +system.cpu7.l1c.demand_hits::total 9838 # number of demand (read+write) hits +system.cpu7.l1c.overall_hits::cpu7 9838 # number of overall hits +system.cpu7.l1c.overall_hits::total 9838 # number of overall hits +system.cpu7.l1c.ReadReq_misses::cpu7 36077 # number of ReadReq misses +system.cpu7.l1c.ReadReq_misses::total 36077 # number of ReadReq misses +system.cpu7.l1c.WriteReq_misses::cpu7 24110 # number of WriteReq misses +system.cpu7.l1c.WriteReq_misses::total 24110 # number of WriteReq misses +system.cpu7.l1c.demand_misses::cpu7 60187 # number of demand (read+write) misses +system.cpu7.l1c.demand_misses::total 60187 # number of demand (read+write) misses +system.cpu7.l1c.overall_misses::cpu7 60187 # number of overall misses +system.cpu7.l1c.overall_misses::total 60187 # number of overall misses +system.cpu7.l1c.ReadReq_miss_latency::cpu7 719876948 # number of ReadReq miss cycles +system.cpu7.l1c.ReadReq_miss_latency::total 719876948 # number of ReadReq miss cycles +system.cpu7.l1c.WriteReq_miss_latency::cpu7 591584960 # number of WriteReq miss cycles +system.cpu7.l1c.WriteReq_miss_latency::total 591584960 # number of WriteReq miss cycles +system.cpu7.l1c.demand_miss_latency::cpu7 1311461908 # number of demand (read+write) miss cycles +system.cpu7.l1c.demand_miss_latency::total 1311461908 # number of demand (read+write) miss cycles +system.cpu7.l1c.overall_miss_latency::cpu7 1311461908 # number of overall miss cycles +system.cpu7.l1c.overall_miss_latency::total 1311461908 # number of overall miss cycles +system.cpu7.l1c.ReadReq_accesses::cpu7 44692 # number of ReadReq accesses(hits+misses) +system.cpu7.l1c.ReadReq_accesses::total 44692 # number of ReadReq accesses(hits+misses) +system.cpu7.l1c.WriteReq_accesses::cpu7 25333 # number of WriteReq accesses(hits+misses) +system.cpu7.l1c.WriteReq_accesses::total 25333 # number of WriteReq accesses(hits+misses) +system.cpu7.l1c.demand_accesses::cpu7 70025 # number of demand (read+write) accesses +system.cpu7.l1c.demand_accesses::total 70025 # number of demand (read+write) accesses +system.cpu7.l1c.overall_accesses::cpu7 70025 # number of overall (read+write) accesses +system.cpu7.l1c.overall_accesses::total 70025 # number of overall (read+write) accesses +system.cpu7.l1c.ReadReq_miss_rate::cpu7 0.807236 # miss rate for ReadReq accesses +system.cpu7.l1c.ReadReq_miss_rate::total 0.807236 # miss rate for ReadReq accesses +system.cpu7.l1c.WriteReq_miss_rate::cpu7 0.951723 # miss rate for WriteReq accesses +system.cpu7.l1c.WriteReq_miss_rate::total 0.951723 # miss rate for WriteReq accesses +system.cpu7.l1c.demand_miss_rate::cpu7 0.859507 # miss rate for demand accesses +system.cpu7.l1c.demand_miss_rate::total 0.859507 # miss rate for demand accesses +system.cpu7.l1c.overall_miss_rate::cpu7 0.859507 # miss rate for overall accesses +system.cpu7.l1c.overall_miss_rate::total 0.859507 # miss rate for overall accesses +system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 19953.902708 # average ReadReq miss latency +system.cpu7.l1c.ReadReq_avg_miss_latency::total 19953.902708 # average ReadReq miss latency +system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 24536.912484 # average WriteReq miss latency +system.cpu7.l1c.WriteReq_avg_miss_latency::total 24536.912484 # average WriteReq miss latency +system.cpu7.l1c.demand_avg_miss_latency::cpu7 21789.786964 # average overall miss latency +system.cpu7.l1c.demand_avg_miss_latency::total 21789.786964 # average overall miss latency +system.cpu7.l1c.overall_avg_miss_latency::cpu7 21789.786964 # average overall miss latency +system.cpu7.l1c.overall_avg_miss_latency::total 21789.786964 # average overall miss latency +system.cpu7.l1c.blocked_cycles::no_mshrs 881767 # number of cycles access was blocked system.cpu7.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu7.l1c.blocked::no_mshrs 66592 # number of cycles access was blocked +system.cpu7.l1c.blocked::no_mshrs 66704 # number of cycles access was blocked system.cpu7.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu7.l1c.avg_blocked_cycles::no_mshrs 12.374745 # average number of cycles each access was blocked +system.cpu7.l1c.avg_blocked_cycles::no_mshrs 13.219102 # average number of cycles each access was blocked system.cpu7.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu7.l1c.writebacks::writebacks 9889 # number of writebacks -system.cpu7.l1c.writebacks::total 9889 # number of writebacks -system.cpu7.l1c.ReadReq_mshr_misses::cpu7 36511 # number of ReadReq MSHR misses -system.cpu7.l1c.ReadReq_mshr_misses::total 36511 # number of ReadReq MSHR misses -system.cpu7.l1c.WriteReq_mshr_misses::cpu7 24145 # number of WriteReq MSHR misses -system.cpu7.l1c.WriteReq_mshr_misses::total 24145 # number of WriteReq MSHR misses -system.cpu7.l1c.demand_mshr_misses::cpu7 60656 # number of demand (read+write) MSHR misses -system.cpu7.l1c.demand_mshr_misses::total 60656 # number of demand (read+write) MSHR misses -system.cpu7.l1c.overall_mshr_misses::cpu7 60656 # number of overall MSHR misses -system.cpu7.l1c.overall_mshr_misses::total 60656 # number of overall MSHR misses -system.cpu7.l1c.ReadReq_mshr_uncacheable::cpu7 9951 # number of ReadReq MSHR uncacheable -system.cpu7.l1c.ReadReq_mshr_uncacheable::total 9951 # number of ReadReq MSHR uncacheable -system.cpu7.l1c.WriteReq_mshr_uncacheable::cpu7 5417 # number of WriteReq MSHR uncacheable -system.cpu7.l1c.WriteReq_mshr_uncacheable::total 5417 # number of WriteReq MSHR uncacheable -system.cpu7.l1c.overall_mshr_uncacheable_misses::cpu7 15368 # number of overall MSHR uncacheable misses -system.cpu7.l1c.overall_mshr_uncacheable_misses::total 15368 # number of overall MSHR uncacheable misses -system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7 631704285 # number of ReadReq MSHR miss cycles -system.cpu7.l1c.ReadReq_mshr_miss_latency::total 631704285 # number of ReadReq MSHR miss cycles -system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7 539994498 # number of WriteReq MSHR miss cycles -system.cpu7.l1c.WriteReq_mshr_miss_latency::total 539994498 # number of WriteReq MSHR miss cycles -system.cpu7.l1c.demand_mshr_miss_latency::cpu7 1171698783 # number of demand (read+write) MSHR miss cycles -system.cpu7.l1c.demand_mshr_miss_latency::total 1171698783 # number of demand (read+write) MSHR miss cycles -system.cpu7.l1c.overall_mshr_miss_latency::cpu7 1171698783 # number of overall MSHR miss cycles -system.cpu7.l1c.overall_mshr_miss_latency::total 1171698783 # number of overall MSHR miss cycles -system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 757938041 # number of ReadReq MSHR uncacheable cycles -system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 757938041 # number of ReadReq MSHR uncacheable cycles -system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 757938041 # number of overall MSHR uncacheable cycles -system.cpu7.l1c.overall_mshr_uncacheable_latency::total 757938041 # number of overall MSHR uncacheable cycles -system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.807891 # mshr miss rate for ReadReq accesses -system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.807891 # mshr miss rate for ReadReq accesses -system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.953669 # mshr miss rate for WriteReq accesses -system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.953669 # mshr miss rate for WriteReq accesses -system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.860235 # mshr miss rate for demand accesses -system.cpu7.l1c.demand_mshr_miss_rate::total 0.860235 # mshr miss rate for demand accesses -system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.860235 # mshr miss rate for overall accesses -system.cpu7.l1c.overall_mshr_miss_rate::total 0.860235 # mshr miss rate for overall accesses -system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 17301.752486 # average ReadReq mshr miss latency -system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 17301.752486 # average ReadReq mshr miss latency -system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 22364.650984 # average WriteReq mshr miss latency -system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 22364.650984 # average WriteReq mshr miss latency -system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 19317.112619 # average overall mshr miss latency -system.cpu7.l1c.demand_avg_mshr_miss_latency::total 19317.112619 # average overall mshr miss latency -system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 19317.112619 # average overall mshr miss latency -system.cpu7.l1c.overall_avg_mshr_miss_latency::total 19317.112619 # average overall mshr miss latency -system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7 76167.022510 # average ReadReq mshr uncacheable latency -system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total 76167.022510 # average ReadReq mshr uncacheable latency -system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::cpu7 49319.237441 # average overall mshr uncacheable latency -system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::total 49319.237441 # average overall mshr uncacheable latency -system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 501584000 # Cumulative time (in ticks) in various power states -system.l2c.tags.replacements 13600 # number of replacements -system.l2c.tags.tagsinuse 785.994901 # Cycle average of tags in use -system.l2c.tags.total_refs 164496 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 14391 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 11.430477 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 730.947637 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0 6.698781 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1 6.684981 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2 7.056959 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3 6.865777 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu4 6.833706 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu5 7.577663 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu6 6.826515 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu7 6.502881 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.713816 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0 0.006542 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1 0.006528 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2 0.006892 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3 0.006705 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu4 0.006674 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu5 0.007400 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu6 0.006667 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu7 0.006350 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.767573 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 791 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 651 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 140 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.772461 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 2102241 # Number of tag accesses -system.l2c.tags.data_accesses 2102241 # Number of data accesses -system.l2c.pwrStateResidencyTicks::UNDEFINED 501584000 # Cumulative time (in ticks) in various power states -system.l2c.WritebackDirty_hits::writebacks 77703 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 77703 # number of WritebackDirty hits -system.l2c.UpgradeReq_hits::cpu0 290 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1 290 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu2 294 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu3 264 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu4 279 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu5 289 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu6 268 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu7 325 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 2299 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0 1816 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1 1719 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2 1709 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu3 1840 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu4 1788 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu5 1754 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu6 1794 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu7 1762 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 14182 # number of ReadExReq hits -system.l2c.ReadSharedReq_hits::cpu0 10810 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1 10840 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu2 11008 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu3 10829 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu4 10875 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu5 10716 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu6 10827 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu7 10910 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 86815 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0 12626 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1 12559 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2 12717 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3 12669 # number of demand (read+write) hits -system.l2c.demand_hits::cpu4 12663 # number of demand (read+write) hits -system.l2c.demand_hits::cpu5 12470 # number of demand (read+write) hits -system.l2c.demand_hits::cpu6 12621 # number of demand (read+write) hits -system.l2c.demand_hits::cpu7 12672 # number of demand (read+write) hits -system.l2c.demand_hits::total 100997 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0 12626 # number of overall hits -system.l2c.overall_hits::cpu1 12559 # number of overall hits -system.l2c.overall_hits::cpu2 12717 # number of overall hits -system.l2c.overall_hits::cpu3 12669 # number of overall hits -system.l2c.overall_hits::cpu4 12663 # number of overall hits -system.l2c.overall_hits::cpu5 12470 # number of overall hits -system.l2c.overall_hits::cpu6 12621 # number of overall hits -system.l2c.overall_hits::cpu7 12672 # number of overall hits -system.l2c.overall_hits::total 100997 # number of overall hits -system.l2c.UpgradeReq_misses::cpu0 1987 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1 2133 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2 2089 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu3 2051 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu4 2132 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu5 2090 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu6 2082 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu7 2039 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 16603 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu0 4589 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1 4573 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu2 4653 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu3 4696 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu4 4757 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu5 4526 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu6 4651 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu7 4580 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 37025 # number of ReadExReq misses -system.l2c.ReadSharedReq_misses::cpu0 704 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1 708 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu2 710 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu3 726 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu4 671 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu5 758 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu6 689 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu7 675 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::total 5641 # number of ReadSharedReq misses -system.l2c.demand_misses::cpu0 5293 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1 5281 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2 5363 # number of demand (read+write) misses -system.l2c.demand_misses::cpu3 5422 # number of demand (read+write) misses -system.l2c.demand_misses::cpu4 5428 # number of demand (read+write) misses -system.l2c.demand_misses::cpu5 5284 # number of demand (read+write) misses -system.l2c.demand_misses::cpu6 5340 # number of demand (read+write) misses -system.l2c.demand_misses::cpu7 5255 # number of demand (read+write) misses -system.l2c.demand_misses::total 42666 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0 5293 # number of overall misses -system.l2c.overall_misses::cpu1 5281 # number of overall misses -system.l2c.overall_misses::cpu2 5363 # number of overall misses -system.l2c.overall_misses::cpu3 5422 # number of overall misses -system.l2c.overall_misses::cpu4 5428 # number of overall misses -system.l2c.overall_misses::cpu5 5284 # number of overall misses -system.l2c.overall_misses::cpu6 5340 # number of overall misses -system.l2c.overall_misses::cpu7 5255 # number of overall misses -system.l2c.overall_misses::total 42666 # number of overall misses -system.l2c.UpgradeReq_miss_latency::cpu0 33033499 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1 37073999 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu2 35504000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu3 34167500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu4 35922999 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu5 36683500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu6 35141499 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu7 35012999 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 282539995 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0 156097931 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1 156545440 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu2 159419095 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu3 159741454 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu4 162402934 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu5 154349443 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu6 159730395 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu7 156156442 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 1264443134 # number of ReadExReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0 50090895 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1 50336063 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu2 50437231 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu3 51704240 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu4 47729417 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu5 53673691 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu6 48908906 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu7 47302737 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::total 400183180 # number of ReadSharedReq miss cycles -system.l2c.demand_miss_latency::cpu0 206188826 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1 206881503 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2 209856326 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu3 211445694 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu4 210132351 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu5 208023134 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu6 208639301 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu7 203459179 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 1664626314 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0 206188826 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1 206881503 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2 209856326 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu3 211445694 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu4 210132351 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu5 208023134 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu6 208639301 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu7 203459179 # number of overall miss cycles -system.l2c.overall_miss_latency::total 1664626314 # number of overall miss cycles -system.l2c.WritebackDirty_accesses::writebacks 77703 # number of WritebackDirty accesses(hits+misses) -system.l2c.WritebackDirty_accesses::total 77703 # number of WritebackDirty accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0 2277 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1 2423 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu2 2383 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu3 2315 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu4 2411 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu5 2379 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu6 2350 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu7 2364 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 18902 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0 6405 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1 6292 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu2 6362 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu3 6536 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu4 6545 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu5 6280 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu6 6445 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu7 6342 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 51207 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0 11514 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1 11548 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu2 11718 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu3 11555 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu4 11546 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu5 11474 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu6 11516 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu7 11585 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::total 92456 # number of ReadSharedReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0 17919 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1 17840 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2 18080 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu3 18091 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu4 18091 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu5 17754 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu6 17961 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu7 17927 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 143663 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0 17919 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1 17840 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2 18080 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu3 18091 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu4 18091 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu5 17754 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu6 17961 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu7 17927 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 143663 # number of overall (read+write) accesses -system.l2c.UpgradeReq_miss_rate::cpu0 0.872639 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1 0.880314 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu2 0.876626 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu3 0.885961 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu4 0.884280 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu5 0.878520 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu6 0.885957 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu7 0.862521 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.878373 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0 0.716472 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1 0.726796 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu2 0.731374 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu3 0.718482 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu4 0.726814 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu5 0.720701 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu6 0.721645 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu7 0.722170 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.723046 # miss rate for ReadExReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0 0.061143 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1 0.061309 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu2 0.060591 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu3 0.062830 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu4 0.058115 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu5 0.066062 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu6 0.059830 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu7 0.058265 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::total 0.061013 # miss rate for ReadSharedReq accesses -system.l2c.demand_miss_rate::cpu0 0.295385 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1 0.296020 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2 0.296626 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu3 0.299707 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu4 0.300039 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu5 0.297623 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu6 0.297311 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu7 0.293133 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.296987 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0 0.295385 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1 0.296020 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2 0.296626 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu3 0.299707 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu4 0.300039 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu5 0.297623 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu6 0.297311 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu7 0.293133 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.296987 # miss rate for overall accesses -system.l2c.UpgradeReq_avg_miss_latency::cpu0 16624.810770 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1 17381.152836 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu2 16995.691719 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu3 16658.946855 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu4 16849.436679 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu5 17551.913876 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu6 16878.721902 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu7 17171.652281 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 17017.406192 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0 34015.674657 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1 34232.547562 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu2 34261.572104 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu3 34016.493612 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu4 34139.780114 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu5 34102.837605 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu6 34343.236938 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu7 34095.293013 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 34151.063714 # average ReadExReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0 71151.839489 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1 71096.134181 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu2 71038.353521 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu3 71217.961433 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu4 71131.769001 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu5 70809.618734 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu6 70985.349782 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu7 70078.128889 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::total 70941.886190 # average ReadSharedReq miss latency -system.l2c.demand_avg_miss_latency::cpu0 38955.002078 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1 39174.683393 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2 39130.398285 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu3 38997.730358 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu4 38712.665991 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu5 39368.496215 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu6 39071.030150 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu7 38717.255756 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 39015.288848 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0 38955.002078 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1 39174.683393 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2 39130.398285 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu3 38997.730358 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu4 38712.665991 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu5 39368.496215 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu6 39071.030150 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu7 38717.255756 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 39015.288848 # average overall miss latency -system.l2c.blocked_cycles::no_mshrs 20827 # number of cycles access was blocked +system.cpu7.l1c.writebacks::writebacks 9764 # number of writebacks +system.cpu7.l1c.writebacks::total 9764 # number of writebacks +system.cpu7.l1c.ReadReq_mshr_misses::cpu7 36077 # number of ReadReq MSHR misses +system.cpu7.l1c.ReadReq_mshr_misses::total 36077 # number of ReadReq MSHR misses +system.cpu7.l1c.WriteReq_mshr_misses::cpu7 24110 # number of WriteReq MSHR misses +system.cpu7.l1c.WriteReq_mshr_misses::total 24110 # number of WriteReq MSHR misses +system.cpu7.l1c.demand_mshr_misses::cpu7 60187 # number of demand (read+write) MSHR misses +system.cpu7.l1c.demand_mshr_misses::total 60187 # number of demand (read+write) MSHR misses +system.cpu7.l1c.overall_mshr_misses::cpu7 60187 # number of overall MSHR misses +system.cpu7.l1c.overall_mshr_misses::total 60187 # number of overall MSHR misses +system.cpu7.l1c.ReadReq_mshr_uncacheable::cpu7 9808 # number of ReadReq MSHR uncacheable +system.cpu7.l1c.ReadReq_mshr_uncacheable::total 9808 # number of ReadReq MSHR uncacheable +system.cpu7.l1c.WriteReq_mshr_uncacheable::cpu7 5554 # number of WriteReq MSHR uncacheable +system.cpu7.l1c.WriteReq_mshr_uncacheable::total 5554 # number of WriteReq MSHR uncacheable +system.cpu7.l1c.overall_mshr_uncacheable_misses::cpu7 15362 # number of overall MSHR uncacheable misses +system.cpu7.l1c.overall_mshr_uncacheable_misses::total 15362 # number of overall MSHR uncacheable misses +system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7 683799948 # number of ReadReq MSHR miss cycles +system.cpu7.l1c.ReadReq_mshr_miss_latency::total 683799948 # number of ReadReq MSHR miss cycles +system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7 567476960 # number of WriteReq MSHR miss cycles +system.cpu7.l1c.WriteReq_mshr_miss_latency::total 567476960 # number of WriteReq MSHR miss cycles +system.cpu7.l1c.demand_mshr_miss_latency::cpu7 1251276908 # number of demand (read+write) MSHR miss cycles +system.cpu7.l1c.demand_mshr_miss_latency::total 1251276908 # number of demand (read+write) MSHR miss cycles +system.cpu7.l1c.overall_mshr_miss_latency::cpu7 1251276908 # number of overall MSHR miss cycles +system.cpu7.l1c.overall_mshr_miss_latency::total 1251276908 # number of overall MSHR miss cycles +system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 764550984 # number of ReadReq MSHR uncacheable cycles +system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 764550984 # number of ReadReq MSHR uncacheable cycles +system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 764550984 # number of overall MSHR uncacheable cycles +system.cpu7.l1c.overall_mshr_uncacheable_latency::total 764550984 # number of overall MSHR uncacheable cycles +system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.807236 # mshr miss rate for ReadReq accesses +system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.807236 # mshr miss rate for ReadReq accesses +system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.951723 # mshr miss rate for WriteReq accesses +system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.951723 # mshr miss rate for WriteReq accesses +system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.859507 # mshr miss rate for demand accesses +system.cpu7.l1c.demand_mshr_miss_rate::total 0.859507 # mshr miss rate for demand accesses +system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.859507 # mshr miss rate for overall accesses +system.cpu7.l1c.overall_mshr_miss_rate::total 0.859507 # mshr miss rate for overall accesses +system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 18953.902708 # average ReadReq mshr miss latency +system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 18953.902708 # average ReadReq mshr miss latency +system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 23536.995438 # average WriteReq mshr miss latency +system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 23536.995438 # average WriteReq mshr miss latency +system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 20789.820194 # average overall mshr miss latency +system.cpu7.l1c.demand_avg_mshr_miss_latency::total 20789.820194 # average overall mshr miss latency +system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 20789.820194 # average overall mshr miss latency +system.cpu7.l1c.overall_avg_mshr_miss_latency::total 20789.820194 # average overall mshr miss latency +system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7 77951.772431 # average ReadReq mshr uncacheable latency +system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total 77951.772431 # average ReadReq mshr uncacheable latency +system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::cpu7 49768.974352 # average overall mshr uncacheable latency +system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::total 49768.974352 # average overall mshr uncacheable latency +system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 519755500 # Cumulative time (in ticks) in various power states +system.l2c.tags.replacements 90719 # number of replacements +system.l2c.tags.tagsinuse 1018.150991 # Cycle average of tags in use +system.l2c.tags.total_refs 149983 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 91743 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 1.634817 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 9046000 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 702.470265 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0 39.119320 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1 40.193520 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2 38.067708 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3 40.504400 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu4 39.836129 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu5 39.104490 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu6 39.067369 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu7 39.787790 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.686006 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0 0.038202 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1 0.039251 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2 0.037175 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3 0.039555 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu4 0.038902 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu5 0.038188 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu6 0.038152 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu7 0.038855 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.994288 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1024 1024 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 929 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 95 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 2127679 # Number of tag accesses +system.l2c.tags.data_accesses 2127679 # Number of data accesses +system.l2c.pwrStateResidencyTicks::UNDEFINED 519755500 # Cumulative time (in ticks) in various power states +system.l2c.WritebackDirty_hits::writebacks 76258 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 76258 # number of WritebackDirty hits +system.l2c.UpgradeReq_hits::cpu0 455 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1 421 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu2 452 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu3 407 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu4 451 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu5 439 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu6 454 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu7 475 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 3554 # number of UpgradeReq hits +system.l2c.ReadExReq_hits::cpu0 1826 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1 1861 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu2 1960 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu3 1829 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu4 1871 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu5 1808 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu6 1856 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu7 1881 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 14892 # number of ReadExReq hits +system.l2c.ReadSharedReq_hits::cpu0 9343 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1 9296 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu2 9301 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu3 9456 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu4 9362 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu5 9172 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu6 9284 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu7 9134 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 74348 # number of ReadSharedReq hits +system.l2c.demand_hits::cpu0 11169 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1 11157 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2 11261 # number of demand (read+write) hits +system.l2c.demand_hits::cpu3 11285 # number of demand (read+write) hits +system.l2c.demand_hits::cpu4 11233 # number of demand (read+write) hits +system.l2c.demand_hits::cpu5 10980 # number of demand (read+write) hits +system.l2c.demand_hits::cpu6 11140 # number of demand (read+write) hits +system.l2c.demand_hits::cpu7 11015 # number of demand (read+write) hits +system.l2c.demand_hits::total 89240 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0 11169 # number of overall hits +system.l2c.overall_hits::cpu1 11157 # number of overall hits +system.l2c.overall_hits::cpu2 11261 # number of overall hits +system.l2c.overall_hits::cpu3 11285 # number of overall hits +system.l2c.overall_hits::cpu4 11233 # number of overall hits +system.l2c.overall_hits::cpu5 10980 # number of overall hits +system.l2c.overall_hits::cpu6 11140 # number of overall hits +system.l2c.overall_hits::cpu7 11015 # number of overall hits +system.l2c.overall_hits::total 89240 # number of overall hits +system.l2c.UpgradeReq_misses::cpu0 1925 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1 1836 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu2 1914 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu3 1906 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu4 1942 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu5 1877 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu6 1898 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu7 1911 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 15209 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::cpu0 4693 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1 4629 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu2 4644 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu3 4614 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu4 4607 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu5 4628 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu6 4562 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu7 4784 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 37161 # number of ReadExReq misses +system.l2c.ReadSharedReq_misses::cpu0 2455 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1 2583 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu2 2376 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu3 2554 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu4 2482 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu5 2499 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu6 2567 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu7 2497 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::total 20013 # number of ReadSharedReq misses +system.l2c.demand_misses::cpu0 7148 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1 7212 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2 7020 # number of demand (read+write) misses +system.l2c.demand_misses::cpu3 7168 # number of demand (read+write) misses +system.l2c.demand_misses::cpu4 7089 # number of demand (read+write) misses +system.l2c.demand_misses::cpu5 7127 # number of demand (read+write) misses +system.l2c.demand_misses::cpu6 7129 # number of demand (read+write) misses +system.l2c.demand_misses::cpu7 7281 # number of demand (read+write) misses +system.l2c.demand_misses::total 57174 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0 7148 # number of overall misses +system.l2c.overall_misses::cpu1 7212 # number of overall misses +system.l2c.overall_misses::cpu2 7020 # number of overall misses +system.l2c.overall_misses::cpu3 7168 # number of overall misses +system.l2c.overall_misses::cpu4 7089 # number of overall misses +system.l2c.overall_misses::cpu5 7127 # number of overall misses +system.l2c.overall_misses::cpu6 7129 # number of overall misses +system.l2c.overall_misses::cpu7 7281 # number of overall misses +system.l2c.overall_misses::total 57174 # number of overall misses +system.l2c.UpgradeReq_miss_latency::cpu0 32240808 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1 31334307 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu2 31443971 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu3 32481798 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu4 31939294 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu5 32487949 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu6 32438947 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu7 31458982 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 255826056 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0 205522581 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1 201589053 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu2 204096506 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu3 201630443 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu4 202953396 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu5 200092863 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu6 200475342 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu7 208573158 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 1624933342 # number of ReadExReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0 170016591 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1 178762923 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu2 164403073 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu3 176363992 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu4 171439292 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu5 173166429 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu6 177285527 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu7 173293048 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::total 1384730875 # number of ReadSharedReq miss cycles +system.l2c.demand_miss_latency::cpu0 375539172 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1 380351976 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2 368499579 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu3 377994435 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu4 374392688 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu5 373259292 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu6 377760869 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu7 381866206 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 3009664217 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0 375539172 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1 380351976 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2 368499579 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu3 377994435 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu4 374392688 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu5 373259292 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu6 377760869 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu7 381866206 # number of overall miss cycles +system.l2c.overall_miss_latency::total 3009664217 # number of overall miss cycles +system.l2c.WritebackDirty_accesses::writebacks 76258 # number of WritebackDirty accesses(hits+misses) +system.l2c.WritebackDirty_accesses::total 76258 # number of WritebackDirty accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0 2380 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1 2257 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu2 2366 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu3 2313 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu4 2393 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu5 2316 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu6 2352 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu7 2386 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 18763 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0 6519 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1 6490 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu2 6604 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu3 6443 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu4 6478 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu5 6436 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu6 6418 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu7 6665 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 52053 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0 11798 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1 11879 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu2 11677 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu3 12010 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu4 11844 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu5 11671 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu6 11851 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu7 11631 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::total 94361 # number of ReadSharedReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0 18317 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1 18369 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2 18281 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu3 18453 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu4 18322 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu5 18107 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu6 18269 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu7 18296 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 146414 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0 18317 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1 18369 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2 18281 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu3 18453 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu4 18322 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu5 18107 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu6 18269 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu7 18296 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 146414 # number of overall (read+write) accesses +system.l2c.UpgradeReq_miss_rate::cpu0 0.808824 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1 0.813469 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu2 0.808960 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu3 0.824038 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu4 0.811534 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu5 0.810449 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu6 0.806973 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu7 0.800922 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.810585 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0 0.719896 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1 0.713251 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu2 0.703210 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu3 0.716126 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu4 0.711176 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu5 0.719080 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu6 0.710813 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu7 0.717779 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.713907 # miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0 0.208086 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1 0.217443 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu2 0.203477 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu3 0.212656 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu4 0.209558 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu5 0.214120 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu6 0.216606 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu7 0.214685 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::total 0.212090 # miss rate for ReadSharedReq accesses +system.l2c.demand_miss_rate::cpu0 0.390239 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1 0.392618 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2 0.384005 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu3 0.388446 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu4 0.386912 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu5 0.393605 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu6 0.390224 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu7 0.397956 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.390495 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0 0.390239 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1 0.392618 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2 0.384005 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu3 0.388446 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu4 0.386912 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu5 0.393605 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu6 0.390224 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu7 0.397956 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.390495 # miss rate for overall accesses +system.l2c.UpgradeReq_avg_miss_latency::cpu0 16748.471688 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1 17066.616013 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu2 16428.407001 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu3 17041.866737 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu4 16446.598352 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu5 17308.443793 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu6 17091.120653 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu7 16462.052329 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 16820.701953 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0 43793.432985 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1 43549.158134 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu2 43948.429371 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu3 43699.705895 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu4 44053.265900 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu5 43235.277226 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu6 43944.616835 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu7 43598.068144 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 43726.846479 # average ReadExReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0 69253.193890 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1 69207.480836 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu2 69193.212542 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu3 69054.029757 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu4 69073.042707 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu5 69294.289316 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu6 69063.313985 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu7 69400.499800 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::total 69191.569230 # average ReadSharedReq miss latency +system.l2c.demand_avg_miss_latency::cpu0 52537.656967 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1 52738.765391 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2 52492.817521 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu3 52733.598633 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu4 52813.187756 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu5 52372.567981 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu6 52989.320943 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu7 52446.944925 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 52640.434761 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0 52537.656967 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1 52738.765391 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2 52492.817521 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu3 52733.598633 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu4 52813.187756 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu5 52372.567981 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu6 52989.320943 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu7 52446.944925 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 52640.434761 # average overall miss latency +system.l2c.blocked_cycles::no_mshrs 47178 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.blocked::no_mshrs 3189 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 7722 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs 6.530887 # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_mshrs 6.109557 # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.l2c.writebacks::writebacks 6244 # number of writebacks -system.l2c.writebacks::total 6244 # number of writebacks -system.l2c.UpgradeReq_mshr_hits::cpu1 1 # number of UpgradeReq MSHR hits +system.l2c.writebacks::writebacks 22214 # number of writebacks +system.l2c.writebacks::total 22214 # number of writebacks +system.l2c.UpgradeReq_mshr_hits::cpu0 1 # number of UpgradeReq MSHR hits +system.l2c.UpgradeReq_mshr_hits::cpu1 3 # number of UpgradeReq MSHR hits system.l2c.UpgradeReq_mshr_hits::cpu2 1 # number of UpgradeReq MSHR hits +system.l2c.UpgradeReq_mshr_hits::cpu3 3 # number of UpgradeReq MSHR hits +system.l2c.UpgradeReq_mshr_hits::cpu4 3 # number of UpgradeReq MSHR hits system.l2c.UpgradeReq_mshr_hits::cpu5 2 # number of UpgradeReq MSHR hits -system.l2c.UpgradeReq_mshr_hits::total 4 # number of UpgradeReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu0 2 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu1 2 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu2 5 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu3 6 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu4 4 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu5 2 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu6 8 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu7 6 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::total 35 # number of ReadExReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu0 10 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu1 9 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu2 15 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu3 4 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu4 4 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu5 10 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu6 10 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu7 15 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::total 77 # number of ReadSharedReq MSHR hits -system.l2c.demand_mshr_hits::cpu0 12 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1 11 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu2 20 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu3 10 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu4 8 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu5 12 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu6 18 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu7 21 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 112 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu0 12 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1 11 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu2 20 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu3 10 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu4 8 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu5 12 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu6 18 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu7 21 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 112 # number of overall MSHR hits -system.l2c.CleanEvict_mshr_misses::writebacks 1208 # number of CleanEvict MSHR misses -system.l2c.CleanEvict_mshr_misses::total 1208 # number of CleanEvict MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0 1987 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1 2132 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu2 2088 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu3 2051 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu4 2132 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu5 2088 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu6 2082 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu7 2039 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 16599 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0 4587 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1 4571 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu2 4648 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu3 4690 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu4 4753 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu5 4524 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu6 4643 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu7 4574 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 36990 # number of ReadExReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu0 694 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu1 699 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu2 695 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu3 722 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu4 667 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu5 748 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu6 679 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu7 660 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::total 5564 # number of ReadSharedReq MSHR misses -system.l2c.demand_mshr_misses::cpu0 5281 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1 5270 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2 5343 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu3 5412 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu4 5420 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu5 5272 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu6 5322 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu7 5234 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 42554 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0 5281 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1 5270 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2 5343 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu3 5412 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu4 5420 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu5 5272 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu6 5322 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu7 5234 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 42554 # number of overall MSHR misses -system.l2c.ReadReq_mshr_uncacheable::cpu0 9909 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu1 9863 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu2 10005 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu3 9773 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu4 9801 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu5 9765 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu6 9782 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu7 9951 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::total 78849 # number of ReadReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu0 5376 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu1 5525 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu2 5482 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu3 5537 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu4 5496 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu5 5409 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu6 5438 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu7 5416 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::total 43679 # number of WriteReq MSHR uncacheable -system.l2c.overall_mshr_uncacheable_misses::cpu0 15285 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu1 15388 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu2 15487 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu3 15310 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu4 15297 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu5 15174 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu6 15220 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu7 15367 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::total 122528 # number of overall MSHR uncacheable misses -system.l2c.UpgradeReq_mshr_miss_latency::cpu0 41114731 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1 44135575 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu2 43262560 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu3 42495420 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu4 44129731 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu5 43370592 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu6 43201403 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu7 42227606 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 343937618 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0 110096109 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1 110716645 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu2 112771891 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu3 112546795 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu4 114695609 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu5 108961847 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu6 112947605 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu7 110110769 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 892847270 # number of ReadExReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu0 42686190 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu1 42892571 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu2 42733862 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu3 44195932 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu4 40778543 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu5 45766520 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu6 41640903 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu7 39953551 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::total 340648072 # number of ReadSharedReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0 152782299 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1 153609216 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2 155505753 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu3 156742727 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu4 155474152 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu5 154728367 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu6 154588508 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu7 150064320 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 1233495342 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0 152782299 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1 153609216 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2 155505753 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu3 156742727 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu4 155474152 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu5 154728367 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu6 154588508 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu7 150064320 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 1233495342 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0 531934603 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1 529144419 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu2 536612256 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu3 524755063 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu4 526637223 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu5 524048250 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu6 524701912 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu7 534783521 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 4232617247 # number of ReadReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0 531934603 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1 529144419 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu2 536612256 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu3 524755063 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu4 526637223 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu5 524048250 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu6 524701912 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu7 534783521 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 4232617247 # number of overall MSHR uncacheable cycles +system.l2c.UpgradeReq_mshr_hits::cpu6 1 # number of UpgradeReq MSHR hits +system.l2c.UpgradeReq_mshr_hits::cpu7 4 # number of UpgradeReq MSHR hits +system.l2c.UpgradeReq_mshr_hits::total 18 # number of UpgradeReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu0 16 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu1 18 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu2 19 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu3 22 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu4 24 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu5 19 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu6 17 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu7 18 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::total 153 # number of ReadExReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu0 39 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu1 35 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu2 40 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu3 33 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu4 29 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu5 39 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu6 37 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu7 32 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::total 284 # number of ReadSharedReq MSHR hits +system.l2c.demand_mshr_hits::cpu0 55 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1 53 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu2 59 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu3 55 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu4 53 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu5 58 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu6 54 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu7 50 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 437 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu0 55 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1 53 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu2 59 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu3 55 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu4 53 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu5 58 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu6 54 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu7 50 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 437 # number of overall MSHR hits +system.l2c.CleanEvict_mshr_misses::writebacks 4803 # number of CleanEvict MSHR misses +system.l2c.CleanEvict_mshr_misses::total 4803 # number of CleanEvict MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0 1924 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1 1833 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu2 1913 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu3 1903 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu4 1939 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu5 1875 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu6 1897 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu7 1907 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 15191 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0 4677 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1 4611 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu2 4625 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu3 4592 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu4 4583 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu5 4609 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu6 4545 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu7 4766 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 37008 # number of ReadExReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0 2416 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1 2548 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu2 2336 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu3 2521 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu4 2453 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu5 2460 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu6 2530 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu7 2465 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::total 19729 # number of ReadSharedReq MSHR misses +system.l2c.demand_mshr_misses::cpu0 7093 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1 7159 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2 6961 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu3 7113 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu4 7036 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu5 7069 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu6 7075 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu7 7231 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 56737 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0 7093 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1 7159 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2 6961 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu3 7113 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu4 7036 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu5 7069 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu6 7075 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu7 7231 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 56737 # number of overall MSHR misses +system.l2c.ReadReq_mshr_uncacheable::cpu0 9869 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu1 9955 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu2 9851 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu3 9751 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu4 9934 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu5 9850 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu6 9817 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu7 9808 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::total 78835 # number of ReadReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu0 5546 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu1 5403 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu2 5468 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu3 5504 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu4 5430 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu5 5362 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu6 5563 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu7 5554 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::total 43830 # number of WriteReq MSHR uncacheable +system.l2c.overall_mshr_uncacheable_misses::cpu0 15415 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu1 15358 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu2 15319 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu3 15255 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu4 15364 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu5 15212 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu6 15380 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu7 15362 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::total 122665 # number of overall MSHR uncacheable misses +system.l2c.UpgradeReq_mshr_miss_latency::cpu0 44370463 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1 41900556 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu2 43952891 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu3 43546523 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu4 44916850 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu5 43178222 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu6 43968016 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu7 43732622 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 349566143 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0 157972902 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1 154816531 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu2 157133230 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu3 154812258 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu4 156142960 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu5 152972566 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu6 154139305 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu7 159984433 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 1247974185 # number of ReadExReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0 144081359 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1 151505606 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu2 139163869 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu3 149583647 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu4 145392585 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu5 146682187 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu6 150257353 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu7 146960130 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::total 1173626736 # number of ReadSharedReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0 302054261 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1 306322137 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2 296297099 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu3 304395905 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu4 301535545 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu5 299654753 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu6 304396658 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu7 306944563 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 2421600921 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0 302054261 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1 306322137 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2 296297099 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu3 304395905 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu4 301535545 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu5 299654753 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu6 304396658 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu7 306944563 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 2421600921 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0 562092060 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1 566771491 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu2 561276835 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu3 555967979 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu4 566543445 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu5 562440249 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu6 559671781 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu7 557696401 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 4492460241 # number of ReadReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0 562092060 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1 566771491 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu2 561276835 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu3 555967979 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu4 566543445 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu5 562440249 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu6 559671781 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu7 557696401 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 4492460241 # number of overall MSHR uncacheable cycles system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0 0.872639 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.879901 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.876206 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu3 0.885961 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.884280 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.877680 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.885957 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.862521 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.878161 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0 0.716159 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.726478 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu2 0.730588 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu3 0.717564 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.726203 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.720382 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.720403 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.721224 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.722362 # mshr miss rate for ReadExReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0 0.060274 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1 0.060530 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu2 0.059310 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu3 0.062484 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu4 0.057769 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu5 0.065191 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu6 0.058961 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu7 0.056970 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::total 0.060180 # mshr miss rate for ReadSharedReq accesses -system.l2c.demand_mshr_miss_rate::cpu0 0.294715 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1 0.295404 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2 0.295520 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu3 0.299154 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu4 0.299596 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu5 0.296947 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu6 0.296309 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu7 0.291962 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.296207 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0 0.294715 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1 0.295404 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2 0.295520 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu3 0.299154 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu4 0.299596 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu5 0.296947 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu6 0.296309 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu7 0.291962 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.296207 # mshr miss rate for overall accesses -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 20691.862607 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 20701.489212 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 20719.616858 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 20719.366163 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 20698.748124 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 20771.356322 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 20749.953410 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 20709.958803 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20720.381830 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 24001.767822 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 24221.536863 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 24262.455034 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 23997.184435 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 24131.203240 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 24085.288904 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 24326.427956 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 24073.189550 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 24137.530954 # average ReadExReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0 61507.478386 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1 61362.762518 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2 61487.571223 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3 61213.202216 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu4 61137.245877 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu5 61185.187166 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu6 61326.808542 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu7 60535.683333 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 61223.593098 # average ReadSharedReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0 28930.562204 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1 29147.858824 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2 29104.576642 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3 28962.070769 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu4 28685.267897 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu5 29349.083270 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu6 29047.070274 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu7 28671.058464 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 28986.589792 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0 28930.562204 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1 29147.858824 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2 29104.576642 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3 28962.070769 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu4 28685.267897 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu5 29349.083270 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu6 29047.070274 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu7 28671.058464 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 28986.589792 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 53681.966192 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1 53649.439217 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2 53634.408396 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3 53694.368464 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu4 53733.009183 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu5 53665.975422 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu6 53639.533020 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu7 53741.686363 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 53680.037122 # average ReadReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0 34801.086228 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1 34386.822134 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu2 34649.206173 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu3 34275.314370 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu4 34427.484016 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu5 34535.933175 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu6 34474.501445 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 34800.775753 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 34544.081736 # average overall mshr uncacheable latency -system.membus.snoop_filter.tot_requests 125015 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 119335 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.l2c.UpgradeReq_mshr_miss_rate::cpu0 0.808403 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.812140 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.808538 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu3 0.822741 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.810280 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.809585 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.806548 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.799246 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.809625 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0 0.717441 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.710478 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2 0.700333 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu3 0.712711 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.707471 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.716128 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.708165 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.715079 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.710968 # mshr miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0 0.204780 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1 0.214496 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu2 0.200051 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu3 0.209908 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu4 0.207109 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu5 0.210779 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu6 0.213484 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu7 0.211934 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.209080 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu0 0.387236 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1 0.389733 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2 0.380778 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3 0.385466 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu4 0.384019 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu5 0.390402 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu6 0.387268 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu7 0.395223 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.387511 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0 0.387236 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1 0.389733 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2 0.380778 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3 0.385466 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu4 0.384019 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu5 0.390402 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu6 0.387268 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu7 0.395223 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.387511 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 23061.571206 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 22859.004910 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 22975.897020 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 22883.091435 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 23164.956163 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 23028.385067 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 23177.657354 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 22932.680650 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 23011.397736 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 33776.545221 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 33575.478421 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 33974.752432 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 33713.470819 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 34070.032730 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 33189.968757 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 33914.038504 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 33567.862568 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 33721.740840 # average ReadExReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0 59636.324089 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1 59460.598901 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2 59573.574058 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3 59335.044427 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu4 59271.335100 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu5 59626.905285 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu6 59390.258103 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu7 59618.713996 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 59487.390947 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0 42584.838714 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1 42788.397402 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2 42565.306565 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3 42794.306903 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu4 42856.103610 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu5 42389.977790 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu6 43024.262615 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu7 42448.425252 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 42681.159050 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0 42584.838714 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1 42788.397402 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2 42565.306565 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3 42794.306903 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu4 42856.103610 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu5 42389.977790 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu6 43024.262615 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu7 42448.425252 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 42681.159050 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 56955.320701 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1 56933.349171 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2 56976.635367 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3 57016.508973 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu4 57030.747433 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu5 57100.532893 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu6 57010.469695 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu7 56861.378569 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 56985.605898 # average ReadReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0 36463.967564 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1 36903.990819 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu2 36639.260722 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu3 36444.967486 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu4 36874.736071 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu5 36973.458388 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu6 36389.582640 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 36303.632405 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 36623.814788 # average overall mshr uncacheable latency +system.membus.snoop_filter.tot_requests 164288 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 148961 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 501584000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 78845 # Transaction distribution -system.membus.trans_dist::ReadResp 84388 # Transaction distribution -system.membus.trans_dist::WriteReq 43678 # Transaction distribution -system.membus.trans_dist::WriteResp 43672 # Transaction distribution -system.membus.trans_dist::WritebackDirty 6244 # Transaction distribution -system.membus.trans_dist::CleanEvict 1238 # Transaction distribution -system.membus.trans_dist::UpgradeReq 61417 # Transaction distribution -system.membus.trans_dist::ReadExReq 49074 # Transaction distribution -system.membus.trans_dist::ReadExResp 3109 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 5552 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 377217 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 377217 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 1076434 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 1076434 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 56879 # Total snoops (count) +system.membus.pwrStateResidencyTicks::UNDEFINED 519755500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadReq 78834 # Transaction distribution +system.membus.trans_dist::ReadResp 98509 # Transaction distribution +system.membus.trans_dist::WriteReq 43828 # Transaction distribution +system.membus.trans_dist::WriteResp 43821 # Transaction distribution +system.membus.trans_dist::WritebackDirty 22214 # Transaction distribution +system.membus.trans_dist::CleanEvict 4965 # Transaction distribution +system.membus.trans_dist::UpgradeReq 52120 # Transaction distribution +system.membus.trans_dist::ReadExReq 56238 # Transaction distribution +system.membus.trans_dist::ReadExResp 10901 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 19680 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 431110 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 431110 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 3501537 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 3501537 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 56051 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 245548 # Request fanout histogram +system.membus.snoop_fanout::samples 276559 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 245548 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 276559 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 245548 # Request fanout histogram -system.membus.reqLayer0.occupancy 288762573 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 57.6 # Layer utilization (%) -system.membus.respLayer0.occupancy 244649000 # Layer occupancy (ticks) -system.membus.respLayer0.utilization 48.8 # Layer utilization (%) -system.toL2Bus.snoop_filter.tot_requests 663848 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 283900 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 334405 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 12239 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 5805 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 6434 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 501584000 # Cumulative time (in ticks) in various power states -system.toL2Bus.trans_dist::ReadReq 78849 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 372013 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 43679 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 43671 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 83947 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 105636 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 29816 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 29815 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 162678 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 162674 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 293185 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side 133340 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side 133547 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side 134024 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side 133820 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side 133857 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side 133294 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side 133675 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side 133694 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 1069251 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side 1781172 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side 1779932 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side 1786043 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side 1802764 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side 1783744 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side 1780612 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side 1792304 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side 1782917 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 14289488 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 336712 # Total snoops (count) -system.toL2Bus.snoopTraffic 20380288 # Total snoop traffic (bytes) -system.toL2Bus.snoop_fanout::samples 624467 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.150434 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.985907 # Request fanout histogram +system.membus.snoop_fanout::total 276559 # Request fanout histogram +system.membus.reqLayer0.occupancy 402118445 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 77.4 # Layer utilization (%) +system.membus.respLayer0.occupancy 354384000 # Layer occupancy (ticks) +system.membus.respLayer0.utilization 68.2 # Layer utilization (%) +system.toL2Bus.snoop_filter.tot_requests 665414 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 284013 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 335409 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 85048 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 42676 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 42372 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 519755500 # Cumulative time (in ticks) in various power states +system.toL2Bus.trans_dist::ReadReq 78835 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 370283 # Transaction distribution +system.toL2Bus.trans_dist::ReadRespWithInvalidate 4 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 43830 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 43821 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 98472 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 166953 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 29477 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 29475 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 161940 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 161937 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 291468 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side 133769 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side 133274 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side 133373 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side 133750 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side 133468 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side 133407 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side 133623 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side 133404 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 1068068 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side 1804723 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side 1795646 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side 1797908 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side 1798742 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side 1795138 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side 1788203 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side 1789204 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side 1803712 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 14373276 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 408427 # Total snoops (count) +system.toL2Bus.snoopTraffic 21069312 # Total snoop traffic (bytes) +system.toL2Bus.snoop_fanout::samples 705291 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.195765 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.989501 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 172892 27.69% 27.69% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 258676 41.42% 69.11% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 133601 21.39% 90.50% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 46619 7.47% 97.97% # Request fanout histogram -system.toL2Bus.snoop_fanout::4 10890 1.74% 99.71% # Request fanout histogram -system.toL2Bus.snoop_fanout::5 1624 0.26% 99.97% # Request fanout histogram -system.toL2Bus.snoop_fanout::6 162 0.03% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::7 3 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 180431 25.58% 25.58% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 295517 41.90% 67.48% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 157808 22.37% 89.86% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 56265 7.98% 97.83% # Request fanout histogram +system.toL2Bus.snoop_fanout::4 13098 1.86% 99.69% # Request fanout histogram +system.toL2Bus.snoop_fanout::5 1998 0.28% 99.98% # Request fanout histogram +system.toL2Bus.snoop_fanout::6 166 0.02% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::7 8 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 7 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 624467 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 494463871 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 98.6 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 102665881 # Layer occupancy (ticks) -system.toL2Bus.respLayer0.utilization 20.5 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 102599371 # Layer occupancy (ticks) -system.toL2Bus.respLayer1.utilization 20.5 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 102945420 # Layer occupancy (ticks) -system.toL2Bus.respLayer2.utilization 20.5 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 102767709 # Layer occupancy (ticks) -system.toL2Bus.respLayer3.utilization 20.5 # Layer utilization (%) -system.toL2Bus.respLayer4.occupancy 102912196 # Layer occupancy (ticks) -system.toL2Bus.respLayer4.utilization 20.5 # Layer utilization (%) -system.toL2Bus.respLayer5.occupancy 102768177 # Layer occupancy (ticks) -system.toL2Bus.respLayer5.utilization 20.5 # Layer utilization (%) -system.toL2Bus.respLayer6.occupancy 102966672 # Layer occupancy (ticks) -system.toL2Bus.respLayer6.utilization 20.5 # Layer utilization (%) -system.toL2Bus.respLayer7.occupancy 102752542 # Layer occupancy (ticks) -system.toL2Bus.respLayer7.utilization 20.5 # Layer utilization (%) +system.toL2Bus.snoop_fanout::total 705291 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 498497896 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 95.9 # Layer utilization (%) +system.toL2Bus.respLayer0.occupancy 102236927 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 19.7 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 101928534 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.utilization 19.6 # Layer utilization (%) +system.toL2Bus.respLayer2.occupancy 102159135 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.utilization 19.7 # Layer utilization (%) +system.toL2Bus.respLayer3.occupancy 102401165 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.utilization 19.7 # Layer utilization (%) +system.toL2Bus.respLayer4.occupancy 102112987 # Layer occupancy (ticks) +system.toL2Bus.respLayer4.utilization 19.6 # Layer utilization (%) +system.toL2Bus.respLayer5.occupancy 102230994 # Layer occupancy (ticks) +system.toL2Bus.respLayer5.utilization 19.7 # Layer utilization (%) +system.toL2Bus.respLayer6.occupancy 102247991 # Layer occupancy (ticks) +system.toL2Bus.respLayer6.utilization 19.7 # Layer utilization (%) +system.toL2Bus.respLayer7.occupancy 101908995 # Layer occupancy (ticks) +system.toL2Bus.respLayer7.utilization 19.6 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt b/tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt index bfbf99e79..797f06fbf 100644 --- a/tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt +++ b/tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt @@ -1,1765 +1,1777 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000500 # Number of seconds simulated -sim_ticks 500337000 # Number of ticks simulated -final_tick 500337000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000522 # Number of seconds simulated +sim_ticks 521659000 # Number of ticks simulated +final_tick 521659000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_tick_rate 71022114 # Simulator tick rate (ticks/s) -host_mem_usage 232508 # Number of bytes of host memory used -host_seconds 7.04 # Real time elapsed on the host +host_tick_rate 99821577 # Simulator tick rate (ticks/s) +host_mem_usage 236108 # Number of bytes of host memory used +host_seconds 5.23 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 500337000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu0 75919 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1 81043 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2 80577 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3 79993 # Number of bytes read from this memory -system.physmem.bytes_read::cpu4 82197 # Number of bytes read from this memory -system.physmem.bytes_read::cpu5 76405 # Number of bytes read from this memory -system.physmem.bytes_read::cpu6 83460 # Number of bytes read from this memory -system.physmem.bytes_read::cpu7 78091 # Number of bytes read from this memory -system.physmem.bytes_read::total 637685 # Number of bytes read from this memory -system.physmem.bytes_written::writebacks 400320 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0 5398 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1 5467 # Number of bytes written to this memory -system.physmem.bytes_written::cpu2 5426 # Number of bytes written to this memory -system.physmem.bytes_written::cpu3 5579 # Number of bytes written to this memory -system.physmem.bytes_written::cpu4 5520 # Number of bytes written to this memory -system.physmem.bytes_written::cpu5 5451 # Number of bytes written to this memory -system.physmem.bytes_written::cpu6 5589 # Number of bytes written to this memory -system.physmem.bytes_written::cpu7 5357 # Number of bytes written to this memory -system.physmem.bytes_written::total 444107 # Number of bytes written to this memory -system.physmem.num_reads::cpu0 10777 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1 10924 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2 11088 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3 10945 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu4 11007 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu5 10948 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu6 11010 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu7 10807 # Number of read requests responded to by this memory -system.physmem.num_reads::total 87506 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 6255 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0 5398 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1 5467 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu2 5426 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu3 5579 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu4 5520 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu5 5451 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu6 5589 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu7 5357 # Number of write requests responded to by this memory -system.physmem.num_writes::total 50042 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0 151735730 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1 161976828 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2 161045455 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3 159878242 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu4 164283273 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu5 152707075 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu6 166807572 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu7 156076804 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1274510980 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 800100732 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0 10788728 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1 10926635 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu2 10844691 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu3 11150485 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu4 11032564 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu5 10894657 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu6 11170471 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu7 10706784 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 887615747 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 800100732 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0 162524459 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1 172903463 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2 171890146 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3 171028727 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu4 175315837 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu5 163601732 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu6 177978043 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu7 166783588 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2162126727 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 500337000 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 521659000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu0 261574 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1 259726 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2 254844 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3 256223 # Number of bytes read from this memory +system.physmem.bytes_read::cpu4 261709 # Number of bytes read from this memory +system.physmem.bytes_read::cpu5 259188 # Number of bytes read from this memory +system.physmem.bytes_read::cpu6 257071 # Number of bytes read from this memory +system.physmem.bytes_read::cpu7 253171 # Number of bytes read from this memory +system.physmem.bytes_read::total 2063506 # Number of bytes read from this memory +system.physmem.bytes_written::writebacks 1454400 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0 5412 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1 5468 # Number of bytes written to this memory +system.physmem.bytes_written::cpu2 5497 # Number of bytes written to this memory +system.physmem.bytes_written::cpu3 5381 # Number of bytes written to this memory +system.physmem.bytes_written::cpu4 5437 # Number of bytes written to this memory +system.physmem.bytes_written::cpu5 5503 # Number of bytes written to this memory +system.physmem.bytes_written::cpu6 5505 # Number of bytes written to this memory +system.physmem.bytes_written::cpu7 5688 # Number of bytes written to this memory +system.physmem.bytes_written::total 1498291 # Number of bytes written to this memory +system.physmem.num_reads::cpu0 13795 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1 13774 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2 13680 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3 13673 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu4 13678 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu5 13740 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu6 13765 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu7 13771 # Number of read requests responded to by this memory +system.physmem.num_reads::total 109876 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 22725 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0 5412 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1 5468 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu2 5497 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu3 5381 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu4 5437 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu5 5503 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu6 5505 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu7 5688 # Number of write requests responded to by this memory +system.physmem.num_writes::total 66616 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0 501427178 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1 497884633 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2 488526029 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3 491169519 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu4 501685967 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu5 496853308 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu6 492795102 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu7 485318954 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3955660690 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2788028195 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0 10374593 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1 10481943 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu2 10537535 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu3 10315168 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu4 10422517 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu5 10549037 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu6 10552871 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu7 10903675 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2872165533 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2788028195 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0 511801771 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1 508366577 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2 499063565 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3 501484686 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu4 512108485 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu5 507402345 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu6 503347973 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu7 496222628 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6827826224 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 521659000 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu0.pwrStateResidencyTicks::UNDEFINED 500337000 # Cumulative time (in ticks) in various power states -system.cpu0.num_reads 99905 # number of read accesses completed -system.cpu0.num_writes 55400 # number of write accesses completed -system.cpu0.l1c.tags.pwrStateResidencyTicks::UNDEFINED 500337000 # Cumulative time (in ticks) in various power states -system.cpu0.l1c.tags.replacements 22463 # number of replacements -system.cpu0.l1c.tags.tagsinuse 391.153981 # Cycle average of tags in use -system.cpu0.l1c.tags.total_refs 13877 # Total number of references to valid blocks. -system.cpu0.l1c.tags.sampled_refs 22862 # Sample count of references to valid blocks. -system.cpu0.l1c.tags.avg_refs 0.606990 # Average number of references to valid blocks. +system.cpu0.pwrStateResidencyTicks::UNDEFINED 521659000 # Cumulative time (in ticks) in various power states +system.cpu0.num_reads 99316 # number of read accesses completed +system.cpu0.num_writes 55523 # number of write accesses completed +system.cpu0.l1c.tags.pwrStateResidencyTicks::UNDEFINED 521659000 # Cumulative time (in ticks) in various power states +system.cpu0.l1c.tags.replacements 22284 # number of replacements +system.cpu0.l1c.tags.tagsinuse 390.956341 # Cycle average of tags in use +system.cpu0.l1c.tags.total_refs 13404 # Total number of references to valid blocks. +system.cpu0.l1c.tags.sampled_refs 22693 # Sample count of references to valid blocks. +system.cpu0.l1c.tags.avg_refs 0.590667 # Average number of references to valid blocks. system.cpu0.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.l1c.tags.occ_blocks::cpu0 391.153981 # Average occupied blocks per requestor -system.cpu0.l1c.tags.occ_percent::cpu0 0.763973 # Average percentage of cache occupancy -system.cpu0.l1c.tags.occ_percent::total 0.763973 # Average percentage of cache occupancy -system.cpu0.l1c.tags.occ_task_id_blocks::1024 399 # Occupied blocks per task id -system.cpu0.l1c.tags.age_task_id_blocks_1024::0 389 # Occupied blocks per task id -system.cpu0.l1c.tags.age_task_id_blocks_1024::1 10 # Occupied blocks per task id -system.cpu0.l1c.tags.occ_task_id_percent::1024 0.779297 # Percentage of cache occupancy per task id -system.cpu0.l1c.tags.tag_accesses 340651 # Number of tag accesses -system.cpu0.l1c.tags.data_accesses 340651 # Number of data accesses -system.cpu0.l1c.pwrStateResidencyTicks::UNDEFINED 500337000 # Cumulative time (in ticks) in various power states -system.cpu0.l1c.ReadReq_hits::cpu0 8894 # number of ReadReq hits -system.cpu0.l1c.ReadReq_hits::total 8894 # number of ReadReq hits -system.cpu0.l1c.WriteReq_hits::cpu0 1261 # number of WriteReq hits -system.cpu0.l1c.WriteReq_hits::total 1261 # number of WriteReq hits -system.cpu0.l1c.demand_hits::cpu0 10155 # number of demand (read+write) hits -system.cpu0.l1c.demand_hits::total 10155 # number of demand (read+write) hits -system.cpu0.l1c.overall_hits::cpu0 10155 # number of overall hits -system.cpu0.l1c.overall_hits::total 10155 # number of overall hits -system.cpu0.l1c.ReadReq_misses::cpu0 36720 # number of ReadReq misses -system.cpu0.l1c.ReadReq_misses::total 36720 # number of ReadReq misses -system.cpu0.l1c.WriteReq_misses::cpu0 24041 # number of WriteReq misses -system.cpu0.l1c.WriteReq_misses::total 24041 # number of WriteReq misses -system.cpu0.l1c.demand_misses::cpu0 60761 # number of demand (read+write) misses -system.cpu0.l1c.demand_misses::total 60761 # number of demand (read+write) misses -system.cpu0.l1c.overall_misses::cpu0 60761 # number of overall misses -system.cpu0.l1c.overall_misses::total 60761 # number of overall misses -system.cpu0.l1c.ReadReq_miss_latency::cpu0 677337671 # number of ReadReq miss cycles -system.cpu0.l1c.ReadReq_miss_latency::total 677337671 # number of ReadReq miss cycles -system.cpu0.l1c.WriteReq_miss_latency::cpu0 564207136 # number of WriteReq miss cycles -system.cpu0.l1c.WriteReq_miss_latency::total 564207136 # number of WriteReq miss cycles -system.cpu0.l1c.demand_miss_latency::cpu0 1241544807 # number of demand (read+write) miss cycles -system.cpu0.l1c.demand_miss_latency::total 1241544807 # number of demand (read+write) miss cycles -system.cpu0.l1c.overall_miss_latency::cpu0 1241544807 # number of overall miss cycles -system.cpu0.l1c.overall_miss_latency::total 1241544807 # number of overall miss cycles -system.cpu0.l1c.ReadReq_accesses::cpu0 45614 # number of ReadReq accesses(hits+misses) -system.cpu0.l1c.ReadReq_accesses::total 45614 # number of ReadReq accesses(hits+misses) -system.cpu0.l1c.WriteReq_accesses::cpu0 25302 # number of WriteReq accesses(hits+misses) -system.cpu0.l1c.WriteReq_accesses::total 25302 # number of WriteReq accesses(hits+misses) -system.cpu0.l1c.demand_accesses::cpu0 70916 # number of demand (read+write) accesses -system.cpu0.l1c.demand_accesses::total 70916 # number of demand (read+write) accesses -system.cpu0.l1c.overall_accesses::cpu0 70916 # number of overall (read+write) accesses -system.cpu0.l1c.overall_accesses::total 70916 # number of overall (read+write) accesses -system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.805016 # miss rate for ReadReq accesses -system.cpu0.l1c.ReadReq_miss_rate::total 0.805016 # miss rate for ReadReq accesses -system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.950162 # miss rate for WriteReq accesses -system.cpu0.l1c.WriteReq_miss_rate::total 0.950162 # miss rate for WriteReq accesses -system.cpu0.l1c.demand_miss_rate::cpu0 0.856802 # miss rate for demand accesses -system.cpu0.l1c.demand_miss_rate::total 0.856802 # miss rate for demand accesses -system.cpu0.l1c.overall_miss_rate::cpu0 0.856802 # miss rate for overall accesses -system.cpu0.l1c.overall_miss_rate::total 0.856802 # miss rate for overall accesses -system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 18446.015005 # average ReadReq miss latency -system.cpu0.l1c.ReadReq_avg_miss_latency::total 18446.015005 # average ReadReq miss latency -system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 23468.538580 # average WriteReq miss latency -system.cpu0.l1c.WriteReq_avg_miss_latency::total 23468.538580 # average WriteReq miss latency -system.cpu0.l1c.demand_avg_miss_latency::cpu0 20433.251708 # average overall miss latency -system.cpu0.l1c.demand_avg_miss_latency::total 20433.251708 # average overall miss latency -system.cpu0.l1c.overall_avg_miss_latency::cpu0 20433.251708 # average overall miss latency -system.cpu0.l1c.overall_avg_miss_latency::total 20433.251708 # average overall miss latency -system.cpu0.l1c.blocked_cycles::no_mshrs 800862 # number of cycles access was blocked +system.cpu0.l1c.tags.occ_blocks::cpu0 390.956341 # Average occupied blocks per requestor +system.cpu0.l1c.tags.occ_percent::cpu0 0.763587 # Average percentage of cache occupancy +system.cpu0.l1c.tags.occ_percent::total 0.763587 # Average percentage of cache occupancy +system.cpu0.l1c.tags.occ_task_id_blocks::1024 409 # Occupied blocks per task id +system.cpu0.l1c.tags.age_task_id_blocks_1024::0 395 # Occupied blocks per task id +system.cpu0.l1c.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id +system.cpu0.l1c.tags.occ_task_id_percent::1024 0.798828 # Percentage of cache occupancy per task id +system.cpu0.l1c.tags.tag_accesses 337730 # Number of tag accesses +system.cpu0.l1c.tags.data_accesses 337730 # Number of data accesses +system.cpu0.l1c.pwrStateResidencyTicks::UNDEFINED 521659000 # Cumulative time (in ticks) in various power states +system.cpu0.l1c.ReadReq_hits::cpu0 8729 # number of ReadReq hits +system.cpu0.l1c.ReadReq_hits::total 8729 # number of ReadReq hits +system.cpu0.l1c.WriteReq_hits::cpu0 1158 # number of WriteReq hits +system.cpu0.l1c.WriteReq_hits::total 1158 # number of WriteReq hits +system.cpu0.l1c.demand_hits::cpu0 9887 # number of demand (read+write) hits +system.cpu0.l1c.demand_hits::total 9887 # number of demand (read+write) hits +system.cpu0.l1c.overall_hits::cpu0 9887 # number of overall hits +system.cpu0.l1c.overall_hits::total 9887 # number of overall hits +system.cpu0.l1c.ReadReq_misses::cpu0 36226 # number of ReadReq misses +system.cpu0.l1c.ReadReq_misses::total 36226 # number of ReadReq misses +system.cpu0.l1c.WriteReq_misses::cpu0 24124 # number of WriteReq misses +system.cpu0.l1c.WriteReq_misses::total 24124 # number of WriteReq misses +system.cpu0.l1c.demand_misses::cpu0 60350 # number of demand (read+write) misses +system.cpu0.l1c.demand_misses::total 60350 # number of demand (read+write) misses +system.cpu0.l1c.overall_misses::cpu0 60350 # number of overall misses +system.cpu0.l1c.overall_misses::total 60350 # number of overall misses +system.cpu0.l1c.ReadReq_miss_latency::cpu0 712731918 # number of ReadReq miss cycles +system.cpu0.l1c.ReadReq_miss_latency::total 712731918 # number of ReadReq miss cycles +system.cpu0.l1c.WriteReq_miss_latency::cpu0 593276823 # number of WriteReq miss cycles +system.cpu0.l1c.WriteReq_miss_latency::total 593276823 # number of WriteReq miss cycles +system.cpu0.l1c.demand_miss_latency::cpu0 1306008741 # number of demand (read+write) miss cycles +system.cpu0.l1c.demand_miss_latency::total 1306008741 # number of demand (read+write) miss cycles +system.cpu0.l1c.overall_miss_latency::cpu0 1306008741 # number of overall miss cycles +system.cpu0.l1c.overall_miss_latency::total 1306008741 # number of overall miss cycles +system.cpu0.l1c.ReadReq_accesses::cpu0 44955 # number of ReadReq accesses(hits+misses) +system.cpu0.l1c.ReadReq_accesses::total 44955 # number of ReadReq accesses(hits+misses) +system.cpu0.l1c.WriteReq_accesses::cpu0 25282 # number of WriteReq accesses(hits+misses) +system.cpu0.l1c.WriteReq_accesses::total 25282 # number of WriteReq accesses(hits+misses) +system.cpu0.l1c.demand_accesses::cpu0 70237 # number of demand (read+write) accesses +system.cpu0.l1c.demand_accesses::total 70237 # number of demand (read+write) accesses +system.cpu0.l1c.overall_accesses::cpu0 70237 # number of overall (read+write) accesses +system.cpu0.l1c.overall_accesses::total 70237 # number of overall (read+write) accesses +system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.805828 # miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_miss_rate::total 0.805828 # miss rate for ReadReq accesses +system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.954197 # miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_miss_rate::total 0.954197 # miss rate for WriteReq accesses +system.cpu0.l1c.demand_miss_rate::cpu0 0.859234 # miss rate for demand accesses +system.cpu0.l1c.demand_miss_rate::total 0.859234 # miss rate for demand accesses +system.cpu0.l1c.overall_miss_rate::cpu0 0.859234 # miss rate for overall accesses +system.cpu0.l1c.overall_miss_rate::total 0.859234 # miss rate for overall accesses +system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 19674.596091 # average ReadReq miss latency +system.cpu0.l1c.ReadReq_avg_miss_latency::total 19674.596091 # average ReadReq miss latency +system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 24592.804800 # average WriteReq miss latency +system.cpu0.l1c.WriteReq_avg_miss_latency::total 24592.804800 # average WriteReq miss latency +system.cpu0.l1c.demand_avg_miss_latency::cpu0 21640.575659 # average overall miss latency +system.cpu0.l1c.demand_avg_miss_latency::total 21640.575659 # average overall miss latency +system.cpu0.l1c.overall_avg_miss_latency::cpu0 21640.575659 # average overall miss latency +system.cpu0.l1c.overall_avg_miss_latency::total 21640.575659 # average overall miss latency +system.cpu0.l1c.blocked_cycles::no_mshrs 872655 # number of cycles access was blocked system.cpu0.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.l1c.blocked::no_mshrs 65942 # number of cycles access was blocked +system.cpu0.l1c.blocked::no_mshrs 66710 # number of cycles access was blocked system.cpu0.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.l1c.avg_blocked_cycles::no_mshrs 12.144946 # average number of cycles each access was blocked +system.cpu0.l1c.avg_blocked_cycles::no_mshrs 13.081322 # average number of cycles each access was blocked system.cpu0.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.l1c.writebacks::writebacks 10055 # number of writebacks -system.cpu0.l1c.writebacks::total 10055 # number of writebacks -system.cpu0.l1c.ReadReq_mshr_misses::cpu0 36720 # number of ReadReq MSHR misses -system.cpu0.l1c.ReadReq_mshr_misses::total 36720 # number of ReadReq MSHR misses -system.cpu0.l1c.WriteReq_mshr_misses::cpu0 24041 # number of WriteReq MSHR misses -system.cpu0.l1c.WriteReq_mshr_misses::total 24041 # number of WriteReq MSHR misses -system.cpu0.l1c.demand_mshr_misses::cpu0 60761 # number of demand (read+write) MSHR misses -system.cpu0.l1c.demand_mshr_misses::total 60761 # number of demand (read+write) MSHR misses -system.cpu0.l1c.overall_mshr_misses::cpu0 60761 # number of overall MSHR misses -system.cpu0.l1c.overall_mshr_misses::total 60761 # number of overall MSHR misses -system.cpu0.l1c.ReadReq_mshr_uncacheable::cpu0 9743 # number of ReadReq MSHR uncacheable -system.cpu0.l1c.ReadReq_mshr_uncacheable::total 9743 # number of ReadReq MSHR uncacheable -system.cpu0.l1c.WriteReq_mshr_uncacheable::cpu0 5400 # number of WriteReq MSHR uncacheable -system.cpu0.l1c.WriteReq_mshr_uncacheable::total 5400 # number of WriteReq MSHR uncacheable -system.cpu0.l1c.overall_mshr_uncacheable_misses::cpu0 15143 # number of overall MSHR uncacheable misses -system.cpu0.l1c.overall_mshr_uncacheable_misses::total 15143 # number of overall MSHR uncacheable misses -system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0 640619671 # number of ReadReq MSHR miss cycles -system.cpu0.l1c.ReadReq_mshr_miss_latency::total 640619671 # number of ReadReq MSHR miss cycles -system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0 540167136 # number of WriteReq MSHR miss cycles -system.cpu0.l1c.WriteReq_mshr_miss_latency::total 540167136 # number of WriteReq MSHR miss cycles -system.cpu0.l1c.demand_mshr_miss_latency::cpu0 1180786807 # number of demand (read+write) MSHR miss cycles -system.cpu0.l1c.demand_mshr_miss_latency::total 1180786807 # number of demand (read+write) MSHR miss cycles -system.cpu0.l1c.overall_mshr_miss_latency::cpu0 1180786807 # number of overall MSHR miss cycles -system.cpu0.l1c.overall_mshr_miss_latency::total 1180786807 # number of overall MSHR miss cycles -system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 730760811 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 730760811 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 730760811 # number of overall MSHR uncacheable cycles -system.cpu0.l1c.overall_mshr_uncacheable_latency::total 730760811 # number of overall MSHR uncacheable cycles -system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.805016 # mshr miss rate for ReadReq accesses -system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.805016 # mshr miss rate for ReadReq accesses -system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.950162 # mshr miss rate for WriteReq accesses -system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.950162 # mshr miss rate for WriteReq accesses -system.cpu0.l1c.demand_mshr_miss_rate::cpu0 0.856802 # mshr miss rate for demand accesses -system.cpu0.l1c.demand_mshr_miss_rate::total 0.856802 # mshr miss rate for demand accesses -system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.856802 # mshr miss rate for overall accesses -system.cpu0.l1c.overall_mshr_miss_rate::total 0.856802 # mshr miss rate for overall accesses -system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 17446.069472 # average ReadReq mshr miss latency -system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 17446.069472 # average ReadReq mshr miss latency -system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 22468.580176 # average WriteReq mshr miss latency -system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 22468.580176 # average WriteReq mshr miss latency -system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 19433.301081 # average overall mshr miss latency -system.cpu0.l1c.demand_avg_mshr_miss_latency::total 19433.301081 # average overall mshr miss latency -system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 19433.301081 # average overall mshr miss latency -system.cpu0.l1c.overall_avg_mshr_miss_latency::total 19433.301081 # average overall mshr miss latency -system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0 75003.675562 # average ReadReq mshr uncacheable latency -system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total 75003.675562 # average ReadReq mshr uncacheable latency -system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 48257.334148 # average overall mshr uncacheable latency -system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total 48257.334148 # average overall mshr uncacheable latency -system.cpu1.pwrStateResidencyTicks::UNDEFINED 500337000 # Cumulative time (in ticks) in various power states -system.cpu1.num_reads 99552 # number of read accesses completed -system.cpu1.num_writes 55243 # number of write accesses completed -system.cpu1.l1c.tags.pwrStateResidencyTicks::UNDEFINED 500337000 # Cumulative time (in ticks) in various power states -system.cpu1.l1c.tags.replacements 22440 # number of replacements -system.cpu1.l1c.tags.tagsinuse 392.475962 # Cycle average of tags in use -system.cpu1.l1c.tags.total_refs 13641 # Total number of references to valid blocks. -system.cpu1.l1c.tags.sampled_refs 22851 # Sample count of references to valid blocks. -system.cpu1.l1c.tags.avg_refs 0.596954 # Average number of references to valid blocks. +system.cpu0.l1c.writebacks::writebacks 9923 # number of writebacks +system.cpu0.l1c.writebacks::total 9923 # number of writebacks +system.cpu0.l1c.ReadReq_mshr_misses::cpu0 36226 # number of ReadReq MSHR misses +system.cpu0.l1c.ReadReq_mshr_misses::total 36226 # number of ReadReq MSHR misses +system.cpu0.l1c.WriteReq_mshr_misses::cpu0 24124 # number of WriteReq MSHR misses +system.cpu0.l1c.WriteReq_mshr_misses::total 24124 # number of WriteReq MSHR misses +system.cpu0.l1c.demand_mshr_misses::cpu0 60350 # number of demand (read+write) MSHR misses +system.cpu0.l1c.demand_mshr_misses::total 60350 # number of demand (read+write) MSHR misses +system.cpu0.l1c.overall_mshr_misses::cpu0 60350 # number of overall MSHR misses +system.cpu0.l1c.overall_mshr_misses::total 60350 # number of overall MSHR misses +system.cpu0.l1c.ReadReq_mshr_uncacheable::cpu0 9863 # number of ReadReq MSHR uncacheable +system.cpu0.l1c.ReadReq_mshr_uncacheable::total 9863 # number of ReadReq MSHR uncacheable +system.cpu0.l1c.WriteReq_mshr_uncacheable::cpu0 5414 # number of WriteReq MSHR uncacheable +system.cpu0.l1c.WriteReq_mshr_uncacheable::total 5414 # number of WriteReq MSHR uncacheable +system.cpu0.l1c.overall_mshr_uncacheable_misses::cpu0 15277 # number of overall MSHR uncacheable misses +system.cpu0.l1c.overall_mshr_uncacheable_misses::total 15277 # number of overall MSHR uncacheable misses +system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0 676507918 # number of ReadReq MSHR miss cycles +system.cpu0.l1c.ReadReq_mshr_miss_latency::total 676507918 # number of ReadReq MSHR miss cycles +system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0 569152823 # number of WriteReq MSHR miss cycles +system.cpu0.l1c.WriteReq_mshr_miss_latency::total 569152823 # number of WriteReq MSHR miss cycles +system.cpu0.l1c.demand_mshr_miss_latency::cpu0 1245660741 # number of demand (read+write) MSHR miss cycles +system.cpu0.l1c.demand_mshr_miss_latency::total 1245660741 # number of demand (read+write) MSHR miss cycles +system.cpu0.l1c.overall_mshr_miss_latency::cpu0 1245660741 # number of overall MSHR miss cycles +system.cpu0.l1c.overall_mshr_miss_latency::total 1245660741 # number of overall MSHR miss cycles +system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 770027425 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 770027425 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 770027425 # number of overall MSHR uncacheable cycles +system.cpu0.l1c.overall_mshr_uncacheable_latency::total 770027425 # number of overall MSHR uncacheable cycles +system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.805828 # mshr miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.805828 # mshr miss rate for ReadReq accesses +system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.954197 # mshr miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.954197 # mshr miss rate for WriteReq accesses +system.cpu0.l1c.demand_mshr_miss_rate::cpu0 0.859234 # mshr miss rate for demand accesses +system.cpu0.l1c.demand_mshr_miss_rate::total 0.859234 # mshr miss rate for demand accesses +system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.859234 # mshr miss rate for overall accesses +system.cpu0.l1c.overall_mshr_miss_rate::total 0.859234 # mshr miss rate for overall accesses +system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 18674.651300 # average ReadReq mshr miss latency +system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 18674.651300 # average ReadReq mshr miss latency +system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 23592.804800 # average WriteReq mshr miss latency +system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 23592.804800 # average WriteReq mshr miss latency +system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 20640.608799 # average overall mshr miss latency +system.cpu0.l1c.demand_avg_mshr_miss_latency::total 20640.608799 # average overall mshr miss latency +system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 20640.608799 # average overall mshr miss latency +system.cpu0.l1c.overall_avg_mshr_miss_latency::total 20640.608799 # average overall mshr miss latency +system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0 78072.333469 # average ReadReq mshr uncacheable latency +system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total 78072.333469 # average ReadReq mshr uncacheable latency +system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 50404.361131 # average overall mshr uncacheable latency +system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total 50404.361131 # average overall mshr uncacheable latency +system.cpu1.pwrStateResidencyTicks::UNDEFINED 521659000 # Cumulative time (in ticks) in various power states +system.cpu1.num_reads 99894 # number of read accesses completed +system.cpu1.num_writes 55231 # number of write accesses completed +system.cpu1.l1c.tags.pwrStateResidencyTicks::UNDEFINED 521659000 # Cumulative time (in ticks) in various power states +system.cpu1.l1c.tags.replacements 22436 # number of replacements +system.cpu1.l1c.tags.tagsinuse 391.315294 # Cycle average of tags in use +system.cpu1.l1c.tags.total_refs 13542 # Total number of references to valid blocks. +system.cpu1.l1c.tags.sampled_refs 22813 # Sample count of references to valid blocks. +system.cpu1.l1c.tags.avg_refs 0.593609 # Average number of references to valid blocks. system.cpu1.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l1c.tags.occ_blocks::cpu1 392.475962 # Average occupied blocks per requestor -system.cpu1.l1c.tags.occ_percent::cpu1 0.766555 # Average percentage of cache occupancy -system.cpu1.l1c.tags.occ_percent::total 0.766555 # Average percentage of cache occupancy -system.cpu1.l1c.tags.occ_task_id_blocks::1024 411 # Occupied blocks per task id -system.cpu1.l1c.tags.age_task_id_blocks_1024::0 399 # Occupied blocks per task id -system.cpu1.l1c.tags.age_task_id_blocks_1024::1 12 # Occupied blocks per task id -system.cpu1.l1c.tags.occ_task_id_percent::1024 0.802734 # Percentage of cache occupancy per task id -system.cpu1.l1c.tags.tag_accesses 339640 # Number of tag accesses -system.cpu1.l1c.tags.data_accesses 339640 # Number of data accesses -system.cpu1.l1c.pwrStateResidencyTicks::UNDEFINED 500337000 # Cumulative time (in ticks) in various power states -system.cpu1.l1c.ReadReq_hits::cpu1 8906 # number of ReadReq hits -system.cpu1.l1c.ReadReq_hits::total 8906 # number of ReadReq hits -system.cpu1.l1c.WriteReq_hits::cpu1 1136 # number of WriteReq hits -system.cpu1.l1c.WriteReq_hits::total 1136 # number of WriteReq hits -system.cpu1.l1c.demand_hits::cpu1 10042 # number of demand (read+write) hits -system.cpu1.l1c.demand_hits::total 10042 # number of demand (read+write) hits -system.cpu1.l1c.overall_hits::cpu1 10042 # number of overall hits -system.cpu1.l1c.overall_hits::total 10042 # number of overall hits -system.cpu1.l1c.ReadReq_misses::cpu1 36595 # number of ReadReq misses -system.cpu1.l1c.ReadReq_misses::total 36595 # number of ReadReq misses -system.cpu1.l1c.WriteReq_misses::cpu1 24033 # number of WriteReq misses -system.cpu1.l1c.WriteReq_misses::total 24033 # number of WriteReq misses -system.cpu1.l1c.demand_misses::cpu1 60628 # number of demand (read+write) misses -system.cpu1.l1c.demand_misses::total 60628 # number of demand (read+write) misses -system.cpu1.l1c.overall_misses::cpu1 60628 # number of overall misses -system.cpu1.l1c.overall_misses::total 60628 # number of overall misses -system.cpu1.l1c.ReadReq_miss_latency::cpu1 675076804 # number of ReadReq miss cycles -system.cpu1.l1c.ReadReq_miss_latency::total 675076804 # number of ReadReq miss cycles -system.cpu1.l1c.WriteReq_miss_latency::cpu1 561344066 # number of WriteReq miss cycles -system.cpu1.l1c.WriteReq_miss_latency::total 561344066 # number of WriteReq miss cycles -system.cpu1.l1c.demand_miss_latency::cpu1 1236420870 # number of demand (read+write) miss cycles -system.cpu1.l1c.demand_miss_latency::total 1236420870 # number of demand (read+write) miss cycles -system.cpu1.l1c.overall_miss_latency::cpu1 1236420870 # number of overall miss cycles -system.cpu1.l1c.overall_miss_latency::total 1236420870 # number of overall miss cycles -system.cpu1.l1c.ReadReq_accesses::cpu1 45501 # number of ReadReq accesses(hits+misses) -system.cpu1.l1c.ReadReq_accesses::total 45501 # number of ReadReq accesses(hits+misses) -system.cpu1.l1c.WriteReq_accesses::cpu1 25169 # number of WriteReq accesses(hits+misses) -system.cpu1.l1c.WriteReq_accesses::total 25169 # number of WriteReq accesses(hits+misses) -system.cpu1.l1c.demand_accesses::cpu1 70670 # number of demand (read+write) accesses -system.cpu1.l1c.demand_accesses::total 70670 # number of demand (read+write) accesses -system.cpu1.l1c.overall_accesses::cpu1 70670 # number of overall (read+write) accesses -system.cpu1.l1c.overall_accesses::total 70670 # number of overall (read+write) accesses -system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.804268 # miss rate for ReadReq accesses -system.cpu1.l1c.ReadReq_miss_rate::total 0.804268 # miss rate for ReadReq accesses -system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.954865 # miss rate for WriteReq accesses -system.cpu1.l1c.WriteReq_miss_rate::total 0.954865 # miss rate for WriteReq accesses -system.cpu1.l1c.demand_miss_rate::cpu1 0.857903 # miss rate for demand accesses -system.cpu1.l1c.demand_miss_rate::total 0.857903 # miss rate for demand accesses -system.cpu1.l1c.overall_miss_rate::cpu1 0.857903 # miss rate for overall accesses -system.cpu1.l1c.overall_miss_rate::total 0.857903 # miss rate for overall accesses -system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 18447.241536 # average ReadReq miss latency -system.cpu1.l1c.ReadReq_avg_miss_latency::total 18447.241536 # average ReadReq miss latency -system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 23357.219906 # average WriteReq miss latency -system.cpu1.l1c.WriteReq_avg_miss_latency::total 23357.219906 # average WriteReq miss latency -system.cpu1.l1c.demand_avg_miss_latency::cpu1 20393.561886 # average overall miss latency -system.cpu1.l1c.demand_avg_miss_latency::total 20393.561886 # average overall miss latency -system.cpu1.l1c.overall_avg_miss_latency::cpu1 20393.561886 # average overall miss latency -system.cpu1.l1c.overall_avg_miss_latency::total 20393.561886 # average overall miss latency -system.cpu1.l1c.blocked_cycles::no_mshrs 800224 # number of cycles access was blocked +system.cpu1.l1c.tags.occ_blocks::cpu1 391.315294 # Average occupied blocks per requestor +system.cpu1.l1c.tags.occ_percent::cpu1 0.764288 # Average percentage of cache occupancy +system.cpu1.l1c.tags.occ_percent::total 0.764288 # Average percentage of cache occupancy +system.cpu1.l1c.tags.occ_task_id_blocks::1024 377 # Occupied blocks per task id +system.cpu1.l1c.tags.age_task_id_blocks_1024::0 366 # Occupied blocks per task id +system.cpu1.l1c.tags.age_task_id_blocks_1024::1 11 # Occupied blocks per task id +system.cpu1.l1c.tags.occ_task_id_percent::1024 0.736328 # Percentage of cache occupancy per task id +system.cpu1.l1c.tags.tag_accesses 338824 # Number of tag accesses +system.cpu1.l1c.tags.data_accesses 338824 # Number of data accesses +system.cpu1.l1c.pwrStateResidencyTicks::UNDEFINED 521659000 # Cumulative time (in ticks) in various power states +system.cpu1.l1c.ReadReq_hits::cpu1 8855 # number of ReadReq hits +system.cpu1.l1c.ReadReq_hits::total 8855 # number of ReadReq hits +system.cpu1.l1c.WriteReq_hits::cpu1 1149 # number of WriteReq hits +system.cpu1.l1c.WriteReq_hits::total 1149 # number of WriteReq hits +system.cpu1.l1c.demand_hits::cpu1 10004 # number of demand (read+write) hits +system.cpu1.l1c.demand_hits::total 10004 # number of demand (read+write) hits +system.cpu1.l1c.overall_hits::cpu1 10004 # number of overall hits +system.cpu1.l1c.overall_hits::total 10004 # number of overall hits +system.cpu1.l1c.ReadReq_misses::cpu1 36651 # number of ReadReq misses +system.cpu1.l1c.ReadReq_misses::total 36651 # number of ReadReq misses +system.cpu1.l1c.WriteReq_misses::cpu1 23831 # number of WriteReq misses +system.cpu1.l1c.WriteReq_misses::total 23831 # number of WriteReq misses +system.cpu1.l1c.demand_misses::cpu1 60482 # number of demand (read+write) misses +system.cpu1.l1c.demand_misses::total 60482 # number of demand (read+write) misses +system.cpu1.l1c.overall_misses::cpu1 60482 # number of overall misses +system.cpu1.l1c.overall_misses::total 60482 # number of overall misses +system.cpu1.l1c.ReadReq_miss_latency::cpu1 724296905 # number of ReadReq miss cycles +system.cpu1.l1c.ReadReq_miss_latency::total 724296905 # number of ReadReq miss cycles +system.cpu1.l1c.WriteReq_miss_latency::cpu1 578481683 # number of WriteReq miss cycles +system.cpu1.l1c.WriteReq_miss_latency::total 578481683 # number of WriteReq miss cycles +system.cpu1.l1c.demand_miss_latency::cpu1 1302778588 # number of demand (read+write) miss cycles +system.cpu1.l1c.demand_miss_latency::total 1302778588 # number of demand (read+write) miss cycles +system.cpu1.l1c.overall_miss_latency::cpu1 1302778588 # number of overall miss cycles +system.cpu1.l1c.overall_miss_latency::total 1302778588 # number of overall miss cycles +system.cpu1.l1c.ReadReq_accesses::cpu1 45506 # number of ReadReq accesses(hits+misses) +system.cpu1.l1c.ReadReq_accesses::total 45506 # number of ReadReq accesses(hits+misses) +system.cpu1.l1c.WriteReq_accesses::cpu1 24980 # number of WriteReq accesses(hits+misses) +system.cpu1.l1c.WriteReq_accesses::total 24980 # number of WriteReq accesses(hits+misses) +system.cpu1.l1c.demand_accesses::cpu1 70486 # number of demand (read+write) accesses +system.cpu1.l1c.demand_accesses::total 70486 # number of demand (read+write) accesses +system.cpu1.l1c.overall_accesses::cpu1 70486 # number of overall (read+write) accesses +system.cpu1.l1c.overall_accesses::total 70486 # number of overall (read+write) accesses +system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.805410 # miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_miss_rate::total 0.805410 # miss rate for ReadReq accesses +system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.954003 # miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_miss_rate::total 0.954003 # miss rate for WriteReq accesses +system.cpu1.l1c.demand_miss_rate::cpu1 0.858071 # miss rate for demand accesses +system.cpu1.l1c.demand_miss_rate::total 0.858071 # miss rate for demand accesses +system.cpu1.l1c.overall_miss_rate::cpu1 0.858071 # miss rate for overall accesses +system.cpu1.l1c.overall_miss_rate::total 0.858071 # miss rate for overall accesses +system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 19761.995716 # average ReadReq miss latency +system.cpu1.l1c.ReadReq_avg_miss_latency::total 19761.995716 # average ReadReq miss latency +system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 24274.335236 # average WriteReq miss latency +system.cpu1.l1c.WriteReq_avg_miss_latency::total 24274.335236 # average WriteReq miss latency +system.cpu1.l1c.demand_avg_miss_latency::cpu1 21539.938957 # average overall miss latency +system.cpu1.l1c.demand_avg_miss_latency::total 21539.938957 # average overall miss latency +system.cpu1.l1c.overall_avg_miss_latency::cpu1 21539.938957 # average overall miss latency +system.cpu1.l1c.overall_avg_miss_latency::total 21539.938957 # average overall miss latency +system.cpu1.l1c.blocked_cycles::no_mshrs 869423 # number of cycles access was blocked system.cpu1.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.l1c.blocked::no_mshrs 65844 # number of cycles access was blocked +system.cpu1.l1c.blocked::no_mshrs 66885 # number of cycles access was blocked system.cpu1.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.l1c.avg_blocked_cycles::no_mshrs 12.153332 # average number of cycles each access was blocked +system.cpu1.l1c.avg_blocked_cycles::no_mshrs 12.998774 # average number of cycles each access was blocked system.cpu1.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.l1c.writebacks::writebacks 9864 # number of writebacks -system.cpu1.l1c.writebacks::total 9864 # number of writebacks -system.cpu1.l1c.ReadReq_mshr_misses::cpu1 36595 # number of ReadReq MSHR misses -system.cpu1.l1c.ReadReq_mshr_misses::total 36595 # number of ReadReq MSHR misses -system.cpu1.l1c.WriteReq_mshr_misses::cpu1 24033 # number of WriteReq MSHR misses -system.cpu1.l1c.WriteReq_mshr_misses::total 24033 # number of WriteReq MSHR misses -system.cpu1.l1c.demand_mshr_misses::cpu1 60628 # number of demand (read+write) MSHR misses -system.cpu1.l1c.demand_mshr_misses::total 60628 # number of demand (read+write) MSHR misses -system.cpu1.l1c.overall_mshr_misses::cpu1 60628 # number of overall MSHR misses -system.cpu1.l1c.overall_mshr_misses::total 60628 # number of overall MSHR misses -system.cpu1.l1c.ReadReq_mshr_uncacheable::cpu1 9811 # number of ReadReq MSHR uncacheable -system.cpu1.l1c.ReadReq_mshr_uncacheable::total 9811 # number of ReadReq MSHR uncacheable -system.cpu1.l1c.WriteReq_mshr_uncacheable::cpu1 5468 # number of WriteReq MSHR uncacheable -system.cpu1.l1c.WriteReq_mshr_uncacheable::total 5468 # number of WriteReq MSHR uncacheable -system.cpu1.l1c.overall_mshr_uncacheable_misses::cpu1 15279 # number of overall MSHR uncacheable misses -system.cpu1.l1c.overall_mshr_uncacheable_misses::total 15279 # number of overall MSHR uncacheable misses -system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1 638481804 # number of ReadReq MSHR miss cycles -system.cpu1.l1c.ReadReq_mshr_miss_latency::total 638481804 # number of ReadReq MSHR miss cycles -system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 537312066 # number of WriteReq MSHR miss cycles -system.cpu1.l1c.WriteReq_mshr_miss_latency::total 537312066 # number of WriteReq MSHR miss cycles -system.cpu1.l1c.demand_mshr_miss_latency::cpu1 1175793870 # number of demand (read+write) MSHR miss cycles -system.cpu1.l1c.demand_mshr_miss_latency::total 1175793870 # number of demand (read+write) MSHR miss cycles -system.cpu1.l1c.overall_mshr_miss_latency::cpu1 1175793870 # number of overall MSHR miss cycles -system.cpu1.l1c.overall_mshr_miss_latency::total 1175793870 # number of overall MSHR miss cycles -system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 734637731 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 734637731 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 734637731 # number of overall MSHR uncacheable cycles -system.cpu1.l1c.overall_mshr_uncacheable_latency::total 734637731 # number of overall MSHR uncacheable cycles -system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.804268 # mshr miss rate for ReadReq accesses -system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.804268 # mshr miss rate for ReadReq accesses -system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.954865 # mshr miss rate for WriteReq accesses -system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.954865 # mshr miss rate for WriteReq accesses -system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.857903 # mshr miss rate for demand accesses -system.cpu1.l1c.demand_mshr_miss_rate::total 0.857903 # mshr miss rate for demand accesses -system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.857903 # mshr miss rate for overall accesses -system.cpu1.l1c.overall_mshr_miss_rate::total 0.857903 # mshr miss rate for overall accesses -system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 17447.241536 # average ReadReq mshr miss latency -system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 17447.241536 # average ReadReq mshr miss latency -system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 22357.261515 # average WriteReq mshr miss latency -system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 22357.261515 # average WriteReq mshr miss latency -system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 19393.578380 # average overall mshr miss latency -system.cpu1.l1c.demand_avg_mshr_miss_latency::total 19393.578380 # average overall mshr miss latency -system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 19393.578380 # average overall mshr miss latency -system.cpu1.l1c.overall_avg_mshr_miss_latency::total 19393.578380 # average overall mshr miss latency -system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 74878.985934 # average ReadReq mshr uncacheable latency -system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total 74878.985934 # average ReadReq mshr uncacheable latency -system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 48081.532234 # average overall mshr uncacheable latency -system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total 48081.532234 # average overall mshr uncacheable latency -system.cpu2.pwrStateResidencyTicks::UNDEFINED 500337000 # Cumulative time (in ticks) in various power states -system.cpu2.num_reads 100001 # number of read accesses completed -system.cpu2.num_writes 55556 # number of write accesses completed -system.cpu2.l1c.tags.pwrStateResidencyTicks::UNDEFINED 500337000 # Cumulative time (in ticks) in various power states -system.cpu2.l1c.tags.replacements 22129 # number of replacements -system.cpu2.l1c.tags.tagsinuse 390.469202 # Cycle average of tags in use -system.cpu2.l1c.tags.total_refs 13617 # Total number of references to valid blocks. -system.cpu2.l1c.tags.sampled_refs 22527 # Sample count of references to valid blocks. -system.cpu2.l1c.tags.avg_refs 0.604475 # Average number of references to valid blocks. +system.cpu1.l1c.writebacks::writebacks 9819 # number of writebacks +system.cpu1.l1c.writebacks::total 9819 # number of writebacks +system.cpu1.l1c.ReadReq_mshr_misses::cpu1 36651 # number of ReadReq MSHR misses +system.cpu1.l1c.ReadReq_mshr_misses::total 36651 # number of ReadReq MSHR misses +system.cpu1.l1c.WriteReq_mshr_misses::cpu1 23831 # number of WriteReq MSHR misses +system.cpu1.l1c.WriteReq_mshr_misses::total 23831 # number of WriteReq MSHR misses +system.cpu1.l1c.demand_mshr_misses::cpu1 60482 # number of demand (read+write) MSHR misses +system.cpu1.l1c.demand_mshr_misses::total 60482 # number of demand (read+write) MSHR misses +system.cpu1.l1c.overall_mshr_misses::cpu1 60482 # number of overall MSHR misses +system.cpu1.l1c.overall_mshr_misses::total 60482 # number of overall MSHR misses +system.cpu1.l1c.ReadReq_mshr_uncacheable::cpu1 9872 # number of ReadReq MSHR uncacheable +system.cpu1.l1c.ReadReq_mshr_uncacheable::total 9872 # number of ReadReq MSHR uncacheable +system.cpu1.l1c.WriteReq_mshr_uncacheable::cpu1 5469 # number of WriteReq MSHR uncacheable +system.cpu1.l1c.WriteReq_mshr_uncacheable::total 5469 # number of WriteReq MSHR uncacheable +system.cpu1.l1c.overall_mshr_uncacheable_misses::cpu1 15341 # number of overall MSHR uncacheable misses +system.cpu1.l1c.overall_mshr_uncacheable_misses::total 15341 # number of overall MSHR uncacheable misses +system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1 687646905 # number of ReadReq MSHR miss cycles +system.cpu1.l1c.ReadReq_mshr_miss_latency::total 687646905 # number of ReadReq MSHR miss cycles +system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 554650683 # number of WriteReq MSHR miss cycles +system.cpu1.l1c.WriteReq_mshr_miss_latency::total 554650683 # number of WriteReq MSHR miss cycles +system.cpu1.l1c.demand_mshr_miss_latency::cpu1 1242297588 # number of demand (read+write) MSHR miss cycles +system.cpu1.l1c.demand_mshr_miss_latency::total 1242297588 # number of demand (read+write) MSHR miss cycles +system.cpu1.l1c.overall_mshr_miss_latency::cpu1 1242297588 # number of overall MSHR miss cycles +system.cpu1.l1c.overall_mshr_miss_latency::total 1242297588 # number of overall MSHR miss cycles +system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 771585814 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 771585814 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 771585814 # number of overall MSHR uncacheable cycles +system.cpu1.l1c.overall_mshr_uncacheable_latency::total 771585814 # number of overall MSHR uncacheable cycles +system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.805410 # mshr miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.805410 # mshr miss rate for ReadReq accesses +system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.954003 # mshr miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.954003 # mshr miss rate for WriteReq accesses +system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.858071 # mshr miss rate for demand accesses +system.cpu1.l1c.demand_mshr_miss_rate::total 0.858071 # mshr miss rate for demand accesses +system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.858071 # mshr miss rate for overall accesses +system.cpu1.l1c.overall_mshr_miss_rate::total 0.858071 # mshr miss rate for overall accesses +system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 18762.023001 # average ReadReq mshr miss latency +system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 18762.023001 # average ReadReq mshr miss latency +system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 23274.335236 # average WriteReq mshr miss latency +system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 23274.335236 # average WriteReq mshr miss latency +system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 20539.955491 # average overall mshr miss latency +system.cpu1.l1c.demand_avg_mshr_miss_latency::total 20539.955491 # average overall mshr miss latency +system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 20539.955491 # average overall mshr miss latency +system.cpu1.l1c.overall_avg_mshr_miss_latency::total 20539.955491 # average overall mshr miss latency +system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 78159.016815 # average ReadReq mshr uncacheable latency +system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total 78159.016815 # average ReadReq mshr uncacheable latency +system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 50295.666123 # average overall mshr uncacheable latency +system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total 50295.666123 # average overall mshr uncacheable latency +system.cpu2.pwrStateResidencyTicks::UNDEFINED 521659000 # Cumulative time (in ticks) in various power states +system.cpu2.num_reads 99314 # number of read accesses completed +system.cpu2.num_writes 55477 # number of write accesses completed +system.cpu2.l1c.tags.pwrStateResidencyTicks::UNDEFINED 521659000 # Cumulative time (in ticks) in various power states +system.cpu2.l1c.tags.replacements 22237 # number of replacements +system.cpu2.l1c.tags.tagsinuse 390.931192 # Cycle average of tags in use +system.cpu2.l1c.tags.total_refs 13493 # Total number of references to valid blocks. +system.cpu2.l1c.tags.sampled_refs 22636 # Sample count of references to valid blocks. +system.cpu2.l1c.tags.avg_refs 0.596086 # Average number of references to valid blocks. system.cpu2.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.l1c.tags.occ_blocks::cpu2 390.469202 # Average occupied blocks per requestor -system.cpu2.l1c.tags.occ_percent::cpu2 0.762635 # Average percentage of cache occupancy -system.cpu2.l1c.tags.occ_percent::total 0.762635 # Average percentage of cache occupancy -system.cpu2.l1c.tags.occ_task_id_blocks::1024 398 # Occupied blocks per task id -system.cpu2.l1c.tags.age_task_id_blocks_1024::0 390 # Occupied blocks per task id -system.cpu2.l1c.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id -system.cpu2.l1c.tags.occ_task_id_percent::1024 0.777344 # Percentage of cache occupancy per task id -system.cpu2.l1c.tags.tag_accesses 339163 # Number of tag accesses -system.cpu2.l1c.tags.data_accesses 339163 # Number of data accesses -system.cpu2.l1c.pwrStateResidencyTicks::UNDEFINED 500337000 # Cumulative time (in ticks) in various power states -system.cpu2.l1c.ReadReq_hits::cpu2 8741 # number of ReadReq hits -system.cpu2.l1c.ReadReq_hits::total 8741 # number of ReadReq hits -system.cpu2.l1c.WriteReq_hits::cpu2 1177 # number of WriteReq hits -system.cpu2.l1c.WriteReq_hits::total 1177 # number of WriteReq hits -system.cpu2.l1c.demand_hits::cpu2 9918 # number of demand (read+write) hits -system.cpu2.l1c.demand_hits::total 9918 # number of demand (read+write) hits -system.cpu2.l1c.overall_hits::cpu2 9918 # number of overall hits -system.cpu2.l1c.overall_hits::total 9918 # number of overall hits -system.cpu2.l1c.ReadReq_misses::cpu2 36520 # number of ReadReq misses -system.cpu2.l1c.ReadReq_misses::total 36520 # number of ReadReq misses +system.cpu2.l1c.tags.occ_blocks::cpu2 390.931192 # Average occupied blocks per requestor +system.cpu2.l1c.tags.occ_percent::cpu2 0.763537 # Average percentage of cache occupancy +system.cpu2.l1c.tags.occ_percent::total 0.763537 # Average percentage of cache occupancy +system.cpu2.l1c.tags.occ_task_id_blocks::1024 399 # Occupied blocks per task id +system.cpu2.l1c.tags.age_task_id_blocks_1024::0 379 # Occupied blocks per task id +system.cpu2.l1c.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id +system.cpu2.l1c.tags.occ_task_id_percent::1024 0.779297 # Percentage of cache occupancy per task id +system.cpu2.l1c.tags.tag_accesses 337492 # Number of tag accesses +system.cpu2.l1c.tags.data_accesses 337492 # Number of data accesses +system.cpu2.l1c.pwrStateResidencyTicks::UNDEFINED 521659000 # Cumulative time (in ticks) in various power states +system.cpu2.l1c.ReadReq_hits::cpu2 8705 # number of ReadReq hits +system.cpu2.l1c.ReadReq_hits::total 8705 # number of ReadReq hits +system.cpu2.l1c.WriteReq_hits::cpu2 1188 # number of WriteReq hits +system.cpu2.l1c.WriteReq_hits::total 1188 # number of WriteReq hits +system.cpu2.l1c.demand_hits::cpu2 9893 # number of demand (read+write) hits +system.cpu2.l1c.demand_hits::total 9893 # number of demand (read+write) hits +system.cpu2.l1c.overall_hits::cpu2 9893 # number of overall hits +system.cpu2.l1c.overall_hits::total 9893 # number of overall hits +system.cpu2.l1c.ReadReq_misses::cpu2 36190 # number of ReadReq misses +system.cpu2.l1c.ReadReq_misses::total 36190 # number of ReadReq misses system.cpu2.l1c.WriteReq_misses::cpu2 24129 # number of WriteReq misses system.cpu2.l1c.WriteReq_misses::total 24129 # number of WriteReq misses -system.cpu2.l1c.demand_misses::cpu2 60649 # number of demand (read+write) misses -system.cpu2.l1c.demand_misses::total 60649 # number of demand (read+write) misses -system.cpu2.l1c.overall_misses::cpu2 60649 # number of overall misses -system.cpu2.l1c.overall_misses::total 60649 # number of overall misses -system.cpu2.l1c.ReadReq_miss_latency::cpu2 666978729 # number of ReadReq miss cycles -system.cpu2.l1c.ReadReq_miss_latency::total 666978729 # number of ReadReq miss cycles -system.cpu2.l1c.WriteReq_miss_latency::cpu2 561823462 # number of WriteReq miss cycles -system.cpu2.l1c.WriteReq_miss_latency::total 561823462 # number of WriteReq miss cycles -system.cpu2.l1c.demand_miss_latency::cpu2 1228802191 # number of demand (read+write) miss cycles -system.cpu2.l1c.demand_miss_latency::total 1228802191 # number of demand (read+write) miss cycles -system.cpu2.l1c.overall_miss_latency::cpu2 1228802191 # number of overall miss cycles -system.cpu2.l1c.overall_miss_latency::total 1228802191 # number of overall miss cycles -system.cpu2.l1c.ReadReq_accesses::cpu2 45261 # number of ReadReq accesses(hits+misses) -system.cpu2.l1c.ReadReq_accesses::total 45261 # number of ReadReq accesses(hits+misses) -system.cpu2.l1c.WriteReq_accesses::cpu2 25306 # number of WriteReq accesses(hits+misses) -system.cpu2.l1c.WriteReq_accesses::total 25306 # number of WriteReq accesses(hits+misses) -system.cpu2.l1c.demand_accesses::cpu2 70567 # number of demand (read+write) accesses -system.cpu2.l1c.demand_accesses::total 70567 # number of demand (read+write) accesses -system.cpu2.l1c.overall_accesses::cpu2 70567 # number of overall (read+write) accesses -system.cpu2.l1c.overall_accesses::total 70567 # number of overall (read+write) accesses -system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.806876 # miss rate for ReadReq accesses -system.cpu2.l1c.ReadReq_miss_rate::total 0.806876 # miss rate for ReadReq accesses -system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.953489 # miss rate for WriteReq accesses -system.cpu2.l1c.WriteReq_miss_rate::total 0.953489 # miss rate for WriteReq accesses -system.cpu2.l1c.demand_miss_rate::cpu2 0.859453 # miss rate for demand accesses -system.cpu2.l1c.demand_miss_rate::total 0.859453 # miss rate for demand accesses -system.cpu2.l1c.overall_miss_rate::cpu2 0.859453 # miss rate for overall accesses -system.cpu2.l1c.overall_miss_rate::total 0.859453 # miss rate for overall accesses -system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 18263.382503 # average ReadReq miss latency -system.cpu2.l1c.ReadReq_avg_miss_latency::total 18263.382503 # average ReadReq miss latency -system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 23284.158564 # average WriteReq miss latency -system.cpu2.l1c.WriteReq_avg_miss_latency::total 23284.158564 # average WriteReq miss latency -system.cpu2.l1c.demand_avg_miss_latency::cpu2 20260.881317 # average overall miss latency -system.cpu2.l1c.demand_avg_miss_latency::total 20260.881317 # average overall miss latency -system.cpu2.l1c.overall_avg_miss_latency::cpu2 20260.881317 # average overall miss latency -system.cpu2.l1c.overall_avg_miss_latency::total 20260.881317 # average overall miss latency -system.cpu2.l1c.blocked_cycles::no_mshrs 804972 # number of cycles access was blocked +system.cpu2.l1c.demand_misses::cpu2 60319 # number of demand (read+write) misses +system.cpu2.l1c.demand_misses::total 60319 # number of demand (read+write) misses +system.cpu2.l1c.overall_misses::cpu2 60319 # number of overall misses +system.cpu2.l1c.overall_misses::total 60319 # number of overall misses +system.cpu2.l1c.ReadReq_miss_latency::cpu2 713868287 # number of ReadReq miss cycles +system.cpu2.l1c.ReadReq_miss_latency::total 713868287 # number of ReadReq miss cycles +system.cpu2.l1c.WriteReq_miss_latency::cpu2 591883556 # number of WriteReq miss cycles +system.cpu2.l1c.WriteReq_miss_latency::total 591883556 # number of WriteReq miss cycles +system.cpu2.l1c.demand_miss_latency::cpu2 1305751843 # number of demand (read+write) miss cycles +system.cpu2.l1c.demand_miss_latency::total 1305751843 # number of demand (read+write) miss cycles +system.cpu2.l1c.overall_miss_latency::cpu2 1305751843 # number of overall miss cycles +system.cpu2.l1c.overall_miss_latency::total 1305751843 # number of overall miss cycles +system.cpu2.l1c.ReadReq_accesses::cpu2 44895 # number of ReadReq accesses(hits+misses) +system.cpu2.l1c.ReadReq_accesses::total 44895 # number of ReadReq accesses(hits+misses) +system.cpu2.l1c.WriteReq_accesses::cpu2 25317 # number of WriteReq accesses(hits+misses) +system.cpu2.l1c.WriteReq_accesses::total 25317 # number of WriteReq accesses(hits+misses) +system.cpu2.l1c.demand_accesses::cpu2 70212 # number of demand (read+write) accesses +system.cpu2.l1c.demand_accesses::total 70212 # number of demand (read+write) accesses +system.cpu2.l1c.overall_accesses::cpu2 70212 # number of overall (read+write) accesses +system.cpu2.l1c.overall_accesses::total 70212 # number of overall (read+write) accesses +system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.806103 # miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_miss_rate::total 0.806103 # miss rate for ReadReq accesses +system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.953075 # miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_miss_rate::total 0.953075 # miss rate for WriteReq accesses +system.cpu2.l1c.demand_miss_rate::cpu2 0.859098 # miss rate for demand accesses +system.cpu2.l1c.demand_miss_rate::total 0.859098 # miss rate for demand accesses +system.cpu2.l1c.overall_miss_rate::cpu2 0.859098 # miss rate for overall accesses +system.cpu2.l1c.overall_miss_rate::total 0.859098 # miss rate for overall accesses +system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 19725.567477 # average ReadReq miss latency +system.cpu2.l1c.ReadReq_avg_miss_latency::total 19725.567477 # average ReadReq miss latency +system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 24529.966265 # average WriteReq miss latency +system.cpu2.l1c.WriteReq_avg_miss_latency::total 24529.966265 # average WriteReq miss latency +system.cpu2.l1c.demand_avg_miss_latency::cpu2 21647.438502 # average overall miss latency +system.cpu2.l1c.demand_avg_miss_latency::total 21647.438502 # average overall miss latency +system.cpu2.l1c.overall_avg_miss_latency::cpu2 21647.438502 # average overall miss latency +system.cpu2.l1c.overall_avg_miss_latency::total 21647.438502 # average overall miss latency +system.cpu2.l1c.blocked_cycles::no_mshrs 871392 # number of cycles access was blocked system.cpu2.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu2.l1c.blocked::no_mshrs 66283 # number of cycles access was blocked +system.cpu2.l1c.blocked::no_mshrs 66762 # number of cycles access was blocked system.cpu2.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu2.l1c.avg_blocked_cycles::no_mshrs 12.144471 # average number of cycles each access was blocked +system.cpu2.l1c.avg_blocked_cycles::no_mshrs 13.052215 # average number of cycles each access was blocked system.cpu2.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu2.l1c.writebacks::writebacks 9821 # number of writebacks -system.cpu2.l1c.writebacks::total 9821 # number of writebacks -system.cpu2.l1c.ReadReq_mshr_misses::cpu2 36520 # number of ReadReq MSHR misses -system.cpu2.l1c.ReadReq_mshr_misses::total 36520 # number of ReadReq MSHR misses +system.cpu2.l1c.writebacks::writebacks 9753 # number of writebacks +system.cpu2.l1c.writebacks::total 9753 # number of writebacks +system.cpu2.l1c.ReadReq_mshr_misses::cpu2 36190 # number of ReadReq MSHR misses +system.cpu2.l1c.ReadReq_mshr_misses::total 36190 # number of ReadReq MSHR misses system.cpu2.l1c.WriteReq_mshr_misses::cpu2 24129 # number of WriteReq MSHR misses system.cpu2.l1c.WriteReq_mshr_misses::total 24129 # number of WriteReq MSHR misses -system.cpu2.l1c.demand_mshr_misses::cpu2 60649 # number of demand (read+write) MSHR misses -system.cpu2.l1c.demand_mshr_misses::total 60649 # number of demand (read+write) MSHR misses -system.cpu2.l1c.overall_mshr_misses::cpu2 60649 # number of overall MSHR misses -system.cpu2.l1c.overall_mshr_misses::total 60649 # number of overall MSHR misses -system.cpu2.l1c.ReadReq_mshr_uncacheable::cpu2 9985 # number of ReadReq MSHR uncacheable -system.cpu2.l1c.ReadReq_mshr_uncacheable::total 9985 # number of ReadReq MSHR uncacheable -system.cpu2.l1c.WriteReq_mshr_uncacheable::cpu2 5427 # number of WriteReq MSHR uncacheable -system.cpu2.l1c.WriteReq_mshr_uncacheable::total 5427 # number of WriteReq MSHR uncacheable -system.cpu2.l1c.overall_mshr_uncacheable_misses::cpu2 15412 # number of overall MSHR uncacheable misses -system.cpu2.l1c.overall_mshr_uncacheable_misses::total 15412 # number of overall MSHR uncacheable misses -system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2 630459729 # number of ReadReq MSHR miss cycles -system.cpu2.l1c.ReadReq_mshr_miss_latency::total 630459729 # number of ReadReq MSHR miss cycles -system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 537696462 # number of WriteReq MSHR miss cycles -system.cpu2.l1c.WriteReq_mshr_miss_latency::total 537696462 # number of WriteReq MSHR miss cycles -system.cpu2.l1c.demand_mshr_miss_latency::cpu2 1168156191 # number of demand (read+write) MSHR miss cycles -system.cpu2.l1c.demand_mshr_miss_latency::total 1168156191 # number of demand (read+write) MSHR miss cycles -system.cpu2.l1c.overall_mshr_miss_latency::cpu2 1168156191 # number of overall MSHR miss cycles -system.cpu2.l1c.overall_mshr_miss_latency::total 1168156191 # number of overall MSHR miss cycles -system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 746431095 # number of ReadReq MSHR uncacheable cycles -system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 746431095 # number of ReadReq MSHR uncacheable cycles -system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 746431095 # number of overall MSHR uncacheable cycles -system.cpu2.l1c.overall_mshr_uncacheable_latency::total 746431095 # number of overall MSHR uncacheable cycles -system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.806876 # mshr miss rate for ReadReq accesses -system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.806876 # mshr miss rate for ReadReq accesses -system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.953489 # mshr miss rate for WriteReq accesses -system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.953489 # mshr miss rate for WriteReq accesses -system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.859453 # mshr miss rate for demand accesses -system.cpu2.l1c.demand_mshr_miss_rate::total 0.859453 # mshr miss rate for demand accesses -system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.859453 # mshr miss rate for overall accesses -system.cpu2.l1c.overall_mshr_miss_rate::total 0.859453 # mshr miss rate for overall accesses -system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 17263.409885 # average ReadReq mshr miss latency -system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 17263.409885 # average ReadReq mshr miss latency -system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 22284.241452 # average WriteReq mshr miss latency -system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 22284.241452 # average WriteReq mshr miss latency -system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 19260.930782 # average overall mshr miss latency -system.cpu2.l1c.demand_avg_mshr_miss_latency::total 19260.930782 # average overall mshr miss latency -system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 19260.930782 # average overall mshr miss latency -system.cpu2.l1c.overall_avg_mshr_miss_latency::total 19260.930782 # average overall mshr miss latency -system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2 74755.242364 # average ReadReq mshr uncacheable latency -system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total 74755.242364 # average ReadReq mshr uncacheable latency -system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 48431.812549 # average overall mshr uncacheable latency -system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total 48431.812549 # average overall mshr uncacheable latency -system.cpu3.pwrStateResidencyTicks::UNDEFINED 500337000 # Cumulative time (in ticks) in various power states -system.cpu3.num_reads 99831 # number of read accesses completed -system.cpu3.num_writes 55461 # number of write accesses completed -system.cpu3.l1c.tags.pwrStateResidencyTicks::UNDEFINED 500337000 # Cumulative time (in ticks) in various power states -system.cpu3.l1c.tags.replacements 22291 # number of replacements -system.cpu3.l1c.tags.tagsinuse 391.006782 # Cycle average of tags in use -system.cpu3.l1c.tags.total_refs 13350 # Total number of references to valid blocks. -system.cpu3.l1c.tags.sampled_refs 22681 # Sample count of references to valid blocks. -system.cpu3.l1c.tags.avg_refs 0.588598 # Average number of references to valid blocks. +system.cpu2.l1c.demand_mshr_misses::cpu2 60319 # number of demand (read+write) MSHR misses +system.cpu2.l1c.demand_mshr_misses::total 60319 # number of demand (read+write) MSHR misses +system.cpu2.l1c.overall_mshr_misses::cpu2 60319 # number of overall MSHR misses +system.cpu2.l1c.overall_mshr_misses::total 60319 # number of overall MSHR misses +system.cpu2.l1c.ReadReq_mshr_uncacheable::cpu2 9852 # number of ReadReq MSHR uncacheable +system.cpu2.l1c.ReadReq_mshr_uncacheable::total 9852 # number of ReadReq MSHR uncacheable +system.cpu2.l1c.WriteReq_mshr_uncacheable::cpu2 5498 # number of WriteReq MSHR uncacheable +system.cpu2.l1c.WriteReq_mshr_uncacheable::total 5498 # number of WriteReq MSHR uncacheable +system.cpu2.l1c.overall_mshr_uncacheable_misses::cpu2 15350 # number of overall MSHR uncacheable misses +system.cpu2.l1c.overall_mshr_uncacheable_misses::total 15350 # number of overall MSHR uncacheable misses +system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2 677680287 # number of ReadReq MSHR miss cycles +system.cpu2.l1c.ReadReq_mshr_miss_latency::total 677680287 # number of ReadReq MSHR miss cycles +system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 567754556 # number of WriteReq MSHR miss cycles +system.cpu2.l1c.WriteReq_mshr_miss_latency::total 567754556 # number of WriteReq MSHR miss cycles +system.cpu2.l1c.demand_mshr_miss_latency::cpu2 1245434843 # number of demand (read+write) MSHR miss cycles +system.cpu2.l1c.demand_mshr_miss_latency::total 1245434843 # number of demand (read+write) MSHR miss cycles +system.cpu2.l1c.overall_mshr_miss_latency::cpu2 1245434843 # number of overall MSHR miss cycles +system.cpu2.l1c.overall_mshr_miss_latency::total 1245434843 # number of overall MSHR miss cycles +system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 769926007 # number of ReadReq MSHR uncacheable cycles +system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 769926007 # number of ReadReq MSHR uncacheable cycles +system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 769926007 # number of overall MSHR uncacheable cycles +system.cpu2.l1c.overall_mshr_uncacheable_latency::total 769926007 # number of overall MSHR uncacheable cycles +system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.806103 # mshr miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.806103 # mshr miss rate for ReadReq accesses +system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.953075 # mshr miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.953075 # mshr miss rate for WriteReq accesses +system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.859098 # mshr miss rate for demand accesses +system.cpu2.l1c.demand_mshr_miss_rate::total 0.859098 # mshr miss rate for demand accesses +system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.859098 # mshr miss rate for overall accesses +system.cpu2.l1c.overall_mshr_miss_rate::total 0.859098 # mshr miss rate for overall accesses +system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 18725.622741 # average ReadReq mshr miss latency +system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 18725.622741 # average ReadReq mshr miss latency +system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 23529.966265 # average WriteReq mshr miss latency +system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 23529.966265 # average WriteReq mshr miss latency +system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 20647.471659 # average overall mshr miss latency +system.cpu2.l1c.demand_avg_mshr_miss_latency::total 20647.471659 # average overall mshr miss latency +system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 20647.471659 # average overall mshr miss latency +system.cpu2.l1c.overall_avg_mshr_miss_latency::total 20647.471659 # average overall mshr miss latency +system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2 78149.208993 # average ReadReq mshr uncacheable latency +system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total 78149.208993 # average ReadReq mshr uncacheable latency +system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 50158.046059 # average overall mshr uncacheable latency +system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total 50158.046059 # average overall mshr uncacheable latency +system.cpu3.pwrStateResidencyTicks::UNDEFINED 521659000 # Cumulative time (in ticks) in various power states +system.cpu3.num_reads 99963 # number of read accesses completed +system.cpu3.num_writes 54829 # number of write accesses completed +system.cpu3.l1c.tags.pwrStateResidencyTicks::UNDEFINED 521659000 # Cumulative time (in ticks) in various power states +system.cpu3.l1c.tags.replacements 22502 # number of replacements +system.cpu3.l1c.tags.tagsinuse 392.266593 # Cycle average of tags in use +system.cpu3.l1c.tags.total_refs 13442 # Total number of references to valid blocks. +system.cpu3.l1c.tags.sampled_refs 22904 # Sample count of references to valid blocks. +system.cpu3.l1c.tags.avg_refs 0.586884 # Average number of references to valid blocks. system.cpu3.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.l1c.tags.occ_blocks::cpu3 391.006782 # Average occupied blocks per requestor -system.cpu3.l1c.tags.occ_percent::cpu3 0.763685 # Average percentage of cache occupancy -system.cpu3.l1c.tags.occ_percent::total 0.763685 # Average percentage of cache occupancy -system.cpu3.l1c.tags.occ_task_id_blocks::1024 390 # Occupied blocks per task id -system.cpu3.l1c.tags.age_task_id_blocks_1024::0 379 # Occupied blocks per task id -system.cpu3.l1c.tags.age_task_id_blocks_1024::1 11 # Occupied blocks per task id -system.cpu3.l1c.tags.occ_task_id_percent::1024 0.761719 # Percentage of cache occupancy per task id -system.cpu3.l1c.tags.tag_accesses 338050 # Number of tag accesses -system.cpu3.l1c.tags.data_accesses 338050 # Number of data accesses -system.cpu3.l1c.pwrStateResidencyTicks::UNDEFINED 500337000 # Cumulative time (in ticks) in various power states -system.cpu3.l1c.ReadReq_hits::cpu3 8529 # number of ReadReq hits -system.cpu3.l1c.ReadReq_hits::total 8529 # number of ReadReq hits -system.cpu3.l1c.WriteReq_hits::cpu3 1176 # number of WriteReq hits -system.cpu3.l1c.WriteReq_hits::total 1176 # number of WriteReq hits -system.cpu3.l1c.demand_hits::cpu3 9705 # number of demand (read+write) hits -system.cpu3.l1c.demand_hits::total 9705 # number of demand (read+write) hits -system.cpu3.l1c.overall_hits::cpu3 9705 # number of overall hits -system.cpu3.l1c.overall_hits::total 9705 # number of overall hits -system.cpu3.l1c.ReadReq_misses::cpu3 36689 # number of ReadReq misses -system.cpu3.l1c.ReadReq_misses::total 36689 # number of ReadReq misses -system.cpu3.l1c.WriteReq_misses::cpu3 23899 # number of WriteReq misses -system.cpu3.l1c.WriteReq_misses::total 23899 # number of WriteReq misses -system.cpu3.l1c.demand_misses::cpu3 60588 # number of demand (read+write) misses -system.cpu3.l1c.demand_misses::total 60588 # number of demand (read+write) misses -system.cpu3.l1c.overall_misses::cpu3 60588 # number of overall misses -system.cpu3.l1c.overall_misses::total 60588 # number of overall misses -system.cpu3.l1c.ReadReq_miss_latency::cpu3 675943664 # number of ReadReq miss cycles -system.cpu3.l1c.ReadReq_miss_latency::total 675943664 # number of ReadReq miss cycles -system.cpu3.l1c.WriteReq_miss_latency::cpu3 557387689 # number of WriteReq miss cycles -system.cpu3.l1c.WriteReq_miss_latency::total 557387689 # number of WriteReq miss cycles -system.cpu3.l1c.demand_miss_latency::cpu3 1233331353 # number of demand (read+write) miss cycles -system.cpu3.l1c.demand_miss_latency::total 1233331353 # number of demand (read+write) miss cycles -system.cpu3.l1c.overall_miss_latency::cpu3 1233331353 # number of overall miss cycles -system.cpu3.l1c.overall_miss_latency::total 1233331353 # number of overall miss cycles -system.cpu3.l1c.ReadReq_accesses::cpu3 45218 # number of ReadReq accesses(hits+misses) -system.cpu3.l1c.ReadReq_accesses::total 45218 # number of ReadReq accesses(hits+misses) -system.cpu3.l1c.WriteReq_accesses::cpu3 25075 # number of WriteReq accesses(hits+misses) -system.cpu3.l1c.WriteReq_accesses::total 25075 # number of WriteReq accesses(hits+misses) -system.cpu3.l1c.demand_accesses::cpu3 70293 # number of demand (read+write) accesses -system.cpu3.l1c.demand_accesses::total 70293 # number of demand (read+write) accesses -system.cpu3.l1c.overall_accesses::cpu3 70293 # number of overall (read+write) accesses -system.cpu3.l1c.overall_accesses::total 70293 # number of overall (read+write) accesses -system.cpu3.l1c.ReadReq_miss_rate::cpu3 0.811380 # miss rate for ReadReq accesses -system.cpu3.l1c.ReadReq_miss_rate::total 0.811380 # miss rate for ReadReq accesses -system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.953101 # miss rate for WriteReq accesses -system.cpu3.l1c.WriteReq_miss_rate::total 0.953101 # miss rate for WriteReq accesses -system.cpu3.l1c.demand_miss_rate::cpu3 0.861935 # miss rate for demand accesses -system.cpu3.l1c.demand_miss_rate::total 0.861935 # miss rate for demand accesses -system.cpu3.l1c.overall_miss_rate::cpu3 0.861935 # miss rate for overall accesses -system.cpu3.l1c.overall_miss_rate::total 0.861935 # miss rate for overall accesses -system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 18423.605549 # average ReadReq miss latency -system.cpu3.l1c.ReadReq_avg_miss_latency::total 18423.605549 # average ReadReq miss latency -system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 23322.636470 # average WriteReq miss latency -system.cpu3.l1c.WriteReq_avg_miss_latency::total 23322.636470 # average WriteReq miss latency -system.cpu3.l1c.demand_avg_miss_latency::cpu3 20356.033422 # average overall miss latency -system.cpu3.l1c.demand_avg_miss_latency::total 20356.033422 # average overall miss latency -system.cpu3.l1c.overall_avg_miss_latency::cpu3 20356.033422 # average overall miss latency -system.cpu3.l1c.overall_avg_miss_latency::total 20356.033422 # average overall miss latency -system.cpu3.l1c.blocked_cycles::no_mshrs 801051 # number of cycles access was blocked +system.cpu3.l1c.tags.occ_blocks::cpu3 392.266593 # Average occupied blocks per requestor +system.cpu3.l1c.tags.occ_percent::cpu3 0.766146 # Average percentage of cache occupancy +system.cpu3.l1c.tags.occ_percent::total 0.766146 # Average percentage of cache occupancy +system.cpu3.l1c.tags.occ_task_id_blocks::1024 402 # Occupied blocks per task id +system.cpu3.l1c.tags.age_task_id_blocks_1024::0 394 # Occupied blocks per task id +system.cpu3.l1c.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id +system.cpu3.l1c.tags.occ_task_id_percent::1024 0.785156 # Percentage of cache occupancy per task id +system.cpu3.l1c.tags.tag_accesses 338127 # Number of tag accesses +system.cpu3.l1c.tags.data_accesses 338127 # Number of data accesses +system.cpu3.l1c.pwrStateResidencyTicks::UNDEFINED 521659000 # Cumulative time (in ticks) in various power states +system.cpu3.l1c.ReadReq_hits::cpu3 8758 # number of ReadReq hits +system.cpu3.l1c.ReadReq_hits::total 8758 # number of ReadReq hits +system.cpu3.l1c.WriteReq_hits::cpu3 1160 # number of WriteReq hits +system.cpu3.l1c.WriteReq_hits::total 1160 # number of WriteReq hits +system.cpu3.l1c.demand_hits::cpu3 9918 # number of demand (read+write) hits +system.cpu3.l1c.demand_hits::total 9918 # number of demand (read+write) hits +system.cpu3.l1c.overall_hits::cpu3 9918 # number of overall hits +system.cpu3.l1c.overall_hits::total 9918 # number of overall hits +system.cpu3.l1c.ReadReq_misses::cpu3 36654 # number of ReadReq misses +system.cpu3.l1c.ReadReq_misses::total 36654 # number of ReadReq misses +system.cpu3.l1c.WriteReq_misses::cpu3 23751 # number of WriteReq misses +system.cpu3.l1c.WriteReq_misses::total 23751 # number of WriteReq misses +system.cpu3.l1c.demand_misses::cpu3 60405 # number of demand (read+write) misses +system.cpu3.l1c.demand_misses::total 60405 # number of demand (read+write) misses +system.cpu3.l1c.overall_misses::cpu3 60405 # number of overall misses +system.cpu3.l1c.overall_misses::total 60405 # number of overall misses +system.cpu3.l1c.ReadReq_miss_latency::cpu3 726630781 # number of ReadReq miss cycles +system.cpu3.l1c.ReadReq_miss_latency::total 726630781 # number of ReadReq miss cycles +system.cpu3.l1c.WriteReq_miss_latency::cpu3 580088175 # number of WriteReq miss cycles +system.cpu3.l1c.WriteReq_miss_latency::total 580088175 # number of WriteReq miss cycles +system.cpu3.l1c.demand_miss_latency::cpu3 1306718956 # number of demand (read+write) miss cycles +system.cpu3.l1c.demand_miss_latency::total 1306718956 # number of demand (read+write) miss cycles +system.cpu3.l1c.overall_miss_latency::cpu3 1306718956 # number of overall miss cycles +system.cpu3.l1c.overall_miss_latency::total 1306718956 # number of overall miss cycles +system.cpu3.l1c.ReadReq_accesses::cpu3 45412 # number of ReadReq accesses(hits+misses) +system.cpu3.l1c.ReadReq_accesses::total 45412 # number of ReadReq accesses(hits+misses) +system.cpu3.l1c.WriteReq_accesses::cpu3 24911 # number of WriteReq accesses(hits+misses) +system.cpu3.l1c.WriteReq_accesses::total 24911 # number of WriteReq accesses(hits+misses) +system.cpu3.l1c.demand_accesses::cpu3 70323 # number of demand (read+write) accesses +system.cpu3.l1c.demand_accesses::total 70323 # number of demand (read+write) accesses +system.cpu3.l1c.overall_accesses::cpu3 70323 # number of overall (read+write) accesses +system.cpu3.l1c.overall_accesses::total 70323 # number of overall (read+write) accesses +system.cpu3.l1c.ReadReq_miss_rate::cpu3 0.807143 # miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_miss_rate::total 0.807143 # miss rate for ReadReq accesses +system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.953434 # miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_miss_rate::total 0.953434 # miss rate for WriteReq accesses +system.cpu3.l1c.demand_miss_rate::cpu3 0.858965 # miss rate for demand accesses +system.cpu3.l1c.demand_miss_rate::total 0.858965 # miss rate for demand accesses +system.cpu3.l1c.overall_miss_rate::cpu3 0.858965 # miss rate for overall accesses +system.cpu3.l1c.overall_miss_rate::total 0.858965 # miss rate for overall accesses +system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 19824.051427 # average ReadReq miss latency +system.cpu3.l1c.ReadReq_avg_miss_latency::total 19824.051427 # average ReadReq miss latency +system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 24423.736895 # average WriteReq miss latency +system.cpu3.l1c.WriteReq_avg_miss_latency::total 24423.736895 # average WriteReq miss latency +system.cpu3.l1c.demand_avg_miss_latency::cpu3 21632.629021 # average overall miss latency +system.cpu3.l1c.demand_avg_miss_latency::total 21632.629021 # average overall miss latency +system.cpu3.l1c.overall_avg_miss_latency::cpu3 21632.629021 # average overall miss latency +system.cpu3.l1c.overall_avg_miss_latency::total 21632.629021 # average overall miss latency +system.cpu3.l1c.blocked_cycles::no_mshrs 870625 # number of cycles access was blocked system.cpu3.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu3.l1c.blocked::no_mshrs 65873 # number of cycles access was blocked +system.cpu3.l1c.blocked::no_mshrs 66788 # number of cycles access was blocked system.cpu3.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu3.l1c.avg_blocked_cycles::no_mshrs 12.160536 # average number of cycles each access was blocked +system.cpu3.l1c.avg_blocked_cycles::no_mshrs 13.035650 # average number of cycles each access was blocked system.cpu3.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu3.l1c.writebacks::writebacks 9857 # number of writebacks -system.cpu3.l1c.writebacks::total 9857 # number of writebacks -system.cpu3.l1c.ReadReq_mshr_misses::cpu3 36689 # number of ReadReq MSHR misses -system.cpu3.l1c.ReadReq_mshr_misses::total 36689 # number of ReadReq MSHR misses -system.cpu3.l1c.WriteReq_mshr_misses::cpu3 23899 # number of WriteReq MSHR misses -system.cpu3.l1c.WriteReq_mshr_misses::total 23899 # number of WriteReq MSHR misses -system.cpu3.l1c.demand_mshr_misses::cpu3 60588 # number of demand (read+write) MSHR misses -system.cpu3.l1c.demand_mshr_misses::total 60588 # number of demand (read+write) MSHR misses -system.cpu3.l1c.overall_mshr_misses::cpu3 60588 # number of overall MSHR misses -system.cpu3.l1c.overall_mshr_misses::total 60588 # number of overall MSHR misses -system.cpu3.l1c.ReadReq_mshr_uncacheable::cpu3 9849 # number of ReadReq MSHR uncacheable -system.cpu3.l1c.ReadReq_mshr_uncacheable::total 9849 # number of ReadReq MSHR uncacheable -system.cpu3.l1c.WriteReq_mshr_uncacheable::cpu3 5582 # number of WriteReq MSHR uncacheable -system.cpu3.l1c.WriteReq_mshr_uncacheable::total 5582 # number of WriteReq MSHR uncacheable -system.cpu3.l1c.overall_mshr_uncacheable_misses::cpu3 15431 # number of overall MSHR uncacheable misses -system.cpu3.l1c.overall_mshr_uncacheable_misses::total 15431 # number of overall MSHR uncacheable misses -system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3 639257664 # number of ReadReq MSHR miss cycles -system.cpu3.l1c.ReadReq_mshr_miss_latency::total 639257664 # number of ReadReq MSHR miss cycles -system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 533488689 # number of WriteReq MSHR miss cycles -system.cpu3.l1c.WriteReq_mshr_miss_latency::total 533488689 # number of WriteReq MSHR miss cycles -system.cpu3.l1c.demand_mshr_miss_latency::cpu3 1172746353 # number of demand (read+write) MSHR miss cycles -system.cpu3.l1c.demand_mshr_miss_latency::total 1172746353 # number of demand (read+write) MSHR miss cycles -system.cpu3.l1c.overall_mshr_miss_latency::cpu3 1172746353 # number of overall MSHR miss cycles -system.cpu3.l1c.overall_mshr_miss_latency::total 1172746353 # number of overall MSHR miss cycles -system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 738856089 # number of ReadReq MSHR uncacheable cycles -system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 738856089 # number of ReadReq MSHR uncacheable cycles -system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 738856089 # number of overall MSHR uncacheable cycles -system.cpu3.l1c.overall_mshr_uncacheable_latency::total 738856089 # number of overall MSHR uncacheable cycles -system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.811380 # mshr miss rate for ReadReq accesses -system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.811380 # mshr miss rate for ReadReq accesses -system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.953101 # mshr miss rate for WriteReq accesses -system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.953101 # mshr miss rate for WriteReq accesses -system.cpu3.l1c.demand_mshr_miss_rate::cpu3 0.861935 # mshr miss rate for demand accesses -system.cpu3.l1c.demand_mshr_miss_rate::total 0.861935 # mshr miss rate for demand accesses -system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.861935 # mshr miss rate for overall accesses -system.cpu3.l1c.overall_mshr_miss_rate::total 0.861935 # mshr miss rate for overall accesses -system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 17423.687318 # average ReadReq mshr miss latency -system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 17423.687318 # average ReadReq mshr miss latency -system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 22322.636470 # average WriteReq mshr miss latency -system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 22322.636470 # average WriteReq mshr miss latency -system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 19356.082937 # average overall mshr miss latency -system.cpu3.l1c.demand_avg_mshr_miss_latency::total 19356.082937 # average overall mshr miss latency -system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 19356.082937 # average overall mshr miss latency -system.cpu3.l1c.overall_avg_mshr_miss_latency::total 19356.082937 # average overall mshr miss latency -system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3 75018.386537 # average ReadReq mshr uncacheable latency -system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total 75018.386537 # average ReadReq mshr uncacheable latency -system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 47881.283715 # average overall mshr uncacheable latency -system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total 47881.283715 # average overall mshr uncacheable latency -system.cpu4.pwrStateResidencyTicks::UNDEFINED 500337000 # Cumulative time (in ticks) in various power states -system.cpu4.num_reads 99911 # number of read accesses completed -system.cpu4.num_writes 55300 # number of write accesses completed -system.cpu4.l1c.tags.pwrStateResidencyTicks::UNDEFINED 500337000 # Cumulative time (in ticks) in various power states -system.cpu4.l1c.tags.replacements 22364 # number of replacements -system.cpu4.l1c.tags.tagsinuse 391.705900 # Cycle average of tags in use -system.cpu4.l1c.tags.total_refs 13535 # Total number of references to valid blocks. -system.cpu4.l1c.tags.sampled_refs 22773 # Sample count of references to valid blocks. -system.cpu4.l1c.tags.avg_refs 0.594344 # Average number of references to valid blocks. +system.cpu3.l1c.writebacks::writebacks 9808 # number of writebacks +system.cpu3.l1c.writebacks::total 9808 # number of writebacks +system.cpu3.l1c.ReadReq_mshr_misses::cpu3 36654 # number of ReadReq MSHR misses +system.cpu3.l1c.ReadReq_mshr_misses::total 36654 # number of ReadReq MSHR misses +system.cpu3.l1c.WriteReq_mshr_misses::cpu3 23751 # number of WriteReq MSHR misses +system.cpu3.l1c.WriteReq_mshr_misses::total 23751 # number of WriteReq MSHR misses +system.cpu3.l1c.demand_mshr_misses::cpu3 60405 # number of demand (read+write) MSHR misses +system.cpu3.l1c.demand_mshr_misses::total 60405 # number of demand (read+write) MSHR misses +system.cpu3.l1c.overall_mshr_misses::cpu3 60405 # number of overall MSHR misses +system.cpu3.l1c.overall_mshr_misses::total 60405 # number of overall MSHR misses +system.cpu3.l1c.ReadReq_mshr_uncacheable::cpu3 9824 # number of ReadReq MSHR uncacheable +system.cpu3.l1c.ReadReq_mshr_uncacheable::total 9824 # number of ReadReq MSHR uncacheable +system.cpu3.l1c.WriteReq_mshr_uncacheable::cpu3 5382 # number of WriteReq MSHR uncacheable +system.cpu3.l1c.WriteReq_mshr_uncacheable::total 5382 # number of WriteReq MSHR uncacheable +system.cpu3.l1c.overall_mshr_uncacheable_misses::cpu3 15206 # number of overall MSHR uncacheable misses +system.cpu3.l1c.overall_mshr_uncacheable_misses::total 15206 # number of overall MSHR uncacheable misses +system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3 689977781 # number of ReadReq MSHR miss cycles +system.cpu3.l1c.ReadReq_mshr_miss_latency::total 689977781 # number of ReadReq MSHR miss cycles +system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 556338175 # number of WriteReq MSHR miss cycles +system.cpu3.l1c.WriteReq_mshr_miss_latency::total 556338175 # number of WriteReq MSHR miss cycles +system.cpu3.l1c.demand_mshr_miss_latency::cpu3 1246315956 # number of demand (read+write) MSHR miss cycles +system.cpu3.l1c.demand_mshr_miss_latency::total 1246315956 # number of demand (read+write) MSHR miss cycles +system.cpu3.l1c.overall_mshr_miss_latency::cpu3 1246315956 # number of overall MSHR miss cycles +system.cpu3.l1c.overall_mshr_miss_latency::total 1246315956 # number of overall MSHR miss cycles +system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 768661965 # number of ReadReq MSHR uncacheable cycles +system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 768661965 # number of ReadReq MSHR uncacheable cycles +system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 768661965 # number of overall MSHR uncacheable cycles +system.cpu3.l1c.overall_mshr_uncacheable_latency::total 768661965 # number of overall MSHR uncacheable cycles +system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.807143 # mshr miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.807143 # mshr miss rate for ReadReq accesses +system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.953434 # mshr miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.953434 # mshr miss rate for WriteReq accesses +system.cpu3.l1c.demand_mshr_miss_rate::cpu3 0.858965 # mshr miss rate for demand accesses +system.cpu3.l1c.demand_mshr_miss_rate::total 0.858965 # mshr miss rate for demand accesses +system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.858965 # mshr miss rate for overall accesses +system.cpu3.l1c.overall_mshr_miss_rate::total 0.858965 # mshr miss rate for overall accesses +system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 18824.078709 # average ReadReq mshr miss latency +system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 18824.078709 # average ReadReq mshr miss latency +system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 23423.778999 # average WriteReq mshr miss latency +system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 23423.778999 # average WriteReq mshr miss latency +system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 20632.662131 # average overall mshr miss latency +system.cpu3.l1c.demand_avg_mshr_miss_latency::total 20632.662131 # average overall mshr miss latency +system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 20632.662131 # average overall mshr miss latency +system.cpu3.l1c.overall_avg_mshr_miss_latency::total 20632.662131 # average overall mshr miss latency +system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3 78243.278196 # average ReadReq mshr uncacheable latency +system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total 78243.278196 # average ReadReq mshr uncacheable latency +system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 50549.912206 # average overall mshr uncacheable latency +system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total 50549.912206 # average overall mshr uncacheable latency +system.cpu4.pwrStateResidencyTicks::UNDEFINED 521659000 # Cumulative time (in ticks) in various power states +system.cpu4.num_reads 98794 # number of read accesses completed +system.cpu4.num_writes 54937 # number of write accesses completed +system.cpu4.l1c.tags.pwrStateResidencyTicks::UNDEFINED 521659000 # Cumulative time (in ticks) in various power states +system.cpu4.l1c.tags.replacements 22508 # number of replacements +system.cpu4.l1c.tags.tagsinuse 392.668091 # Cycle average of tags in use +system.cpu4.l1c.tags.total_refs 13409 # Total number of references to valid blocks. +system.cpu4.l1c.tags.sampled_refs 22922 # Sample count of references to valid blocks. +system.cpu4.l1c.tags.avg_refs 0.584984 # Average number of references to valid blocks. system.cpu4.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu4.l1c.tags.occ_blocks::cpu4 391.705900 # Average occupied blocks per requestor -system.cpu4.l1c.tags.occ_percent::cpu4 0.765051 # Average percentage of cache occupancy -system.cpu4.l1c.tags.occ_percent::total 0.765051 # Average percentage of cache occupancy -system.cpu4.l1c.tags.occ_task_id_blocks::1024 409 # Occupied blocks per task id -system.cpu4.l1c.tags.age_task_id_blocks_1024::0 401 # Occupied blocks per task id -system.cpu4.l1c.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id -system.cpu4.l1c.tags.occ_task_id_percent::1024 0.798828 # Percentage of cache occupancy per task id -system.cpu4.l1c.tags.tag_accesses 339861 # Number of tag accesses -system.cpu4.l1c.tags.data_accesses 339861 # Number of data accesses -system.cpu4.l1c.pwrStateResidencyTicks::UNDEFINED 500337000 # Cumulative time (in ticks) in various power states -system.cpu4.l1c.ReadReq_hits::cpu4 8886 # number of ReadReq hits -system.cpu4.l1c.ReadReq_hits::total 8886 # number of ReadReq hits -system.cpu4.l1c.WriteReq_hits::cpu4 1168 # number of WriteReq hits -system.cpu4.l1c.WriteReq_hits::total 1168 # number of WriteReq hits -system.cpu4.l1c.demand_hits::cpu4 10054 # number of demand (read+write) hits -system.cpu4.l1c.demand_hits::total 10054 # number of demand (read+write) hits -system.cpu4.l1c.overall_hits::cpu4 10054 # number of overall hits -system.cpu4.l1c.overall_hits::total 10054 # number of overall hits -system.cpu4.l1c.ReadReq_misses::cpu4 36446 # number of ReadReq misses -system.cpu4.l1c.ReadReq_misses::total 36446 # number of ReadReq misses -system.cpu4.l1c.WriteReq_misses::cpu4 24191 # number of WriteReq misses -system.cpu4.l1c.WriteReq_misses::total 24191 # number of WriteReq misses -system.cpu4.l1c.demand_misses::cpu4 60637 # number of demand (read+write) misses -system.cpu4.l1c.demand_misses::total 60637 # number of demand (read+write) misses -system.cpu4.l1c.overall_misses::cpu4 60637 # number of overall misses -system.cpu4.l1c.overall_misses::total 60637 # number of overall misses -system.cpu4.l1c.ReadReq_miss_latency::cpu4 672672441 # number of ReadReq miss cycles -system.cpu4.l1c.ReadReq_miss_latency::total 672672441 # number of ReadReq miss cycles -system.cpu4.l1c.WriteReq_miss_latency::cpu4 560233927 # number of WriteReq miss cycles -system.cpu4.l1c.WriteReq_miss_latency::total 560233927 # number of WriteReq miss cycles -system.cpu4.l1c.demand_miss_latency::cpu4 1232906368 # number of demand (read+write) miss cycles -system.cpu4.l1c.demand_miss_latency::total 1232906368 # number of demand (read+write) miss cycles -system.cpu4.l1c.overall_miss_latency::cpu4 1232906368 # number of overall miss cycles -system.cpu4.l1c.overall_miss_latency::total 1232906368 # number of overall miss cycles -system.cpu4.l1c.ReadReq_accesses::cpu4 45332 # number of ReadReq accesses(hits+misses) -system.cpu4.l1c.ReadReq_accesses::total 45332 # number of ReadReq accesses(hits+misses) -system.cpu4.l1c.WriteReq_accesses::cpu4 25359 # number of WriteReq accesses(hits+misses) -system.cpu4.l1c.WriteReq_accesses::total 25359 # number of WriteReq accesses(hits+misses) -system.cpu4.l1c.demand_accesses::cpu4 70691 # number of demand (read+write) accesses -system.cpu4.l1c.demand_accesses::total 70691 # number of demand (read+write) accesses -system.cpu4.l1c.overall_accesses::cpu4 70691 # number of overall (read+write) accesses -system.cpu4.l1c.overall_accesses::total 70691 # number of overall (read+write) accesses -system.cpu4.l1c.ReadReq_miss_rate::cpu4 0.803980 # miss rate for ReadReq accesses -system.cpu4.l1c.ReadReq_miss_rate::total 0.803980 # miss rate for ReadReq accesses -system.cpu4.l1c.WriteReq_miss_rate::cpu4 0.953941 # miss rate for WriteReq accesses -system.cpu4.l1c.WriteReq_miss_rate::total 0.953941 # miss rate for WriteReq accesses -system.cpu4.l1c.demand_miss_rate::cpu4 0.857775 # miss rate for demand accesses -system.cpu4.l1c.demand_miss_rate::total 0.857775 # miss rate for demand accesses -system.cpu4.l1c.overall_miss_rate::cpu4 0.857775 # miss rate for overall accesses -system.cpu4.l1c.overall_miss_rate::total 0.857775 # miss rate for overall accesses -system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 18456.687730 # average ReadReq miss latency -system.cpu4.l1c.ReadReq_avg_miss_latency::total 18456.687730 # average ReadReq miss latency -system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 23158.775040 # average WriteReq miss latency -system.cpu4.l1c.WriteReq_avg_miss_latency::total 23158.775040 # average WriteReq miss latency -system.cpu4.l1c.demand_avg_miss_latency::cpu4 20332.575292 # average overall miss latency -system.cpu4.l1c.demand_avg_miss_latency::total 20332.575292 # average overall miss latency -system.cpu4.l1c.overall_avg_miss_latency::cpu4 20332.575292 # average overall miss latency -system.cpu4.l1c.overall_avg_miss_latency::total 20332.575292 # average overall miss latency -system.cpu4.l1c.blocked_cycles::no_mshrs 801696 # number of cycles access was blocked +system.cpu4.l1c.tags.occ_blocks::cpu4 392.668091 # Average occupied blocks per requestor +system.cpu4.l1c.tags.occ_percent::cpu4 0.766930 # Average percentage of cache occupancy +system.cpu4.l1c.tags.occ_percent::total 0.766930 # Average percentage of cache occupancy +system.cpu4.l1c.tags.occ_task_id_blocks::1024 414 # Occupied blocks per task id +system.cpu4.l1c.tags.age_task_id_blocks_1024::0 402 # Occupied blocks per task id +system.cpu4.l1c.tags.age_task_id_blocks_1024::1 12 # Occupied blocks per task id +system.cpu4.l1c.tags.occ_task_id_percent::1024 0.808594 # Percentage of cache occupancy per task id +system.cpu4.l1c.tags.tag_accesses 337369 # Number of tag accesses +system.cpu4.l1c.tags.data_accesses 337369 # Number of data accesses +system.cpu4.l1c.pwrStateResidencyTicks::UNDEFINED 521659000 # Cumulative time (in ticks) in various power states +system.cpu4.l1c.ReadReq_hits::cpu4 8739 # number of ReadReq hits +system.cpu4.l1c.ReadReq_hits::total 8739 # number of ReadReq hits +system.cpu4.l1c.WriteReq_hits::cpu4 1134 # number of WriteReq hits +system.cpu4.l1c.WriteReq_hits::total 1134 # number of WriteReq hits +system.cpu4.l1c.demand_hits::cpu4 9873 # number of demand (read+write) hits +system.cpu4.l1c.demand_hits::total 9873 # number of demand (read+write) hits +system.cpu4.l1c.overall_hits::cpu4 9873 # number of overall hits +system.cpu4.l1c.overall_hits::total 9873 # number of overall hits +system.cpu4.l1c.ReadReq_misses::cpu4 36311 # number of ReadReq misses +system.cpu4.l1c.ReadReq_misses::total 36311 # number of ReadReq misses +system.cpu4.l1c.WriteReq_misses::cpu4 23983 # number of WriteReq misses +system.cpu4.l1c.WriteReq_misses::total 23983 # number of WriteReq misses +system.cpu4.l1c.demand_misses::cpu4 60294 # number of demand (read+write) misses +system.cpu4.l1c.demand_misses::total 60294 # number of demand (read+write) misses +system.cpu4.l1c.overall_misses::cpu4 60294 # number of overall misses +system.cpu4.l1c.overall_misses::total 60294 # number of overall misses +system.cpu4.l1c.ReadReq_miss_latency::cpu4 724331862 # number of ReadReq miss cycles +system.cpu4.l1c.ReadReq_miss_latency::total 724331862 # number of ReadReq miss cycles +system.cpu4.l1c.WriteReq_miss_latency::cpu4 586488864 # number of WriteReq miss cycles +system.cpu4.l1c.WriteReq_miss_latency::total 586488864 # number of WriteReq miss cycles +system.cpu4.l1c.demand_miss_latency::cpu4 1310820726 # number of demand (read+write) miss cycles +system.cpu4.l1c.demand_miss_latency::total 1310820726 # number of demand (read+write) miss cycles +system.cpu4.l1c.overall_miss_latency::cpu4 1310820726 # number of overall miss cycles +system.cpu4.l1c.overall_miss_latency::total 1310820726 # number of overall miss cycles +system.cpu4.l1c.ReadReq_accesses::cpu4 45050 # number of ReadReq accesses(hits+misses) +system.cpu4.l1c.ReadReq_accesses::total 45050 # number of ReadReq accesses(hits+misses) +system.cpu4.l1c.WriteReq_accesses::cpu4 25117 # number of WriteReq accesses(hits+misses) +system.cpu4.l1c.WriteReq_accesses::total 25117 # number of WriteReq accesses(hits+misses) +system.cpu4.l1c.demand_accesses::cpu4 70167 # number of demand (read+write) accesses +system.cpu4.l1c.demand_accesses::total 70167 # number of demand (read+write) accesses +system.cpu4.l1c.overall_accesses::cpu4 70167 # number of overall (read+write) accesses +system.cpu4.l1c.overall_accesses::total 70167 # number of overall (read+write) accesses +system.cpu4.l1c.ReadReq_miss_rate::cpu4 0.806016 # miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_miss_rate::total 0.806016 # miss rate for ReadReq accesses +system.cpu4.l1c.WriteReq_miss_rate::cpu4 0.954851 # miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_miss_rate::total 0.954851 # miss rate for WriteReq accesses +system.cpu4.l1c.demand_miss_rate::cpu4 0.859293 # miss rate for demand accesses +system.cpu4.l1c.demand_miss_rate::total 0.859293 # miss rate for demand accesses +system.cpu4.l1c.overall_miss_rate::cpu4 0.859293 # miss rate for overall accesses +system.cpu4.l1c.overall_miss_rate::total 0.859293 # miss rate for overall accesses +system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 19948.000936 # average ReadReq miss latency +system.cpu4.l1c.ReadReq_avg_miss_latency::total 19948.000936 # average ReadReq miss latency +system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 24454.357837 # average WriteReq miss latency +system.cpu4.l1c.WriteReq_avg_miss_latency::total 24454.357837 # average WriteReq miss latency +system.cpu4.l1c.demand_avg_miss_latency::cpu4 21740.483730 # average overall miss latency +system.cpu4.l1c.demand_avg_miss_latency::total 21740.483730 # average overall miss latency +system.cpu4.l1c.overall_avg_miss_latency::cpu4 21740.483730 # average overall miss latency +system.cpu4.l1c.overall_avg_miss_latency::total 21740.483730 # average overall miss latency +system.cpu4.l1c.blocked_cycles::no_mshrs 869421 # number of cycles access was blocked system.cpu4.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu4.l1c.blocked::no_mshrs 65950 # number of cycles access was blocked +system.cpu4.l1c.blocked::no_mshrs 66532 # number of cycles access was blocked system.cpu4.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu4.l1c.avg_blocked_cycles::no_mshrs 12.156118 # average number of cycles each access was blocked +system.cpu4.l1c.avg_blocked_cycles::no_mshrs 13.067712 # average number of cycles each access was blocked system.cpu4.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu4.l1c.writebacks::writebacks 9921 # number of writebacks -system.cpu4.l1c.writebacks::total 9921 # number of writebacks -system.cpu4.l1c.ReadReq_mshr_misses::cpu4 36446 # number of ReadReq MSHR misses -system.cpu4.l1c.ReadReq_mshr_misses::total 36446 # number of ReadReq MSHR misses -system.cpu4.l1c.WriteReq_mshr_misses::cpu4 24191 # number of WriteReq MSHR misses -system.cpu4.l1c.WriteReq_mshr_misses::total 24191 # number of WriteReq MSHR misses -system.cpu4.l1c.demand_mshr_misses::cpu4 60637 # number of demand (read+write) MSHR misses -system.cpu4.l1c.demand_mshr_misses::total 60637 # number of demand (read+write) MSHR misses -system.cpu4.l1c.overall_mshr_misses::cpu4 60637 # number of overall MSHR misses -system.cpu4.l1c.overall_mshr_misses::total 60637 # number of overall MSHR misses -system.cpu4.l1c.ReadReq_mshr_uncacheable::cpu4 9877 # number of ReadReq MSHR uncacheable -system.cpu4.l1c.ReadReq_mshr_uncacheable::total 9877 # number of ReadReq MSHR uncacheable -system.cpu4.l1c.WriteReq_mshr_uncacheable::cpu4 5522 # number of WriteReq MSHR uncacheable -system.cpu4.l1c.WriteReq_mshr_uncacheable::total 5522 # number of WriteReq MSHR uncacheable -system.cpu4.l1c.overall_mshr_uncacheable_misses::cpu4 15399 # number of overall MSHR uncacheable misses -system.cpu4.l1c.overall_mshr_uncacheable_misses::total 15399 # number of overall MSHR uncacheable misses -system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4 636227441 # number of ReadReq MSHR miss cycles -system.cpu4.l1c.ReadReq_mshr_miss_latency::total 636227441 # number of ReadReq MSHR miss cycles -system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4 536043927 # number of WriteReq MSHR miss cycles -system.cpu4.l1c.WriteReq_mshr_miss_latency::total 536043927 # number of WriteReq MSHR miss cycles -system.cpu4.l1c.demand_mshr_miss_latency::cpu4 1172271368 # number of demand (read+write) MSHR miss cycles -system.cpu4.l1c.demand_mshr_miss_latency::total 1172271368 # number of demand (read+write) MSHR miss cycles -system.cpu4.l1c.overall_mshr_miss_latency::cpu4 1172271368 # number of overall MSHR miss cycles -system.cpu4.l1c.overall_mshr_miss_latency::total 1172271368 # number of overall MSHR miss cycles -system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4 739458183 # number of ReadReq MSHR uncacheable cycles -system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 739458183 # number of ReadReq MSHR uncacheable cycles -system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4 739458183 # number of overall MSHR uncacheable cycles -system.cpu4.l1c.overall_mshr_uncacheable_latency::total 739458183 # number of overall MSHR uncacheable cycles -system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4 0.803980 # mshr miss rate for ReadReq accesses -system.cpu4.l1c.ReadReq_mshr_miss_rate::total 0.803980 # mshr miss rate for ReadReq accesses -system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4 0.953941 # mshr miss rate for WriteReq accesses -system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.953941 # mshr miss rate for WriteReq accesses -system.cpu4.l1c.demand_mshr_miss_rate::cpu4 0.857775 # mshr miss rate for demand accesses -system.cpu4.l1c.demand_mshr_miss_rate::total 0.857775 # mshr miss rate for demand accesses -system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.857775 # mshr miss rate for overall accesses -system.cpu4.l1c.overall_mshr_miss_rate::total 0.857775 # mshr miss rate for overall accesses -system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 17456.715168 # average ReadReq mshr miss latency -system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 17456.715168 # average ReadReq mshr miss latency -system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 22158.816378 # average WriteReq mshr miss latency -system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 22158.816378 # average WriteReq mshr miss latency -system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 19332.608275 # average overall mshr miss latency -system.cpu4.l1c.demand_avg_mshr_miss_latency::total 19332.608275 # average overall mshr miss latency -system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 19332.608275 # average overall mshr miss latency -system.cpu4.l1c.overall_avg_mshr_miss_latency::total 19332.608275 # average overall mshr miss latency -system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4 74866.678445 # average ReadReq mshr uncacheable latency -system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total 74866.678445 # average ReadReq mshr uncacheable latency -system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 48019.883304 # average overall mshr uncacheable latency -system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total 48019.883304 # average overall mshr uncacheable latency -system.cpu5.pwrStateResidencyTicks::UNDEFINED 500337000 # Cumulative time (in ticks) in various power states -system.cpu5.num_reads 99665 # number of read accesses completed -system.cpu5.num_writes 55439 # number of write accesses completed -system.cpu5.l1c.tags.pwrStateResidencyTicks::UNDEFINED 500337000 # Cumulative time (in ticks) in various power states -system.cpu5.l1c.tags.replacements 22286 # number of replacements -system.cpu5.l1c.tags.tagsinuse 391.859990 # Cycle average of tags in use -system.cpu5.l1c.tags.total_refs 13458 # Total number of references to valid blocks. -system.cpu5.l1c.tags.sampled_refs 22703 # Sample count of references to valid blocks. -system.cpu5.l1c.tags.avg_refs 0.592785 # Average number of references to valid blocks. +system.cpu4.l1c.writebacks::writebacks 9883 # number of writebacks +system.cpu4.l1c.writebacks::total 9883 # number of writebacks +system.cpu4.l1c.ReadReq_mshr_misses::cpu4 36311 # number of ReadReq MSHR misses +system.cpu4.l1c.ReadReq_mshr_misses::total 36311 # number of ReadReq MSHR misses +system.cpu4.l1c.WriteReq_mshr_misses::cpu4 23983 # number of WriteReq MSHR misses +system.cpu4.l1c.WriteReq_mshr_misses::total 23983 # number of WriteReq MSHR misses +system.cpu4.l1c.demand_mshr_misses::cpu4 60294 # number of demand (read+write) MSHR misses +system.cpu4.l1c.demand_mshr_misses::total 60294 # number of demand (read+write) MSHR misses +system.cpu4.l1c.overall_mshr_misses::cpu4 60294 # number of overall MSHR misses +system.cpu4.l1c.overall_mshr_misses::total 60294 # number of overall MSHR misses +system.cpu4.l1c.ReadReq_mshr_uncacheable::cpu4 9741 # number of ReadReq MSHR uncacheable +system.cpu4.l1c.ReadReq_mshr_uncacheable::total 9741 # number of ReadReq MSHR uncacheable +system.cpu4.l1c.WriteReq_mshr_uncacheable::cpu4 5439 # number of WriteReq MSHR uncacheable +system.cpu4.l1c.WriteReq_mshr_uncacheable::total 5439 # number of WriteReq MSHR uncacheable +system.cpu4.l1c.overall_mshr_uncacheable_misses::cpu4 15180 # number of overall MSHR uncacheable misses +system.cpu4.l1c.overall_mshr_uncacheable_misses::total 15180 # number of overall MSHR uncacheable misses +system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4 688022862 # number of ReadReq MSHR miss cycles +system.cpu4.l1c.ReadReq_mshr_miss_latency::total 688022862 # number of ReadReq MSHR miss cycles +system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4 562507864 # number of WriteReq MSHR miss cycles +system.cpu4.l1c.WriteReq_mshr_miss_latency::total 562507864 # number of WriteReq MSHR miss cycles +system.cpu4.l1c.demand_mshr_miss_latency::cpu4 1250530726 # number of demand (read+write) MSHR miss cycles +system.cpu4.l1c.demand_mshr_miss_latency::total 1250530726 # number of demand (read+write) MSHR miss cycles +system.cpu4.l1c.overall_mshr_miss_latency::cpu4 1250530726 # number of overall MSHR miss cycles +system.cpu4.l1c.overall_mshr_miss_latency::total 1250530726 # number of overall MSHR miss cycles +system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4 763019844 # number of ReadReq MSHR uncacheable cycles +system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 763019844 # number of ReadReq MSHR uncacheable cycles +system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4 763019844 # number of overall MSHR uncacheable cycles +system.cpu4.l1c.overall_mshr_uncacheable_latency::total 763019844 # number of overall MSHR uncacheable cycles +system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4 0.806016 # mshr miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_mshr_miss_rate::total 0.806016 # mshr miss rate for ReadReq accesses +system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4 0.954851 # mshr miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.954851 # mshr miss rate for WriteReq accesses +system.cpu4.l1c.demand_mshr_miss_rate::cpu4 0.859293 # mshr miss rate for demand accesses +system.cpu4.l1c.demand_mshr_miss_rate::total 0.859293 # mshr miss rate for demand accesses +system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.859293 # mshr miss rate for overall accesses +system.cpu4.l1c.overall_mshr_miss_rate::total 0.859293 # mshr miss rate for overall accesses +system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 18948.056016 # average ReadReq mshr miss latency +system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 18948.056016 # average ReadReq mshr miss latency +system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 23454.441229 # average WriteReq mshr miss latency +system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 23454.441229 # average WriteReq mshr miss latency +system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 20740.550071 # average overall mshr miss latency +system.cpu4.l1c.demand_avg_mshr_miss_latency::total 20740.550071 # average overall mshr miss latency +system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 20740.550071 # average overall mshr miss latency +system.cpu4.l1c.overall_avg_mshr_miss_latency::total 20740.550071 # average overall mshr miss latency +system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4 78330.750847 # average ReadReq mshr uncacheable latency +system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total 78330.750847 # average ReadReq mshr uncacheable latency +system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 50264.811858 # average overall mshr uncacheable latency +system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total 50264.811858 # average overall mshr uncacheable latency +system.cpu5.pwrStateResidencyTicks::UNDEFINED 521659000 # Cumulative time (in ticks) in various power states +system.cpu5.num_reads 99762 # number of read accesses completed +system.cpu5.num_writes 55488 # number of write accesses completed +system.cpu5.l1c.tags.pwrStateResidencyTicks::UNDEFINED 521659000 # Cumulative time (in ticks) in various power states +system.cpu5.l1c.tags.replacements 22372 # number of replacements +system.cpu5.l1c.tags.tagsinuse 391.676077 # Cycle average of tags in use +system.cpu5.l1c.tags.total_refs 13488 # Total number of references to valid blocks. +system.cpu5.l1c.tags.sampled_refs 22774 # Sample count of references to valid blocks. +system.cpu5.l1c.tags.avg_refs 0.592254 # Average number of references to valid blocks. system.cpu5.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu5.l1c.tags.occ_blocks::cpu5 391.859990 # Average occupied blocks per requestor -system.cpu5.l1c.tags.occ_percent::cpu5 0.765352 # Average percentage of cache occupancy -system.cpu5.l1c.tags.occ_percent::total 0.765352 # Average percentage of cache occupancy -system.cpu5.l1c.tags.occ_task_id_blocks::1024 417 # Occupied blocks per task id -system.cpu5.l1c.tags.age_task_id_blocks_1024::0 407 # Occupied blocks per task id -system.cpu5.l1c.tags.age_task_id_blocks_1024::1 10 # Occupied blocks per task id -system.cpu5.l1c.tags.occ_task_id_percent::1024 0.814453 # Percentage of cache occupancy per task id -system.cpu5.l1c.tags.tag_accesses 338594 # Number of tag accesses -system.cpu5.l1c.tags.data_accesses 338594 # Number of data accesses -system.cpu5.l1c.pwrStateResidencyTicks::UNDEFINED 500337000 # Cumulative time (in ticks) in various power states -system.cpu5.l1c.ReadReq_hits::cpu5 8649 # number of ReadReq hits -system.cpu5.l1c.ReadReq_hits::total 8649 # number of ReadReq hits -system.cpu5.l1c.WriteReq_hits::cpu5 1196 # number of WriteReq hits -system.cpu5.l1c.WriteReq_hits::total 1196 # number of WriteReq hits -system.cpu5.l1c.demand_hits::cpu5 9845 # number of demand (read+write) hits -system.cpu5.l1c.demand_hits::total 9845 # number of demand (read+write) hits -system.cpu5.l1c.overall_hits::cpu5 9845 # number of overall hits -system.cpu5.l1c.overall_hits::total 9845 # number of overall hits -system.cpu5.l1c.ReadReq_misses::cpu5 36574 # number of ReadReq misses -system.cpu5.l1c.ReadReq_misses::total 36574 # number of ReadReq misses -system.cpu5.l1c.WriteReq_misses::cpu5 24003 # number of WriteReq misses -system.cpu5.l1c.WriteReq_misses::total 24003 # number of WriteReq misses -system.cpu5.l1c.demand_misses::cpu5 60577 # number of demand (read+write) misses -system.cpu5.l1c.demand_misses::total 60577 # number of demand (read+write) misses -system.cpu5.l1c.overall_misses::cpu5 60577 # number of overall misses -system.cpu5.l1c.overall_misses::total 60577 # number of overall misses -system.cpu5.l1c.ReadReq_miss_latency::cpu5 671451246 # number of ReadReq miss cycles -system.cpu5.l1c.ReadReq_miss_latency::total 671451246 # number of ReadReq miss cycles -system.cpu5.l1c.WriteReq_miss_latency::cpu5 559158053 # number of WriteReq miss cycles -system.cpu5.l1c.WriteReq_miss_latency::total 559158053 # number of WriteReq miss cycles -system.cpu5.l1c.demand_miss_latency::cpu5 1230609299 # number of demand (read+write) miss cycles -system.cpu5.l1c.demand_miss_latency::total 1230609299 # number of demand (read+write) miss cycles -system.cpu5.l1c.overall_miss_latency::cpu5 1230609299 # number of overall miss cycles -system.cpu5.l1c.overall_miss_latency::total 1230609299 # number of overall miss cycles -system.cpu5.l1c.ReadReq_accesses::cpu5 45223 # number of ReadReq accesses(hits+misses) -system.cpu5.l1c.ReadReq_accesses::total 45223 # number of ReadReq accesses(hits+misses) -system.cpu5.l1c.WriteReq_accesses::cpu5 25199 # number of WriteReq accesses(hits+misses) -system.cpu5.l1c.WriteReq_accesses::total 25199 # number of WriteReq accesses(hits+misses) -system.cpu5.l1c.demand_accesses::cpu5 70422 # number of demand (read+write) accesses -system.cpu5.l1c.demand_accesses::total 70422 # number of demand (read+write) accesses -system.cpu5.l1c.overall_accesses::cpu5 70422 # number of overall (read+write) accesses -system.cpu5.l1c.overall_accesses::total 70422 # number of overall (read+write) accesses -system.cpu5.l1c.ReadReq_miss_rate::cpu5 0.808748 # miss rate for ReadReq accesses -system.cpu5.l1c.ReadReq_miss_rate::total 0.808748 # miss rate for ReadReq accesses -system.cpu5.l1c.WriteReq_miss_rate::cpu5 0.952538 # miss rate for WriteReq accesses -system.cpu5.l1c.WriteReq_miss_rate::total 0.952538 # miss rate for WriteReq accesses -system.cpu5.l1c.demand_miss_rate::cpu5 0.860200 # miss rate for demand accesses -system.cpu5.l1c.demand_miss_rate::total 0.860200 # miss rate for demand accesses -system.cpu5.l1c.overall_miss_rate::cpu5 0.860200 # miss rate for overall accesses -system.cpu5.l1c.overall_miss_rate::total 0.860200 # miss rate for overall accesses -system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 18358.704161 # average ReadReq miss latency -system.cpu5.l1c.ReadReq_avg_miss_latency::total 18358.704161 # average ReadReq miss latency -system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 23295.340291 # average WriteReq miss latency -system.cpu5.l1c.WriteReq_avg_miss_latency::total 23295.340291 # average WriteReq miss latency -system.cpu5.l1c.demand_avg_miss_latency::cpu5 20314.794377 # average overall miss latency -system.cpu5.l1c.demand_avg_miss_latency::total 20314.794377 # average overall miss latency -system.cpu5.l1c.overall_avg_miss_latency::cpu5 20314.794377 # average overall miss latency -system.cpu5.l1c.overall_avg_miss_latency::total 20314.794377 # average overall miss latency -system.cpu5.l1c.blocked_cycles::no_mshrs 802483 # number of cycles access was blocked +system.cpu5.l1c.tags.occ_blocks::cpu5 391.676077 # Average occupied blocks per requestor +system.cpu5.l1c.tags.occ_percent::cpu5 0.764992 # Average percentage of cache occupancy +system.cpu5.l1c.tags.occ_percent::total 0.764992 # Average percentage of cache occupancy +system.cpu5.l1c.tags.occ_task_id_blocks::1024 402 # Occupied blocks per task id +system.cpu5.l1c.tags.age_task_id_blocks_1024::0 387 # Occupied blocks per task id +system.cpu5.l1c.tags.age_task_id_blocks_1024::1 15 # Occupied blocks per task id +system.cpu5.l1c.tags.occ_task_id_percent::1024 0.785156 # Percentage of cache occupancy per task id +system.cpu5.l1c.tags.tag_accesses 338416 # Number of tag accesses +system.cpu5.l1c.tags.data_accesses 338416 # Number of data accesses +system.cpu5.l1c.pwrStateResidencyTicks::UNDEFINED 521659000 # Cumulative time (in ticks) in various power states +system.cpu5.l1c.ReadReq_hits::cpu5 8728 # number of ReadReq hits +system.cpu5.l1c.ReadReq_hits::total 8728 # number of ReadReq hits +system.cpu5.l1c.WriteReq_hits::cpu5 1164 # number of WriteReq hits +system.cpu5.l1c.WriteReq_hits::total 1164 # number of WriteReq hits +system.cpu5.l1c.demand_hits::cpu5 9892 # number of demand (read+write) hits +system.cpu5.l1c.demand_hits::total 9892 # number of demand (read+write) hits +system.cpu5.l1c.overall_hits::cpu5 9892 # number of overall hits +system.cpu5.l1c.overall_hits::total 9892 # number of overall hits +system.cpu5.l1c.ReadReq_misses::cpu5 36506 # number of ReadReq misses +system.cpu5.l1c.ReadReq_misses::total 36506 # number of ReadReq misses +system.cpu5.l1c.WriteReq_misses::cpu5 23995 # number of WriteReq misses +system.cpu5.l1c.WriteReq_misses::total 23995 # number of WriteReq misses +system.cpu5.l1c.demand_misses::cpu5 60501 # number of demand (read+write) misses +system.cpu5.l1c.demand_misses::total 60501 # number of demand (read+write) misses +system.cpu5.l1c.overall_misses::cpu5 60501 # number of overall misses +system.cpu5.l1c.overall_misses::total 60501 # number of overall misses +system.cpu5.l1c.ReadReq_miss_latency::cpu5 721706442 # number of ReadReq miss cycles +system.cpu5.l1c.ReadReq_miss_latency::total 721706442 # number of ReadReq miss cycles +system.cpu5.l1c.WriteReq_miss_latency::cpu5 584665158 # number of WriteReq miss cycles +system.cpu5.l1c.WriteReq_miss_latency::total 584665158 # number of WriteReq miss cycles +system.cpu5.l1c.demand_miss_latency::cpu5 1306371600 # number of demand (read+write) miss cycles +system.cpu5.l1c.demand_miss_latency::total 1306371600 # number of demand (read+write) miss cycles +system.cpu5.l1c.overall_miss_latency::cpu5 1306371600 # number of overall miss cycles +system.cpu5.l1c.overall_miss_latency::total 1306371600 # number of overall miss cycles +system.cpu5.l1c.ReadReq_accesses::cpu5 45234 # number of ReadReq accesses(hits+misses) +system.cpu5.l1c.ReadReq_accesses::total 45234 # number of ReadReq accesses(hits+misses) +system.cpu5.l1c.WriteReq_accesses::cpu5 25159 # number of WriteReq accesses(hits+misses) +system.cpu5.l1c.WriteReq_accesses::total 25159 # number of WriteReq accesses(hits+misses) +system.cpu5.l1c.demand_accesses::cpu5 70393 # number of demand (read+write) accesses +system.cpu5.l1c.demand_accesses::total 70393 # number of demand (read+write) accesses +system.cpu5.l1c.overall_accesses::cpu5 70393 # number of overall (read+write) accesses +system.cpu5.l1c.overall_accesses::total 70393 # number of overall (read+write) accesses +system.cpu5.l1c.ReadReq_miss_rate::cpu5 0.807048 # miss rate for ReadReq accesses +system.cpu5.l1c.ReadReq_miss_rate::total 0.807048 # miss rate for ReadReq accesses +system.cpu5.l1c.WriteReq_miss_rate::cpu5 0.953734 # miss rate for WriteReq accesses +system.cpu5.l1c.WriteReq_miss_rate::total 0.953734 # miss rate for WriteReq accesses +system.cpu5.l1c.demand_miss_rate::cpu5 0.859475 # miss rate for demand accesses +system.cpu5.l1c.demand_miss_rate::total 0.859475 # miss rate for demand accesses +system.cpu5.l1c.overall_miss_rate::cpu5 0.859475 # miss rate for overall accesses +system.cpu5.l1c.overall_miss_rate::total 0.859475 # miss rate for overall accesses +system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 19769.529447 # average ReadReq miss latency +system.cpu5.l1c.ReadReq_avg_miss_latency::total 19769.529447 # average ReadReq miss latency +system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 24366.124526 # average WriteReq miss latency +system.cpu5.l1c.WriteReq_avg_miss_latency::total 24366.124526 # average WriteReq miss latency +system.cpu5.l1c.demand_avg_miss_latency::cpu5 21592.562106 # average overall miss latency +system.cpu5.l1c.demand_avg_miss_latency::total 21592.562106 # average overall miss latency +system.cpu5.l1c.overall_avg_miss_latency::cpu5 21592.562106 # average overall miss latency +system.cpu5.l1c.overall_avg_miss_latency::total 21592.562106 # average overall miss latency +system.cpu5.l1c.blocked_cycles::no_mshrs 870792 # number of cycles access was blocked system.cpu5.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu5.l1c.blocked::no_mshrs 66128 # number of cycles access was blocked +system.cpu5.l1c.blocked::no_mshrs 66903 # number of cycles access was blocked system.cpu5.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu5.l1c.avg_blocked_cycles::no_mshrs 12.135298 # average number of cycles each access was blocked +system.cpu5.l1c.avg_blocked_cycles::no_mshrs 13.015739 # average number of cycles each access was blocked system.cpu5.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu5.l1c.writebacks::writebacks 9886 # number of writebacks -system.cpu5.l1c.writebacks::total 9886 # number of writebacks -system.cpu5.l1c.ReadReq_mshr_misses::cpu5 36574 # number of ReadReq MSHR misses -system.cpu5.l1c.ReadReq_mshr_misses::total 36574 # number of ReadReq MSHR misses -system.cpu5.l1c.WriteReq_mshr_misses::cpu5 24003 # number of WriteReq MSHR misses -system.cpu5.l1c.WriteReq_mshr_misses::total 24003 # number of WriteReq MSHR misses -system.cpu5.l1c.demand_mshr_misses::cpu5 60577 # number of demand (read+write) MSHR misses -system.cpu5.l1c.demand_mshr_misses::total 60577 # number of demand (read+write) MSHR misses -system.cpu5.l1c.overall_mshr_misses::cpu5 60577 # number of overall MSHR misses -system.cpu5.l1c.overall_mshr_misses::total 60577 # number of overall MSHR misses -system.cpu5.l1c.ReadReq_mshr_uncacheable::cpu5 9910 # number of ReadReq MSHR uncacheable -system.cpu5.l1c.ReadReq_mshr_uncacheable::total 9910 # number of ReadReq MSHR uncacheable -system.cpu5.l1c.WriteReq_mshr_uncacheable::cpu5 5451 # number of WriteReq MSHR uncacheable -system.cpu5.l1c.WriteReq_mshr_uncacheable::total 5451 # number of WriteReq MSHR uncacheable -system.cpu5.l1c.overall_mshr_uncacheable_misses::cpu5 15361 # number of overall MSHR uncacheable misses -system.cpu5.l1c.overall_mshr_uncacheable_misses::total 15361 # number of overall MSHR uncacheable misses -system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5 634877246 # number of ReadReq MSHR miss cycles -system.cpu5.l1c.ReadReq_mshr_miss_latency::total 634877246 # number of ReadReq MSHR miss cycles -system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5 535156053 # number of WriteReq MSHR miss cycles -system.cpu5.l1c.WriteReq_mshr_miss_latency::total 535156053 # number of WriteReq MSHR miss cycles -system.cpu5.l1c.demand_mshr_miss_latency::cpu5 1170033299 # number of demand (read+write) MSHR miss cycles -system.cpu5.l1c.demand_mshr_miss_latency::total 1170033299 # number of demand (read+write) MSHR miss cycles -system.cpu5.l1c.overall_mshr_miss_latency::cpu5 1170033299 # number of overall MSHR miss cycles -system.cpu5.l1c.overall_mshr_miss_latency::total 1170033299 # number of overall MSHR miss cycles -system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5 742019082 # number of ReadReq MSHR uncacheable cycles -system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 742019082 # number of ReadReq MSHR uncacheable cycles -system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5 742019082 # number of overall MSHR uncacheable cycles -system.cpu5.l1c.overall_mshr_uncacheable_latency::total 742019082 # number of overall MSHR uncacheable cycles -system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5 0.808748 # mshr miss rate for ReadReq accesses -system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.808748 # mshr miss rate for ReadReq accesses -system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.952538 # mshr miss rate for WriteReq accesses -system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.952538 # mshr miss rate for WriteReq accesses -system.cpu5.l1c.demand_mshr_miss_rate::cpu5 0.860200 # mshr miss rate for demand accesses -system.cpu5.l1c.demand_mshr_miss_rate::total 0.860200 # mshr miss rate for demand accesses -system.cpu5.l1c.overall_mshr_miss_rate::cpu5 0.860200 # mshr miss rate for overall accesses -system.cpu5.l1c.overall_mshr_miss_rate::total 0.860200 # mshr miss rate for overall accesses -system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 17358.704161 # average ReadReq mshr miss latency -system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 17358.704161 # average ReadReq mshr miss latency -system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 22295.381952 # average WriteReq mshr miss latency -system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 22295.381952 # average WriteReq mshr miss latency -system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 19314.810885 # average overall mshr miss latency -system.cpu5.l1c.demand_avg_mshr_miss_latency::total 19314.810885 # average overall mshr miss latency -system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 19314.810885 # average overall mshr miss latency -system.cpu5.l1c.overall_avg_mshr_miss_latency::total 19314.810885 # average overall mshr miss latency -system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5 74875.790313 # average ReadReq mshr uncacheable latency -system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total 74875.790313 # average ReadReq mshr uncacheable latency -system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 48305.389102 # average overall mshr uncacheable latency -system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total 48305.389102 # average overall mshr uncacheable latency -system.cpu6.pwrStateResidencyTicks::UNDEFINED 500337000 # Cumulative time (in ticks) in various power states -system.cpu6.num_reads 99712 # number of read accesses completed -system.cpu6.num_writes 55282 # number of write accesses completed -system.cpu6.l1c.tags.pwrStateResidencyTicks::UNDEFINED 500337000 # Cumulative time (in ticks) in various power states -system.cpu6.l1c.tags.replacements 22239 # number of replacements -system.cpu6.l1c.tags.tagsinuse 392.046110 # Cycle average of tags in use -system.cpu6.l1c.tags.total_refs 13503 # Total number of references to valid blocks. -system.cpu6.l1c.tags.sampled_refs 22637 # Sample count of references to valid blocks. -system.cpu6.l1c.tags.avg_refs 0.596501 # Average number of references to valid blocks. +system.cpu5.l1c.writebacks::writebacks 9839 # number of writebacks +system.cpu5.l1c.writebacks::total 9839 # number of writebacks +system.cpu5.l1c.ReadReq_mshr_misses::cpu5 36506 # number of ReadReq MSHR misses +system.cpu5.l1c.ReadReq_mshr_misses::total 36506 # number of ReadReq MSHR misses +system.cpu5.l1c.WriteReq_mshr_misses::cpu5 23995 # number of WriteReq MSHR misses +system.cpu5.l1c.WriteReq_mshr_misses::total 23995 # number of WriteReq MSHR misses +system.cpu5.l1c.demand_mshr_misses::cpu5 60501 # number of demand (read+write) MSHR misses +system.cpu5.l1c.demand_mshr_misses::total 60501 # number of demand (read+write) MSHR misses +system.cpu5.l1c.overall_mshr_misses::cpu5 60501 # number of overall MSHR misses +system.cpu5.l1c.overall_mshr_misses::total 60501 # number of overall MSHR misses +system.cpu5.l1c.ReadReq_mshr_uncacheable::cpu5 9845 # number of ReadReq MSHR uncacheable +system.cpu5.l1c.ReadReq_mshr_uncacheable::total 9845 # number of ReadReq MSHR uncacheable +system.cpu5.l1c.WriteReq_mshr_uncacheable::cpu5 5507 # number of WriteReq MSHR uncacheable +system.cpu5.l1c.WriteReq_mshr_uncacheable::total 5507 # number of WriteReq MSHR uncacheable +system.cpu5.l1c.overall_mshr_uncacheable_misses::cpu5 15352 # number of overall MSHR uncacheable misses +system.cpu5.l1c.overall_mshr_uncacheable_misses::total 15352 # number of overall MSHR uncacheable misses +system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5 685200442 # number of ReadReq MSHR miss cycles +system.cpu5.l1c.ReadReq_mshr_miss_latency::total 685200442 # number of ReadReq MSHR miss cycles +system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5 560672158 # number of WriteReq MSHR miss cycles +system.cpu5.l1c.WriteReq_mshr_miss_latency::total 560672158 # number of WriteReq MSHR miss cycles +system.cpu5.l1c.demand_mshr_miss_latency::cpu5 1245872600 # number of demand (read+write) MSHR miss cycles +system.cpu5.l1c.demand_mshr_miss_latency::total 1245872600 # number of demand (read+write) MSHR miss cycles +system.cpu5.l1c.overall_mshr_miss_latency::cpu5 1245872600 # number of overall MSHR miss cycles +system.cpu5.l1c.overall_mshr_miss_latency::total 1245872600 # number of overall MSHR miss cycles +system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5 769357074 # number of ReadReq MSHR uncacheable cycles +system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 769357074 # number of ReadReq MSHR uncacheable cycles +system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5 769357074 # number of overall MSHR uncacheable cycles +system.cpu5.l1c.overall_mshr_uncacheable_latency::total 769357074 # number of overall MSHR uncacheable cycles +system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5 0.807048 # mshr miss rate for ReadReq accesses +system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.807048 # mshr miss rate for ReadReq accesses +system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.953734 # mshr miss rate for WriteReq accesses +system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.953734 # mshr miss rate for WriteReq accesses +system.cpu5.l1c.demand_mshr_miss_rate::cpu5 0.859475 # mshr miss rate for demand accesses +system.cpu5.l1c.demand_mshr_miss_rate::total 0.859475 # mshr miss rate for demand accesses +system.cpu5.l1c.overall_mshr_miss_rate::cpu5 0.859475 # mshr miss rate for overall accesses +system.cpu5.l1c.overall_mshr_miss_rate::total 0.859475 # mshr miss rate for overall accesses +system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 18769.529447 # average ReadReq mshr miss latency +system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 18769.529447 # average ReadReq mshr miss latency +system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 23366.207877 # average WriteReq mshr miss latency +system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 23366.207877 # average WriteReq mshr miss latency +system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 20592.595164 # average overall mshr miss latency +system.cpu5.l1c.demand_avg_mshr_miss_latency::total 20592.595164 # average overall mshr miss latency +system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 20592.595164 # average overall mshr miss latency +system.cpu5.l1c.overall_avg_mshr_miss_latency::total 20592.595164 # average overall mshr miss latency +system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5 78146.985678 # average ReadReq mshr uncacheable latency +system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total 78146.985678 # average ReadReq mshr uncacheable latency +system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 50114.452449 # average overall mshr uncacheable latency +system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total 50114.452449 # average overall mshr uncacheable latency +system.cpu6.pwrStateResidencyTicks::UNDEFINED 521659000 # Cumulative time (in ticks) in various power states +system.cpu6.num_reads 100000 # number of read accesses completed +system.cpu6.num_writes 55102 # number of write accesses completed +system.cpu6.l1c.tags.pwrStateResidencyTicks::UNDEFINED 521659000 # Cumulative time (in ticks) in various power states +system.cpu6.l1c.tags.replacements 22254 # number of replacements +system.cpu6.l1c.tags.tagsinuse 391.922561 # Cycle average of tags in use +system.cpu6.l1c.tags.total_refs 13477 # Total number of references to valid blocks. +system.cpu6.l1c.tags.sampled_refs 22655 # Sample count of references to valid blocks. +system.cpu6.l1c.tags.avg_refs 0.594880 # Average number of references to valid blocks. system.cpu6.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu6.l1c.tags.occ_blocks::cpu6 392.046110 # Average occupied blocks per requestor -system.cpu6.l1c.tags.occ_percent::cpu6 0.765715 # Average percentage of cache occupancy -system.cpu6.l1c.tags.occ_percent::total 0.765715 # Average percentage of cache occupancy -system.cpu6.l1c.tags.occ_task_id_blocks::1024 398 # Occupied blocks per task id -system.cpu6.l1c.tags.age_task_id_blocks_1024::0 382 # Occupied blocks per task id -system.cpu6.l1c.tags.age_task_id_blocks_1024::1 16 # Occupied blocks per task id -system.cpu6.l1c.tags.occ_task_id_percent::1024 0.777344 # Percentage of cache occupancy per task id -system.cpu6.l1c.tags.tag_accesses 338073 # Number of tag accesses -system.cpu6.l1c.tags.data_accesses 338073 # Number of data accesses -system.cpu6.l1c.pwrStateResidencyTicks::UNDEFINED 500337000 # Cumulative time (in ticks) in various power states -system.cpu6.l1c.ReadReq_hits::cpu6 8758 # number of ReadReq hits -system.cpu6.l1c.ReadReq_hits::total 8758 # number of ReadReq hits -system.cpu6.l1c.WriteReq_hits::cpu6 1067 # number of WriteReq hits -system.cpu6.l1c.WriteReq_hits::total 1067 # number of WriteReq hits -system.cpu6.l1c.demand_hits::cpu6 9825 # number of demand (read+write) hits -system.cpu6.l1c.demand_hits::total 9825 # number of demand (read+write) hits -system.cpu6.l1c.overall_hits::cpu6 9825 # number of overall hits -system.cpu6.l1c.overall_hits::total 9825 # number of overall hits -system.cpu6.l1c.ReadReq_misses::cpu6 36548 # number of ReadReq misses -system.cpu6.l1c.ReadReq_misses::total 36548 # number of ReadReq misses -system.cpu6.l1c.WriteReq_misses::cpu6 23952 # number of WriteReq misses -system.cpu6.l1c.WriteReq_misses::total 23952 # number of WriteReq misses -system.cpu6.l1c.demand_misses::cpu6 60500 # number of demand (read+write) misses -system.cpu6.l1c.demand_misses::total 60500 # number of demand (read+write) misses -system.cpu6.l1c.overall_misses::cpu6 60500 # number of overall misses -system.cpu6.l1c.overall_misses::total 60500 # number of overall misses -system.cpu6.l1c.ReadReq_miss_latency::cpu6 674135322 # number of ReadReq miss cycles -system.cpu6.l1c.ReadReq_miss_latency::total 674135322 # number of ReadReq miss cycles -system.cpu6.l1c.WriteReq_miss_latency::cpu6 560982121 # number of WriteReq miss cycles -system.cpu6.l1c.WriteReq_miss_latency::total 560982121 # number of WriteReq miss cycles -system.cpu6.l1c.demand_miss_latency::cpu6 1235117443 # number of demand (read+write) miss cycles -system.cpu6.l1c.demand_miss_latency::total 1235117443 # number of demand (read+write) miss cycles -system.cpu6.l1c.overall_miss_latency::cpu6 1235117443 # number of overall miss cycles -system.cpu6.l1c.overall_miss_latency::total 1235117443 # number of overall miss cycles -system.cpu6.l1c.ReadReq_accesses::cpu6 45306 # number of ReadReq accesses(hits+misses) -system.cpu6.l1c.ReadReq_accesses::total 45306 # number of ReadReq accesses(hits+misses) -system.cpu6.l1c.WriteReq_accesses::cpu6 25019 # number of WriteReq accesses(hits+misses) -system.cpu6.l1c.WriteReq_accesses::total 25019 # number of WriteReq accesses(hits+misses) -system.cpu6.l1c.demand_accesses::cpu6 70325 # number of demand (read+write) accesses -system.cpu6.l1c.demand_accesses::total 70325 # number of demand (read+write) accesses -system.cpu6.l1c.overall_accesses::cpu6 70325 # number of overall (read+write) accesses -system.cpu6.l1c.overall_accesses::total 70325 # number of overall (read+write) accesses -system.cpu6.l1c.ReadReq_miss_rate::cpu6 0.806692 # miss rate for ReadReq accesses -system.cpu6.l1c.ReadReq_miss_rate::total 0.806692 # miss rate for ReadReq accesses -system.cpu6.l1c.WriteReq_miss_rate::cpu6 0.957352 # miss rate for WriteReq accesses -system.cpu6.l1c.WriteReq_miss_rate::total 0.957352 # miss rate for WriteReq accesses -system.cpu6.l1c.demand_miss_rate::cpu6 0.860292 # miss rate for demand accesses -system.cpu6.l1c.demand_miss_rate::total 0.860292 # miss rate for demand accesses -system.cpu6.l1c.overall_miss_rate::cpu6 0.860292 # miss rate for overall accesses -system.cpu6.l1c.overall_miss_rate::total 0.860292 # miss rate for overall accesses -system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 18445.204170 # average ReadReq miss latency -system.cpu6.l1c.ReadReq_avg_miss_latency::total 18445.204170 # average ReadReq miss latency -system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 23421.097236 # average WriteReq miss latency -system.cpu6.l1c.WriteReq_avg_miss_latency::total 23421.097236 # average WriteReq miss latency -system.cpu6.l1c.demand_avg_miss_latency::cpu6 20415.164347 # average overall miss latency -system.cpu6.l1c.demand_avg_miss_latency::total 20415.164347 # average overall miss latency -system.cpu6.l1c.overall_avg_miss_latency::cpu6 20415.164347 # average overall miss latency -system.cpu6.l1c.overall_avg_miss_latency::total 20415.164347 # average overall miss latency -system.cpu6.l1c.blocked_cycles::no_mshrs 802988 # number of cycles access was blocked +system.cpu6.l1c.tags.occ_blocks::cpu6 391.922561 # Average occupied blocks per requestor +system.cpu6.l1c.tags.occ_percent::cpu6 0.765474 # Average percentage of cache occupancy +system.cpu6.l1c.tags.occ_percent::total 0.765474 # Average percentage of cache occupancy +system.cpu6.l1c.tags.occ_task_id_blocks::1024 401 # Occupied blocks per task id +system.cpu6.l1c.tags.age_task_id_blocks_1024::0 393 # Occupied blocks per task id +system.cpu6.l1c.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id +system.cpu6.l1c.tags.occ_task_id_percent::1024 0.783203 # Percentage of cache occupancy per task id +system.cpu6.l1c.tags.tag_accesses 337953 # Number of tag accesses +system.cpu6.l1c.tags.data_accesses 337953 # Number of data accesses +system.cpu6.l1c.pwrStateResidencyTicks::UNDEFINED 521659000 # Cumulative time (in ticks) in various power states +system.cpu6.l1c.ReadReq_hits::cpu6 8677 # number of ReadReq hits +system.cpu6.l1c.ReadReq_hits::total 8677 # number of ReadReq hits +system.cpu6.l1c.WriteReq_hits::cpu6 1226 # number of WriteReq hits +system.cpu6.l1c.WriteReq_hits::total 1226 # number of WriteReq hits +system.cpu6.l1c.demand_hits::cpu6 9903 # number of demand (read+write) hits +system.cpu6.l1c.demand_hits::total 9903 # number of demand (read+write) hits +system.cpu6.l1c.overall_hits::cpu6 9903 # number of overall hits +system.cpu6.l1c.overall_hits::total 9903 # number of overall hits +system.cpu6.l1c.ReadReq_misses::cpu6 36565 # number of ReadReq misses +system.cpu6.l1c.ReadReq_misses::total 36565 # number of ReadReq misses +system.cpu6.l1c.WriteReq_misses::cpu6 23825 # number of WriteReq misses +system.cpu6.l1c.WriteReq_misses::total 23825 # number of WriteReq misses +system.cpu6.l1c.demand_misses::cpu6 60390 # number of demand (read+write) misses +system.cpu6.l1c.demand_misses::total 60390 # number of demand (read+write) misses +system.cpu6.l1c.overall_misses::cpu6 60390 # number of overall misses +system.cpu6.l1c.overall_misses::total 60390 # number of overall misses +system.cpu6.l1c.ReadReq_miss_latency::cpu6 723690383 # number of ReadReq miss cycles +system.cpu6.l1c.ReadReq_miss_latency::total 723690383 # number of ReadReq miss cycles +system.cpu6.l1c.WriteReq_miss_latency::cpu6 577264297 # number of WriteReq miss cycles +system.cpu6.l1c.WriteReq_miss_latency::total 577264297 # number of WriteReq miss cycles +system.cpu6.l1c.demand_miss_latency::cpu6 1300954680 # number of demand (read+write) miss cycles +system.cpu6.l1c.demand_miss_latency::total 1300954680 # number of demand (read+write) miss cycles +system.cpu6.l1c.overall_miss_latency::cpu6 1300954680 # number of overall miss cycles +system.cpu6.l1c.overall_miss_latency::total 1300954680 # number of overall miss cycles +system.cpu6.l1c.ReadReq_accesses::cpu6 45242 # number of ReadReq accesses(hits+misses) +system.cpu6.l1c.ReadReq_accesses::total 45242 # number of ReadReq accesses(hits+misses) +system.cpu6.l1c.WriteReq_accesses::cpu6 25051 # number of WriteReq accesses(hits+misses) +system.cpu6.l1c.WriteReq_accesses::total 25051 # number of WriteReq accesses(hits+misses) +system.cpu6.l1c.demand_accesses::cpu6 70293 # number of demand (read+write) accesses +system.cpu6.l1c.demand_accesses::total 70293 # number of demand (read+write) accesses +system.cpu6.l1c.overall_accesses::cpu6 70293 # number of overall (read+write) accesses +system.cpu6.l1c.overall_accesses::total 70293 # number of overall (read+write) accesses +system.cpu6.l1c.ReadReq_miss_rate::cpu6 0.808209 # miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_miss_rate::total 0.808209 # miss rate for ReadReq accesses +system.cpu6.l1c.WriteReq_miss_rate::cpu6 0.951060 # miss rate for WriteReq accesses +system.cpu6.l1c.WriteReq_miss_rate::total 0.951060 # miss rate for WriteReq accesses +system.cpu6.l1c.demand_miss_rate::cpu6 0.859118 # miss rate for demand accesses +system.cpu6.l1c.demand_miss_rate::total 0.859118 # miss rate for demand accesses +system.cpu6.l1c.overall_miss_rate::cpu6 0.859118 # miss rate for overall accesses +system.cpu6.l1c.overall_miss_rate::total 0.859118 # miss rate for overall accesses +system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 19791.887953 # average ReadReq miss latency +system.cpu6.l1c.ReadReq_avg_miss_latency::total 19791.887953 # average ReadReq miss latency +system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 24229.351396 # average WriteReq miss latency +system.cpu6.l1c.WriteReq_avg_miss_latency::total 24229.351396 # average WriteReq miss latency +system.cpu6.l1c.demand_avg_miss_latency::cpu6 21542.551416 # average overall miss latency +system.cpu6.l1c.demand_avg_miss_latency::total 21542.551416 # average overall miss latency +system.cpu6.l1c.overall_avg_miss_latency::cpu6 21542.551416 # average overall miss latency +system.cpu6.l1c.overall_avg_miss_latency::total 21542.551416 # average overall miss latency +system.cpu6.l1c.blocked_cycles::no_mshrs 870051 # number of cycles access was blocked system.cpu6.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu6.l1c.blocked::no_mshrs 65839 # number of cycles access was blocked +system.cpu6.l1c.blocked::no_mshrs 66789 # number of cycles access was blocked system.cpu6.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu6.l1c.avg_blocked_cycles::no_mshrs 12.196236 # average number of cycles each access was blocked +system.cpu6.l1c.avg_blocked_cycles::no_mshrs 13.026861 # average number of cycles each access was blocked system.cpu6.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu6.l1c.writebacks::writebacks 9826 # number of writebacks -system.cpu6.l1c.writebacks::total 9826 # number of writebacks -system.cpu6.l1c.ReadReq_mshr_misses::cpu6 36548 # number of ReadReq MSHR misses -system.cpu6.l1c.ReadReq_mshr_misses::total 36548 # number of ReadReq MSHR misses -system.cpu6.l1c.WriteReq_mshr_misses::cpu6 23952 # number of WriteReq MSHR misses -system.cpu6.l1c.WriteReq_mshr_misses::total 23952 # number of WriteReq MSHR misses -system.cpu6.l1c.demand_mshr_misses::cpu6 60500 # number of demand (read+write) MSHR misses -system.cpu6.l1c.demand_mshr_misses::total 60500 # number of demand (read+write) MSHR misses -system.cpu6.l1c.overall_mshr_misses::cpu6 60500 # number of overall MSHR misses -system.cpu6.l1c.overall_mshr_misses::total 60500 # number of overall MSHR misses -system.cpu6.l1c.ReadReq_mshr_uncacheable::cpu6 9861 # number of ReadReq MSHR uncacheable -system.cpu6.l1c.ReadReq_mshr_uncacheable::total 9861 # number of ReadReq MSHR uncacheable -system.cpu6.l1c.WriteReq_mshr_uncacheable::cpu6 5592 # number of WriteReq MSHR uncacheable -system.cpu6.l1c.WriteReq_mshr_uncacheable::total 5592 # number of WriteReq MSHR uncacheable -system.cpu6.l1c.overall_mshr_uncacheable_misses::cpu6 15453 # number of overall MSHR uncacheable misses -system.cpu6.l1c.overall_mshr_uncacheable_misses::total 15453 # number of overall MSHR uncacheable misses -system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6 637587322 # number of ReadReq MSHR miss cycles -system.cpu6.l1c.ReadReq_mshr_miss_latency::total 637587322 # number of ReadReq MSHR miss cycles -system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6 537030121 # number of WriteReq MSHR miss cycles -system.cpu6.l1c.WriteReq_mshr_miss_latency::total 537030121 # number of WriteReq MSHR miss cycles -system.cpu6.l1c.demand_mshr_miss_latency::cpu6 1174617443 # number of demand (read+write) MSHR miss cycles -system.cpu6.l1c.demand_mshr_miss_latency::total 1174617443 # number of demand (read+write) MSHR miss cycles -system.cpu6.l1c.overall_mshr_miss_latency::cpu6 1174617443 # number of overall MSHR miss cycles -system.cpu6.l1c.overall_mshr_miss_latency::total 1174617443 # number of overall MSHR miss cycles -system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6 737828201 # number of ReadReq MSHR uncacheable cycles -system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total 737828201 # number of ReadReq MSHR uncacheable cycles -system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6 737828201 # number of overall MSHR uncacheable cycles -system.cpu6.l1c.overall_mshr_uncacheable_latency::total 737828201 # number of overall MSHR uncacheable cycles -system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6 0.806692 # mshr miss rate for ReadReq accesses -system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.806692 # mshr miss rate for ReadReq accesses -system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6 0.957352 # mshr miss rate for WriteReq accesses -system.cpu6.l1c.WriteReq_mshr_miss_rate::total 0.957352 # mshr miss rate for WriteReq accesses -system.cpu6.l1c.demand_mshr_miss_rate::cpu6 0.860292 # mshr miss rate for demand accesses -system.cpu6.l1c.demand_mshr_miss_rate::total 0.860292 # mshr miss rate for demand accesses -system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.860292 # mshr miss rate for overall accesses -system.cpu6.l1c.overall_mshr_miss_rate::total 0.860292 # mshr miss rate for overall accesses -system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 17445.204170 # average ReadReq mshr miss latency -system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 17445.204170 # average ReadReq mshr miss latency -system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 22421.097236 # average WriteReq mshr miss latency -system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 22421.097236 # average WriteReq mshr miss latency -system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 19415.164347 # average overall mshr miss latency -system.cpu6.l1c.demand_avg_mshr_miss_latency::total 19415.164347 # average overall mshr miss latency -system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 19415.164347 # average overall mshr miss latency -system.cpu6.l1c.overall_avg_mshr_miss_latency::total 19415.164347 # average overall mshr miss latency -system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 74822.857824 # average ReadReq mshr uncacheable latency -system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total 74822.857824 # average ReadReq mshr uncacheable latency -system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 47746.599431 # average overall mshr uncacheable latency -system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total 47746.599431 # average overall mshr uncacheable latency -system.cpu7.pwrStateResidencyTicks::UNDEFINED 500337000 # Cumulative time (in ticks) in various power states -system.cpu7.num_reads 99031 # number of read accesses completed -system.cpu7.num_writes 54931 # number of write accesses completed -system.cpu7.l1c.tags.pwrStateResidencyTicks::UNDEFINED 500337000 # Cumulative time (in ticks) in various power states -system.cpu7.l1c.tags.replacements 22638 # number of replacements -system.cpu7.l1c.tags.tagsinuse 391.993848 # Cycle average of tags in use -system.cpu7.l1c.tags.total_refs 13556 # Total number of references to valid blocks. -system.cpu7.l1c.tags.sampled_refs 23038 # Sample count of references to valid blocks. -system.cpu7.l1c.tags.avg_refs 0.588419 # Average number of references to valid blocks. +system.cpu6.l1c.writebacks::writebacks 9787 # number of writebacks +system.cpu6.l1c.writebacks::total 9787 # number of writebacks +system.cpu6.l1c.ReadReq_mshr_misses::cpu6 36565 # number of ReadReq MSHR misses +system.cpu6.l1c.ReadReq_mshr_misses::total 36565 # number of ReadReq MSHR misses +system.cpu6.l1c.WriteReq_mshr_misses::cpu6 23825 # number of WriteReq MSHR misses +system.cpu6.l1c.WriteReq_mshr_misses::total 23825 # number of WriteReq MSHR misses +system.cpu6.l1c.demand_mshr_misses::cpu6 60390 # number of demand (read+write) MSHR misses +system.cpu6.l1c.demand_mshr_misses::total 60390 # number of demand (read+write) MSHR misses +system.cpu6.l1c.overall_mshr_misses::cpu6 60390 # number of overall MSHR misses +system.cpu6.l1c.overall_mshr_misses::total 60390 # number of overall MSHR misses +system.cpu6.l1c.ReadReq_mshr_uncacheable::cpu6 9904 # number of ReadReq MSHR uncacheable +system.cpu6.l1c.ReadReq_mshr_uncacheable::total 9904 # number of ReadReq MSHR uncacheable +system.cpu6.l1c.WriteReq_mshr_uncacheable::cpu6 5506 # number of WriteReq MSHR uncacheable +system.cpu6.l1c.WriteReq_mshr_uncacheable::total 5506 # number of WriteReq MSHR uncacheable +system.cpu6.l1c.overall_mshr_uncacheable_misses::cpu6 15410 # number of overall MSHR uncacheable misses +system.cpu6.l1c.overall_mshr_uncacheable_misses::total 15410 # number of overall MSHR uncacheable misses +system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6 687127383 # number of ReadReq MSHR miss cycles +system.cpu6.l1c.ReadReq_mshr_miss_latency::total 687127383 # number of ReadReq MSHR miss cycles +system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6 553439297 # number of WriteReq MSHR miss cycles +system.cpu6.l1c.WriteReq_mshr_miss_latency::total 553439297 # number of WriteReq MSHR miss cycles +system.cpu6.l1c.demand_mshr_miss_latency::cpu6 1240566680 # number of demand (read+write) MSHR miss cycles +system.cpu6.l1c.demand_mshr_miss_latency::total 1240566680 # number of demand (read+write) MSHR miss cycles +system.cpu6.l1c.overall_mshr_miss_latency::cpu6 1240566680 # number of overall MSHR miss cycles +system.cpu6.l1c.overall_mshr_miss_latency::total 1240566680 # number of overall MSHR miss cycles +system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6 773835448 # number of ReadReq MSHR uncacheable cycles +system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total 773835448 # number of ReadReq MSHR uncacheable cycles +system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6 773835448 # number of overall MSHR uncacheable cycles +system.cpu6.l1c.overall_mshr_uncacheable_latency::total 773835448 # number of overall MSHR uncacheable cycles +system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6 0.808209 # mshr miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.808209 # mshr miss rate for ReadReq accesses +system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6 0.951060 # mshr miss rate for WriteReq accesses +system.cpu6.l1c.WriteReq_mshr_miss_rate::total 0.951060 # mshr miss rate for WriteReq accesses +system.cpu6.l1c.demand_mshr_miss_rate::cpu6 0.859118 # mshr miss rate for demand accesses +system.cpu6.l1c.demand_mshr_miss_rate::total 0.859118 # mshr miss rate for demand accesses +system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.859118 # mshr miss rate for overall accesses +system.cpu6.l1c.overall_mshr_miss_rate::total 0.859118 # mshr miss rate for overall accesses +system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 18791.942650 # average ReadReq mshr miss latency +system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 18791.942650 # average ReadReq mshr miss latency +system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 23229.351396 # average WriteReq mshr miss latency +system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 23229.351396 # average WriteReq mshr miss latency +system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 20542.584534 # average overall mshr miss latency +system.cpu6.l1c.demand_avg_mshr_miss_latency::total 20542.584534 # average overall mshr miss latency +system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 20542.584534 # average overall mshr miss latency +system.cpu6.l1c.overall_avg_mshr_miss_latency::total 20542.584534 # average overall mshr miss latency +system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 78133.627625 # average ReadReq mshr uncacheable latency +system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total 78133.627625 # average ReadReq mshr uncacheable latency +system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 50216.446982 # average overall mshr uncacheable latency +system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total 50216.446982 # average overall mshr uncacheable latency +system.cpu7.pwrStateResidencyTicks::UNDEFINED 521659000 # Cumulative time (in ticks) in various power states +system.cpu7.num_reads 99606 # number of read accesses completed +system.cpu7.num_writes 54773 # number of write accesses completed +system.cpu7.l1c.tags.pwrStateResidencyTicks::UNDEFINED 521659000 # Cumulative time (in ticks) in various power states +system.cpu7.l1c.tags.replacements 21949 # number of replacements +system.cpu7.l1c.tags.tagsinuse 391.189669 # Cycle average of tags in use +system.cpu7.l1c.tags.total_refs 13361 # Total number of references to valid blocks. +system.cpu7.l1c.tags.sampled_refs 22347 # Sample count of references to valid blocks. +system.cpu7.l1c.tags.avg_refs 0.597888 # Average number of references to valid blocks. system.cpu7.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu7.l1c.tags.occ_blocks::cpu7 391.993848 # Average occupied blocks per requestor -system.cpu7.l1c.tags.occ_percent::cpu7 0.765613 # Average percentage of cache occupancy -system.cpu7.l1c.tags.occ_percent::total 0.765613 # Average percentage of cache occupancy -system.cpu7.l1c.tags.occ_task_id_blocks::1024 400 # Occupied blocks per task id -system.cpu7.l1c.tags.age_task_id_blocks_1024::0 386 # Occupied blocks per task id -system.cpu7.l1c.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id -system.cpu7.l1c.tags.occ_task_id_percent::1024 0.781250 # Percentage of cache occupancy per task id -system.cpu7.l1c.tags.tag_accesses 339734 # Number of tag accesses -system.cpu7.l1c.tags.data_accesses 339734 # Number of data accesses -system.cpu7.l1c.pwrStateResidencyTicks::UNDEFINED 500337000 # Cumulative time (in ticks) in various power states -system.cpu7.l1c.ReadReq_hits::cpu7 8818 # number of ReadReq hits -system.cpu7.l1c.ReadReq_hits::total 8818 # number of ReadReq hits +system.cpu7.l1c.tags.occ_blocks::cpu7 391.189669 # Average occupied blocks per requestor +system.cpu7.l1c.tags.occ_percent::cpu7 0.764042 # Average percentage of cache occupancy +system.cpu7.l1c.tags.occ_percent::total 0.764042 # Average percentage of cache occupancy +system.cpu7.l1c.tags.occ_task_id_blocks::1024 398 # Occupied blocks per task id +system.cpu7.l1c.tags.age_task_id_blocks_1024::0 378 # Occupied blocks per task id +system.cpu7.l1c.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id +system.cpu7.l1c.tags.occ_task_id_percent::1024 0.777344 # Percentage of cache occupancy per task id +system.cpu7.l1c.tags.tag_accesses 335877 # Number of tag accesses +system.cpu7.l1c.tags.data_accesses 335877 # Number of data accesses +system.cpu7.l1c.pwrStateResidencyTicks::UNDEFINED 521659000 # Cumulative time (in ticks) in various power states +system.cpu7.l1c.ReadReq_hits::cpu7 8692 # number of ReadReq hits +system.cpu7.l1c.ReadReq_hits::total 8692 # number of ReadReq hits system.cpu7.l1c.WriteReq_hits::cpu7 1148 # number of WriteReq hits system.cpu7.l1c.WriteReq_hits::total 1148 # number of WriteReq hits -system.cpu7.l1c.demand_hits::cpu7 9966 # number of demand (read+write) hits -system.cpu7.l1c.demand_hits::total 9966 # number of demand (read+write) hits -system.cpu7.l1c.overall_hits::cpu7 9966 # number of overall hits -system.cpu7.l1c.overall_hits::total 9966 # number of overall hits -system.cpu7.l1c.ReadReq_misses::cpu7 36554 # number of ReadReq misses -system.cpu7.l1c.ReadReq_misses::total 36554 # number of ReadReq misses -system.cpu7.l1c.WriteReq_misses::cpu7 24149 # number of WriteReq misses -system.cpu7.l1c.WriteReq_misses::total 24149 # number of WriteReq misses -system.cpu7.l1c.demand_misses::cpu7 60703 # number of demand (read+write) misses -system.cpu7.l1c.demand_misses::total 60703 # number of demand (read+write) misses -system.cpu7.l1c.overall_misses::cpu7 60703 # number of overall misses -system.cpu7.l1c.overall_misses::total 60703 # number of overall misses -system.cpu7.l1c.ReadReq_miss_latency::cpu7 675691654 # number of ReadReq miss cycles -system.cpu7.l1c.ReadReq_miss_latency::total 675691654 # number of ReadReq miss cycles -system.cpu7.l1c.WriteReq_miss_latency::cpu7 565139421 # number of WriteReq miss cycles -system.cpu7.l1c.WriteReq_miss_latency::total 565139421 # number of WriteReq miss cycles -system.cpu7.l1c.demand_miss_latency::cpu7 1240831075 # number of demand (read+write) miss cycles -system.cpu7.l1c.demand_miss_latency::total 1240831075 # number of demand (read+write) miss cycles -system.cpu7.l1c.overall_miss_latency::cpu7 1240831075 # number of overall miss cycles -system.cpu7.l1c.overall_miss_latency::total 1240831075 # number of overall miss cycles -system.cpu7.l1c.ReadReq_accesses::cpu7 45372 # number of ReadReq accesses(hits+misses) -system.cpu7.l1c.ReadReq_accesses::total 45372 # number of ReadReq accesses(hits+misses) -system.cpu7.l1c.WriteReq_accesses::cpu7 25297 # number of WriteReq accesses(hits+misses) -system.cpu7.l1c.WriteReq_accesses::total 25297 # number of WriteReq accesses(hits+misses) -system.cpu7.l1c.demand_accesses::cpu7 70669 # number of demand (read+write) accesses -system.cpu7.l1c.demand_accesses::total 70669 # number of demand (read+write) accesses -system.cpu7.l1c.overall_accesses::cpu7 70669 # number of overall (read+write) accesses -system.cpu7.l1c.overall_accesses::total 70669 # number of overall (read+write) accesses -system.cpu7.l1c.ReadReq_miss_rate::cpu7 0.805651 # miss rate for ReadReq accesses -system.cpu7.l1c.ReadReq_miss_rate::total 0.805651 # miss rate for ReadReq accesses -system.cpu7.l1c.WriteReq_miss_rate::cpu7 0.954619 # miss rate for WriteReq accesses -system.cpu7.l1c.WriteReq_miss_rate::total 0.954619 # miss rate for WriteReq accesses -system.cpu7.l1c.demand_miss_rate::cpu7 0.858976 # miss rate for demand accesses -system.cpu7.l1c.demand_miss_rate::total 0.858976 # miss rate for demand accesses -system.cpu7.l1c.overall_miss_rate::cpu7 0.858976 # miss rate for overall accesses -system.cpu7.l1c.overall_miss_rate::total 0.858976 # miss rate for overall accesses -system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 18484.752804 # average ReadReq miss latency -system.cpu7.l1c.ReadReq_avg_miss_latency::total 18484.752804 # average ReadReq miss latency -system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 23402.187296 # average WriteReq miss latency -system.cpu7.l1c.WriteReq_avg_miss_latency::total 23402.187296 # average WriteReq miss latency -system.cpu7.l1c.demand_avg_miss_latency::cpu7 20441.017330 # average overall miss latency -system.cpu7.l1c.demand_avg_miss_latency::total 20441.017330 # average overall miss latency -system.cpu7.l1c.overall_avg_miss_latency::cpu7 20441.017330 # average overall miss latency -system.cpu7.l1c.overall_avg_miss_latency::total 20441.017330 # average overall miss latency -system.cpu7.l1c.blocked_cycles::no_mshrs 799894 # number of cycles access was blocked +system.cpu7.l1c.demand_hits::cpu7 9840 # number of demand (read+write) hits +system.cpu7.l1c.demand_hits::total 9840 # number of demand (read+write) hits +system.cpu7.l1c.overall_hits::cpu7 9840 # number of overall hits +system.cpu7.l1c.overall_hits::total 9840 # number of overall hits +system.cpu7.l1c.ReadReq_misses::cpu7 36424 # number of ReadReq misses +system.cpu7.l1c.ReadReq_misses::total 36424 # number of ReadReq misses +system.cpu7.l1c.WriteReq_misses::cpu7 23598 # number of WriteReq misses +system.cpu7.l1c.WriteReq_misses::total 23598 # number of WriteReq misses +system.cpu7.l1c.demand_misses::cpu7 60022 # number of demand (read+write) misses +system.cpu7.l1c.demand_misses::total 60022 # number of demand (read+write) misses +system.cpu7.l1c.overall_misses::cpu7 60022 # number of overall misses +system.cpu7.l1c.overall_misses::total 60022 # number of overall misses +system.cpu7.l1c.ReadReq_miss_latency::cpu7 721113865 # number of ReadReq miss cycles +system.cpu7.l1c.ReadReq_miss_latency::total 721113865 # number of ReadReq miss cycles +system.cpu7.l1c.WriteReq_miss_latency::cpu7 575330708 # number of WriteReq miss cycles +system.cpu7.l1c.WriteReq_miss_latency::total 575330708 # number of WriteReq miss cycles +system.cpu7.l1c.demand_miss_latency::cpu7 1296444573 # number of demand (read+write) miss cycles +system.cpu7.l1c.demand_miss_latency::total 1296444573 # number of demand (read+write) miss cycles +system.cpu7.l1c.overall_miss_latency::cpu7 1296444573 # number of overall miss cycles +system.cpu7.l1c.overall_miss_latency::total 1296444573 # number of overall miss cycles +system.cpu7.l1c.ReadReq_accesses::cpu7 45116 # number of ReadReq accesses(hits+misses) +system.cpu7.l1c.ReadReq_accesses::total 45116 # number of ReadReq accesses(hits+misses) +system.cpu7.l1c.WriteReq_accesses::cpu7 24746 # number of WriteReq accesses(hits+misses) +system.cpu7.l1c.WriteReq_accesses::total 24746 # number of WriteReq accesses(hits+misses) +system.cpu7.l1c.demand_accesses::cpu7 69862 # number of demand (read+write) accesses +system.cpu7.l1c.demand_accesses::total 69862 # number of demand (read+write) accesses +system.cpu7.l1c.overall_accesses::cpu7 69862 # number of overall (read+write) accesses +system.cpu7.l1c.overall_accesses::total 69862 # number of overall (read+write) accesses +system.cpu7.l1c.ReadReq_miss_rate::cpu7 0.807341 # miss rate for ReadReq accesses +system.cpu7.l1c.ReadReq_miss_rate::total 0.807341 # miss rate for ReadReq accesses +system.cpu7.l1c.WriteReq_miss_rate::cpu7 0.953609 # miss rate for WriteReq accesses +system.cpu7.l1c.WriteReq_miss_rate::total 0.953609 # miss rate for WriteReq accesses +system.cpu7.l1c.demand_miss_rate::cpu7 0.859151 # miss rate for demand accesses +system.cpu7.l1c.demand_miss_rate::total 0.859151 # miss rate for demand accesses +system.cpu7.l1c.overall_miss_rate::cpu7 0.859151 # miss rate for overall accesses +system.cpu7.l1c.overall_miss_rate::total 0.859151 # miss rate for overall accesses +system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 19797.766994 # average ReadReq miss latency +system.cpu7.l1c.ReadReq_avg_miss_latency::total 19797.766994 # average ReadReq miss latency +system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 24380.485973 # average WriteReq miss latency +system.cpu7.l1c.WriteReq_avg_miss_latency::total 24380.485973 # average WriteReq miss latency +system.cpu7.l1c.demand_avg_miss_latency::cpu7 21599.489737 # average overall miss latency +system.cpu7.l1c.demand_avg_miss_latency::total 21599.489737 # average overall miss latency +system.cpu7.l1c.overall_avg_miss_latency::cpu7 21599.489737 # average overall miss latency +system.cpu7.l1c.overall_avg_miss_latency::total 21599.489737 # average overall miss latency +system.cpu7.l1c.blocked_cycles::no_mshrs 871786 # number of cycles access was blocked system.cpu7.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu7.l1c.blocked::no_mshrs 65859 # number of cycles access was blocked +system.cpu7.l1c.blocked::no_mshrs 66469 # number of cycles access was blocked system.cpu7.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu7.l1c.avg_blocked_cycles::no_mshrs 12.145553 # average number of cycles each access was blocked +system.cpu7.l1c.avg_blocked_cycles::no_mshrs 13.115678 # average number of cycles each access was blocked system.cpu7.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu7.l1c.writebacks::writebacks 9912 # number of writebacks -system.cpu7.l1c.writebacks::total 9912 # number of writebacks -system.cpu7.l1c.ReadReq_mshr_misses::cpu7 36554 # number of ReadReq MSHR misses -system.cpu7.l1c.ReadReq_mshr_misses::total 36554 # number of ReadReq MSHR misses -system.cpu7.l1c.WriteReq_mshr_misses::cpu7 24149 # number of WriteReq MSHR misses -system.cpu7.l1c.WriteReq_mshr_misses::total 24149 # number of WriteReq MSHR misses -system.cpu7.l1c.demand_mshr_misses::cpu7 60703 # number of demand (read+write) MSHR misses -system.cpu7.l1c.demand_mshr_misses::total 60703 # number of demand (read+write) MSHR misses -system.cpu7.l1c.overall_mshr_misses::cpu7 60703 # number of overall MSHR misses -system.cpu7.l1c.overall_mshr_misses::total 60703 # number of overall MSHR misses -system.cpu7.l1c.ReadReq_mshr_uncacheable::cpu7 9740 # number of ReadReq MSHR uncacheable -system.cpu7.l1c.ReadReq_mshr_uncacheable::total 9740 # number of ReadReq MSHR uncacheable -system.cpu7.l1c.WriteReq_mshr_uncacheable::cpu7 5359 # number of WriteReq MSHR uncacheable -system.cpu7.l1c.WriteReq_mshr_uncacheable::total 5359 # number of WriteReq MSHR uncacheable -system.cpu7.l1c.overall_mshr_uncacheable_misses::cpu7 15099 # number of overall MSHR uncacheable misses -system.cpu7.l1c.overall_mshr_uncacheable_misses::total 15099 # number of overall MSHR uncacheable misses -system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7 639138654 # number of ReadReq MSHR miss cycles -system.cpu7.l1c.ReadReq_mshr_miss_latency::total 639138654 # number of ReadReq MSHR miss cycles -system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7 540990421 # number of WriteReq MSHR miss cycles -system.cpu7.l1c.WriteReq_mshr_miss_latency::total 540990421 # number of WriteReq MSHR miss cycles -system.cpu7.l1c.demand_mshr_miss_latency::cpu7 1180129075 # number of demand (read+write) MSHR miss cycles -system.cpu7.l1c.demand_mshr_miss_latency::total 1180129075 # number of demand (read+write) MSHR miss cycles -system.cpu7.l1c.overall_mshr_miss_latency::cpu7 1180129075 # number of overall MSHR miss cycles -system.cpu7.l1c.overall_mshr_miss_latency::total 1180129075 # number of overall MSHR miss cycles -system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 730529776 # number of ReadReq MSHR uncacheable cycles -system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 730529776 # number of ReadReq MSHR uncacheable cycles -system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 730529776 # number of overall MSHR uncacheable cycles -system.cpu7.l1c.overall_mshr_uncacheable_latency::total 730529776 # number of overall MSHR uncacheable cycles -system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.805651 # mshr miss rate for ReadReq accesses -system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.805651 # mshr miss rate for ReadReq accesses -system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.954619 # mshr miss rate for WriteReq accesses -system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.954619 # mshr miss rate for WriteReq accesses -system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.858976 # mshr miss rate for demand accesses -system.cpu7.l1c.demand_mshr_miss_rate::total 0.858976 # mshr miss rate for demand accesses -system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.858976 # mshr miss rate for overall accesses -system.cpu7.l1c.overall_mshr_miss_rate::total 0.858976 # mshr miss rate for overall accesses -system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 17484.780161 # average ReadReq mshr miss latency -system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 17484.780161 # average ReadReq mshr miss latency -system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 22402.187296 # average WriteReq mshr miss latency -system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 22402.187296 # average WriteReq mshr miss latency -system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 19441.033804 # average overall mshr miss latency -system.cpu7.l1c.demand_avg_mshr_miss_latency::total 19441.033804 # average overall mshr miss latency -system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 19441.033804 # average overall mshr miss latency -system.cpu7.l1c.overall_avg_mshr_miss_latency::total 19441.033804 # average overall mshr miss latency -system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7 75003.057084 # average ReadReq mshr uncacheable latency -system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total 75003.057084 # average ReadReq mshr uncacheable latency -system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::cpu7 48382.659514 # average overall mshr uncacheable latency -system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::total 48382.659514 # average overall mshr uncacheable latency -system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 500337000 # Cumulative time (in ticks) in various power states -system.l2c.tags.replacements 13688 # number of replacements -system.l2c.tags.tagsinuse 782.559938 # Cycle average of tags in use -system.l2c.tags.total_refs 164623 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 14478 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 11.370562 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 726.348525 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0 6.677170 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1 6.765222 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2 6.924842 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3 7.010620 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu4 7.585654 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu5 6.814501 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu6 7.441816 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu7 6.991588 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.709325 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0 0.006521 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1 0.006607 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2 0.006763 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3 0.006846 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu4 0.007408 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu5 0.006655 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu6 0.007267 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu7 0.006828 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.764219 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 790 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 664 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 126 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.771484 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 2107372 # Number of tag accesses -system.l2c.tags.data_accesses 2107372 # Number of data accesses -system.l2c.pwrStateResidencyTicks::UNDEFINED 500337000 # Cumulative time (in ticks) in various power states -system.l2c.WritebackDirty_hits::writebacks 77671 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 77671 # number of WritebackDirty hits -system.l2c.UpgradeReq_hits::cpu0 272 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1 284 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu2 276 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu3 280 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu4 255 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu5 283 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu6 239 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu7 262 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 2151 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0 1876 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1 1780 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2 1805 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu3 1782 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu4 1816 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu5 1727 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu6 1803 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu7 1809 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 14398 # number of ReadExReq hits -system.l2c.ReadSharedReq_hits::cpu0 10873 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1 10958 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu2 10812 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu3 11007 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu4 10755 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu5 10989 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu6 11012 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu7 10808 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 87214 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0 12749 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1 12738 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2 12617 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3 12789 # number of demand (read+write) hits -system.l2c.demand_hits::cpu4 12571 # number of demand (read+write) hits -system.l2c.demand_hits::cpu5 12716 # number of demand (read+write) hits -system.l2c.demand_hits::cpu6 12815 # number of demand (read+write) hits -system.l2c.demand_hits::cpu7 12617 # number of demand (read+write) hits -system.l2c.demand_hits::total 101612 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0 12749 # number of overall hits -system.l2c.overall_hits::cpu1 12738 # number of overall hits -system.l2c.overall_hits::cpu2 12617 # number of overall hits -system.l2c.overall_hits::cpu3 12789 # number of overall hits -system.l2c.overall_hits::cpu4 12571 # number of overall hits -system.l2c.overall_hits::cpu5 12716 # number of overall hits -system.l2c.overall_hits::cpu6 12815 # number of overall hits -system.l2c.overall_hits::cpu7 12617 # number of overall hits -system.l2c.overall_hits::total 101612 # number of overall hits -system.l2c.UpgradeReq_misses::cpu0 2119 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1 2003 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2 2061 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu3 2101 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu4 1934 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu5 2026 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu6 2139 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu7 2027 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 16410 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu0 4596 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1 4672 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu2 4641 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu3 4561 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu4 4696 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu5 4677 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu6 4637 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu7 4651 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 37131 # number of ReadExReq misses -system.l2c.ReadSharedReq_misses::cpu0 698 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1 712 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu2 734 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu3 737 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu4 740 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu5 681 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu6 738 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu7 697 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::total 5737 # number of ReadSharedReq misses -system.l2c.demand_misses::cpu0 5294 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1 5384 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2 5375 # number of demand (read+write) misses -system.l2c.demand_misses::cpu3 5298 # number of demand (read+write) misses -system.l2c.demand_misses::cpu4 5436 # number of demand (read+write) misses -system.l2c.demand_misses::cpu5 5358 # number of demand (read+write) misses -system.l2c.demand_misses::cpu6 5375 # number of demand (read+write) misses -system.l2c.demand_misses::cpu7 5348 # number of demand (read+write) misses -system.l2c.demand_misses::total 42868 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0 5294 # number of overall misses -system.l2c.overall_misses::cpu1 5384 # number of overall misses -system.l2c.overall_misses::cpu2 5375 # number of overall misses -system.l2c.overall_misses::cpu3 5298 # number of overall misses -system.l2c.overall_misses::cpu4 5436 # number of overall misses -system.l2c.overall_misses::cpu5 5358 # number of overall misses -system.l2c.overall_misses::cpu6 5375 # number of overall misses -system.l2c.overall_misses::cpu7 5348 # number of overall misses -system.l2c.overall_misses::total 42868 # number of overall misses -system.l2c.UpgradeReq_miss_latency::cpu0 34306000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1 32515999 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu2 33970000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu3 33665000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu4 30524499 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu5 33417998 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu6 35180998 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu7 31945000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 265525494 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0 148628443 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1 153234943 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu2 151708946 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu3 148204781 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu4 153854439 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu5 151693945 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu6 152734439 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu7 151392920 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 1211452856 # number of ReadExReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0 49327224 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1 49579908 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu2 50488876 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu3 50929398 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu4 51564743 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu5 47695729 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu6 51087902 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu7 48881401 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::total 399555181 # number of ReadSharedReq miss cycles -system.l2c.demand_miss_latency::cpu0 197955667 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1 202814851 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2 202197822 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu3 199134179 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu4 205419182 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu5 199389674 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu6 203822341 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu7 200274321 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 1611008037 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0 197955667 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1 202814851 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2 202197822 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu3 199134179 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu4 205419182 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu5 199389674 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu6 203822341 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu7 200274321 # number of overall miss cycles -system.l2c.overall_miss_latency::total 1611008037 # number of overall miss cycles -system.l2c.WritebackDirty_accesses::writebacks 77671 # number of WritebackDirty accesses(hits+misses) -system.l2c.WritebackDirty_accesses::total 77671 # number of WritebackDirty accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0 2391 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1 2287 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu2 2337 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu3 2381 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu4 2189 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu5 2309 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu6 2378 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu7 2289 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 18561 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0 6472 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1 6452 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu2 6446 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu3 6343 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu4 6512 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu5 6404 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu6 6440 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu7 6460 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 51529 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0 11571 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1 11670 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu2 11546 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu3 11744 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu4 11495 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu5 11670 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu6 11750 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu7 11505 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::total 92951 # number of ReadSharedReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0 18043 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1 18122 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2 17992 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu3 18087 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu4 18007 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu5 18074 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu6 18190 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu7 17965 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 144480 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0 18043 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1 18122 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2 17992 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu3 18087 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu4 18007 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu5 18074 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu6 18190 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu7 17965 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 144480 # number of overall (read+write) accesses -system.l2c.UpgradeReq_miss_rate::cpu0 0.886240 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1 0.875820 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu2 0.881900 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu3 0.882402 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu4 0.883508 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu5 0.877436 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu6 0.899495 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu7 0.885540 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.884112 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0 0.710136 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1 0.724117 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu2 0.719981 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu3 0.719060 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu4 0.721130 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu5 0.730325 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu6 0.720031 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu7 0.719969 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.720585 # miss rate for ReadExReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0 0.060323 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1 0.061011 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu2 0.063572 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu3 0.062755 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu4 0.064376 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu5 0.058355 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu6 0.062809 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu7 0.060582 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::total 0.061721 # miss rate for ReadSharedReq accesses -system.l2c.demand_miss_rate::cpu0 0.293410 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1 0.297097 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2 0.298744 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu3 0.292918 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu4 0.301883 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu5 0.296448 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu6 0.295492 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu7 0.297690 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.296705 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0 0.293410 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1 0.297097 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2 0.298744 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu3 0.292918 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu4 0.301883 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu5 0.296448 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu6 0.295492 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu7 0.297690 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.296705 # miss rate for overall accesses -system.l2c.UpgradeReq_avg_miss_latency::cpu0 16189.712128 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1 16233.649026 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu2 16482.290150 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu3 16023.322228 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu4 15783.091520 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu5 16494.569595 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu6 16447.404395 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu7 15759.743463 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 16180.712614 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0 32338.651654 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1 32798.575128 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu2 32688.848524 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu3 32493.922605 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu4 32762.870315 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu5 32434.027154 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu6 32938.201208 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu7 32550.617072 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 32626.453799 # average ReadExReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0 70669.375358 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1 69634.702247 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu2 68785.934605 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu3 69103.660787 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu4 69682.085135 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu5 70037.781204 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu6 69224.799458 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu7 70131.134864 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::total 69645.316542 # average ReadSharedReq miss latency -system.l2c.demand_avg_miss_latency::cpu0 37392.456932 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1 37669.920319 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2 37618.199442 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu3 37586.670253 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu4 37788.664827 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu5 37213.451661 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu6 37920.435535 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu7 37448.451945 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 37580.667094 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0 37392.456932 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1 37669.920319 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2 37618.199442 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu3 37586.670253 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu4 37788.664827 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu5 37213.451661 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu6 37920.435535 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu7 37448.451945 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 37580.667094 # average overall miss latency -system.l2c.blocked_cycles::no_mshrs 19223 # number of cycles access was blocked +system.cpu7.l1c.writebacks::writebacks 9508 # number of writebacks +system.cpu7.l1c.writebacks::total 9508 # number of writebacks +system.cpu7.l1c.ReadReq_mshr_misses::cpu7 36424 # number of ReadReq MSHR misses +system.cpu7.l1c.ReadReq_mshr_misses::total 36424 # number of ReadReq MSHR misses +system.cpu7.l1c.WriteReq_mshr_misses::cpu7 23598 # number of WriteReq MSHR misses +system.cpu7.l1c.WriteReq_mshr_misses::total 23598 # number of WriteReq MSHR misses +system.cpu7.l1c.demand_mshr_misses::cpu7 60022 # number of demand (read+write) MSHR misses +system.cpu7.l1c.demand_mshr_misses::total 60022 # number of demand (read+write) MSHR misses +system.cpu7.l1c.overall_mshr_misses::cpu7 60022 # number of overall MSHR misses +system.cpu7.l1c.overall_mshr_misses::total 60022 # number of overall MSHR misses +system.cpu7.l1c.ReadReq_mshr_uncacheable::cpu7 9972 # number of ReadReq MSHR uncacheable +system.cpu7.l1c.ReadReq_mshr_uncacheable::total 9972 # number of ReadReq MSHR uncacheable +system.cpu7.l1c.WriteReq_mshr_uncacheable::cpu7 5689 # number of WriteReq MSHR uncacheable +system.cpu7.l1c.WriteReq_mshr_uncacheable::total 5689 # number of WriteReq MSHR uncacheable +system.cpu7.l1c.overall_mshr_uncacheable_misses::cpu7 15661 # number of overall MSHR uncacheable misses +system.cpu7.l1c.overall_mshr_uncacheable_misses::total 15661 # number of overall MSHR uncacheable misses +system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7 684690865 # number of ReadReq MSHR miss cycles +system.cpu7.l1c.ReadReq_mshr_miss_latency::total 684690865 # number of ReadReq MSHR miss cycles +system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7 551733708 # number of WriteReq MSHR miss cycles +system.cpu7.l1c.WriteReq_mshr_miss_latency::total 551733708 # number of WriteReq MSHR miss cycles +system.cpu7.l1c.demand_mshr_miss_latency::cpu7 1236424573 # number of demand (read+write) MSHR miss cycles +system.cpu7.l1c.demand_mshr_miss_latency::total 1236424573 # number of demand (read+write) MSHR miss cycles +system.cpu7.l1c.overall_mshr_miss_latency::cpu7 1236424573 # number of overall MSHR miss cycles +system.cpu7.l1c.overall_mshr_miss_latency::total 1236424573 # number of overall MSHR miss cycles +system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 778989868 # number of ReadReq MSHR uncacheable cycles +system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 778989868 # number of ReadReq MSHR uncacheable cycles +system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 778989868 # number of overall MSHR uncacheable cycles +system.cpu7.l1c.overall_mshr_uncacheable_latency::total 778989868 # number of overall MSHR uncacheable cycles +system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.807341 # mshr miss rate for ReadReq accesses +system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.807341 # mshr miss rate for ReadReq accesses +system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.953609 # mshr miss rate for WriteReq accesses +system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.953609 # mshr miss rate for WriteReq accesses +system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.859151 # mshr miss rate for demand accesses +system.cpu7.l1c.demand_mshr_miss_rate::total 0.859151 # mshr miss rate for demand accesses +system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.859151 # mshr miss rate for overall accesses +system.cpu7.l1c.overall_mshr_miss_rate::total 0.859151 # mshr miss rate for overall accesses +system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 18797.794449 # average ReadReq mshr miss latency +system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 18797.794449 # average ReadReq mshr miss latency +system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 23380.528350 # average WriteReq mshr miss latency +system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 23380.528350 # average WriteReq mshr miss latency +system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 20599.523058 # average overall mshr miss latency +system.cpu7.l1c.demand_avg_mshr_miss_latency::total 20599.523058 # average overall mshr miss latency +system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 20599.523058 # average overall mshr miss latency +system.cpu7.l1c.overall_avg_mshr_miss_latency::total 20599.523058 # average overall mshr miss latency +system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7 78117.716406 # average ReadReq mshr uncacheable latency +system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total 78117.716406 # average ReadReq mshr uncacheable latency +system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::cpu7 49740.748867 # average overall mshr uncacheable latency +system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::total 49740.748867 # average overall mshr uncacheable latency +system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 521659000 # Cumulative time (in ticks) in various power states +system.l2c.tags.replacements 91944 # number of replacements +system.l2c.tags.tagsinuse 1018.135199 # Cycle average of tags in use +system.l2c.tags.total_refs 150035 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 92968 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 1.613835 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 8704000 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 700.601873 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0 40.249147 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1 40.174988 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2 39.327766 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3 40.057426 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu4 39.781379 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu5 39.374996 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu6 39.797467 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu7 38.770159 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.684182 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0 0.039306 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1 0.039233 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2 0.038406 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3 0.039119 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu4 0.038849 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu5 0.038452 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu6 0.038865 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu7 0.037861 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.994273 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1024 1024 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 947 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 77 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 2139200 # Number of tag accesses +system.l2c.tags.data_accesses 2139200 # Number of data accesses +system.l2c.pwrStateResidencyTicks::UNDEFINED 521659000 # Cumulative time (in ticks) in various power states +system.l2c.WritebackDirty_hits::writebacks 77024 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 77024 # number of WritebackDirty hits +system.l2c.UpgradeReq_hits::cpu0 414 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1 433 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu2 398 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu3 417 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu4 426 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu5 450 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu6 421 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu7 435 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 3394 # number of UpgradeReq hits +system.l2c.ReadExReq_hits::cpu0 1862 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1 1934 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu2 1949 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu3 1865 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu4 1828 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu5 1873 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu6 1869 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu7 1854 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 15034 # number of ReadExReq hits +system.l2c.ReadSharedReq_hits::cpu0 9356 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1 9333 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu2 9371 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu3 9291 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu4 9201 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu5 9292 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu6 9177 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu7 9226 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 74247 # number of ReadSharedReq hits +system.l2c.demand_hits::cpu0 11218 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1 11267 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2 11320 # number of demand (read+write) hits +system.l2c.demand_hits::cpu3 11156 # number of demand (read+write) hits +system.l2c.demand_hits::cpu4 11029 # number of demand (read+write) hits +system.l2c.demand_hits::cpu5 11165 # number of demand (read+write) hits +system.l2c.demand_hits::cpu6 11046 # number of demand (read+write) hits +system.l2c.demand_hits::cpu7 11080 # number of demand (read+write) hits +system.l2c.demand_hits::total 89281 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0 11218 # number of overall hits +system.l2c.overall_hits::cpu1 11267 # number of overall hits +system.l2c.overall_hits::cpu2 11320 # number of overall hits +system.l2c.overall_hits::cpu3 11156 # number of overall hits +system.l2c.overall_hits::cpu4 11029 # number of overall hits +system.l2c.overall_hits::cpu5 11165 # number of overall hits +system.l2c.overall_hits::cpu6 11046 # number of overall hits +system.l2c.overall_hits::cpu7 11080 # number of overall hits +system.l2c.overall_hits::total 89281 # number of overall hits +system.l2c.UpgradeReq_misses::cpu0 1872 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1 1844 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu2 1947 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu3 1836 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu4 1852 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu5 1900 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu6 1862 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu7 1851 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 14964 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::cpu0 4900 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1 4669 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu2 4784 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu3 4718 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu4 4791 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu5 4701 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu6 4630 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu7 4626 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 37819 # number of ReadExReq misses +system.l2c.ReadSharedReq_misses::cpu0 2463 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1 2553 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu2 2469 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu3 2512 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu4 2543 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu5 2510 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu6 2544 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu7 2476 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::total 20070 # number of ReadSharedReq misses +system.l2c.demand_misses::cpu0 7363 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1 7222 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2 7253 # number of demand (read+write) misses +system.l2c.demand_misses::cpu3 7230 # number of demand (read+write) misses +system.l2c.demand_misses::cpu4 7334 # number of demand (read+write) misses +system.l2c.demand_misses::cpu5 7211 # number of demand (read+write) misses +system.l2c.demand_misses::cpu6 7174 # number of demand (read+write) misses +system.l2c.demand_misses::cpu7 7102 # number of demand (read+write) misses +system.l2c.demand_misses::total 57889 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0 7363 # number of overall misses +system.l2c.overall_misses::cpu1 7222 # number of overall misses +system.l2c.overall_misses::cpu2 7253 # number of overall misses +system.l2c.overall_misses::cpu3 7230 # number of overall misses +system.l2c.overall_misses::cpu4 7334 # number of overall misses +system.l2c.overall_misses::cpu5 7211 # number of overall misses +system.l2c.overall_misses::cpu6 7174 # number of overall misses +system.l2c.overall_misses::cpu7 7102 # number of overall misses +system.l2c.overall_misses::total 57889 # number of overall misses +system.l2c.UpgradeReq_miss_latency::cpu0 31234104 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1 31358138 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu2 32572788 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu3 30120451 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu4 30799263 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu5 31792446 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu6 30352791 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu7 30383968 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 248613949 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0 215803873 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1 203805632 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu2 208081416 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu3 204329473 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu4 209030536 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu5 205216215 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu6 201405883 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu7 201887028 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 1649560056 # number of ReadExReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0 169116609 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1 174843463 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu2 170153096 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu3 173149203 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu4 175448063 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu5 172961782 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu6 175284714 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu7 170387602 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::total 1381344532 # number of ReadSharedReq miss cycles +system.l2c.demand_miss_latency::cpu0 384920482 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1 378649095 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2 378234512 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu3 377478676 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu4 384478599 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu5 378177997 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu6 376690597 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu7 372274630 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 3030904588 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0 384920482 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1 378649095 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2 378234512 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu3 377478676 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu4 384478599 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu5 378177997 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu6 376690597 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu7 372274630 # number of overall miss cycles +system.l2c.overall_miss_latency::total 3030904588 # number of overall miss cycles +system.l2c.WritebackDirty_accesses::writebacks 77024 # number of WritebackDirty accesses(hits+misses) +system.l2c.WritebackDirty_accesses::total 77024 # number of WritebackDirty accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0 2286 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1 2277 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu2 2345 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu3 2253 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu4 2278 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu5 2350 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu6 2283 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu7 2286 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 18358 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0 6762 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1 6603 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu2 6733 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu3 6583 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu4 6619 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu5 6574 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu6 6499 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu7 6480 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 52853 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0 11819 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1 11886 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu2 11840 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu3 11803 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu4 11744 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu5 11802 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu6 11721 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu7 11702 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::total 94317 # number of ReadSharedReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0 18581 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1 18489 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2 18573 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu3 18386 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu4 18363 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu5 18376 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu6 18220 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu7 18182 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 147170 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0 18581 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1 18489 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2 18573 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu3 18386 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu4 18363 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu5 18376 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu6 18220 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu7 18182 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 147170 # number of overall (read+write) accesses +system.l2c.UpgradeReq_miss_rate::cpu0 0.818898 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1 0.809838 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu2 0.830277 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu3 0.814913 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu4 0.812994 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu5 0.808511 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu6 0.815594 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu7 0.809711 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.815121 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0 0.724638 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1 0.707103 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu2 0.710530 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu3 0.716695 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu4 0.723825 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu5 0.715090 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu6 0.712417 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu7 0.713889 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.715551 # miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0 0.208393 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1 0.214791 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu2 0.208530 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu3 0.212827 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu4 0.216536 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu5 0.212676 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu6 0.217046 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu7 0.211588 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::total 0.212793 # miss rate for ReadSharedReq accesses +system.l2c.demand_miss_rate::cpu0 0.396265 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1 0.390611 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2 0.390513 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu3 0.393234 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu4 0.399390 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu5 0.392414 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu6 0.393743 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu7 0.390606 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.393348 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0 0.396265 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1 0.390611 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2 0.390513 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu3 0.393234 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu4 0.399390 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu5 0.392414 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu6 0.393743 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu7 0.390606 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.393348 # miss rate for overall accesses +system.l2c.UpgradeReq_avg_miss_latency::cpu0 16684.884615 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1 17005.497831 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu2 16729.731895 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu3 16405.474401 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu4 16630.271598 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu5 16732.866316 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu6 16301.176692 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu7 16414.893571 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 16614.137196 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0 44041.606735 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1 43650.810024 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu2 43495.279264 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu3 43308.493641 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu4 43629.834273 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu5 43653.736439 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu6 43500.190713 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu7 43641.813230 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 43617.230916 # average ReadExReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0 68662.853837 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1 68485.492754 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu2 68915.794249 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu3 68928.822850 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu4 68992.553284 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu5 68909.076494 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu6 68901.224057 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu7 68815.671244 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::total 68826.334429 # average ReadSharedReq miss latency +system.l2c.demand_avg_miss_latency::cpu0 52277.669700 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1 52429.949460 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2 52148.698745 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu3 52210.052006 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu4 52424.134033 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu5 52444.598114 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu6 52507.749791 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu7 52418.280766 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 52357.176458 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0 52277.669700 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1 52429.949460 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2 52148.698745 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu3 52210.052006 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu4 52424.134033 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu5 52444.598114 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu6 52507.749791 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu7 52418.280766 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 52357.176458 # average overall miss latency +system.l2c.blocked_cycles::no_mshrs 46726 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.blocked::no_mshrs 2973 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 7668 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs 6.465859 # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_mshrs 6.093636 # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.l2c.writebacks::writebacks 6255 # number of writebacks -system.l2c.writebacks::total 6255 # number of writebacks -system.l2c.UpgradeReq_mshr_hits::cpu2 1 # number of UpgradeReq MSHR hits +system.l2c.writebacks::writebacks 22726 # number of writebacks +system.l2c.writebacks::total 22726 # number of writebacks +system.l2c.UpgradeReq_mshr_hits::cpu0 3 # number of UpgradeReq MSHR hits +system.l2c.UpgradeReq_mshr_hits::cpu1 4 # number of UpgradeReq MSHR hits +system.l2c.UpgradeReq_mshr_hits::cpu2 2 # number of UpgradeReq MSHR hits +system.l2c.UpgradeReq_mshr_hits::cpu3 3 # number of UpgradeReq MSHR hits +system.l2c.UpgradeReq_mshr_hits::cpu4 5 # number of UpgradeReq MSHR hits +system.l2c.UpgradeReq_mshr_hits::cpu5 2 # number of UpgradeReq MSHR hits system.l2c.UpgradeReq_mshr_hits::cpu6 1 # number of UpgradeReq MSHR hits -system.l2c.UpgradeReq_mshr_hits::total 2 # number of UpgradeReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu0 2 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu1 4 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu2 9 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu3 3 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu4 7 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu5 5 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu6 5 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu7 5 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::total 40 # number of ReadExReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu0 11 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu1 10 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu2 14 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu3 13 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu4 8 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu5 9 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu6 8 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu7 10 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::total 83 # number of ReadSharedReq MSHR hits -system.l2c.demand_mshr_hits::cpu0 13 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1 14 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu2 23 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu3 16 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu4 15 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu5 14 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu6 13 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu7 15 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 123 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu0 13 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1 14 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu2 23 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu3 16 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu4 15 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu5 14 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu6 13 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu7 15 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 123 # number of overall MSHR hits -system.l2c.CleanEvict_mshr_misses::writebacks 1242 # number of CleanEvict MSHR misses -system.l2c.CleanEvict_mshr_misses::total 1242 # number of CleanEvict MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0 2119 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1 2003 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu2 2060 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu3 2101 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu4 1934 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu5 2026 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu6 2138 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu7 2027 # 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number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 57456 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0 7310 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1 7175 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2 7205 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu3 7182 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu4 7282 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu5 7149 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu6 7113 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu7 7040 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 57456 # number of overall MSHR misses +system.l2c.ReadReq_mshr_uncacheable::cpu0 9863 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu1 9872 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu2 9852 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu3 9823 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu4 9741 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu5 9844 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu6 9904 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu7 9971 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::total 78870 # number of ReadReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu0 5413 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu1 5469 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu2 5498 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu3 5381 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu4 5438 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu5 5504 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu6 5505 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu7 5689 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::total 43897 # number of WriteReq MSHR uncacheable +system.l2c.overall_mshr_uncacheable_misses::cpu0 15276 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu1 15341 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu2 15350 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu3 15204 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu4 15179 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu5 15348 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu6 15409 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu7 15660 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::total 122767 # number of overall MSHR uncacheable misses +system.l2c.UpgradeReq_mshr_miss_latency::cpu0 42798637 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1 41900379 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu2 44540803 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu3 41317767 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu4 42296498 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu5 43188221 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu6 42540949 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu7 41448863 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 340032117 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0 166179988 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1 156537743 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu2 159697945 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu3 156613177 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu4 160372266 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu5 157473921 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu6 154279145 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu7 154804178 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 1265958363 # number of ReadExReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0 143336439 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1 148034574 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu2 144250348 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu3 146721083 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu4 148442317 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu5 146274036 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu6 148395292 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu7 144143903 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::total 1169597992 # number of ReadSharedReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0 309516427 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1 304572317 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2 303948293 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu3 303334260 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu4 308814583 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu5 303747957 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu6 302674437 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu7 298948081 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 2435556355 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0 309516427 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1 304572317 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2 303948293 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu3 303334260 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu4 308814583 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu5 303747957 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu6 302674437 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu7 298948081 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 2435556355 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0 558924481 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1 559228006 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu2 558782791 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu3 556927201 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu4 552042138 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu5 557542912 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu6 561245949 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu7 564245669 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 4468939147 # number of ReadReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0 558924481 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1 559228006 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu2 558782791 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu3 556927201 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu4 552042138 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu5 557542912 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu6 561245949 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu7 564245669 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 4468939147 # number of overall MSHR uncacheable cycles system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0 0.886240 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.875820 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.881472 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu3 0.882402 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.883508 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.877436 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.899075 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.885540 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.884004 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0 0.709827 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.723497 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu2 0.718585 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu3 0.718587 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.720055 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.729544 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.719255 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.719195 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.719808 # mshr miss rate for ReadExReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0 0.059373 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1 0.060154 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu2 0.062359 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu3 0.061649 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu4 0.063680 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu5 0.057584 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu6 0.062128 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu7 0.059713 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::total 0.060828 # mshr miss rate for ReadSharedReq accesses -system.l2c.demand_mshr_miss_rate::cpu0 0.292690 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1 0.296325 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2 0.297466 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu3 0.292033 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu4 0.301050 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu5 0.295673 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu6 0.294777 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu7 0.296855 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.295854 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0 0.292690 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1 0.296325 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2 0.297466 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu3 0.292033 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu4 0.301050 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu5 0.295673 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu6 0.294777 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu7 0.296855 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.295854 # mshr miss rate for overall accesses -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 19274.155262 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 19253.227659 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 19246.403883 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 19237.206092 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 19206.719235 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 19200.354393 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 19283.960243 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 19244.956586 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 19243.994332 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 22334.515237 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 22783.451371 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 22680.037781 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 22477.211496 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 22744.141395 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 22433.699058 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 22933.635363 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 22549.261946 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 22617.696207 # average ReadExReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0 61112.551674 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1 59870.158120 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2 59292.448611 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3 59588.425414 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu4 59871.435792 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu5 60236.848214 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu6 59459.368493 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu7 60442.264920 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 59971.698797 # average ReadSharedReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0 27379.111153 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1 27631.657728 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2 27605.474215 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3 27564.019311 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu4 27757.456189 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu5 27187.388473 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu6 27906.366654 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu7 27430.659479 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 27558.613990 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0 27379.111153 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1 27631.657728 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2 27605.474215 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3 27564.019311 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu4 27757.456189 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu5 27187.388473 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu6 27906.366654 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu7 27430.659479 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 27558.613990 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 51975.587807 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1 51914.458465 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2 51919.662694 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3 51952.415169 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu4 51935.072593 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu5 51933.073461 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu6 51940.917554 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu7 51928.287298 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 51937.372529 # average ReadReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0 33443.280412 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1 33337.658856 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu2 33637.284713 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu3 33165.629829 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu4 33315.757096 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu5 33504.118091 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu6 33149.271115 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 33500.900238 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 33381.197903 # average overall mshr uncacheable latency -system.membus.pwrStateResidencyTicks::UNDEFINED 500337000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 78773 # Transaction distribution -system.membus.trans_dist::ReadResp 84410 # Transaction distribution -system.membus.trans_dist::WriteReq 43787 # Transaction distribution -system.membus.trans_dist::WriteResp 43783 # Transaction distribution -system.membus.trans_dist::WritebackDirty 6255 # Transaction distribution -system.membus.trans_dist::CleanEvict 1278 # Transaction distribution -system.membus.trans_dist::UpgradeReq 61348 # Transaction distribution -system.membus.trans_dist::ReadExReq 49073 # Transaction distribution -system.membus.trans_dist::ReadExResp 3087 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 5646 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 377440 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 377440 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 1081783 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 1081783 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 56900 # Total snoops (count) +system.l2c.UpgradeReq_mshr_miss_rate::cpu0 0.817585 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.808081 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.829424 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu3 0.813582 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.810799 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.807660 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.815155 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.807524 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.813760 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0 0.721680 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.704528 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2 0.707857 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu3 0.713504 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.721106 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.711287 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.708417 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.710648 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.712410 # mshr miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0 0.205601 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1 0.212267 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu2 0.205997 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu3 0.210540 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu4 0.213641 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu5 0.209541 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu6 0.214060 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu7 0.208084 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.209962 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu0 0.393413 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1 0.388069 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2 0.387929 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3 0.390623 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu4 0.396558 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu5 0.389040 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu6 0.390395 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu7 0.387196 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.390406 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0 0.393413 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1 0.388069 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2 0.387929 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3 0.390623 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu4 0.396558 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu5 0.389040 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu6 0.390395 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu7 0.387196 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.390406 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 22899.217228 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 22771.945109 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 22900.155784 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 22541.062193 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 22900.107201 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 22754.594837 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 22859.188071 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 22453.338570 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 22761.370708 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 34053.276230 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 33649.557825 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 33507.751783 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 33343.235469 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 33599.888121 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 33677.057528 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 33509.805604 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 33616.542454 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 33621.713091 # average ReadExReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0 58986.188889 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1 58674.028537 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2 59143.234112 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3 59042.689336 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu4 59163.936628 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu5 59148.417307 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu6 59145.194101 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu7 59196.674743 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 59061.656921 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0 42341.508482 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1 42449.103415 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2 42185.745038 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3 42235.346700 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu4 42407.935045 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu5 42488.174150 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu6 42552.289751 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu7 42464.216051 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 42389.939345 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0 42341.508482 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1 42449.103415 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2 42185.745038 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3 42235.346700 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu4 42407.935045 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu5 42488.174150 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu6 42552.289751 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu7 42464.216051 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 42389.939345 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 56668.810808 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1 56647.893639 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2 56717.701076 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3 56696.243612 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu4 56672.019095 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu5 56637.841528 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu6 56668.613590 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu7 56588.674055 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 56662.091378 # average ReadReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0 36588.405407 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1 36453.165113 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu2 36402.787687 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu3 36630.307880 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu4 36368.808090 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu5 36326.746938 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu6 36423.255825 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 36031.013346 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 36401.794839 # average overall mshr uncacheable latency +system.membus.snoop_filter.tot_requests 165129 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 149421 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 521659000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadReq 78866 # Transaction distribution +system.membus.trans_dist::ReadResp 98603 # Transaction distribution +system.membus.trans_dist::WriteReq 43891 # Transaction distribution +system.membus.trans_dist::WriteResp 43890 # Transaction distribution +system.membus.trans_dist::WritebackDirty 22725 # Transaction distribution +system.membus.trans_dist::CleanEvict 5096 # Transaction distribution +system.membus.trans_dist::UpgradeReq 51962 # Transaction distribution +system.membus.trans_dist::ReadExReq 56321 # Transaction distribution +system.membus.trans_dist::ReadExResp 11265 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 19745 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 432364 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 432364 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 3561537 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 3561537 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 55548 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 253448 # Request fanout histogram +system.membus.snoop_fanout::samples 277065 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 253448 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 277065 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 253448 # Request fanout histogram -system.membus.reqLayer0.occupancy 289313112 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 57.8 # Layer utilization (%) -system.membus.respLayer0.occupancy 244976000 # Layer occupancy (ticks) -system.membus.respLayer0.utilization 49.0 # Layer utilization (%) -system.toL2Bus.snoop_filter.tot_requests 662658 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 284136 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 332740 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 12293 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 5765 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 6528 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 500337000 # Cumulative time (in ticks) in various power states -system.toL2Bus.trans_dist::ReadReq 78775 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 371396 # Transaction distribution -system.toL2Bus.trans_dist::ReadRespWithInvalidate 3 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 43790 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 43780 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 83926 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 105295 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 29475 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 29475 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 162920 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 162916 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 292639 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side 133502 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side 133647 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side 133520 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side 133779 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side 133547 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side 133528 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side 133790 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side 133396 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 1068709 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side 1800550 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side 1795691 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side 1783667 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side 1792707 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side 1790564 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side 1791999 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side 1796631 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side 1788086 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 14339895 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 335681 # Total snoops (count) -system.toL2Bus.snoopTraffic 20309376 # Total snoop traffic (bytes) -system.toL2Bus.snoop_fanout::samples 623777 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.148975 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.984758 # Request fanout histogram +system.membus.snoop_fanout::total 277065 # Request fanout histogram +system.membus.reqLayer0.occupancy 406206026 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 77.9 # Layer utilization (%) +system.membus.respLayer0.occupancy 356644000 # Layer occupancy (ticks) +system.membus.respLayer0.utilization 68.4 # Layer utilization (%) +system.toL2Bus.snoop_filter.tot_requests 666785 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 283960 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 335937 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 86136 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 43107 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 43029 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 521659000 # Cumulative time (in ticks) in various power states +system.toL2Bus.trans_dist::ReadReq 78870 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 370375 # Transaction distribution +system.toL2Bus.trans_dist::ReadRespWithInvalidate 2 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 43897 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 43890 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 99750 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 167866 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 28850 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 28850 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 162383 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 162380 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 291522 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side 133688 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side 134001 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side 133796 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side 133576 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side 133426 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side 133904 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side 133634 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side 133439 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 1069464 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side 1829226 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side 1815722 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side 1817716 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side 1809443 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side 1812235 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side 1808884 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side 1798064 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side 1779371 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 14470661 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 409171 # Total snoops (count) +system.toL2Bus.snoopTraffic 21085504 # Total snoop traffic (bytes) +system.toL2Bus.snoop_fanout::samples 706797 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.196447 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.990756 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 172972 27.73% 27.73% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 258444 41.43% 69.16% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 133198 21.35% 90.52% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 46670 7.48% 98.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::4 10752 1.72% 99.72% # Request fanout histogram -system.toL2Bus.snoop_fanout::5 1603 0.26% 99.98% # Request fanout histogram -system.toL2Bus.snoop_fanout::6 135 0.02% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::7 3 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 181481 25.68% 25.68% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 294628 41.68% 67.36% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 158602 22.44% 89.80% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 56776 8.03% 97.83% # Request fanout histogram +system.toL2Bus.snoop_fanout::4 13243 1.87% 99.71% # Request fanout histogram +system.toL2Bus.snoop_fanout::5 1898 0.27% 99.98% # Request fanout histogram +system.toL2Bus.snoop_fanout::6 160 0.02% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::7 9 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 7 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 623777 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 493769156 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 98.7 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 102470874 # Layer occupancy (ticks) -system.toL2Bus.respLayer0.utilization 20.5 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 102502346 # Layer occupancy (ticks) -system.toL2Bus.respLayer1.utilization 20.5 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 102645272 # Layer occupancy (ticks) -system.toL2Bus.respLayer2.utilization 20.5 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 102492443 # Layer occupancy (ticks) -system.toL2Bus.respLayer3.utilization 20.5 # Layer utilization (%) -system.toL2Bus.respLayer4.occupancy 102725884 # Layer occupancy (ticks) -system.toL2Bus.respLayer4.utilization 20.5 # Layer utilization (%) -system.toL2Bus.respLayer5.occupancy 102549521 # Layer occupancy (ticks) -system.toL2Bus.respLayer5.utilization 20.5 # Layer utilization (%) -system.toL2Bus.respLayer6.occupancy 102424000 # Layer occupancy (ticks) -system.toL2Bus.respLayer6.utilization 20.5 # Layer utilization (%) -system.toL2Bus.respLayer7.occupancy 102560017 # Layer occupancy (ticks) -system.toL2Bus.respLayer7.utilization 20.5 # Layer utilization (%) +system.toL2Bus.snoop_fanout::total 706797 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 500161714 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 95.9 # Layer utilization (%) +system.toL2Bus.respLayer0.occupancy 102256739 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 19.6 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 102545160 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.utilization 19.7 # Layer utilization (%) +system.toL2Bus.respLayer2.occupancy 102125332 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.utilization 19.6 # Layer utilization (%) +system.toL2Bus.respLayer3.occupancy 102285646 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.utilization 19.6 # Layer utilization (%) +system.toL2Bus.respLayer4.occupancy 102013056 # Layer occupancy (ticks) +system.toL2Bus.respLayer4.utilization 19.6 # Layer utilization (%) +system.toL2Bus.respLayer5.occupancy 102427641 # Layer occupancy (ticks) +system.toL2Bus.respLayer5.utilization 19.6 # Layer utilization (%) +system.toL2Bus.respLayer6.occupancy 102433420 # Layer occupancy (ticks) +system.toL2Bus.respLayer6.utilization 19.6 # Layer utilization (%) +system.toL2Bus.respLayer7.occupancy 101994041 # Layer occupancy (ticks) +system.toL2Bus.respLayer7.utilization 19.6 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt b/tests/quick/se/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt index a2e00980d..9ca521f76 100644 --- a/tests/quick/se/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/quick/se/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.044221 # Nu sim_ticks 44221003000 # Number of ticks simulated final_tick 44221003000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1536521 # Simulator instruction rate (inst/s) -host_op_rate 1536520 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 769141125 # Simulator tick rate (ticks/s) -host_mem_usage 247596 # Number of bytes of host memory used -host_seconds 57.49 # Real time elapsed on the host +host_inst_rate 1734998 # Simulator instruction rate (inst/s) +host_op_rate 1734998 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 868493662 # Simulator tick rate (ticks/s) +host_mem_usage 251200 # Number of bytes of host memory used +host_seconds 50.92 # Real time elapsed on the host sim_insts 88340673 # Number of instructions simulated sim_ops 88340673 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -130,6 +130,12 @@ system.cpu.op_class::MemWrite 14620629 16.53% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 88438073 # Class of executed instruction +system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.pwrStateResidencyTicks::UNDEFINED 44221003000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 108714711 # Transaction distribution system.membus.trans_dist::ReadResp 108714711 # Transaction distribution @@ -144,14 +150,14 @@ system.membus.pkt_size::total 572107835 # Cu system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) system.membus.snoop_fanout::samples 123328088 # Request fanout histogram -system.membus.snoop_fanout::mean 0.717096 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.450410 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 34890015 28.29% 28.29% # Request fanout histogram -system.membus.snoop_fanout::1 88438073 71.71% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 123328088 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 123328088 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt b/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt index 51d70d56c..39b06f58a 100644 --- a/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt @@ -1,43 +1,43 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.134742 # Number of seconds simulated -sim_ticks 134741611500 # Number of ticks simulated -final_tick 134741611500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.134921 # Number of seconds simulated +sim_ticks 134921160500 # Number of ticks simulated +final_tick 134921160500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 968280 # Simulator instruction rate (inst/s) -host_op_rate 968280 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1476869211 # Simulator tick rate (ticks/s) -host_mem_usage 256564 # Number of bytes of host memory used -host_seconds 91.23 # Real time elapsed on the host +host_inst_rate 1080841 # Simulator instruction rate (inst/s) +host_op_rate 1080841 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1650749081 # Simulator tick rate (ticks/s) +host_mem_usage 262472 # Number of bytes of host memory used +host_seconds 81.73 # Real time elapsed on the host sim_insts 88340673 # Number of instructions simulated sim_ops 88340673 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 134741611500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 367360 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10138112 # Number of bytes read from this memory -system.physmem.bytes_read::total 10505472 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 367360 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 367360 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7320448 # Number of bytes written to this memory -system.physmem.bytes_written::total 7320448 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 5740 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 158408 # Number of read requests responded to by this memory -system.physmem.num_reads::total 164148 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 114382 # Number of write requests responded to by this memory -system.physmem.num_writes::total 114382 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 2726403 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 75241137 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 77967540 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2726403 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2726403 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 54329527 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 54329527 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 54329527 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2726403 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 75241137 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 132297067 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 134741611500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 134921160500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 369920 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10155520 # Number of bytes read from this memory +system.physmem.bytes_read::total 10525440 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 369920 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 369920 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7371264 # Number of bytes written to this memory +system.physmem.bytes_written::total 7371264 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 5780 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 158680 # Number of read requests responded to by this memory +system.physmem.num_reads::total 164460 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 115176 # Number of write requests responded to by this memory +system.physmem.num_writes::total 115176 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 2741749 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 75270031 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 78011781 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2741749 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2741749 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 54633862 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 54633862 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 54633862 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2741749 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 75270031 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 132645642 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 134921160500 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses @@ -72,8 +72,8 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 134741611500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 269483223 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 134921160500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 269842321 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 88340673 # Number of instructions committed @@ -92,7 +92,7 @@ system.cpu.num_mem_refs 34987415 # nu system.cpu.num_load_insts 20366786 # Number of load instructions system.cpu.num_store_insts 14620629 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 269483223 # Number of busy cycles +system.cpu.num_busy_cycles 269842321 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 13754477 # Number of branches fetched @@ -131,24 +131,24 @@ system.cpu.op_class::MemWrite 14620629 16.53% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 88438073 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 134741611500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 134921160500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 200248 # number of replacements -system.cpu.dcache.tags.tagsinuse 4078.397630 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 4078.334496 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 34685671 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 204344 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 169.741568 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 983457500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4078.397630 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.995703 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.995703 # Average percentage of cache occupancy +system.cpu.dcache.tags.warmup_cycle 990170500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4078.334496 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.995687 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.995687 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 454 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 3595 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 445 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 3604 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 69984374 # Number of tag accesses system.cpu.dcache.tags.data_accesses 69984374 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 134741611500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 134921160500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 20215872 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 20215872 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 14469799 # number of WriteReq hits @@ -165,14 +165,14 @@ system.cpu.dcache.demand_misses::cpu.data 204344 # n system.cpu.dcache.demand_misses::total 204344 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 204344 # number of overall misses system.cpu.dcache.overall_misses::total 204344 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 2138978000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 2138978000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 8279807000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 8279807000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 10418785000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 10418785000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 10418785000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 10418785000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 2178421500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 2178421500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 8412226500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 8412226500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 10590648000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 10590648000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 10590648000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 10590648000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 20276638 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 20276638 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) @@ -189,22 +189,22 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.005857 system.cpu.dcache.demand_miss_rate::total 0.005857 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.005857 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.005857 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 35200.243557 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 35200.243557 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 57667.657998 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 57667.657998 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 50986.498258 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 50986.498258 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 50986.498258 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 50986.498258 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 35849.348320 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 35849.348320 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 58589.940659 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 58589.940659 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 51827.545707 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 51827.545707 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 51827.545707 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 51827.545707 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 168278 # number of writebacks -system.cpu.dcache.writebacks::total 168278 # number of writebacks +system.cpu.dcache.writebacks::writebacks 167988 # number of writebacks +system.cpu.dcache.writebacks::total 167988 # number of writebacks system.cpu.dcache.ReadReq_mshr_misses::cpu.data 60766 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 60766 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143578 # number of WriteReq MSHR misses @@ -213,14 +213,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 204344 system.cpu.dcache.demand_mshr_misses::total 204344 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 204344 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 204344 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2078212000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2078212000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8136229000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8136229000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10214441000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10214441000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10214441000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10214441000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2117655500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2117655500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8268648500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8268648500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10386304000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10386304000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10386304000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10386304000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002997 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002997 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009825 # mshr miss rate for WriteReq accesses @@ -229,33 +229,33 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005857 system.cpu.dcache.demand_mshr_miss_rate::total 0.005857 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005857 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.005857 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34200.243557 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34200.243557 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 56667.657998 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 56667.657998 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 49986.498258 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 49986.498258 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 49986.498258 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 49986.498258 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 134741611500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34849.348320 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34849.348320 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 57589.940659 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 57589.940659 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 50827.545707 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 50827.545707 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 50827.545707 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 50827.545707 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 134921160500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 74391 # number of replacements -system.cpu.icache.tags.tagsinuse 1870.507754 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1870.340281 # Cycle average of tags in use system.cpu.icache.tags.total_refs 88361638 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 76436 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 1156.021220 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1870.507754 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.913334 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.913334 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1870.340281 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.913252 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.913252 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 2045 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 109 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 36 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 110 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 191 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1708 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.998535 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 176952584 # Number of tag accesses system.cpu.icache.tags.data_accesses 176952584 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 134741611500 # Cumulative time (in ticks) in various power states +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 134921160500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 88361638 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 88361638 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 88361638 # number of demand (read+write) hits @@ -268,12 +268,12 @@ system.cpu.icache.demand_misses::cpu.inst 76436 # n system.cpu.icache.demand_misses::total 76436 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 76436 # number of overall misses system.cpu.icache.overall_misses::total 76436 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 1275518500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 1275518500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 1275518500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 1275518500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 1275518500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 1275518500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 1283204500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 1283204500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 1283204500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 1283204500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 1283204500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 1283204500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 88438074 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 88438074 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 88438074 # number of demand (read+write) accesses @@ -286,12 +286,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000864 system.cpu.icache.demand_miss_rate::total 0.000864 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000864 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000864 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16687.405149 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 16687.405149 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 16687.405149 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 16687.405149 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 16687.405149 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 16687.405149 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16787.959862 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 16787.959862 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 16787.959862 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 16787.959862 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 16787.959862 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 16787.959862 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -306,90 +306,90 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 76436 system.cpu.icache.demand_mshr_misses::total 76436 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 76436 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 76436 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1199082500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 1199082500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1199082500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 1199082500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1199082500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 1199082500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1206768500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 1206768500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1206768500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 1206768500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1206768500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 1206768500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000864 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000864 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000864 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000864 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000864 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000864 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15687.405149 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15687.405149 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15687.405149 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 15687.405149 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15687.405149 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 15687.405149 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 134741611500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 131998 # number of replacements -system.cpu.l2cache.tags.tagsinuse 30708.485304 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 247404 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 164074 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 1.507881 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 27397.900187 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1667.759999 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 1642.825119 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.836118 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.050896 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.050135 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.937149 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 32076 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 143 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 731 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 9441 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 21639 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 122 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.978882 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 4751004 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 4751004 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 134741611500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 168278 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 168278 # number of WritebackDirty hits +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15787.959862 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15787.959862 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15787.959862 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 15787.959862 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15787.959862 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 15787.959862 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 134921160500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.replacements 133742 # number of replacements +system.cpu.l2cache.tags.tagsinuse 31970.307618 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 388803 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 166510 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 2.335013 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 30559527000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 658.522624 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1588.260241 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 29723.524754 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.020097 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.048470 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.907090 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.975656 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 119 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 655 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 7663 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 24220 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 111 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 4609862 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 4609862 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 134921160500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.WritebackDirty_hits::writebacks 167988 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 167988 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 74391 # number of WritebackClean hits system.cpu.l2cache.WritebackClean_hits::total 74391 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 12696 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 12696 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 70696 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 70696 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 33240 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 33240 # 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mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.456950 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.075619 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.776534 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.585725 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.075619 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.776534 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.585725 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500.389572 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500.389572 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50548.788927 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50548.788927 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50502.178845 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50502.178845 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50548.788927 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500.702672 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50502.392679 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50548.788927 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500.702672 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50502.392679 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 555419 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 274639 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 3875 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3875 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 4055 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 4055 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 134741611500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 134921160500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 137202 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 282660 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 283165 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 74391 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 49586 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 50825 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 143578 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 143578 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 76436 # Transaction distribution @@ -507,53 +507,59 @@ system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_ system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 608936 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 836199 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9652928 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23847808 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 33500736 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 131998 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 7320448 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 412778 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.009388 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.096434 # Request fanout histogram +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23829248 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 33482176 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 133742 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 7371328 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 414522 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.009782 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.098421 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 408903 99.06% 99.06% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 3875 0.94% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 410467 99.02% 99.02% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 4055 0.98% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 412778 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 520378500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 414522 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 520088500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.4 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 114654000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 306516000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 134741611500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 33266 # Transaction distribution -system.membus.trans_dist::WritebackDirty 114382 # Transaction distribution -system.membus.trans_dist::CleanEvict 13845 # Transaction distribution -system.membus.trans_dist::ReadExReq 130882 # Transaction distribution -system.membus.trans_dist::ReadExResp 130882 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 33266 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 456523 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 456523 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17825920 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 17825920 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoop_filter.tot_requests 294252 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 129792 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 134921160500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 33547 # Transaction distribution +system.membus.trans_dist::WritebackDirty 115176 # Transaction distribution +system.membus.trans_dist::CleanEvict 14616 # Transaction distribution +system.membus.trans_dist::ReadExReq 130913 # Transaction distribution +system.membus.trans_dist::ReadExResp 130913 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 33547 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 458712 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 458712 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17896704 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 17896704 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 292375 # Request fanout histogram +system.membus.snoop_fanout::samples 164460 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 292375 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 164460 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 292375 # Request fanout histogram -system.membus.reqLayer0.occupancy 750324500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 164460 # Request fanout histogram +system.membus.reqLayer0.occupancy 755151000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.6 # Layer utilization (%) -system.membus.respLayer1.occupancy 820740000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 822300000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.6 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt b/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt index 4508adaf3..0dedef5a8 100644 --- a/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.048960 # Nu sim_ticks 48960022500 # Number of ticks simulated final_tick 48960022500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 832939 # Simulator instruction rate (inst/s) -host_op_rate 1065213 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 575079073 # Simulator tick rate (ticks/s) -host_mem_usage 264380 # Number of bytes of host memory used -host_seconds 85.14 # Real time elapsed on the host +host_inst_rate 970522 # Simulator instruction rate (inst/s) +host_op_rate 1241163 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 670069309 # Simulator tick rate (ticks/s) +host_mem_usage 268760 # Number of bytes of host memory used +host_seconds 73.07 # Real time elapsed on the host sim_insts 70913204 # Number of instructions simulated sim_ops 90688159 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -220,6 +220,12 @@ system.cpu.op_class::MemWrite 20555739 22.67% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 90690106 # Class of executed instruction +system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.pwrStateResidencyTicks::UNDEFINED 48960022500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 100925158 # Transaction distribution system.membus.trans_dist::ReadResp 100941077 # Transaction distribution @@ -239,14 +245,14 @@ system.membus.pkt_size::total 497813920 # Cu system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) system.membus.snoop_fanout::samples 120930641 # Request fanout histogram -system.membus.snoop_fanout::mean 0.646198 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.478149 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 42785550 35.38% 35.38% # Request fanout histogram -system.membus.snoop_fanout::1 78145091 64.62% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 120930641 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 120930641 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt index 60128a0c8..992da2d61 100644 --- a/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt +++ b/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt @@ -1,45 +1,45 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.128077 # Number of seconds simulated -sim_ticks 128076834500 # Number of ticks simulated -final_tick 128076834500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.128202 # Number of seconds simulated +sim_ticks 128202163500 # Number of ticks simulated +final_tick 128202163500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 523174 # Simulator instruction rate (inst/s) -host_op_rate 667947 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 952153159 # Simulator tick rate (ticks/s) -host_mem_usage 273092 # Number of bytes of host memory used -host_seconds 134.51 # Real time elapsed on the host +host_inst_rate 621865 # Simulator instruction rate (inst/s) +host_op_rate 793946 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1132872219 # Simulator tick rate (ticks/s) +host_mem_usage 278756 # Number of bytes of host memory used +host_seconds 113.17 # Real time elapsed on the host sim_insts 70373651 # Number of instructions simulated sim_ops 89847385 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 128076834500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 233152 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 7925248 # Number of bytes read from this memory -system.physmem.bytes_read::total 8158400 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 233152 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 233152 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 5513600 # Number of bytes written to this memory -system.physmem.bytes_written::total 5513600 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3643 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 123832 # Number of read requests responded to by this memory -system.physmem.num_reads::total 127475 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 86150 # Number of write requests responded to by this memory -system.physmem.num_writes::total 86150 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 1820407 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 61878856 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 63699263 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1820407 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1820407 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 43049159 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 43049159 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 43049159 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1820407 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 61878856 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 106748422 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 128076834500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 128202163500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 233344 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 7939200 # Number of bytes read from this memory +system.physmem.bytes_read::total 8172544 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 233344 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 233344 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 5534528 # Number of bytes written to this memory +system.physmem.bytes_written::total 5534528 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 3646 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 124050 # Number of read requests responded to by this memory +system.physmem.num_reads::total 127696 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 86477 # Number of write requests responded to by this memory +system.physmem.num_writes::total 86477 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 1820125 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 61927192 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 63747317 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1820125 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1820125 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 43170317 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 43170317 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 43170317 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1820125 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 61927192 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 106917634 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 128202163500 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 128076834500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 128202163500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -69,7 +69,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 128076834500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 128202163500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -99,7 +99,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 128076834500 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 128202163500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -129,7 +129,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 128076834500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 128202163500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -160,8 +160,8 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 128076834500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 256153669 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 128202163500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 256404327 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 70373651 # Number of instructions committed @@ -182,7 +182,7 @@ system.cpu.num_mem_refs 43422001 # nu system.cpu.num_load_insts 22866262 # Number of load instructions system.cpu.num_store_insts 20555739 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 256153668.998000 # Number of busy cycles +system.cpu.num_busy_cycles 256404326.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 13741468 # Number of branches fetched @@ -221,56 +221,56 @@ system.cpu.op_class::MemWrite 20555739 22.67% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 90690106 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 128076834500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 128202163500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 155902 # number of replacements -system.cpu.dcache.tags.tagsinuse 4075.927155 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 42601677 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 4075.863858 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 42601590 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 159998 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 266.263810 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 1109655500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4075.927155 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.995099 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.995099 # Average percentage of cache occupancy +system.cpu.dcache.tags.avg_refs 266.263266 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 1116590500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4075.863858 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.995084 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.995084 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 787 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 3263 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 45 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 774 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 3277 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 85731098 # Number of tag accesses system.cpu.dcache.tags.data_accesses 85731098 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 128076834500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 22743361 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 22743361 # number of ReadReq hits +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 128202163500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 22743326 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 22743326 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 19742869 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 19742869 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 83609 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 83609 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 83557 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 83557 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 15919 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 15919 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 42486230 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 42486230 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 42569839 # number of overall hits -system.cpu.dcache.overall_hits::total 42569839 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 36706 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 36706 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 42486195 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 42486195 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 42569752 # number of overall hits +system.cpu.dcache.overall_hits::total 42569752 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 36741 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 36741 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 107032 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 107032 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 40135 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 40135 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 143738 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 143738 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 183873 # number of overall misses -system.cpu.dcache.overall_misses::total 183873 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 577584000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 577584000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 6405138000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 6405138000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 6982722000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 6982722000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 6982722000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 6982722000 # number of overall miss cycles +system.cpu.dcache.SoftPFReq_misses::cpu.data 40187 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 40187 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 143773 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 143773 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 183960 # number of overall misses +system.cpu.dcache.overall_misses::total 183960 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 594992500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 594992500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 6509368500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 6509368500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 7104361000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 7104361000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 7104361000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 7104361000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 22780067 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 22780067 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) @@ -285,38 +285,38 @@ system.cpu.dcache.demand_accesses::cpu.data 42629968 # system.cpu.dcache.demand_accesses::total 42629968 # number of demand (read+write) accesses system.cpu.dcache.overall_accesses::cpu.data 42753712 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 42753712 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001611 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.001611 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001613 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.001613 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005392 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.005392 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.324339 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.324339 # miss rate for SoftPFReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.003372 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.003372 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.004301 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.004301 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15735.411104 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 15735.411104 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59843.205770 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 59843.205770 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 48579.512725 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 48579.512725 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 37975.787636 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 37975.787636 # average overall miss latency +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.324759 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.324759 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.003373 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.003373 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.004303 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.004303 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16194.238045 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 16194.238045 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60817.031355 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 60817.031355 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 49413.735541 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 49413.735541 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 38619.053055 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 38619.053055 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 128175 # number of writebacks -system.cpu.dcache.writebacks::total 128175 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 7598 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 7598 # number of ReadReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 7598 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 7598 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 7598 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 7598 # number of overall MSHR hits +system.cpu.dcache.writebacks::writebacks 127926 # number of writebacks +system.cpu.dcache.writebacks::total 127926 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 7633 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 7633 # number of ReadReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 7633 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 7633 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 7633 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 7633 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 29108 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 29108 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107032 # number of WriteReq MSHR misses @@ -327,16 +327,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 136140 system.cpu.dcache.demand_mshr_misses::total 136140 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 159998 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 159998 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 495022500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 495022500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6298106000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 6298106000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1201109000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1201109000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6793128500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6793128500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7994237500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7994237500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 504199000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 504199000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6402336500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 6402336500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1220892000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1220892000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6906535500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6906535500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8127427500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 8127427500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001278 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001278 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005392 # mshr miss rate for WriteReq accesses @@ -347,26 +347,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003194 system.cpu.dcache.demand_mshr_miss_rate::total 0.003194 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003742 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.003742 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17006.407173 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17006.407173 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 58843.205770 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 58843.205770 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 50344.077458 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 50344.077458 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 49898.108565 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 49898.108565 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 49964.608933 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 49964.608933 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 128076834500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17321.664147 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17321.664147 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59817.031355 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59817.031355 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 51173.275212 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 51173.275212 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 50731.126047 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 50731.126047 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 50797.056838 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 50797.056838 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 128202163500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 16890 # number of replacements -system.cpu.icache.tags.tagsinuse 1732.356634 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1732.172375 # Cycle average of tags in use system.cpu.icache.tags.total_refs 78126184 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 18908 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 4131.911572 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1732.356634 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.845877 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.845877 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1732.172375 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.845787 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.845787 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 2018 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id @@ -375,7 +375,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 1645 system.cpu.icache.tags.occ_task_id_percent::1024 0.985352 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 156309092 # Number of tag accesses system.cpu.icache.tags.data_accesses 156309092 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 128076834500 # Cumulative time (in ticks) in various power states +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 128202163500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 78126184 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 78126184 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 78126184 # number of demand (read+write) hits @@ -388,12 +388,12 @@ system.cpu.icache.demand_misses::cpu.inst 18908 # n system.cpu.icache.demand_misses::total 18908 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 18908 # number of overall misses system.cpu.icache.overall_misses::total 18908 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 426200500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 426200500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 426200500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 426200500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 426200500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 426200500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 429951000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 429951000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 429951000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 429951000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 429951000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 429951000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 78145092 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 78145092 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 78145092 # number of demand (read+write) accesses @@ -406,12 +406,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000242 system.cpu.icache.demand_miss_rate::total 0.000242 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000242 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000242 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22540.749947 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 22540.749947 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 22540.749947 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 22540.749947 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 22540.749947 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 22540.749947 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22739.105141 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 22739.105141 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 22739.105141 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 22739.105141 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 22739.105141 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 22739.105141 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -426,90 +426,90 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 18908 system.cpu.icache.demand_mshr_misses::total 18908 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 18908 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 18908 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 407292500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 407292500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 407292500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 407292500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 407292500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 407292500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 411043000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 411043000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 411043000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 411043000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 411043000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 411043000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000242 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000242 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000242 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000242 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000242 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000242 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21540.749947 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21540.749947 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21540.749947 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 21540.749947 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21540.749947 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 21540.749947 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 128076834500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 95333 # number of replacements -system.cpu.l2cache.tags.tagsinuse 30336.891531 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 114380 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 126455 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.904511 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 27758.605525 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1088.258663 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 1490.027343 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.847125 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.033211 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.045472 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.925808 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 31122 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 156 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1225 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 13921 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 15196 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 624 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.949768 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 3017503 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 3017503 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 128076834500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 128175 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 128175 # number of WritebackDirty hits +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21739.105141 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21739.105141 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21739.105141 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 21739.105141 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21739.105141 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 21739.105141 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 128202163500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.replacements 96062 # number of replacements +system.cpu.l2cache.tags.tagsinuse 31698.820174 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 219067 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 128830 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 1.700435 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 20553705000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 380.243921 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1041.373654 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 30277.202598 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.011604 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.031780 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.923987 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.967371 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 153 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 798 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 14304 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 16713 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 800 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 2912846 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 2912846 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 128202163500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.WritebackDirty_hits::writebacks 127926 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 127926 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 15790 # number of WritebackClean hits system.cpu.l2cache.WritebackClean_hits::total 15790 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 4751 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 4751 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 15265 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 15265 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 31415 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 31415 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 15265 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 36166 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 51431 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 15265 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 36166 # number of overall hits -system.cpu.l2cache.overall_hits::total 51431 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 102281 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 102281 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3643 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 3643 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 21551 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 21551 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 3643 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 123832 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 127475 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 3643 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 123832 # number of overall misses -system.cpu.l2cache.overall_misses::total 127475 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6087670500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 6087670500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 217265500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 217265500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1284434000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 1284434000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 217265500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7372104500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 7589370000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 217265500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7372104500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 7589370000 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 128175 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 128175 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.ReadExReq_hits::cpu.data 4712 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 4712 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 15262 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 15262 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 31236 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 31236 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 15262 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 35948 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 51210 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 15262 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 35948 # number of overall hits +system.cpu.l2cache.overall_hits::total 51210 # number of overall hits +system.cpu.l2cache.ReadExReq_misses::cpu.data 102320 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 102320 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3646 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 3646 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 21730 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 21730 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 3646 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 124050 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 127696 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 3646 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 124050 # number of overall misses +system.cpu.l2cache.overall_misses::total 127696 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6192310500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 6192310500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 221047500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 221047500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1315278500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 1315278500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 221047500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 7507589000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 7728636500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 221047500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 7507589000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 7728636500 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 127926 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 127926 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::writebacks 15790 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::total 15790 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 107032 # number of ReadExReq accesses(hits+misses) @@ -524,101 +524,101 @@ system.cpu.l2cache.demand_accesses::total 178906 # n system.cpu.l2cache.overall_accesses::cpu.inst 18908 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 159998 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 178906 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.955611 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.955611 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.192670 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.192670 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.406884 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.406884 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.192670 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.773960 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.712525 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.192670 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.773960 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.712525 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59519.074901 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59519.074901 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59639.171013 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59639.171013 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59599.740151 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59599.740151 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59639.171013 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59533.113412 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 59536.144342 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59639.171013 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59533.113412 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 59536.144342 # average overall miss latency +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.955976 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.955976 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.192828 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.192828 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.410263 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.410263 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.192828 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.775322 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.713760 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.192828 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.775322 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.713760 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60519.062744 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60519.062744 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60627.399890 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60627.399890 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60528.232858 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60528.232858 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60627.399890 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60520.669085 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 60523.716483 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60627.399890 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60520.669085 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 60523.716483 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 86150 # number of writebacks -system.cpu.l2cache.writebacks::total 86150 # number of writebacks -system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 104 # number of CleanEvict MSHR misses -system.cpu.l2cache.CleanEvict_mshr_misses::total 104 # number of CleanEvict MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102281 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 102281 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3643 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3643 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 21551 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 21551 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3643 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 123832 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 127475 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3643 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 123832 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 127475 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5064860500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5064860500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 180835500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 180835500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1068924000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1068924000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 180835500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6133784500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 6314620000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 180835500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6133784500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 6314620000 # number of overall MSHR miss cycles +system.cpu.l2cache.writebacks::writebacks 86477 # number of writebacks +system.cpu.l2cache.writebacks::total 86477 # number of writebacks +system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 105 # number of CleanEvict MSHR misses +system.cpu.l2cache.CleanEvict_mshr_misses::total 105 # number of CleanEvict MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102320 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 102320 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3646 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3646 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 21730 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 21730 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3646 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 124050 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 127696 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3646 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 124050 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 127696 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5169110500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5169110500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 184587500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 184587500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1097978500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1097978500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 184587500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6267089000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 6451676500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 184587500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6267089000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 6451676500 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955611 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955611 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.192670 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.192670 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.406884 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.406884 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.192670 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.773960 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.712525 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.192670 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.773960 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.712525 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49519.074901 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49519.074901 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49639.171013 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49639.171013 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49599.740151 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49599.740151 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49639.171013 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49533.113412 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49536.144342 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49639.171013 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49533.113412 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49536.144342 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955976 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955976 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.192828 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.192828 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.410263 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.410263 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.192828 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.775322 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.713760 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.192828 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.775322 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.713760 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50519.062744 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50519.062744 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50627.399890 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50627.399890 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50528.232858 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50528.232858 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50627.399890 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50520.669085 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50523.716483 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50627.399890 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50520.669085 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50523.716483 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 351698 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 172817 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3696 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 3119 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3089 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 3224 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3194 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 30 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 128076834500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 128202163500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 71874 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 214325 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 214403 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 16890 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 36910 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 37561 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 107032 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 107032 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 18908 # Transaction distribution @@ -627,53 +627,59 @@ system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_ system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 475898 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 530604 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2291072 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18443072 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 20734144 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 95333 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 5513600 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 274239 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.025051 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.156979 # Request fanout histogram +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18427136 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 20718208 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 96062 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 5534528 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 274968 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.025367 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.157929 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 267399 97.51% 97.51% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 6810 2.48% 99.99% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 268023 97.47% 97.47% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 6915 2.51% 99.99% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 30 0.01% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 274239 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 320914000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 274968 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 320665000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 28362000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 239997000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 128076834500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 25194 # Transaction distribution -system.membus.trans_dist::WritebackDirty 86150 # Transaction distribution -system.membus.trans_dist::CleanEvict 6168 # Transaction distribution -system.membus.trans_dist::ReadExReq 102281 # Transaction distribution -system.membus.trans_dist::ReadExResp 102281 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 25194 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 347268 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 347268 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13672000 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 13672000 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoop_filter.tot_requests 220672 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 93041 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 128202163500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 25376 # Transaction distribution +system.membus.trans_dist::WritebackDirty 86477 # Transaction distribution +system.membus.trans_dist::CleanEvict 6466 # Transaction distribution +system.membus.trans_dist::ReadExReq 102320 # Transaction distribution +system.membus.trans_dist::ReadExResp 102320 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 25376 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 348335 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 348335 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13707072 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 13707072 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 219817 # Request fanout histogram +system.membus.snoop_fanout::samples 127704 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 219817 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 127704 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 219817 # Request fanout histogram -system.membus.reqLayer0.occupancy 568080092 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 127704 # Request fanout histogram +system.membus.reqLayer0.occupancy 569386372 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.4 # Layer utilization (%) -system.membus.respLayer1.occupancy 637375000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 638480000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.5 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt b/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt index 5541d62f0..3cc7eb188 100644 --- a/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.068149 # Nu sim_ticks 68148677000 # Number of ticks simulated final_tick 68148677000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1812136 # Simulator instruction rate (inst/s) -host_op_rate 1835600 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 918865875 # Simulator tick rate (ticks/s) -host_mem_usage 247504 # Number of bytes of host memory used -host_seconds 74.17 # Real time elapsed on the host +host_inst_rate 2595314 # Simulator instruction rate (inst/s) +host_op_rate 2628918 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1315986019 # Simulator tick rate (ticks/s) +host_mem_usage 250608 # Number of bytes of host memory used +host_seconds 51.79 # Real time elapsed on the host sim_insts 134398959 # Number of instructions simulated sim_ops 136139187 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -100,6 +100,12 @@ system.cpu.op_class::MemWrite 20884397 15.32% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 136293808 # Class of executed instruction +system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.pwrStateResidencyTicks::UNDEFINED 68148677000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 171784880 # Transaction distribution system.membus.trans_dist::ReadResp 171784880 # Transaction distribution @@ -116,14 +122,14 @@ system.membus.pkt_size::total 775783958 # Cu system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) system.membus.snoop_fanout::samples 192665100 # Request fanout histogram -system.membus.snoop_fanout::mean 0.698381 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.458961 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 58111520 30.16% 30.16% # Request fanout histogram -system.membus.snoop_fanout::1 134553580 69.84% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 192665100 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 192665100 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt index e21e8eadd..03cf29f2f 100644 --- a/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt @@ -1,47 +1,47 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.203116 # Number of seconds simulated -sim_ticks 203115946500 # Number of ticks simulated -final_tick 203115946500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.203261 # Number of seconds simulated +sim_ticks 203260902500 # Number of ticks simulated +final_tick 203260902500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1206960 # Simulator instruction rate (inst/s) -host_op_rate 1222588 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1824068108 # Simulator tick rate (ticks/s) -host_mem_usage 256216 # Number of bytes of host memory used -host_seconds 111.35 # Real time elapsed on the host +host_inst_rate 1624841 # Simulator instruction rate (inst/s) +host_op_rate 1645879 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2457359114 # Simulator tick rate (ticks/s) +host_mem_usage 261872 # Number of bytes of host memory used +host_seconds 82.72 # Real time elapsed on the host sim_insts 134398959 # Number of instructions simulated sim_ops 136139187 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 203115946500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 525056 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 7828352 # Number of bytes read from this memory -system.physmem.bytes_read::total 8353408 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 525056 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 525056 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 5457280 # Number of bytes written to this memory -system.physmem.bytes_written::total 5457280 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 8204 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 122318 # Number of read requests responded to by this memory -system.physmem.num_reads::total 130522 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 85270 # Number of write requests responded to by this memory -system.physmem.num_writes::total 85270 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 2585006 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 38541297 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 41126303 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2585006 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2585006 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 26867807 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 26867807 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 26867807 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2585006 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 38541297 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 67994110 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 203115946500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 203260902500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 526720 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 7845184 # Number of bytes read from this memory +system.physmem.bytes_read::total 8371904 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 526720 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 526720 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 5476224 # Number of bytes written to this memory +system.physmem.bytes_written::total 5476224 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 8230 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 122581 # Number of read requests responded to by this memory +system.physmem.num_reads::total 130811 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 85566 # Number of write requests responded to by this memory +system.physmem.num_writes::total 85566 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 2591349 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 38596621 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 41187970 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2591349 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2591349 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 26941846 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 26941846 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 26941846 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2591349 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 38596621 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 68129817 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 203260902500 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 203115946500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 406231893 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 203260902500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 406521805 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 134398959 # Number of instructions committed @@ -60,7 +60,7 @@ system.cpu.num_mem_refs 58160261 # nu system.cpu.num_load_insts 37275864 # Number of load instructions system.cpu.num_store_insts 20884397 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 406231892.998000 # Number of busy cycles +system.cpu.num_busy_cycles 406521804.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 12719094 # Number of branches fetched @@ -99,24 +99,24 @@ system.cpu.op_class::MemWrite 20884397 15.32% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 136293808 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 203115946500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 203260902500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 146583 # number of replacements -system.cpu.dcache.tags.tagsinuse 4087.268923 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 4087.215868 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 57960841 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 150679 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 384.664359 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 822359500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4087.268923 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.997868 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.997868 # Average percentage of cache occupancy +system.cpu.dcache.tags.warmup_cycle 829975500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4087.215868 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.997855 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.997855 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 36 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 474 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 3586 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 462 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 3598 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 116373719 # Number of tag accesses system.cpu.dcache.tags.data_accesses 116373719 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 203115946500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 203260902500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 37185800 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 37185800 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 20759140 # number of WriteReq hits @@ -137,16 +137,16 @@ system.cpu.dcache.demand_misses::cpu.data 150664 # n system.cpu.dcache.demand_misses::total 150664 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 150664 # number of overall misses system.cpu.dcache.overall_misses::total 150664 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 1623315500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 1623315500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 6329554000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 6329554000 # number of WriteReq miss cycles -system.cpu.dcache.SwapReq_miss_latency::cpu.data 441000 # number of SwapReq miss cycles -system.cpu.dcache.SwapReq_miss_latency::total 441000 # number of SwapReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 7952869500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 7952869500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 7952869500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 7952869500 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 1655141000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 1655141000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 6433166000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 6433166000 # number of WriteReq miss cycles +system.cpu.dcache.SwapReq_miss_latency::cpu.data 446000 # number of SwapReq miss cycles +system.cpu.dcache.SwapReq_miss_latency::total 446000 # number of SwapReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 8088307000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 8088307000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 8088307000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 8088307000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 37231300 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 37231300 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 20864304 # number of WriteReq accesses(hits+misses) @@ -167,24 +167,24 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.002593 system.cpu.dcache.demand_miss_rate::total 0.002593 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.002593 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.002593 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 35677.263736 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 35677.263736 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60187.459587 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 60187.459587 # average WriteReq miss latency -system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 29400 # average SwapReq miss latency -system.cpu.dcache.SwapReq_avg_miss_latency::total 29400 # average SwapReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 52785.466336 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 52785.466336 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 52785.466336 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 52785.466336 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 36376.725275 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 36376.725275 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61172.701685 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 61172.701685 # average WriteReq miss latency +system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 29733.333333 # average SwapReq miss latency +system.cpu.dcache.SwapReq_avg_miss_latency::total 29733.333333 # average SwapReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 53684.403706 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 53684.403706 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 53684.403706 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 53684.403706 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 123865 # number of writebacks -system.cpu.dcache.writebacks::total 123865 # number of writebacks +system.cpu.dcache.writebacks::writebacks 123615 # number of writebacks +system.cpu.dcache.writebacks::total 123615 # number of writebacks system.cpu.dcache.ReadReq_mshr_misses::cpu.data 45500 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 45500 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 105164 # number of WriteReq MSHR misses @@ -195,16 +195,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 150664 system.cpu.dcache.demand_mshr_misses::total 150664 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 150664 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 150664 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1577815500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 1577815500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6224390000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 6224390000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 426000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.SwapReq_mshr_miss_latency::total 426000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7802205500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7802205500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7802205500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7802205500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1609641000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 1609641000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6328002000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 6328002000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 431000 # number of SwapReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency::total 431000 # number of SwapReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7937643000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 7937643000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7937643000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7937643000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001222 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001222 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005040 # mshr miss rate for WriteReq accesses @@ -215,36 +215,36 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002593 system.cpu.dcache.demand_mshr_miss_rate::total 0.002593 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002593 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002593 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34677.263736 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34677.263736 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59187.459587 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59187.459587 # average WriteReq mshr miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 28400 # average SwapReq mshr miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 28400 # average SwapReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51785.466336 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 51785.466336 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51785.466336 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 51785.466336 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 203115946500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35376.725275 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 35376.725275 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 60172.701685 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 60172.701685 # average WriteReq mshr miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 28733.333333 # average SwapReq mshr miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 28733.333333 # average SwapReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52684.403706 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 52684.403706 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52684.403706 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 52684.403706 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 203260902500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 184976 # number of replacements -system.cpu.icache.tags.tagsinuse 2004.181265 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 2004.091327 # Cycle average of tags in use system.cpu.icache.tags.total_refs 134366557 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 187024 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 718.445531 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 144582800500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 2004.181265 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.978604 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.978604 # Average percentage of cache occupancy +system.cpu.icache.tags.warmup_cycle 144688165500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 2004.091327 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.978560 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.978560 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 2048 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 78 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 85 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 76 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 87 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 456 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1427 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 269294186 # Number of tag accesses system.cpu.icache.tags.data_accesses 269294186 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 203115946500 # Cumulative time (in ticks) in various power states +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 203260902500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 134366557 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 134366557 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 134366557 # number of demand (read+write) hits @@ -257,12 +257,12 @@ system.cpu.icache.demand_misses::cpu.inst 187024 # n system.cpu.icache.demand_misses::total 187024 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 187024 # number of overall misses system.cpu.icache.overall_misses::total 187024 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 2835239000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 2835239000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 2835239000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 2835239000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 2835239000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 2835239000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 2844752500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 2844752500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 2844752500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 2844752500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 2844752500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 2844752500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 134553581 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 134553581 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 134553581 # number of demand (read+write) accesses @@ -275,12 +275,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.001390 system.cpu.icache.demand_miss_rate::total 0.001390 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.001390 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.001390 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15159.760245 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 15159.760245 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 15159.760245 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 15159.760245 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 15159.760245 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 15159.760245 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15210.628048 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 15210.628048 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 15210.628048 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 15210.628048 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 15210.628048 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 15210.628048 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -295,90 +295,90 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 187024 system.cpu.icache.demand_mshr_misses::total 187024 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 187024 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 187024 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 2648215000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 2648215000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 2648215000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 2648215000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 2648215000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 2648215000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 2657728500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 2657728500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 2657728500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 2657728500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 2657728500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 2657728500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001390 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001390 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001390 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.001390 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001390 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.001390 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14159.760245 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14159.760245 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14159.760245 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 14159.760245 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14159.760245 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 14159.760245 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 203115946500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 99022 # number of replacements -system.cpu.l2cache.tags.tagsinuse 30843.699683 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 433832 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 130065 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 3.335501 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 26289.169168 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 3249.863620 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 1304.666895 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.802282 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.099178 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.039815 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.941275 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 31043 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 193 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 566 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 11257 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 18470 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 557 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.947357 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 5588812 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 5588812 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 203115946500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 123865 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 123865 # number of WritebackDirty hits +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14210.628048 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14210.628048 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14210.628048 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 14210.628048 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14210.628048 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 14210.628048 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 203260902500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.replacements 99926 # number of replacements +system.cpu.l2cache.tags.tagsinuse 32138.485238 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 536406 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 132694 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 4.042428 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 26729442000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 711.528666 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 3108.349977 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 28318.606595 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.021714 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.094859 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.864215 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.980789 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 188 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 570 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 10913 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 20279 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 818 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 5486262 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 5486262 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 203260902500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.WritebackDirty_hits::writebacks 123615 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 123615 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 184923 # number of WritebackClean hits system.cpu.l2cache.WritebackClean_hits::total 184923 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 3915 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 3915 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 178820 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 178820 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 24446 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 24446 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 178820 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 28361 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 207181 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 178820 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 28361 # number of overall hits -system.cpu.l2cache.overall_hits::total 207181 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 101264 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 101264 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 8204 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 8204 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 21054 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 21054 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 8204 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 122318 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 130522 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 8204 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 122318 # number of overall misses -system.cpu.l2cache.overall_misses::total 130522 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6025890000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 6025890000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 488461500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 488461500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1252834000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 1252834000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 488461500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7278724000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 7767185500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 488461500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7278724000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 7767185500 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 123865 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 123865 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.ReadExReq_hits::cpu.data 3868 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 3868 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 178794 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 178794 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 24230 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 24230 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 178794 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 28098 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 206892 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 178794 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 28098 # number of overall hits +system.cpu.l2cache.overall_hits::total 206892 # number of overall hits +system.cpu.l2cache.ReadExReq_misses::cpu.data 101311 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 101311 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 8230 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 8230 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 21270 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 21270 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 8230 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 122581 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 130811 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 8230 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 122581 # number of overall misses +system.cpu.l2cache.overall_misses::total 130811 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6130000500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 6130000500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 498248500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 498248500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1286927500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 1286927500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 498248500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 7416928000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 7915176500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 498248500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 7416928000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 7915176500 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 123615 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 123615 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::writebacks 184923 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::total 184923 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 105179 # number of ReadExReq accesses(hits+misses) @@ -393,101 +393,101 @@ system.cpu.l2cache.demand_accesses::total 337703 # n system.cpu.l2cache.overall_accesses::cpu.inst 187024 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 150679 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 337703 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.962778 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.962778 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.043866 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.043866 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.462725 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.462725 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.043866 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.811779 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.386499 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.043866 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.811779 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.386499 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59506.734871 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59506.734871 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59539.431984 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59539.431984 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59505.747126 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59505.747126 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59539.431984 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59506.564856 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 59508.630729 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59539.431984 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59506.564856 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 59508.630729 # average overall miss latency +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.963225 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.963225 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.044005 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.044005 # 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average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60540.522479 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60504.348848 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60504.348848 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60540.522479 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60506.342745 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 60508.493170 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60540.522479 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60506.342745 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 60508.493170 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 85270 # number of writebacks -system.cpu.l2cache.writebacks::total 85270 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 85566 # number of writebacks +system.cpu.l2cache.writebacks::total 85566 # number of writebacks system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 96 # number of CleanEvict MSHR misses system.cpu.l2cache.CleanEvict_mshr_misses::total 96 # number of CleanEvict MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 101264 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 101264 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 8204 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 8204 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 21054 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 21054 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 8204 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 122318 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 130522 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 8204 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 122318 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 130522 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5013250000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5013250000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 406421500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 406421500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1042294000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1042294000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 406421500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6055544000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 6461965500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 406421500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6055544000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 6461965500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 101311 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 101311 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 8230 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 8230 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 21270 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 21270 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 8230 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 122581 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 130811 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 8230 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 122581 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 130811 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5116890500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5116890500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 415948500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 415948500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1074227500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1074227500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 415948500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6191118000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 6607066500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 415948500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6191118000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 6607066500 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.962778 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.962778 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.043866 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.043866 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.462725 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.462725 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.043866 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.811779 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.386499 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.043866 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.811779 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.386499 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49506.734871 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49506.734871 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49539.431984 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49539.431984 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49505.747126 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49505.747126 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49539.431984 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49506.564856 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49508.630729 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49539.431984 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49506.564856 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49508.630729 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.963225 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.963225 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.044005 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.044005 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.467473 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.467473 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.044005 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.813524 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.387355 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.044005 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.813524 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.387355 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50506.761359 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50506.761359 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50540.522479 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50540.522479 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50504.348848 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50504.348848 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50540.522479 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50506.342745 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50508.493170 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50540.522479 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50506.342745 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50508.493170 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 669262 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 331559 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 66 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 3547 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3547 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 3837 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3837 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 203115946500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 203260902500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 232524 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 209135 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 209181 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 184976 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 36470 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 37328 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 105179 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 105179 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 187024 # Transaction distribution @@ -496,53 +496,59 @@ system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_ system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 447941 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 1006965 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23808000 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 17570816 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 41378816 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 99022 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 5457280 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 436725 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.008273 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.090579 # Request fanout histogram +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 17554816 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 41362816 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 99926 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 5476224 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 437629 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.008919 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.094016 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 433112 99.17% 99.17% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 3613 0.83% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 433726 99.11% 99.11% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 3903 0.89% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 436725 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 643472000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 437629 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 643222000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 280536000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 226018500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 203115946500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 29258 # Transaction distribution -system.membus.trans_dist::WritebackDirty 85270 # Transaction distribution -system.membus.trans_dist::CleanEvict 10301 # Transaction distribution -system.membus.trans_dist::ReadExReq 101264 # Transaction distribution -system.membus.trans_dist::ReadExResp 101264 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 29258 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 356615 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 356615 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13810688 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 13810688 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoop_filter.tot_requests 226995 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 96184 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 203260902500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 29500 # Transaction distribution +system.membus.trans_dist::WritebackDirty 85566 # Transaction distribution +system.membus.trans_dist::CleanEvict 10618 # Transaction distribution +system.membus.trans_dist::ReadExReq 101311 # Transaction distribution +system.membus.trans_dist::ReadExResp 101311 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 29500 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 357806 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 357806 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13848128 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 13848128 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 226093 # Request fanout histogram +system.membus.snoop_fanout::samples 130811 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 226093 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 130811 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 226093 # Request fanout histogram -system.membus.reqLayer0.occupancy 568574500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 130811 # Request fanout histogram +system.membus.reqLayer0.occupancy 570211500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.membus.respLayer1.occupancy 652610000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 654055000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.3 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/51.memcheck/ref/null/none/memcheck/stats.txt b/tests/quick/se/51.memcheck/ref/null/none/memcheck/stats.txt index 50754e5cd..55a02cfdc 100644 --- a/tests/quick/se/51.memcheck/ref/null/none/memcheck/stats.txt +++ b/tests/quick/se/51.memcheck/ref/null/none/memcheck/stats.txt @@ -4,164 +4,164 @@ sim_seconds 0.010000 # Nu sim_ticks 10000000000 # Number of ticks simulated final_tick 10000000000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_tick_rate 494870114 # Simulator tick rate (ticks/s) -host_mem_usage 1444260 # Number of bytes of host memory used -host_seconds 20.21 # Real time elapsed on the host +host_tick_rate 586000670 # Simulator tick rate (ticks/s) +host_mem_usage 1428656 # Number of bytes of host memory used +host_seconds 17.06 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::l0subsys0.tester0 2151552 # Number of bytes read from this memory -system.physmem.bytes_read::l0subsys0.tester1 2168960 # Number of bytes read from this memory -system.physmem.bytes_read::l0subsys1.tester0 2107520 # Number of bytes read from this memory -system.physmem.bytes_read::l0subsys1.tester1 2291904 # Number of bytes read from this memory -system.physmem.bytes_read::l0subsys2.tester0 2067776 # Number of bytes read from this memory -system.physmem.bytes_read::l0subsys2.tester1 2030080 # Number of bytes read from this memory -system.physmem.bytes_read::l0subsys3.tester0 2082688 # Number of bytes read from this memory -system.physmem.bytes_read::l0subsys3.tester1 1995392 # Number of bytes read from this memory -system.physmem.bytes_read::l0subsys4.tester0 2164544 # Number of bytes read from this memory -system.physmem.bytes_read::l0subsys4.tester1 2010944 # Number of bytes read from this memory -system.physmem.bytes_read::l0subsys5.tester0 2155328 # Number of bytes read from this memory -system.physmem.bytes_read::l0subsys5.tester1 2130240 # Number of bytes read from this memory -system.physmem.bytes_read::l2subsys0.tester 2177536 # Number of bytes read from this memory -system.physmem.bytes_read::total 27534464 # Number of bytes read from this memory -system.physmem.bytes_written::writebacks 9685696 # Number of bytes written to this memory -system.physmem.bytes_written::total 9685696 # Number of bytes written to this memory -system.physmem.num_reads::l0subsys0.tester0 33618 # Number of read requests responded to by this memory -system.physmem.num_reads::l0subsys0.tester1 33890 # Number of read requests responded to by this memory -system.physmem.num_reads::l0subsys1.tester0 32930 # Number of read requests responded to by this memory -system.physmem.num_reads::l0subsys1.tester1 35811 # Number of read requests responded to by this memory -system.physmem.num_reads::l0subsys2.tester0 32309 # Number of read requests responded to by this memory -system.physmem.num_reads::l0subsys2.tester1 31720 # Number of read requests responded to by this memory -system.physmem.num_reads::l0subsys3.tester0 32542 # Number of read requests responded to by this memory -system.physmem.num_reads::l0subsys3.tester1 31178 # Number of read requests responded to by this memory -system.physmem.num_reads::l0subsys4.tester0 33821 # Number of read requests responded to by this memory -system.physmem.num_reads::l0subsys4.tester1 31421 # Number of read requests responded to by this memory -system.physmem.num_reads::l0subsys5.tester0 33677 # Number of read requests responded to by this memory -system.physmem.num_reads::l0subsys5.tester1 33285 # Number of read requests responded to by this memory -system.physmem.num_reads::l2subsys0.tester 34024 # Number of read requests responded to by this memory -system.physmem.num_reads::total 430226 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 151339 # Number of write requests responded to by this memory -system.physmem.num_writes::total 151339 # Number of write requests responded to by this memory -system.physmem.bw_read::l0subsys0.tester0 215155200 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::l0subsys0.tester1 216896000 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::l0subsys1.tester0 210752000 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::l0subsys1.tester1 229190400 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::l0subsys2.tester0 206777600 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::l0subsys2.tester1 203008000 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::l0subsys3.tester0 208268800 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::l0subsys3.tester1 199539200 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::l0subsys4.tester0 216454400 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::l0subsys4.tester1 201094400 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::l0subsys5.tester0 215532800 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::l0subsys5.tester1 213024000 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::l2subsys0.tester 217753600 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2753446400 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 968569600 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 968569600 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 968569600 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::l0subsys0.tester0 215155200 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::l0subsys0.tester1 216896000 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::l0subsys1.tester0 210752000 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::l0subsys1.tester1 229190400 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::l0subsys2.tester0 206777600 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::l0subsys2.tester1 203008000 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::l0subsys3.tester0 208268800 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::l0subsys3.tester1 199539200 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::l0subsys4.tester0 216454400 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::l0subsys4.tester1 201094400 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::l0subsys5.tester0 215532800 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::l0subsys5.tester1 213024000 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::l2subsys0.tester 217753600 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3722016000 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 430231 # Number of read requests accepted -system.physmem.writeReqs 151339 # Number of write requests accepted -system.physmem.readBursts 430231 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 151339 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 27531200 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 3264 # Total number of bytes read from write queue -system.physmem.bytesWritten 9684288 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 27534784 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 9685696 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 51 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::l0subsys0.tester0 2056192 # Number of bytes read from this memory +system.physmem.bytes_read::l0subsys0.tester1 2014720 # Number of bytes read from this memory +system.physmem.bytes_read::l0subsys1.tester0 2083456 # Number of bytes read from this memory +system.physmem.bytes_read::l0subsys1.tester1 2130880 # Number of bytes read from this memory +system.physmem.bytes_read::l0subsys2.tester0 2005568 # Number of bytes read from this memory +system.physmem.bytes_read::l0subsys2.tester1 2026048 # Number of bytes read from this memory +system.physmem.bytes_read::l0subsys3.tester0 2065280 # Number of bytes read from this memory +system.physmem.bytes_read::l0subsys3.tester1 2035584 # Number of bytes read from this memory +system.physmem.bytes_read::l0subsys4.tester0 2163904 # Number of bytes read from this memory +system.physmem.bytes_read::l0subsys4.tester1 2093312 # Number of bytes read from this memory +system.physmem.bytes_read::l0subsys5.tester0 2131712 # Number of bytes read from this memory +system.physmem.bytes_read::l0subsys5.tester1 2070336 # Number of bytes read from this memory +system.physmem.bytes_read::l2subsys0.tester 2185536 # Number of bytes read from this memory +system.physmem.bytes_read::total 27062528 # Number of bytes read from this memory +system.physmem.bytes_written::writebacks 9533312 # Number of bytes written to this memory +system.physmem.bytes_written::total 9533312 # Number of bytes written to this memory +system.physmem.num_reads::l0subsys0.tester0 32128 # Number of read requests responded to by this memory +system.physmem.num_reads::l0subsys0.tester1 31480 # Number of read requests responded to by this memory +system.physmem.num_reads::l0subsys1.tester0 32554 # Number of read requests responded to by this memory +system.physmem.num_reads::l0subsys1.tester1 33295 # Number of read requests responded to by this memory +system.physmem.num_reads::l0subsys2.tester0 31337 # Number of read requests responded to by this memory +system.physmem.num_reads::l0subsys2.tester1 31657 # Number of read requests responded to by this memory +system.physmem.num_reads::l0subsys3.tester0 32270 # Number of read requests responded to by this memory +system.physmem.num_reads::l0subsys3.tester1 31806 # Number of read requests responded to by this memory +system.physmem.num_reads::l0subsys4.tester0 33811 # Number of read requests responded to by this memory +system.physmem.num_reads::l0subsys4.tester1 32708 # Number of read requests responded to by this memory +system.physmem.num_reads::l0subsys5.tester0 33308 # Number of read requests responded to by this memory +system.physmem.num_reads::l0subsys5.tester1 32349 # Number of read requests responded to by this memory +system.physmem.num_reads::l2subsys0.tester 34149 # Number of read requests responded to by this memory +system.physmem.num_reads::total 422852 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 148958 # Number of write requests responded to by this memory +system.physmem.num_writes::total 148958 # Number of write requests responded to by this memory +system.physmem.bw_read::l0subsys0.tester0 205619200 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::l0subsys0.tester1 201472000 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::l0subsys1.tester0 208345600 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::l0subsys1.tester1 213088000 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::l0subsys2.tester0 200556800 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::l0subsys2.tester1 202604800 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::l0subsys3.tester0 206528000 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::l0subsys3.tester1 203558400 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::l0subsys4.tester0 216390400 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::l0subsys4.tester1 209331200 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::l0subsys5.tester0 213171200 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::l0subsys5.tester1 207033600 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::l2subsys0.tester 218553600 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2706252800 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 953331200 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 953331200 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 953331200 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::l0subsys0.tester0 205619200 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::l0subsys0.tester1 201472000 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::l0subsys1.tester0 208345600 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::l0subsys1.tester1 213088000 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::l0subsys2.tester0 200556800 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::l0subsys2.tester1 202604800 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::l0subsys3.tester0 206528000 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::l0subsys3.tester1 203558400 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::l0subsys4.tester0 216390400 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::l0subsys4.tester1 209331200 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::l0subsys5.tester0 213171200 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::l0subsys5.tester1 207033600 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::l2subsys0.tester 218553600 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3659584000 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 422854 # Number of read requests accepted +system.physmem.writeReqs 148958 # Number of write requests accepted +system.physmem.readBursts 422854 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 148958 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 27060224 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 2432 # Total number of bytes read from write queue +system.physmem.bytesWritten 9531904 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 27062656 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 9533312 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 38 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 26877 # Per bank write bursts -system.physmem.perBankRdBursts::1 26937 # Per bank write bursts -system.physmem.perBankRdBursts::2 26857 # Per bank write bursts -system.physmem.perBankRdBursts::3 26981 # Per bank write bursts -system.physmem.perBankRdBursts::4 26710 # Per bank write bursts -system.physmem.perBankRdBursts::5 26644 # Per bank write bursts -system.physmem.perBankRdBursts::6 26827 # Per bank write bursts -system.physmem.perBankRdBursts::7 26908 # Per bank write bursts -system.physmem.perBankRdBursts::8 26975 # Per bank write bursts -system.physmem.perBankRdBursts::9 26813 # Per bank write bursts -system.physmem.perBankRdBursts::10 27050 # Per bank write bursts -system.physmem.perBankRdBursts::11 26884 # Per bank write bursts -system.physmem.perBankRdBursts::12 26917 # Per bank write bursts -system.physmem.perBankRdBursts::13 26720 # Per bank write bursts -system.physmem.perBankRdBursts::14 26856 # Per bank write bursts -system.physmem.perBankRdBursts::15 27219 # Per bank write bursts -system.physmem.perBankWrBursts::0 9454 # Per bank write bursts -system.physmem.perBankWrBursts::1 9383 # Per bank write bursts -system.physmem.perBankWrBursts::2 9499 # Per bank write bursts -system.physmem.perBankWrBursts::3 9581 # Per bank write bursts -system.physmem.perBankWrBursts::4 9343 # Per bank write bursts -system.physmem.perBankWrBursts::5 9358 # Per bank write bursts -system.physmem.perBankWrBursts::6 9421 # Per bank write bursts -system.physmem.perBankWrBursts::7 9630 # Per bank write bursts -system.physmem.perBankWrBursts::8 9324 # Per bank write bursts -system.physmem.perBankWrBursts::9 9571 # Per bank write bursts -system.physmem.perBankWrBursts::10 9542 # Per bank write bursts -system.physmem.perBankWrBursts::11 9440 # Per bank write bursts -system.physmem.perBankWrBursts::12 9456 # Per bank write bursts -system.physmem.perBankWrBursts::13 9411 # Per bank write bursts -system.physmem.perBankWrBursts::14 9459 # Per bank write bursts -system.physmem.perBankWrBursts::15 9445 # Per bank write bursts +system.physmem.perBankRdBursts::0 26538 # Per bank write bursts +system.physmem.perBankRdBursts::1 26515 # Per bank write bursts +system.physmem.perBankRdBursts::2 26457 # Per bank write bursts +system.physmem.perBankRdBursts::3 26413 # Per bank write bursts +system.physmem.perBankRdBursts::4 26526 # Per bank write bursts +system.physmem.perBankRdBursts::5 26432 # Per bank write bursts +system.physmem.perBankRdBursts::6 26460 # Per bank write bursts +system.physmem.perBankRdBursts::7 26446 # Per bank write bursts +system.physmem.perBankRdBursts::8 26723 # Per bank write bursts +system.physmem.perBankRdBursts::9 26408 # Per bank write bursts +system.physmem.perBankRdBursts::10 26159 # Per bank write bursts +system.physmem.perBankRdBursts::11 26321 # Per bank write bursts +system.physmem.perBankRdBursts::12 26387 # Per bank write bursts +system.physmem.perBankRdBursts::13 26566 # Per bank write bursts +system.physmem.perBankRdBursts::14 26098 # Per bank write bursts +system.physmem.perBankRdBursts::15 26367 # Per bank write bursts +system.physmem.perBankWrBursts::0 9312 # Per bank write bursts +system.physmem.perBankWrBursts::1 9367 # Per bank write bursts +system.physmem.perBankWrBursts::2 9386 # Per bank write bursts +system.physmem.perBankWrBursts::3 9443 # Per bank write bursts +system.physmem.perBankWrBursts::4 9257 # Per bank write bursts +system.physmem.perBankWrBursts::5 9263 # Per bank write bursts +system.physmem.perBankWrBursts::6 9303 # Per bank write bursts +system.physmem.perBankWrBursts::7 9331 # Per bank write bursts +system.physmem.perBankWrBursts::8 9435 # Per bank write bursts +system.physmem.perBankWrBursts::9 9399 # Per bank write bursts +system.physmem.perBankWrBursts::10 9280 # Per bank write bursts +system.physmem.perBankWrBursts::11 9145 # Per bank write bursts +system.physmem.perBankWrBursts::12 9382 # Per bank write bursts +system.physmem.perBankWrBursts::13 9282 # Per bank write bursts +system.physmem.perBankWrBursts::14 9214 # Per bank write bursts +system.physmem.perBankWrBursts::15 9137 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 9999931000 # Total gap between requests +system.physmem.totGap 9999908219 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 430231 # Read request sizes (log2) +system.physmem.readPktSize::6 422854 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 151339 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 40581 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 84851 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 88171 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 66344 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 45057 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 31235 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 22114 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 15903 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 10888 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 7742 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 5414 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 3780 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 2518 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1750 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 1229 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 881 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 583 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 395 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 271 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 184 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 106 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 67 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 50 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 35 # What read queue length does an incoming req see +system.physmem.writePktSize::6 148958 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 43122 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 85605 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 84278 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 61946 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 43434 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 30724 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 21728 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 15491 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 10921 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 7752 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 5579 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 3961 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 2651 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1810 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 1278 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 839 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 584 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 407 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 282 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 163 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 99 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 60 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 46 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 32 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 13 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::25 9 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::26 6 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::27 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 8 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see @@ -181,144 +181,145 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 27 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 37 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 2224 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4883 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6853 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 8013 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 8815 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 9458 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 9950 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 10142 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 10187 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 10172 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 10193 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 10353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 10425 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 10538 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 10309 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 10107 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 1834 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 1201 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 900 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 690 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 531 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 451 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 376 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 328 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 307 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 261 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 217 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 182 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 167 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 157 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 153 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 123 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 116 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 102 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 94 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 88 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 74 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 31 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 21 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 23 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 2139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4877 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6843 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 7878 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 8666 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 9331 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 9709 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 9888 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 10059 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 9944 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 10042 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 10156 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 10189 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 10292 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 10096 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 9928 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1820 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1122 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 833 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 613 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 503 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 412 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 340 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 306 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 287 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 268 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 278 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 264 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 248 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 225 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 199 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 177 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 180 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 170 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 165 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 145 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 122 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 61 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 574593 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 64.767764 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 64.530995 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 7.164333 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 567789 98.82% 98.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 6802 1.18% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 565061 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 64.756251 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 64.522780 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 7.121324 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 558476 98.83% 98.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 6582 1.16% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 1 0.00% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::512-639 1 0.00% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 574593 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 9452 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 45.511532 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 43.175305 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 49.584245 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-255 9449 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::total 565061 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 9305 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 45.437292 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 43.280128 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 45.255047 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-255 9302 99.97% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::256-511 2 0.02% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::4608-4863 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 9452 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 9451 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.009311 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.008638 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.155730 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 9411 99.58% 99.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 8 0.08% 99.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 20 0.21% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 10 0.11% 99.98% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::4096-4351 1 0.01% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 9305 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 9305 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.006018 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.005571 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.126830 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 9281 99.74% 99.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 3 0.03% 99.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 13 0.14% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 6 0.06% 99.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::20 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 9451 # Writes before turning the bus around for reads -system.physmem.totQLat 23573477583 # Total ticks spent queuing -system.physmem.totMemAccLat 31639258833 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2150875000 # Total ticks spent in databus transfers -system.physmem.avgQLat 54799.10 # Average queueing delay per DRAM burst -system.physmem.avgBusLat 4999.94 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 73548.88 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 2753.12 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 968.43 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 2753.48 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 968.57 # Average system write bandwidth in MiByte/s +system.physmem.wrPerTurnAround::21 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 9305 # Writes before turning the bus around for reads +system.physmem.totQLat 23113331872 # Total ticks spent queuing +system.physmem.totMemAccLat 31041131872 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2114080000 # Total ticks spent in databus transfers +system.physmem.avgQLat 54665.23 # Average queueing delay per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 73415.23 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2706.02 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 953.19 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 2706.27 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 953.33 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 29.07 # Data bus utilization in percentage -system.physmem.busUtilRead 21.51 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 7.57 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 3.99 # Average read queue length when enqueuing -system.physmem.avgWrQLen 26.91 # Average write queue length when enqueuing -system.physmem.readRowHits 2754 # Number of row buffer hits during reads -system.physmem.writeRowHits 4139 # Number of row buffer hits during writes -system.physmem.readRowHitRate 0.64 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 2.73 # Row buffer hit rate for writes -system.physmem.avgGap 17194.72 # Average gap between requests -system.physmem.pageHitRate 1.19 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 2169221040 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1183602750 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1674394800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 490140720 # Energy for write commands per rank (pJ) +system.physmem.busUtil 28.59 # Data bus utilization in percentage +system.physmem.busUtilRead 21.14 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 7.45 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 3.92 # Average read queue length when enqueuing +system.physmem.avgWrQLen 26.94 # Average write queue length when enqueuing +system.physmem.readRowHits 2662 # Number of row buffer hits during reads +system.physmem.writeRowHits 4016 # Number of row buffer hits during writes +system.physmem.readRowHitRate 0.63 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 2.70 # Row buffer hit rate for writes +system.physmem.avgGap 17488.10 # Average gap between requests +system.physmem.pageHitRate 1.17 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 2139737040 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1167515250 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1651455000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 483654240 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 652991040 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 6786500940 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 45612000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 13002463290 # Total energy per rank (pJ) -system.physmem_0.averagePower 1300.531796 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 39716528 # Time in different power states +system.physmem_0.actBackEnergy 6798762495 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 34896750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 12929011815 # Total energy per rank (pJ) +system.physmem_0.averagePower 1293.176305 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 21746512 # Time in different power states system.physmem_0.memoryStateTime::REF 333840000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 9624262222 # Time in different power states +system.physmem_0.memoryStateTime::ACT 9642298751 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 2173220280 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1185784875 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1679862600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 489998160 # Energy for write commands per rank (pJ) +system.physmem_1.actEnergy 2131012800 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1162755000 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1645597200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 481140000 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 652991040 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 6784084710 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 47754750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 13013696415 # Total energy per rank (pJ) -system.physmem_1.averagePower 1301.650310 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 43432412 # Time in different power states +system.physmem_1.actBackEnergy 6796546335 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 36816750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 12906859125 # Total energy per rank (pJ) +system.physmem_1.averagePower 1290.965729 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 25323820 # Time in different power states system.physmem_1.memoryStateTime::REF 333840000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 9620586338 # Time in different power states +system.physmem_1.memoryStateTime::ACT 9638682193 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states system.l0subsys0.checkers0.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states system.l0subsys0.checkers1.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states system.l0subsys0.tester0.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states -system.l0subsys0.tester0.numPackets 67424 # Number of packets generated -system.l0subsys0.tester0.numRetries 2732 # Number of retries -system.l0subsys0.tester0.retryTicks 71787172 # Time spent waiting due to back-pressure (ticks) +system.l0subsys0.tester0.numPackets 65034 # Number of packets generated +system.l0subsys0.tester0.numRetries 2631 # Number of retries +system.l0subsys0.tester0.retryTicks 64675381 # Time spent waiting due to back-pressure (ticks) system.l0subsys0.tester1.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states -system.l0subsys0.tester1.numPackets 67451 # Number of packets generated -system.l0subsys0.tester1.numRetries 2817 # Number of retries -system.l0subsys0.tester1.retryTicks 69161680 # Time spent waiting due to back-pressure (ticks) +system.l0subsys0.tester1.numPackets 65594 # Number of packets generated +system.l0subsys0.tester1.numRetries 2683 # Number of retries +system.l0subsys0.tester1.retryTicks 67015418 # Time spent waiting due to back-pressure (ticks) system.l0subsys0.xbar.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. system.l0subsys0.xbar.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.l0subsys0.xbar.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. @@ -326,49 +327,49 @@ system.l0subsys0.xbar.snoop_filter.tot_snoops 0 system.l0subsys0.xbar.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.l0subsys0.xbar.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.l0subsys0.xbar.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states -system.l0subsys0.xbar.trans_dist::ReadReq 86409 # Transaction distribution -system.l0subsys0.xbar.trans_dist::ReadResp 82049 # Transaction distribution -system.l0subsys0.xbar.trans_dist::ReadRespWithInvalidate 4359 # Transaction distribution -system.l0subsys0.xbar.trans_dist::WriteReq 48466 # Transaction distribution -system.l0subsys0.xbar.trans_dist::WriteResp 48465 # Transaction distribution -system.l0subsys0.xbar.trans_dist::WritebackDirty 24314 # Transaction distribution -system.l0subsys0.xbar.trans_dist::CleanEvict 58742 # Transaction distribution -system.l0subsys0.xbar.trans_dist::UpgradeReq 16073 # Transaction distribution -system.l0subsys0.xbar.trans_dist::ReadExReq 19288 # Transaction distribution -system.l0subsys0.xbar.trans_dist::ReadSharedReq 26254 # Transaction distribution -system.l0subsys0.xbar.pkt_count_system.l0subsys0.checkers0-master::system.l1subsys0.cache0.cpu_side 134847 # Packet count per connected master and slave (bytes) -system.l0subsys0.xbar.pkt_count_system.l0subsys0.checkers1-master::system.l1subsys0.cache0.cpu_side 134901 # Packet count per connected master and slave (bytes) -system.l0subsys0.xbar.pkt_count::total 269748 # Packet count per connected master and slave (bytes) -system.l0subsys0.xbar.pkt_size_system.l0subsys0.checkers0-master::system.l1subsys0.cache0.cpu_side 539392 # Cumulative packet size per connected master and slave (bytes) -system.l0subsys0.xbar.pkt_size_system.l0subsys0.checkers1-master::system.l1subsys0.cache0.cpu_side 539600 # Cumulative packet size per connected master and slave (bytes) -system.l0subsys0.xbar.pkt_size::total 1078992 # Cumulative packet size per connected master and slave (bytes) -system.l0subsys0.xbar.snoops 144671 # Total snoops (count) -system.l0subsys0.xbar.snoopTraffic 1556096 # Total snoop traffic (bytes) -system.l0subsys0.xbar.snoop_fanout::samples 282356 # Request fanout histogram +system.l0subsys0.xbar.trans_dist::ReadReq 84077 # Transaction distribution +system.l0subsys0.xbar.trans_dist::ReadResp 79156 # Transaction distribution +system.l0subsys0.xbar.trans_dist::ReadRespWithInvalidate 4921 # Transaction distribution +system.l0subsys0.xbar.trans_dist::WriteReq 46551 # Transaction distribution +system.l0subsys0.xbar.trans_dist::WriteResp 46551 # Transaction distribution +system.l0subsys0.xbar.trans_dist::WritebackDirty 22891 # Transaction distribution +system.l0subsys0.xbar.trans_dist::CleanEvict 74163 # Transaction distribution +system.l0subsys0.xbar.trans_dist::UpgradeReq 16582 # Transaction distribution +system.l0subsys0.xbar.trans_dist::ReadExReq 21053 # Transaction distribution +system.l0subsys0.xbar.trans_dist::ReadSharedReq 27577 # Transaction distribution +system.l0subsys0.xbar.pkt_count_system.l0subsys0.checkers0-master::system.l1subsys0.cache0.cpu_side 130068 # Packet count per connected master and slave (bytes) +system.l0subsys0.xbar.pkt_count_system.l0subsys0.checkers1-master::system.l1subsys0.cache0.cpu_side 131188 # Packet count per connected master and slave (bytes) +system.l0subsys0.xbar.pkt_count::total 261256 # Packet count per connected master and slave (bytes) +system.l0subsys0.xbar.pkt_size_system.l0subsys0.checkers0-master::system.l1subsys0.cache0.cpu_side 520272 # Cumulative packet size per connected master and slave (bytes) +system.l0subsys0.xbar.pkt_size_system.l0subsys0.checkers1-master::system.l1subsys0.cache0.cpu_side 524752 # Cumulative packet size per connected master and slave (bytes) +system.l0subsys0.xbar.pkt_size::total 1045024 # Cumulative packet size per connected master and slave (bytes) +system.l0subsys0.xbar.snoops 162266 # Total snoops (count) +system.l0subsys0.xbar.snoopTraffic 1465024 # Total snoop traffic (bytes) +system.l0subsys0.xbar.snoop_fanout::samples 295596 # Request fanout histogram system.l0subsys0.xbar.snoop_fanout::mean 0 # Request fanout histogram system.l0subsys0.xbar.snoop_fanout::stdev 0 # Request fanout histogram system.l0subsys0.xbar.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.l0subsys0.xbar.snoop_fanout::0 282356 100.00% 100.00% # Request fanout histogram +system.l0subsys0.xbar.snoop_fanout::0 295596 100.00% 100.00% # Request fanout histogram system.l0subsys0.xbar.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.l0subsys0.xbar.snoop_fanout::min_value 0 # Request fanout histogram system.l0subsys0.xbar.snoop_fanout::max_value 0 # Request fanout histogram -system.l0subsys0.xbar.snoop_fanout::total 282356 # Request fanout histogram -system.l0subsys0.xbar.reqLayer0.occupancy 255038046 # Layer occupancy (ticks) -system.l0subsys0.xbar.reqLayer0.utilization 2.6 # Layer utilization (%) -system.l0subsys0.xbar.respLayer0.occupancy 116989147 # Layer occupancy (ticks) -system.l0subsys0.xbar.respLayer0.utilization 1.2 # Layer utilization (%) -system.l0subsys0.xbar.respLayer1.occupancy 116411811 # Layer occupancy (ticks) -system.l0subsys0.xbar.respLayer1.utilization 1.2 # Layer utilization (%) +system.l0subsys0.xbar.snoop_fanout::total 295596 # Request fanout histogram +system.l0subsys0.xbar.reqLayer0.occupancy 246613193 # Layer occupancy (ticks) +system.l0subsys0.xbar.reqLayer0.utilization 2.5 # Layer utilization (%) +system.l0subsys0.xbar.respLayer0.occupancy 112497122 # Layer occupancy (ticks) +system.l0subsys0.xbar.respLayer0.utilization 1.1 # Layer utilization (%) +system.l0subsys0.xbar.respLayer1.occupancy 113637927 # Layer occupancy (ticks) +system.l0subsys0.xbar.respLayer1.utilization 1.1 # Layer utilization (%) system.l0subsys1.checkers0.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states system.l0subsys1.checkers1.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states system.l0subsys1.tester0.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states -system.l0subsys1.tester0.numPackets 65180 # Number of packets generated -system.l0subsys1.tester0.numRetries 2851 # Number of retries -system.l0subsys1.tester0.retryTicks 74729692 # Time spent waiting due to back-pressure (ticks) +system.l0subsys1.tester0.numPackets 64234 # Number of packets generated +system.l0subsys1.tester0.numRetries 2842 # Number of retries +system.l0subsys1.tester0.retryTicks 72381522 # Time spent waiting due to back-pressure (ticks) system.l0subsys1.tester1.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states -system.l0subsys1.tester1.numPackets 68174 # Number of packets generated -system.l0subsys1.tester1.numRetries 2790 # Number of retries -system.l0subsys1.tester1.retryTicks 74335880 # Time spent waiting due to back-pressure (ticks) +system.l0subsys1.tester1.numPackets 67237 # Number of packets generated +system.l0subsys1.tester1.numRetries 2791 # Number of retries +system.l0subsys1.tester1.retryTicks 70676938 # Time spent waiting due to back-pressure (ticks) system.l0subsys1.xbar.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. system.l0subsys1.xbar.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.l0subsys1.xbar.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. @@ -376,49 +377,49 @@ system.l0subsys1.xbar.snoop_filter.tot_snoops 0 system.l0subsys1.xbar.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.l0subsys1.xbar.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.l0subsys1.xbar.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states -system.l0subsys1.xbar.trans_dist::ReadReq 85972 # Transaction distribution -system.l0subsys1.xbar.trans_dist::ReadResp 82000 # Transaction distribution -system.l0subsys1.xbar.trans_dist::ReadRespWithInvalidate 3972 # Transaction distribution -system.l0subsys1.xbar.trans_dist::WriteReq 47382 # Transaction distribution -system.l0subsys1.xbar.trans_dist::WriteResp 47382 # Transaction distribution -system.l0subsys1.xbar.trans_dist::WritebackDirty 24686 # Transaction distribution -system.l0subsys1.xbar.trans_dist::CleanEvict 59276 # Transaction distribution -system.l0subsys1.xbar.trans_dist::UpgradeReq 14812 # Transaction distribution -system.l0subsys1.xbar.trans_dist::ReadExReq 17637 # Transaction distribution -system.l0subsys1.xbar.trans_dist::ReadSharedReq 23647 # Transaction distribution -system.l0subsys1.xbar.pkt_count_system.l0subsys1.checkers0-master::system.l1subsys0.cache1.cpu_side 130360 # Packet count per connected master and slave (bytes) -system.l0subsys1.xbar.pkt_count_system.l0subsys1.checkers1-master::system.l1subsys0.cache1.cpu_side 136348 # Packet count per connected master and slave (bytes) -system.l0subsys1.xbar.pkt_count::total 266708 # Packet count per connected master and slave (bytes) -system.l0subsys1.xbar.pkt_size_system.l0subsys1.checkers0-master::system.l1subsys0.cache1.cpu_side 521440 # Cumulative packet size per connected master and slave (bytes) -system.l0subsys1.xbar.pkt_size_system.l0subsys1.checkers1-master::system.l1subsys0.cache1.cpu_side 545392 # Cumulative packet size per connected master and slave (bytes) -system.l0subsys1.xbar.pkt_size::total 1066832 # Cumulative packet size per connected master and slave (bytes) -system.l0subsys1.xbar.snoops 140058 # Total snoops (count) -system.l0subsys1.xbar.snoopTraffic 1579904 # Total snoop traffic (bytes) -system.l0subsys1.xbar.snoop_fanout::samples 276384 # Request fanout histogram +system.l0subsys1.xbar.trans_dist::ReadReq 84459 # Transaction distribution +system.l0subsys1.xbar.trans_dist::ReadResp 79428 # Transaction distribution +system.l0subsys1.xbar.trans_dist::ReadRespWithInvalidate 5031 # Transaction distribution +system.l0subsys1.xbar.trans_dist::WriteReq 47012 # Transaction distribution +system.l0subsys1.xbar.trans_dist::WriteResp 47011 # Transaction distribution +system.l0subsys1.xbar.trans_dist::WritebackDirty 23704 # Transaction distribution +system.l0subsys1.xbar.trans_dist::CleanEvict 74816 # Transaction distribution +system.l0subsys1.xbar.trans_dist::UpgradeReq 15753 # Transaction distribution +system.l0subsys1.xbar.trans_dist::ReadExReq 20596 # Transaction distribution +system.l0subsys1.xbar.trans_dist::ReadSharedReq 26573 # Transaction distribution +system.l0subsys1.xbar.pkt_count_system.l0subsys1.checkers0-master::system.l1subsys0.cache1.cpu_side 128468 # Packet count per connected master and slave (bytes) +system.l0subsys1.xbar.pkt_count_system.l0subsys1.checkers1-master::system.l1subsys0.cache1.cpu_side 134473 # Packet count per connected master and slave (bytes) +system.l0subsys1.xbar.pkt_count::total 262941 # Packet count per connected master and slave (bytes) +system.l0subsys1.xbar.pkt_size_system.l0subsys1.checkers0-master::system.l1subsys0.cache1.cpu_side 513872 # Cumulative packet size per connected master and slave (bytes) +system.l0subsys1.xbar.pkt_size_system.l0subsys1.checkers1-master::system.l1subsys0.cache1.cpu_side 537896 # Cumulative packet size per connected master and slave (bytes) +system.l0subsys1.xbar.pkt_size::total 1051768 # Cumulative packet size per connected master and slave (bytes) +system.l0subsys1.xbar.snoops 161442 # Total snoops (count) +system.l0subsys1.xbar.snoopTraffic 1517056 # Total snoop traffic (bytes) +system.l0subsys1.xbar.snoop_fanout::samples 295865 # Request fanout histogram system.l0subsys1.xbar.snoop_fanout::mean 0 # Request fanout histogram system.l0subsys1.xbar.snoop_fanout::stdev 0 # Request fanout histogram system.l0subsys1.xbar.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.l0subsys1.xbar.snoop_fanout::0 276384 100.00% 100.00% # Request fanout histogram +system.l0subsys1.xbar.snoop_fanout::0 295865 100.00% 100.00% # Request fanout histogram system.l0subsys1.xbar.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.l0subsys1.xbar.snoop_fanout::min_value 0 # Request fanout histogram system.l0subsys1.xbar.snoop_fanout::max_value 0 # Request fanout histogram -system.l0subsys1.xbar.snoop_fanout::total 276384 # Request fanout histogram -system.l0subsys1.xbar.reqLayer0.occupancy 252009041 # Layer occupancy (ticks) +system.l0subsys1.xbar.snoop_fanout::total 295865 # Request fanout histogram +system.l0subsys1.xbar.reqLayer0.occupancy 248872620 # Layer occupancy (ticks) system.l0subsys1.xbar.reqLayer0.utilization 2.5 # Layer utilization (%) -system.l0subsys1.xbar.respLayer0.occupancy 113396564 # Layer occupancy (ticks) +system.l0subsys1.xbar.respLayer0.occupancy 110615455 # Layer occupancy (ticks) system.l0subsys1.xbar.respLayer0.utilization 1.1 # Layer utilization (%) -system.l0subsys1.xbar.respLayer1.occupancy 118377078 # Layer occupancy (ticks) +system.l0subsys1.xbar.respLayer1.occupancy 116451863 # Layer occupancy (ticks) system.l0subsys1.xbar.respLayer1.utilization 1.2 # Layer utilization (%) system.l0subsys2.checkers0.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states system.l0subsys2.checkers1.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states system.l0subsys2.tester0.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states -system.l0subsys2.tester0.numPackets 65223 # Number of packets generated -system.l0subsys2.tester0.numRetries 2584 # Number of retries -system.l0subsys2.tester0.retryTicks 64900705 # Time spent waiting due to back-pressure (ticks) +system.l0subsys2.tester0.numPackets 65812 # Number of packets generated +system.l0subsys2.tester0.numRetries 2732 # Number of retries +system.l0subsys2.tester0.retryTicks 67922794 # Time spent waiting due to back-pressure (ticks) system.l0subsys2.tester1.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states -system.l0subsys2.tester1.numPackets 65256 # Number of packets generated -system.l0subsys2.tester1.numRetries 2558 # Number of retries -system.l0subsys2.tester1.retryTicks 64249844 # Time spent waiting due to back-pressure (ticks) +system.l0subsys2.tester1.numPackets 65437 # Number of packets generated +system.l0subsys2.tester1.numRetries 2695 # Number of retries +system.l0subsys2.tester1.retryTicks 66990492 # Time spent waiting due to back-pressure (ticks) system.l0subsys2.xbar.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. system.l0subsys2.xbar.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.l0subsys2.xbar.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. @@ -426,49 +427,49 @@ system.l0subsys2.xbar.snoop_filter.tot_snoops 0 system.l0subsys2.xbar.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.l0subsys2.xbar.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.l0subsys2.xbar.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states -system.l0subsys2.xbar.trans_dist::ReadReq 84127 # Transaction distribution -system.l0subsys2.xbar.trans_dist::ReadResp 80122 # Transaction distribution -system.l0subsys2.xbar.trans_dist::ReadRespWithInvalidate 4004 # Transaction distribution -system.l0subsys2.xbar.trans_dist::WriteReq 46352 # Transaction distribution -system.l0subsys2.xbar.trans_dist::WriteResp 46352 # Transaction distribution -system.l0subsys2.xbar.trans_dist::WritebackDirty 22898 # Transaction distribution -system.l0subsys2.xbar.trans_dist::CleanEvict 55455 # Transaction distribution -system.l0subsys2.xbar.trans_dist::UpgradeReq 15512 # Transaction distribution -system.l0subsys2.xbar.trans_dist::ReadExReq 18753 # Transaction distribution -system.l0subsys2.xbar.trans_dist::ReadSharedReq 25514 # Transaction distribution -system.l0subsys2.xbar.pkt_count_system.l0subsys2.checkers0-master::system.l1subsys1.cache0.cpu_side 130445 # Packet count per connected master and slave (bytes) -system.l0subsys2.xbar.pkt_count_system.l0subsys2.checkers1-master::system.l1subsys1.cache0.cpu_side 130512 # Packet count per connected master and slave (bytes) -system.l0subsys2.xbar.pkt_count::total 260957 # Packet count per connected master and slave (bytes) -system.l0subsys2.xbar.pkt_size_system.l0subsys2.checkers0-master::system.l1subsys1.cache0.cpu_side 521776 # Cumulative packet size per connected master and slave (bytes) -system.l0subsys2.xbar.pkt_size_system.l0subsys2.checkers1-master::system.l1subsys1.cache0.cpu_side 522048 # Cumulative packet size per connected master and slave (bytes) -system.l0subsys2.xbar.pkt_size::total 1043824 # Cumulative packet size per connected master and slave (bytes) -system.l0subsys2.xbar.snoops 138132 # Total snoops (count) -system.l0subsys2.xbar.snoopTraffic 1465472 # Total snoop traffic (bytes) -system.l0subsys2.xbar.snoop_fanout::samples 271270 # Request fanout histogram +system.l0subsys2.xbar.trans_dist::ReadReq 84334 # Transaction distribution +system.l0subsys2.xbar.trans_dist::ReadResp 79404 # Transaction distribution +system.l0subsys2.xbar.trans_dist::ReadRespWithInvalidate 4929 # Transaction distribution +system.l0subsys2.xbar.trans_dist::WriteReq 46915 # Transaction distribution +system.l0subsys2.xbar.trans_dist::WriteResp 46915 # Transaction distribution +system.l0subsys2.xbar.trans_dist::WritebackDirty 22486 # Transaction distribution +system.l0subsys2.xbar.trans_dist::CleanEvict 73149 # Transaction distribution +system.l0subsys2.xbar.trans_dist::UpgradeReq 16126 # Transaction distribution +system.l0subsys2.xbar.trans_dist::ReadExReq 21115 # Transaction distribution +system.l0subsys2.xbar.trans_dist::ReadSharedReq 28234 # Transaction distribution +system.l0subsys2.xbar.pkt_count_system.l0subsys2.checkers0-master::system.l1subsys1.cache0.cpu_side 131623 # Packet count per connected master and slave (bytes) +system.l0subsys2.xbar.pkt_count_system.l0subsys2.checkers1-master::system.l1subsys1.cache0.cpu_side 130874 # Packet count per connected master and slave (bytes) +system.l0subsys2.xbar.pkt_count::total 262497 # Packet count per connected master and slave (bytes) +system.l0subsys2.xbar.pkt_size_system.l0subsys2.checkers0-master::system.l1subsys1.cache0.cpu_side 526488 # Cumulative packet size per connected master and slave (bytes) +system.l0subsys2.xbar.pkt_size_system.l0subsys2.checkers1-master::system.l1subsys1.cache0.cpu_side 523496 # Cumulative packet size per connected master and slave (bytes) +system.l0subsys2.xbar.pkt_size::total 1049984 # Cumulative packet size per connected master and slave (bytes) +system.l0subsys2.xbar.snoops 161110 # Total snoops (count) +system.l0subsys2.xbar.snoopTraffic 1439104 # Total snoop traffic (bytes) +system.l0subsys2.xbar.snoop_fanout::samples 295231 # Request fanout histogram system.l0subsys2.xbar.snoop_fanout::mean 0 # Request fanout histogram system.l0subsys2.xbar.snoop_fanout::stdev 0 # Request fanout histogram system.l0subsys2.xbar.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.l0subsys2.xbar.snoop_fanout::0 271270 100.00% 100.00% # Request fanout histogram +system.l0subsys2.xbar.snoop_fanout::0 295231 100.00% 100.00% # Request fanout histogram system.l0subsys2.xbar.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.l0subsys2.xbar.snoop_fanout::min_value 0 # Request fanout histogram system.l0subsys2.xbar.snoop_fanout::max_value 0 # Request fanout histogram -system.l0subsys2.xbar.snoop_fanout::total 271270 # Request fanout histogram -system.l0subsys2.xbar.reqLayer0.occupancy 246097783 # Layer occupancy (ticks) +system.l0subsys2.xbar.snoop_fanout::total 295231 # Request fanout histogram +system.l0subsys2.xbar.reqLayer0.occupancy 248142071 # Layer occupancy (ticks) system.l0subsys2.xbar.reqLayer0.utilization 2.5 # Layer utilization (%) -system.l0subsys2.xbar.respLayer0.occupancy 113755357 # Layer occupancy (ticks) +system.l0subsys2.xbar.respLayer0.occupancy 114094156 # Layer occupancy (ticks) system.l0subsys2.xbar.respLayer0.utilization 1.1 # Layer utilization (%) -system.l0subsys2.xbar.respLayer1.occupancy 113314488 # Layer occupancy (ticks) +system.l0subsys2.xbar.respLayer1.occupancy 113403149 # Layer occupancy (ticks) system.l0subsys2.xbar.respLayer1.utilization 1.1 # Layer utilization (%) system.l0subsys3.checkers0.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states system.l0subsys3.checkers1.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states system.l0subsys3.tester0.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states -system.l0subsys3.tester0.numPackets 66015 # Number of packets generated -system.l0subsys3.tester0.numRetries 2474 # Number of retries -system.l0subsys3.tester0.retryTicks 61325178 # Time spent waiting due to back-pressure (ticks) +system.l0subsys3.tester0.numPackets 65010 # Number of packets generated +system.l0subsys3.tester0.numRetries 2630 # Number of retries +system.l0subsys3.tester0.retryTicks 64351691 # Time spent waiting due to back-pressure (ticks) system.l0subsys3.tester1.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states -system.l0subsys3.tester1.numPackets 63774 # Number of packets generated -system.l0subsys3.tester1.numRetries 2406 # Number of retries -system.l0subsys3.tester1.retryTicks 60532485 # Time spent waiting due to back-pressure (ticks) +system.l0subsys3.tester1.numPackets 65550 # Number of packets generated +system.l0subsys3.tester1.numRetries 2637 # Number of retries +system.l0subsys3.tester1.retryTicks 67267239 # Time spent waiting due to back-pressure (ticks) system.l0subsys3.xbar.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. system.l0subsys3.xbar.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.l0subsys3.xbar.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. @@ -476,49 +477,49 @@ system.l0subsys3.xbar.snoop_filter.tot_snoops 0 system.l0subsys3.xbar.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.l0subsys3.xbar.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.l0subsys3.xbar.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states -system.l0subsys3.xbar.trans_dist::ReadReq 83355 # Transaction distribution -system.l0subsys3.xbar.trans_dist::ReadResp 78973 # Transaction distribution -system.l0subsys3.xbar.trans_dist::ReadRespWithInvalidate 4382 # Transaction distribution -system.l0subsys3.xbar.trans_dist::WriteReq 46434 # Transaction distribution -system.l0subsys3.xbar.trans_dist::WriteResp 46434 # Transaction distribution -system.l0subsys3.xbar.trans_dist::WritebackDirty 22791 # Transaction distribution -system.l0subsys3.xbar.trans_dist::CleanEvict 55545 # Transaction distribution -system.l0subsys3.xbar.trans_dist::UpgradeReq 16499 # Transaction distribution -system.l0subsys3.xbar.trans_dist::ReadExReq 19577 # Transaction distribution -system.l0subsys3.xbar.trans_dist::ReadSharedReq 26175 # Transaction distribution -system.l0subsys3.xbar.pkt_count_system.l0subsys3.checkers0-master::system.l1subsys1.cache1.cpu_side 132030 # Packet count per connected master and slave (bytes) -system.l0subsys3.xbar.pkt_count_system.l0subsys3.checkers1-master::system.l1subsys1.cache1.cpu_side 127548 # Packet count per connected master and slave (bytes) -system.l0subsys3.xbar.pkt_count::total 259578 # Packet count per connected master and slave (bytes) -system.l0subsys3.xbar.pkt_size_system.l0subsys3.checkers0-master::system.l1subsys1.cache1.cpu_side 528120 # Cumulative packet size per connected master and slave (bytes) -system.l0subsys3.xbar.pkt_size_system.l0subsys3.checkers1-master::system.l1subsys1.cache1.cpu_side 510192 # Cumulative packet size per connected master and slave (bytes) -system.l0subsys3.xbar.pkt_size::total 1038312 # Cumulative packet size per connected master and slave (bytes) -system.l0subsys3.xbar.snoops 140587 # Total snoops (count) -system.l0subsys3.xbar.snoopTraffic 1458624 # Total snoop traffic (bytes) -system.l0subsys3.xbar.snoop_fanout::samples 272839 # Request fanout histogram +system.l0subsys3.xbar.trans_dist::ReadReq 83832 # Transaction distribution +system.l0subsys3.xbar.trans_dist::ReadResp 78911 # Transaction distribution +system.l0subsys3.xbar.trans_dist::ReadRespWithInvalidate 4921 # Transaction distribution +system.l0subsys3.xbar.trans_dist::WriteReq 46728 # Transaction distribution +system.l0subsys3.xbar.trans_dist::WriteResp 46727 # Transaction distribution +system.l0subsys3.xbar.trans_dist::WritebackDirty 23115 # Transaction distribution +system.l0subsys3.xbar.trans_dist::CleanEvict 73076 # Transaction distribution +system.l0subsys3.xbar.trans_dist::UpgradeReq 16273 # Transaction distribution +system.l0subsys3.xbar.trans_dist::ReadExReq 21213 # Transaction distribution +system.l0subsys3.xbar.trans_dist::ReadSharedReq 27196 # Transaction distribution +system.l0subsys3.xbar.pkt_count_system.l0subsys3.checkers0-master::system.l1subsys1.cache1.cpu_side 130019 # Packet count per connected master and slave (bytes) +system.l0subsys3.xbar.pkt_count_system.l0subsys3.checkers1-master::system.l1subsys1.cache1.cpu_side 131100 # Packet count per connected master and slave (bytes) +system.l0subsys3.xbar.pkt_count::total 261119 # Packet count per connected master and slave (bytes) +system.l0subsys3.xbar.pkt_size_system.l0subsys3.checkers0-master::system.l1subsys1.cache1.cpu_side 520080 # Cumulative packet size per connected master and slave (bytes) +system.l0subsys3.xbar.pkt_size_system.l0subsys3.checkers1-master::system.l1subsys1.cache1.cpu_side 524400 # Cumulative packet size per connected master and slave (bytes) +system.l0subsys3.xbar.pkt_size::total 1044480 # Cumulative packet size per connected master and slave (bytes) +system.l0subsys3.xbar.snoops 160873 # Total snoops (count) +system.l0subsys3.xbar.snoopTraffic 1479360 # Total snoop traffic (bytes) +system.l0subsys3.xbar.snoop_fanout::samples 294076 # Request fanout histogram system.l0subsys3.xbar.snoop_fanout::mean 0 # Request fanout histogram system.l0subsys3.xbar.snoop_fanout::stdev 0 # Request fanout histogram system.l0subsys3.xbar.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.l0subsys3.xbar.snoop_fanout::0 272839 100.00% 100.00% # Request fanout histogram +system.l0subsys3.xbar.snoop_fanout::0 294076 100.00% 100.00% # Request fanout histogram system.l0subsys3.xbar.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.l0subsys3.xbar.snoop_fanout::min_value 0 # Request fanout histogram system.l0subsys3.xbar.snoop_fanout::max_value 0 # Request fanout histogram -system.l0subsys3.xbar.snoop_fanout::total 272839 # Request fanout histogram -system.l0subsys3.xbar.reqLayer0.occupancy 244629226 # Layer occupancy (ticks) -system.l0subsys3.xbar.reqLayer0.utilization 2.4 # Layer utilization (%) -system.l0subsys3.xbar.respLayer0.occupancy 114100947 # Layer occupancy (ticks) +system.l0subsys3.xbar.snoop_fanout::total 294076 # Request fanout histogram +system.l0subsys3.xbar.reqLayer0.occupancy 246366404 # Layer occupancy (ticks) +system.l0subsys3.xbar.reqLayer0.utilization 2.5 # Layer utilization (%) +system.l0subsys3.xbar.respLayer0.occupancy 112403324 # Layer occupancy (ticks) system.l0subsys3.xbar.respLayer0.utilization 1.1 # Layer utilization (%) -system.l0subsys3.xbar.respLayer1.occupancy 110374985 # Layer occupancy (ticks) +system.l0subsys3.xbar.respLayer1.occupancy 113183873 # Layer occupancy (ticks) system.l0subsys3.xbar.respLayer1.utilization 1.1 # Layer utilization (%) system.l0subsys4.checkers0.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states system.l0subsys4.checkers1.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states system.l0subsys4.tester0.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states -system.l0subsys4.tester0.numPackets 67184 # Number of packets generated -system.l0subsys4.tester0.numRetries 2523 # Number of retries -system.l0subsys4.tester0.retryTicks 66430147 # Time spent waiting due to back-pressure (ticks) +system.l0subsys4.tester0.numPackets 66012 # Number of packets generated +system.l0subsys4.tester0.numRetries 2782 # Number of retries +system.l0subsys4.tester0.retryTicks 70240058 # Time spent waiting due to back-pressure (ticks) system.l0subsys4.tester1.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states -system.l0subsys4.tester1.numPackets 65756 # Number of packets generated -system.l0subsys4.tester1.numRetries 2580 # Number of retries -system.l0subsys4.tester1.retryTicks 67683660 # Time spent waiting due to back-pressure (ticks) +system.l0subsys4.tester1.numPackets 66554 # Number of packets generated +system.l0subsys4.tester1.numRetries 2702 # Number of retries +system.l0subsys4.tester1.retryTicks 70715102 # Time spent waiting due to back-pressure (ticks) system.l0subsys4.xbar.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. system.l0subsys4.xbar.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.l0subsys4.xbar.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. @@ -526,49 +527,49 @@ system.l0subsys4.xbar.snoop_filter.tot_snoops 0 system.l0subsys4.xbar.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.l0subsys4.xbar.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.l0subsys4.xbar.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states -system.l0subsys4.xbar.trans_dist::ReadReq 85507 # Transaction distribution -system.l0subsys4.xbar.trans_dist::ReadResp 81442 # Transaction distribution -system.l0subsys4.xbar.trans_dist::ReadRespWithInvalidate 4064 # Transaction distribution -system.l0subsys4.xbar.trans_dist::WriteReq 47433 # Transaction distribution -system.l0subsys4.xbar.trans_dist::WriteResp 47433 # Transaction distribution -system.l0subsys4.xbar.trans_dist::WritebackDirty 23550 # Transaction distribution -system.l0subsys4.xbar.trans_dist::CleanEvict 56716 # Transaction distribution -system.l0subsys4.xbar.trans_dist::UpgradeReq 15634 # Transaction distribution -system.l0subsys4.xbar.trans_dist::ReadExReq 17863 # Transaction distribution -system.l0subsys4.xbar.trans_dist::ReadSharedReq 24215 # Transaction distribution -system.l0subsys4.xbar.pkt_count_system.l0subsys4.checkers0-master::system.l1subsys2.cache0.cpu_side 134368 # Packet count per connected master and slave (bytes) -system.l0subsys4.xbar.pkt_count_system.l0subsys4.checkers1-master::system.l1subsys2.cache0.cpu_side 131511 # Packet count per connected master and slave (bytes) -system.l0subsys4.xbar.pkt_count::total 265879 # Packet count per connected master and slave (bytes) -system.l0subsys4.xbar.pkt_size_system.l0subsys4.checkers0-master::system.l1subsys2.cache0.cpu_side 537472 # Cumulative packet size per connected master and slave (bytes) -system.l0subsys4.xbar.pkt_size_system.l0subsys4.checkers1-master::system.l1subsys2.cache0.cpu_side 526040 # Cumulative packet size per connected master and slave (bytes) -system.l0subsys4.xbar.pkt_size::total 1063512 # Cumulative packet size per connected master and slave (bytes) -system.l0subsys4.xbar.snoops 137978 # Total snoops (count) -system.l0subsys4.xbar.snoopTraffic 1507200 # Total snoop traffic (bytes) -system.l0subsys4.xbar.snoop_fanout::samples 273585 # Request fanout histogram +system.l0subsys4.xbar.trans_dist::ReadReq 85335 # Transaction distribution +system.l0subsys4.xbar.trans_dist::ReadResp 80858 # Transaction distribution +system.l0subsys4.xbar.trans_dist::ReadRespWithInvalidate 4477 # Transaction distribution +system.l0subsys4.xbar.trans_dist::WriteReq 47231 # Transaction distribution +system.l0subsys4.xbar.trans_dist::WriteResp 47231 # Transaction distribution +system.l0subsys4.xbar.trans_dist::WritebackDirty 23610 # Transaction distribution +system.l0subsys4.xbar.trans_dist::CleanEvict 76410 # Transaction distribution +system.l0subsys4.xbar.trans_dist::UpgradeReq 15815 # Transaction distribution +system.l0subsys4.xbar.trans_dist::ReadExReq 19797 # Transaction distribution +system.l0subsys4.xbar.trans_dist::ReadSharedReq 26031 # Transaction distribution +system.l0subsys4.xbar.pkt_count_system.l0subsys4.checkers0-master::system.l1subsys2.cache0.cpu_side 132024 # Packet count per connected master and slave (bytes) +system.l0subsys4.xbar.pkt_count_system.l0subsys4.checkers1-master::system.l1subsys2.cache0.cpu_side 133108 # Packet count per connected master and slave (bytes) +system.l0subsys4.xbar.pkt_count::total 265132 # Packet count per connected master and slave (bytes) +system.l0subsys4.xbar.pkt_size_system.l0subsys4.checkers0-master::system.l1subsys2.cache0.cpu_side 528096 # Cumulative packet size per connected master and slave (bytes) +system.l0subsys4.xbar.pkt_size_system.l0subsys4.checkers1-master::system.l1subsys2.cache0.cpu_side 532432 # Cumulative packet size per connected master and slave (bytes) +system.l0subsys4.xbar.pkt_size::total 1060528 # Cumulative packet size per connected master and slave (bytes) +system.l0subsys4.xbar.snoops 161663 # Total snoops (count) +system.l0subsys4.xbar.snoopTraffic 1511040 # Total snoop traffic (bytes) +system.l0subsys4.xbar.snoop_fanout::samples 297063 # Request fanout histogram system.l0subsys4.xbar.snoop_fanout::mean 0 # Request fanout histogram system.l0subsys4.xbar.snoop_fanout::stdev 0 # Request fanout histogram system.l0subsys4.xbar.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.l0subsys4.xbar.snoop_fanout::0 273585 100.00% 100.00% # Request fanout histogram +system.l0subsys4.xbar.snoop_fanout::0 297063 100.00% 100.00% # Request fanout histogram system.l0subsys4.xbar.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.l0subsys4.xbar.snoop_fanout::min_value 0 # Request fanout histogram system.l0subsys4.xbar.snoop_fanout::max_value 0 # Request fanout histogram -system.l0subsys4.xbar.snoop_fanout::total 273585 # Request fanout histogram -system.l0subsys4.xbar.reqLayer0.occupancy 250950593 # Layer occupancy (ticks) +system.l0subsys4.xbar.snoop_fanout::total 297063 # Request fanout histogram +system.l0subsys4.xbar.reqLayer0.occupancy 250291221 # Layer occupancy (ticks) system.l0subsys4.xbar.reqLayer0.utilization 2.5 # Layer utilization (%) -system.l0subsys4.xbar.respLayer0.occupancy 116964811 # Layer occupancy (ticks) +system.l0subsys4.xbar.respLayer0.occupancy 115013486 # Layer occupancy (ticks) system.l0subsys4.xbar.respLayer0.utilization 1.2 # Layer utilization (%) -system.l0subsys4.xbar.respLayer1.occupancy 114597175 # Layer occupancy (ticks) +system.l0subsys4.xbar.respLayer1.occupancy 114676529 # Layer occupancy (ticks) system.l0subsys4.xbar.respLayer1.utilization 1.1 # Layer utilization (%) system.l0subsys5.checkers0.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states system.l0subsys5.checkers1.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states system.l0subsys5.tester0.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states -system.l0subsys5.tester0.numPackets 67119 # Number of packets generated -system.l0subsys5.tester0.numRetries 2560 # Number of retries -system.l0subsys5.tester0.retryTicks 65403498 # Time spent waiting due to back-pressure (ticks) +system.l0subsys5.tester0.numPackets 66218 # Number of packets generated +system.l0subsys5.tester0.numRetries 2474 # Number of retries +system.l0subsys5.tester0.retryTicks 63721903 # Time spent waiting due to back-pressure (ticks) system.l0subsys5.tester1.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states -system.l0subsys5.tester1.numPackets 65308 # Number of packets generated -system.l0subsys5.tester1.numRetries 2642 # Number of retries -system.l0subsys5.tester1.retryTicks 65659220 # Time spent waiting due to back-pressure (ticks) +system.l0subsys5.tester1.numPackets 66053 # Number of packets generated +system.l0subsys5.tester1.numRetries 2552 # Number of retries +system.l0subsys5.tester1.retryTicks 62099800 # Time spent waiting due to back-pressure (ticks) system.l0subsys5.xbar.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. system.l0subsys5.xbar.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.l0subsys5.xbar.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. @@ -576,2218 +577,2233 @@ system.l0subsys5.xbar.snoop_filter.tot_snoops 0 system.l0subsys5.xbar.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.l0subsys5.xbar.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.l0subsys5.xbar.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states -system.l0subsys5.xbar.trans_dist::ReadReq 85511 # Transaction distribution -system.l0subsys5.xbar.trans_dist::ReadResp 81276 # Transaction distribution -system.l0subsys5.xbar.trans_dist::ReadRespWithInvalidate 4233 # Transaction distribution -system.l0subsys5.xbar.trans_dist::WriteReq 46916 # Transaction distribution -system.l0subsys5.xbar.trans_dist::WriteResp 46916 # Transaction distribution -system.l0subsys5.xbar.trans_dist::WritebackDirty 23832 # Transaction distribution -system.l0subsys5.xbar.trans_dist::CleanEvict 57742 # Transaction distribution -system.l0subsys5.xbar.trans_dist::UpgradeReq 16247 # Transaction distribution -system.l0subsys5.xbar.trans_dist::ReadExReq 18726 # Transaction distribution -system.l0subsys5.xbar.trans_dist::ReadSharedReq 25287 # Transaction distribution -system.l0subsys5.xbar.pkt_count_system.l0subsys5.checkers0-master::system.l1subsys2.cache1.cpu_side 134237 # Packet count per connected master and slave (bytes) -system.l0subsys5.xbar.pkt_count_system.l0subsys5.checkers1-master::system.l1subsys2.cache1.cpu_side 130615 # Packet count per connected master and slave (bytes) -system.l0subsys5.xbar.pkt_count::total 264852 # Packet count per connected master and slave (bytes) -system.l0subsys5.xbar.pkt_size_system.l0subsys5.checkers0-master::system.l1subsys2.cache1.cpu_side 536944 # Cumulative packet size per connected master and slave (bytes) -system.l0subsys5.xbar.pkt_size_system.l0subsys5.checkers1-master::system.l1subsys2.cache1.cpu_side 522456 # Cumulative packet size per connected master and slave (bytes) -system.l0subsys5.xbar.pkt_size::total 1059400 # Cumulative packet size per connected master and slave (bytes) -system.l0subsys5.xbar.snoops 141834 # Total snoops (count) -system.l0subsys5.xbar.snoopTraffic 1525248 # Total snoop traffic (bytes) -system.l0subsys5.xbar.snoop_fanout::samples 276831 # Request fanout histogram +system.l0subsys5.xbar.trans_dist::ReadReq 85318 # Transaction distribution +system.l0subsys5.xbar.trans_dist::ReadResp 80121 # Transaction distribution +system.l0subsys5.xbar.trans_dist::ReadRespWithInvalidate 5196 # Transaction distribution +system.l0subsys5.xbar.trans_dist::WriteReq 46953 # Transaction distribution +system.l0subsys5.xbar.trans_dist::WriteResp 46953 # Transaction distribution +system.l0subsys5.xbar.trans_dist::WritebackDirty 23264 # Transaction distribution +system.l0subsys5.xbar.trans_dist::CleanEvict 76398 # Transaction distribution +system.l0subsys5.xbar.trans_dist::UpgradeReq 16610 # Transaction distribution +system.l0subsys5.xbar.trans_dist::ReadExReq 21094 # Transaction distribution +system.l0subsys5.xbar.trans_dist::ReadSharedReq 27416 # Transaction distribution +system.l0subsys5.xbar.pkt_count_system.l0subsys5.checkers0-master::system.l1subsys2.cache1.cpu_side 132435 # Packet count per connected master and slave (bytes) +system.l0subsys5.xbar.pkt_count_system.l0subsys5.checkers1-master::system.l1subsys2.cache1.cpu_side 132106 # Packet count per connected master and slave (bytes) +system.l0subsys5.xbar.pkt_count::total 264541 # Packet count per connected master and slave (bytes) +system.l0subsys5.xbar.pkt_size_system.l0subsys5.checkers0-master::system.l1subsys2.cache1.cpu_side 529736 # Cumulative packet size per connected master and slave (bytes) +system.l0subsys5.xbar.pkt_size_system.l0subsys5.checkers1-master::system.l1subsys2.cache1.cpu_side 528424 # Cumulative packet size per connected master and slave (bytes) +system.l0subsys5.xbar.pkt_size::total 1058160 # Cumulative packet size per connected master and slave (bytes) +system.l0subsys5.xbar.snoops 164782 # Total snoops (count) +system.l0subsys5.xbar.snoopTraffic 1488896 # Total snoop traffic (bytes) +system.l0subsys5.xbar.snoop_fanout::samples 299602 # Request fanout histogram system.l0subsys5.xbar.snoop_fanout::mean 0 # Request fanout histogram system.l0subsys5.xbar.snoop_fanout::stdev 0 # Request fanout histogram system.l0subsys5.xbar.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.l0subsys5.xbar.snoop_fanout::0 276831 100.00% 100.00% # Request fanout histogram +system.l0subsys5.xbar.snoop_fanout::0 299602 100.00% 100.00% # Request fanout histogram system.l0subsys5.xbar.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.l0subsys5.xbar.snoop_fanout::min_value 0 # Request fanout histogram system.l0subsys5.xbar.snoop_fanout::max_value 0 # Request fanout histogram -system.l0subsys5.xbar.snoop_fanout::total 276831 # Request fanout histogram -system.l0subsys5.xbar.reqLayer0.occupancy 249400901 # Layer occupancy (ticks) +system.l0subsys5.xbar.snoop_fanout::total 299602 # Request fanout histogram +system.l0subsys5.xbar.reqLayer0.occupancy 249141230 # Layer occupancy (ticks) system.l0subsys5.xbar.reqLayer0.utilization 2.5 # Layer utilization (%) -system.l0subsys5.xbar.respLayer0.occupancy 116426882 # Layer occupancy (ticks) -system.l0subsys5.xbar.respLayer0.utilization 1.2 # Layer utilization (%) -system.l0subsys5.xbar.respLayer1.occupancy 112976792 # Layer occupancy (ticks) +system.l0subsys5.xbar.respLayer0.occupancy 114371637 # Layer occupancy (ticks) +system.l0subsys5.xbar.respLayer0.utilization 1.1 # Layer utilization (%) +system.l0subsys5.xbar.respLayer1.occupancy 114160981 # Layer occupancy (ticks) system.l0subsys5.xbar.respLayer1.utilization 1.1 # Layer utilization (%) system.l1subsys0.cache0.tags.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states -system.l1subsys0.cache0.tags.replacements 67551 # number of replacements -system.l1subsys0.cache0.tags.tagsinuse 502.758409 # Cycle average of tags in use -system.l1subsys0.cache0.tags.total_refs 31003 # Total number of references to valid blocks. -system.l1subsys0.cache0.tags.sampled_refs 68058 # Sample count of references to valid blocks. -system.l1subsys0.cache0.tags.avg_refs 0.455538 # Average number of references to valid blocks. -system.l1subsys0.cache0.tags.warmup_cycle 710764000 # Cycle when the warmup percentage was hit. -system.l1subsys0.cache0.tags.occ_blocks::l0subsys0.tester0 249.937583 # Average occupied blocks per requestor -system.l1subsys0.cache0.tags.occ_blocks::l0subsys0.tester1 252.820826 # Average occupied blocks per requestor -system.l1subsys0.cache0.tags.occ_percent::l0subsys0.tester0 0.488159 # Average percentage of cache occupancy -system.l1subsys0.cache0.tags.occ_percent::l0subsys0.tester1 0.493791 # Average percentage of cache occupancy -system.l1subsys0.cache0.tags.occ_percent::total 0.981950 # Average percentage of cache occupancy -system.l1subsys0.cache0.tags.occ_task_id_blocks::1024 507 # Occupied blocks per task id -system.l1subsys0.cache0.tags.age_task_id_blocks_1024::0 105 # Occupied blocks per task id -system.l1subsys0.cache0.tags.age_task_id_blocks_1024::1 339 # Occupied blocks per task id -system.l1subsys0.cache0.tags.age_task_id_blocks_1024::2 63 # Occupied blocks per task id -system.l1subsys0.cache0.tags.occ_task_id_percent::1024 0.990234 # Percentage of cache occupancy per task id -system.l1subsys0.cache0.tags.tag_accesses 641417 # Number of tag accesses -system.l1subsys0.cache0.tags.data_accesses 641417 # Number of data accesses +system.l1subsys0.cache0.tags.replacements 63572 # number of replacements +system.l1subsys0.cache0.tags.tagsinuse 502.721619 # Cycle average of tags in use +system.l1subsys0.cache0.tags.total_refs 28948 # Total number of references to valid blocks. +system.l1subsys0.cache0.tags.sampled_refs 64070 # Sample count of references to valid blocks. +system.l1subsys0.cache0.tags.avg_refs 0.451818 # Average number of references to valid blocks. +system.l1subsys0.cache0.tags.warmup_cycle 175326000 # Cycle when the warmup percentage was hit. +system.l1subsys0.cache0.tags.occ_blocks::l0subsys0.tester0 252.816838 # Average occupied blocks per requestor +system.l1subsys0.cache0.tags.occ_blocks::l0subsys0.tester1 249.904781 # Average occupied blocks per requestor +system.l1subsys0.cache0.tags.occ_percent::l0subsys0.tester0 0.493783 # Average percentage of cache occupancy +system.l1subsys0.cache0.tags.occ_percent::l0subsys0.tester1 0.488095 # Average percentage of cache occupancy +system.l1subsys0.cache0.tags.occ_percent::total 0.981878 # Average percentage of cache occupancy +system.l1subsys0.cache0.tags.occ_task_id_blocks::1024 498 # Occupied blocks per task id +system.l1subsys0.cache0.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id +system.l1subsys0.cache0.tags.age_task_id_blocks_1024::1 447 # Occupied blocks per task id +system.l1subsys0.cache0.tags.age_task_id_blocks_1024::2 50 # Occupied blocks per task id +system.l1subsys0.cache0.tags.occ_task_id_percent::1024 0.972656 # Percentage of cache occupancy per task id +system.l1subsys0.cache0.tags.tag_accesses 622356 # Number of tag accesses +system.l1subsys0.cache0.tags.data_accesses 622356 # Number of data accesses system.l1subsys0.cache0.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states -system.l1subsys0.cache0.ReadReq_hits::l0subsys0.tester0 9938 # number of ReadReq hits -system.l1subsys0.cache0.ReadReq_hits::l0subsys0.tester1 9361 # number of ReadReq hits -system.l1subsys0.cache0.ReadReq_hits::total 19299 # number of ReadReq hits -system.l1subsys0.cache0.WriteReq_hits::l0subsys0.tester0 1368 # number of WriteReq hits -system.l1subsys0.cache0.WriteReq_hits::l0subsys0.tester1 1240 # number of WriteReq hits -system.l1subsys0.cache0.WriteReq_hits::total 2608 # number of WriteReq hits -system.l1subsys0.cache0.demand_hits::l0subsys0.tester0 11306 # number of demand (read+write) hits -system.l1subsys0.cache0.demand_hits::l0subsys0.tester1 10601 # number of demand (read+write) hits -system.l1subsys0.cache0.demand_hits::total 21907 # number of demand (read+write) hits -system.l1subsys0.cache0.overall_hits::l0subsys0.tester0 11306 # number of overall hits -system.l1subsys0.cache0.overall_hits::l0subsys0.tester1 10601 # number of overall hits -system.l1subsys0.cache0.overall_hits::total 21907 # number of overall hits -system.l1subsys0.cache0.ReadReq_misses::l0subsys0.tester0 33357 # number of ReadReq misses -system.l1subsys0.cache0.ReadReq_misses::l0subsys0.tester1 33753 # number of ReadReq misses -system.l1subsys0.cache0.ReadReq_misses::total 67110 # number of ReadReq misses -system.l1subsys0.cache0.WriteReq_misses::l0subsys0.tester0 22761 # number of WriteReq misses -system.l1subsys0.cache0.WriteReq_misses::l0subsys0.tester1 23097 # number of WriteReq misses -system.l1subsys0.cache0.WriteReq_misses::total 45858 # number of WriteReq misses -system.l1subsys0.cache0.demand_misses::l0subsys0.tester0 56118 # number of demand (read+write) misses -system.l1subsys0.cache0.demand_misses::l0subsys0.tester1 56850 # number of demand (read+write) misses -system.l1subsys0.cache0.demand_misses::total 112968 # number of demand (read+write) misses -system.l1subsys0.cache0.overall_misses::l0subsys0.tester0 56118 # number of overall misses -system.l1subsys0.cache0.overall_misses::l0subsys0.tester1 56850 # number of overall misses -system.l1subsys0.cache0.overall_misses::total 112968 # number of overall misses -system.l1subsys0.cache0.ReadReq_miss_latency::l0subsys0.tester0 3073108727 # number of ReadReq miss cycles -system.l1subsys0.cache0.ReadReq_miss_latency::l0subsys0.tester1 3087222111 # number of ReadReq miss cycles -system.l1subsys0.cache0.ReadReq_miss_latency::total 6160330838 # number of ReadReq miss cycles -system.l1subsys0.cache0.WriteReq_miss_latency::l0subsys0.tester0 1908688077 # number of WriteReq miss cycles -system.l1subsys0.cache0.WriteReq_miss_latency::l0subsys0.tester1 1921428264 # number of WriteReq miss cycles -system.l1subsys0.cache0.WriteReq_miss_latency::total 3830116341 # number of WriteReq miss cycles -system.l1subsys0.cache0.demand_miss_latency::l0subsys0.tester0 4981796804 # number of demand (read+write) miss cycles -system.l1subsys0.cache0.demand_miss_latency::l0subsys0.tester1 5008650375 # number of demand (read+write) miss cycles -system.l1subsys0.cache0.demand_miss_latency::total 9990447179 # number of demand (read+write) miss cycles -system.l1subsys0.cache0.overall_miss_latency::l0subsys0.tester0 4981796804 # number of overall miss cycles -system.l1subsys0.cache0.overall_miss_latency::l0subsys0.tester1 5008650375 # number of overall miss cycles -system.l1subsys0.cache0.overall_miss_latency::total 9990447179 # number of overall miss cycles -system.l1subsys0.cache0.ReadReq_accesses::l0subsys0.tester0 43295 # number of ReadReq accesses(hits+misses) -system.l1subsys0.cache0.ReadReq_accesses::l0subsys0.tester1 43114 # number of ReadReq accesses(hits+misses) -system.l1subsys0.cache0.ReadReq_accesses::total 86409 # number of ReadReq accesses(hits+misses) -system.l1subsys0.cache0.WriteReq_accesses::l0subsys0.tester0 24129 # number of WriteReq accesses(hits+misses) -system.l1subsys0.cache0.WriteReq_accesses::l0subsys0.tester1 24337 # number of WriteReq accesses(hits+misses) -system.l1subsys0.cache0.WriteReq_accesses::total 48466 # number of WriteReq accesses(hits+misses) -system.l1subsys0.cache0.demand_accesses::l0subsys0.tester0 67424 # number of demand (read+write) accesses -system.l1subsys0.cache0.demand_accesses::l0subsys0.tester1 67451 # number of demand (read+write) accesses -system.l1subsys0.cache0.demand_accesses::total 134875 # number of demand (read+write) accesses -system.l1subsys0.cache0.overall_accesses::l0subsys0.tester0 67424 # number of overall (read+write) accesses -system.l1subsys0.cache0.overall_accesses::l0subsys0.tester1 67451 # number of overall (read+write) accesses -system.l1subsys0.cache0.overall_accesses::total 134875 # number of overall (read+write) accesses -system.l1subsys0.cache0.ReadReq_miss_rate::l0subsys0.tester0 0.770458 # miss rate for ReadReq accesses -system.l1subsys0.cache0.ReadReq_miss_rate::l0subsys0.tester1 0.782878 # miss rate for ReadReq accesses -system.l1subsys0.cache0.ReadReq_miss_rate::total 0.776655 # miss rate for ReadReq accesses -system.l1subsys0.cache0.WriteReq_miss_rate::l0subsys0.tester0 0.943305 # miss rate for WriteReq accesses -system.l1subsys0.cache0.WriteReq_miss_rate::l0subsys0.tester1 0.949049 # miss rate for WriteReq accesses -system.l1subsys0.cache0.WriteReq_miss_rate::total 0.946189 # miss rate for WriteReq accesses -system.l1subsys0.cache0.demand_miss_rate::l0subsys0.tester0 0.832315 # miss rate for demand accesses -system.l1subsys0.cache0.demand_miss_rate::l0subsys0.tester1 0.842834 # miss rate for demand accesses -system.l1subsys0.cache0.demand_miss_rate::total 0.837576 # miss rate for demand accesses -system.l1subsys0.cache0.overall_miss_rate::l0subsys0.tester0 0.832315 # miss rate for overall accesses -system.l1subsys0.cache0.overall_miss_rate::l0subsys0.tester1 0.842834 # miss rate for overall accesses -system.l1subsys0.cache0.overall_miss_rate::total 0.837576 # miss rate for overall accesses -system.l1subsys0.cache0.ReadReq_avg_miss_latency::l0subsys0.tester0 92127.851036 # average ReadReq miss latency -system.l1subsys0.cache0.ReadReq_avg_miss_latency::l0subsys0.tester1 91465.117501 # average ReadReq miss latency -system.l1subsys0.cache0.ReadReq_avg_miss_latency::total 91794.528952 # average ReadReq miss latency -system.l1subsys0.cache0.WriteReq_avg_miss_latency::l0subsys0.tester0 83857.830368 # average WriteReq miss latency -system.l1subsys0.cache0.WriteReq_avg_miss_latency::l0subsys0.tester1 83189.516561 # average WriteReq miss latency -system.l1subsys0.cache0.WriteReq_avg_miss_latency::total 83521.225108 # average WriteReq miss latency -system.l1subsys0.cache0.demand_avg_miss_latency::l0subsys0.tester0 88773.598560 # average overall miss latency -system.l1subsys0.cache0.demand_avg_miss_latency::l0subsys0.tester1 88102.908971 # average overall miss latency -system.l1subsys0.cache0.demand_avg_miss_latency::total 88436.080828 # average overall miss latency -system.l1subsys0.cache0.overall_avg_miss_latency::l0subsys0.tester0 88773.598560 # average overall miss latency -system.l1subsys0.cache0.overall_avg_miss_latency::l0subsys0.tester1 88102.908971 # average overall miss latency -system.l1subsys0.cache0.overall_avg_miss_latency::total 88436.080828 # average overall miss latency -system.l1subsys0.cache0.blocked_cycles::no_mshrs 271859 # number of cycles access was blocked +system.l1subsys0.cache0.ReadReq_hits::l0subsys0.tester0 9054 # number of ReadReq hits +system.l1subsys0.cache0.ReadReq_hits::l0subsys0.tester1 9218 # number of ReadReq hits +system.l1subsys0.cache0.ReadReq_hits::total 18272 # number of ReadReq hits +system.l1subsys0.cache0.WriteReq_hits::l0subsys0.tester0 1043 # number of WriteReq hits +system.l1subsys0.cache0.WriteReq_hits::l0subsys0.tester1 1065 # number of WriteReq hits +system.l1subsys0.cache0.WriteReq_hits::total 2108 # number of WriteReq hits +system.l1subsys0.cache0.demand_hits::l0subsys0.tester0 10097 # number of demand (read+write) hits +system.l1subsys0.cache0.demand_hits::l0subsys0.tester1 10283 # number of demand (read+write) hits +system.l1subsys0.cache0.demand_hits::total 20380 # number of demand (read+write) hits +system.l1subsys0.cache0.overall_hits::l0subsys0.tester0 10097 # number of overall hits +system.l1subsys0.cache0.overall_hits::l0subsys0.tester1 10283 # number of overall hits +system.l1subsys0.cache0.overall_hits::total 20380 # number of overall hits +system.l1subsys0.cache0.ReadReq_misses::l0subsys0.tester0 32756 # number of ReadReq misses +system.l1subsys0.cache0.ReadReq_misses::l0subsys0.tester1 33049 # number of ReadReq misses +system.l1subsys0.cache0.ReadReq_misses::total 65805 # number of ReadReq misses +system.l1subsys0.cache0.WriteReq_misses::l0subsys0.tester0 22181 # number of WriteReq misses +system.l1subsys0.cache0.WriteReq_misses::l0subsys0.tester1 22262 # number of WriteReq misses +system.l1subsys0.cache0.WriteReq_misses::total 44443 # number of WriteReq misses +system.l1subsys0.cache0.demand_misses::l0subsys0.tester0 54937 # number of demand (read+write) misses +system.l1subsys0.cache0.demand_misses::l0subsys0.tester1 55311 # number of demand (read+write) misses +system.l1subsys0.cache0.demand_misses::total 110248 # number of demand (read+write) misses +system.l1subsys0.cache0.overall_misses::l0subsys0.tester0 54937 # number of overall misses +system.l1subsys0.cache0.overall_misses::l0subsys0.tester1 55311 # number of overall misses +system.l1subsys0.cache0.overall_misses::total 110248 # number of overall misses +system.l1subsys0.cache0.ReadReq_miss_latency::l0subsys0.tester0 3001619678 # number of ReadReq miss cycles +system.l1subsys0.cache0.ReadReq_miss_latency::l0subsys0.tester1 2958296743 # number of ReadReq miss cycles +system.l1subsys0.cache0.ReadReq_miss_latency::total 5959916421 # number of ReadReq miss cycles +system.l1subsys0.cache0.WriteReq_miss_latency::l0subsys0.tester0 1842729426 # number of WriteReq miss cycles +system.l1subsys0.cache0.WriteReq_miss_latency::l0subsys0.tester1 1811086120 # number of WriteReq miss cycles +system.l1subsys0.cache0.WriteReq_miss_latency::total 3653815546 # number of WriteReq miss cycles +system.l1subsys0.cache0.demand_miss_latency::l0subsys0.tester0 4844349104 # number of demand (read+write) miss cycles +system.l1subsys0.cache0.demand_miss_latency::l0subsys0.tester1 4769382863 # number of demand (read+write) miss cycles +system.l1subsys0.cache0.demand_miss_latency::total 9613731967 # number of demand (read+write) miss cycles +system.l1subsys0.cache0.overall_miss_latency::l0subsys0.tester0 4844349104 # number of overall miss cycles +system.l1subsys0.cache0.overall_miss_latency::l0subsys0.tester1 4769382863 # number of overall miss cycles +system.l1subsys0.cache0.overall_miss_latency::total 9613731967 # number of overall miss cycles +system.l1subsys0.cache0.ReadReq_accesses::l0subsys0.tester0 41810 # number of ReadReq accesses(hits+misses) +system.l1subsys0.cache0.ReadReq_accesses::l0subsys0.tester1 42267 # number of ReadReq accesses(hits+misses) +system.l1subsys0.cache0.ReadReq_accesses::total 84077 # number of ReadReq accesses(hits+misses) +system.l1subsys0.cache0.WriteReq_accesses::l0subsys0.tester0 23224 # number of WriteReq accesses(hits+misses) +system.l1subsys0.cache0.WriteReq_accesses::l0subsys0.tester1 23327 # number of WriteReq accesses(hits+misses) +system.l1subsys0.cache0.WriteReq_accesses::total 46551 # number of WriteReq accesses(hits+misses) +system.l1subsys0.cache0.demand_accesses::l0subsys0.tester0 65034 # number of demand (read+write) accesses +system.l1subsys0.cache0.demand_accesses::l0subsys0.tester1 65594 # number of demand (read+write) accesses +system.l1subsys0.cache0.demand_accesses::total 130628 # number of demand (read+write) accesses +system.l1subsys0.cache0.overall_accesses::l0subsys0.tester0 65034 # number of overall (read+write) accesses +system.l1subsys0.cache0.overall_accesses::l0subsys0.tester1 65594 # number of overall (read+write) accesses +system.l1subsys0.cache0.overall_accesses::total 130628 # number of overall (read+write) accesses +system.l1subsys0.cache0.ReadReq_miss_rate::l0subsys0.tester0 0.783449 # miss rate for ReadReq accesses +system.l1subsys0.cache0.ReadReq_miss_rate::l0subsys0.tester1 0.781910 # miss rate for ReadReq accesses +system.l1subsys0.cache0.ReadReq_miss_rate::total 0.782675 # miss rate for ReadReq accesses +system.l1subsys0.cache0.WriteReq_miss_rate::l0subsys0.tester0 0.955090 # miss rate for WriteReq accesses +system.l1subsys0.cache0.WriteReq_miss_rate::l0subsys0.tester1 0.954345 # miss rate for WriteReq accesses +system.l1subsys0.cache0.WriteReq_miss_rate::total 0.954716 # miss rate for WriteReq accesses +system.l1subsys0.cache0.demand_miss_rate::l0subsys0.tester0 0.844743 # miss rate for demand accesses +system.l1subsys0.cache0.demand_miss_rate::l0subsys0.tester1 0.843233 # miss rate for demand accesses +system.l1subsys0.cache0.demand_miss_rate::total 0.843984 # miss rate for demand accesses +system.l1subsys0.cache0.overall_miss_rate::l0subsys0.tester0 0.844743 # miss rate for overall accesses +system.l1subsys0.cache0.overall_miss_rate::l0subsys0.tester1 0.843233 # miss rate for overall accesses +system.l1subsys0.cache0.overall_miss_rate::total 0.843984 # miss rate for overall accesses +system.l1subsys0.cache0.ReadReq_avg_miss_latency::l0subsys0.tester0 91635.721028 # average ReadReq miss latency +system.l1subsys0.cache0.ReadReq_avg_miss_latency::l0subsys0.tester1 89512.443432 # average ReadReq miss latency +system.l1subsys0.cache0.ReadReq_avg_miss_latency::total 90569.355231 # average ReadReq miss latency +system.l1subsys0.cache0.WriteReq_avg_miss_latency::l0subsys0.tester0 83076.931879 # average WriteReq miss latency +system.l1subsys0.cache0.WriteReq_avg_miss_latency::l0subsys0.tester1 81353.253077 # average WriteReq miss latency +system.l1subsys0.cache0.WriteReq_avg_miss_latency::total 82213.521724 # average WriteReq miss latency +system.l1subsys0.cache0.demand_avg_miss_latency::l0subsys0.tester0 88180.080893 # average overall miss latency +system.l1subsys0.cache0.demand_avg_miss_latency::l0subsys0.tester1 86228.469256 # average overall miss latency +system.l1subsys0.cache0.demand_avg_miss_latency::total 87200.964798 # average overall miss latency +system.l1subsys0.cache0.overall_avg_miss_latency::l0subsys0.tester0 88180.080893 # average overall miss latency +system.l1subsys0.cache0.overall_avg_miss_latency::l0subsys0.tester1 86228.469256 # average overall miss latency +system.l1subsys0.cache0.overall_avg_miss_latency::total 87200.964798 # average overall miss latency +system.l1subsys0.cache0.blocked_cycles::no_mshrs 255047 # number of cycles access was blocked system.l1subsys0.cache0.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l1subsys0.cache0.blocked::no_mshrs 8472 # number of cycles access was blocked +system.l1subsys0.cache0.blocked::no_mshrs 7903 # number of cycles access was blocked system.l1subsys0.cache0.blocked::no_targets 0 # number of cycles access was blocked -system.l1subsys0.cache0.avg_blocked_cycles::no_mshrs 32.089117 # average number of cycles each access was blocked +system.l1subsys0.cache0.avg_blocked_cycles::no_mshrs 32.272175 # average number of cycles each access was blocked system.l1subsys0.cache0.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.l1subsys0.cache0.writebacks::writebacks 24312 # number of writebacks -system.l1subsys0.cache0.writebacks::total 24312 # number of writebacks -system.l1subsys0.cache0.ReadReq_mshr_hits::l0subsys0.tester0 1310 # number of ReadReq MSHR hits -system.l1subsys0.cache0.ReadReq_mshr_hits::l0subsys0.tester1 1307 # number of ReadReq MSHR hits -system.l1subsys0.cache0.ReadReq_mshr_hits::total 2617 # number of ReadReq MSHR hits -system.l1subsys0.cache0.WriteReq_mshr_hits::l0subsys0.tester0 720 # number of WriteReq MSHR hits -system.l1subsys0.cache0.WriteReq_mshr_hits::l0subsys0.tester1 761 # number of WriteReq MSHR hits -system.l1subsys0.cache0.WriteReq_mshr_hits::total 1481 # number of WriteReq MSHR hits -system.l1subsys0.cache0.demand_mshr_hits::l0subsys0.tester0 2030 # number of demand (read+write) MSHR hits -system.l1subsys0.cache0.demand_mshr_hits::l0subsys0.tester1 2068 # number of demand (read+write) MSHR hits -system.l1subsys0.cache0.demand_mshr_hits::total 4098 # number of demand (read+write) MSHR hits -system.l1subsys0.cache0.overall_mshr_hits::l0subsys0.tester0 2030 # number of overall MSHR hits -system.l1subsys0.cache0.overall_mshr_hits::l0subsys0.tester1 2068 # number of overall MSHR hits -system.l1subsys0.cache0.overall_mshr_hits::total 4098 # number of overall MSHR hits -system.l1subsys0.cache0.ReadReq_mshr_misses::l0subsys0.tester0 32047 # number of ReadReq MSHR misses -system.l1subsys0.cache0.ReadReq_mshr_misses::l0subsys0.tester1 32446 # number of ReadReq MSHR misses -system.l1subsys0.cache0.ReadReq_mshr_misses::total 64493 # number of ReadReq MSHR misses -system.l1subsys0.cache0.WriteReq_mshr_misses::l0subsys0.tester0 22041 # number of WriteReq MSHR misses -system.l1subsys0.cache0.WriteReq_mshr_misses::l0subsys0.tester1 22336 # number of WriteReq MSHR misses -system.l1subsys0.cache0.WriteReq_mshr_misses::total 44377 # number of WriteReq MSHR misses -system.l1subsys0.cache0.demand_mshr_misses::l0subsys0.tester0 54088 # number of demand (read+write) MSHR misses -system.l1subsys0.cache0.demand_mshr_misses::l0subsys0.tester1 54782 # number of demand (read+write) MSHR misses -system.l1subsys0.cache0.demand_mshr_misses::total 108870 # number of demand (read+write) MSHR misses -system.l1subsys0.cache0.overall_mshr_misses::l0subsys0.tester0 54088 # number of overall MSHR misses -system.l1subsys0.cache0.overall_mshr_misses::l0subsys0.tester1 54782 # number of overall MSHR misses -system.l1subsys0.cache0.overall_mshr_misses::total 108870 # number of overall MSHR misses -system.l1subsys0.cache0.ReadReq_mshr_miss_latency::l0subsys0.tester0 3011177002 # number of ReadReq MSHR miss cycles -system.l1subsys0.cache0.ReadReq_mshr_miss_latency::l0subsys0.tester1 3025731013 # number of ReadReq MSHR miss cycles -system.l1subsys0.cache0.ReadReq_mshr_miss_latency::total 6036908015 # number of ReadReq MSHR miss cycles -system.l1subsys0.cache0.WriteReq_mshr_miss_latency::l0subsys0.tester0 1877689400 # number of WriteReq MSHR miss cycles -system.l1subsys0.cache0.WriteReq_mshr_miss_latency::l0subsys0.tester1 1889694563 # number of WriteReq MSHR miss cycles -system.l1subsys0.cache0.WriteReq_mshr_miss_latency::total 3767383963 # number of WriteReq MSHR miss cycles -system.l1subsys0.cache0.demand_mshr_miss_latency::l0subsys0.tester0 4888866402 # number of demand (read+write) MSHR miss cycles -system.l1subsys0.cache0.demand_mshr_miss_latency::l0subsys0.tester1 4915425576 # number of demand (read+write) MSHR miss cycles -system.l1subsys0.cache0.demand_mshr_miss_latency::total 9804291978 # number of demand (read+write) MSHR miss cycles -system.l1subsys0.cache0.overall_mshr_miss_latency::l0subsys0.tester0 4888866402 # number of overall MSHR miss cycles -system.l1subsys0.cache0.overall_mshr_miss_latency::l0subsys0.tester1 4915425576 # number of overall MSHR miss cycles -system.l1subsys0.cache0.overall_mshr_miss_latency::total 9804291978 # number of overall MSHR miss cycles -system.l1subsys0.cache0.ReadReq_mshr_miss_rate::l0subsys0.tester0 0.740201 # mshr miss rate for ReadReq accesses -system.l1subsys0.cache0.ReadReq_mshr_miss_rate::l0subsys0.tester1 0.752563 # mshr miss rate for ReadReq accesses -system.l1subsys0.cache0.ReadReq_mshr_miss_rate::total 0.746369 # mshr miss rate for ReadReq accesses -system.l1subsys0.cache0.WriteReq_mshr_miss_rate::l0subsys0.tester0 0.913465 # mshr miss rate for WriteReq accesses -system.l1subsys0.cache0.WriteReq_mshr_miss_rate::l0subsys0.tester1 0.917780 # mshr miss rate for WriteReq accesses -system.l1subsys0.cache0.WriteReq_mshr_miss_rate::total 0.915632 # mshr miss rate for WriteReq accesses -system.l1subsys0.cache0.demand_mshr_miss_rate::l0subsys0.tester0 0.802207 # mshr miss rate for demand accesses -system.l1subsys0.cache0.demand_mshr_miss_rate::l0subsys0.tester1 0.812175 # mshr miss rate for demand accesses -system.l1subsys0.cache0.demand_mshr_miss_rate::total 0.807192 # mshr miss rate for demand accesses -system.l1subsys0.cache0.overall_mshr_miss_rate::l0subsys0.tester0 0.802207 # mshr miss rate for overall accesses -system.l1subsys0.cache0.overall_mshr_miss_rate::l0subsys0.tester1 0.812175 # mshr miss rate for overall accesses -system.l1subsys0.cache0.overall_mshr_miss_rate::total 0.807192 # mshr miss rate for overall accesses -system.l1subsys0.cache0.ReadReq_avg_mshr_miss_latency::l0subsys0.tester0 93961.275689 # average ReadReq mshr miss latency -system.l1subsys0.cache0.ReadReq_avg_mshr_miss_latency::l0subsys0.tester1 93254.361493 # average ReadReq mshr miss latency -system.l1subsys0.cache0.ReadReq_avg_mshr_miss_latency::total 93605.631852 # average ReadReq mshr miss latency -system.l1subsys0.cache0.WriteReq_avg_mshr_miss_latency::l0subsys0.tester0 85190.753596 # average WriteReq mshr miss latency -system.l1subsys0.cache0.WriteReq_avg_mshr_miss_latency::l0subsys0.tester1 84603.087527 # average WriteReq mshr miss latency -system.l1subsys0.cache0.WriteReq_avg_mshr_miss_latency::total 84894.967280 # average WriteReq mshr miss latency -system.l1subsys0.cache0.demand_avg_mshr_miss_latency::l0subsys0.tester0 90387.265234 # average overall mshr miss latency -system.l1subsys0.cache0.demand_avg_mshr_miss_latency::l0subsys0.tester1 89727.019386 # average overall mshr miss latency -system.l1subsys0.cache0.demand_avg_mshr_miss_latency::total 90055.037917 # average overall mshr miss latency -system.l1subsys0.cache0.overall_avg_mshr_miss_latency::l0subsys0.tester0 90387.265234 # average overall mshr miss latency -system.l1subsys0.cache0.overall_avg_mshr_miss_latency::l0subsys0.tester1 89727.019386 # average overall mshr miss latency -system.l1subsys0.cache0.overall_avg_mshr_miss_latency::total 90055.037917 # average overall mshr miss latency +system.l1subsys0.cache0.writebacks::writebacks 22887 # number of writebacks +system.l1subsys0.cache0.writebacks::total 22887 # number of writebacks +system.l1subsys0.cache0.ReadReq_mshr_hits::l0subsys0.tester0 1216 # number of ReadReq MSHR hits +system.l1subsys0.cache0.ReadReq_mshr_hits::l0subsys0.tester1 1243 # number of ReadReq MSHR hits +system.l1subsys0.cache0.ReadReq_mshr_hits::total 2459 # number of ReadReq MSHR hits +system.l1subsys0.cache0.WriteReq_mshr_hits::l0subsys0.tester0 661 # number of WriteReq MSHR hits +system.l1subsys0.cache0.WriteReq_mshr_hits::l0subsys0.tester1 689 # number of WriteReq MSHR hits +system.l1subsys0.cache0.WriteReq_mshr_hits::total 1350 # number of WriteReq MSHR hits +system.l1subsys0.cache0.demand_mshr_hits::l0subsys0.tester0 1877 # number of demand (read+write) MSHR hits +system.l1subsys0.cache0.demand_mshr_hits::l0subsys0.tester1 1932 # number of demand (read+write) MSHR hits +system.l1subsys0.cache0.demand_mshr_hits::total 3809 # number of demand (read+write) MSHR hits +system.l1subsys0.cache0.overall_mshr_hits::l0subsys0.tester0 1877 # number of overall MSHR hits +system.l1subsys0.cache0.overall_mshr_hits::l0subsys0.tester1 1932 # number of overall MSHR hits +system.l1subsys0.cache0.overall_mshr_hits::total 3809 # number of overall MSHR hits +system.l1subsys0.cache0.ReadReq_mshr_misses::l0subsys0.tester0 31540 # number of ReadReq MSHR misses +system.l1subsys0.cache0.ReadReq_mshr_misses::l0subsys0.tester1 31806 # number of ReadReq MSHR misses +system.l1subsys0.cache0.ReadReq_mshr_misses::total 63346 # number of ReadReq MSHR misses +system.l1subsys0.cache0.WriteReq_mshr_misses::l0subsys0.tester0 21520 # number of WriteReq MSHR misses +system.l1subsys0.cache0.WriteReq_mshr_misses::l0subsys0.tester1 21573 # number of WriteReq MSHR misses +system.l1subsys0.cache0.WriteReq_mshr_misses::total 43093 # number of WriteReq MSHR misses +system.l1subsys0.cache0.demand_mshr_misses::l0subsys0.tester0 53060 # number of demand (read+write) MSHR misses +system.l1subsys0.cache0.demand_mshr_misses::l0subsys0.tester1 53379 # number of demand (read+write) MSHR misses +system.l1subsys0.cache0.demand_mshr_misses::total 106439 # number of demand (read+write) MSHR misses +system.l1subsys0.cache0.overall_mshr_misses::l0subsys0.tester0 53060 # number of overall MSHR misses +system.l1subsys0.cache0.overall_mshr_misses::l0subsys0.tester1 53379 # number of overall MSHR misses +system.l1subsys0.cache0.overall_mshr_misses::total 106439 # number of overall MSHR misses +system.l1subsys0.cache0.ReadReq_mshr_miss_latency::l0subsys0.tester0 2943016198 # number of ReadReq MSHR miss cycles +system.l1subsys0.cache0.ReadReq_mshr_miss_latency::l0subsys0.tester1 2898664159 # number of ReadReq MSHR miss cycles +system.l1subsys0.cache0.ReadReq_mshr_miss_latency::total 5841680357 # number of ReadReq MSHR miss cycles +system.l1subsys0.cache0.WriteReq_mshr_miss_latency::l0subsys0.tester0 1812017394 # number of WriteReq MSHR miss cycles +system.l1subsys0.cache0.WriteReq_mshr_miss_latency::l0subsys0.tester1 1780656760 # number of WriteReq MSHR miss cycles +system.l1subsys0.cache0.WriteReq_mshr_miss_latency::total 3592674154 # number of WriteReq MSHR miss cycles +system.l1subsys0.cache0.demand_mshr_miss_latency::l0subsys0.tester0 4755033592 # number of demand (read+write) MSHR miss cycles +system.l1subsys0.cache0.demand_mshr_miss_latency::l0subsys0.tester1 4679320919 # number of demand (read+write) MSHR miss cycles +system.l1subsys0.cache0.demand_mshr_miss_latency::total 9434354511 # number of demand (read+write) MSHR miss cycles +system.l1subsys0.cache0.overall_mshr_miss_latency::l0subsys0.tester0 4755033592 # number of overall MSHR miss cycles +system.l1subsys0.cache0.overall_mshr_miss_latency::l0subsys0.tester1 4679320919 # number of overall MSHR miss cycles +system.l1subsys0.cache0.overall_mshr_miss_latency::total 9434354511 # number of overall MSHR miss cycles +system.l1subsys0.cache0.ReadReq_mshr_miss_rate::l0subsys0.tester0 0.754365 # mshr miss rate for ReadReq accesses +system.l1subsys0.cache0.ReadReq_mshr_miss_rate::l0subsys0.tester1 0.752502 # mshr miss rate for ReadReq accesses +system.l1subsys0.cache0.ReadReq_mshr_miss_rate::total 0.753428 # mshr miss rate for ReadReq accesses +system.l1subsys0.cache0.WriteReq_mshr_miss_rate::l0subsys0.tester0 0.926628 # mshr miss rate for WriteReq accesses +system.l1subsys0.cache0.WriteReq_mshr_miss_rate::l0subsys0.tester1 0.924808 # mshr miss rate for WriteReq accesses +system.l1subsys0.cache0.WriteReq_mshr_miss_rate::total 0.925716 # mshr miss rate for WriteReq accesses +system.l1subsys0.cache0.demand_mshr_miss_rate::l0subsys0.tester0 0.815881 # mshr miss rate for demand accesses +system.l1subsys0.cache0.demand_mshr_miss_rate::l0subsys0.tester1 0.813779 # mshr miss rate for demand accesses +system.l1subsys0.cache0.demand_mshr_miss_rate::total 0.814825 # mshr miss rate for demand accesses +system.l1subsys0.cache0.overall_mshr_miss_rate::l0subsys0.tester0 0.815881 # mshr miss rate for overall accesses +system.l1subsys0.cache0.overall_mshr_miss_rate::l0subsys0.tester1 0.813779 # mshr miss rate for overall accesses +system.l1subsys0.cache0.overall_mshr_miss_rate::total 0.814825 # mshr miss rate for overall accesses +system.l1subsys0.cache0.ReadReq_avg_mshr_miss_latency::l0subsys0.tester0 93310.596005 # average ReadReq mshr miss latency +system.l1subsys0.cache0.ReadReq_avg_mshr_miss_latency::l0subsys0.tester1 91135.765547 # average ReadReq mshr miss latency +system.l1subsys0.cache0.ReadReq_avg_mshr_miss_latency::total 92218.614546 # average ReadReq mshr miss latency +system.l1subsys0.cache0.WriteReq_avg_mshr_miss_latency::l0subsys0.tester0 84201.551766 # average WriteReq mshr miss latency +system.l1subsys0.cache0.WriteReq_avg_mshr_miss_latency::l0subsys0.tester1 82540.989199 # average WriteReq mshr miss latency +system.l1subsys0.cache0.WriteReq_avg_mshr_miss_latency::total 83370.249321 # average WriteReq mshr miss latency +system.l1subsys0.cache0.demand_avg_mshr_miss_latency::l0subsys0.tester0 89616.162684 # average overall mshr miss latency +system.l1subsys0.cache0.demand_avg_mshr_miss_latency::l0subsys0.tester1 87662.206467 # average overall mshr miss latency +system.l1subsys0.cache0.demand_avg_mshr_miss_latency::total 88636.256551 # average overall mshr miss latency +system.l1subsys0.cache0.overall_avg_mshr_miss_latency::l0subsys0.tester0 89616.162684 # average overall mshr miss latency +system.l1subsys0.cache0.overall_avg_mshr_miss_latency::l0subsys0.tester1 87662.206467 # average overall mshr miss latency +system.l1subsys0.cache0.overall_avg_mshr_miss_latency::total 88636.256551 # average overall mshr miss latency system.l1subsys0.cache1.tags.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states -system.l1subsys0.cache1.tags.replacements 68848 # number of replacements -system.l1subsys0.cache1.tags.tagsinuse 504.594743 # Cycle average of tags in use -system.l1subsys0.cache1.tags.total_refs 31105 # Total number of references to valid blocks. -system.l1subsys0.cache1.tags.sampled_refs 69348 # Sample count of references to valid blocks. -system.l1subsys0.cache1.tags.avg_refs 0.448535 # Average number of references to valid blocks. -system.l1subsys0.cache1.tags.warmup_cycle 229896000 # Cycle when the warmup percentage was hit. -system.l1subsys0.cache1.tags.occ_blocks::l0subsys1.tester0 242.878191 # Average occupied blocks per requestor -system.l1subsys0.cache1.tags.occ_blocks::l0subsys1.tester1 261.716552 # Average occupied blocks per requestor -system.l1subsys0.cache1.tags.occ_percent::l0subsys1.tester0 0.474371 # Average percentage of cache occupancy -system.l1subsys0.cache1.tags.occ_percent::l0subsys1.tester1 0.511165 # Average percentage of cache occupancy -system.l1subsys0.cache1.tags.occ_percent::total 0.985537 # Average percentage of cache occupancy -system.l1subsys0.cache1.tags.occ_task_id_blocks::1024 500 # Occupied blocks per task id -system.l1subsys0.cache1.tags.age_task_id_blocks_1024::0 92 # Occupied blocks per task id -system.l1subsys0.cache1.tags.age_task_id_blocks_1024::1 318 # Occupied blocks per task id -system.l1subsys0.cache1.tags.age_task_id_blocks_1024::2 90 # Occupied blocks per task id -system.l1subsys0.cache1.tags.occ_task_id_percent::1024 0.976562 # Percentage of cache occupancy per task id -system.l1subsys0.cache1.tags.tag_accesses 633805 # Number of tag accesses -system.l1subsys0.cache1.tags.data_accesses 633805 # Number of data accesses +system.l1subsys0.cache1.tags.replacements 65828 # number of replacements +system.l1subsys0.cache1.tags.tagsinuse 503.967314 # Cycle average of tags in use +system.l1subsys0.cache1.tags.total_refs 28277 # Total number of references to valid blocks. +system.l1subsys0.cache1.tags.sampled_refs 66340 # Sample count of references to valid blocks. +system.l1subsys0.cache1.tags.avg_refs 0.426244 # Average number of references to valid blocks. +system.l1subsys0.cache1.tags.warmup_cycle 396891000 # Cycle when the warmup percentage was hit. +system.l1subsys0.cache1.tags.occ_blocks::l0subsys1.tester0 249.180331 # Average occupied blocks per requestor +system.l1subsys0.cache1.tags.occ_blocks::l0subsys1.tester1 254.786982 # Average occupied blocks per requestor +system.l1subsys0.cache1.tags.occ_percent::l0subsys1.tester0 0.486680 # Average percentage of cache occupancy +system.l1subsys0.cache1.tags.occ_percent::l0subsys1.tester1 0.497631 # Average percentage of cache occupancy +system.l1subsys0.cache1.tags.occ_percent::total 0.984311 # Average percentage of cache occupancy +system.l1subsys0.cache1.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.l1subsys0.cache1.tags.age_task_id_blocks_1024::0 116 # Occupied blocks per task id +system.l1subsys0.cache1.tags.age_task_id_blocks_1024::1 337 # Occupied blocks per task id +system.l1subsys0.cache1.tags.age_task_id_blocks_1024::2 59 # Occupied blocks per task id +system.l1subsys0.cache1.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.l1subsys0.cache1.tags.tag_accesses 626837 # Number of tag accesses +system.l1subsys0.cache1.tags.data_accesses 626837 # Number of data accesses system.l1subsys0.cache1.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states -system.l1subsys0.cache1.ReadReq_hits::l0subsys1.tester0 9817 # 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number of overall MSHR misses -system.l1subsys0.cache1.ReadReq_mshr_miss_latency::l0subsys1.tester0 2946301712 # number of ReadReq MSHR miss cycles -system.l1subsys0.cache1.ReadReq_mshr_miss_latency::l0subsys1.tester1 3181085510 # number of ReadReq MSHR miss cycles -system.l1subsys0.cache1.ReadReq_mshr_miss_latency::total 6127387222 # number of ReadReq MSHR miss cycles -system.l1subsys0.cache1.WriteReq_mshr_miss_latency::l0subsys1.tester0 1810955934 # number of WriteReq MSHR miss cycles -system.l1subsys0.cache1.WriteReq_mshr_miss_latency::l0subsys1.tester1 1924620571 # number of WriteReq MSHR miss cycles -system.l1subsys0.cache1.WriteReq_mshr_miss_latency::total 3735576505 # number of WriteReq MSHR miss cycles -system.l1subsys0.cache1.demand_mshr_miss_latency::l0subsys1.tester0 4757257646 # number of demand (read+write) MSHR miss cycles -system.l1subsys0.cache1.demand_mshr_miss_latency::l0subsys1.tester1 5105706081 # number of demand (read+write) MSHR miss cycles -system.l1subsys0.cache1.demand_mshr_miss_latency::total 9862963727 # number of demand (read+write) MSHR miss cycles -system.l1subsys0.cache1.overall_mshr_miss_latency::l0subsys1.tester0 4757257646 # number of overall MSHR miss cycles -system.l1subsys0.cache1.overall_mshr_miss_latency::l0subsys1.tester1 5105706081 # number of overall MSHR miss cycles -system.l1subsys0.cache1.overall_mshr_miss_latency::total 9862963727 # number of overall MSHR miss cycles -system.l1subsys0.cache1.ReadReq_mshr_miss_rate::l0subsys1.tester0 0.738181 # mshr miss rate for ReadReq accesses -system.l1subsys0.cache1.ReadReq_mshr_miss_rate::l0subsys1.tester1 0.748320 # mshr miss rate for ReadReq accesses -system.l1subsys0.cache1.ReadReq_mshr_miss_rate::total 0.743358 # mshr miss rate for ReadReq accesses -system.l1subsys0.cache1.WriteReq_mshr_miss_rate::l0subsys1.tester0 0.912631 # mshr miss rate for WriteReq accesses -system.l1subsys0.cache1.WriteReq_mshr_miss_rate::l0subsys1.tester1 0.908952 # mshr miss rate for WriteReq accesses -system.l1subsys0.cache1.WriteReq_mshr_miss_rate::total 0.910747 # mshr miss rate for WriteReq accesses -system.l1subsys0.cache1.demand_mshr_miss_rate::l0subsys1.tester0 0.800031 # mshr miss rate for demand accesses -system.l1subsys0.cache1.demand_mshr_miss_rate::l0subsys1.tester1 0.805512 # mshr miss rate for demand accesses -system.l1subsys0.cache1.demand_mshr_miss_rate::total 0.802833 # mshr miss rate for demand accesses -system.l1subsys0.cache1.overall_mshr_miss_rate::l0subsys1.tester0 0.800031 # mshr miss rate for overall accesses -system.l1subsys0.cache1.overall_mshr_miss_rate::l0subsys1.tester1 0.805512 # mshr miss rate for overall accesses -system.l1subsys0.cache1.overall_mshr_miss_rate::total 0.802833 # mshr miss rate for overall accesses -system.l1subsys0.cache1.ReadReq_avg_mshr_miss_latency::l0subsys1.tester0 94870.611540 # average ReadReq mshr miss latency -system.l1subsys0.cache1.ReadReq_avg_mshr_miss_latency::l0subsys1.tester1 96830.802082 # average ReadReq mshr miss latency -system.l1subsys0.cache1.ReadReq_avg_mshr_miss_latency::total 95878.250329 # average ReadReq mshr miss latency -system.l1subsys0.cache1.WriteReq_avg_mshr_miss_latency::l0subsys1.tester0 85867.991181 # average WriteReq mshr miss latency -system.l1subsys0.cache1.WriteReq_avg_mshr_miss_latency::l0subsys1.tester1 87232.949780 # average WriteReq mshr miss latency -system.l1subsys0.cache1.WriteReq_avg_mshr_miss_latency::total 86565.858805 # average WriteReq mshr miss latency -system.l1subsys0.cache1.demand_avg_mshr_miss_latency::l0subsys1.tester0 91229.579373 # average overall mshr miss latency -system.l1subsys0.cache1.demand_avg_mshr_miss_latency::l0subsys1.tester1 92974.707839 # average overall mshr miss latency -system.l1subsys0.cache1.demand_avg_mshr_miss_latency::total 92124.711398 # average overall mshr miss latency -system.l1subsys0.cache1.overall_avg_mshr_miss_latency::l0subsys1.tester0 91229.579373 # average overall mshr miss latency -system.l1subsys0.cache1.overall_avg_mshr_miss_latency::l0subsys1.tester1 92974.707839 # average overall mshr miss latency -system.l1subsys0.cache1.overall_avg_mshr_miss_latency::total 92124.711398 # average overall mshr miss latency -system.l1subsys0.xbar.snoop_filter.tot_requests 354135 # Total number of requests made to the snoop filter. -system.l1subsys0.xbar.snoop_filter.hit_single_requests 168078 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.l1subsys0.xbar.snoop_filter.hit_multi_requests 8556 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.l1subsys0.xbar.snoop_filter.tot_snoops 114062 # Total number of snoops made to the snoop filter. -system.l1subsys0.xbar.snoop_filter.hit_single_snoops 98725 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.l1subsys0.xbar.snoop_filter.hit_multi_snoops 15337 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.l1subsys0.cache1.writebacks::writebacks 23700 # number of writebacks +system.l1subsys0.cache1.writebacks::total 23700 # number of writebacks +system.l1subsys0.cache1.ReadReq_mshr_hits::l0subsys1.tester0 1375 # number of ReadReq MSHR hits +system.l1subsys0.cache1.ReadReq_mshr_hits::l0subsys1.tester1 1361 # number of ReadReq MSHR hits +system.l1subsys0.cache1.ReadReq_mshr_hits::total 2736 # number of ReadReq MSHR hits +system.l1subsys0.cache1.WriteReq_mshr_hits::l0subsys1.tester0 770 # number of WriteReq MSHR hits +system.l1subsys0.cache1.WriteReq_mshr_hits::l0subsys1.tester1 782 # number of WriteReq MSHR hits +system.l1subsys0.cache1.WriteReq_mshr_hits::total 1552 # number of WriteReq MSHR hits +system.l1subsys0.cache1.demand_mshr_hits::l0subsys1.tester0 2145 # number of demand (read+write) MSHR hits +system.l1subsys0.cache1.demand_mshr_hits::l0subsys1.tester1 2143 # number of demand (read+write) MSHR hits +system.l1subsys0.cache1.demand_mshr_hits::total 4288 # number of demand (read+write) MSHR hits +system.l1subsys0.cache1.overall_mshr_hits::l0subsys1.tester0 2145 # number of overall MSHR hits +system.l1subsys0.cache1.overall_mshr_hits::l0subsys1.tester1 2143 # number of overall MSHR hits +system.l1subsys0.cache1.overall_mshr_hits::total 4288 # number of overall MSHR hits +system.l1subsys0.cache1.ReadReq_mshr_misses::l0subsys1.tester0 31614 # number of ReadReq MSHR misses +system.l1subsys0.cache1.ReadReq_mshr_misses::l0subsys1.tester1 32420 # number of ReadReq MSHR misses +system.l1subsys0.cache1.ReadReq_mshr_misses::total 64034 # number of ReadReq MSHR misses +system.l1subsys0.cache1.WriteReq_mshr_misses::l0subsys1.tester0 21286 # number of WriteReq MSHR misses +system.l1subsys0.cache1.WriteReq_mshr_misses::l0subsys1.tester1 22012 # number of WriteReq MSHR misses +system.l1subsys0.cache1.WriteReq_mshr_misses::total 43298 # number of WriteReq MSHR misses +system.l1subsys0.cache1.demand_mshr_misses::l0subsys1.tester0 52900 # number of demand (read+write) MSHR misses +system.l1subsys0.cache1.demand_mshr_misses::l0subsys1.tester1 54432 # number of demand (read+write) MSHR misses +system.l1subsys0.cache1.demand_mshr_misses::total 107332 # number of demand (read+write) MSHR misses +system.l1subsys0.cache1.overall_mshr_misses::l0subsys1.tester0 52900 # number of overall MSHR misses +system.l1subsys0.cache1.overall_mshr_misses::l0subsys1.tester1 54432 # number of overall MSHR misses +system.l1subsys0.cache1.overall_mshr_misses::total 107332 # number of overall MSHR misses +system.l1subsys0.cache1.ReadReq_mshr_miss_latency::l0subsys1.tester0 2931797311 # number of ReadReq MSHR miss cycles +system.l1subsys0.cache1.ReadReq_mshr_miss_latency::l0subsys1.tester1 3008653517 # number of ReadReq MSHR miss cycles +system.l1subsys0.cache1.ReadReq_mshr_miss_latency::total 5940450828 # number of ReadReq MSHR miss cycles +system.l1subsys0.cache1.WriteReq_mshr_miss_latency::l0subsys1.tester0 1826715134 # number of WriteReq MSHR miss cycles +system.l1subsys0.cache1.WriteReq_mshr_miss_latency::l0subsys1.tester1 1854734052 # number of WriteReq MSHR miss cycles +system.l1subsys0.cache1.WriteReq_mshr_miss_latency::total 3681449186 # number of WriteReq MSHR miss cycles +system.l1subsys0.cache1.demand_mshr_miss_latency::l0subsys1.tester0 4758512445 # number of demand (read+write) MSHR miss cycles +system.l1subsys0.cache1.demand_mshr_miss_latency::l0subsys1.tester1 4863387569 # number of demand (read+write) MSHR miss cycles +system.l1subsys0.cache1.demand_mshr_miss_latency::total 9621900014 # number of demand (read+write) MSHR miss cycles +system.l1subsys0.cache1.overall_mshr_miss_latency::l0subsys1.tester0 4758512445 # number of overall MSHR miss cycles +system.l1subsys0.cache1.overall_mshr_miss_latency::l0subsys1.tester1 4863387569 # number of overall MSHR miss cycles +system.l1subsys0.cache1.overall_mshr_miss_latency::total 9621900014 # number of overall MSHR miss cycles +system.l1subsys0.cache1.ReadReq_mshr_miss_rate::l0subsys1.tester0 0.767610 # mshr miss rate for ReadReq accesses +system.l1subsys0.cache1.ReadReq_mshr_miss_rate::l0subsys1.tester1 0.749180 # mshr miss rate for ReadReq accesses +system.l1subsys0.cache1.ReadReq_mshr_miss_rate::total 0.758167 # mshr miss rate for ReadReq accesses +system.l1subsys0.cache1.WriteReq_mshr_miss_rate::l0subsys1.tester0 0.923511 # mshr miss rate for WriteReq accesses +system.l1subsys0.cache1.WriteReq_mshr_miss_rate::l0subsys1.tester1 0.918583 # mshr miss rate for WriteReq accesses +system.l1subsys0.cache1.WriteReq_mshr_miss_rate::total 0.920999 # mshr miss rate for WriteReq accesses +system.l1subsys0.cache1.demand_mshr_miss_rate::l0subsys1.tester0 0.823551 # mshr miss rate for demand accesses +system.l1subsys0.cache1.demand_mshr_miss_rate::l0subsys1.tester1 0.809554 # mshr miss rate for demand accesses +system.l1subsys0.cache1.demand_mshr_miss_rate::total 0.816393 # mshr miss rate for demand accesses +system.l1subsys0.cache1.overall_mshr_miss_rate::l0subsys1.tester0 0.823551 # mshr miss rate for overall accesses +system.l1subsys0.cache1.overall_mshr_miss_rate::l0subsys1.tester1 0.809554 # mshr miss rate for overall accesses +system.l1subsys0.cache1.overall_mshr_miss_rate::total 0.816393 # mshr miss rate for overall accesses +system.l1subsys0.cache1.ReadReq_avg_mshr_miss_latency::l0subsys1.tester0 92737.309768 # average ReadReq mshr miss latency +system.l1subsys0.cache1.ReadReq_avg_mshr_miss_latency::l0subsys1.tester1 92802.391024 # average ReadReq mshr miss latency +system.l1subsys0.cache1.ReadReq_avg_mshr_miss_latency::total 92770.259987 # average ReadReq mshr miss latency +system.l1subsys0.cache1.WriteReq_avg_mshr_miss_latency::l0subsys1.tester0 85817.679883 # average WriteReq mshr miss latency +system.l1subsys0.cache1.WriteReq_avg_mshr_miss_latency::l0subsys1.tester1 84260.133200 # average WriteReq mshr miss latency +system.l1subsys0.cache1.WriteReq_avg_mshr_miss_latency::total 85025.848446 # average WriteReq mshr miss latency +system.l1subsys0.cache1.demand_avg_mshr_miss_latency::l0subsys1.tester0 89952.976276 # average overall mshr miss latency +system.l1subsys0.cache1.demand_avg_mshr_miss_latency::l0subsys1.tester1 89347.949166 # average overall mshr miss latency +system.l1subsys0.cache1.demand_avg_mshr_miss_latency::total 89646.144803 # average overall mshr miss latency +system.l1subsys0.cache1.overall_avg_mshr_miss_latency::l0subsys1.tester0 89952.976276 # average overall mshr miss latency +system.l1subsys0.cache1.overall_avg_mshr_miss_latency::l0subsys1.tester1 89347.949166 # average overall mshr miss latency +system.l1subsys0.cache1.overall_avg_mshr_miss_latency::total 89646.144803 # average overall mshr miss latency +system.l1subsys0.xbar.snoop_filter.tot_requests 345070 # Total number of requests made to the snoop filter. +system.l1subsys0.xbar.snoop_filter.hit_single_requests 163003 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.l1subsys0.xbar.snoop_filter.hit_multi_requests 8917 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.l1subsys0.xbar.snoop_filter.tot_snoops 156506 # Total number of snoops made to the snoop filter. +system.l1subsys0.xbar.snoop_filter.hit_single_snoops 138247 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.l1subsys0.xbar.snoop_filter.hit_multi_snoops 18259 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.l1subsys0.xbar.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states -system.l1subsys0.xbar.trans_dist::ReadResp 154200 # Transaction distribution -system.l1subsys0.xbar.trans_dist::ReadRespWithInvalidate 3741 # Transaction distribution -system.l1subsys0.xbar.trans_dist::WritebackDirty 97097 # Transaction distribution -system.l1subsys0.xbar.trans_dist::CleanEvict 173883 # Transaction distribution -system.l1subsys0.xbar.trans_dist::UpgradeReq 38331 # Transaction distribution -system.l1subsys0.xbar.trans_dist::UpgradeResp 23879 # Transaction distribution -system.l1subsys0.xbar.trans_dist::ReadExReq 99951 # Transaction distribution -system.l1subsys0.xbar.trans_dist::ReadExResp 92343 # Transaction distribution -system.l1subsys0.xbar.trans_dist::ReadSharedReq 167597 # Transaction distribution -system.l1subsys0.xbar.pkt_count_system.l1subsys0.cache0.mem_side::system.l2subsys0.cache1.cpu_side 309959 # Packet count per connected master and slave (bytes) -system.l1subsys0.xbar.pkt_count_system.l1subsys0.cache1.mem_side::system.l2subsys0.cache1.cpu_side 304154 # Packet count per connected master and slave (bytes) -system.l1subsys0.xbar.pkt_count::total 614113 # Packet count per connected master and slave (bytes) -system.l1subsys0.xbar.pkt_size_system.l1subsys0.cache0.mem_side::system.l2subsys0.cache1.cpu_side 9308608 # Cumulative packet size per connected master and slave (bytes) -system.l1subsys0.xbar.pkt_size_system.l1subsys0.cache1.mem_side::system.l2subsys0.cache1.cpu_side 9043712 # Cumulative packet size per connected master and slave (bytes) -system.l1subsys0.xbar.pkt_size::total 18352320 # Cumulative packet size per connected master and slave (bytes) -system.l1subsys0.xbar.snoops 293338 # Total snoops (count) -system.l1subsys0.xbar.snoopTraffic 6950656 # Total snoop traffic (bytes) -system.l1subsys0.xbar.snoop_fanout::samples 440460 # Request fanout histogram -system.l1subsys0.xbar.snoop_fanout::mean 0.353033 # Request fanout histogram -system.l1subsys0.xbar.snoop_fanout::stdev 0.545932 # Request fanout histogram +system.l1subsys0.xbar.trans_dist::ReadResp 154272 # Transaction distribution +system.l1subsys0.xbar.trans_dist::ReadRespWithInvalidate 4493 # Transaction distribution +system.l1subsys0.xbar.trans_dist::WritebackDirty 92411 # Transaction distribution +system.l1subsys0.xbar.trans_dist::CleanEvict 188842 # Transaction distribution +system.l1subsys0.xbar.trans_dist::UpgradeReq 38589 # Transaction distribution +system.l1subsys0.xbar.trans_dist::UpgradeResp 23198 # Transaction distribution +system.l1subsys0.xbar.trans_dist::ReadExReq 102825 # Transaction distribution +system.l1subsys0.xbar.trans_dist::ReadExResp 93371 # Transaction distribution +system.l1subsys0.xbar.trans_dist::ReadSharedReq 169934 # Transaction distribution +system.l1subsys0.xbar.pkt_count_system.l1subsys0.cache0.mem_side::system.l2subsys0.cache1.cpu_side 301161 # Packet count per connected master and slave (bytes) +system.l1subsys0.xbar.pkt_count_system.l1subsys0.cache1.mem_side::system.l2subsys0.cache1.cpu_side 304465 # Packet count per connected master and slave (bytes) +system.l1subsys0.xbar.pkt_count::total 605626 # Packet count per connected master and slave (bytes) +system.l1subsys0.xbar.pkt_size_system.l1subsys0.cache0.mem_side::system.l2subsys0.cache1.cpu_side 9099264 # Cumulative packet size per connected master and slave (bytes) +system.l1subsys0.xbar.pkt_size_system.l1subsys0.cache1.mem_side::system.l2subsys0.cache1.cpu_side 9173504 # Cumulative packet size per connected master and slave (bytes) +system.l1subsys0.xbar.pkt_size::total 18272768 # Cumulative packet size per connected master and slave (bytes) +system.l1subsys0.xbar.snoops 321974 # Total snoops (count) +system.l1subsys0.xbar.snoopTraffic 7063936 # Total snoop traffic (bytes) +system.l1subsys0.xbar.snoop_fanout::samples 463201 # Request fanout histogram +system.l1subsys0.xbar.snoop_fanout::mean 0.438401 # Request fanout histogram +system.l1subsys0.xbar.snoop_fanout::stdev 0.570127 # Request fanout histogram system.l1subsys0.xbar.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.l1subsys0.xbar.snoop_fanout::0 300300 68.18% 68.18% # Request fanout histogram -system.l1subsys0.xbar.snoop_fanout::1 124823 28.34% 96.52% # Request fanout histogram -system.l1subsys0.xbar.snoop_fanout::2 15337 3.48% 100.00% # Request fanout histogram +system.l1subsys0.xbar.snoop_fanout::0 278392 60.10% 60.10% # Request fanout histogram +system.l1subsys0.xbar.snoop_fanout::1 166550 35.96% 96.06% # Request fanout histogram +system.l1subsys0.xbar.snoop_fanout::2 18259 3.94% 100.00% # Request fanout histogram system.l1subsys0.xbar.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.l1subsys0.xbar.snoop_fanout::min_value 0 # Request fanout histogram system.l1subsys0.xbar.snoop_fanout::max_value 2 # Request fanout histogram -system.l1subsys0.xbar.snoop_fanout::total 440460 # Request fanout histogram -system.l1subsys0.xbar.reqLayer0.occupancy 551865865 # Layer occupancy (ticks) -system.l1subsys0.xbar.reqLayer0.utilization 5.5 # Layer utilization (%) -system.l1subsys0.xbar.snoopLayer0.occupancy 170972115 # Layer occupancy (ticks) -system.l1subsys0.xbar.snoopLayer0.utilization 1.7 # Layer utilization (%) -system.l1subsys0.xbar.respLayer0.occupancy 318997409 # Layer occupancy (ticks) -system.l1subsys0.xbar.respLayer0.utilization 3.2 # Layer utilization (%) -system.l1subsys0.xbar.respLayer1.occupancy 314273952 # Layer occupancy (ticks) -system.l1subsys0.xbar.respLayer1.utilization 3.1 # Layer utilization (%) +system.l1subsys0.xbar.snoop_fanout::total 463201 # Request fanout histogram +system.l1subsys0.xbar.reqLayer0.occupancy 536944163 # Layer occupancy (ticks) +system.l1subsys0.xbar.reqLayer0.utilization 5.4 # Layer utilization (%) +system.l1subsys0.xbar.snoopLayer0.occupancy 181542409 # Layer occupancy (ticks) +system.l1subsys0.xbar.snoopLayer0.utilization 1.8 # Layer utilization (%) +system.l1subsys0.xbar.respLayer0.occupancy 313026103 # Layer occupancy (ticks) +system.l1subsys0.xbar.respLayer0.utilization 3.1 # Layer utilization (%) +system.l1subsys0.xbar.respLayer1.occupancy 316235883 # Layer occupancy (ticks) +system.l1subsys0.xbar.respLayer1.utilization 3.2 # Layer utilization (%) system.l1subsys1.cache0.tags.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states -system.l1subsys1.cache0.tags.replacements 64055 # number of replacements -system.l1subsys1.cache0.tags.tagsinuse 501.915078 # Cycle average of tags in use -system.l1subsys1.cache0.tags.total_refs 31614 # Total number of references to valid blocks. -system.l1subsys1.cache0.tags.sampled_refs 64566 # Sample count of references to valid blocks. -system.l1subsys1.cache0.tags.avg_refs 0.489639 # Average number of references to valid blocks. -system.l1subsys1.cache0.tags.warmup_cycle 361927000 # Cycle when the warmup percentage was hit. -system.l1subsys1.cache0.tags.occ_blocks::l0subsys2.tester0 251.524472 # Average occupied blocks per requestor -system.l1subsys1.cache0.tags.occ_blocks::l0subsys2.tester1 250.390607 # Average occupied blocks per requestor -system.l1subsys1.cache0.tags.occ_percent::l0subsys2.tester0 0.491259 # Average percentage of cache occupancy -system.l1subsys1.cache0.tags.occ_percent::l0subsys2.tester1 0.489044 # Average percentage of cache occupancy -system.l1subsys1.cache0.tags.occ_percent::total 0.980303 # Average percentage of cache occupancy -system.l1subsys1.cache0.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id -system.l1subsys1.cache0.tags.age_task_id_blocks_1024::0 105 # Occupied blocks per task id -system.l1subsys1.cache0.tags.age_task_id_blocks_1024::1 383 # Occupied blocks per task id -system.l1subsys1.cache0.tags.age_task_id_blocks_1024::2 23 # Occupied blocks per task id -system.l1subsys1.cache0.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.l1subsys1.cache0.tags.tag_accesses 619158 # Number of tag accesses -system.l1subsys1.cache0.tags.data_accesses 619158 # Number of data accesses +system.l1subsys1.cache0.tags.replacements 62894 # number of replacements +system.l1subsys1.cache0.tags.tagsinuse 502.360512 # Cycle average of tags in use +system.l1subsys1.cache0.tags.total_refs 30318 # Total number of references to valid blocks. +system.l1subsys1.cache0.tags.sampled_refs 63398 # Sample count of references to valid blocks. +system.l1subsys1.cache0.tags.avg_refs 0.478217 # Average number of references to valid blocks. +system.l1subsys1.cache0.tags.warmup_cycle 195013000 # Cycle when the warmup percentage was hit. +system.l1subsys1.cache0.tags.occ_blocks::l0subsys2.tester0 249.855893 # Average occupied blocks per requestor +system.l1subsys1.cache0.tags.occ_blocks::l0subsys2.tester1 252.504619 # Average occupied blocks per requestor +system.l1subsys1.cache0.tags.occ_percent::l0subsys2.tester0 0.488000 # Average percentage of cache occupancy +system.l1subsys1.cache0.tags.occ_percent::l0subsys2.tester1 0.493173 # Average percentage of cache occupancy +system.l1subsys1.cache0.tags.occ_percent::total 0.981173 # Average percentage of cache occupancy +system.l1subsys1.cache0.tags.occ_task_id_blocks::1024 504 # Occupied blocks per task id +system.l1subsys1.cache0.tags.age_task_id_blocks_1024::0 102 # Occupied blocks per task id +system.l1subsys1.cache0.tags.age_task_id_blocks_1024::1 380 # Occupied blocks per task id +system.l1subsys1.cache0.tags.age_task_id_blocks_1024::2 22 # Occupied blocks per task id +system.l1subsys1.cache0.tags.occ_task_id_percent::1024 0.984375 # Percentage of cache occupancy per task id +system.l1subsys1.cache0.tags.tag_accesses 623844 # Number of tag accesses +system.l1subsys1.cache0.tags.data_accesses 623844 # Number of data accesses system.l1subsys1.cache0.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states -system.l1subsys1.cache0.ReadReq_hits::l0subsys2.tester0 10039 # number of ReadReq hits -system.l1subsys1.cache0.ReadReq_hits::l0subsys2.tester1 9798 # number of ReadReq hits -system.l1subsys1.cache0.ReadReq_hits::total 19837 # number of ReadReq hits -system.l1subsys1.cache0.WriteReq_hits::l0subsys2.tester0 1458 # number of WriteReq hits -system.l1subsys1.cache0.WriteReq_hits::l0subsys2.tester1 1375 # number of WriteReq hits -system.l1subsys1.cache0.WriteReq_hits::total 2833 # number of WriteReq hits -system.l1subsys1.cache0.demand_hits::l0subsys2.tester0 11497 # number of demand (read+write) hits -system.l1subsys1.cache0.demand_hits::l0subsys2.tester1 11173 # number of demand (read+write) hits -system.l1subsys1.cache0.demand_hits::total 22670 # number of demand (read+write) hits -system.l1subsys1.cache0.overall_hits::l0subsys2.tester0 11497 # number of overall hits -system.l1subsys1.cache0.overall_hits::l0subsys2.tester1 11173 # number of overall hits -system.l1subsys1.cache0.overall_hits::total 22670 # number of overall hits -system.l1subsys1.cache0.ReadReq_misses::l0subsys2.tester0 32196 # number of ReadReq misses -system.l1subsys1.cache0.ReadReq_misses::l0subsys2.tester1 32094 # number of ReadReq misses -system.l1subsys1.cache0.ReadReq_misses::total 64290 # number of ReadReq misses -system.l1subsys1.cache0.WriteReq_misses::l0subsys2.tester0 21530 # number of WriteReq misses -system.l1subsys1.cache0.WriteReq_misses::l0subsys2.tester1 21989 # number of WriteReq misses -system.l1subsys1.cache0.WriteReq_misses::total 43519 # number of WriteReq misses -system.l1subsys1.cache0.demand_misses::l0subsys2.tester0 53726 # number of demand (read+write) misses -system.l1subsys1.cache0.demand_misses::l0subsys2.tester1 54083 # number of demand (read+write) misses -system.l1subsys1.cache0.demand_misses::total 107809 # number of demand (read+write) misses -system.l1subsys1.cache0.overall_misses::l0subsys2.tester0 53726 # number of overall misses -system.l1subsys1.cache0.overall_misses::l0subsys2.tester1 54083 # number of overall misses -system.l1subsys1.cache0.overall_misses::total 107809 # number of overall misses -system.l1subsys1.cache0.ReadReq_miss_latency::l0subsys2.tester0 2965752810 # number of ReadReq miss cycles -system.l1subsys1.cache0.ReadReq_miss_latency::l0subsys2.tester1 2931730977 # number of ReadReq miss cycles -system.l1subsys1.cache0.ReadReq_miss_latency::total 5897483787 # number of ReadReq miss cycles -system.l1subsys1.cache0.WriteReq_miss_latency::l0subsys2.tester0 1800358800 # number of WriteReq miss cycles -system.l1subsys1.cache0.WriteReq_miss_latency::l0subsys2.tester1 1820867176 # number of WriteReq miss cycles -system.l1subsys1.cache0.WriteReq_miss_latency::total 3621225976 # number of WriteReq miss cycles -system.l1subsys1.cache0.demand_miss_latency::l0subsys2.tester0 4766111610 # number of demand (read+write) miss cycles -system.l1subsys1.cache0.demand_miss_latency::l0subsys2.tester1 4752598153 # number of demand (read+write) miss cycles -system.l1subsys1.cache0.demand_miss_latency::total 9518709763 # number of demand (read+write) miss cycles -system.l1subsys1.cache0.overall_miss_latency::l0subsys2.tester0 4766111610 # number of overall miss cycles -system.l1subsys1.cache0.overall_miss_latency::l0subsys2.tester1 4752598153 # number of overall miss cycles -system.l1subsys1.cache0.overall_miss_latency::total 9518709763 # number of overall miss cycles -system.l1subsys1.cache0.ReadReq_accesses::l0subsys2.tester0 42235 # number of ReadReq accesses(hits+misses) -system.l1subsys1.cache0.ReadReq_accesses::l0subsys2.tester1 41892 # number of ReadReq accesses(hits+misses) -system.l1subsys1.cache0.ReadReq_accesses::total 84127 # number of ReadReq accesses(hits+misses) -system.l1subsys1.cache0.WriteReq_accesses::l0subsys2.tester0 22988 # number of WriteReq accesses(hits+misses) -system.l1subsys1.cache0.WriteReq_accesses::l0subsys2.tester1 23364 # number of WriteReq accesses(hits+misses) -system.l1subsys1.cache0.WriteReq_accesses::total 46352 # number of WriteReq accesses(hits+misses) -system.l1subsys1.cache0.demand_accesses::l0subsys2.tester0 65223 # number of demand (read+write) accesses -system.l1subsys1.cache0.demand_accesses::l0subsys2.tester1 65256 # number of demand (read+write) accesses -system.l1subsys1.cache0.demand_accesses::total 130479 # number of demand (read+write) accesses -system.l1subsys1.cache0.overall_accesses::l0subsys2.tester0 65223 # number of overall (read+write) accesses -system.l1subsys1.cache0.overall_accesses::l0subsys2.tester1 65256 # number of overall (read+write) accesses -system.l1subsys1.cache0.overall_accesses::total 130479 # number of overall (read+write) accesses -system.l1subsys1.cache0.ReadReq_miss_rate::l0subsys2.tester0 0.762306 # miss rate for ReadReq accesses -system.l1subsys1.cache0.ReadReq_miss_rate::l0subsys2.tester1 0.766113 # miss rate for ReadReq accesses -system.l1subsys1.cache0.ReadReq_miss_rate::total 0.764202 # miss rate for ReadReq accesses -system.l1subsys1.cache0.WriteReq_miss_rate::l0subsys2.tester0 0.936576 # miss rate for WriteReq accesses -system.l1subsys1.cache0.WriteReq_miss_rate::l0subsys2.tester1 0.941149 # miss rate for WriteReq accesses -system.l1subsys1.cache0.WriteReq_miss_rate::total 0.938881 # miss rate for WriteReq accesses -system.l1subsys1.cache0.demand_miss_rate::l0subsys2.tester0 0.823728 # miss rate for demand accesses -system.l1subsys1.cache0.demand_miss_rate::l0subsys2.tester1 0.828782 # miss rate for demand accesses -system.l1subsys1.cache0.demand_miss_rate::total 0.826256 # miss rate for demand accesses -system.l1subsys1.cache0.overall_miss_rate::l0subsys2.tester0 0.823728 # miss rate for overall accesses -system.l1subsys1.cache0.overall_miss_rate::l0subsys2.tester1 0.828782 # miss rate for overall accesses -system.l1subsys1.cache0.overall_miss_rate::total 0.826256 # miss rate for overall accesses -system.l1subsys1.cache0.ReadReq_avg_miss_latency::l0subsys2.tester0 92115.567462 # average ReadReq miss latency -system.l1subsys1.cache0.ReadReq_avg_miss_latency::l0subsys2.tester1 91348.257525 # average ReadReq miss latency -system.l1subsys1.cache0.ReadReq_avg_miss_latency::total 91732.521185 # average ReadReq miss latency -system.l1subsys1.cache0.WriteReq_avg_miss_latency::l0subsys2.tester0 83620.938226 # average WriteReq miss latency -system.l1subsys1.cache0.WriteReq_avg_miss_latency::l0subsys2.tester1 82808.093865 # average WriteReq miss latency -system.l1subsys1.cache0.WriteReq_avg_miss_latency::total 83210.229463 # average WriteReq miss latency -system.l1subsys1.cache0.demand_avg_miss_latency::l0subsys2.tester0 88711.454603 # average overall miss latency -system.l1subsys1.cache0.demand_avg_miss_latency::l0subsys2.tester1 87876.008228 # average overall miss latency -system.l1subsys1.cache0.demand_avg_miss_latency::total 88292.348162 # average overall miss latency -system.l1subsys1.cache0.overall_avg_miss_latency::l0subsys2.tester0 88711.454603 # average overall miss latency -system.l1subsys1.cache0.overall_avg_miss_latency::l0subsys2.tester1 87876.008228 # average overall miss latency -system.l1subsys1.cache0.overall_avg_miss_latency::total 88292.348162 # average overall miss latency -system.l1subsys1.cache0.blocked_cycles::no_mshrs 257225 # number of cycles access was blocked +system.l1subsys1.cache0.ReadReq_hits::l0subsys2.tester0 9625 # number of ReadReq hits +system.l1subsys1.cache0.ReadReq_hits::l0subsys2.tester1 9444 # number of ReadReq hits +system.l1subsys1.cache0.ReadReq_hits::total 19069 # number of ReadReq hits +system.l1subsys1.cache0.WriteReq_hits::l0subsys2.tester0 1133 # number of WriteReq hits +system.l1subsys1.cache0.WriteReq_hits::l0subsys2.tester1 1194 # number of WriteReq hits +system.l1subsys1.cache0.WriteReq_hits::total 2327 # number of WriteReq hits +system.l1subsys1.cache0.demand_hits::l0subsys2.tester0 10758 # number of demand (read+write) hits +system.l1subsys1.cache0.demand_hits::l0subsys2.tester1 10638 # number of demand (read+write) hits +system.l1subsys1.cache0.demand_hits::total 21396 # number of demand (read+write) hits +system.l1subsys1.cache0.overall_hits::l0subsys2.tester0 10758 # number of overall hits +system.l1subsys1.cache0.overall_hits::l0subsys2.tester1 10638 # number of overall hits +system.l1subsys1.cache0.overall_hits::total 21396 # number of overall hits +system.l1subsys1.cache0.ReadReq_misses::l0subsys2.tester0 32686 # number of ReadReq misses +system.l1subsys1.cache0.ReadReq_misses::l0subsys2.tester1 32579 # number of ReadReq misses +system.l1subsys1.cache0.ReadReq_misses::total 65265 # number of ReadReq misses +system.l1subsys1.cache0.WriteReq_misses::l0subsys2.tester0 22368 # number of WriteReq misses +system.l1subsys1.cache0.WriteReq_misses::l0subsys2.tester1 22220 # number of WriteReq misses +system.l1subsys1.cache0.WriteReq_misses::total 44588 # number of WriteReq misses +system.l1subsys1.cache0.demand_misses::l0subsys2.tester0 55054 # number of demand (read+write) misses +system.l1subsys1.cache0.demand_misses::l0subsys2.tester1 54799 # number of demand (read+write) misses +system.l1subsys1.cache0.demand_misses::total 109853 # number of demand (read+write) misses +system.l1subsys1.cache0.overall_misses::l0subsys2.tester0 55054 # number of overall misses +system.l1subsys1.cache0.overall_misses::l0subsys2.tester1 54799 # number of overall misses +system.l1subsys1.cache0.overall_misses::total 109853 # number of overall misses +system.l1subsys1.cache0.ReadReq_miss_latency::l0subsys2.tester0 2952180938 # number of ReadReq miss cycles +system.l1subsys1.cache0.ReadReq_miss_latency::l0subsys2.tester1 2978156965 # number of ReadReq miss cycles +system.l1subsys1.cache0.ReadReq_miss_latency::total 5930337903 # number of ReadReq miss cycles +system.l1subsys1.cache0.WriteReq_miss_latency::l0subsys2.tester0 1826783335 # number of WriteReq miss cycles +system.l1subsys1.cache0.WriteReq_miss_latency::l0subsys2.tester1 1815663793 # number of WriteReq miss cycles +system.l1subsys1.cache0.WriteReq_miss_latency::total 3642447128 # number of WriteReq miss cycles +system.l1subsys1.cache0.demand_miss_latency::l0subsys2.tester0 4778964273 # number of demand (read+write) miss cycles +system.l1subsys1.cache0.demand_miss_latency::l0subsys2.tester1 4793820758 # number of demand (read+write) miss cycles +system.l1subsys1.cache0.demand_miss_latency::total 9572785031 # number of demand (read+write) miss cycles +system.l1subsys1.cache0.overall_miss_latency::l0subsys2.tester0 4778964273 # number of overall miss cycles +system.l1subsys1.cache0.overall_miss_latency::l0subsys2.tester1 4793820758 # number of overall miss cycles +system.l1subsys1.cache0.overall_miss_latency::total 9572785031 # number of overall miss cycles +system.l1subsys1.cache0.ReadReq_accesses::l0subsys2.tester0 42311 # number of ReadReq accesses(hits+misses) +system.l1subsys1.cache0.ReadReq_accesses::l0subsys2.tester1 42023 # number of ReadReq accesses(hits+misses) +system.l1subsys1.cache0.ReadReq_accesses::total 84334 # number of ReadReq accesses(hits+misses) +system.l1subsys1.cache0.WriteReq_accesses::l0subsys2.tester0 23501 # number of WriteReq accesses(hits+misses) +system.l1subsys1.cache0.WriteReq_accesses::l0subsys2.tester1 23414 # number of WriteReq accesses(hits+misses) +system.l1subsys1.cache0.WriteReq_accesses::total 46915 # number of WriteReq accesses(hits+misses) +system.l1subsys1.cache0.demand_accesses::l0subsys2.tester0 65812 # number of demand (read+write) accesses +system.l1subsys1.cache0.demand_accesses::l0subsys2.tester1 65437 # number of demand (read+write) accesses +system.l1subsys1.cache0.demand_accesses::total 131249 # number of demand (read+write) accesses +system.l1subsys1.cache0.overall_accesses::l0subsys2.tester0 65812 # number of overall (read+write) accesses +system.l1subsys1.cache0.overall_accesses::l0subsys2.tester1 65437 # number of overall (read+write) accesses +system.l1subsys1.cache0.overall_accesses::total 131249 # number of overall (read+write) accesses +system.l1subsys1.cache0.ReadReq_miss_rate::l0subsys2.tester0 0.772518 # miss rate for ReadReq accesses +system.l1subsys1.cache0.ReadReq_miss_rate::l0subsys2.tester1 0.775266 # miss rate for ReadReq accesses +system.l1subsys1.cache0.ReadReq_miss_rate::total 0.773887 # miss rate for ReadReq accesses +system.l1subsys1.cache0.WriteReq_miss_rate::l0subsys2.tester0 0.951789 # miss rate for WriteReq accesses +system.l1subsys1.cache0.WriteReq_miss_rate::l0subsys2.tester1 0.949005 # miss rate for WriteReq accesses +system.l1subsys1.cache0.WriteReq_miss_rate::total 0.950400 # miss rate for WriteReq accesses +system.l1subsys1.cache0.demand_miss_rate::l0subsys2.tester0 0.836534 # miss rate for demand accesses +system.l1subsys1.cache0.demand_miss_rate::l0subsys2.tester1 0.837431 # miss rate for demand accesses +system.l1subsys1.cache0.demand_miss_rate::total 0.836982 # miss rate for demand accesses +system.l1subsys1.cache0.overall_miss_rate::l0subsys2.tester0 0.836534 # miss rate for overall accesses +system.l1subsys1.cache0.overall_miss_rate::l0subsys2.tester1 0.837431 # miss rate for overall accesses +system.l1subsys1.cache0.overall_miss_rate::total 0.836982 # miss rate for overall accesses +system.l1subsys1.cache0.ReadReq_avg_miss_latency::l0subsys2.tester0 90319.431500 # average ReadReq miss latency +system.l1subsys1.cache0.ReadReq_avg_miss_latency::l0subsys2.tester1 91413.394058 # average ReadReq miss latency +system.l1subsys1.cache0.ReadReq_avg_miss_latency::total 90865.516019 # average ReadReq miss latency +system.l1subsys1.cache0.WriteReq_avg_miss_latency::l0subsys2.tester0 81669.498167 # average WriteReq miss latency +system.l1subsys1.cache0.WriteReq_avg_miss_latency::l0subsys2.tester1 81713.041989 # average WriteReq miss latency +system.l1subsys1.cache0.WriteReq_avg_miss_latency::total 81691.197811 # average WriteReq miss latency +system.l1subsys1.cache0.demand_avg_miss_latency::l0subsys2.tester0 86805.032750 # average overall miss latency +system.l1subsys1.cache0.demand_avg_miss_latency::l0subsys2.tester1 87480.077337 # average overall miss latency +system.l1subsys1.cache0.demand_avg_miss_latency::total 87141.771558 # average overall miss latency +system.l1subsys1.cache0.overall_avg_miss_latency::l0subsys2.tester0 86805.032750 # average overall miss latency +system.l1subsys1.cache0.overall_avg_miss_latency::l0subsys2.tester1 87480.077337 # average overall miss latency +system.l1subsys1.cache0.overall_avg_miss_latency::total 87141.771558 # average overall miss latency +system.l1subsys1.cache0.blocked_cycles::no_mshrs 273729 # number of cycles access was blocked system.l1subsys1.cache0.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l1subsys1.cache0.blocked::no_mshrs 7861 # number of cycles access was blocked +system.l1subsys1.cache0.blocked::no_mshrs 8512 # number of cycles access was blocked system.l1subsys1.cache0.blocked::no_targets 0 # number of cycles access was blocked -system.l1subsys1.cache0.avg_blocked_cycles::no_mshrs 32.721664 # average number of cycles each access was blocked +system.l1subsys1.cache0.avg_blocked_cycles::no_mshrs 32.158012 # average number of cycles each access was blocked system.l1subsys1.cache0.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.l1subsys1.cache0.writebacks::writebacks 22897 # number of writebacks -system.l1subsys1.cache0.writebacks::total 22897 # number of writebacks -system.l1subsys1.cache0.ReadReq_mshr_hits::l0subsys2.tester0 1156 # number of ReadReq MSHR hits -system.l1subsys1.cache0.ReadReq_mshr_hits::l0subsys2.tester1 1188 # number of ReadReq MSHR hits -system.l1subsys1.cache0.ReadReq_mshr_hits::total 2344 # number of ReadReq MSHR hits -system.l1subsys1.cache0.WriteReq_mshr_hits::l0subsys2.tester0 629 # number of WriteReq MSHR hits -system.l1subsys1.cache0.WriteReq_mshr_hits::l0subsys2.tester1 630 # number of WriteReq MSHR hits -system.l1subsys1.cache0.WriteReq_mshr_hits::total 1259 # number of WriteReq MSHR hits -system.l1subsys1.cache0.demand_mshr_hits::l0subsys2.tester0 1785 # number of demand (read+write) MSHR hits -system.l1subsys1.cache0.demand_mshr_hits::l0subsys2.tester1 1818 # number of demand (read+write) MSHR hits -system.l1subsys1.cache0.demand_mshr_hits::total 3603 # number of demand (read+write) MSHR hits -system.l1subsys1.cache0.overall_mshr_hits::l0subsys2.tester0 1785 # number of overall MSHR hits -system.l1subsys1.cache0.overall_mshr_hits::l0subsys2.tester1 1818 # number of overall MSHR hits -system.l1subsys1.cache0.overall_mshr_hits::total 3603 # number of overall MSHR hits -system.l1subsys1.cache0.ReadReq_mshr_misses::l0subsys2.tester0 31040 # number of ReadReq MSHR misses -system.l1subsys1.cache0.ReadReq_mshr_misses::l0subsys2.tester1 30906 # number of ReadReq MSHR misses -system.l1subsys1.cache0.ReadReq_mshr_misses::total 61946 # number of ReadReq MSHR misses -system.l1subsys1.cache0.WriteReq_mshr_misses::l0subsys2.tester0 20901 # number of WriteReq MSHR misses -system.l1subsys1.cache0.WriteReq_mshr_misses::l0subsys2.tester1 21359 # number of WriteReq MSHR misses -system.l1subsys1.cache0.WriteReq_mshr_misses::total 42260 # number of WriteReq MSHR misses -system.l1subsys1.cache0.demand_mshr_misses::l0subsys2.tester0 51941 # number of demand (read+write) MSHR misses -system.l1subsys1.cache0.demand_mshr_misses::l0subsys2.tester1 52265 # number of demand (read+write) MSHR misses -system.l1subsys1.cache0.demand_mshr_misses::total 104206 # number of demand (read+write) MSHR misses -system.l1subsys1.cache0.overall_mshr_misses::l0subsys2.tester0 51941 # number of overall MSHR misses -system.l1subsys1.cache0.overall_mshr_misses::l0subsys2.tester1 52265 # number of overall MSHR misses -system.l1subsys1.cache0.overall_mshr_misses::total 104206 # number of overall MSHR misses -system.l1subsys1.cache0.ReadReq_mshr_miss_latency::l0subsys2.tester0 2909591102 # number of ReadReq MSHR miss cycles -system.l1subsys1.cache0.ReadReq_mshr_miss_latency::l0subsys2.tester1 2874236758 # number of ReadReq MSHR miss cycles -system.l1subsys1.cache0.ReadReq_mshr_miss_latency::total 5783827860 # number of ReadReq MSHR miss cycles -system.l1subsys1.cache0.WriteReq_mshr_miss_latency::l0subsys2.tester0 1771691969 # number of WriteReq MSHR miss cycles -system.l1subsys1.cache0.WriteReq_mshr_miss_latency::l0subsys2.tester1 1791296943 # number of WriteReq MSHR miss cycles -system.l1subsys1.cache0.WriteReq_mshr_miss_latency::total 3562988912 # number of WriteReq MSHR miss cycles -system.l1subsys1.cache0.demand_mshr_miss_latency::l0subsys2.tester0 4681283071 # number of demand (read+write) MSHR miss cycles -system.l1subsys1.cache0.demand_mshr_miss_latency::l0subsys2.tester1 4665533701 # number of demand (read+write) MSHR miss cycles -system.l1subsys1.cache0.demand_mshr_miss_latency::total 9346816772 # number of demand (read+write) MSHR miss cycles -system.l1subsys1.cache0.overall_mshr_miss_latency::l0subsys2.tester0 4681283071 # number of overall MSHR miss cycles -system.l1subsys1.cache0.overall_mshr_miss_latency::l0subsys2.tester1 4665533701 # number of overall MSHR miss cycles -system.l1subsys1.cache0.overall_mshr_miss_latency::total 9346816772 # number of overall MSHR miss cycles -system.l1subsys1.cache0.ReadReq_mshr_miss_rate::l0subsys2.tester0 0.734935 # mshr miss rate for ReadReq accesses -system.l1subsys1.cache0.ReadReq_mshr_miss_rate::l0subsys2.tester1 0.737754 # mshr miss rate for ReadReq accesses -system.l1subsys1.cache0.ReadReq_mshr_miss_rate::total 0.736339 # mshr miss rate for ReadReq accesses -system.l1subsys1.cache0.WriteReq_mshr_miss_rate::l0subsys2.tester0 0.909214 # mshr miss rate for WriteReq accesses -system.l1subsys1.cache0.WriteReq_mshr_miss_rate::l0subsys2.tester1 0.914184 # mshr miss rate for WriteReq accesses -system.l1subsys1.cache0.WriteReq_mshr_miss_rate::total 0.911719 # mshr miss rate for WriteReq accesses -system.l1subsys1.cache0.demand_mshr_miss_rate::l0subsys2.tester0 0.796360 # mshr miss rate for demand accesses -system.l1subsys1.cache0.demand_mshr_miss_rate::l0subsys2.tester1 0.800923 # mshr miss rate for demand accesses -system.l1subsys1.cache0.demand_mshr_miss_rate::total 0.798642 # mshr miss rate for demand accesses -system.l1subsys1.cache0.overall_mshr_miss_rate::l0subsys2.tester0 0.796360 # mshr miss rate for overall accesses -system.l1subsys1.cache0.overall_mshr_miss_rate::l0subsys2.tester1 0.800923 # mshr miss rate for overall accesses -system.l1subsys1.cache0.overall_mshr_miss_rate::total 0.798642 # mshr miss rate for overall accesses -system.l1subsys1.cache0.ReadReq_avg_mshr_miss_latency::l0subsys2.tester0 93736.826740 # average ReadReq mshr miss latency -system.l1subsys1.cache0.ReadReq_avg_mshr_miss_latency::l0subsys2.tester1 92999.312690 # average ReadReq mshr miss latency -system.l1subsys1.cache0.ReadReq_avg_mshr_miss_latency::total 93368.867401 # average ReadReq mshr miss latency -system.l1subsys1.cache0.WriteReq_avg_mshr_miss_latency::l0subsys2.tester0 84765.894885 # average WriteReq mshr miss latency -system.l1subsys1.cache0.WriteReq_avg_mshr_miss_latency::l0subsys2.tester1 83866.142750 # average WriteReq mshr miss latency -system.l1subsys1.cache0.WriteReq_avg_mshr_miss_latency::total 84311.143209 # average WriteReq mshr miss latency -system.l1subsys1.cache0.demand_avg_mshr_miss_latency::l0subsys2.tester0 90126.933848 # average overall mshr miss latency -system.l1subsys1.cache0.demand_avg_mshr_miss_latency::l0subsys2.tester1 89266.884167 # average overall mshr miss latency -system.l1subsys1.cache0.demand_avg_mshr_miss_latency::total 89695.571963 # average overall mshr miss latency -system.l1subsys1.cache0.overall_avg_mshr_miss_latency::l0subsys2.tester0 90126.933848 # average overall mshr miss latency -system.l1subsys1.cache0.overall_avg_mshr_miss_latency::l0subsys2.tester1 89266.884167 # average overall mshr miss latency -system.l1subsys1.cache0.overall_avg_mshr_miss_latency::total 89695.571963 # average overall mshr miss latency +system.l1subsys1.cache0.writebacks::writebacks 22484 # number of writebacks +system.l1subsys1.cache0.writebacks::total 22484 # number of writebacks +system.l1subsys1.cache0.ReadReq_mshr_hits::l0subsys2.tester0 1351 # number of ReadReq MSHR hits +system.l1subsys1.cache0.ReadReq_mshr_hits::l0subsys2.tester1 1340 # number of ReadReq MSHR hits +system.l1subsys1.cache0.ReadReq_mshr_hits::total 2691 # number of ReadReq MSHR hits +system.l1subsys1.cache0.WriteReq_mshr_hits::l0subsys2.tester0 761 # number of WriteReq MSHR hits +system.l1subsys1.cache0.WriteReq_mshr_hits::l0subsys2.tester1 811 # number of WriteReq MSHR hits +system.l1subsys1.cache0.WriteReq_mshr_hits::total 1572 # number of WriteReq MSHR hits +system.l1subsys1.cache0.demand_mshr_hits::l0subsys2.tester0 2112 # number of demand (read+write) MSHR hits +system.l1subsys1.cache0.demand_mshr_hits::l0subsys2.tester1 2151 # number of demand (read+write) MSHR hits +system.l1subsys1.cache0.demand_mshr_hits::total 4263 # number of demand (read+write) MSHR hits +system.l1subsys1.cache0.overall_mshr_hits::l0subsys2.tester0 2112 # number of overall MSHR hits +system.l1subsys1.cache0.overall_mshr_hits::l0subsys2.tester1 2151 # number of overall MSHR hits +system.l1subsys1.cache0.overall_mshr_hits::total 4263 # number of overall MSHR hits +system.l1subsys1.cache0.ReadReq_mshr_misses::l0subsys2.tester0 31335 # number of ReadReq MSHR misses +system.l1subsys1.cache0.ReadReq_mshr_misses::l0subsys2.tester1 31239 # number of ReadReq MSHR misses +system.l1subsys1.cache0.ReadReq_mshr_misses::total 62574 # number of ReadReq MSHR misses +system.l1subsys1.cache0.WriteReq_mshr_misses::l0subsys2.tester0 21607 # number of WriteReq MSHR misses +system.l1subsys1.cache0.WriteReq_mshr_misses::l0subsys2.tester1 21409 # number of WriteReq MSHR misses +system.l1subsys1.cache0.WriteReq_mshr_misses::total 43016 # number of WriteReq MSHR misses +system.l1subsys1.cache0.demand_mshr_misses::l0subsys2.tester0 52942 # number of demand (read+write) MSHR misses +system.l1subsys1.cache0.demand_mshr_misses::l0subsys2.tester1 52648 # number of demand (read+write) MSHR misses +system.l1subsys1.cache0.demand_mshr_misses::total 105590 # number of demand (read+write) MSHR misses +system.l1subsys1.cache0.overall_mshr_misses::l0subsys2.tester0 52942 # number of overall MSHR misses +system.l1subsys1.cache0.overall_mshr_misses::l0subsys2.tester1 52648 # number of overall MSHR misses +system.l1subsys1.cache0.overall_mshr_misses::total 105590 # number of overall MSHR misses +system.l1subsys1.cache0.ReadReq_mshr_miss_latency::l0subsys2.tester0 2891074988 # number of ReadReq MSHR miss cycles +system.l1subsys1.cache0.ReadReq_mshr_miss_latency::l0subsys2.tester1 2917502752 # number of ReadReq MSHR miss cycles +system.l1subsys1.cache0.ReadReq_mshr_miss_latency::total 5808577740 # number of ReadReq MSHR miss cycles +system.l1subsys1.cache0.WriteReq_mshr_miss_latency::l0subsys2.tester0 1795222958 # number of WriteReq MSHR miss cycles +system.l1subsys1.cache0.WriteReq_mshr_miss_latency::l0subsys2.tester1 1782842702 # number of WriteReq MSHR miss cycles +system.l1subsys1.cache0.WriteReq_mshr_miss_latency::total 3578065660 # number of WriteReq MSHR miss cycles +system.l1subsys1.cache0.demand_mshr_miss_latency::l0subsys2.tester0 4686297946 # number of demand (read+write) MSHR miss cycles +system.l1subsys1.cache0.demand_mshr_miss_latency::l0subsys2.tester1 4700345454 # number of demand (read+write) MSHR miss cycles +system.l1subsys1.cache0.demand_mshr_miss_latency::total 9386643400 # number of demand (read+write) MSHR miss cycles +system.l1subsys1.cache0.overall_mshr_miss_latency::l0subsys2.tester0 4686297946 # number of overall MSHR miss cycles +system.l1subsys1.cache0.overall_mshr_miss_latency::l0subsys2.tester1 4700345454 # number of overall MSHR miss cycles +system.l1subsys1.cache0.overall_mshr_miss_latency::total 9386643400 # number of overall MSHR miss cycles +system.l1subsys1.cache0.ReadReq_mshr_miss_rate::l0subsys2.tester0 0.740588 # mshr miss rate for ReadReq accesses +system.l1subsys1.cache0.ReadReq_mshr_miss_rate::l0subsys2.tester1 0.743379 # mshr miss rate for ReadReq accesses +system.l1subsys1.cache0.ReadReq_mshr_miss_rate::total 0.741978 # mshr miss rate for ReadReq accesses +system.l1subsys1.cache0.WriteReq_mshr_miss_rate::l0subsys2.tester0 0.919408 # mshr miss rate for WriteReq accesses +system.l1subsys1.cache0.WriteReq_mshr_miss_rate::l0subsys2.tester1 0.914367 # mshr miss rate for WriteReq accesses +system.l1subsys1.cache0.WriteReq_mshr_miss_rate::total 0.916892 # mshr miss rate for WriteReq accesses +system.l1subsys1.cache0.demand_mshr_miss_rate::l0subsys2.tester0 0.804443 # mshr miss rate for demand accesses +system.l1subsys1.cache0.demand_mshr_miss_rate::l0subsys2.tester1 0.804560 # mshr miss rate for demand accesses +system.l1subsys1.cache0.demand_mshr_miss_rate::total 0.804501 # mshr miss rate for demand accesses +system.l1subsys1.cache0.overall_mshr_miss_rate::l0subsys2.tester0 0.804443 # mshr miss rate for overall accesses +system.l1subsys1.cache0.overall_mshr_miss_rate::l0subsys2.tester1 0.804560 # mshr miss rate for overall accesses +system.l1subsys1.cache0.overall_mshr_miss_rate::total 0.804501 # mshr miss rate for overall accesses +system.l1subsys1.cache0.ReadReq_avg_mshr_miss_latency::l0subsys2.tester0 92263.443051 # average ReadReq mshr miss latency +system.l1subsys1.cache0.ReadReq_avg_mshr_miss_latency::l0subsys2.tester1 93392.962387 # average ReadReq mshr miss latency +system.l1subsys1.cache0.ReadReq_avg_mshr_miss_latency::total 92827.336274 # average ReadReq mshr miss latency +system.l1subsys1.cache0.WriteReq_avg_mshr_miss_latency::l0subsys2.tester0 83085.248207 # average WriteReq mshr miss latency +system.l1subsys1.cache0.WriteReq_avg_mshr_miss_latency::l0subsys2.tester1 83275.384278 # average WriteReq mshr miss latency +system.l1subsys1.cache0.WriteReq_avg_mshr_miss_latency::total 83179.878650 # average WriteReq mshr miss latency +system.l1subsys1.cache0.demand_avg_mshr_miss_latency::l0subsys2.tester0 88517.584262 # average overall mshr miss latency +system.l1subsys1.cache0.demand_avg_mshr_miss_latency::l0subsys2.tester1 89278.708669 # average overall mshr miss latency +system.l1subsys1.cache0.demand_avg_mshr_miss_latency::total 88897.086845 # average overall mshr miss latency +system.l1subsys1.cache0.overall_avg_mshr_miss_latency::l0subsys2.tester0 88517.584262 # average overall mshr miss latency +system.l1subsys1.cache0.overall_avg_mshr_miss_latency::l0subsys2.tester1 89278.708669 # average overall mshr miss latency +system.l1subsys1.cache0.overall_avg_mshr_miss_latency::total 88897.086845 # average overall mshr miss latency system.l1subsys1.cache1.tags.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states -system.l1subsys1.cache1.tags.replacements 63731 # number of replacements -system.l1subsys1.cache1.tags.tagsinuse 503.303418 # Cycle average of tags in use -system.l1subsys1.cache1.tags.total_refs 29004 # Total number of references to valid blocks. -system.l1subsys1.cache1.tags.sampled_refs 64234 # Sample count of references to valid blocks. -system.l1subsys1.cache1.tags.avg_refs 0.451537 # Average number of references to valid blocks. -system.l1subsys1.cache1.tags.warmup_cycle 167138000 # Cycle when the warmup percentage was hit. -system.l1subsys1.cache1.tags.occ_blocks::l0subsys3.tester0 256.700726 # Average occupied blocks per requestor -system.l1subsys1.cache1.tags.occ_blocks::l0subsys3.tester1 246.602692 # Average occupied blocks per requestor -system.l1subsys1.cache1.tags.occ_percent::l0subsys3.tester0 0.501369 # Average percentage of cache occupancy -system.l1subsys1.cache1.tags.occ_percent::l0subsys3.tester1 0.481646 # Average percentage of cache occupancy -system.l1subsys1.cache1.tags.occ_percent::total 0.983014 # Average percentage of cache occupancy -system.l1subsys1.cache1.tags.occ_task_id_blocks::1024 503 # Occupied blocks per task id -system.l1subsys1.cache1.tags.age_task_id_blocks_1024::0 5 # Occupied blocks per task id -system.l1subsys1.cache1.tags.age_task_id_blocks_1024::1 405 # Occupied blocks per task id -system.l1subsys1.cache1.tags.age_task_id_blocks_1024::2 93 # Occupied blocks per task id -system.l1subsys1.cache1.tags.occ_task_id_percent::1024 0.982422 # Percentage of cache occupancy per task id -system.l1subsys1.cache1.tags.tag_accesses 617940 # Number of tag accesses -system.l1subsys1.cache1.tags.data_accesses 617940 # Number of data accesses +system.l1subsys1.cache1.tags.replacements 63994 # number of replacements +system.l1subsys1.cache1.tags.tagsinuse 503.289590 # Cycle average of tags in use +system.l1subsys1.cache1.tags.total_refs 28611 # Total number of references to valid blocks. +system.l1subsys1.cache1.tags.sampled_refs 64495 # Sample count of references to valid blocks. +system.l1subsys1.cache1.tags.avg_refs 0.443616 # Average number of references to valid blocks. +system.l1subsys1.cache1.tags.warmup_cycle 273027000 # Cycle when the warmup percentage was hit. +system.l1subsys1.cache1.tags.occ_blocks::l0subsys3.tester0 252.648267 # Average occupied blocks per requestor +system.l1subsys1.cache1.tags.occ_blocks::l0subsys3.tester1 250.641323 # Average occupied blocks per requestor +system.l1subsys1.cache1.tags.occ_percent::l0subsys3.tester0 0.493454 # Average percentage of cache occupancy +system.l1subsys1.cache1.tags.occ_percent::l0subsys3.tester1 0.489534 # Average percentage of cache occupancy +system.l1subsys1.cache1.tags.occ_percent::total 0.982987 # Average percentage of cache occupancy +system.l1subsys1.cache1.tags.occ_task_id_blocks::1024 501 # Occupied blocks per task id +system.l1subsys1.cache1.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id +system.l1subsys1.cache1.tags.age_task_id_blocks_1024::1 370 # Occupied blocks per task id +system.l1subsys1.cache1.tags.age_task_id_blocks_1024::2 32 # Occupied blocks per task id +system.l1subsys1.cache1.tags.occ_task_id_percent::1024 0.978516 # Percentage of cache occupancy per task id +system.l1subsys1.cache1.tags.tag_accesses 622355 # Number of tag accesses +system.l1subsys1.cache1.tags.data_accesses 622355 # Number of data accesses system.l1subsys1.cache1.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states -system.l1subsys1.cache1.ReadReq_hits::l0subsys3.tester0 9182 # number of ReadReq hits -system.l1subsys1.cache1.ReadReq_hits::l0subsys3.tester1 9019 # number of ReadReq hits -system.l1subsys1.cache1.ReadReq_hits::total 18201 # number of ReadReq hits -system.l1subsys1.cache1.WriteReq_hits::l0subsys3.tester0 1038 # number of WriteReq hits -system.l1subsys1.cache1.WriteReq_hits::l0subsys3.tester1 1002 # number of WriteReq hits -system.l1subsys1.cache1.WriteReq_hits::total 2040 # number of WriteReq hits -system.l1subsys1.cache1.demand_hits::l0subsys3.tester0 10220 # number of demand (read+write) hits -system.l1subsys1.cache1.demand_hits::l0subsys3.tester1 10021 # number of demand (read+write) hits -system.l1subsys1.cache1.demand_hits::total 20241 # number of demand (read+write) hits -system.l1subsys1.cache1.overall_hits::l0subsys3.tester0 10220 # number of overall hits -system.l1subsys1.cache1.overall_hits::l0subsys3.tester1 10021 # number of overall hits -system.l1subsys1.cache1.overall_hits::total 20241 # number of overall hits -system.l1subsys1.cache1.ReadReq_misses::l0subsys3.tester0 33178 # number of ReadReq misses -system.l1subsys1.cache1.ReadReq_misses::l0subsys3.tester1 31976 # number of ReadReq misses -system.l1subsys1.cache1.ReadReq_misses::total 65154 # number of ReadReq misses -system.l1subsys1.cache1.WriteReq_misses::l0subsys3.tester0 22617 # number of WriteReq misses -system.l1subsys1.cache1.WriteReq_misses::l0subsys3.tester1 21777 # number of WriteReq misses -system.l1subsys1.cache1.WriteReq_misses::total 44394 # number of WriteReq misses -system.l1subsys1.cache1.demand_misses::l0subsys3.tester0 55795 # number of demand (read+write) misses -system.l1subsys1.cache1.demand_misses::l0subsys3.tester1 53753 # number of demand (read+write) misses -system.l1subsys1.cache1.demand_misses::total 109548 # number of demand (read+write) misses -system.l1subsys1.cache1.overall_misses::l0subsys3.tester0 55795 # number of overall misses -system.l1subsys1.cache1.overall_misses::l0subsys3.tester1 53753 # number of overall misses -system.l1subsys1.cache1.overall_misses::total 109548 # number of overall misses -system.l1subsys1.cache1.ReadReq_miss_latency::l0subsys3.tester0 3002523024 # number of ReadReq miss cycles -system.l1subsys1.cache1.ReadReq_miss_latency::l0subsys3.tester1 2896966528 # number of ReadReq miss cycles -system.l1subsys1.cache1.ReadReq_miss_latency::total 5899489552 # number of ReadReq miss cycles -system.l1subsys1.cache1.WriteReq_miss_latency::l0subsys3.tester0 1848932916 # number of WriteReq miss cycles -system.l1subsys1.cache1.WriteReq_miss_latency::l0subsys3.tester1 1787708045 # number of WriteReq miss cycles -system.l1subsys1.cache1.WriteReq_miss_latency::total 3636640961 # number of WriteReq miss cycles -system.l1subsys1.cache1.demand_miss_latency::l0subsys3.tester0 4851455940 # number of demand (read+write) miss cycles -system.l1subsys1.cache1.demand_miss_latency::l0subsys3.tester1 4684674573 # number of demand (read+write) miss cycles -system.l1subsys1.cache1.demand_miss_latency::total 9536130513 # number of demand (read+write) miss cycles -system.l1subsys1.cache1.overall_miss_latency::l0subsys3.tester0 4851455940 # number of overall miss cycles -system.l1subsys1.cache1.overall_miss_latency::l0subsys3.tester1 4684674573 # number of overall miss cycles -system.l1subsys1.cache1.overall_miss_latency::total 9536130513 # number of overall miss cycles -system.l1subsys1.cache1.ReadReq_accesses::l0subsys3.tester0 42360 # number of ReadReq accesses(hits+misses) -system.l1subsys1.cache1.ReadReq_accesses::l0subsys3.tester1 40995 # number of ReadReq accesses(hits+misses) -system.l1subsys1.cache1.ReadReq_accesses::total 83355 # number of ReadReq accesses(hits+misses) -system.l1subsys1.cache1.WriteReq_accesses::l0subsys3.tester0 23655 # number of WriteReq accesses(hits+misses) -system.l1subsys1.cache1.WriteReq_accesses::l0subsys3.tester1 22779 # number of WriteReq accesses(hits+misses) -system.l1subsys1.cache1.WriteReq_accesses::total 46434 # number of WriteReq accesses(hits+misses) -system.l1subsys1.cache1.demand_accesses::l0subsys3.tester0 66015 # number of demand (read+write) accesses -system.l1subsys1.cache1.demand_accesses::l0subsys3.tester1 63774 # number of demand (read+write) accesses -system.l1subsys1.cache1.demand_accesses::total 129789 # number of demand (read+write) accesses -system.l1subsys1.cache1.overall_accesses::l0subsys3.tester0 66015 # number of overall (read+write) accesses -system.l1subsys1.cache1.overall_accesses::l0subsys3.tester1 63774 # number of overall (read+write) accesses -system.l1subsys1.cache1.overall_accesses::total 129789 # number of overall (read+write) accesses -system.l1subsys1.cache1.ReadReq_miss_rate::l0subsys3.tester0 0.783239 # miss rate for ReadReq accesses -system.l1subsys1.cache1.ReadReq_miss_rate::l0subsys3.tester1 0.779998 # miss rate for ReadReq accesses -system.l1subsys1.cache1.ReadReq_miss_rate::total 0.781645 # miss rate for ReadReq accesses -system.l1subsys1.cache1.WriteReq_miss_rate::l0subsys3.tester0 0.956119 # miss rate for WriteReq accesses -system.l1subsys1.cache1.WriteReq_miss_rate::l0subsys3.tester1 0.956012 # miss rate for WriteReq accesses -system.l1subsys1.cache1.WriteReq_miss_rate::total 0.956067 # miss rate for WriteReq accesses -system.l1subsys1.cache1.demand_miss_rate::l0subsys3.tester0 0.845187 # miss rate for demand accesses -system.l1subsys1.cache1.demand_miss_rate::l0subsys3.tester1 0.842867 # miss rate for demand accesses -system.l1subsys1.cache1.demand_miss_rate::total 0.844047 # miss rate for demand accesses -system.l1subsys1.cache1.overall_miss_rate::l0subsys3.tester0 0.845187 # miss rate for overall accesses -system.l1subsys1.cache1.overall_miss_rate::l0subsys3.tester1 0.842867 # miss rate for overall accesses -system.l1subsys1.cache1.overall_miss_rate::total 0.844047 # miss rate for overall accesses -system.l1subsys1.cache1.ReadReq_avg_miss_latency::l0subsys3.tester0 90497.408644 # average ReadReq miss latency -system.l1subsys1.cache1.ReadReq_avg_miss_latency::l0subsys3.tester1 90598.152614 # average ReadReq miss latency -system.l1subsys1.cache1.ReadReq_avg_miss_latency::total 90546.851337 # average ReadReq miss latency -system.l1subsys1.cache1.WriteReq_avg_miss_latency::l0subsys3.tester0 81749.697838 # average WriteReq miss latency -system.l1subsys1.cache1.WriteReq_avg_miss_latency::l0subsys3.tester1 82091.566561 # average WriteReq miss latency -system.l1subsys1.cache1.WriteReq_avg_miss_latency::total 81917.397869 # average WriteReq miss latency -system.l1subsys1.cache1.demand_avg_miss_latency::l0subsys3.tester0 86951.446187 # average overall miss latency -system.l1subsys1.cache1.demand_avg_miss_latency::l0subsys3.tester1 87151.871951 # average overall miss latency -system.l1subsys1.cache1.demand_avg_miss_latency::total 87049.791078 # average overall miss latency -system.l1subsys1.cache1.overall_avg_miss_latency::l0subsys3.tester0 86951.446187 # average overall miss latency -system.l1subsys1.cache1.overall_avg_miss_latency::l0subsys3.tester1 87151.871951 # average overall miss latency -system.l1subsys1.cache1.overall_avg_miss_latency::total 87049.791078 # average overall miss latency -system.l1subsys1.cache1.blocked_cycles::no_mshrs 234934 # number of cycles access was blocked +system.l1subsys1.cache1.ReadReq_hits::l0subsys3.tester0 8800 # number of ReadReq hits +system.l1subsys1.cache1.ReadReq_hits::l0subsys3.tester1 9171 # number of ReadReq hits +system.l1subsys1.cache1.ReadReq_hits::total 17971 # number of ReadReq hits +system.l1subsys1.cache1.WriteReq_hits::l0subsys3.tester0 1063 # number of WriteReq hits +system.l1subsys1.cache1.WriteReq_hits::l0subsys3.tester1 1139 # number of WriteReq hits +system.l1subsys1.cache1.WriteReq_hits::total 2202 # number of WriteReq hits +system.l1subsys1.cache1.demand_hits::l0subsys3.tester0 9863 # number of demand (read+write) hits +system.l1subsys1.cache1.demand_hits::l0subsys3.tester1 10310 # number of demand (read+write) hits +system.l1subsys1.cache1.demand_hits::total 20173 # number of demand (read+write) hits +system.l1subsys1.cache1.overall_hits::l0subsys3.tester0 9863 # number of overall hits +system.l1subsys1.cache1.overall_hits::l0subsys3.tester1 10310 # number of overall hits +system.l1subsys1.cache1.overall_hits::total 20173 # number of overall hits +system.l1subsys1.cache1.ReadReq_misses::l0subsys3.tester0 33078 # number of ReadReq misses +system.l1subsys1.cache1.ReadReq_misses::l0subsys3.tester1 32783 # number of ReadReq misses +system.l1subsys1.cache1.ReadReq_misses::total 65861 # number of ReadReq misses +system.l1subsys1.cache1.WriteReq_misses::l0subsys3.tester0 22069 # number of WriteReq misses +system.l1subsys1.cache1.WriteReq_misses::l0subsys3.tester1 22457 # number of WriteReq misses +system.l1subsys1.cache1.WriteReq_misses::total 44526 # number of WriteReq misses +system.l1subsys1.cache1.demand_misses::l0subsys3.tester0 55147 # number of demand (read+write) misses +system.l1subsys1.cache1.demand_misses::l0subsys3.tester1 55240 # number of demand (read+write) misses +system.l1subsys1.cache1.demand_misses::total 110387 # number of demand (read+write) misses +system.l1subsys1.cache1.overall_misses::l0subsys3.tester0 55147 # number of overall misses +system.l1subsys1.cache1.overall_misses::l0subsys3.tester1 55240 # number of overall misses +system.l1subsys1.cache1.overall_misses::total 110387 # number of overall misses +system.l1subsys1.cache1.ReadReq_miss_latency::l0subsys3.tester0 2996863885 # number of ReadReq miss cycles +system.l1subsys1.cache1.ReadReq_miss_latency::l0subsys3.tester1 2917691560 # number of ReadReq miss cycles +system.l1subsys1.cache1.ReadReq_miss_latency::total 5914555445 # number of ReadReq miss cycles +system.l1subsys1.cache1.WriteReq_miss_latency::l0subsys3.tester0 1848193916 # number of WriteReq miss cycles +system.l1subsys1.cache1.WriteReq_miss_latency::l0subsys3.tester1 1820903145 # number of WriteReq miss cycles +system.l1subsys1.cache1.WriteReq_miss_latency::total 3669097061 # number of WriteReq miss cycles +system.l1subsys1.cache1.demand_miss_latency::l0subsys3.tester0 4845057801 # number of demand (read+write) miss cycles +system.l1subsys1.cache1.demand_miss_latency::l0subsys3.tester1 4738594705 # number of demand (read+write) miss cycles +system.l1subsys1.cache1.demand_miss_latency::total 9583652506 # number of demand (read+write) miss cycles +system.l1subsys1.cache1.overall_miss_latency::l0subsys3.tester0 4845057801 # number of overall miss cycles +system.l1subsys1.cache1.overall_miss_latency::l0subsys3.tester1 4738594705 # number of overall miss cycles +system.l1subsys1.cache1.overall_miss_latency::total 9583652506 # number of overall miss cycles +system.l1subsys1.cache1.ReadReq_accesses::l0subsys3.tester0 41878 # number of ReadReq accesses(hits+misses) +system.l1subsys1.cache1.ReadReq_accesses::l0subsys3.tester1 41954 # number of ReadReq accesses(hits+misses) +system.l1subsys1.cache1.ReadReq_accesses::total 83832 # number of ReadReq accesses(hits+misses) +system.l1subsys1.cache1.WriteReq_accesses::l0subsys3.tester0 23132 # number of WriteReq accesses(hits+misses) +system.l1subsys1.cache1.WriteReq_accesses::l0subsys3.tester1 23596 # number of WriteReq accesses(hits+misses) +system.l1subsys1.cache1.WriteReq_accesses::total 46728 # number of WriteReq accesses(hits+misses) +system.l1subsys1.cache1.demand_accesses::l0subsys3.tester0 65010 # number of demand (read+write) accesses +system.l1subsys1.cache1.demand_accesses::l0subsys3.tester1 65550 # number of demand (read+write) accesses +system.l1subsys1.cache1.demand_accesses::total 130560 # number of demand (read+write) accesses +system.l1subsys1.cache1.overall_accesses::l0subsys3.tester0 65010 # number of overall (read+write) accesses +system.l1subsys1.cache1.overall_accesses::l0subsys3.tester1 65550 # number of overall (read+write) accesses +system.l1subsys1.cache1.overall_accesses::total 130560 # number of overall (read+write) accesses +system.l1subsys1.cache1.ReadReq_miss_rate::l0subsys3.tester0 0.789866 # miss rate for ReadReq accesses +system.l1subsys1.cache1.ReadReq_miss_rate::l0subsys3.tester1 0.781403 # miss rate for ReadReq accesses +system.l1subsys1.cache1.ReadReq_miss_rate::total 0.785631 # miss rate for ReadReq accesses +system.l1subsys1.cache1.WriteReq_miss_rate::l0subsys3.tester0 0.954046 # miss rate for WriteReq accesses +system.l1subsys1.cache1.WriteReq_miss_rate::l0subsys3.tester1 0.951729 # miss rate for WriteReq accesses +system.l1subsys1.cache1.WriteReq_miss_rate::total 0.952876 # miss rate for WriteReq accesses +system.l1subsys1.cache1.demand_miss_rate::l0subsys3.tester0 0.848285 # miss rate for demand accesses +system.l1subsys1.cache1.demand_miss_rate::l0subsys3.tester1 0.842715 # miss rate for demand accesses +system.l1subsys1.cache1.demand_miss_rate::total 0.845489 # miss rate for demand accesses +system.l1subsys1.cache1.overall_miss_rate::l0subsys3.tester0 0.848285 # miss rate for overall accesses +system.l1subsys1.cache1.overall_miss_rate::l0subsys3.tester1 0.842715 # miss rate for overall accesses +system.l1subsys1.cache1.overall_miss_rate::total 0.845489 # miss rate for overall accesses +system.l1subsys1.cache1.ReadReq_avg_miss_latency::l0subsys3.tester0 90599.911875 # average ReadReq miss latency +system.l1subsys1.cache1.ReadReq_avg_miss_latency::l0subsys3.tester1 89000.139096 # average ReadReq miss latency +system.l1subsys1.cache1.ReadReq_avg_miss_latency::total 89803.608281 # average ReadReq miss latency +system.l1subsys1.cache1.WriteReq_avg_miss_latency::l0subsys3.tester0 83746.155965 # average WriteReq miss latency +system.l1subsys1.cache1.WriteReq_avg_miss_latency::l0subsys3.tester1 81083.989179 # average WriteReq miss latency +system.l1subsys1.cache1.WriteReq_avg_miss_latency::total 82403.473499 # average WriteReq miss latency +system.l1subsys1.cache1.demand_avg_miss_latency::l0subsys3.tester0 87857.141839 # average overall miss latency +system.l1subsys1.cache1.demand_avg_miss_latency::l0subsys3.tester1 85781.946144 # average overall miss latency +system.l1subsys1.cache1.demand_avg_miss_latency::total 86818.669825 # average overall miss latency +system.l1subsys1.cache1.overall_avg_miss_latency::l0subsys3.tester0 87857.141839 # average overall miss latency +system.l1subsys1.cache1.overall_avg_miss_latency::l0subsys3.tester1 85781.946144 # average overall miss latency +system.l1subsys1.cache1.overall_avg_miss_latency::total 86818.669825 # average overall miss latency +system.l1subsys1.cache1.blocked_cycles::no_mshrs 248811 # number of cycles access was blocked system.l1subsys1.cache1.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l1subsys1.cache1.blocked::no_mshrs 7262 # number of cycles access was blocked +system.l1subsys1.cache1.blocked::no_mshrs 7700 # number of cycles access was blocked system.l1subsys1.cache1.blocked::no_targets 0 # number of cycles access was blocked -system.l1subsys1.cache1.avg_blocked_cycles::no_mshrs 32.351143 # average number of cycles each access was blocked +system.l1subsys1.cache1.avg_blocked_cycles::no_mshrs 32.313117 # average number of cycles each access was blocked system.l1subsys1.cache1.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.l1subsys1.cache1.writebacks::writebacks 22786 # number of writebacks -system.l1subsys1.cache1.writebacks::total 22786 # number of writebacks -system.l1subsys1.cache1.ReadReq_mshr_hits::l0subsys3.tester0 1232 # number of ReadReq MSHR hits -system.l1subsys1.cache1.ReadReq_mshr_hits::l0subsys3.tester1 1248 # number of ReadReq MSHR hits -system.l1subsys1.cache1.ReadReq_mshr_hits::total 2480 # number of ReadReq MSHR hits -system.l1subsys1.cache1.WriteReq_mshr_hits::l0subsys3.tester0 756 # number of WriteReq MSHR hits -system.l1subsys1.cache1.WriteReq_mshr_hits::l0subsys3.tester1 697 # number of WriteReq MSHR hits -system.l1subsys1.cache1.WriteReq_mshr_hits::total 1453 # number of WriteReq MSHR hits -system.l1subsys1.cache1.demand_mshr_hits::l0subsys3.tester0 1988 # number of demand (read+write) MSHR hits -system.l1subsys1.cache1.demand_mshr_hits::l0subsys3.tester1 1945 # number of demand (read+write) MSHR hits -system.l1subsys1.cache1.demand_mshr_hits::total 3933 # number of demand (read+write) MSHR hits -system.l1subsys1.cache1.overall_mshr_hits::l0subsys3.tester0 1988 # number of overall MSHR hits -system.l1subsys1.cache1.overall_mshr_hits::l0subsys3.tester1 1945 # number of overall MSHR hits -system.l1subsys1.cache1.overall_mshr_hits::total 3933 # number of overall MSHR hits -system.l1subsys1.cache1.ReadReq_mshr_misses::l0subsys3.tester0 31946 # number of ReadReq MSHR misses -system.l1subsys1.cache1.ReadReq_mshr_misses::l0subsys3.tester1 30728 # number of ReadReq MSHR misses -system.l1subsys1.cache1.ReadReq_mshr_misses::total 62674 # number of ReadReq MSHR misses -system.l1subsys1.cache1.WriteReq_mshr_misses::l0subsys3.tester0 21861 # number of WriteReq MSHR misses -system.l1subsys1.cache1.WriteReq_mshr_misses::l0subsys3.tester1 21080 # number of WriteReq MSHR misses -system.l1subsys1.cache1.WriteReq_mshr_misses::total 42941 # number of WriteReq MSHR misses -system.l1subsys1.cache1.demand_mshr_misses::l0subsys3.tester0 53807 # number of demand (read+write) MSHR misses -system.l1subsys1.cache1.demand_mshr_misses::l0subsys3.tester1 51808 # number of demand (read+write) MSHR misses -system.l1subsys1.cache1.demand_mshr_misses::total 105615 # number of demand (read+write) MSHR misses -system.l1subsys1.cache1.overall_mshr_misses::l0subsys3.tester0 53807 # number of overall MSHR misses -system.l1subsys1.cache1.overall_mshr_misses::l0subsys3.tester1 51808 # number of overall MSHR misses -system.l1subsys1.cache1.overall_mshr_misses::total 105615 # number of overall MSHR misses -system.l1subsys1.cache1.ReadReq_mshr_miss_latency::l0subsys3.tester0 2943009333 # number of ReadReq MSHR miss cycles -system.l1subsys1.cache1.ReadReq_mshr_miss_latency::l0subsys3.tester1 2838633361 # number of ReadReq MSHR miss cycles -system.l1subsys1.cache1.ReadReq_mshr_miss_latency::total 5781642694 # number of ReadReq MSHR miss cycles -system.l1subsys1.cache1.WriteReq_mshr_miss_latency::l0subsys3.tester0 1816893974 # number of WriteReq MSHR miss cycles -system.l1subsys1.cache1.WriteReq_mshr_miss_latency::l0subsys3.tester1 1757317060 # number of WriteReq MSHR miss cycles -system.l1subsys1.cache1.WriteReq_mshr_miss_latency::total 3574211034 # number of WriteReq MSHR miss cycles -system.l1subsys1.cache1.demand_mshr_miss_latency::l0subsys3.tester0 4759903307 # number of demand (read+write) MSHR miss cycles -system.l1subsys1.cache1.demand_mshr_miss_latency::l0subsys3.tester1 4595950421 # number of demand (read+write) MSHR miss cycles -system.l1subsys1.cache1.demand_mshr_miss_latency::total 9355853728 # number of demand (read+write) MSHR miss cycles -system.l1subsys1.cache1.overall_mshr_miss_latency::l0subsys3.tester0 4759903307 # number of overall MSHR miss cycles -system.l1subsys1.cache1.overall_mshr_miss_latency::l0subsys3.tester1 4595950421 # number of overall MSHR miss cycles -system.l1subsys1.cache1.overall_mshr_miss_latency::total 9355853728 # number of overall MSHR miss cycles -system.l1subsys1.cache1.ReadReq_mshr_miss_rate::l0subsys3.tester0 0.754155 # mshr miss rate for ReadReq accesses -system.l1subsys1.cache1.ReadReq_mshr_miss_rate::l0subsys3.tester1 0.749555 # mshr miss rate for ReadReq accesses -system.l1subsys1.cache1.ReadReq_mshr_miss_rate::total 0.751893 # mshr miss rate for ReadReq accesses -system.l1subsys1.cache1.WriteReq_mshr_miss_rate::l0subsys3.tester0 0.924160 # mshr miss rate for WriteReq accesses -system.l1subsys1.cache1.WriteReq_mshr_miss_rate::l0subsys3.tester1 0.925414 # mshr miss rate for WriteReq accesses -system.l1subsys1.cache1.WriteReq_mshr_miss_rate::total 0.924775 # mshr miss rate for WriteReq accesses -system.l1subsys1.cache1.demand_mshr_miss_rate::l0subsys3.tester0 0.815072 # mshr miss rate for demand accesses -system.l1subsys1.cache1.demand_mshr_miss_rate::l0subsys3.tester1 0.812369 # mshr miss rate for demand accesses -system.l1subsys1.cache1.demand_mshr_miss_rate::total 0.813744 # mshr miss rate for demand accesses -system.l1subsys1.cache1.overall_mshr_miss_rate::l0subsys3.tester0 0.815072 # mshr miss rate for overall accesses -system.l1subsys1.cache1.overall_mshr_miss_rate::l0subsys3.tester1 0.812369 # mshr miss rate for overall accesses -system.l1subsys1.cache1.overall_mshr_miss_rate::total 0.813744 # mshr miss rate for overall accesses -system.l1subsys1.cache1.ReadReq_avg_mshr_miss_latency::l0subsys3.tester0 92124.501753 # average ReadReq mshr miss latency -system.l1subsys1.cache1.ReadReq_avg_mshr_miss_latency::l0subsys3.tester1 92379.372592 # average ReadReq mshr miss latency -system.l1subsys1.cache1.ReadReq_avg_mshr_miss_latency::total 92249.460606 # average ReadReq mshr miss latency -system.l1subsys1.cache1.WriteReq_avg_mshr_miss_latency::l0subsys3.tester0 83111.201409 # average WriteReq mshr miss latency -system.l1subsys1.cache1.WriteReq_avg_mshr_miss_latency::l0subsys3.tester1 83364.186907 # average WriteReq mshr miss latency -system.l1subsys1.cache1.WriteReq_avg_mshr_miss_latency::total 83235.393540 # average WriteReq mshr miss latency -system.l1subsys1.cache1.demand_avg_mshr_miss_latency::l0subsys3.tester0 88462.529169 # average overall mshr miss latency -system.l1subsys1.cache1.demand_avg_mshr_miss_latency::l0subsys3.tester1 88711.211029 # average overall mshr miss latency -system.l1subsys1.cache1.demand_avg_mshr_miss_latency::total 88584.516669 # average overall mshr miss latency -system.l1subsys1.cache1.overall_avg_mshr_miss_latency::l0subsys3.tester0 88462.529169 # average overall mshr miss latency -system.l1subsys1.cache1.overall_avg_mshr_miss_latency::l0subsys3.tester1 88711.211029 # average overall mshr miss latency -system.l1subsys1.cache1.overall_avg_mshr_miss_latency::total 88584.516669 # average overall mshr miss latency -system.l1subsys1.xbar.snoop_filter.tot_requests 339288 # Total number of requests made to the snoop filter. -system.l1subsys1.xbar.snoop_filter.hit_single_requests 160503 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.l1subsys1.xbar.snoop_filter.hit_multi_requests 8795 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.l1subsys1.xbar.snoop_filter.tot_snoops 114270 # Total number of snoops made to the snoop filter. -system.l1subsys1.xbar.snoop_filter.hit_single_snoops 97861 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.l1subsys1.xbar.snoop_filter.hit_multi_snoops 16409 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.l1subsys1.cache1.writebacks::writebacks 23111 # number of writebacks +system.l1subsys1.cache1.writebacks::total 23111 # number of writebacks +system.l1subsys1.cache1.ReadReq_mshr_hits::l0subsys3.tester0 1265 # number of ReadReq MSHR hits +system.l1subsys1.cache1.ReadReq_mshr_hits::l0subsys3.tester1 1191 # number of ReadReq MSHR hits +system.l1subsys1.cache1.ReadReq_mshr_hits::total 2456 # number of ReadReq MSHR hits +system.l1subsys1.cache1.WriteReq_mshr_hits::l0subsys3.tester0 636 # number of WriteReq MSHR hits +system.l1subsys1.cache1.WriteReq_mshr_hits::l0subsys3.tester1 652 # number of WriteReq MSHR hits +system.l1subsys1.cache1.WriteReq_mshr_hits::total 1288 # number of WriteReq MSHR hits +system.l1subsys1.cache1.demand_mshr_hits::l0subsys3.tester0 1901 # number of demand (read+write) MSHR hits +system.l1subsys1.cache1.demand_mshr_hits::l0subsys3.tester1 1843 # number of demand (read+write) MSHR hits +system.l1subsys1.cache1.demand_mshr_hits::total 3744 # number of demand (read+write) MSHR hits +system.l1subsys1.cache1.overall_mshr_hits::l0subsys3.tester0 1901 # number of overall MSHR hits +system.l1subsys1.cache1.overall_mshr_hits::l0subsys3.tester1 1843 # number of overall MSHR hits +system.l1subsys1.cache1.overall_mshr_hits::total 3744 # number of overall MSHR hits +system.l1subsys1.cache1.ReadReq_mshr_misses::l0subsys3.tester0 31813 # number of ReadReq MSHR misses +system.l1subsys1.cache1.ReadReq_mshr_misses::l0subsys3.tester1 31592 # number of ReadReq MSHR misses +system.l1subsys1.cache1.ReadReq_mshr_misses::total 63405 # number of ReadReq MSHR misses +system.l1subsys1.cache1.WriteReq_mshr_misses::l0subsys3.tester0 21433 # number of WriteReq MSHR misses +system.l1subsys1.cache1.WriteReq_mshr_misses::l0subsys3.tester1 21805 # number of WriteReq MSHR misses +system.l1subsys1.cache1.WriteReq_mshr_misses::total 43238 # number of WriteReq MSHR misses +system.l1subsys1.cache1.demand_mshr_misses::l0subsys3.tester0 53246 # number of demand (read+write) MSHR misses +system.l1subsys1.cache1.demand_mshr_misses::l0subsys3.tester1 53397 # number of demand (read+write) MSHR misses +system.l1subsys1.cache1.demand_mshr_misses::total 106643 # number of demand (read+write) MSHR misses +system.l1subsys1.cache1.overall_mshr_misses::l0subsys3.tester0 53246 # number of overall MSHR misses +system.l1subsys1.cache1.overall_mshr_misses::l0subsys3.tester1 53397 # number of overall MSHR misses +system.l1subsys1.cache1.overall_mshr_misses::total 106643 # number of overall MSHR misses +system.l1subsys1.cache1.ReadReq_mshr_miss_latency::l0subsys3.tester0 2936678534 # number of ReadReq MSHR miss cycles +system.l1subsys1.cache1.ReadReq_mshr_miss_latency::l0subsys3.tester1 2859058481 # number of ReadReq MSHR miss cycles +system.l1subsys1.cache1.ReadReq_mshr_miss_latency::total 5795737015 # number of ReadReq MSHR miss cycles +system.l1subsys1.cache1.WriteReq_mshr_miss_latency::l0subsys3.tester0 1817912539 # number of WriteReq MSHR miss cycles +system.l1subsys1.cache1.WriteReq_mshr_miss_latency::l0subsys3.tester1 1790790455 # number of WriteReq MSHR miss cycles +system.l1subsys1.cache1.WriteReq_mshr_miss_latency::total 3608702994 # number of WriteReq MSHR miss cycles +system.l1subsys1.cache1.demand_mshr_miss_latency::l0subsys3.tester0 4754591073 # number of demand (read+write) MSHR miss cycles +system.l1subsys1.cache1.demand_mshr_miss_latency::l0subsys3.tester1 4649848936 # number of demand (read+write) MSHR miss cycles +system.l1subsys1.cache1.demand_mshr_miss_latency::total 9404440009 # number of demand (read+write) MSHR miss cycles +system.l1subsys1.cache1.overall_mshr_miss_latency::l0subsys3.tester0 4754591073 # number of overall MSHR miss cycles +system.l1subsys1.cache1.overall_mshr_miss_latency::l0subsys3.tester1 4649848936 # number of overall MSHR miss cycles +system.l1subsys1.cache1.overall_mshr_miss_latency::total 9404440009 # number of overall MSHR miss cycles +system.l1subsys1.cache1.ReadReq_mshr_miss_rate::l0subsys3.tester0 0.759659 # mshr miss rate for ReadReq accesses +system.l1subsys1.cache1.ReadReq_mshr_miss_rate::l0subsys3.tester1 0.753015 # mshr miss rate for ReadReq accesses +system.l1subsys1.cache1.ReadReq_mshr_miss_rate::total 0.756334 # mshr miss rate for ReadReq accesses +system.l1subsys1.cache1.WriteReq_mshr_miss_rate::l0subsys3.tester0 0.926552 # mshr miss rate for WriteReq accesses +system.l1subsys1.cache1.WriteReq_mshr_miss_rate::l0subsys3.tester1 0.924097 # mshr miss rate for WriteReq accesses +system.l1subsys1.cache1.WriteReq_mshr_miss_rate::total 0.925312 # mshr miss rate for WriteReq accesses +system.l1subsys1.cache1.demand_mshr_miss_rate::l0subsys3.tester0 0.819043 # mshr miss rate for demand accesses +system.l1subsys1.cache1.demand_mshr_miss_rate::l0subsys3.tester1 0.814600 # mshr miss rate for demand accesses +system.l1subsys1.cache1.demand_mshr_miss_rate::total 0.816812 # mshr miss rate for demand accesses +system.l1subsys1.cache1.overall_mshr_miss_rate::l0subsys3.tester0 0.819043 # mshr miss rate for overall accesses +system.l1subsys1.cache1.overall_mshr_miss_rate::l0subsys3.tester1 0.814600 # mshr miss rate for overall accesses +system.l1subsys1.cache1.overall_mshr_miss_rate::total 0.816812 # mshr miss rate for overall accesses +system.l1subsys1.cache1.ReadReq_avg_mshr_miss_latency::l0subsys3.tester0 92310.644516 # average ReadReq mshr miss latency +system.l1subsys1.cache1.ReadReq_avg_mshr_miss_latency::l0subsys3.tester1 90499.445461 # average ReadReq mshr miss latency +system.l1subsys1.cache1.ReadReq_avg_mshr_miss_latency::total 91408.201483 # average ReadReq mshr miss latency +system.l1subsys1.cache1.WriteReq_avg_mshr_miss_latency::l0subsys3.tester0 84818.389353 # average WriteReq mshr miss latency +system.l1subsys1.cache1.WriteReq_avg_mshr_miss_latency::l0subsys3.tester1 82127.514561 # average WriteReq mshr miss latency +system.l1subsys1.cache1.WriteReq_avg_mshr_miss_latency::total 83461.376428 # average WriteReq mshr miss latency +system.l1subsys1.cache1.demand_avg_mshr_miss_latency::l0subsys3.tester0 89294.802858 # average overall mshr miss latency +system.l1subsys1.cache1.demand_avg_mshr_miss_latency::l0subsys3.tester1 87080.714947 # average overall mshr miss latency +system.l1subsys1.cache1.demand_avg_mshr_miss_latency::total 88186.191396 # average overall mshr miss latency +system.l1subsys1.cache1.overall_avg_mshr_miss_latency::l0subsys3.tester0 89294.802858 # average overall mshr miss latency +system.l1subsys1.cache1.overall_avg_mshr_miss_latency::l0subsys3.tester1 87080.714947 # average overall mshr miss latency +system.l1subsys1.cache1.overall_avg_mshr_miss_latency::total 88186.191396 # average overall mshr miss latency +system.l1subsys1.xbar.snoop_filter.tot_requests 340971 # Total number of requests made to the snoop filter. +system.l1subsys1.xbar.snoop_filter.hit_single_requests 160937 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.l1subsys1.xbar.snoop_filter.hit_multi_requests 9094 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.l1subsys1.xbar.snoop_filter.tot_snoops 156359 # Total number of snoops made to the snoop filter. +system.l1subsys1.xbar.snoop_filter.hit_single_snoops 137796 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.l1subsys1.xbar.snoop_filter.hit_multi_snoops 18563 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.l1subsys1.xbar.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states -system.l1subsys1.xbar.trans_dist::ReadResp 151000 # Transaction distribution -system.l1subsys1.xbar.trans_dist::ReadRespWithInvalidate 3767 # Transaction distribution -system.l1subsys1.xbar.trans_dist::WritebackDirty 90510 # Transaction distribution -system.l1subsys1.xbar.trans_dist::CleanEvict 163308 # Transaction distribution -system.l1subsys1.xbar.trans_dist::UpgradeReq 39129 # Transaction distribution -system.l1subsys1.xbar.trans_dist::UpgradeResp 23998 # Transaction distribution -system.l1subsys1.xbar.trans_dist::ReadExReq 98068 # Transaction distribution -system.l1subsys1.xbar.trans_dist::ReadExResp 90220 # Transaction distribution -system.l1subsys1.xbar.trans_dist::ReadSharedReq 164629 # Transaction distribution -system.l1subsys1.xbar.pkt_count_system.l1subsys1.cache0.mem_side::system.l2subsys0.cache2.cpu_side 294526 # Packet count per connected master and slave (bytes) -system.l1subsys1.xbar.pkt_count_system.l1subsys1.cache1.mem_side::system.l2subsys0.cache2.cpu_side 298625 # Packet count per connected master and slave (bytes) -system.l1subsys1.xbar.pkt_count::total 593151 # Packet count per connected master and slave (bytes) -system.l1subsys1.xbar.pkt_size_system.l1subsys1.cache0.mem_side::system.l2subsys0.cache2.cpu_side 8784576 # Cumulative packet size per connected master and slave (bytes) -system.l1subsys1.xbar.pkt_size_system.l1subsys1.cache1.mem_side::system.l2subsys0.cache2.cpu_side 8958272 # Cumulative packet size per connected master and slave (bytes) -system.l1subsys1.xbar.pkt_size::total 17742848 # Cumulative packet size per connected master and slave (bytes) -system.l1subsys1.xbar.snoops 288962 # Total snoops (count) -system.l1subsys1.xbar.snoopTraffic 6862464 # Total snoop traffic (bytes) -system.l1subsys1.xbar.snoop_fanout::samples 427858 # Request fanout histogram -system.l1subsys1.xbar.snoop_fanout::mean 0.369602 # Request fanout histogram -system.l1subsys1.xbar.snoop_fanout::stdev 0.556507 # Request fanout histogram +system.l1subsys1.xbar.trans_dist::ReadResp 153671 # Transaction distribution +system.l1subsys1.xbar.trans_dist::ReadRespWithInvalidate 4438 # Transaction distribution +system.l1subsys1.xbar.trans_dist::WritebackDirty 90488 # Transaction distribution +system.l1subsys1.xbar.trans_dist::CleanEvict 185296 # Transaction distribution +system.l1subsys1.xbar.trans_dist::UpgradeReq 38860 # Transaction distribution +system.l1subsys1.xbar.trans_dist::UpgradeResp 23637 # Transaction distribution +system.l1subsys1.xbar.trans_dist::ReadExReq 102525 # Transaction distribution +system.l1subsys1.xbar.trans_dist::ReadExResp 93076 # Transaction distribution +system.l1subsys1.xbar.trans_dist::ReadSharedReq 169429 # Transaction distribution +system.l1subsys1.xbar.pkt_count_system.l1subsys1.cache0.mem_side::system.l2subsys0.cache2.cpu_side 299650 # Packet count per connected master and slave (bytes) +system.l1subsys1.xbar.pkt_count_system.l1subsys1.cache1.mem_side::system.l2subsys0.cache2.cpu_side 300840 # Packet count per connected master and slave (bytes) +system.l1subsys1.xbar.pkt_count::total 600490 # Packet count per connected master and slave (bytes) +system.l1subsys1.xbar.pkt_size_system.l1subsys1.cache0.mem_side::system.l2subsys0.cache2.cpu_side 9042560 # Cumulative packet size per connected master and slave (bytes) +system.l1subsys1.xbar.pkt_size_system.l1subsys1.cache1.mem_side::system.l2subsys0.cache2.cpu_side 9075776 # Cumulative packet size per connected master and slave (bytes) +system.l1subsys1.xbar.pkt_size::total 18118336 # Cumulative packet size per connected master and slave (bytes) +system.l1subsys1.xbar.snoops 321671 # Total snoops (count) +system.l1subsys1.xbar.snoopTraffic 7090944 # Total snoop traffic (bytes) +system.l1subsys1.xbar.snoop_fanout::samples 459710 # Request fanout histogram +system.l1subsys1.xbar.snoop_fanout::mean 0.443486 # Request fanout histogram +system.l1subsys1.xbar.snoop_fanout::stdev 0.572334 # Request fanout histogram system.l1subsys1.xbar.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.l1subsys1.xbar.snoop_fanout::0 286130 66.87% 66.87% # Request fanout histogram -system.l1subsys1.xbar.snoop_fanout::1 125319 29.29% 96.16% # Request fanout histogram -system.l1subsys1.xbar.snoop_fanout::2 16409 3.84% 100.00% # Request fanout histogram +system.l1subsys1.xbar.snoop_fanout::0 274398 59.69% 59.69% # Request fanout histogram +system.l1subsys1.xbar.snoop_fanout::1 166749 36.27% 95.96% # Request fanout histogram +system.l1subsys1.xbar.snoop_fanout::2 18563 4.04% 100.00% # Request fanout histogram system.l1subsys1.xbar.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.l1subsys1.xbar.snoop_fanout::min_value 0 # Request fanout histogram system.l1subsys1.xbar.snoop_fanout::max_value 2 # Request fanout histogram -system.l1subsys1.xbar.snoop_fanout::total 427858 # Request fanout histogram -system.l1subsys1.xbar.reqLayer0.occupancy 528036324 # Layer occupancy (ticks) +system.l1subsys1.xbar.snoop_fanout::total 459710 # Request fanout histogram +system.l1subsys1.xbar.reqLayer0.occupancy 530478299 # Layer occupancy (ticks) system.l1subsys1.xbar.reqLayer0.utilization 5.3 # Layer utilization (%) -system.l1subsys1.xbar.snoopLayer0.occupancy 174007827 # Layer occupancy (ticks) -system.l1subsys1.xbar.snoopLayer0.utilization 1.7 # Layer utilization (%) -system.l1subsys1.xbar.respLayer0.occupancy 305008955 # Layer occupancy (ticks) +system.l1subsys1.xbar.snoopLayer0.occupancy 184704449 # Layer occupancy (ticks) +system.l1subsys1.xbar.snoopLayer0.utilization 1.8 # Layer utilization (%) +system.l1subsys1.xbar.respLayer0.occupancy 310357504 # Layer occupancy (ticks) system.l1subsys1.xbar.respLayer0.utilization 3.1 # Layer utilization (%) -system.l1subsys1.xbar.respLayer1.occupancy 309946184 # Layer occupancy (ticks) +system.l1subsys1.xbar.respLayer1.occupancy 313853796 # Layer occupancy (ticks) system.l1subsys1.xbar.respLayer1.utilization 3.1 # Layer utilization (%) system.l1subsys2.cache0.tags.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states -system.l1subsys2.cache0.tags.replacements 65353 # number of replacements -system.l1subsys2.cache0.tags.tagsinuse 504.458871 # Cycle average of tags in use -system.l1subsys2.cache0.tags.total_refs 33188 # Total number of references to valid blocks. -system.l1subsys2.cache0.tags.sampled_refs 65858 # Sample count of references to valid blocks. -system.l1subsys2.cache0.tags.avg_refs 0.503933 # Average number of references to valid blocks. -system.l1subsys2.cache0.tags.warmup_cycle 466915000 # Cycle when the warmup percentage was hit. -system.l1subsys2.cache0.tags.occ_blocks::l0subsys4.tester0 261.436019 # Average occupied blocks per requestor -system.l1subsys2.cache0.tags.occ_blocks::l0subsys4.tester1 243.022852 # Average occupied blocks per requestor -system.l1subsys2.cache0.tags.occ_percent::l0subsys4.tester0 0.510617 # Average percentage of cache occupancy -system.l1subsys2.cache0.tags.occ_percent::l0subsys4.tester1 0.474654 # Average percentage of cache occupancy -system.l1subsys2.cache0.tags.occ_percent::total 0.985271 # Average percentage of cache occupancy -system.l1subsys2.cache0.tags.occ_task_id_blocks::1024 505 # Occupied blocks per task id -system.l1subsys2.cache0.tags.age_task_id_blocks_1024::0 21 # Occupied blocks per task id -system.l1subsys2.cache0.tags.age_task_id_blocks_1024::1 456 # Occupied blocks per task id -system.l1subsys2.cache0.tags.age_task_id_blocks_1024::2 28 # Occupied blocks per task id -system.l1subsys2.cache0.tags.occ_task_id_percent::1024 0.986328 # Percentage of cache occupancy per task id -system.l1subsys2.cache0.tags.tag_accesses 629863 # Number of tag accesses -system.l1subsys2.cache0.tags.data_accesses 629863 # Number of data accesses +system.l1subsys2.cache0.tags.replacements 66509 # number of replacements +system.l1subsys2.cache0.tags.tagsinuse 503.868093 # Cycle average of tags in use +system.l1subsys2.cache0.tags.total_refs 30279 # Total number of references to valid blocks. +system.l1subsys2.cache0.tags.sampled_refs 67016 # Sample count of references to valid blocks. +system.l1subsys2.cache0.tags.avg_refs 0.451817 # Average number of references to valid blocks. +system.l1subsys2.cache0.tags.warmup_cycle 829394000 # Cycle when the warmup percentage was hit. +system.l1subsys2.cache0.tags.occ_blocks::l0subsys4.tester0 256.450231 # Average occupied blocks per requestor +system.l1subsys2.cache0.tags.occ_blocks::l0subsys4.tester1 247.417862 # Average occupied blocks per requestor +system.l1subsys2.cache0.tags.occ_percent::l0subsys4.tester0 0.500879 # Average percentage of cache occupancy +system.l1subsys2.cache0.tags.occ_percent::l0subsys4.tester1 0.483238 # Average percentage of cache occupancy +system.l1subsys2.cache0.tags.occ_percent::total 0.984117 # Average percentage of cache occupancy +system.l1subsys2.cache0.tags.occ_task_id_blocks::1024 507 # Occupied blocks per task id +system.l1subsys2.cache0.tags.age_task_id_blocks_1024::0 97 # Occupied blocks per task id +system.l1subsys2.cache0.tags.age_task_id_blocks_1024::1 392 # Occupied blocks per task id +system.l1subsys2.cache0.tags.age_task_id_blocks_1024::2 18 # Occupied blocks per task id +system.l1subsys2.cache0.tags.occ_task_id_percent::1024 0.990234 # Percentage of cache occupancy per task id +system.l1subsys2.cache0.tags.tag_accesses 631189 # Number of tag accesses +system.l1subsys2.cache0.tags.data_accesses 631189 # Number of data accesses system.l1subsys2.cache0.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states -system.l1subsys2.cache0.ReadReq_hits::l0subsys4.tester0 10527 # number of ReadReq hits -system.l1subsys2.cache0.ReadReq_hits::l0subsys4.tester1 10271 # number of ReadReq hits -system.l1subsys2.cache0.ReadReq_hits::total 20798 # number of ReadReq hits -system.l1subsys2.cache0.WriteReq_hits::l0subsys4.tester0 1671 # number of WriteReq hits -system.l1subsys2.cache0.WriteReq_hits::l0subsys4.tester1 1543 # number of WriteReq hits -system.l1subsys2.cache0.WriteReq_hits::total 3214 # number of WriteReq hits -system.l1subsys2.cache0.demand_hits::l0subsys4.tester0 12198 # number of demand (read+write) hits -system.l1subsys2.cache0.demand_hits::l0subsys4.tester1 11814 # number of demand (read+write) hits -system.l1subsys2.cache0.demand_hits::total 24012 # number of demand (read+write) hits -system.l1subsys2.cache0.overall_hits::l0subsys4.tester0 12198 # number of overall hits -system.l1subsys2.cache0.overall_hits::l0subsys4.tester1 11814 # number of overall hits -system.l1subsys2.cache0.overall_hits::total 24012 # number of overall hits -system.l1subsys2.cache0.ReadReq_misses::l0subsys4.tester0 32645 # number of ReadReq misses -system.l1subsys2.cache0.ReadReq_misses::l0subsys4.tester1 32064 # number of ReadReq misses -system.l1subsys2.cache0.ReadReq_misses::total 64709 # number of ReadReq misses -system.l1subsys2.cache0.WriteReq_misses::l0subsys4.tester0 22341 # number of WriteReq misses -system.l1subsys2.cache0.WriteReq_misses::l0subsys4.tester1 21878 # number of WriteReq misses -system.l1subsys2.cache0.WriteReq_misses::total 44219 # number of WriteReq misses -system.l1subsys2.cache0.demand_misses::l0subsys4.tester0 54986 # number of demand (read+write) misses -system.l1subsys2.cache0.demand_misses::l0subsys4.tester1 53942 # number of demand (read+write) misses -system.l1subsys2.cache0.demand_misses::total 108928 # number of demand (read+write) misses -system.l1subsys2.cache0.overall_misses::l0subsys4.tester0 54986 # number of overall misses -system.l1subsys2.cache0.overall_misses::l0subsys4.tester1 53942 # number of overall misses -system.l1subsys2.cache0.overall_misses::total 108928 # number of overall misses -system.l1subsys2.cache0.ReadReq_miss_latency::l0subsys4.tester0 3071371580 # number of ReadReq miss cycles -system.l1subsys2.cache0.ReadReq_miss_latency::l0subsys4.tester1 2941118083 # number of ReadReq miss cycles -system.l1subsys2.cache0.ReadReq_miss_latency::total 6012489663 # number of ReadReq miss cycles -system.l1subsys2.cache0.WriteReq_miss_latency::l0subsys4.tester0 1903624532 # number of WriteReq miss cycles -system.l1subsys2.cache0.WriteReq_miss_latency::l0subsys4.tester1 1804246122 # number of WriteReq miss cycles -system.l1subsys2.cache0.WriteReq_miss_latency::total 3707870654 # number of WriteReq miss cycles -system.l1subsys2.cache0.demand_miss_latency::l0subsys4.tester0 4974996112 # number of demand (read+write) miss cycles -system.l1subsys2.cache0.demand_miss_latency::l0subsys4.tester1 4745364205 # number of demand (read+write) miss cycles -system.l1subsys2.cache0.demand_miss_latency::total 9720360317 # number of demand (read+write) miss cycles -system.l1subsys2.cache0.overall_miss_latency::l0subsys4.tester0 4974996112 # number of overall miss cycles -system.l1subsys2.cache0.overall_miss_latency::l0subsys4.tester1 4745364205 # number of overall miss cycles -system.l1subsys2.cache0.overall_miss_latency::total 9720360317 # number of overall miss cycles -system.l1subsys2.cache0.ReadReq_accesses::l0subsys4.tester0 43172 # number of ReadReq accesses(hits+misses) -system.l1subsys2.cache0.ReadReq_accesses::l0subsys4.tester1 42335 # number of ReadReq accesses(hits+misses) -system.l1subsys2.cache0.ReadReq_accesses::total 85507 # number of ReadReq accesses(hits+misses) -system.l1subsys2.cache0.WriteReq_accesses::l0subsys4.tester0 24012 # number of WriteReq accesses(hits+misses) -system.l1subsys2.cache0.WriteReq_accesses::l0subsys4.tester1 23421 # number of WriteReq accesses(hits+misses) -system.l1subsys2.cache0.WriteReq_accesses::total 47433 # number of WriteReq accesses(hits+misses) -system.l1subsys2.cache0.demand_accesses::l0subsys4.tester0 67184 # number of demand (read+write) accesses -system.l1subsys2.cache0.demand_accesses::l0subsys4.tester1 65756 # number of demand (read+write) accesses -system.l1subsys2.cache0.demand_accesses::total 132940 # number of demand (read+write) accesses -system.l1subsys2.cache0.overall_accesses::l0subsys4.tester0 67184 # number of overall (read+write) accesses -system.l1subsys2.cache0.overall_accesses::l0subsys4.tester1 65756 # number of overall (read+write) accesses -system.l1subsys2.cache0.overall_accesses::total 132940 # number of overall (read+write) accesses -system.l1subsys2.cache0.ReadReq_miss_rate::l0subsys4.tester0 0.756161 # miss rate for ReadReq accesses -system.l1subsys2.cache0.ReadReq_miss_rate::l0subsys4.tester1 0.757388 # miss rate for ReadReq accesses -system.l1subsys2.cache0.ReadReq_miss_rate::total 0.756768 # miss rate for ReadReq accesses -system.l1subsys2.cache0.WriteReq_miss_rate::l0subsys4.tester0 0.930410 # miss rate for WriteReq accesses -system.l1subsys2.cache0.WriteReq_miss_rate::l0subsys4.tester1 0.934119 # miss rate for WriteReq accesses -system.l1subsys2.cache0.WriteReq_miss_rate::total 0.932241 # miss rate for WriteReq accesses -system.l1subsys2.cache0.demand_miss_rate::l0subsys4.tester0 0.818439 # miss rate for demand accesses -system.l1subsys2.cache0.demand_miss_rate::l0subsys4.tester1 0.820336 # miss rate for demand accesses -system.l1subsys2.cache0.demand_miss_rate::total 0.819377 # miss rate for demand accesses -system.l1subsys2.cache0.overall_miss_rate::l0subsys4.tester0 0.818439 # miss rate for overall accesses -system.l1subsys2.cache0.overall_miss_rate::l0subsys4.tester1 0.820336 # miss rate for overall accesses -system.l1subsys2.cache0.overall_miss_rate::total 0.819377 # miss rate for overall accesses -system.l1subsys2.cache0.ReadReq_avg_miss_latency::l0subsys4.tester0 94083.981620 # average ReadReq miss latency -system.l1subsys2.cache0.ReadReq_avg_miss_latency::l0subsys4.tester1 91726.487120 # average ReadReq miss latency -system.l1subsys2.cache0.ReadReq_avg_miss_latency::total 92915.817939 # average ReadReq miss latency -system.l1subsys2.cache0.WriteReq_avg_miss_latency::l0subsys4.tester0 85207.668949 # average WriteReq miss latency -system.l1subsys2.cache0.WriteReq_avg_miss_latency::l0subsys4.tester1 82468.512753 # average WriteReq miss latency -system.l1subsys2.cache0.WriteReq_avg_miss_latency::total 83852.431172 # average WriteReq miss latency -system.l1subsys2.cache0.demand_avg_miss_latency::l0subsys4.tester0 90477.505401 # average overall miss latency -system.l1subsys2.cache0.demand_avg_miss_latency::l0subsys4.tester1 87971.602925 # average overall miss latency -system.l1subsys2.cache0.demand_avg_miss_latency::total 89236.562840 # average overall miss latency -system.l1subsys2.cache0.overall_avg_miss_latency::l0subsys4.tester0 90477.505401 # average overall miss latency -system.l1subsys2.cache0.overall_avg_miss_latency::l0subsys4.tester1 87971.602925 # average overall miss latency -system.l1subsys2.cache0.overall_avg_miss_latency::total 89236.562840 # average overall miss latency -system.l1subsys2.cache0.blocked_cycles::no_mshrs 258782 # number of cycles access was blocked +system.l1subsys2.cache0.ReadReq_hits::l0subsys4.tester0 10236 # number of ReadReq hits +system.l1subsys2.cache0.ReadReq_hits::l0subsys4.tester1 8788 # number of ReadReq hits +system.l1subsys2.cache0.ReadReq_hits::total 19024 # number of ReadReq hits +system.l1subsys2.cache0.WriteReq_hits::l0subsys4.tester0 1819 # number of WriteReq hits +system.l1subsys2.cache0.WriteReq_hits::l0subsys4.tester1 1004 # number of WriteReq hits +system.l1subsys2.cache0.WriteReq_hits::total 2823 # number of WriteReq hits +system.l1subsys2.cache0.demand_hits::l0subsys4.tester0 12055 # number of demand (read+write) hits +system.l1subsys2.cache0.demand_hits::l0subsys4.tester1 9792 # number of demand (read+write) hits +system.l1subsys2.cache0.demand_hits::total 21847 # number of demand (read+write) hits +system.l1subsys2.cache0.overall_hits::l0subsys4.tester0 12055 # number of overall hits +system.l1subsys2.cache0.overall_hits::l0subsys4.tester1 9792 # number of overall hits +system.l1subsys2.cache0.overall_hits::total 21847 # number of overall hits +system.l1subsys2.cache0.ReadReq_misses::l0subsys4.tester0 32304 # number of ReadReq misses +system.l1subsys2.cache0.ReadReq_misses::l0subsys4.tester1 34007 # number of ReadReq misses +system.l1subsys2.cache0.ReadReq_misses::total 66311 # number of ReadReq misses +system.l1subsys2.cache0.WriteReq_misses::l0subsys4.tester0 21653 # number of WriteReq misses +system.l1subsys2.cache0.WriteReq_misses::l0subsys4.tester1 22755 # number of WriteReq misses +system.l1subsys2.cache0.WriteReq_misses::total 44408 # number of WriteReq misses +system.l1subsys2.cache0.demand_misses::l0subsys4.tester0 53957 # number of demand (read+write) misses +system.l1subsys2.cache0.demand_misses::l0subsys4.tester1 56762 # number of demand (read+write) misses +system.l1subsys2.cache0.demand_misses::total 110719 # number of demand (read+write) misses +system.l1subsys2.cache0.overall_misses::l0subsys4.tester0 53957 # number of overall misses +system.l1subsys2.cache0.overall_misses::l0subsys4.tester1 56762 # number of overall misses +system.l1subsys2.cache0.overall_misses::total 110719 # number of overall misses +system.l1subsys2.cache0.ReadReq_miss_latency::l0subsys4.tester0 3033418520 # number of ReadReq miss cycles +system.l1subsys2.cache0.ReadReq_miss_latency::l0subsys4.tester1 3062242477 # number of ReadReq miss cycles +system.l1subsys2.cache0.ReadReq_miss_latency::total 6095660997 # number of ReadReq miss cycles +system.l1subsys2.cache0.WriteReq_miss_latency::l0subsys4.tester0 1821498988 # number of WriteReq miss cycles +system.l1subsys2.cache0.WriteReq_miss_latency::l0subsys4.tester1 1866435160 # number of WriteReq miss cycles +system.l1subsys2.cache0.WriteReq_miss_latency::total 3687934148 # number of WriteReq miss cycles +system.l1subsys2.cache0.demand_miss_latency::l0subsys4.tester0 4854917508 # number of demand (read+write) miss cycles +system.l1subsys2.cache0.demand_miss_latency::l0subsys4.tester1 4928677637 # number of demand (read+write) miss cycles +system.l1subsys2.cache0.demand_miss_latency::total 9783595145 # number of demand (read+write) miss cycles +system.l1subsys2.cache0.overall_miss_latency::l0subsys4.tester0 4854917508 # number of overall miss cycles +system.l1subsys2.cache0.overall_miss_latency::l0subsys4.tester1 4928677637 # number of overall miss cycles +system.l1subsys2.cache0.overall_miss_latency::total 9783595145 # number of overall miss cycles +system.l1subsys2.cache0.ReadReq_accesses::l0subsys4.tester0 42540 # number of ReadReq accesses(hits+misses) +system.l1subsys2.cache0.ReadReq_accesses::l0subsys4.tester1 42795 # number of ReadReq accesses(hits+misses) +system.l1subsys2.cache0.ReadReq_accesses::total 85335 # number of ReadReq accesses(hits+misses) +system.l1subsys2.cache0.WriteReq_accesses::l0subsys4.tester0 23472 # number of WriteReq accesses(hits+misses) +system.l1subsys2.cache0.WriteReq_accesses::l0subsys4.tester1 23759 # number of WriteReq accesses(hits+misses) +system.l1subsys2.cache0.WriteReq_accesses::total 47231 # number of WriteReq accesses(hits+misses) +system.l1subsys2.cache0.demand_accesses::l0subsys4.tester0 66012 # number of demand (read+write) accesses +system.l1subsys2.cache0.demand_accesses::l0subsys4.tester1 66554 # number of demand (read+write) accesses +system.l1subsys2.cache0.demand_accesses::total 132566 # number of demand (read+write) accesses +system.l1subsys2.cache0.overall_accesses::l0subsys4.tester0 66012 # number of overall (read+write) accesses +system.l1subsys2.cache0.overall_accesses::l0subsys4.tester1 66554 # number of overall (read+write) accesses +system.l1subsys2.cache0.overall_accesses::total 132566 # number of overall (read+write) accesses +system.l1subsys2.cache0.ReadReq_miss_rate::l0subsys4.tester0 0.759379 # miss rate for ReadReq accesses +system.l1subsys2.cache0.ReadReq_miss_rate::l0subsys4.tester1 0.794649 # miss rate for ReadReq accesses +system.l1subsys2.cache0.ReadReq_miss_rate::total 0.777067 # miss rate for ReadReq accesses +system.l1subsys2.cache0.WriteReq_miss_rate::l0subsys4.tester0 0.922503 # miss rate for WriteReq accesses +system.l1subsys2.cache0.WriteReq_miss_rate::l0subsys4.tester1 0.957742 # miss rate for WriteReq accesses +system.l1subsys2.cache0.WriteReq_miss_rate::total 0.940230 # miss rate for WriteReq accesses +system.l1subsys2.cache0.demand_miss_rate::l0subsys4.tester0 0.817382 # miss rate for demand accesses +system.l1subsys2.cache0.demand_miss_rate::l0subsys4.tester1 0.852871 # miss rate for demand accesses +system.l1subsys2.cache0.demand_miss_rate::total 0.835199 # miss rate for demand accesses +system.l1subsys2.cache0.overall_miss_rate::l0subsys4.tester0 0.817382 # miss rate for overall accesses +system.l1subsys2.cache0.overall_miss_rate::l0subsys4.tester1 0.852871 # miss rate for overall accesses +system.l1subsys2.cache0.overall_miss_rate::total 0.835199 # miss rate for overall accesses +system.l1subsys2.cache0.ReadReq_avg_miss_latency::l0subsys4.tester0 93902.257306 # average ReadReq miss latency +system.l1subsys2.cache0.ReadReq_avg_miss_latency::l0subsys4.tester1 90047.416032 # average ReadReq miss latency +system.l1subsys2.cache0.ReadReq_avg_miss_latency::total 91925.336626 # average ReadReq miss latency +system.l1subsys2.cache0.WriteReq_avg_miss_latency::l0subsys4.tester0 84122.245786 # average WriteReq miss latency +system.l1subsys2.cache0.WriteReq_avg_miss_latency::l0subsys4.tester1 82023.078884 # average WriteReq miss latency +system.l1subsys2.cache0.WriteReq_avg_miss_latency::total 83046.616556 # average WriteReq miss latency +system.l1subsys2.cache0.demand_avg_miss_latency::l0subsys4.tester0 89977.528551 # average overall miss latency +system.l1subsys2.cache0.demand_avg_miss_latency::l0subsys4.tester1 86830.584493 # average overall miss latency +system.l1subsys2.cache0.demand_avg_miss_latency::total 88364.193544 # average overall miss latency +system.l1subsys2.cache0.overall_avg_miss_latency::l0subsys4.tester0 89977.528551 # average overall miss latency +system.l1subsys2.cache0.overall_avg_miss_latency::l0subsys4.tester1 86830.584493 # average overall miss latency +system.l1subsys2.cache0.overall_avg_miss_latency::total 88364.193544 # average overall miss latency +system.l1subsys2.cache0.blocked_cycles::no_mshrs 263390 # number of cycles access was blocked system.l1subsys2.cache0.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l1subsys2.cache0.blocked::no_mshrs 7946 # number of cycles access was blocked +system.l1subsys2.cache0.blocked::no_mshrs 8190 # number of cycles access was blocked system.l1subsys2.cache0.blocked::no_targets 0 # number of cycles access was blocked -system.l1subsys2.cache0.avg_blocked_cycles::no_mshrs 32.567581 # average number of cycles each access was blocked +system.l1subsys2.cache0.avg_blocked_cycles::no_mshrs 32.159951 # average number of cycles each access was blocked system.l1subsys2.cache0.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.l1subsys2.cache0.writebacks::writebacks 23544 # number of writebacks -system.l1subsys2.cache0.writebacks::total 23544 # number of writebacks -system.l1subsys2.cache0.ReadReq_mshr_hits::l0subsys4.tester0 1133 # number of ReadReq MSHR hits -system.l1subsys2.cache0.ReadReq_mshr_hits::l0subsys4.tester1 1138 # number of ReadReq MSHR hits -system.l1subsys2.cache0.ReadReq_mshr_hits::total 2271 # number of ReadReq MSHR hits -system.l1subsys2.cache0.WriteReq_mshr_hits::l0subsys4.tester0 612 # number of WriteReq MSHR hits -system.l1subsys2.cache0.WriteReq_mshr_hits::l0subsys4.tester1 631 # number of WriteReq MSHR hits -system.l1subsys2.cache0.WriteReq_mshr_hits::total 1243 # number of WriteReq MSHR hits -system.l1subsys2.cache0.demand_mshr_hits::l0subsys4.tester0 1745 # number of demand (read+write) MSHR hits -system.l1subsys2.cache0.demand_mshr_hits::l0subsys4.tester1 1769 # number of demand (read+write) MSHR hits -system.l1subsys2.cache0.demand_mshr_hits::total 3514 # number of demand (read+write) MSHR hits -system.l1subsys2.cache0.overall_mshr_hits::l0subsys4.tester0 1745 # number of overall MSHR hits -system.l1subsys2.cache0.overall_mshr_hits::l0subsys4.tester1 1769 # number of overall MSHR hits -system.l1subsys2.cache0.overall_mshr_hits::total 3514 # number of overall MSHR hits -system.l1subsys2.cache0.ReadReq_mshr_misses::l0subsys4.tester0 31512 # number of ReadReq MSHR misses -system.l1subsys2.cache0.ReadReq_mshr_misses::l0subsys4.tester1 30926 # number of ReadReq MSHR misses -system.l1subsys2.cache0.ReadReq_mshr_misses::total 62438 # number of ReadReq MSHR misses -system.l1subsys2.cache0.WriteReq_mshr_misses::l0subsys4.tester0 21729 # number of WriteReq MSHR misses -system.l1subsys2.cache0.WriteReq_mshr_misses::l0subsys4.tester1 21247 # number of WriteReq MSHR misses -system.l1subsys2.cache0.WriteReq_mshr_misses::total 42976 # number of WriteReq MSHR misses -system.l1subsys2.cache0.demand_mshr_misses::l0subsys4.tester0 53241 # number of demand (read+write) MSHR misses -system.l1subsys2.cache0.demand_mshr_misses::l0subsys4.tester1 52173 # number of demand (read+write) MSHR misses -system.l1subsys2.cache0.demand_mshr_misses::total 105414 # number of demand (read+write) MSHR misses -system.l1subsys2.cache0.overall_mshr_misses::l0subsys4.tester0 53241 # number of overall MSHR misses -system.l1subsys2.cache0.overall_mshr_misses::l0subsys4.tester1 52173 # number of overall MSHR misses -system.l1subsys2.cache0.overall_mshr_misses::total 105414 # number of overall MSHR misses -system.l1subsys2.cache0.ReadReq_mshr_miss_latency::l0subsys4.tester0 3015074118 # number of ReadReq MSHR miss cycles -system.l1subsys2.cache0.ReadReq_mshr_miss_latency::l0subsys4.tester1 2885020824 # number of ReadReq MSHR miss cycles -system.l1subsys2.cache0.ReadReq_mshr_miss_latency::total 5900094942 # number of ReadReq MSHR miss cycles -system.l1subsys2.cache0.WriteReq_mshr_miss_latency::l0subsys4.tester0 1873671122 # number of WriteReq MSHR miss cycles -system.l1subsys2.cache0.WriteReq_mshr_miss_latency::l0subsys4.tester1 1773541684 # number of WriteReq MSHR miss cycles -system.l1subsys2.cache0.WriteReq_mshr_miss_latency::total 3647212806 # number of WriteReq MSHR miss cycles -system.l1subsys2.cache0.demand_mshr_miss_latency::l0subsys4.tester0 4888745240 # number of demand (read+write) MSHR miss cycles -system.l1subsys2.cache0.demand_mshr_miss_latency::l0subsys4.tester1 4658562508 # number of demand (read+write) MSHR miss cycles -system.l1subsys2.cache0.demand_mshr_miss_latency::total 9547307748 # number of demand (read+write) MSHR miss cycles -system.l1subsys2.cache0.overall_mshr_miss_latency::l0subsys4.tester0 4888745240 # number of overall MSHR miss cycles -system.l1subsys2.cache0.overall_mshr_miss_latency::l0subsys4.tester1 4658562508 # number of overall MSHR miss cycles -system.l1subsys2.cache0.overall_mshr_miss_latency::total 9547307748 # number of overall MSHR miss cycles -system.l1subsys2.cache0.ReadReq_mshr_miss_rate::l0subsys4.tester0 0.729918 # mshr miss rate for ReadReq accesses -system.l1subsys2.cache0.ReadReq_mshr_miss_rate::l0subsys4.tester1 0.730507 # mshr miss rate for ReadReq accesses -system.l1subsys2.cache0.ReadReq_mshr_miss_rate::total 0.730209 # mshr miss rate for ReadReq accesses -system.l1subsys2.cache0.WriteReq_mshr_miss_rate::l0subsys4.tester0 0.904923 # mshr miss rate for WriteReq accesses -system.l1subsys2.cache0.WriteReq_mshr_miss_rate::l0subsys4.tester1 0.907177 # mshr miss rate for WriteReq accesses -system.l1subsys2.cache0.WriteReq_mshr_miss_rate::total 0.906036 # mshr miss rate for WriteReq accesses -system.l1subsys2.cache0.demand_mshr_miss_rate::l0subsys4.tester0 0.792465 # mshr miss rate for demand accesses -system.l1subsys2.cache0.demand_mshr_miss_rate::l0subsys4.tester1 0.793433 # mshr miss rate for demand accesses -system.l1subsys2.cache0.demand_mshr_miss_rate::total 0.792944 # mshr miss rate for demand accesses -system.l1subsys2.cache0.overall_mshr_miss_rate::l0subsys4.tester0 0.792465 # mshr miss rate for overall accesses -system.l1subsys2.cache0.overall_mshr_miss_rate::l0subsys4.tester1 0.793433 # mshr miss rate for overall accesses -system.l1subsys2.cache0.overall_mshr_miss_rate::total 0.792944 # mshr miss rate for overall accesses -system.l1subsys2.cache0.ReadReq_avg_mshr_miss_latency::l0subsys4.tester0 95680.189071 # average ReadReq mshr miss latency -system.l1subsys2.cache0.ReadReq_avg_mshr_miss_latency::l0subsys4.tester1 93287.875057 # average ReadReq mshr miss latency -system.l1subsys2.cache0.ReadReq_avg_mshr_miss_latency::total 94495.258368 # average ReadReq mshr miss latency -system.l1subsys2.cache0.WriteReq_avg_mshr_miss_latency::l0subsys4.tester0 86229.054351 # average WriteReq mshr miss latency -system.l1subsys2.cache0.WriteReq_avg_mshr_miss_latency::l0subsys4.tester1 83472.569492 # average WriteReq mshr miss latency -system.l1subsys2.cache0.WriteReq_avg_mshr_miss_latency::total 84866.269685 # average WriteReq mshr miss latency -system.l1subsys2.cache0.demand_avg_mshr_miss_latency::l0subsys4.tester0 91822.941718 # average overall mshr miss latency -system.l1subsys2.cache0.demand_avg_mshr_miss_latency::l0subsys4.tester1 89290.677324 # average overall mshr miss latency -system.l1subsys2.cache0.demand_avg_mshr_miss_latency::total 90569.637316 # average overall mshr miss latency -system.l1subsys2.cache0.overall_avg_mshr_miss_latency::l0subsys4.tester0 91822.941718 # average overall mshr miss latency -system.l1subsys2.cache0.overall_avg_mshr_miss_latency::l0subsys4.tester1 89290.677324 # average overall mshr miss latency -system.l1subsys2.cache0.overall_avg_mshr_miss_latency::total 90569.637316 # average overall mshr miss latency +system.l1subsys2.cache0.writebacks::writebacks 23607 # number of writebacks +system.l1subsys2.cache0.writebacks::total 23607 # number of writebacks +system.l1subsys2.cache0.ReadReq_mshr_hits::l0subsys4.tester0 970 # number of ReadReq MSHR hits +system.l1subsys2.cache0.ReadReq_mshr_hits::l0subsys4.tester1 984 # number of ReadReq MSHR hits +system.l1subsys2.cache0.ReadReq_mshr_hits::total 1954 # number of ReadReq MSHR hits +system.l1subsys2.cache0.WriteReq_mshr_hits::l0subsys4.tester0 557 # number of WriteReq MSHR hits +system.l1subsys2.cache0.WriteReq_mshr_hits::l0subsys4.tester1 530 # number of WriteReq MSHR hits +system.l1subsys2.cache0.WriteReq_mshr_hits::total 1087 # number of WriteReq MSHR hits +system.l1subsys2.cache0.demand_mshr_hits::l0subsys4.tester0 1527 # number of demand (read+write) MSHR hits +system.l1subsys2.cache0.demand_mshr_hits::l0subsys4.tester1 1514 # number of demand (read+write) MSHR hits +system.l1subsys2.cache0.demand_mshr_hits::total 3041 # number of demand (read+write) MSHR hits +system.l1subsys2.cache0.overall_mshr_hits::l0subsys4.tester0 1527 # number of overall MSHR hits +system.l1subsys2.cache0.overall_mshr_hits::l0subsys4.tester1 1514 # number of overall MSHR hits +system.l1subsys2.cache0.overall_mshr_hits::total 3041 # number of overall MSHR hits +system.l1subsys2.cache0.ReadReq_mshr_misses::l0subsys4.tester0 31334 # number of ReadReq MSHR misses +system.l1subsys2.cache0.ReadReq_mshr_misses::l0subsys4.tester1 33023 # number of ReadReq MSHR misses +system.l1subsys2.cache0.ReadReq_mshr_misses::total 64357 # number of ReadReq MSHR misses +system.l1subsys2.cache0.WriteReq_mshr_misses::l0subsys4.tester0 21096 # number of WriteReq MSHR misses +system.l1subsys2.cache0.WriteReq_mshr_misses::l0subsys4.tester1 22225 # number of WriteReq MSHR misses +system.l1subsys2.cache0.WriteReq_mshr_misses::total 43321 # number of WriteReq MSHR misses +system.l1subsys2.cache0.demand_mshr_misses::l0subsys4.tester0 52430 # number of demand (read+write) MSHR misses +system.l1subsys2.cache0.demand_mshr_misses::l0subsys4.tester1 55248 # number of demand (read+write) MSHR misses +system.l1subsys2.cache0.demand_mshr_misses::total 107678 # number of demand (read+write) MSHR misses +system.l1subsys2.cache0.overall_mshr_misses::l0subsys4.tester0 52430 # number of overall MSHR misses +system.l1subsys2.cache0.overall_mshr_misses::l0subsys4.tester1 55248 # number of overall MSHR misses +system.l1subsys2.cache0.overall_mshr_misses::total 107678 # number of overall MSHR misses +system.l1subsys2.cache0.ReadReq_mshr_miss_latency::l0subsys4.tester0 2981407825 # number of ReadReq MSHR miss cycles +system.l1subsys2.cache0.ReadReq_mshr_miss_latency::l0subsys4.tester1 3008088243 # number of ReadReq MSHR miss cycles +system.l1subsys2.cache0.ReadReq_mshr_miss_latency::total 5989496068 # number of ReadReq MSHR miss cycles +system.l1subsys2.cache0.WriteReq_mshr_miss_latency::l0subsys4.tester0 1792490103 # number of WriteReq MSHR miss cycles +system.l1subsys2.cache0.WriteReq_mshr_miss_latency::l0subsys4.tester1 1837443596 # number of WriteReq MSHR miss cycles +system.l1subsys2.cache0.WriteReq_mshr_miss_latency::total 3629933699 # number of WriteReq MSHR miss cycles +system.l1subsys2.cache0.demand_mshr_miss_latency::l0subsys4.tester0 4773897928 # number of demand (read+write) MSHR miss cycles +system.l1subsys2.cache0.demand_mshr_miss_latency::l0subsys4.tester1 4845531839 # number of demand (read+write) MSHR miss cycles +system.l1subsys2.cache0.demand_mshr_miss_latency::total 9619429767 # number of demand (read+write) MSHR miss cycles +system.l1subsys2.cache0.overall_mshr_miss_latency::l0subsys4.tester0 4773897928 # number of overall MSHR miss cycles +system.l1subsys2.cache0.overall_mshr_miss_latency::l0subsys4.tester1 4845531839 # number of overall MSHR miss cycles +system.l1subsys2.cache0.overall_mshr_miss_latency::total 9619429767 # number of overall MSHR miss cycles +system.l1subsys2.cache0.ReadReq_mshr_miss_rate::l0subsys4.tester0 0.736577 # mshr miss rate for ReadReq accesses +system.l1subsys2.cache0.ReadReq_mshr_miss_rate::l0subsys4.tester1 0.771656 # mshr miss rate for ReadReq accesses +system.l1subsys2.cache0.ReadReq_mshr_miss_rate::total 0.754169 # mshr miss rate for ReadReq accesses +system.l1subsys2.cache0.WriteReq_mshr_miss_rate::l0subsys4.tester0 0.898773 # mshr miss rate for WriteReq accesses +system.l1subsys2.cache0.WriteReq_mshr_miss_rate::l0subsys4.tester1 0.935435 # mshr miss rate for WriteReq accesses +system.l1subsys2.cache0.WriteReq_mshr_miss_rate::total 0.917215 # mshr miss rate for WriteReq accesses +system.l1subsys2.cache0.demand_mshr_miss_rate::l0subsys4.tester0 0.794250 # mshr miss rate for demand accesses +system.l1subsys2.cache0.demand_mshr_miss_rate::l0subsys4.tester1 0.830123 # mshr miss rate for demand accesses +system.l1subsys2.cache0.demand_mshr_miss_rate::total 0.812260 # mshr miss rate for demand accesses +system.l1subsys2.cache0.overall_mshr_miss_rate::l0subsys4.tester0 0.794250 # mshr miss rate for overall accesses +system.l1subsys2.cache0.overall_mshr_miss_rate::l0subsys4.tester1 0.830123 # mshr miss rate for overall accesses +system.l1subsys2.cache0.overall_mshr_miss_rate::total 0.812260 # mshr miss rate for overall accesses +system.l1subsys2.cache0.ReadReq_avg_mshr_miss_latency::l0subsys4.tester0 95149.289111 # average ReadReq mshr miss latency +system.l1subsys2.cache0.ReadReq_avg_mshr_miss_latency::l0subsys4.tester1 91090.701723 # average ReadReq mshr miss latency +system.l1subsys2.cache0.ReadReq_avg_mshr_miss_latency::total 93066.738164 # average ReadReq mshr miss latency +system.l1subsys2.cache0.WriteReq_avg_mshr_miss_latency::l0subsys4.tester0 84968.245307 # average WriteReq mshr miss latency +system.l1subsys2.cache0.WriteReq_avg_mshr_miss_latency::l0subsys4.tester1 82674.627492 # average WriteReq mshr miss latency +system.l1subsys2.cache0.WriteReq_avg_mshr_miss_latency::total 83791.549110 # average WriteReq mshr miss latency +system.l1subsys2.cache0.demand_avg_mshr_miss_latency::l0subsys4.tester0 91052.792829 # average overall mshr miss latency +system.l1subsys2.cache0.demand_avg_mshr_miss_latency::l0subsys4.tester1 87705.108583 # average overall mshr miss latency +system.l1subsys2.cache0.demand_avg_mshr_miss_latency::total 89335.145220 # average overall mshr miss latency +system.l1subsys2.cache0.overall_avg_mshr_miss_latency::l0subsys4.tester0 91052.792829 # average overall mshr miss latency +system.l1subsys2.cache0.overall_avg_mshr_miss_latency::l0subsys4.tester1 87705.108583 # average overall mshr miss latency +system.l1subsys2.cache0.overall_avg_mshr_miss_latency::total 89335.145220 # average overall mshr miss latency system.l1subsys2.cache1.tags.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states -system.l1subsys2.cache1.tags.replacements 67065 # number of replacements -system.l1subsys2.cache1.tags.tagsinuse 502.741649 # Cycle average of tags in use -system.l1subsys2.cache1.tags.total_refs 30001 # Total number of references to valid blocks. -system.l1subsys2.cache1.tags.sampled_refs 67574 # Sample count of references to valid blocks. -system.l1subsys2.cache1.tags.avg_refs 0.443973 # Average number of references to valid blocks. -system.l1subsys2.cache1.tags.warmup_cycle 917087000 # Cycle when the warmup percentage was hit. -system.l1subsys2.cache1.tags.occ_blocks::l0subsys5.tester0 252.168064 # Average occupied blocks per requestor -system.l1subsys2.cache1.tags.occ_blocks::l0subsys5.tester1 250.573585 # Average occupied blocks per requestor -system.l1subsys2.cache1.tags.occ_percent::l0subsys5.tester0 0.492516 # Average percentage of cache occupancy -system.l1subsys2.cache1.tags.occ_percent::l0subsys5.tester1 0.489402 # Average percentage of cache occupancy -system.l1subsys2.cache1.tags.occ_percent::total 0.981917 # Average percentage of cache occupancy -system.l1subsys2.cache1.tags.occ_task_id_blocks::1024 509 # Occupied blocks per task id -system.l1subsys2.cache1.tags.age_task_id_blocks_1024::0 194 # Occupied blocks per task id -system.l1subsys2.cache1.tags.age_task_id_blocks_1024::1 245 # Occupied blocks per task id -system.l1subsys2.cache1.tags.age_task_id_blocks_1024::2 70 # Occupied blocks per task id -system.l1subsys2.cache1.tags.occ_task_id_percent::1024 0.994141 # Percentage of cache occupancy per task id -system.l1subsys2.cache1.tags.tag_accesses 630788 # Number of tag accesses -system.l1subsys2.cache1.tags.data_accesses 630788 # Number of data accesses +system.l1subsys2.cache1.tags.replacements 65601 # number of replacements +system.l1subsys2.cache1.tags.tagsinuse 502.970157 # Cycle average of tags in use +system.l1subsys2.cache1.tags.total_refs 28017 # Total number of references to valid blocks. +system.l1subsys2.cache1.tags.sampled_refs 66106 # Sample count of references to valid blocks. +system.l1subsys2.cache1.tags.avg_refs 0.423819 # Average number of references to valid blocks. +system.l1subsys2.cache1.tags.warmup_cycle 368043000 # Cycle when the warmup percentage was hit. +system.l1subsys2.cache1.tags.occ_blocks::l0subsys5.tester0 256.035642 # Average occupied blocks per requestor +system.l1subsys2.cache1.tags.occ_blocks::l0subsys5.tester1 246.934515 # Average occupied blocks per requestor +system.l1subsys2.cache1.tags.occ_percent::l0subsys5.tester0 0.500070 # Average percentage of cache occupancy +system.l1subsys2.cache1.tags.occ_percent::l0subsys5.tester1 0.482294 # Average percentage of cache occupancy +system.l1subsys2.cache1.tags.occ_percent::total 0.982364 # Average percentage of cache occupancy +system.l1subsys2.cache1.tags.occ_task_id_blocks::1024 505 # Occupied blocks per task id +system.l1subsys2.cache1.tags.age_task_id_blocks_1024::0 95 # Occupied blocks per task id +system.l1subsys2.cache1.tags.age_task_id_blocks_1024::1 352 # Occupied blocks per task id +system.l1subsys2.cache1.tags.age_task_id_blocks_1024::2 58 # Occupied blocks per task id +system.l1subsys2.cache1.tags.occ_task_id_percent::1024 0.986328 # Percentage of cache occupancy per task id +system.l1subsys2.cache1.tags.tag_accesses 631185 # Number of tag accesses +system.l1subsys2.cache1.tags.data_accesses 631185 # Number of data accesses system.l1subsys2.cache1.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states -system.l1subsys2.cache1.ReadReq_hits::l0subsys5.tester0 9835 # number of ReadReq hits -system.l1subsys2.cache1.ReadReq_hits::l0subsys5.tester1 9033 # number of ReadReq hits -system.l1subsys2.cache1.ReadReq_hits::total 18868 # number of ReadReq hits -system.l1subsys2.cache1.WriteReq_hits::l0subsys5.tester0 1234 # number of WriteReq hits -system.l1subsys2.cache1.WriteReq_hits::l0subsys5.tester1 1110 # number of WriteReq hits -system.l1subsys2.cache1.WriteReq_hits::total 2344 # number of WriteReq hits -system.l1subsys2.cache1.demand_hits::l0subsys5.tester0 11069 # number of demand (read+write) hits -system.l1subsys2.cache1.demand_hits::l0subsys5.tester1 10143 # number of demand (read+write) hits -system.l1subsys2.cache1.demand_hits::total 21212 # number of demand (read+write) hits -system.l1subsys2.cache1.overall_hits::l0subsys5.tester0 11069 # number of overall hits -system.l1subsys2.cache1.overall_hits::l0subsys5.tester1 10143 # number of overall hits -system.l1subsys2.cache1.overall_hits::total 21212 # number of overall hits -system.l1subsys2.cache1.ReadReq_misses::l0subsys5.tester0 33507 # number of ReadReq misses -system.l1subsys2.cache1.ReadReq_misses::l0subsys5.tester1 33136 # number of ReadReq misses -system.l1subsys2.cache1.ReadReq_misses::total 66643 # number of ReadReq misses -system.l1subsys2.cache1.WriteReq_misses::l0subsys5.tester0 22543 # number of WriteReq misses -system.l1subsys2.cache1.WriteReq_misses::l0subsys5.tester1 22029 # number of WriteReq misses -system.l1subsys2.cache1.WriteReq_misses::total 44572 # number of WriteReq misses -system.l1subsys2.cache1.demand_misses::l0subsys5.tester0 56050 # number of demand (read+write) misses -system.l1subsys2.cache1.demand_misses::l0subsys5.tester1 55165 # number of demand (read+write) misses -system.l1subsys2.cache1.demand_misses::total 111215 # number of demand (read+write) misses -system.l1subsys2.cache1.overall_misses::l0subsys5.tester0 56050 # number of overall misses -system.l1subsys2.cache1.overall_misses::l0subsys5.tester1 55165 # number of overall misses -system.l1subsys2.cache1.overall_misses::total 111215 # number of overall misses -system.l1subsys2.cache1.ReadReq_miss_latency::l0subsys5.tester0 3090757790 # number of ReadReq miss cycles -system.l1subsys2.cache1.ReadReq_miss_latency::l0subsys5.tester1 3059427771 # number of ReadReq miss cycles -system.l1subsys2.cache1.ReadReq_miss_latency::total 6150185561 # number of ReadReq miss cycles -system.l1subsys2.cache1.WriteReq_miss_latency::l0subsys5.tester0 1875123029 # number of WriteReq miss cycles -system.l1subsys2.cache1.WriteReq_miss_latency::l0subsys5.tester1 1846091566 # number of WriteReq miss cycles -system.l1subsys2.cache1.WriteReq_miss_latency::total 3721214595 # number of WriteReq miss cycles -system.l1subsys2.cache1.demand_miss_latency::l0subsys5.tester0 4965880819 # number of demand (read+write) miss cycles -system.l1subsys2.cache1.demand_miss_latency::l0subsys5.tester1 4905519337 # number of demand (read+write) miss cycles -system.l1subsys2.cache1.demand_miss_latency::total 9871400156 # number of demand (read+write) miss cycles -system.l1subsys2.cache1.overall_miss_latency::l0subsys5.tester0 4965880819 # number of overall miss cycles -system.l1subsys2.cache1.overall_miss_latency::l0subsys5.tester1 4905519337 # number of overall miss cycles -system.l1subsys2.cache1.overall_miss_latency::total 9871400156 # number of overall miss cycles -system.l1subsys2.cache1.ReadReq_accesses::l0subsys5.tester0 43342 # number of ReadReq accesses(hits+misses) -system.l1subsys2.cache1.ReadReq_accesses::l0subsys5.tester1 42169 # number of ReadReq accesses(hits+misses) -system.l1subsys2.cache1.ReadReq_accesses::total 85511 # number of ReadReq accesses(hits+misses) -system.l1subsys2.cache1.WriteReq_accesses::l0subsys5.tester0 23777 # number of WriteReq accesses(hits+misses) -system.l1subsys2.cache1.WriteReq_accesses::l0subsys5.tester1 23139 # number of WriteReq accesses(hits+misses) -system.l1subsys2.cache1.WriteReq_accesses::total 46916 # number of WriteReq accesses(hits+misses) -system.l1subsys2.cache1.demand_accesses::l0subsys5.tester0 67119 # number of demand (read+write) accesses -system.l1subsys2.cache1.demand_accesses::l0subsys5.tester1 65308 # number of demand (read+write) accesses -system.l1subsys2.cache1.demand_accesses::total 132427 # number of demand (read+write) accesses -system.l1subsys2.cache1.overall_accesses::l0subsys5.tester0 67119 # number of overall (read+write) accesses -system.l1subsys2.cache1.overall_accesses::l0subsys5.tester1 65308 # number of overall (read+write) accesses -system.l1subsys2.cache1.overall_accesses::total 132427 # number of overall (read+write) accesses -system.l1subsys2.cache1.ReadReq_miss_rate::l0subsys5.tester0 0.773084 # miss rate for ReadReq accesses -system.l1subsys2.cache1.ReadReq_miss_rate::l0subsys5.tester1 0.785791 # miss rate for ReadReq accesses -system.l1subsys2.cache1.ReadReq_miss_rate::total 0.779350 # miss rate for ReadReq accesses -system.l1subsys2.cache1.WriteReq_miss_rate::l0subsys5.tester0 0.948101 # miss rate for WriteReq accesses -system.l1subsys2.cache1.WriteReq_miss_rate::l0subsys5.tester1 0.952029 # miss rate for WriteReq accesses -system.l1subsys2.cache1.WriteReq_miss_rate::total 0.950038 # miss rate for WriteReq accesses -system.l1subsys2.cache1.demand_miss_rate::l0subsys5.tester0 0.835084 # miss rate for demand accesses -system.l1subsys2.cache1.demand_miss_rate::l0subsys5.tester1 0.844690 # miss rate for demand accesses -system.l1subsys2.cache1.demand_miss_rate::total 0.839821 # miss rate for demand accesses -system.l1subsys2.cache1.overall_miss_rate::l0subsys5.tester0 0.835084 # miss rate for overall accesses -system.l1subsys2.cache1.overall_miss_rate::l0subsys5.tester1 0.844690 # miss rate for overall accesses -system.l1subsys2.cache1.overall_miss_rate::total 0.839821 # miss rate for overall accesses -system.l1subsys2.cache1.ReadReq_avg_miss_latency::l0subsys5.tester0 92242.152088 # average ReadReq miss latency -system.l1subsys2.cache1.ReadReq_avg_miss_latency::l0subsys5.tester1 92329.423316 # average ReadReq miss latency -system.l1subsys2.cache1.ReadReq_avg_miss_latency::total 92285.544783 # average ReadReq miss latency -system.l1subsys2.cache1.WriteReq_avg_miss_latency::l0subsys5.tester0 83179.835381 # average WriteReq miss latency -system.l1subsys2.cache1.WriteReq_avg_miss_latency::l0subsys5.tester1 83802.785692 # average WriteReq miss latency -system.l1subsys2.cache1.WriteReq_avg_miss_latency::total 83487.718635 # average WriteReq miss latency -system.l1subsys2.cache1.demand_avg_miss_latency::l0subsys5.tester0 88597.338430 # average overall miss latency -system.l1subsys2.cache1.demand_avg_miss_latency::l0subsys5.tester1 88924.487211 # average overall miss latency -system.l1subsys2.cache1.demand_avg_miss_latency::total 88759.611168 # average overall miss latency -system.l1subsys2.cache1.overall_avg_miss_latency::l0subsys5.tester0 88597.338430 # average overall miss latency -system.l1subsys2.cache1.overall_avg_miss_latency::l0subsys5.tester1 88924.487211 # average overall miss latency -system.l1subsys2.cache1.overall_avg_miss_latency::total 88759.611168 # average overall miss latency -system.l1subsys2.cache1.blocked_cycles::no_mshrs 248353 # number of cycles access was blocked +system.l1subsys2.cache1.ReadReq_hits::l0subsys5.tester0 8598 # number of ReadReq hits +system.l1subsys2.cache1.ReadReq_hits::l0subsys5.tester1 8958 # number of ReadReq hits +system.l1subsys2.cache1.ReadReq_hits::total 17556 # number of ReadReq hits +system.l1subsys2.cache1.WriteReq_hits::l0subsys5.tester0 971 # number of WriteReq hits +system.l1subsys2.cache1.WriteReq_hits::l0subsys5.tester1 994 # number of WriteReq hits +system.l1subsys2.cache1.WriteReq_hits::total 1965 # number of WriteReq hits +system.l1subsys2.cache1.demand_hits::l0subsys5.tester0 9569 # number of demand (read+write) hits +system.l1subsys2.cache1.demand_hits::l0subsys5.tester1 9952 # number of demand (read+write) hits +system.l1subsys2.cache1.demand_hits::total 19521 # number of demand (read+write) hits +system.l1subsys2.cache1.overall_hits::l0subsys5.tester0 9569 # number of overall hits +system.l1subsys2.cache1.overall_hits::l0subsys5.tester1 9952 # number of overall hits +system.l1subsys2.cache1.overall_hits::total 19521 # number of overall hits +system.l1subsys2.cache1.ReadReq_misses::l0subsys5.tester0 34186 # number of ReadReq misses +system.l1subsys2.cache1.ReadReq_misses::l0subsys5.tester1 33576 # number of ReadReq misses +system.l1subsys2.cache1.ReadReq_misses::total 67762 # number of ReadReq misses +system.l1subsys2.cache1.WriteReq_misses::l0subsys5.tester0 22463 # number of WriteReq misses +system.l1subsys2.cache1.WriteReq_misses::l0subsys5.tester1 22525 # number of WriteReq misses +system.l1subsys2.cache1.WriteReq_misses::total 44988 # number of WriteReq misses +system.l1subsys2.cache1.demand_misses::l0subsys5.tester0 56649 # number of demand (read+write) misses +system.l1subsys2.cache1.demand_misses::l0subsys5.tester1 56101 # number of demand (read+write) misses +system.l1subsys2.cache1.demand_misses::total 112750 # number of demand (read+write) misses +system.l1subsys2.cache1.overall_misses::l0subsys5.tester0 56649 # number of overall misses +system.l1subsys2.cache1.overall_misses::l0subsys5.tester1 56101 # number of overall misses +system.l1subsys2.cache1.overall_misses::total 112750 # number of overall misses +system.l1subsys2.cache1.ReadReq_miss_latency::l0subsys5.tester0 3101171642 # number of ReadReq miss cycles +system.l1subsys2.cache1.ReadReq_miss_latency::l0subsys5.tester1 3046677897 # number of ReadReq miss cycles +system.l1subsys2.cache1.ReadReq_miss_latency::total 6147849539 # number of ReadReq miss cycles +system.l1subsys2.cache1.WriteReq_miss_latency::l0subsys5.tester0 1867972083 # number of WriteReq miss cycles +system.l1subsys2.cache1.WriteReq_miss_latency::l0subsys5.tester1 1852914357 # number of WriteReq miss cycles +system.l1subsys2.cache1.WriteReq_miss_latency::total 3720886440 # number of WriteReq miss cycles +system.l1subsys2.cache1.demand_miss_latency::l0subsys5.tester0 4969143725 # number of demand (read+write) miss cycles +system.l1subsys2.cache1.demand_miss_latency::l0subsys5.tester1 4899592254 # number of demand (read+write) miss cycles +system.l1subsys2.cache1.demand_miss_latency::total 9868735979 # number of demand (read+write) miss cycles +system.l1subsys2.cache1.overall_miss_latency::l0subsys5.tester0 4969143725 # number of overall miss cycles +system.l1subsys2.cache1.overall_miss_latency::l0subsys5.tester1 4899592254 # number of overall miss cycles +system.l1subsys2.cache1.overall_miss_latency::total 9868735979 # number of overall miss cycles +system.l1subsys2.cache1.ReadReq_accesses::l0subsys5.tester0 42784 # number of ReadReq accesses(hits+misses) +system.l1subsys2.cache1.ReadReq_accesses::l0subsys5.tester1 42534 # number of ReadReq accesses(hits+misses) +system.l1subsys2.cache1.ReadReq_accesses::total 85318 # number of ReadReq accesses(hits+misses) +system.l1subsys2.cache1.WriteReq_accesses::l0subsys5.tester0 23434 # number of WriteReq accesses(hits+misses) +system.l1subsys2.cache1.WriteReq_accesses::l0subsys5.tester1 23519 # number of WriteReq accesses(hits+misses) +system.l1subsys2.cache1.WriteReq_accesses::total 46953 # number of WriteReq accesses(hits+misses) +system.l1subsys2.cache1.demand_accesses::l0subsys5.tester0 66218 # number of demand (read+write) accesses +system.l1subsys2.cache1.demand_accesses::l0subsys5.tester1 66053 # number of demand (read+write) accesses +system.l1subsys2.cache1.demand_accesses::total 132271 # number of demand (read+write) accesses +system.l1subsys2.cache1.overall_accesses::l0subsys5.tester0 66218 # number of overall (read+write) accesses +system.l1subsys2.cache1.overall_accesses::l0subsys5.tester1 66053 # number of overall (read+write) accesses +system.l1subsys2.cache1.overall_accesses::total 132271 # number of overall (read+write) accesses +system.l1subsys2.cache1.ReadReq_miss_rate::l0subsys5.tester0 0.799037 # miss rate for ReadReq accesses +system.l1subsys2.cache1.ReadReq_miss_rate::l0subsys5.tester1 0.789392 # miss rate for ReadReq accesses +system.l1subsys2.cache1.ReadReq_miss_rate::total 0.794229 # miss rate for ReadReq accesses +system.l1subsys2.cache1.WriteReq_miss_rate::l0subsys5.tester0 0.958564 # miss rate for WriteReq accesses +system.l1subsys2.cache1.WriteReq_miss_rate::l0subsys5.tester1 0.957736 # miss rate for WriteReq accesses +system.l1subsys2.cache1.WriteReq_miss_rate::total 0.958150 # miss rate for WriteReq accesses +system.l1subsys2.cache1.demand_miss_rate::l0subsys5.tester0 0.855492 # miss rate for demand accesses +system.l1subsys2.cache1.demand_miss_rate::l0subsys5.tester1 0.849333 # miss rate for demand accesses +system.l1subsys2.cache1.demand_miss_rate::total 0.852417 # miss rate for demand accesses +system.l1subsys2.cache1.overall_miss_rate::l0subsys5.tester0 0.855492 # miss rate for overall accesses +system.l1subsys2.cache1.overall_miss_rate::l0subsys5.tester1 0.849333 # miss rate for overall accesses +system.l1subsys2.cache1.overall_miss_rate::total 0.852417 # miss rate for overall accesses +system.l1subsys2.cache1.ReadReq_avg_miss_latency::l0subsys5.tester0 90714.668051 # average ReadReq miss latency +system.l1subsys2.cache1.ReadReq_avg_miss_latency::l0subsys5.tester1 90739.751519 # average ReadReq miss latency +system.l1subsys2.cache1.ReadReq_avg_miss_latency::total 90727.096883 # average ReadReq miss latency +system.l1subsys2.cache1.WriteReq_avg_miss_latency::l0subsys5.tester0 83157.729733 # average WriteReq miss latency +system.l1subsys2.cache1.WriteReq_avg_miss_latency::l0subsys5.tester1 82260.348812 # average WriteReq miss latency +system.l1subsys2.cache1.WriteReq_avg_miss_latency::total 82708.420912 # average WriteReq miss latency +system.l1subsys2.cache1.demand_avg_miss_latency::l0subsys5.tester0 87718.119031 # average overall miss latency +system.l1subsys2.cache1.demand_avg_miss_latency::l0subsys5.tester1 87335.203544 # average overall miss latency +system.l1subsys2.cache1.demand_avg_miss_latency::total 87527.591831 # average overall miss latency +system.l1subsys2.cache1.overall_avg_miss_latency::l0subsys5.tester0 87718.119031 # average overall miss latency +system.l1subsys2.cache1.overall_avg_miss_latency::l0subsys5.tester1 87335.203544 # average overall miss latency +system.l1subsys2.cache1.overall_avg_miss_latency::total 87527.591831 # average overall miss latency +system.l1subsys2.cache1.blocked_cycles::no_mshrs 243675 # number of cycles access was blocked system.l1subsys2.cache1.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l1subsys2.cache1.blocked::no_mshrs 7598 # number of cycles access was blocked +system.l1subsys2.cache1.blocked::no_mshrs 7511 # number of cycles access was blocked system.l1subsys2.cache1.blocked::no_targets 0 # number of cycles access was blocked -system.l1subsys2.cache1.avg_blocked_cycles::no_mshrs 32.686628 # average number of cycles each access was blocked +system.l1subsys2.cache1.avg_blocked_cycles::no_mshrs 32.442418 # average number of cycles each access was blocked system.l1subsys2.cache1.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.l1subsys2.cache1.writebacks::writebacks 23828 # number of writebacks -system.l1subsys2.cache1.writebacks::total 23828 # number of writebacks -system.l1subsys2.cache1.ReadReq_mshr_hits::l0subsys5.tester0 949 # number of ReadReq MSHR hits -system.l1subsys2.cache1.ReadReq_mshr_hits::l0subsys5.tester1 1026 # number of ReadReq MSHR hits -system.l1subsys2.cache1.ReadReq_mshr_hits::total 1975 # number of ReadReq MSHR hits -system.l1subsys2.cache1.WriteReq_mshr_hits::l0subsys5.tester0 516 # number of WriteReq MSHR hits -system.l1subsys2.cache1.WriteReq_mshr_hits::l0subsys5.tester1 532 # number of WriteReq MSHR hits -system.l1subsys2.cache1.WriteReq_mshr_hits::total 1048 # number of WriteReq MSHR hits -system.l1subsys2.cache1.demand_mshr_hits::l0subsys5.tester0 1465 # number of demand (read+write) MSHR hits -system.l1subsys2.cache1.demand_mshr_hits::l0subsys5.tester1 1558 # number of demand (read+write) MSHR hits -system.l1subsys2.cache1.demand_mshr_hits::total 3023 # number of demand (read+write) MSHR hits -system.l1subsys2.cache1.overall_mshr_hits::l0subsys5.tester0 1465 # number of overall MSHR hits -system.l1subsys2.cache1.overall_mshr_hits::l0subsys5.tester1 1558 # number of overall MSHR hits -system.l1subsys2.cache1.overall_mshr_hits::total 3023 # number of overall MSHR hits -system.l1subsys2.cache1.ReadReq_mshr_misses::l0subsys5.tester0 32558 # number of ReadReq MSHR misses -system.l1subsys2.cache1.ReadReq_mshr_misses::l0subsys5.tester1 32110 # number of ReadReq MSHR misses -system.l1subsys2.cache1.ReadReq_mshr_misses::total 64668 # number of ReadReq MSHR misses -system.l1subsys2.cache1.WriteReq_mshr_misses::l0subsys5.tester0 22027 # number of WriteReq MSHR misses -system.l1subsys2.cache1.WriteReq_mshr_misses::l0subsys5.tester1 21497 # number of WriteReq MSHR misses -system.l1subsys2.cache1.WriteReq_mshr_misses::total 43524 # number of WriteReq MSHR misses -system.l1subsys2.cache1.demand_mshr_misses::l0subsys5.tester0 54585 # number of demand (read+write) MSHR misses -system.l1subsys2.cache1.demand_mshr_misses::l0subsys5.tester1 53607 # number of demand (read+write) MSHR misses -system.l1subsys2.cache1.demand_mshr_misses::total 108192 # number of demand (read+write) MSHR misses -system.l1subsys2.cache1.overall_mshr_misses::l0subsys5.tester0 54585 # number of overall MSHR misses -system.l1subsys2.cache1.overall_mshr_misses::l0subsys5.tester1 53607 # number of overall MSHR misses -system.l1subsys2.cache1.overall_mshr_misses::total 108192 # number of overall MSHR misses -system.l1subsys2.cache1.ReadReq_mshr_miss_latency::l0subsys5.tester0 3037433156 # number of ReadReq MSHR miss cycles -system.l1subsys2.cache1.ReadReq_mshr_miss_latency::l0subsys5.tester1 3005867164 # number of ReadReq MSHR miss cycles -system.l1subsys2.cache1.ReadReq_mshr_miss_latency::total 6043300320 # number of ReadReq MSHR miss cycles -system.l1subsys2.cache1.WriteReq_mshr_miss_latency::l0subsys5.tester0 1845702999 # number of WriteReq MSHR miss cycles -system.l1subsys2.cache1.WriteReq_mshr_miss_latency::l0subsys5.tester1 1817333709 # number of WriteReq MSHR miss cycles -system.l1subsys2.cache1.WriteReq_mshr_miss_latency::total 3663036708 # number of WriteReq MSHR miss cycles -system.l1subsys2.cache1.demand_mshr_miss_latency::l0subsys5.tester0 4883136155 # number of demand (read+write) MSHR miss cycles -system.l1subsys2.cache1.demand_mshr_miss_latency::l0subsys5.tester1 4823200873 # number of demand (read+write) MSHR miss cycles -system.l1subsys2.cache1.demand_mshr_miss_latency::total 9706337028 # number of demand (read+write) MSHR miss cycles -system.l1subsys2.cache1.overall_mshr_miss_latency::l0subsys5.tester0 4883136155 # number of overall MSHR miss cycles -system.l1subsys2.cache1.overall_mshr_miss_latency::l0subsys5.tester1 4823200873 # number of overall MSHR miss cycles -system.l1subsys2.cache1.overall_mshr_miss_latency::total 9706337028 # number of overall MSHR miss cycles -system.l1subsys2.cache1.ReadReq_mshr_miss_rate::l0subsys5.tester0 0.751188 # mshr miss rate for ReadReq accesses -system.l1subsys2.cache1.ReadReq_mshr_miss_rate::l0subsys5.tester1 0.761460 # mshr miss rate for ReadReq accesses -system.l1subsys2.cache1.ReadReq_mshr_miss_rate::total 0.756254 # mshr miss rate for ReadReq accesses -system.l1subsys2.cache1.WriteReq_mshr_miss_rate::l0subsys5.tester0 0.926399 # mshr miss rate for WriteReq accesses -system.l1subsys2.cache1.WriteReq_mshr_miss_rate::l0subsys5.tester1 0.929038 # mshr miss rate for WriteReq accesses -system.l1subsys2.cache1.WriteReq_mshr_miss_rate::total 0.927701 # mshr miss rate for WriteReq accesses -system.l1subsys2.cache1.demand_mshr_miss_rate::l0subsys5.tester0 0.813257 # mshr miss rate for demand accesses -system.l1subsys2.cache1.demand_mshr_miss_rate::l0subsys5.tester1 0.820834 # mshr miss rate for demand accesses -system.l1subsys2.cache1.demand_mshr_miss_rate::total 0.816994 # mshr miss rate for demand accesses -system.l1subsys2.cache1.overall_mshr_miss_rate::l0subsys5.tester0 0.813257 # mshr miss rate for overall accesses -system.l1subsys2.cache1.overall_mshr_miss_rate::l0subsys5.tester1 0.820834 # mshr miss rate for overall accesses -system.l1subsys2.cache1.overall_mshr_miss_rate::total 0.816994 # mshr miss rate for overall accesses -system.l1subsys2.cache1.ReadReq_avg_mshr_miss_latency::l0subsys5.tester0 93292.989619 # average ReadReq mshr miss latency -system.l1subsys2.cache1.ReadReq_avg_mshr_miss_latency::l0subsys5.tester1 93611.559140 # average ReadReq mshr miss latency -system.l1subsys2.cache1.ReadReq_avg_mshr_miss_latency::total 93451.170904 # average ReadReq mshr miss latency -system.l1subsys2.cache1.WriteReq_avg_mshr_miss_latency::l0subsys5.tester0 83792.754302 # average WriteReq mshr miss latency -system.l1subsys2.cache1.WriteReq_avg_mshr_miss_latency::l0subsys5.tester1 84538.945388 # average WriteReq mshr miss latency -system.l1subsys2.cache1.WriteReq_avg_mshr_miss_latency::total 84161.306589 # average WriteReq mshr miss latency -system.l1subsys2.cache1.demand_avg_mshr_miss_latency::l0subsys5.tester0 89459.304846 # average overall mshr miss latency -system.l1subsys2.cache1.demand_avg_mshr_miss_latency::l0subsys5.tester1 89973.340664 # average overall mshr miss latency -system.l1subsys2.cache1.demand_avg_mshr_miss_latency::total 89713.999445 # average overall mshr miss latency -system.l1subsys2.cache1.overall_avg_mshr_miss_latency::l0subsys5.tester0 89459.304846 # average overall mshr miss latency -system.l1subsys2.cache1.overall_avg_mshr_miss_latency::l0subsys5.tester1 89973.340664 # average overall mshr miss latency -system.l1subsys2.cache1.overall_avg_mshr_miss_latency::total 89713.999445 # average overall mshr miss latency -system.l1subsys2.xbar.snoop_filter.tot_requests 347420 # Total number of requests made to the snoop filter. -system.l1subsys2.xbar.snoop_filter.hit_single_requests 164404 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.l1subsys2.xbar.snoop_filter.hit_multi_requests 8459 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.l1subsys2.xbar.snoop_filter.tot_snoops 114014 # Total number of snoops made to the snoop filter. -system.l1subsys2.xbar.snoop_filter.hit_single_snoops 99574 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.l1subsys2.xbar.snoop_filter.hit_multi_snoops 14440 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.l1subsys2.cache1.writebacks::writebacks 23261 # number of writebacks +system.l1subsys2.cache1.writebacks::total 23261 # number of writebacks +system.l1subsys2.cache1.ReadReq_mshr_hits::l0subsys5.tester0 1398 # number of ReadReq MSHR hits +system.l1subsys2.cache1.ReadReq_mshr_hits::l0subsys5.tester1 1315 # number of ReadReq MSHR hits +system.l1subsys2.cache1.ReadReq_mshr_hits::total 2713 # number of ReadReq MSHR hits +system.l1subsys2.cache1.WriteReq_mshr_hits::l0subsys5.tester0 724 # number of WriteReq MSHR hits +system.l1subsys2.cache1.WriteReq_mshr_hits::l0subsys5.tester1 737 # number of WriteReq MSHR hits +system.l1subsys2.cache1.WriteReq_mshr_hits::total 1461 # number of WriteReq MSHR hits +system.l1subsys2.cache1.demand_mshr_hits::l0subsys5.tester0 2122 # number of demand (read+write) MSHR hits +system.l1subsys2.cache1.demand_mshr_hits::l0subsys5.tester1 2052 # number of demand (read+write) MSHR hits +system.l1subsys2.cache1.demand_mshr_hits::total 4174 # number of demand (read+write) MSHR hits +system.l1subsys2.cache1.overall_mshr_hits::l0subsys5.tester0 2122 # number of overall MSHR hits +system.l1subsys2.cache1.overall_mshr_hits::l0subsys5.tester1 2052 # number of overall MSHR hits +system.l1subsys2.cache1.overall_mshr_hits::total 4174 # number of overall MSHR hits +system.l1subsys2.cache1.ReadReq_mshr_misses::l0subsys5.tester0 32788 # number of ReadReq MSHR misses +system.l1subsys2.cache1.ReadReq_mshr_misses::l0subsys5.tester1 32261 # number of ReadReq MSHR misses +system.l1subsys2.cache1.ReadReq_mshr_misses::total 65049 # number of ReadReq MSHR misses +system.l1subsys2.cache1.WriteReq_mshr_misses::l0subsys5.tester0 21739 # number of WriteReq MSHR misses +system.l1subsys2.cache1.WriteReq_mshr_misses::l0subsys5.tester1 21788 # number of WriteReq MSHR misses +system.l1subsys2.cache1.WriteReq_mshr_misses::total 43527 # number of WriteReq MSHR misses +system.l1subsys2.cache1.demand_mshr_misses::l0subsys5.tester0 54527 # number of demand (read+write) MSHR misses +system.l1subsys2.cache1.demand_mshr_misses::l0subsys5.tester1 54049 # number of demand (read+write) MSHR misses +system.l1subsys2.cache1.demand_mshr_misses::total 108576 # number of demand (read+write) MSHR misses +system.l1subsys2.cache1.overall_mshr_misses::l0subsys5.tester0 54527 # number of overall MSHR misses +system.l1subsys2.cache1.overall_mshr_misses::l0subsys5.tester1 54049 # number of overall MSHR misses +system.l1subsys2.cache1.overall_mshr_misses::total 108576 # number of overall MSHR misses +system.l1subsys2.cache1.ReadReq_mshr_miss_latency::l0subsys5.tester0 3037090619 # number of ReadReq MSHR miss cycles +system.l1subsys2.cache1.ReadReq_mshr_miss_latency::l0subsys5.tester1 2984778636 # number of ReadReq MSHR miss cycles +system.l1subsys2.cache1.ReadReq_mshr_miss_latency::total 6021869255 # number of ReadReq MSHR miss cycles +system.l1subsys2.cache1.WriteReq_mshr_miss_latency::l0subsys5.tester0 1837384657 # number of WriteReq MSHR miss cycles +system.l1subsys2.cache1.WriteReq_mshr_miss_latency::l0subsys5.tester1 1821394302 # number of WriteReq MSHR miss cycles +system.l1subsys2.cache1.WriteReq_mshr_miss_latency::total 3658778959 # number of WriteReq MSHR miss cycles +system.l1subsys2.cache1.demand_mshr_miss_latency::l0subsys5.tester0 4874475276 # number of demand (read+write) MSHR miss cycles +system.l1subsys2.cache1.demand_mshr_miss_latency::l0subsys5.tester1 4806172938 # number of demand (read+write) MSHR miss cycles +system.l1subsys2.cache1.demand_mshr_miss_latency::total 9680648214 # number of demand (read+write) MSHR miss cycles +system.l1subsys2.cache1.overall_mshr_miss_latency::l0subsys5.tester0 4874475276 # number of overall MSHR miss cycles +system.l1subsys2.cache1.overall_mshr_miss_latency::l0subsys5.tester1 4806172938 # number of overall MSHR miss cycles +system.l1subsys2.cache1.overall_mshr_miss_latency::total 9680648214 # number of overall MSHR miss cycles +system.l1subsys2.cache1.ReadReq_mshr_miss_rate::l0subsys5.tester0 0.766361 # mshr miss rate for ReadReq accesses +system.l1subsys2.cache1.ReadReq_mshr_miss_rate::l0subsys5.tester1 0.758476 # mshr miss rate for ReadReq accesses +system.l1subsys2.cache1.ReadReq_mshr_miss_rate::total 0.762430 # mshr miss rate for ReadReq accesses +system.l1subsys2.cache1.WriteReq_mshr_miss_rate::l0subsys5.tester0 0.927669 # mshr miss rate for WriteReq accesses +system.l1subsys2.cache1.WriteReq_mshr_miss_rate::l0subsys5.tester1 0.926400 # mshr miss rate for WriteReq accesses +system.l1subsys2.cache1.WriteReq_mshr_miss_rate::total 0.927033 # mshr miss rate for WriteReq accesses +system.l1subsys2.cache1.demand_mshr_miss_rate::l0subsys5.tester0 0.823447 # mshr miss rate for demand accesses +system.l1subsys2.cache1.demand_mshr_miss_rate::l0subsys5.tester1 0.818267 # mshr miss rate for demand accesses +system.l1subsys2.cache1.demand_mshr_miss_rate::total 0.820860 # mshr miss rate for demand accesses +system.l1subsys2.cache1.overall_mshr_miss_rate::l0subsys5.tester0 0.823447 # mshr miss rate for overall accesses +system.l1subsys2.cache1.overall_mshr_miss_rate::l0subsys5.tester1 0.818267 # mshr miss rate for overall accesses +system.l1subsys2.cache1.overall_mshr_miss_rate::total 0.820860 # mshr miss rate for overall accesses +system.l1subsys2.cache1.ReadReq_avg_mshr_miss_latency::l0subsys5.tester0 92628.114524 # average ReadReq mshr miss latency +system.l1subsys2.cache1.ReadReq_avg_mshr_miss_latency::l0subsys5.tester1 92519.718422 # average ReadReq mshr miss latency +system.l1subsys2.cache1.ReadReq_avg_mshr_miss_latency::total 92574.355563 # average ReadReq mshr miss latency +system.l1subsys2.cache1.WriteReq_avg_mshr_miss_latency::l0subsys5.tester0 84520.201343 # average WriteReq mshr miss latency +system.l1subsys2.cache1.WriteReq_avg_mshr_miss_latency::l0subsys5.tester1 83596.213604 # average WriteReq mshr miss latency +system.l1subsys2.cache1.WriteReq_avg_mshr_miss_latency::total 84057.687389 # average WriteReq mshr miss latency +system.l1subsys2.cache1.demand_avg_mshr_miss_latency::l0subsys5.tester0 89395.625580 # average overall mshr miss latency +system.l1subsys2.cache1.demand_avg_mshr_miss_latency::l0subsys5.tester1 88922.513608 # average overall mshr miss latency +system.l1subsys2.cache1.demand_avg_mshr_miss_latency::total 89160.111019 # average overall mshr miss latency +system.l1subsys2.cache1.overall_avg_mshr_miss_latency::l0subsys5.tester0 89395.625580 # average overall mshr miss latency +system.l1subsys2.cache1.overall_avg_mshr_miss_latency::l0subsys5.tester1 88922.513608 # average overall mshr miss latency +system.l1subsys2.cache1.overall_avg_mshr_miss_latency::total 89160.111019 # average overall mshr miss latency +system.l1subsys2.xbar.snoop_filter.tot_requests 350018 # Total number of requests made to the snoop filter. +system.l1subsys2.xbar.snoop_filter.hit_single_requests 165507 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.l1subsys2.xbar.snoop_filter.hit_multi_requests 8863 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.l1subsys2.xbar.snoop_filter.tot_snoops 157282 # Total number of snoops made to the snoop filter. +system.l1subsys2.xbar.snoop_filter.hit_single_snoops 139819 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.l1subsys2.xbar.snoop_filter.hit_multi_snoops 17463 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.l1subsys2.xbar.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states -system.l1subsys2.xbar.trans_dist::ReadResp 152712 # Transaction distribution -system.l1subsys2.xbar.trans_dist::ReadRespWithInvalidate 3827 # Transaction distribution -system.l1subsys2.xbar.trans_dist::WritebackDirty 93911 # Transaction distribution -system.l1subsys2.xbar.trans_dist::CleanEvict 169169 # Transaction distribution -system.l1subsys2.xbar.trans_dist::UpgradeReq 39714 # Transaction distribution -system.l1subsys2.xbar.trans_dist::UpgradeResp 24494 # Transaction distribution -system.l1subsys2.xbar.trans_dist::ReadExReq 98494 # Transaction distribution -system.l1subsys2.xbar.trans_dist::ReadExResp 90450 # Transaction distribution -system.l1subsys2.xbar.trans_dist::ReadSharedReq 166204 # Transaction distribution -system.l1subsys2.xbar.pkt_count_system.l1subsys2.cache0.mem_side::system.l2subsys0.cache3.cpu_side 298570 # Packet count per connected master and slave (bytes) -system.l1subsys2.xbar.pkt_count_system.l1subsys2.cache1.mem_side::system.l2subsys0.cache3.cpu_side 306224 # Packet count per connected master and slave (bytes) -system.l1subsys2.xbar.pkt_count::total 604794 # Packet count per connected master and slave (bytes) -system.l1subsys2.xbar.pkt_size_system.l1subsys2.cache0.mem_side::system.l2subsys0.cache3.cpu_side 8902976 # Cumulative packet size per connected master and slave (bytes) -system.l1subsys2.xbar.pkt_size_system.l1subsys2.cache1.mem_side::system.l2subsys0.cache3.cpu_side 9148608 # Cumulative packet size per connected master and slave (bytes) -system.l1subsys2.xbar.pkt_size::total 18051584 # Cumulative packet size per connected master and slave (bytes) -system.l1subsys2.xbar.snoops 290665 # Total snoops (count) -system.l1subsys2.xbar.snoopTraffic 6825600 # Total snoop traffic (bytes) -system.l1subsys2.xbar.snoop_fanout::samples 435074 # Request fanout histogram -system.l1subsys2.xbar.snoop_fanout::mean 0.354188 # Request fanout histogram -system.l1subsys2.xbar.snoop_fanout::stdev 0.543249 # Request fanout histogram +system.l1subsys2.xbar.trans_dist::ReadResp 155964 # Transaction distribution +system.l1subsys2.xbar.trans_dist::ReadRespWithInvalidate 4483 # Transaction distribution +system.l1subsys2.xbar.trans_dist::WritebackDirty 93011 # Transaction distribution +system.l1subsys2.xbar.trans_dist::CleanEvict 193898 # Transaction distribution +system.l1subsys2.xbar.trans_dist::UpgradeReq 38837 # Transaction distribution +system.l1subsys2.xbar.trans_dist::UpgradeResp 23341 # Transaction distribution +system.l1subsys2.xbar.trans_dist::ReadExReq 102617 # Transaction distribution +system.l1subsys2.xbar.trans_dist::ReadExResp 93375 # Transaction distribution +system.l1subsys2.xbar.trans_dist::ReadSharedReq 171504 # Transaction distribution +system.l1subsys2.xbar.pkt_count_system.l1subsys2.cache0.mem_side::system.l2subsys0.cache3.cpu_side 304422 # Packet count per connected master and slave (bytes) +system.l1subsys2.xbar.pkt_count_system.l1subsys2.cache1.mem_side::system.l2subsys0.cache3.cpu_side 307736 # Packet count per connected master and slave (bytes) +system.l1subsys2.xbar.pkt_count::total 612158 # Packet count per connected master and slave (bytes) +system.l1subsys2.xbar.pkt_size_system.l1subsys2.cache0.mem_side::system.l2subsys0.cache3.cpu_side 9114816 # Cumulative packet size per connected master and slave (bytes) +system.l1subsys2.xbar.pkt_size_system.l1subsys2.cache1.mem_side::system.l2subsys0.cache3.cpu_side 9277120 # Cumulative packet size per connected master and slave (bytes) +system.l1subsys2.xbar.pkt_size::total 18391936 # Cumulative packet size per connected master and slave (bytes) +system.l1subsys2.xbar.snoops 324128 # Total snoops (count) +system.l1subsys2.xbar.snoopTraffic 7056320 # Total snoop traffic (bytes) +system.l1subsys2.xbar.snoop_fanout::samples 467757 # Request fanout histogram +system.l1subsys2.xbar.snoop_fanout::mean 0.433484 # Request fanout histogram +system.l1subsys2.xbar.snoop_fanout::stdev 0.565900 # Request fanout histogram system.l1subsys2.xbar.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.l1subsys2.xbar.snoop_fanout::0 295416 67.90% 67.90% # Request fanout histogram -system.l1subsys2.xbar.snoop_fanout::1 125218 28.78% 96.68% # Request fanout histogram -system.l1subsys2.xbar.snoop_fanout::2 14440 3.32% 100.00% # Request fanout histogram +system.l1subsys2.xbar.snoop_fanout::0 282455 60.38% 60.38% # Request fanout histogram +system.l1subsys2.xbar.snoop_fanout::1 167839 35.88% 96.27% # Request fanout histogram +system.l1subsys2.xbar.snoop_fanout::2 17463 3.73% 100.00% # Request fanout histogram system.l1subsys2.xbar.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.l1subsys2.xbar.snoop_fanout::min_value 0 # Request fanout histogram system.l1subsys2.xbar.snoop_fanout::max_value 2 # Request fanout histogram -system.l1subsys2.xbar.snoop_fanout::total 435074 # Request fanout histogram -system.l1subsys2.xbar.reqLayer0.occupancy 541007805 # Layer occupancy (ticks) +system.l1subsys2.xbar.snoop_fanout::total 467757 # Request fanout histogram +system.l1subsys2.xbar.reqLayer0.occupancy 543938741 # Layer occupancy (ticks) system.l1subsys2.xbar.reqLayer0.utilization 5.4 # Layer utilization (%) -system.l1subsys2.xbar.snoopLayer0.occupancy 170855469 # Layer occupancy (ticks) -system.l1subsys2.xbar.snoopLayer0.utilization 1.7 # Layer utilization (%) -system.l1subsys2.xbar.respLayer0.occupancy 307826729 # Layer occupancy (ticks) -system.l1subsys2.xbar.respLayer0.utilization 3.1 # Layer utilization (%) -system.l1subsys2.xbar.respLayer1.occupancy 316356652 # Layer occupancy (ticks) +system.l1subsys2.xbar.snoopLayer0.occupancy 179965490 # Layer occupancy (ticks) +system.l1subsys2.xbar.snoopLayer0.utilization 1.8 # Layer utilization (%) +system.l1subsys2.xbar.respLayer0.occupancy 316289424 # Layer occupancy (ticks) +system.l1subsys2.xbar.respLayer0.utilization 3.2 # Layer utilization (%) +system.l1subsys2.xbar.respLayer1.occupancy 319642014 # Layer occupancy (ticks) system.l1subsys2.xbar.respLayer1.utilization 3.2 # Layer utilization (%) system.l2subsys0.cache0.tags.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states -system.l2subsys0.cache0.tags.replacements 33571 # number of replacements -system.l2subsys0.cache0.tags.tagsinuse 498.351113 # Cycle average of tags in use -system.l2subsys0.cache0.tags.total_refs 14579 # Total number of references to valid blocks. -system.l2subsys0.cache0.tags.sampled_refs 34078 # Sample count of references to valid blocks. -system.l2subsys0.cache0.tags.avg_refs 0.427813 # Average number of references to valid blocks. -system.l2subsys0.cache0.tags.warmup_cycle 663555000 # Cycle when the warmup percentage was hit. -system.l2subsys0.cache0.tags.occ_blocks::l2subsys0.tester 498.351113 # Average occupied blocks per requestor -system.l2subsys0.cache0.tags.occ_percent::l2subsys0.tester 0.973342 # Average percentage of cache occupancy -system.l2subsys0.cache0.tags.occ_percent::total 0.973342 # Average percentage of cache occupancy -system.l2subsys0.cache0.tags.occ_task_id_blocks::1024 507 # Occupied blocks per task id -system.l2subsys0.cache0.tags.age_task_id_blocks_1024::0 103 # Occupied blocks per task id -system.l2subsys0.cache0.tags.age_task_id_blocks_1024::1 186 # Occupied blocks per task id -system.l2subsys0.cache0.tags.age_task_id_blocks_1024::2 218 # Occupied blocks per task id -system.l2subsys0.cache0.tags.occ_task_id_percent::1024 0.990234 # Percentage of cache occupancy per task id -system.l2subsys0.cache0.tags.tag_accesses 327999 # Number of tag accesses -system.l2subsys0.cache0.tags.data_accesses 327999 # Number of data accesses +system.l2subsys0.cache0.tags.replacements 33659 # number of replacements +system.l2subsys0.cache0.tags.tagsinuse 498.694876 # Cycle average of tags in use +system.l2subsys0.cache0.tags.total_refs 11307 # Total number of references to valid blocks. +system.l2subsys0.cache0.tags.sampled_refs 34163 # Sample count of references to valid blocks. +system.l2subsys0.cache0.tags.avg_refs 0.330972 # Average number of references to valid blocks. +system.l2subsys0.cache0.tags.warmup_cycle 1001764000 # Cycle when the warmup percentage was hit. +system.l2subsys0.cache0.tags.occ_blocks::l2subsys0.tester 498.694876 # Average occupied blocks per requestor +system.l2subsys0.cache0.tags.occ_percent::l2subsys0.tester 0.974013 # Average percentage of cache occupancy +system.l2subsys0.cache0.tags.occ_percent::total 0.974013 # Average percentage of cache occupancy +system.l2subsys0.cache0.tags.occ_task_id_blocks::1024 504 # Occupied blocks per task id +system.l2subsys0.cache0.tags.age_task_id_blocks_1024::0 2 # Occupied blocks per task id +system.l2subsys0.cache0.tags.age_task_id_blocks_1024::1 346 # Occupied blocks per task id +system.l2subsys0.cache0.tags.age_task_id_blocks_1024::2 156 # Occupied blocks per task id +system.l2subsys0.cache0.tags.occ_task_id_percent::1024 0.984375 # Percentage of cache occupancy per task id +system.l2subsys0.cache0.tags.tag_accesses 325927 # Number of tag accesses +system.l2subsys0.cache0.tags.data_accesses 325927 # Number of data accesses system.l2subsys0.cache0.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states -system.l2subsys0.cache0.ReadReq_hits::l2subsys0.tester 9421 # number of ReadReq hits -system.l2subsys0.cache0.ReadReq_hits::total 9421 # number of ReadReq hits -system.l2subsys0.cache0.WriteReq_hits::l2subsys0.tester 1165 # number of WriteReq hits -system.l2subsys0.cache0.WriteReq_hits::total 1165 # number of WriteReq hits -system.l2subsys0.cache0.demand_hits::l2subsys0.tester 10586 # number of demand (read+write) hits -system.l2subsys0.cache0.demand_hits::total 10586 # number of demand (read+write) hits -system.l2subsys0.cache0.overall_hits::l2subsys0.tester 10586 # number of overall hits -system.l2subsys0.cache0.overall_hits::total 10586 # number of overall hits -system.l2subsys0.cache0.ReadReq_misses::l2subsys0.tester 34778 # number of ReadReq misses -system.l2subsys0.cache0.ReadReq_misses::total 34778 # number of ReadReq misses -system.l2subsys0.cache0.WriteReq_misses::l2subsys0.tester 23153 # number of WriteReq misses -system.l2subsys0.cache0.WriteReq_misses::total 23153 # number of WriteReq misses -system.l2subsys0.cache0.demand_misses::l2subsys0.tester 57931 # number of demand (read+write) misses -system.l2subsys0.cache0.demand_misses::total 57931 # number of demand (read+write) misses -system.l2subsys0.cache0.overall_misses::l2subsys0.tester 57931 # number of overall misses -system.l2subsys0.cache0.overall_misses::total 57931 # number of overall misses -system.l2subsys0.cache0.ReadReq_miss_latency::l2subsys0.tester 2442508704 # number of ReadReq miss cycles -system.l2subsys0.cache0.ReadReq_miss_latency::total 2442508704 # number of ReadReq miss cycles -system.l2subsys0.cache0.WriteReq_miss_latency::l2subsys0.tester 1393937168 # number of WriteReq miss cycles -system.l2subsys0.cache0.WriteReq_miss_latency::total 1393937168 # number of WriteReq miss cycles -system.l2subsys0.cache0.demand_miss_latency::l2subsys0.tester 3836445872 # number of demand (read+write) miss cycles -system.l2subsys0.cache0.demand_miss_latency::total 3836445872 # number of demand (read+write) miss cycles -system.l2subsys0.cache0.overall_miss_latency::l2subsys0.tester 3836445872 # number of overall miss cycles -system.l2subsys0.cache0.overall_miss_latency::total 3836445872 # number of overall miss cycles -system.l2subsys0.cache0.ReadReq_accesses::l2subsys0.tester 44199 # number of ReadReq accesses(hits+misses) -system.l2subsys0.cache0.ReadReq_accesses::total 44199 # number of ReadReq accesses(hits+misses) -system.l2subsys0.cache0.WriteReq_accesses::l2subsys0.tester 24318 # number of WriteReq accesses(hits+misses) -system.l2subsys0.cache0.WriteReq_accesses::total 24318 # number of WriteReq accesses(hits+misses) -system.l2subsys0.cache0.demand_accesses::l2subsys0.tester 68517 # number of demand (read+write) accesses -system.l2subsys0.cache0.demand_accesses::total 68517 # number of demand (read+write) accesses -system.l2subsys0.cache0.overall_accesses::l2subsys0.tester 68517 # number of overall (read+write) accesses -system.l2subsys0.cache0.overall_accesses::total 68517 # number of overall (read+write) accesses -system.l2subsys0.cache0.ReadReq_miss_rate::l2subsys0.tester 0.786850 # miss rate for ReadReq accesses -system.l2subsys0.cache0.ReadReq_miss_rate::total 0.786850 # miss rate for ReadReq accesses -system.l2subsys0.cache0.WriteReq_miss_rate::l2subsys0.tester 0.952093 # miss rate for WriteReq accesses -system.l2subsys0.cache0.WriteReq_miss_rate::total 0.952093 # miss rate for WriteReq accesses -system.l2subsys0.cache0.demand_miss_rate::l2subsys0.tester 0.845498 # miss rate for demand accesses -system.l2subsys0.cache0.demand_miss_rate::total 0.845498 # miss rate for demand accesses -system.l2subsys0.cache0.overall_miss_rate::l2subsys0.tester 0.845498 # miss rate for overall accesses -system.l2subsys0.cache0.overall_miss_rate::total 0.845498 # miss rate for overall accesses -system.l2subsys0.cache0.ReadReq_avg_miss_latency::l2subsys0.tester 70231.430905 # average ReadReq miss latency -system.l2subsys0.cache0.ReadReq_avg_miss_latency::total 70231.430905 # average ReadReq miss latency -system.l2subsys0.cache0.WriteReq_avg_miss_latency::l2subsys0.tester 60205.466592 # average WriteReq miss latency -system.l2subsys0.cache0.WriteReq_avg_miss_latency::total 60205.466592 # average WriteReq miss latency -system.l2subsys0.cache0.demand_avg_miss_latency::l2subsys0.tester 66224.402686 # average overall miss latency -system.l2subsys0.cache0.demand_avg_miss_latency::total 66224.402686 # average overall miss latency -system.l2subsys0.cache0.overall_avg_miss_latency::l2subsys0.tester 66224.402686 # average overall miss latency -system.l2subsys0.cache0.overall_avg_miss_latency::total 66224.402686 # average overall miss latency -system.l2subsys0.cache0.blocked_cycles::no_mshrs 26017 # number of cycles access was blocked +system.l2subsys0.cache0.ReadReq_hits::l2subsys0.tester 7262 # number of ReadReq hits +system.l2subsys0.cache0.ReadReq_hits::total 7262 # number of ReadReq hits +system.l2subsys0.cache0.WriteReq_hits::l2subsys0.tester 605 # number of WriteReq hits +system.l2subsys0.cache0.WriteReq_hits::total 605 # number of WriteReq hits +system.l2subsys0.cache0.demand_hits::l2subsys0.tester 7867 # number of demand (read+write) hits +system.l2subsys0.cache0.demand_hits::total 7867 # number of demand (read+write) hits +system.l2subsys0.cache0.overall_hits::l2subsys0.tester 7867 # number of overall hits +system.l2subsys0.cache0.overall_hits::total 7867 # number of overall hits +system.l2subsys0.cache0.ReadReq_misses::l2subsys0.tester 36028 # number of ReadReq misses +system.l2subsys0.cache0.ReadReq_misses::total 36028 # number of ReadReq misses +system.l2subsys0.cache0.WriteReq_misses::l2subsys0.tester 23553 # number of WriteReq misses +system.l2subsys0.cache0.WriteReq_misses::total 23553 # number of WriteReq misses +system.l2subsys0.cache0.demand_misses::l2subsys0.tester 59581 # number of demand (read+write) misses +system.l2subsys0.cache0.demand_misses::total 59581 # number of demand (read+write) misses +system.l2subsys0.cache0.overall_misses::l2subsys0.tester 59581 # number of overall misses +system.l2subsys0.cache0.overall_misses::total 59581 # number of overall misses +system.l2subsys0.cache0.ReadReq_miss_latency::l2subsys0.tester 2432084535 # number of ReadReq miss cycles +system.l2subsys0.cache0.ReadReq_miss_latency::total 2432084535 # number of ReadReq miss cycles +system.l2subsys0.cache0.WriteReq_miss_latency::l2subsys0.tester 1416934536 # number of WriteReq miss cycles +system.l2subsys0.cache0.WriteReq_miss_latency::total 1416934536 # number of WriteReq miss cycles +system.l2subsys0.cache0.demand_miss_latency::l2subsys0.tester 3849019071 # number of demand (read+write) miss cycles +system.l2subsys0.cache0.demand_miss_latency::total 3849019071 # number of demand (read+write) miss cycles +system.l2subsys0.cache0.overall_miss_latency::l2subsys0.tester 3849019071 # number of overall miss cycles +system.l2subsys0.cache0.overall_miss_latency::total 3849019071 # number of overall miss cycles +system.l2subsys0.cache0.ReadReq_accesses::l2subsys0.tester 43290 # number of ReadReq accesses(hits+misses) +system.l2subsys0.cache0.ReadReq_accesses::total 43290 # number of ReadReq accesses(hits+misses) +system.l2subsys0.cache0.WriteReq_accesses::l2subsys0.tester 24158 # number of WriteReq accesses(hits+misses) +system.l2subsys0.cache0.WriteReq_accesses::total 24158 # number of WriteReq accesses(hits+misses) +system.l2subsys0.cache0.demand_accesses::l2subsys0.tester 67448 # number of demand (read+write) accesses +system.l2subsys0.cache0.demand_accesses::total 67448 # number of demand (read+write) accesses +system.l2subsys0.cache0.overall_accesses::l2subsys0.tester 67448 # number of overall (read+write) accesses +system.l2subsys0.cache0.overall_accesses::total 67448 # number of overall (read+write) accesses +system.l2subsys0.cache0.ReadReq_miss_rate::l2subsys0.tester 0.832248 # miss rate for ReadReq accesses +system.l2subsys0.cache0.ReadReq_miss_rate::total 0.832248 # miss rate for ReadReq accesses +system.l2subsys0.cache0.WriteReq_miss_rate::l2subsys0.tester 0.974957 # miss rate for WriteReq accesses +system.l2subsys0.cache0.WriteReq_miss_rate::total 0.974957 # miss rate for WriteReq accesses +system.l2subsys0.cache0.demand_miss_rate::l2subsys0.tester 0.883362 # miss rate for demand accesses +system.l2subsys0.cache0.demand_miss_rate::total 0.883362 # miss rate for demand accesses +system.l2subsys0.cache0.overall_miss_rate::l2subsys0.tester 0.883362 # miss rate for overall accesses +system.l2subsys0.cache0.overall_miss_rate::total 0.883362 # miss rate for overall accesses +system.l2subsys0.cache0.ReadReq_avg_miss_latency::l2subsys0.tester 67505.399550 # average ReadReq miss latency +system.l2subsys0.cache0.ReadReq_avg_miss_latency::total 67505.399550 # average ReadReq miss latency +system.l2subsys0.cache0.WriteReq_avg_miss_latency::l2subsys0.tester 60159.407974 # average WriteReq miss latency +system.l2subsys0.cache0.WriteReq_avg_miss_latency::total 60159.407974 # average WriteReq miss latency +system.l2subsys0.cache0.demand_avg_miss_latency::l2subsys0.tester 64601.451318 # average overall miss latency +system.l2subsys0.cache0.demand_avg_miss_latency::total 64601.451318 # average overall miss latency +system.l2subsys0.cache0.overall_avg_miss_latency::l2subsys0.tester 64601.451318 # average overall miss latency +system.l2subsys0.cache0.overall_avg_miss_latency::total 64601.451318 # average overall miss latency +system.l2subsys0.cache0.blocked_cycles::no_mshrs 22051 # number of cycles access was blocked system.l2subsys0.cache0.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2subsys0.cache0.blocked::no_mshrs 506 # number of cycles access was blocked +system.l2subsys0.cache0.blocked::no_mshrs 434 # number of cycles access was blocked system.l2subsys0.cache0.blocked::no_targets 0 # number of cycles access was blocked -system.l2subsys0.cache0.avg_blocked_cycles::no_mshrs 51.416996 # average number of cycles each access was blocked +system.l2subsys0.cache0.avg_blocked_cycles::no_mshrs 50.808756 # average number of cycles each access was blocked system.l2subsys0.cache0.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.l2subsys0.cache0.writebacks::writebacks 11870 # number of writebacks -system.l2subsys0.cache0.writebacks::total 11870 # number of writebacks -system.l2subsys0.cache0.ReadReq_mshr_hits::l2subsys0.tester 3 # number of ReadReq MSHR hits -system.l2subsys0.cache0.ReadReq_mshr_hits::total 3 # number of ReadReq MSHR hits -system.l2subsys0.cache0.WriteReq_mshr_hits::l2subsys0.tester 5 # number of WriteReq MSHR hits -system.l2subsys0.cache0.WriteReq_mshr_hits::total 5 # number of WriteReq MSHR hits -system.l2subsys0.cache0.demand_mshr_hits::l2subsys0.tester 8 # number of demand (read+write) MSHR hits -system.l2subsys0.cache0.demand_mshr_hits::total 8 # number of demand (read+write) MSHR hits -system.l2subsys0.cache0.overall_mshr_hits::l2subsys0.tester 8 # number of overall MSHR hits -system.l2subsys0.cache0.overall_mshr_hits::total 8 # number of overall MSHR hits -system.l2subsys0.cache0.ReadReq_mshr_misses::l2subsys0.tester 34775 # number of ReadReq MSHR misses -system.l2subsys0.cache0.ReadReq_mshr_misses::total 34775 # number of ReadReq MSHR misses -system.l2subsys0.cache0.WriteReq_mshr_misses::l2subsys0.tester 23148 # number of WriteReq MSHR misses -system.l2subsys0.cache0.WriteReq_mshr_misses::total 23148 # number of WriteReq MSHR misses -system.l2subsys0.cache0.demand_mshr_misses::l2subsys0.tester 57923 # number of demand (read+write) MSHR misses -system.l2subsys0.cache0.demand_mshr_misses::total 57923 # number of demand (read+write) MSHR misses -system.l2subsys0.cache0.overall_mshr_misses::l2subsys0.tester 57923 # number of overall MSHR misses -system.l2subsys0.cache0.overall_mshr_misses::total 57923 # number of overall MSHR misses -system.l2subsys0.cache0.ReadReq_mshr_miss_latency::l2subsys0.tester 2407714740 # number of ReadReq MSHR miss cycles -system.l2subsys0.cache0.ReadReq_mshr_miss_latency::total 2407714740 # number of ReadReq MSHR miss cycles -system.l2subsys0.cache0.WriteReq_mshr_miss_latency::l2subsys0.tester 1370739559 # number of WriteReq MSHR miss cycles -system.l2subsys0.cache0.WriteReq_mshr_miss_latency::total 1370739559 # number of WriteReq MSHR miss cycles -system.l2subsys0.cache0.demand_mshr_miss_latency::l2subsys0.tester 3778454299 # number of demand (read+write) MSHR miss cycles -system.l2subsys0.cache0.demand_mshr_miss_latency::total 3778454299 # number of demand (read+write) MSHR miss cycles -system.l2subsys0.cache0.overall_mshr_miss_latency::l2subsys0.tester 3778454299 # number of overall MSHR miss cycles -system.l2subsys0.cache0.overall_mshr_miss_latency::total 3778454299 # number of overall MSHR miss cycles -system.l2subsys0.cache0.ReadReq_mshr_miss_rate::l2subsys0.tester 0.786783 # mshr miss rate for ReadReq accesses -system.l2subsys0.cache0.ReadReq_mshr_miss_rate::total 0.786783 # mshr miss rate for ReadReq accesses -system.l2subsys0.cache0.WriteReq_mshr_miss_rate::l2subsys0.tester 0.951887 # mshr miss rate for WriteReq accesses -system.l2subsys0.cache0.WriteReq_mshr_miss_rate::total 0.951887 # mshr miss rate for WriteReq accesses -system.l2subsys0.cache0.demand_mshr_miss_rate::l2subsys0.tester 0.845381 # mshr miss rate for demand accesses -system.l2subsys0.cache0.demand_mshr_miss_rate::total 0.845381 # mshr miss rate for demand accesses -system.l2subsys0.cache0.overall_mshr_miss_rate::l2subsys0.tester 0.845381 # mshr miss rate for overall accesses -system.l2subsys0.cache0.overall_mshr_miss_rate::total 0.845381 # mshr miss rate for overall accesses -system.l2subsys0.cache0.ReadReq_avg_mshr_miss_latency::l2subsys0.tester 69236.944357 # average ReadReq mshr miss latency -system.l2subsys0.cache0.ReadReq_avg_mshr_miss_latency::total 69236.944357 # average ReadReq mshr miss latency -system.l2subsys0.cache0.WriteReq_avg_mshr_miss_latency::l2subsys0.tester 59216.327933 # average WriteReq mshr miss latency -system.l2subsys0.cache0.WriteReq_avg_mshr_miss_latency::total 59216.327933 # average WriteReq mshr miss latency -system.l2subsys0.cache0.demand_avg_mshr_miss_latency::l2subsys0.tester 65232.365364 # average overall mshr miss latency -system.l2subsys0.cache0.demand_avg_mshr_miss_latency::total 65232.365364 # average overall mshr miss latency -system.l2subsys0.cache0.overall_avg_mshr_miss_latency::l2subsys0.tester 65232.365364 # average overall mshr miss latency -system.l2subsys0.cache0.overall_avg_mshr_miss_latency::total 65232.365364 # average overall mshr miss latency +system.l2subsys0.cache0.writebacks::writebacks 12098 # number of writebacks +system.l2subsys0.cache0.writebacks::total 12098 # number of writebacks +system.l2subsys0.cache0.ReadReq_mshr_hits::l2subsys0.tester 8 # number of ReadReq MSHR hits +system.l2subsys0.cache0.ReadReq_mshr_hits::total 8 # number of ReadReq MSHR hits +system.l2subsys0.cache0.WriteReq_mshr_hits::l2subsys0.tester 6 # number of WriteReq MSHR hits +system.l2subsys0.cache0.WriteReq_mshr_hits::total 6 # number of WriteReq MSHR hits +system.l2subsys0.cache0.demand_mshr_hits::l2subsys0.tester 14 # number of demand (read+write) MSHR hits +system.l2subsys0.cache0.demand_mshr_hits::total 14 # number of demand (read+write) MSHR hits +system.l2subsys0.cache0.overall_mshr_hits::l2subsys0.tester 14 # number of overall MSHR hits +system.l2subsys0.cache0.overall_mshr_hits::total 14 # number of overall MSHR hits +system.l2subsys0.cache0.ReadReq_mshr_misses::l2subsys0.tester 36020 # number of ReadReq MSHR misses +system.l2subsys0.cache0.ReadReq_mshr_misses::total 36020 # number of ReadReq MSHR misses +system.l2subsys0.cache0.WriteReq_mshr_misses::l2subsys0.tester 23547 # number of WriteReq MSHR misses +system.l2subsys0.cache0.WriteReq_mshr_misses::total 23547 # number of WriteReq MSHR misses +system.l2subsys0.cache0.demand_mshr_misses::l2subsys0.tester 59567 # number of demand (read+write) MSHR misses +system.l2subsys0.cache0.demand_mshr_misses::total 59567 # number of demand (read+write) MSHR misses +system.l2subsys0.cache0.overall_mshr_misses::l2subsys0.tester 59567 # number of overall MSHR misses +system.l2subsys0.cache0.overall_mshr_misses::total 59567 # number of overall MSHR misses +system.l2subsys0.cache0.ReadReq_mshr_miss_latency::l2subsys0.tester 2396005584 # number of ReadReq MSHR miss cycles +system.l2subsys0.cache0.ReadReq_mshr_miss_latency::total 2396005584 # number of ReadReq MSHR miss cycles +system.l2subsys0.cache0.WriteReq_mshr_miss_latency::l2subsys0.tester 1393365242 # number of WriteReq MSHR miss cycles +system.l2subsys0.cache0.WriteReq_mshr_miss_latency::total 1393365242 # number of WriteReq MSHR miss cycles +system.l2subsys0.cache0.demand_mshr_miss_latency::l2subsys0.tester 3789370826 # number of demand (read+write) MSHR miss cycles +system.l2subsys0.cache0.demand_mshr_miss_latency::total 3789370826 # number of demand (read+write) MSHR miss cycles +system.l2subsys0.cache0.overall_mshr_miss_latency::l2subsys0.tester 3789370826 # number of overall MSHR miss cycles +system.l2subsys0.cache0.overall_mshr_miss_latency::total 3789370826 # number of overall MSHR miss cycles +system.l2subsys0.cache0.ReadReq_mshr_miss_rate::l2subsys0.tester 0.832063 # mshr miss rate for ReadReq accesses +system.l2subsys0.cache0.ReadReq_mshr_miss_rate::total 0.832063 # mshr miss rate for ReadReq accesses +system.l2subsys0.cache0.WriteReq_mshr_miss_rate::l2subsys0.tester 0.974708 # mshr miss rate for WriteReq accesses +system.l2subsys0.cache0.WriteReq_mshr_miss_rate::total 0.974708 # mshr miss rate for WriteReq accesses +system.l2subsys0.cache0.demand_mshr_miss_rate::l2subsys0.tester 0.883154 # mshr miss rate for demand accesses +system.l2subsys0.cache0.demand_mshr_miss_rate::total 0.883154 # mshr miss rate for demand accesses +system.l2subsys0.cache0.overall_mshr_miss_rate::l2subsys0.tester 0.883154 # mshr miss rate for overall accesses +system.l2subsys0.cache0.overall_mshr_miss_rate::total 0.883154 # mshr miss rate for overall accesses +system.l2subsys0.cache0.ReadReq_avg_mshr_miss_latency::l2subsys0.tester 66518.755802 # average ReadReq mshr miss latency +system.l2subsys0.cache0.ReadReq_avg_mshr_miss_latency::total 66518.755802 # average ReadReq mshr miss latency +system.l2subsys0.cache0.WriteReq_avg_mshr_miss_latency::l2subsys0.tester 59173.790377 # average WriteReq mshr miss latency +system.l2subsys0.cache0.WriteReq_avg_mshr_miss_latency::total 59173.790377 # average WriteReq mshr miss latency +system.l2subsys0.cache0.demand_avg_mshr_miss_latency::l2subsys0.tester 63615.270636 # average overall mshr miss latency +system.l2subsys0.cache0.demand_avg_mshr_miss_latency::total 63615.270636 # average overall mshr miss latency +system.l2subsys0.cache0.overall_avg_mshr_miss_latency::l2subsys0.tester 63615.270636 # average overall mshr miss latency +system.l2subsys0.cache0.overall_avg_mshr_miss_latency::total 63615.270636 # average overall mshr miss latency system.l2subsys0.cache1.tags.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states -system.l2subsys0.cache1.tags.replacements 134581 # number of replacements -system.l2subsys0.cache1.tags.tagsinuse 1490.708088 # Cycle average of tags in use -system.l2subsys0.cache1.tags.total_refs 68619 # Total number of references to valid blocks. -system.l2subsys0.cache1.tags.sampled_refs 136082 # Sample count of references to valid blocks. -system.l2subsys0.cache1.tags.avg_refs 0.504247 # Average number of references to valid blocks. -system.l2subsys0.cache1.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2subsys0.cache1.tags.occ_blocks::writebacks 429.815840 # Average occupied blocks per requestor -system.l2subsys0.cache1.tags.occ_blocks::l0subsys0.tester0 261.351611 # Average occupied blocks per requestor -system.l2subsys0.cache1.tags.occ_blocks::l0subsys0.tester1 262.808878 # Average occupied blocks per requestor -system.l2subsys0.cache1.tags.occ_blocks::l0subsys1.tester0 256.750011 # Average occupied blocks per requestor -system.l2subsys0.cache1.tags.occ_blocks::l0subsys1.tester1 279.981748 # Average occupied blocks per requestor -system.l2subsys0.cache1.tags.occ_percent::writebacks 0.279828 # Average percentage of cache occupancy -system.l2subsys0.cache1.tags.occ_percent::l0subsys0.tester0 0.170151 # Average percentage of cache occupancy -system.l2subsys0.cache1.tags.occ_percent::l0subsys0.tester1 0.171100 # Average percentage of cache occupancy -system.l2subsys0.cache1.tags.occ_percent::l0subsys1.tester0 0.167155 # Average percentage of cache occupancy -system.l2subsys0.cache1.tags.occ_percent::l0subsys1.tester1 0.182280 # Average percentage of cache occupancy -system.l2subsys0.cache1.tags.occ_percent::total 0.970513 # Average percentage of cache occupancy -system.l2subsys0.cache1.tags.occ_task_id_blocks::1024 1501 # Occupied blocks per task id -system.l2subsys0.cache1.tags.age_task_id_blocks_1024::0 191 # Occupied blocks per task id -system.l2subsys0.cache1.tags.age_task_id_blocks_1024::1 848 # Occupied blocks per task id -system.l2subsys0.cache1.tags.age_task_id_blocks_1024::2 462 # Occupied blocks per task id -system.l2subsys0.cache1.tags.occ_task_id_percent::1024 0.977214 # Percentage of cache occupancy per task id -system.l2subsys0.cache1.tags.tag_accesses 4309680 # Number of tag accesses -system.l2subsys0.cache1.tags.data_accesses 4309680 # Number of data accesses +system.l2subsys0.cache1.tags.replacements 151853 # number of replacements +system.l2subsys0.cache1.tags.tagsinuse 1524.082956 # Cycle average of tags in use +system.l2subsys0.cache1.tags.total_refs 82258 # Total number of references to valid blocks. +system.l2subsys0.cache1.tags.sampled_refs 153387 # Sample count of references to valid blocks. +system.l2subsys0.cache1.tags.avg_refs 0.536278 # Average number of references to valid blocks. +system.l2subsys0.cache1.tags.warmup_cycle 439051000 # Cycle when the warmup percentage was hit. +system.l2subsys0.cache1.tags.occ_blocks::writebacks 190.667622 # Average occupied blocks per requestor +system.l2subsys0.cache1.tags.occ_blocks::l0subsys0.tester0 328.055957 # Average occupied blocks per requestor +system.l2subsys0.cache1.tags.occ_blocks::l0subsys0.tester1 322.496146 # Average occupied blocks per requestor +system.l2subsys0.cache1.tags.occ_blocks::l0subsys1.tester0 335.799241 # Average occupied blocks per requestor +system.l2subsys0.cache1.tags.occ_blocks::l0subsys1.tester1 347.063989 # Average occupied blocks per requestor +system.l2subsys0.cache1.tags.occ_percent::writebacks 0.124133 # Average percentage of cache occupancy +system.l2subsys0.cache1.tags.occ_percent::l0subsys0.tester0 0.213578 # Average percentage of cache occupancy +system.l2subsys0.cache1.tags.occ_percent::l0subsys0.tester1 0.209958 # Average percentage of cache occupancy +system.l2subsys0.cache1.tags.occ_percent::l0subsys1.tester0 0.218619 # Average percentage of cache occupancy +system.l2subsys0.cache1.tags.occ_percent::l0subsys1.tester1 0.225953 # Average percentage of cache occupancy +system.l2subsys0.cache1.tags.occ_percent::total 0.992242 # Average percentage of cache occupancy +system.l2subsys0.cache1.tags.occ_task_id_blocks::1024 1534 # Occupied blocks per task id +system.l2subsys0.cache1.tags.age_task_id_blocks_1024::0 135 # Occupied blocks per task id +system.l2subsys0.cache1.tags.age_task_id_blocks_1024::1 1102 # Occupied blocks per task id +system.l2subsys0.cache1.tags.age_task_id_blocks_1024::2 297 # Occupied blocks per task id +system.l2subsys0.cache1.tags.occ_task_id_percent::1024 0.998698 # Percentage of cache occupancy per task id +system.l2subsys0.cache1.tags.tag_accesses 4165543 # Number of tag accesses +system.l2subsys0.cache1.tags.data_accesses 4165543 # Number of data accesses system.l2subsys0.cache1.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states -system.l2subsys0.cache1.WritebackDirty_hits::writebacks 48994 # number of WritebackDirty hits -system.l2subsys0.cache1.WritebackDirty_hits::total 48994 # number of WritebackDirty hits -system.l2subsys0.cache1.ReadExReq_hits::l0subsys0.tester0 45 # number of ReadExReq hits -system.l2subsys0.cache1.ReadExReq_hits::l0subsys0.tester1 48 # number of ReadExReq hits -system.l2subsys0.cache1.ReadExReq_hits::l0subsys1.tester0 49 # number of ReadExReq hits -system.l2subsys0.cache1.ReadExReq_hits::l0subsys1.tester1 69 # number of ReadExReq hits -system.l2subsys0.cache1.ReadExReq_hits::total 211 # number of ReadExReq hits -system.l2subsys0.cache1.ReadSharedReq_hits::l0subsys0.tester0 593 # number of ReadSharedReq hits -system.l2subsys0.cache1.ReadSharedReq_hits::l0subsys0.tester1 551 # number of ReadSharedReq hits -system.l2subsys0.cache1.ReadSharedReq_hits::l0subsys1.tester0 635 # number of ReadSharedReq hits -system.l2subsys0.cache1.ReadSharedReq_hits::l0subsys1.tester1 706 # number of ReadSharedReq hits -system.l2subsys0.cache1.ReadSharedReq_hits::total 2485 # number of ReadSharedReq hits -system.l2subsys0.cache1.demand_hits::l0subsys0.tester0 638 # number of demand (read+write) hits -system.l2subsys0.cache1.demand_hits::l0subsys0.tester1 599 # number of demand (read+write) hits -system.l2subsys0.cache1.demand_hits::l0subsys1.tester0 684 # number of demand (read+write) hits -system.l2subsys0.cache1.demand_hits::l0subsys1.tester1 775 # number of demand (read+write) hits -system.l2subsys0.cache1.demand_hits::total 2696 # number of demand (read+write) hits -system.l2subsys0.cache1.overall_hits::l0subsys0.tester0 638 # number of overall hits -system.l2subsys0.cache1.overall_hits::l0subsys0.tester1 599 # number of overall hits -system.l2subsys0.cache1.overall_hits::l0subsys1.tester0 684 # number of overall hits -system.l2subsys0.cache1.overall_hits::l0subsys1.tester1 775 # number of overall hits -system.l2subsys0.cache1.overall_hits::total 2696 # number of overall hits -system.l2subsys0.cache1.UpgradeReq_misses::l0subsys0.tester0 3840 # number of UpgradeReq misses -system.l2subsys0.cache1.UpgradeReq_misses::l0subsys0.tester1 3889 # number of UpgradeReq misses -system.l2subsys0.cache1.UpgradeReq_misses::l0subsys1.tester0 3668 # number of UpgradeReq misses -system.l2subsys0.cache1.UpgradeReq_misses::l0subsys1.tester1 3541 # number of UpgradeReq misses -system.l2subsys0.cache1.UpgradeReq_misses::total 14938 # number of UpgradeReq misses -system.l2subsys0.cache1.ReadExReq_misses::l0subsys0.tester0 17049 # number of ReadExReq misses -system.l2subsys0.cache1.ReadExReq_misses::l0subsys0.tester1 17258 # number of ReadExReq misses -system.l2subsys0.cache1.ReadExReq_misses::l0subsys1.tester0 16261 # number of ReadExReq misses -system.l2subsys0.cache1.ReadExReq_misses::l0subsys1.tester1 17121 # number of ReadExReq misses -system.l2subsys0.cache1.ReadExReq_misses::total 67689 # number of ReadExReq misses -system.l2subsys0.cache1.ReadSharedReq_misses::l0subsys0.tester0 29631 # number of ReadSharedReq misses -system.l2subsys0.cache1.ReadSharedReq_misses::l0subsys0.tester1 29938 # number of ReadSharedReq misses -system.l2subsys0.cache1.ReadSharedReq_misses::l0subsys1.tester0 28534 # number of ReadSharedReq misses -system.l2subsys0.cache1.ReadSharedReq_misses::l0subsys1.tester1 30125 # number of ReadSharedReq misses -system.l2subsys0.cache1.ReadSharedReq_misses::total 118228 # number of ReadSharedReq misses -system.l2subsys0.cache1.demand_misses::l0subsys0.tester0 46680 # number of demand (read+write) misses -system.l2subsys0.cache1.demand_misses::l0subsys0.tester1 47196 # number of demand (read+write) misses -system.l2subsys0.cache1.demand_misses::l0subsys1.tester0 44795 # number of demand (read+write) misses -system.l2subsys0.cache1.demand_misses::l0subsys1.tester1 47246 # number of demand (read+write) misses -system.l2subsys0.cache1.demand_misses::total 185917 # number of demand (read+write) misses -system.l2subsys0.cache1.overall_misses::l0subsys0.tester0 46680 # number of overall misses -system.l2subsys0.cache1.overall_misses::l0subsys0.tester1 47196 # number of overall misses -system.l2subsys0.cache1.overall_misses::l0subsys1.tester0 44795 # number of overall misses -system.l2subsys0.cache1.overall_misses::l0subsys1.tester1 47246 # number of overall misses -system.l2subsys0.cache1.overall_misses::total 185917 # number of overall misses -system.l2subsys0.cache1.UpgradeReq_miss_latency::l0subsys0.tester0 66953620 # number of UpgradeReq miss cycles -system.l2subsys0.cache1.UpgradeReq_miss_latency::l0subsys0.tester1 64831058 # number of UpgradeReq miss cycles -system.l2subsys0.cache1.UpgradeReq_miss_latency::l0subsys1.tester0 65919546 # number of UpgradeReq miss cycles -system.l2subsys0.cache1.UpgradeReq_miss_latency::l0subsys1.tester1 63268681 # number of UpgradeReq miss cycles -system.l2subsys0.cache1.UpgradeReq_miss_latency::total 260972905 # number of UpgradeReq miss cycles -system.l2subsys0.cache1.ReadExReq_miss_latency::l0subsys0.tester0 1641905219 # number of ReadExReq miss cycles -system.l2subsys0.cache1.ReadExReq_miss_latency::l0subsys0.tester1 1650456796 # number of ReadExReq miss cycles -system.l2subsys0.cache1.ReadExReq_miss_latency::l0subsys1.tester0 1582415666 # number of ReadExReq miss cycles -system.l2subsys0.cache1.ReadExReq_miss_latency::l0subsys1.tester1 1694756023 # number of ReadExReq miss cycles -system.l2subsys0.cache1.ReadExReq_miss_latency::total 6569533704 # number of ReadExReq miss cycles -system.l2subsys0.cache1.ReadSharedReq_miss_latency::l0subsys0.tester0 2850992349 # number of ReadSharedReq miss cycles -system.l2subsys0.cache1.ReadSharedReq_miss_latency::l0subsys0.tester1 2862959666 # number of ReadSharedReq miss cycles -system.l2subsys0.cache1.ReadSharedReq_miss_latency::l0subsys1.tester0 2786932114 # number of ReadSharedReq miss cycles -system.l2subsys0.cache1.ReadSharedReq_miss_latency::l0subsys1.tester1 3012471447 # number of ReadSharedReq miss cycles -system.l2subsys0.cache1.ReadSharedReq_miss_latency::total 11513355576 # number of ReadSharedReq miss cycles -system.l2subsys0.cache1.demand_miss_latency::l0subsys0.tester0 4492897568 # number of demand (read+write) miss cycles -system.l2subsys0.cache1.demand_miss_latency::l0subsys0.tester1 4513416462 # number of demand (read+write) miss cycles -system.l2subsys0.cache1.demand_miss_latency::l0subsys1.tester0 4369347780 # number of demand (read+write) miss cycles -system.l2subsys0.cache1.demand_miss_latency::l0subsys1.tester1 4707227470 # number of demand (read+write) miss cycles -system.l2subsys0.cache1.demand_miss_latency::total 18082889280 # number of demand (read+write) miss cycles -system.l2subsys0.cache1.overall_miss_latency::l0subsys0.tester0 4492897568 # number of overall miss cycles -system.l2subsys0.cache1.overall_miss_latency::l0subsys0.tester1 4513416462 # number of overall miss cycles -system.l2subsys0.cache1.overall_miss_latency::l0subsys1.tester0 4369347780 # number of overall miss cycles -system.l2subsys0.cache1.overall_miss_latency::l0subsys1.tester1 4707227470 # number of overall miss cycles -system.l2subsys0.cache1.overall_miss_latency::total 18082889280 # number of overall miss cycles -system.l2subsys0.cache1.WritebackDirty_accesses::writebacks 48994 # number of WritebackDirty accesses(hits+misses) -system.l2subsys0.cache1.WritebackDirty_accesses::total 48994 # number of WritebackDirty accesses(hits+misses) -system.l2subsys0.cache1.UpgradeReq_accesses::l0subsys0.tester0 3840 # number of UpgradeReq accesses(hits+misses) -system.l2subsys0.cache1.UpgradeReq_accesses::l0subsys0.tester1 3889 # number of UpgradeReq accesses(hits+misses) -system.l2subsys0.cache1.UpgradeReq_accesses::l0subsys1.tester0 3668 # number of UpgradeReq accesses(hits+misses) -system.l2subsys0.cache1.UpgradeReq_accesses::l0subsys1.tester1 3541 # number of UpgradeReq accesses(hits+misses) -system.l2subsys0.cache1.UpgradeReq_accesses::total 14938 # number of UpgradeReq accesses(hits+misses) -system.l2subsys0.cache1.ReadExReq_accesses::l0subsys0.tester0 17094 # number of ReadExReq accesses(hits+misses) -system.l2subsys0.cache1.ReadExReq_accesses::l0subsys0.tester1 17306 # number of ReadExReq accesses(hits+misses) -system.l2subsys0.cache1.ReadExReq_accesses::l0subsys1.tester0 16310 # number of ReadExReq accesses(hits+misses) -system.l2subsys0.cache1.ReadExReq_accesses::l0subsys1.tester1 17190 # number of ReadExReq accesses(hits+misses) -system.l2subsys0.cache1.ReadExReq_accesses::total 67900 # number of ReadExReq accesses(hits+misses) -system.l2subsys0.cache1.ReadSharedReq_accesses::l0subsys0.tester0 30224 # number of ReadSharedReq accesses(hits+misses) -system.l2subsys0.cache1.ReadSharedReq_accesses::l0subsys0.tester1 30489 # number of ReadSharedReq accesses(hits+misses) -system.l2subsys0.cache1.ReadSharedReq_accesses::l0subsys1.tester0 29169 # number of ReadSharedReq accesses(hits+misses) -system.l2subsys0.cache1.ReadSharedReq_accesses::l0subsys1.tester1 30831 # number of ReadSharedReq accesses(hits+misses) -system.l2subsys0.cache1.ReadSharedReq_accesses::total 120713 # number of ReadSharedReq accesses(hits+misses) -system.l2subsys0.cache1.demand_accesses::l0subsys0.tester0 47318 # number of demand (read+write) accesses -system.l2subsys0.cache1.demand_accesses::l0subsys0.tester1 47795 # number of demand (read+write) accesses -system.l2subsys0.cache1.demand_accesses::l0subsys1.tester0 45479 # number of demand (read+write) accesses -system.l2subsys0.cache1.demand_accesses::l0subsys1.tester1 48021 # number of demand (read+write) accesses -system.l2subsys0.cache1.demand_accesses::total 188613 # number of demand (read+write) accesses -system.l2subsys0.cache1.overall_accesses::l0subsys0.tester0 47318 # number of overall (read+write) accesses -system.l2subsys0.cache1.overall_accesses::l0subsys0.tester1 47795 # number of overall (read+write) accesses -system.l2subsys0.cache1.overall_accesses::l0subsys1.tester0 45479 # number of overall (read+write) accesses -system.l2subsys0.cache1.overall_accesses::l0subsys1.tester1 48021 # number of overall (read+write) accesses -system.l2subsys0.cache1.overall_accesses::total 188613 # number of overall (read+write) accesses -system.l2subsys0.cache1.UpgradeReq_miss_rate::l0subsys0.tester0 1 # miss rate for UpgradeReq accesses -system.l2subsys0.cache1.UpgradeReq_miss_rate::l0subsys0.tester1 1 # miss rate for UpgradeReq accesses -system.l2subsys0.cache1.UpgradeReq_miss_rate::l0subsys1.tester0 1 # miss rate for UpgradeReq accesses -system.l2subsys0.cache1.UpgradeReq_miss_rate::l0subsys1.tester1 1 # miss rate for UpgradeReq accesses -system.l2subsys0.cache1.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses -system.l2subsys0.cache1.ReadExReq_miss_rate::l0subsys0.tester0 0.997367 # miss rate for ReadExReq accesses -system.l2subsys0.cache1.ReadExReq_miss_rate::l0subsys0.tester1 0.997226 # miss rate for ReadExReq accesses -system.l2subsys0.cache1.ReadExReq_miss_rate::l0subsys1.tester0 0.996996 # miss rate for ReadExReq accesses -system.l2subsys0.cache1.ReadExReq_miss_rate::l0subsys1.tester1 0.995986 # miss rate for ReadExReq accesses -system.l2subsys0.cache1.ReadExReq_miss_rate::total 0.996892 # miss rate for ReadExReq accesses -system.l2subsys0.cache1.ReadSharedReq_miss_rate::l0subsys0.tester0 0.980380 # miss rate for ReadSharedReq accesses -system.l2subsys0.cache1.ReadSharedReq_miss_rate::l0subsys0.tester1 0.981928 # miss rate for ReadSharedReq accesses -system.l2subsys0.cache1.ReadSharedReq_miss_rate::l0subsys1.tester0 0.978230 # miss rate for ReadSharedReq accesses -system.l2subsys0.cache1.ReadSharedReq_miss_rate::l0subsys1.tester1 0.977101 # miss rate for ReadSharedReq accesses -system.l2subsys0.cache1.ReadSharedReq_miss_rate::total 0.979414 # miss rate for ReadSharedReq accesses -system.l2subsys0.cache1.demand_miss_rate::l0subsys0.tester0 0.986517 # miss rate for demand accesses -system.l2subsys0.cache1.demand_miss_rate::l0subsys0.tester1 0.987467 # miss rate for demand accesses -system.l2subsys0.cache1.demand_miss_rate::l0subsys1.tester0 0.984960 # miss rate for demand accesses -system.l2subsys0.cache1.demand_miss_rate::l0subsys1.tester1 0.983861 # miss rate for demand accesses -system.l2subsys0.cache1.demand_miss_rate::total 0.985706 # miss rate for demand accesses -system.l2subsys0.cache1.overall_miss_rate::l0subsys0.tester0 0.986517 # miss rate for overall accesses -system.l2subsys0.cache1.overall_miss_rate::l0subsys0.tester1 0.987467 # miss rate for overall accesses -system.l2subsys0.cache1.overall_miss_rate::l0subsys1.tester0 0.984960 # miss rate for overall accesses -system.l2subsys0.cache1.overall_miss_rate::l0subsys1.tester1 0.983861 # miss rate for overall accesses -system.l2subsys0.cache1.overall_miss_rate::total 0.985706 # miss rate for overall accesses -system.l2subsys0.cache1.UpgradeReq_avg_miss_latency::l0subsys0.tester0 17435.838542 # average UpgradeReq miss latency -system.l2subsys0.cache1.UpgradeReq_avg_miss_latency::l0subsys0.tester1 16670.367190 # average UpgradeReq miss latency -system.l2subsys0.cache1.UpgradeReq_avg_miss_latency::l0subsys1.tester0 17971.522901 # average UpgradeReq miss latency -system.l2subsys0.cache1.UpgradeReq_avg_miss_latency::l0subsys1.tester1 17867.461452 # average UpgradeReq miss latency -system.l2subsys0.cache1.UpgradeReq_avg_miss_latency::total 17470.404673 # average UpgradeReq miss latency -system.l2subsys0.cache1.ReadExReq_avg_miss_latency::l0subsys0.tester0 96305.074726 # average ReadExReq miss latency -system.l2subsys0.cache1.ReadExReq_avg_miss_latency::l0subsys0.tester1 95634.302700 # average ReadExReq miss latency -system.l2subsys0.cache1.ReadExReq_avg_miss_latency::l0subsys1.tester0 97313.551811 # average ReadExReq miss latency -system.l2subsys0.cache1.ReadExReq_avg_miss_latency::l0subsys1.tester1 98986.976403 # average ReadExReq miss latency -system.l2subsys0.cache1.ReadExReq_avg_miss_latency::total 97054.672162 # average ReadExReq miss latency -system.l2subsys0.cache1.ReadSharedReq_avg_miss_latency::l0subsys0.tester0 96216.541764 # average ReadSharedReq miss latency -system.l2subsys0.cache1.ReadSharedReq_avg_miss_latency::l0subsys0.tester1 95629.623422 # average ReadSharedReq miss latency -system.l2subsys0.cache1.ReadSharedReq_avg_miss_latency::l0subsys1.tester0 97670.572440 # average ReadSharedReq miss latency -system.l2subsys0.cache1.ReadSharedReq_avg_miss_latency::l0subsys1.tester1 99999.052183 # average ReadSharedReq miss latency -system.l2subsys0.cache1.ReadSharedReq_avg_miss_latency::total 97382.646886 # average ReadSharedReq miss latency -system.l2subsys0.cache1.demand_avg_miss_latency::l0subsys0.tester0 96248.876778 # average overall miss latency -system.l2subsys0.cache1.demand_avg_miss_latency::l0subsys0.tester1 95631.334477 # average overall miss latency -system.l2subsys0.cache1.demand_avg_miss_latency::l0subsys1.tester0 97540.970644 # average overall miss latency -system.l2subsys0.cache1.demand_avg_miss_latency::l0subsys1.tester1 99632.296279 # average overall miss latency -system.l2subsys0.cache1.demand_avg_miss_latency::total 97263.237251 # average overall miss latency -system.l2subsys0.cache1.overall_avg_miss_latency::l0subsys0.tester0 96248.876778 # average overall miss latency -system.l2subsys0.cache1.overall_avg_miss_latency::l0subsys0.tester1 95631.334477 # average overall miss latency -system.l2subsys0.cache1.overall_avg_miss_latency::l0subsys1.tester0 97540.970644 # average overall miss latency -system.l2subsys0.cache1.overall_avg_miss_latency::l0subsys1.tester1 99632.296279 # average overall miss latency -system.l2subsys0.cache1.overall_avg_miss_latency::total 97263.237251 # average overall miss latency +system.l2subsys0.cache1.WritebackDirty_hits::writebacks 46587 # number of WritebackDirty hits +system.l2subsys0.cache1.WritebackDirty_hits::total 46587 # number of WritebackDirty hits +system.l2subsys0.cache1.UpgradeReq_hits::l0subsys0.tester0 168 # number of UpgradeReq hits +system.l2subsys0.cache1.UpgradeReq_hits::l0subsys0.tester1 121 # number of UpgradeReq hits +system.l2subsys0.cache1.UpgradeReq_hits::l0subsys1.tester0 142 # number of UpgradeReq hits +system.l2subsys0.cache1.UpgradeReq_hits::l0subsys1.tester1 160 # number of UpgradeReq hits +system.l2subsys0.cache1.UpgradeReq_hits::total 591 # number of UpgradeReq hits +system.l2subsys0.cache1.ReadExReq_hits::l0subsys0.tester0 42 # number of ReadExReq hits +system.l2subsys0.cache1.ReadExReq_hits::l0subsys0.tester1 49 # number of ReadExReq hits +system.l2subsys0.cache1.ReadExReq_hits::l0subsys1.tester0 38 # number of ReadExReq hits +system.l2subsys0.cache1.ReadExReq_hits::l0subsys1.tester1 33 # number of ReadExReq hits +system.l2subsys0.cache1.ReadExReq_hits::total 162 # number of ReadExReq hits +system.l2subsys0.cache1.ReadSharedReq_hits::l0subsys0.tester0 686 # number of ReadSharedReq hits +system.l2subsys0.cache1.ReadSharedReq_hits::l0subsys0.tester1 632 # number of ReadSharedReq hits +system.l2subsys0.cache1.ReadSharedReq_hits::l0subsys1.tester0 726 # number of ReadSharedReq hits +system.l2subsys0.cache1.ReadSharedReq_hits::l0subsys1.tester1 731 # number of ReadSharedReq hits +system.l2subsys0.cache1.ReadSharedReq_hits::total 2775 # number of ReadSharedReq hits +system.l2subsys0.cache1.demand_hits::l0subsys0.tester0 728 # number of demand (read+write) hits +system.l2subsys0.cache1.demand_hits::l0subsys0.tester1 681 # number of demand (read+write) hits +system.l2subsys0.cache1.demand_hits::l0subsys1.tester0 764 # number of demand (read+write) hits +system.l2subsys0.cache1.demand_hits::l0subsys1.tester1 764 # number of demand (read+write) hits +system.l2subsys0.cache1.demand_hits::total 2937 # number of demand (read+write) hits +system.l2subsys0.cache1.overall_hits::l0subsys0.tester0 728 # number of overall hits +system.l2subsys0.cache1.overall_hits::l0subsys0.tester1 681 # number of overall hits +system.l2subsys0.cache1.overall_hits::l0subsys1.tester0 764 # number of overall hits +system.l2subsys0.cache1.overall_hits::l0subsys1.tester1 764 # number of overall hits +system.l2subsys0.cache1.overall_hits::total 2937 # number of overall hits +system.l2subsys0.cache1.UpgradeReq_misses::l0subsys0.tester0 3496 # number of UpgradeReq misses +system.l2subsys0.cache1.UpgradeReq_misses::l0subsys0.tester1 3545 # number of UpgradeReq misses +system.l2subsys0.cache1.UpgradeReq_misses::l0subsys1.tester0 3229 # number of UpgradeReq misses +system.l2subsys0.cache1.UpgradeReq_misses::l0subsys1.tester1 3694 # number of UpgradeReq misses +system.l2subsys0.cache1.UpgradeReq_misses::total 13964 # number of UpgradeReq misses +system.l2subsys0.cache1.ReadExReq_misses::l0subsys0.tester0 16533 # number of ReadExReq misses +system.l2subsys0.cache1.ReadExReq_misses::l0subsys0.tester1 16684 # number of ReadExReq misses +system.l2subsys0.cache1.ReadExReq_misses::l0subsys1.tester0 16775 # number of ReadExReq misses +system.l2subsys0.cache1.ReadExReq_misses::l0subsys1.tester1 16964 # number of ReadExReq misses +system.l2subsys0.cache1.ReadExReq_misses::total 66956 # number of ReadExReq misses +system.l2subsys0.cache1.ReadSharedReq_misses::l0subsys0.tester0 28808 # number of ReadSharedReq misses +system.l2subsys0.cache1.ReadSharedReq_misses::l0subsys0.tester1 29088 # number of ReadSharedReq misses +system.l2subsys0.cache1.ReadSharedReq_misses::l0subsys1.tester0 28899 # number of ReadSharedReq misses +system.l2subsys0.cache1.ReadSharedReq_misses::l0subsys1.tester1 29649 # number of ReadSharedReq misses +system.l2subsys0.cache1.ReadSharedReq_misses::total 116444 # number of ReadSharedReq misses +system.l2subsys0.cache1.demand_misses::l0subsys0.tester0 45341 # number of demand (read+write) misses +system.l2subsys0.cache1.demand_misses::l0subsys0.tester1 45772 # number of demand (read+write) misses +system.l2subsys0.cache1.demand_misses::l0subsys1.tester0 45674 # number of demand (read+write) misses +system.l2subsys0.cache1.demand_misses::l0subsys1.tester1 46613 # number of demand (read+write) misses +system.l2subsys0.cache1.demand_misses::total 183400 # number of demand (read+write) misses +system.l2subsys0.cache1.overall_misses::l0subsys0.tester0 45341 # number of overall misses +system.l2subsys0.cache1.overall_misses::l0subsys0.tester1 45772 # number of overall misses +system.l2subsys0.cache1.overall_misses::l0subsys1.tester0 45674 # number of overall misses +system.l2subsys0.cache1.overall_misses::l0subsys1.tester1 46613 # number of overall misses +system.l2subsys0.cache1.overall_misses::total 183400 # number of overall misses +system.l2subsys0.cache1.UpgradeReq_miss_latency::l0subsys0.tester0 113867429 # number of UpgradeReq miss cycles +system.l2subsys0.cache1.UpgradeReq_miss_latency::l0subsys0.tester1 115764935 # number of UpgradeReq miss cycles +system.l2subsys0.cache1.UpgradeReq_miss_latency::l0subsys1.tester0 105593459 # number of UpgradeReq miss cycles +system.l2subsys0.cache1.UpgradeReq_miss_latency::l0subsys1.tester1 122664883 # number of UpgradeReq miss cycles +system.l2subsys0.cache1.UpgradeReq_miss_latency::total 457890706 # number of UpgradeReq miss cycles +system.l2subsys0.cache1.ReadExReq_miss_latency::l0subsys0.tester0 1586451745 # number of ReadExReq miss cycles +system.l2subsys0.cache1.ReadExReq_miss_latency::l0subsys0.tester1 1553900027 # number of ReadExReq miss cycles +system.l2subsys0.cache1.ReadExReq_miss_latency::l0subsys1.tester0 1610224177 # number of ReadExReq miss cycles +system.l2subsys0.cache1.ReadExReq_miss_latency::l0subsys1.tester1 1616496304 # number of ReadExReq miss cycles +system.l2subsys0.cache1.ReadExReq_miss_latency::total 6367072253 # number of ReadExReq miss cycles +system.l2subsys0.cache1.ReadSharedReq_miss_latency::l0subsys0.tester0 2779939089 # number of ReadSharedReq miss cycles +system.l2subsys0.cache1.ReadSharedReq_miss_latency::l0subsys0.tester1 2733735321 # number of ReadSharedReq miss cycles +system.l2subsys0.cache1.ReadSharedReq_miss_latency::l0subsys1.tester0 2766545210 # number of ReadSharedReq miss cycles +system.l2subsys0.cache1.ReadSharedReq_miss_latency::l0subsys1.tester1 2839007144 # number of ReadSharedReq miss cycles +system.l2subsys0.cache1.ReadSharedReq_miss_latency::total 11119226764 # number of ReadSharedReq miss cycles +system.l2subsys0.cache1.demand_miss_latency::l0subsys0.tester0 4366390834 # number of demand (read+write) miss cycles +system.l2subsys0.cache1.demand_miss_latency::l0subsys0.tester1 4287635348 # number of demand (read+write) miss cycles +system.l2subsys0.cache1.demand_miss_latency::l0subsys1.tester0 4376769387 # number of demand (read+write) miss cycles +system.l2subsys0.cache1.demand_miss_latency::l0subsys1.tester1 4455503448 # number of demand (read+write) miss cycles +system.l2subsys0.cache1.demand_miss_latency::total 17486299017 # number of demand (read+write) miss cycles +system.l2subsys0.cache1.overall_miss_latency::l0subsys0.tester0 4366390834 # number of overall miss cycles +system.l2subsys0.cache1.overall_miss_latency::l0subsys0.tester1 4287635348 # number of overall miss cycles +system.l2subsys0.cache1.overall_miss_latency::l0subsys1.tester0 4376769387 # number of overall miss cycles +system.l2subsys0.cache1.overall_miss_latency::l0subsys1.tester1 4455503448 # number of overall miss cycles +system.l2subsys0.cache1.overall_miss_latency::total 17486299017 # number of overall miss cycles +system.l2subsys0.cache1.WritebackDirty_accesses::writebacks 46587 # number of WritebackDirty accesses(hits+misses) +system.l2subsys0.cache1.WritebackDirty_accesses::total 46587 # number of WritebackDirty accesses(hits+misses) +system.l2subsys0.cache1.UpgradeReq_accesses::l0subsys0.tester0 3664 # number of UpgradeReq accesses(hits+misses) +system.l2subsys0.cache1.UpgradeReq_accesses::l0subsys0.tester1 3666 # number of UpgradeReq accesses(hits+misses) +system.l2subsys0.cache1.UpgradeReq_accesses::l0subsys1.tester0 3371 # number of UpgradeReq accesses(hits+misses) +system.l2subsys0.cache1.UpgradeReq_accesses::l0subsys1.tester1 3854 # number of UpgradeReq accesses(hits+misses) +system.l2subsys0.cache1.UpgradeReq_accesses::total 14555 # number of UpgradeReq accesses(hits+misses) +system.l2subsys0.cache1.ReadExReq_accesses::l0subsys0.tester0 16575 # number of ReadExReq accesses(hits+misses) +system.l2subsys0.cache1.ReadExReq_accesses::l0subsys0.tester1 16733 # number of ReadExReq accesses(hits+misses) +system.l2subsys0.cache1.ReadExReq_accesses::l0subsys1.tester0 16813 # number of ReadExReq accesses(hits+misses) +system.l2subsys0.cache1.ReadExReq_accesses::l0subsys1.tester1 16997 # number of ReadExReq accesses(hits+misses) +system.l2subsys0.cache1.ReadExReq_accesses::total 67118 # number of ReadExReq accesses(hits+misses) +system.l2subsys0.cache1.ReadSharedReq_accesses::l0subsys0.tester0 29494 # number of ReadSharedReq accesses(hits+misses) +system.l2subsys0.cache1.ReadSharedReq_accesses::l0subsys0.tester1 29720 # number of ReadSharedReq accesses(hits+misses) +system.l2subsys0.cache1.ReadSharedReq_accesses::l0subsys1.tester0 29625 # number of ReadSharedReq accesses(hits+misses) +system.l2subsys0.cache1.ReadSharedReq_accesses::l0subsys1.tester1 30380 # number of ReadSharedReq accesses(hits+misses) +system.l2subsys0.cache1.ReadSharedReq_accesses::total 119219 # number of ReadSharedReq accesses(hits+misses) +system.l2subsys0.cache1.demand_accesses::l0subsys0.tester0 46069 # number of demand (read+write) accesses +system.l2subsys0.cache1.demand_accesses::l0subsys0.tester1 46453 # number of demand (read+write) accesses +system.l2subsys0.cache1.demand_accesses::l0subsys1.tester0 46438 # number of demand (read+write) accesses +system.l2subsys0.cache1.demand_accesses::l0subsys1.tester1 47377 # number of demand (read+write) accesses +system.l2subsys0.cache1.demand_accesses::total 186337 # number of demand (read+write) accesses +system.l2subsys0.cache1.overall_accesses::l0subsys0.tester0 46069 # number of overall (read+write) accesses +system.l2subsys0.cache1.overall_accesses::l0subsys0.tester1 46453 # number of overall (read+write) accesses +system.l2subsys0.cache1.overall_accesses::l0subsys1.tester0 46438 # number of overall (read+write) accesses +system.l2subsys0.cache1.overall_accesses::l0subsys1.tester1 47377 # number of overall (read+write) accesses +system.l2subsys0.cache1.overall_accesses::total 186337 # number of overall (read+write) accesses +system.l2subsys0.cache1.UpgradeReq_miss_rate::l0subsys0.tester0 0.954148 # miss rate for UpgradeReq accesses +system.l2subsys0.cache1.UpgradeReq_miss_rate::l0subsys0.tester1 0.966994 # miss rate for UpgradeReq accesses +system.l2subsys0.cache1.UpgradeReq_miss_rate::l0subsys1.tester0 0.957876 # miss rate for UpgradeReq accesses +system.l2subsys0.cache1.UpgradeReq_miss_rate::l0subsys1.tester1 0.958485 # miss rate for UpgradeReq accesses +system.l2subsys0.cache1.UpgradeReq_miss_rate::total 0.959395 # miss rate for UpgradeReq accesses +system.l2subsys0.cache1.ReadExReq_miss_rate::l0subsys0.tester0 0.997466 # miss rate for ReadExReq accesses +system.l2subsys0.cache1.ReadExReq_miss_rate::l0subsys0.tester1 0.997072 # miss rate for ReadExReq accesses +system.l2subsys0.cache1.ReadExReq_miss_rate::l0subsys1.tester0 0.997740 # miss rate for ReadExReq accesses +system.l2subsys0.cache1.ReadExReq_miss_rate::l0subsys1.tester1 0.998058 # miss rate for ReadExReq accesses +system.l2subsys0.cache1.ReadExReq_miss_rate::total 0.997586 # miss rate for ReadExReq accesses +system.l2subsys0.cache1.ReadSharedReq_miss_rate::l0subsys0.tester0 0.976741 # miss rate for ReadSharedReq accesses +system.l2subsys0.cache1.ReadSharedReq_miss_rate::l0subsys0.tester1 0.978735 # miss rate for ReadSharedReq accesses +system.l2subsys0.cache1.ReadSharedReq_miss_rate::l0subsys1.tester0 0.975494 # miss rate for ReadSharedReq accesses +system.l2subsys0.cache1.ReadSharedReq_miss_rate::l0subsys1.tester1 0.975938 # miss rate for ReadSharedReq accesses +system.l2subsys0.cache1.ReadSharedReq_miss_rate::total 0.976724 # miss rate for ReadSharedReq accesses +system.l2subsys0.cache1.demand_miss_rate::l0subsys0.tester0 0.984198 # miss rate for demand accesses +system.l2subsys0.cache1.demand_miss_rate::l0subsys0.tester1 0.985340 # miss rate for demand accesses +system.l2subsys0.cache1.demand_miss_rate::l0subsys1.tester0 0.983548 # miss rate for demand accesses +system.l2subsys0.cache1.demand_miss_rate::l0subsys1.tester1 0.983874 # miss rate for demand accesses +system.l2subsys0.cache1.demand_miss_rate::total 0.984238 # miss rate for demand accesses +system.l2subsys0.cache1.overall_miss_rate::l0subsys0.tester0 0.984198 # miss rate for overall accesses +system.l2subsys0.cache1.overall_miss_rate::l0subsys0.tester1 0.985340 # miss rate for overall accesses +system.l2subsys0.cache1.overall_miss_rate::l0subsys1.tester0 0.983548 # miss rate for overall accesses +system.l2subsys0.cache1.overall_miss_rate::l0subsys1.tester1 0.983874 # miss rate for overall accesses +system.l2subsys0.cache1.overall_miss_rate::total 0.984238 # miss rate for overall accesses +system.l2subsys0.cache1.UpgradeReq_avg_miss_latency::l0subsys0.tester0 32570.774886 # average UpgradeReq miss latency +system.l2subsys0.cache1.UpgradeReq_avg_miss_latency::l0subsys0.tester1 32655.834979 # average UpgradeReq miss latency +system.l2subsys0.cache1.UpgradeReq_avg_miss_latency::l0subsys1.tester0 32701.597708 # average UpgradeReq miss latency +system.l2subsys0.cache1.UpgradeReq_avg_miss_latency::l0subsys1.tester1 33206.519491 # average UpgradeReq miss latency +system.l2subsys0.cache1.UpgradeReq_avg_miss_latency::total 32790.798195 # average UpgradeReq miss latency +system.l2subsys0.cache1.ReadExReq_avg_miss_latency::l0subsys0.tester0 95956.677252 # average ReadExReq miss latency +system.l2subsys0.cache1.ReadExReq_avg_miss_latency::l0subsys0.tester1 93137.138995 # average ReadExReq miss latency +system.l2subsys0.cache1.ReadExReq_avg_miss_latency::l0subsys1.tester0 95989.518748 # average ReadExReq miss latency +system.l2subsys0.cache1.ReadExReq_avg_miss_latency::l0subsys1.tester1 95289.808064 # average ReadExReq miss latency +system.l2subsys0.cache1.ReadExReq_avg_miss_latency::total 95093.378532 # average ReadExReq miss latency +system.l2subsys0.cache1.ReadSharedReq_avg_miss_latency::l0subsys0.tester0 96498.857574 # average ReadSharedReq miss latency +system.l2subsys0.cache1.ReadSharedReq_avg_miss_latency::l0subsys0.tester1 93981.549814 # average ReadSharedReq miss latency +system.l2subsys0.cache1.ReadSharedReq_avg_miss_latency::l0subsys1.tester0 95731.520468 # average ReadSharedReq miss latency +system.l2subsys0.cache1.ReadSharedReq_avg_miss_latency::l0subsys1.tester1 95753.892003 # average ReadSharedReq miss latency +system.l2subsys0.cache1.ReadSharedReq_avg_miss_latency::total 95489.907286 # average ReadSharedReq miss latency +system.l2subsys0.cache1.demand_avg_miss_latency::l0subsys0.tester0 96301.158642 # average overall miss latency +system.l2subsys0.cache1.demand_avg_miss_latency::l0subsys0.tester1 93673.760115 # average overall miss latency +system.l2subsys0.cache1.demand_avg_miss_latency::l0subsys1.tester0 95826.277247 # average overall miss latency +system.l2subsys0.cache1.demand_avg_miss_latency::l0subsys1.tester1 95584.996632 # average overall miss latency +system.l2subsys0.cache1.demand_avg_miss_latency::total 95345.141859 # average overall miss latency +system.l2subsys0.cache1.overall_avg_miss_latency::l0subsys0.tester0 96301.158642 # average overall miss latency +system.l2subsys0.cache1.overall_avg_miss_latency::l0subsys0.tester1 93673.760115 # average overall miss latency +system.l2subsys0.cache1.overall_avg_miss_latency::l0subsys1.tester0 95826.277247 # average overall miss latency +system.l2subsys0.cache1.overall_avg_miss_latency::l0subsys1.tester1 95584.996632 # average overall miss latency +system.l2subsys0.cache1.overall_avg_miss_latency::total 95345.141859 # average overall miss latency system.l2subsys0.cache1.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2subsys0.cache1.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2subsys0.cache1.blocked::no_mshrs 0 # number of cycles access was blocked system.l2subsys0.cache1.blocked::no_targets 0 # number of cycles access was blocked system.l2subsys0.cache1.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.l2subsys0.cache1.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.l2subsys0.cache1.writebacks::writebacks 48103 # number of writebacks -system.l2subsys0.cache1.writebacks::total 48103 # number of writebacks -system.l2subsys0.cache1.ReadExReq_mshr_hits::l0subsys0.tester0 269 # number of ReadExReq MSHR hits -system.l2subsys0.cache1.ReadExReq_mshr_hits::l0subsys0.tester1 310 # number of ReadExReq MSHR hits -system.l2subsys0.cache1.ReadExReq_mshr_hits::l0subsys1.tester0 278 # number of ReadExReq MSHR hits -system.l2subsys0.cache1.ReadExReq_mshr_hits::l0subsys1.tester1 276 # number of ReadExReq MSHR hits -system.l2subsys0.cache1.ReadExReq_mshr_hits::total 1133 # number of ReadExReq MSHR hits -system.l2subsys0.cache1.ReadSharedReq_mshr_hits::l0subsys0.tester0 458 # number of ReadSharedReq MSHR hits -system.l2subsys0.cache1.ReadSharedReq_mshr_hits::l0subsys0.tester1 558 # number of ReadSharedReq MSHR hits -system.l2subsys0.cache1.ReadSharedReq_mshr_hits::l0subsys1.tester0 503 # number of ReadSharedReq MSHR hits -system.l2subsys0.cache1.ReadSharedReq_mshr_hits::l0subsys1.tester1 524 # number of ReadSharedReq MSHR hits -system.l2subsys0.cache1.ReadSharedReq_mshr_hits::total 2043 # number of ReadSharedReq MSHR hits -system.l2subsys0.cache1.demand_mshr_hits::l0subsys0.tester0 727 # number of demand (read+write) MSHR hits -system.l2subsys0.cache1.demand_mshr_hits::l0subsys0.tester1 868 # number of demand (read+write) MSHR hits -system.l2subsys0.cache1.demand_mshr_hits::l0subsys1.tester0 781 # number of demand (read+write) MSHR hits -system.l2subsys0.cache1.demand_mshr_hits::l0subsys1.tester1 800 # number of demand (read+write) MSHR hits -system.l2subsys0.cache1.demand_mshr_hits::total 3176 # number of demand (read+write) MSHR hits -system.l2subsys0.cache1.overall_mshr_hits::l0subsys0.tester0 727 # number of overall MSHR hits -system.l2subsys0.cache1.overall_mshr_hits::l0subsys0.tester1 868 # number of overall MSHR hits -system.l2subsys0.cache1.overall_mshr_hits::l0subsys1.tester0 781 # number of overall MSHR hits -system.l2subsys0.cache1.overall_mshr_hits::l0subsys1.tester1 800 # number of overall MSHR hits -system.l2subsys0.cache1.overall_mshr_hits::total 3176 # number of overall MSHR hits -system.l2subsys0.cache1.CleanEvict_mshr_misses::writebacks 30416 # number of CleanEvict MSHR misses -system.l2subsys0.cache1.CleanEvict_mshr_misses::total 30416 # number of CleanEvict MSHR misses -system.l2subsys0.cache1.UpgradeReq_mshr_misses::l0subsys0.tester0 3840 # number of UpgradeReq MSHR misses -system.l2subsys0.cache1.UpgradeReq_mshr_misses::l0subsys0.tester1 3889 # number of UpgradeReq MSHR misses -system.l2subsys0.cache1.UpgradeReq_mshr_misses::l0subsys1.tester0 3668 # number of UpgradeReq MSHR misses -system.l2subsys0.cache1.UpgradeReq_mshr_misses::l0subsys1.tester1 3541 # number of UpgradeReq MSHR misses -system.l2subsys0.cache1.UpgradeReq_mshr_misses::total 14938 # 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number of ReadExReq MSHR miss cycles -system.l2subsys0.cache1.ReadExReq_mshr_miss_latency::total 5868915333 # number of ReadExReq MSHR miss cycles -system.l2subsys0.cache1.ReadSharedReq_mshr_miss_latency::l0subsys0.tester0 2547272284 # number of ReadSharedReq MSHR miss cycles -system.l2subsys0.cache1.ReadSharedReq_mshr_miss_latency::l0subsys0.tester1 2554397032 # number of ReadSharedReq MSHR miss cycles -system.l2subsys0.cache1.ReadSharedReq_mshr_miss_latency::l0subsys1.tester0 2493574245 # number of ReadSharedReq MSHR miss cycles -system.l2subsys0.cache1.ReadSharedReq_mshr_miss_latency::l0subsys1.tester1 2703309675 # number of ReadSharedReq MSHR miss cycles -system.l2subsys0.cache1.ReadSharedReq_mshr_miss_latency::total 10298553236 # number of ReadSharedReq MSHR miss cycles -system.l2subsys0.cache1.demand_mshr_miss_latency::l0subsys0.tester0 4012473687 # number of demand (read+write) MSHR miss cycles -system.l2subsys0.cache1.demand_mshr_miss_latency::l0subsys0.tester1 4025987309 # number of demand (read+write) MSHR miss cycles -system.l2subsys0.cache1.demand_mshr_miss_latency::l0subsys1.tester0 3907786558 # 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number of writebacks +system.l2subsys0.cache1.ReadExReq_mshr_hits::l0subsys0.tester0 331 # number of ReadExReq MSHR hits +system.l2subsys0.cache1.ReadExReq_mshr_hits::l0subsys0.tester1 329 # number of ReadExReq MSHR hits +system.l2subsys0.cache1.ReadExReq_mshr_hits::l0subsys1.tester0 351 # number of ReadExReq MSHR hits +system.l2subsys0.cache1.ReadExReq_mshr_hits::l0subsys1.tester1 338 # number of ReadExReq MSHR hits +system.l2subsys0.cache1.ReadExReq_mshr_hits::total 1349 # number of ReadExReq MSHR hits +system.l2subsys0.cache1.ReadSharedReq_mshr_hits::l0subsys0.tester0 639 # number of ReadSharedReq MSHR hits +system.l2subsys0.cache1.ReadSharedReq_mshr_hits::l0subsys0.tester1 567 # number of ReadSharedReq MSHR hits +system.l2subsys0.cache1.ReadSharedReq_mshr_hits::l0subsys1.tester0 568 # number of ReadSharedReq MSHR hits +system.l2subsys0.cache1.ReadSharedReq_mshr_hits::l0subsys1.tester1 602 # number of ReadSharedReq MSHR hits +system.l2subsys0.cache1.ReadSharedReq_mshr_hits::total 2376 # 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number of ReadExReq MSHR misses +system.l2subsys0.cache1.ReadExReq_mshr_misses::total 65607 # number of ReadExReq MSHR misses +system.l2subsys0.cache1.ReadSharedReq_mshr_misses::l0subsys0.tester0 28169 # number of ReadSharedReq MSHR misses +system.l2subsys0.cache1.ReadSharedReq_mshr_misses::l0subsys0.tester1 28521 # number of ReadSharedReq MSHR misses +system.l2subsys0.cache1.ReadSharedReq_mshr_misses::l0subsys1.tester0 28331 # number of ReadSharedReq MSHR misses +system.l2subsys0.cache1.ReadSharedReq_mshr_misses::l0subsys1.tester1 29047 # number of ReadSharedReq MSHR misses +system.l2subsys0.cache1.ReadSharedReq_mshr_misses::total 114068 # number of ReadSharedReq MSHR misses +system.l2subsys0.cache1.demand_mshr_misses::l0subsys0.tester0 44371 # number of demand (read+write) MSHR misses +system.l2subsys0.cache1.demand_mshr_misses::l0subsys0.tester1 44876 # number of demand (read+write) MSHR misses +system.l2subsys0.cache1.demand_mshr_misses::l0subsys1.tester0 44755 # number of demand (read+write) MSHR misses +system.l2subsys0.cache1.demand_mshr_misses::l0subsys1.tester1 45673 # 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number of UpgradeReq MSHR miss cycles +system.l2subsys0.cache1.UpgradeReq_mshr_miss_latency::total 328362223 # number of UpgradeReq MSHR miss cycles +system.l2subsys0.cache1.ReadExReq_mshr_miss_latency::l0subsys0.tester0 1414482686 # number of ReadExReq MSHR miss cycles +system.l2subsys0.cache1.ReadExReq_mshr_miss_latency::l0subsys0.tester1 1379942377 # number of ReadExReq MSHR miss cycles +system.l2subsys0.cache1.ReadExReq_mshr_miss_latency::l0subsys1.tester0 1435894366 # number of ReadExReq MSHR miss cycles +system.l2subsys0.cache1.ReadExReq_mshr_miss_latency::l0subsys1.tester1 1440517955 # number of ReadExReq MSHR miss cycles +system.l2subsys0.cache1.ReadExReq_mshr_miss_latency::total 5670837384 # number of ReadExReq MSHR miss cycles +system.l2subsys0.cache1.ReadSharedReq_mshr_miss_latency::l0subsys0.tester0 2482055887 # number of ReadSharedReq MSHR miss cycles +system.l2subsys0.cache1.ReadSharedReq_mshr_miss_latency::l0subsys0.tester1 2433508746 # number of ReadSharedReq MSHR miss cycles +system.l2subsys0.cache1.ReadSharedReq_mshr_miss_latency::l0subsys1.tester0 2468466034 # number of ReadSharedReq MSHR miss cycles +system.l2subsys0.cache1.ReadSharedReq_mshr_miss_latency::l0subsys1.tester1 2532799653 # number of ReadSharedReq MSHR miss cycles +system.l2subsys0.cache1.ReadSharedReq_mshr_miss_latency::total 9916830320 # number of ReadSharedReq MSHR miss cycles +system.l2subsys0.cache1.demand_mshr_miss_latency::l0subsys0.tester0 3896538573 # number of demand (read+write) MSHR miss cycles +system.l2subsys0.cache1.demand_mshr_miss_latency::l0subsys0.tester1 3813451123 # number of demand (read+write) MSHR miss cycles +system.l2subsys0.cache1.demand_mshr_miss_latency::l0subsys1.tester0 3904360400 # number of demand (read+write) MSHR miss cycles +system.l2subsys0.cache1.demand_mshr_miss_latency::l0subsys1.tester1 3973317608 # number of demand (read+write) MSHR miss cycles +system.l2subsys0.cache1.demand_mshr_miss_latency::total 15587667704 # number of demand (read+write) MSHR miss cycles +system.l2subsys0.cache1.overall_mshr_miss_latency::l0subsys0.tester0 3896538573 # number of overall MSHR miss cycles +system.l2subsys0.cache1.overall_mshr_miss_latency::l0subsys0.tester1 3813451123 # number of overall MSHR miss cycles +system.l2subsys0.cache1.overall_mshr_miss_latency::l0subsys1.tester0 3904360400 # number of overall MSHR miss cycles +system.l2subsys0.cache1.overall_mshr_miss_latency::l0subsys1.tester1 3973317608 # number of overall MSHR miss cycles +system.l2subsys0.cache1.overall_mshr_miss_latency::total 15587667704 # number of overall MSHR miss cycles system.l2subsys0.cache1.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.l2subsys0.cache1.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.l2subsys0.cache1.UpgradeReq_mshr_miss_rate::l0subsys0.tester0 1 # mshr miss rate for UpgradeReq accesses -system.l2subsys0.cache1.UpgradeReq_mshr_miss_rate::l0subsys0.tester1 1 # mshr miss rate for UpgradeReq accesses -system.l2subsys0.cache1.UpgradeReq_mshr_miss_rate::l0subsys1.tester0 1 # mshr miss rate for UpgradeReq accesses -system.l2subsys0.cache1.UpgradeReq_mshr_miss_rate::l0subsys1.tester1 1 # mshr miss rate for UpgradeReq accesses -system.l2subsys0.cache1.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses -system.l2subsys0.cache1.ReadExReq_mshr_miss_rate::l0subsys0.tester0 0.981631 # mshr miss rate for ReadExReq accesses -system.l2subsys0.cache1.ReadExReq_mshr_miss_rate::l0subsys0.tester1 0.979314 # mshr miss rate for ReadExReq accesses -system.l2subsys0.cache1.ReadExReq_mshr_miss_rate::l0subsys1.tester0 0.979951 # mshr miss rate for ReadExReq accesses -system.l2subsys0.cache1.ReadExReq_mshr_miss_rate::l0subsys1.tester1 0.979930 # mshr miss rate for ReadExReq accesses -system.l2subsys0.cache1.ReadExReq_mshr_miss_rate::total 0.980206 # mshr miss rate for ReadExReq accesses -system.l2subsys0.cache1.ReadSharedReq_mshr_miss_rate::l0subsys0.tester0 0.965226 # mshr miss rate for ReadSharedReq accesses -system.l2subsys0.cache1.ReadSharedReq_mshr_miss_rate::l0subsys0.tester1 0.963626 # mshr miss rate for ReadSharedReq accesses -system.l2subsys0.cache1.ReadSharedReq_mshr_miss_rate::l0subsys1.tester0 0.960986 # mshr miss rate for ReadSharedReq accesses -system.l2subsys0.cache1.ReadSharedReq_mshr_miss_rate::l0subsys1.tester1 0.960105 # mshr miss rate for ReadSharedReq accesses -system.l2subsys0.cache1.ReadSharedReq_mshr_miss_rate::total 0.962490 # mshr miss rate for ReadSharedReq accesses -system.l2subsys0.cache1.demand_mshr_miss_rate::l0subsys0.tester0 0.971153 # mshr miss rate for demand accesses -system.l2subsys0.cache1.demand_mshr_miss_rate::l0subsys0.tester1 0.969306 # mshr miss rate for demand accesses -system.l2subsys0.cache1.demand_mshr_miss_rate::l0subsys1.tester0 0.967787 # mshr miss rate for demand accesses -system.l2subsys0.cache1.demand_mshr_miss_rate::l0subsys1.tester1 0.967202 # mshr miss rate for demand accesses -system.l2subsys0.cache1.demand_mshr_miss_rate::total 0.968867 # mshr miss rate for demand accesses -system.l2subsys0.cache1.overall_mshr_miss_rate::l0subsys0.tester0 0.971153 # mshr miss rate for overall accesses -system.l2subsys0.cache1.overall_mshr_miss_rate::l0subsys0.tester1 0.969306 # mshr miss rate for overall accesses -system.l2subsys0.cache1.overall_mshr_miss_rate::l0subsys1.tester0 0.967787 # mshr miss rate for overall accesses -system.l2subsys0.cache1.overall_mshr_miss_rate::l0subsys1.tester1 0.967202 # mshr miss rate for overall accesses -system.l2subsys0.cache1.overall_mshr_miss_rate::total 0.968867 # mshr miss rate for overall accesses -system.l2subsys0.cache1.UpgradeReq_avg_mshr_miss_latency::l0subsys0.tester0 23379.292187 # average UpgradeReq mshr miss latency -system.l2subsys0.cache1.UpgradeReq_avg_mshr_miss_latency::l0subsys0.tester1 23121.208023 # average UpgradeReq mshr miss latency -system.l2subsys0.cache1.UpgradeReq_avg_mshr_miss_latency::l0subsys1.tester0 23941.043621 # average UpgradeReq mshr miss latency -system.l2subsys0.cache1.UpgradeReq_avg_mshr_miss_latency::l0subsys1.tester1 23851.192601 # average UpgradeReq mshr miss latency -system.l2subsys0.cache1.UpgradeReq_avg_mshr_miss_latency::total 23561.901259 # average UpgradeReq mshr miss latency -system.l2subsys0.cache1.ReadExReq_avg_mshr_miss_latency::l0subsys0.tester0 87318.319607 # average ReadExReq mshr miss latency -system.l2subsys0.cache1.ReadExReq_avg_mshr_miss_latency::l0subsys0.tester1 86829.730765 # average ReadExReq mshr miss latency -system.l2subsys0.cache1.ReadExReq_avg_mshr_miss_latency::l0subsys1.tester0 88482.281987 # average ReadExReq mshr miss latency -system.l2subsys0.cache1.ReadExReq_avg_mshr_miss_latency::l0subsys1.tester1 90110.498071 # average ReadExReq mshr miss latency -system.l2subsys0.cache1.ReadExReq_avg_mshr_miss_latency::total 88180.108976 # average ReadExReq mshr miss latency -system.l2subsys0.cache1.ReadSharedReq_avg_mshr_miss_latency::l0subsys0.tester0 87316.089672 # average ReadSharedReq mshr miss latency -system.l2subsys0.cache1.ReadSharedReq_avg_mshr_miss_latency::l0subsys0.tester1 86943.397958 # average ReadSharedReq mshr miss latency -system.l2subsys0.cache1.ReadSharedReq_avg_mshr_miss_latency::l0subsys1.tester0 88957.734116 # average ReadSharedReq mshr miss latency -system.l2subsys0.cache1.ReadSharedReq_avg_mshr_miss_latency::l0subsys1.tester1 91324.944259 # average ReadSharedReq mshr miss latency -system.l2subsys0.cache1.ReadSharedReq_avg_mshr_miss_latency::total 88639.266997 # average ReadSharedReq mshr miss latency -system.l2subsys0.cache1.demand_avg_mshr_miss_latency::l0subsys0.tester0 87316.903945 # average overall mshr miss latency -system.l2subsys0.cache1.demand_avg_mshr_miss_latency::l0subsys0.tester1 86901.815511 # average overall mshr miss latency -system.l2subsys0.cache1.demand_avg_mshr_miss_latency::l0subsys1.tester0 88785.081065 # average overall mshr miss latency -system.l2subsys0.cache1.demand_avg_mshr_miss_latency::l0subsys1.tester1 90884.489838 # average overall mshr miss latency -system.l2subsys0.cache1.demand_avg_mshr_miss_latency::total 88472.037304 # average overall mshr miss latency -system.l2subsys0.cache1.overall_avg_mshr_miss_latency::l0subsys0.tester0 87316.903945 # average overall mshr miss latency -system.l2subsys0.cache1.overall_avg_mshr_miss_latency::l0subsys0.tester1 86901.815511 # average overall mshr miss latency -system.l2subsys0.cache1.overall_avg_mshr_miss_latency::l0subsys1.tester0 88785.081065 # average overall mshr miss latency -system.l2subsys0.cache1.overall_avg_mshr_miss_latency::l0subsys1.tester1 90884.489838 # average overall mshr miss latency -system.l2subsys0.cache1.overall_avg_mshr_miss_latency::total 88472.037304 # average overall mshr miss latency +system.l2subsys0.cache1.UpgradeReq_mshr_miss_rate::l0subsys0.tester0 0.954148 # mshr miss rate for UpgradeReq accesses +system.l2subsys0.cache1.UpgradeReq_mshr_miss_rate::l0subsys0.tester1 0.966994 # mshr miss rate for UpgradeReq accesses +system.l2subsys0.cache1.UpgradeReq_mshr_miss_rate::l0subsys1.tester0 0.957876 # mshr miss rate for UpgradeReq accesses +system.l2subsys0.cache1.UpgradeReq_mshr_miss_rate::l0subsys1.tester1 0.958485 # mshr miss rate for UpgradeReq accesses +system.l2subsys0.cache1.UpgradeReq_mshr_miss_rate::total 0.959395 # mshr miss rate for UpgradeReq accesses +system.l2subsys0.cache1.ReadExReq_mshr_miss_rate::l0subsys0.tester0 0.977496 # mshr miss rate for ReadExReq accesses +system.l2subsys0.cache1.ReadExReq_mshr_miss_rate::l0subsys0.tester1 0.977410 # mshr miss rate for ReadExReq accesses +system.l2subsys0.cache1.ReadExReq_mshr_miss_rate::l0subsys1.tester0 0.976863 # mshr miss rate for ReadExReq accesses +system.l2subsys0.cache1.ReadExReq_mshr_miss_rate::l0subsys1.tester1 0.978173 # mshr miss rate for ReadExReq accesses +system.l2subsys0.cache1.ReadExReq_mshr_miss_rate::total 0.977487 # mshr miss rate for ReadExReq accesses +system.l2subsys0.cache1.ReadSharedReq_mshr_miss_rate::l0subsys0.tester0 0.955076 # mshr miss rate for ReadSharedReq accesses +system.l2subsys0.cache1.ReadSharedReq_mshr_miss_rate::l0subsys0.tester1 0.959657 # mshr miss rate for ReadSharedReq accesses +system.l2subsys0.cache1.ReadSharedReq_mshr_miss_rate::l0subsys1.tester0 0.956321 # mshr miss rate for ReadSharedReq accesses +system.l2subsys0.cache1.ReadSharedReq_mshr_miss_rate::l0subsys1.tester1 0.956122 # mshr miss rate for ReadSharedReq accesses +system.l2subsys0.cache1.ReadSharedReq_mshr_miss_rate::total 0.956794 # mshr miss rate for ReadSharedReq accesses +system.l2subsys0.cache1.demand_mshr_miss_rate::l0subsys0.tester0 0.963142 # mshr miss rate for demand accesses +system.l2subsys0.cache1.demand_mshr_miss_rate::l0subsys0.tester1 0.966052 # mshr miss rate for demand accesses +system.l2subsys0.cache1.demand_mshr_miss_rate::l0subsys1.tester0 0.963758 # mshr miss rate for demand accesses +system.l2subsys0.cache1.demand_mshr_miss_rate::l0subsys1.tester1 0.964033 # mshr miss rate for demand accesses +system.l2subsys0.cache1.demand_mshr_miss_rate::total 0.964248 # mshr miss rate for demand accesses +system.l2subsys0.cache1.overall_mshr_miss_rate::l0subsys0.tester0 0.963142 # mshr miss rate for overall accesses +system.l2subsys0.cache1.overall_mshr_miss_rate::l0subsys0.tester1 0.966052 # mshr miss rate for overall accesses +system.l2subsys0.cache1.overall_mshr_miss_rate::l0subsys1.tester0 0.963758 # mshr miss rate for overall accesses +system.l2subsys0.cache1.overall_mshr_miss_rate::l0subsys1.tester1 0.964033 # mshr miss rate for overall accesses +system.l2subsys0.cache1.overall_mshr_miss_rate::total 0.964248 # mshr miss rate for overall accesses +system.l2subsys0.cache1.UpgradeReq_avg_mshr_miss_latency::l0subsys0.tester0 23367.876144 # average UpgradeReq mshr miss latency +system.l2subsys0.cache1.UpgradeReq_avg_mshr_miss_latency::l0subsys0.tester1 23401.571509 # average UpgradeReq mshr miss latency +system.l2subsys0.cache1.UpgradeReq_avg_mshr_miss_latency::l0subsys1.tester0 23469.231651 # average UpgradeReq mshr miss latency +system.l2subsys0.cache1.UpgradeReq_avg_mshr_miss_latency::l0subsys1.tester1 23802.763400 # average UpgradeReq mshr miss latency +system.l2subsys0.cache1.UpgradeReq_avg_mshr_miss_latency::total 23514.911415 # average UpgradeReq mshr miss latency +system.l2subsys0.cache1.ReadExReq_avg_mshr_miss_latency::l0subsys0.tester0 87302.967905 # average ReadExReq mshr miss latency +system.l2subsys0.cache1.ReadExReq_avg_mshr_miss_latency::l0subsys0.tester1 84374.342831 # average ReadExReq mshr miss latency +system.l2subsys0.cache1.ReadExReq_avg_mshr_miss_latency::l0subsys1.tester0 87426.593156 # average ReadExReq mshr miss latency +system.l2subsys0.cache1.ReadExReq_avg_mshr_miss_latency::l0subsys1.tester1 86642.484963 # average ReadExReq mshr miss latency +system.l2subsys0.cache1.ReadExReq_avg_mshr_miss_latency::total 86436.468426 # average ReadExReq mshr miss latency +system.l2subsys0.cache1.ReadSharedReq_avg_mshr_miss_latency::l0subsys0.tester0 88113.028045 # average ReadSharedReq mshr miss latency +system.l2subsys0.cache1.ReadSharedReq_avg_mshr_miss_latency::l0subsys0.tester1 85323.401914 # average ReadSharedReq mshr miss latency +system.l2subsys0.cache1.ReadSharedReq_avg_mshr_miss_latency::l0subsys1.tester0 87129.505983 # average ReadSharedReq mshr miss latency +system.l2subsys0.cache1.ReadSharedReq_avg_mshr_miss_latency::l0subsys1.tester1 87196.600441 # average ReadSharedReq mshr miss latency +system.l2subsys0.cache1.ReadSharedReq_avg_mshr_miss_latency::total 86937.881965 # average ReadSharedReq mshr miss latency +system.l2subsys0.cache1.demand_avg_mshr_miss_latency::l0subsys0.tester0 87817.235875 # average overall mshr miss latency +system.l2subsys0.cache1.demand_avg_mshr_miss_latency::l0subsys0.tester1 84977.518562 # average overall mshr miss latency +system.l2subsys0.cache1.demand_avg_mshr_miss_latency::l0subsys1.tester0 87238.529773 # average overall mshr miss latency +system.l2subsys0.cache1.demand_avg_mshr_miss_latency::l0subsys1.tester1 86994.889935 # average overall mshr miss latency +system.l2subsys0.cache1.demand_avg_mshr_miss_latency::total 86754.794512 # average overall mshr miss latency +system.l2subsys0.cache1.overall_avg_mshr_miss_latency::l0subsys0.tester0 87817.235875 # average overall mshr miss latency +system.l2subsys0.cache1.overall_avg_mshr_miss_latency::l0subsys0.tester1 84977.518562 # average overall mshr miss latency +system.l2subsys0.cache1.overall_avg_mshr_miss_latency::l0subsys1.tester0 87238.529773 # average overall mshr miss latency +system.l2subsys0.cache1.overall_avg_mshr_miss_latency::l0subsys1.tester1 86994.889935 # average overall mshr miss latency +system.l2subsys0.cache1.overall_avg_mshr_miss_latency::total 86754.794512 # average overall mshr miss latency system.l2subsys0.cache2.tags.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states -system.l2subsys0.cache2.tags.replacements 126032 # number of replacements -system.l2subsys0.cache2.tags.tagsinuse 1489.728979 # Cycle average of tags in use -system.l2subsys0.cache2.tags.total_refs 65365 # Total number of references to valid blocks. -system.l2subsys0.cache2.tags.sampled_refs 127529 # Sample count of references to valid blocks. -system.l2subsys0.cache2.tags.avg_refs 0.512550 # Average number of references to valid blocks. -system.l2subsys0.cache2.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2subsys0.cache2.tags.occ_blocks::writebacks 427.527348 # Average occupied blocks per requestor -system.l2subsys0.cache2.tags.occ_blocks::l0subsys2.tester0 271.510882 # Average occupied blocks per requestor -system.l2subsys0.cache2.tags.occ_blocks::l0subsys2.tester1 262.023740 # Average occupied blocks per requestor -system.l2subsys0.cache2.tags.occ_blocks::l0subsys3.tester0 270.301105 # Average occupied blocks per requestor -system.l2subsys0.cache2.tags.occ_blocks::l0subsys3.tester1 258.365905 # Average occupied blocks per requestor -system.l2subsys0.cache2.tags.occ_percent::writebacks 0.278338 # Average percentage of cache occupancy -system.l2subsys0.cache2.tags.occ_percent::l0subsys2.tester0 0.176765 # Average percentage of cache occupancy -system.l2subsys0.cache2.tags.occ_percent::l0subsys2.tester1 0.170588 # Average percentage of cache occupancy -system.l2subsys0.cache2.tags.occ_percent::l0subsys3.tester0 0.175977 # Average percentage of cache occupancy -system.l2subsys0.cache2.tags.occ_percent::l0subsys3.tester1 0.168207 # Average percentage of cache occupancy -system.l2subsys0.cache2.tags.occ_percent::total 0.969876 # Average percentage of cache occupancy -system.l2subsys0.cache2.tags.occ_task_id_blocks::1024 1497 # Occupied blocks per task id -system.l2subsys0.cache2.tags.age_task_id_blocks_1024::0 106 # Occupied blocks per task id -system.l2subsys0.cache2.tags.age_task_id_blocks_1024::1 1033 # Occupied blocks per task id -system.l2subsys0.cache2.tags.age_task_id_blocks_1024::2 358 # Occupied blocks per task id -system.l2subsys0.cache2.tags.occ_task_id_percent::1024 0.974609 # Percentage of cache occupancy per task id -system.l2subsys0.cache2.tags.tag_accesses 4109673 # Number of tag accesses -system.l2subsys0.cache2.tags.data_accesses 4109673 # Number of data accesses +system.l2subsys0.cache2.tags.replacements 148896 # number of replacements +system.l2subsys0.cache2.tags.tagsinuse 1523.034958 # Cycle average of tags in use +system.l2subsys0.cache2.tags.total_refs 81242 # Total number of references to valid blocks. +system.l2subsys0.cache2.tags.sampled_refs 150425 # Sample count of references to valid blocks. +system.l2subsys0.cache2.tags.avg_refs 0.540083 # Average number of references to valid blocks. +system.l2subsys0.cache2.tags.warmup_cycle 259670000 # Cycle when the warmup percentage was hit. +system.l2subsys0.cache2.tags.occ_blocks::writebacks 189.526445 # Average occupied blocks per requestor +system.l2subsys0.cache2.tags.occ_blocks::l0subsys2.tester0 325.843379 # Average occupied blocks per requestor +system.l2subsys0.cache2.tags.occ_blocks::l0subsys2.tester1 331.240676 # Average occupied blocks per requestor +system.l2subsys0.cache2.tags.occ_blocks::l0subsys3.tester0 338.598926 # Average occupied blocks per requestor +system.l2subsys0.cache2.tags.occ_blocks::l0subsys3.tester1 337.825532 # Average occupied blocks per requestor +system.l2subsys0.cache2.tags.occ_percent::writebacks 0.123390 # Average percentage of cache occupancy +system.l2subsys0.cache2.tags.occ_percent::l0subsys2.tester0 0.212138 # Average percentage of cache occupancy +system.l2subsys0.cache2.tags.occ_percent::l0subsys2.tester1 0.215651 # Average percentage of cache occupancy +system.l2subsys0.cache2.tags.occ_percent::l0subsys3.tester0 0.220442 # Average percentage of cache occupancy +system.l2subsys0.cache2.tags.occ_percent::l0subsys3.tester1 0.219938 # Average percentage of cache occupancy +system.l2subsys0.cache2.tags.occ_percent::total 0.991559 # Average percentage of cache occupancy +system.l2subsys0.cache2.tags.occ_task_id_blocks::1024 1529 # Occupied blocks per task id +system.l2subsys0.cache2.tags.age_task_id_blocks_1024::0 247 # Occupied blocks per task id +system.l2subsys0.cache2.tags.age_task_id_blocks_1024::1 1113 # Occupied blocks per task id +system.l2subsys0.cache2.tags.age_task_id_blocks_1024::2 169 # Occupied blocks per task id +system.l2subsys0.cache2.tags.occ_task_id_percent::1024 0.995443 # Percentage of cache occupancy per task id +system.l2subsys0.cache2.tags.tag_accesses 4107279 # Number of tag accesses +system.l2subsys0.cache2.tags.data_accesses 4107279 # Number of data accesses system.l2subsys0.cache2.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states -system.l2subsys0.cache2.WritebackDirty_hits::writebacks 45683 # number of WritebackDirty hits -system.l2subsys0.cache2.WritebackDirty_hits::total 45683 # number of WritebackDirty hits -system.l2subsys0.cache2.ReadExReq_hits::l0subsys2.tester0 37 # number of ReadExReq hits -system.l2subsys0.cache2.ReadExReq_hits::l0subsys2.tester1 43 # number of ReadExReq hits -system.l2subsys0.cache2.ReadExReq_hits::l0subsys3.tester0 54 # number of ReadExReq hits -system.l2subsys0.cache2.ReadExReq_hits::l0subsys3.tester1 63 # number of ReadExReq hits -system.l2subsys0.cache2.ReadExReq_hits::total 197 # number of ReadExReq hits -system.l2subsys0.cache2.ReadSharedReq_hits::l0subsys2.tester0 624 # number of ReadSharedReq hits -system.l2subsys0.cache2.ReadSharedReq_hits::l0subsys2.tester1 645 # number of ReadSharedReq hits -system.l2subsys0.cache2.ReadSharedReq_hits::l0subsys3.tester0 739 # number of ReadSharedReq hits -system.l2subsys0.cache2.ReadSharedReq_hits::l0subsys3.tester1 680 # number of ReadSharedReq hits -system.l2subsys0.cache2.ReadSharedReq_hits::total 2688 # number of ReadSharedReq hits -system.l2subsys0.cache2.demand_hits::l0subsys2.tester0 661 # number of demand (read+write) hits -system.l2subsys0.cache2.demand_hits::l0subsys2.tester1 688 # number of demand (read+write) hits -system.l2subsys0.cache2.demand_hits::l0subsys3.tester0 793 # number of demand (read+write) hits -system.l2subsys0.cache2.demand_hits::l0subsys3.tester1 743 # number of demand (read+write) hits -system.l2subsys0.cache2.demand_hits::total 2885 # number of demand (read+write) hits -system.l2subsys0.cache2.overall_hits::l0subsys2.tester0 661 # number of overall hits -system.l2subsys0.cache2.overall_hits::l0subsys2.tester1 688 # number of overall hits -system.l2subsys0.cache2.overall_hits::l0subsys3.tester0 793 # number of overall hits -system.l2subsys0.cache2.overall_hits::l0subsys3.tester1 743 # number of overall hits -system.l2subsys0.cache2.overall_hits::total 2885 # number of overall hits -system.l2subsys0.cache2.UpgradeReq_misses::l0subsys2.tester0 3779 # number of UpgradeReq misses -system.l2subsys0.cache2.UpgradeReq_misses::l0subsys2.tester1 3809 # number of UpgradeReq misses -system.l2subsys0.cache2.UpgradeReq_misses::l0subsys3.tester0 3732 # number of UpgradeReq misses -system.l2subsys0.cache2.UpgradeReq_misses::l0subsys3.tester1 3718 # number of UpgradeReq misses -system.l2subsys0.cache2.UpgradeReq_misses::total 15038 # number of UpgradeReq misses -system.l2subsys0.cache2.ReadExReq_misses::l0subsys2.tester0 15930 # number of ReadExReq misses -system.l2subsys0.cache2.ReadExReq_misses::l0subsys2.tester1 16135 # number of ReadExReq misses -system.l2subsys0.cache2.ReadExReq_misses::l0subsys3.tester0 16698 # number of ReadExReq misses -system.l2subsys0.cache2.ReadExReq_misses::l0subsys3.tester1 16012 # number of ReadExReq misses -system.l2subsys0.cache2.ReadExReq_misses::total 64775 # number of ReadExReq misses -system.l2subsys0.cache2.ReadSharedReq_misses::l0subsys2.tester0 28567 # number of ReadSharedReq misses -system.l2subsys0.cache2.ReadSharedReq_misses::l0subsys2.tester1 28110 # number of ReadSharedReq misses -system.l2subsys0.cache2.ReadSharedReq_misses::l0subsys3.tester0 28999 # number of ReadSharedReq misses -system.l2subsys0.cache2.ReadSharedReq_misses::l0subsys3.tester1 28006 # number of ReadSharedReq misses -system.l2subsys0.cache2.ReadSharedReq_misses::total 113682 # number of ReadSharedReq misses -system.l2subsys0.cache2.demand_misses::l0subsys2.tester0 44497 # number of demand (read+write) misses -system.l2subsys0.cache2.demand_misses::l0subsys2.tester1 44245 # number of demand (read+write) misses -system.l2subsys0.cache2.demand_misses::l0subsys3.tester0 45697 # number of demand (read+write) misses -system.l2subsys0.cache2.demand_misses::l0subsys3.tester1 44018 # number of demand (read+write) misses -system.l2subsys0.cache2.demand_misses::total 178457 # number of demand (read+write) misses -system.l2subsys0.cache2.overall_misses::l0subsys2.tester0 44497 # number of overall misses -system.l2subsys0.cache2.overall_misses::l0subsys2.tester1 44245 # number of overall misses -system.l2subsys0.cache2.overall_misses::l0subsys3.tester0 45697 # number of overall misses -system.l2subsys0.cache2.overall_misses::l0subsys3.tester1 44018 # number of overall misses -system.l2subsys0.cache2.overall_misses::total 178457 # number of overall misses -system.l2subsys0.cache2.UpgradeReq_miss_latency::l0subsys2.tester0 67563408 # number of UpgradeReq miss cycles -system.l2subsys0.cache2.UpgradeReq_miss_latency::l0subsys2.tester1 65236743 # number of UpgradeReq miss cycles -system.l2subsys0.cache2.UpgradeReq_miss_latency::l0subsys3.tester0 64646512 # number of UpgradeReq miss cycles -system.l2subsys0.cache2.UpgradeReq_miss_latency::l0subsys3.tester1 61011114 # number of UpgradeReq miss cycles -system.l2subsys0.cache2.UpgradeReq_miss_latency::total 258457777 # number of UpgradeReq miss cycles -system.l2subsys0.cache2.ReadExReq_miss_latency::l0subsys2.tester0 1543612037 # number of ReadExReq miss cycles -system.l2subsys0.cache2.ReadExReq_miss_latency::l0subsys2.tester1 1560300540 # number of ReadExReq miss cycles -system.l2subsys0.cache2.ReadExReq_miss_latency::l0subsys3.tester0 1583219117 # number of ReadExReq miss cycles -system.l2subsys0.cache2.ReadExReq_miss_latency::l0subsys3.tester1 1530352863 # number of ReadExReq miss cycles -system.l2subsys0.cache2.ReadExReq_miss_latency::total 6217484557 # number of ReadExReq miss cycles -system.l2subsys0.cache2.ReadSharedReq_miss_latency::l0subsys2.tester0 2752412028 # number of ReadSharedReq miss cycles -system.l2subsys0.cache2.ReadSharedReq_miss_latency::l0subsys2.tester1 2714107363 # number of ReadSharedReq miss cycles -system.l2subsys0.cache2.ReadSharedReq_miss_latency::l0subsys3.tester0 2778714049 # number of ReadSharedReq miss cycles -system.l2subsys0.cache2.ReadSharedReq_miss_latency::l0subsys3.tester1 2679096326 # number of ReadSharedReq miss cycles -system.l2subsys0.cache2.ReadSharedReq_miss_latency::total 10924329766 # number of ReadSharedReq miss cycles -system.l2subsys0.cache2.demand_miss_latency::l0subsys2.tester0 4296024065 # number of demand (read+write) miss cycles -system.l2subsys0.cache2.demand_miss_latency::l0subsys2.tester1 4274407903 # number of demand (read+write) miss cycles -system.l2subsys0.cache2.demand_miss_latency::l0subsys3.tester0 4361933166 # number of demand (read+write) miss cycles -system.l2subsys0.cache2.demand_miss_latency::l0subsys3.tester1 4209449189 # number of demand (read+write) miss cycles -system.l2subsys0.cache2.demand_miss_latency::total 17141814323 # number of demand (read+write) miss cycles -system.l2subsys0.cache2.overall_miss_latency::l0subsys2.tester0 4296024065 # number of overall miss cycles -system.l2subsys0.cache2.overall_miss_latency::l0subsys2.tester1 4274407903 # number of overall miss cycles -system.l2subsys0.cache2.overall_miss_latency::l0subsys3.tester0 4361933166 # number of overall miss cycles -system.l2subsys0.cache2.overall_miss_latency::l0subsys3.tester1 4209449189 # number of overall miss cycles -system.l2subsys0.cache2.overall_miss_latency::total 17141814323 # number of overall miss cycles -system.l2subsys0.cache2.WritebackDirty_accesses::writebacks 45683 # number of WritebackDirty accesses(hits+misses) -system.l2subsys0.cache2.WritebackDirty_accesses::total 45683 # number of WritebackDirty accesses(hits+misses) -system.l2subsys0.cache2.UpgradeReq_accesses::l0subsys2.tester0 3779 # number of UpgradeReq accesses(hits+misses) -system.l2subsys0.cache2.UpgradeReq_accesses::l0subsys2.tester1 3809 # number of UpgradeReq accesses(hits+misses) -system.l2subsys0.cache2.UpgradeReq_accesses::l0subsys3.tester0 3732 # number of UpgradeReq accesses(hits+misses) -system.l2subsys0.cache2.UpgradeReq_accesses::l0subsys3.tester1 3718 # number of UpgradeReq accesses(hits+misses) -system.l2subsys0.cache2.UpgradeReq_accesses::total 15038 # number of UpgradeReq accesses(hits+misses) -system.l2subsys0.cache2.ReadExReq_accesses::l0subsys2.tester0 15967 # number of ReadExReq accesses(hits+misses) -system.l2subsys0.cache2.ReadExReq_accesses::l0subsys2.tester1 16178 # number of ReadExReq accesses(hits+misses) -system.l2subsys0.cache2.ReadExReq_accesses::l0subsys3.tester0 16752 # number of ReadExReq accesses(hits+misses) -system.l2subsys0.cache2.ReadExReq_accesses::l0subsys3.tester1 16075 # number of ReadExReq accesses(hits+misses) -system.l2subsys0.cache2.ReadExReq_accesses::total 64972 # number of ReadExReq accesses(hits+misses) -system.l2subsys0.cache2.ReadSharedReq_accesses::l0subsys2.tester0 29191 # number of ReadSharedReq accesses(hits+misses) -system.l2subsys0.cache2.ReadSharedReq_accesses::l0subsys2.tester1 28755 # number of ReadSharedReq accesses(hits+misses) -system.l2subsys0.cache2.ReadSharedReq_accesses::l0subsys3.tester0 29738 # number of ReadSharedReq accesses(hits+misses) -system.l2subsys0.cache2.ReadSharedReq_accesses::l0subsys3.tester1 28686 # number of ReadSharedReq accesses(hits+misses) -system.l2subsys0.cache2.ReadSharedReq_accesses::total 116370 # number of ReadSharedReq accesses(hits+misses) -system.l2subsys0.cache2.demand_accesses::l0subsys2.tester0 45158 # number of demand (read+write) accesses -system.l2subsys0.cache2.demand_accesses::l0subsys2.tester1 44933 # number of demand (read+write) accesses -system.l2subsys0.cache2.demand_accesses::l0subsys3.tester0 46490 # number of demand (read+write) accesses -system.l2subsys0.cache2.demand_accesses::l0subsys3.tester1 44761 # number of demand (read+write) accesses -system.l2subsys0.cache2.demand_accesses::total 181342 # number of demand (read+write) accesses -system.l2subsys0.cache2.overall_accesses::l0subsys2.tester0 45158 # number of overall (read+write) accesses -system.l2subsys0.cache2.overall_accesses::l0subsys2.tester1 44933 # number of overall (read+write) accesses -system.l2subsys0.cache2.overall_accesses::l0subsys3.tester0 46490 # number of overall (read+write) accesses -system.l2subsys0.cache2.overall_accesses::l0subsys3.tester1 44761 # number of overall (read+write) accesses -system.l2subsys0.cache2.overall_accesses::total 181342 # number of overall (read+write) accesses -system.l2subsys0.cache2.UpgradeReq_miss_rate::l0subsys2.tester0 1 # miss rate for UpgradeReq accesses -system.l2subsys0.cache2.UpgradeReq_miss_rate::l0subsys2.tester1 1 # miss rate for UpgradeReq accesses -system.l2subsys0.cache2.UpgradeReq_miss_rate::l0subsys3.tester0 1 # miss rate for UpgradeReq accesses -system.l2subsys0.cache2.UpgradeReq_miss_rate::l0subsys3.tester1 1 # miss rate for UpgradeReq accesses -system.l2subsys0.cache2.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses -system.l2subsys0.cache2.ReadExReq_miss_rate::l0subsys2.tester0 0.997683 # miss rate for ReadExReq accesses -system.l2subsys0.cache2.ReadExReq_miss_rate::l0subsys2.tester1 0.997342 # miss rate for ReadExReq accesses -system.l2subsys0.cache2.ReadExReq_miss_rate::l0subsys3.tester0 0.996777 # miss rate for ReadExReq accesses -system.l2subsys0.cache2.ReadExReq_miss_rate::l0subsys3.tester1 0.996081 # miss rate for ReadExReq accesses -system.l2subsys0.cache2.ReadExReq_miss_rate::total 0.996968 # miss rate for ReadExReq accesses -system.l2subsys0.cache2.ReadSharedReq_miss_rate::l0subsys2.tester0 0.978624 # miss rate for ReadSharedReq accesses -system.l2subsys0.cache2.ReadSharedReq_miss_rate::l0subsys2.tester1 0.977569 # miss rate for ReadSharedReq accesses -system.l2subsys0.cache2.ReadSharedReq_miss_rate::l0subsys3.tester0 0.975150 # miss rate for ReadSharedReq accesses -system.l2subsys0.cache2.ReadSharedReq_miss_rate::l0subsys3.tester1 0.976295 # miss rate for ReadSharedReq accesses -system.l2subsys0.cache2.ReadSharedReq_miss_rate::total 0.976901 # miss rate for ReadSharedReq accesses -system.l2subsys0.cache2.demand_miss_rate::l0subsys2.tester0 0.985363 # miss rate for demand accesses -system.l2subsys0.cache2.demand_miss_rate::l0subsys2.tester1 0.984688 # miss rate for demand accesses -system.l2subsys0.cache2.demand_miss_rate::l0subsys3.tester0 0.982943 # miss rate for demand accesses -system.l2subsys0.cache2.demand_miss_rate::l0subsys3.tester1 0.983401 # miss rate for demand accesses -system.l2subsys0.cache2.demand_miss_rate::total 0.984091 # miss rate for demand accesses -system.l2subsys0.cache2.overall_miss_rate::l0subsys2.tester0 0.985363 # miss rate for overall accesses -system.l2subsys0.cache2.overall_miss_rate::l0subsys2.tester1 0.984688 # miss rate for overall accesses -system.l2subsys0.cache2.overall_miss_rate::l0subsys3.tester0 0.982943 # miss rate for overall accesses -system.l2subsys0.cache2.overall_miss_rate::l0subsys3.tester1 0.983401 # miss rate for overall accesses -system.l2subsys0.cache2.overall_miss_rate::total 0.984091 # miss rate for overall accesses -system.l2subsys0.cache2.UpgradeReq_avg_miss_latency::l0subsys2.tester0 17878.647261 # average UpgradeReq miss latency -system.l2subsys0.cache2.UpgradeReq_avg_miss_latency::l0subsys2.tester1 17127 # average UpgradeReq miss latency -system.l2subsys0.cache2.UpgradeReq_avg_miss_latency::l0subsys3.tester0 17322.216506 # average UpgradeReq miss latency -system.l2subsys0.cache2.UpgradeReq_avg_miss_latency::l0subsys3.tester1 16409.659494 # average UpgradeReq miss latency -system.l2subsys0.cache2.UpgradeReq_avg_miss_latency::total 17186.978122 # average UpgradeReq miss latency -system.l2subsys0.cache2.ReadExReq_avg_miss_latency::l0subsys2.tester0 96899.688449 # average ReadExReq miss latency -system.l2subsys0.cache2.ReadExReq_avg_miss_latency::l0subsys2.tester1 96702.853424 # average ReadExReq miss latency -system.l2subsys0.cache2.ReadExReq_avg_miss_latency::l0subsys3.tester0 94814.895017 # average ReadExReq miss latency -system.l2subsys0.cache2.ReadExReq_avg_miss_latency::l0subsys3.tester1 95575.372408 # average ReadExReq miss latency -system.l2subsys0.cache2.ReadExReq_avg_miss_latency::total 95985.867341 # average ReadExReq miss latency -system.l2subsys0.cache2.ReadSharedReq_avg_miss_latency::l0subsys2.tester0 96349.355130 # average ReadSharedReq miss latency -system.l2subsys0.cache2.ReadSharedReq_avg_miss_latency::l0subsys2.tester1 96553.090110 # average ReadSharedReq miss latency -system.l2subsys0.cache2.ReadSharedReq_avg_miss_latency::l0subsys3.tester0 95821.030001 # average ReadSharedReq miss latency -system.l2subsys0.cache2.ReadSharedReq_avg_miss_latency::l0subsys3.tester1 95661.512747 # average ReadSharedReq miss latency -system.l2subsys0.cache2.ReadSharedReq_avg_miss_latency::total 96095.509984 # average ReadSharedReq miss latency -system.l2subsys0.cache2.demand_avg_miss_latency::l0subsys2.tester0 96546.375374 # average overall miss latency -system.l2subsys0.cache2.demand_avg_miss_latency::l0subsys2.tester1 96607.704893 # average overall miss latency -system.l2subsys0.cache2.demand_avg_miss_latency::l0subsys3.tester0 95453.381316 # average overall miss latency -system.l2subsys0.cache2.demand_avg_miss_latency::l0subsys3.tester1 95630.178313 # average overall miss latency -system.l2subsys0.cache2.demand_avg_miss_latency::total 96055.712710 # average overall miss latency -system.l2subsys0.cache2.overall_avg_miss_latency::l0subsys2.tester0 96546.375374 # average overall miss latency -system.l2subsys0.cache2.overall_avg_miss_latency::l0subsys2.tester1 96607.704893 # average overall miss latency -system.l2subsys0.cache2.overall_avg_miss_latency::l0subsys3.tester0 95453.381316 # average overall miss latency -system.l2subsys0.cache2.overall_avg_miss_latency::l0subsys3.tester1 95630.178313 # average overall miss latency -system.l2subsys0.cache2.overall_avg_miss_latency::total 96055.712710 # average overall miss latency +system.l2subsys0.cache2.WritebackDirty_hits::writebacks 45595 # number of WritebackDirty hits +system.l2subsys0.cache2.WritebackDirty_hits::total 45595 # number of WritebackDirty hits +system.l2subsys0.cache2.UpgradeReq_hits::l0subsys2.tester0 140 # number of UpgradeReq hits +system.l2subsys0.cache2.UpgradeReq_hits::l0subsys2.tester1 149 # number of UpgradeReq hits +system.l2subsys0.cache2.UpgradeReq_hits::l0subsys3.tester0 120 # number of UpgradeReq hits +system.l2subsys0.cache2.UpgradeReq_hits::l0subsys3.tester1 184 # number of UpgradeReq hits +system.l2subsys0.cache2.UpgradeReq_hits::total 593 # number of UpgradeReq hits +system.l2subsys0.cache2.ReadExReq_hits::l0subsys2.tester0 45 # number of ReadExReq hits +system.l2subsys0.cache2.ReadExReq_hits::l0subsys2.tester1 36 # number of ReadExReq hits +system.l2subsys0.cache2.ReadExReq_hits::l0subsys3.tester0 49 # number of ReadExReq hits +system.l2subsys0.cache2.ReadExReq_hits::l0subsys3.tester1 30 # number of ReadExReq hits +system.l2subsys0.cache2.ReadExReq_hits::total 160 # number of ReadExReq hits +system.l2subsys0.cache2.ReadSharedReq_hits::l0subsys2.tester0 644 # number of ReadSharedReq hits +system.l2subsys0.cache2.ReadSharedReq_hits::l0subsys2.tester1 713 # number of ReadSharedReq hits +system.l2subsys0.cache2.ReadSharedReq_hits::l0subsys3.tester0 722 # number of ReadSharedReq hits +system.l2subsys0.cache2.ReadSharedReq_hits::l0subsys3.tester1 725 # number of ReadSharedReq hits +system.l2subsys0.cache2.ReadSharedReq_hits::total 2804 # number of ReadSharedReq hits +system.l2subsys0.cache2.demand_hits::l0subsys2.tester0 689 # number of demand (read+write) hits +system.l2subsys0.cache2.demand_hits::l0subsys2.tester1 749 # number of demand (read+write) hits +system.l2subsys0.cache2.demand_hits::l0subsys3.tester0 771 # number of demand (read+write) hits +system.l2subsys0.cache2.demand_hits::l0subsys3.tester1 755 # number of demand (read+write) hits +system.l2subsys0.cache2.demand_hits::total 2964 # number of demand (read+write) hits +system.l2subsys0.cache2.overall_hits::l0subsys2.tester0 689 # number of overall hits +system.l2subsys0.cache2.overall_hits::l0subsys2.tester1 749 # number of overall hits +system.l2subsys0.cache2.overall_hits::l0subsys3.tester0 771 # number of overall hits +system.l2subsys0.cache2.overall_hits::l0subsys3.tester1 755 # number of overall hits +system.l2subsys0.cache2.overall_hits::total 2964 # number of overall hits +system.l2subsys0.cache2.UpgradeReq_misses::l0subsys2.tester0 3731 # number of UpgradeReq misses +system.l2subsys0.cache2.UpgradeReq_misses::l0subsys2.tester1 3588 # number of UpgradeReq misses +system.l2subsys0.cache2.UpgradeReq_misses::l0subsys3.tester0 3374 # number of UpgradeReq misses +system.l2subsys0.cache2.UpgradeReq_misses::l0subsys3.tester1 3500 # number of UpgradeReq misses +system.l2subsys0.cache2.UpgradeReq_misses::total 14193 # number of UpgradeReq misses +system.l2subsys0.cache2.ReadExReq_misses::l0subsys2.tester0 16480 # number of ReadExReq misses +system.l2subsys0.cache2.ReadExReq_misses::l0subsys2.tester1 16325 # number of ReadExReq misses +system.l2subsys0.cache2.ReadExReq_misses::l0subsys3.tester0 16664 # number of ReadExReq misses +system.l2subsys0.cache2.ReadExReq_misses::l0subsys3.tester1 16716 # number of ReadExReq misses +system.l2subsys0.cache2.ReadExReq_misses::total 66185 # number of ReadExReq misses +system.l2subsys0.cache2.ReadSharedReq_misses::l0subsys2.tester0 28695 # number of ReadSharedReq misses +system.l2subsys0.cache2.ReadSharedReq_misses::l0subsys2.tester1 28471 # number of ReadSharedReq misses +system.l2subsys0.cache2.ReadSharedReq_misses::l0subsys3.tester0 29046 # number of ReadSharedReq misses +system.l2subsys0.cache2.ReadSharedReq_misses::l0subsys3.tester1 28633 # number of ReadSharedReq misses +system.l2subsys0.cache2.ReadSharedReq_misses::total 114845 # number of ReadSharedReq misses +system.l2subsys0.cache2.demand_misses::l0subsys2.tester0 45175 # number of demand (read+write) misses +system.l2subsys0.cache2.demand_misses::l0subsys2.tester1 44796 # number of demand (read+write) misses +system.l2subsys0.cache2.demand_misses::l0subsys3.tester0 45710 # number of demand (read+write) misses +system.l2subsys0.cache2.demand_misses::l0subsys3.tester1 45349 # number of demand (read+write) misses +system.l2subsys0.cache2.demand_misses::total 181030 # number of demand (read+write) misses +system.l2subsys0.cache2.overall_misses::l0subsys2.tester0 45175 # number of overall misses +system.l2subsys0.cache2.overall_misses::l0subsys2.tester1 44796 # number of overall misses +system.l2subsys0.cache2.overall_misses::l0subsys3.tester0 45710 # number of overall misses +system.l2subsys0.cache2.overall_misses::l0subsys3.tester1 45349 # number of overall misses +system.l2subsys0.cache2.overall_misses::total 181030 # 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number of demand (read+write) miss cycles +system.l2subsys0.cache2.demand_miss_latency::total 17217461942 # number of demand (read+write) miss cycles +system.l2subsys0.cache2.overall_miss_latency::l0subsys2.tester0 4292227269 # number of overall miss cycles +system.l2subsys0.cache2.overall_miss_latency::l0subsys2.tester1 4302911588 # number of overall miss cycles +system.l2subsys0.cache2.overall_miss_latency::l0subsys3.tester0 4367629970 # number of overall miss cycles +system.l2subsys0.cache2.overall_miss_latency::l0subsys3.tester1 4254693115 # number of overall miss cycles +system.l2subsys0.cache2.overall_miss_latency::total 17217461942 # number of overall miss cycles +system.l2subsys0.cache2.WritebackDirty_accesses::writebacks 45595 # number of WritebackDirty accesses(hits+misses) +system.l2subsys0.cache2.WritebackDirty_accesses::total 45595 # number of WritebackDirty accesses(hits+misses) +system.l2subsys0.cache2.UpgradeReq_accesses::l0subsys2.tester0 3871 # number of UpgradeReq accesses(hits+misses) +system.l2subsys0.cache2.UpgradeReq_accesses::l0subsys2.tester1 3737 # number of UpgradeReq accesses(hits+misses) +system.l2subsys0.cache2.UpgradeReq_accesses::l0subsys3.tester0 3494 # number of UpgradeReq accesses(hits+misses) +system.l2subsys0.cache2.UpgradeReq_accesses::l0subsys3.tester1 3684 # number of UpgradeReq accesses(hits+misses) +system.l2subsys0.cache2.UpgradeReq_accesses::total 14786 # number of UpgradeReq accesses(hits+misses) +system.l2subsys0.cache2.ReadExReq_accesses::l0subsys2.tester0 16525 # number of ReadExReq accesses(hits+misses) +system.l2subsys0.cache2.ReadExReq_accesses::l0subsys2.tester1 16361 # number of ReadExReq accesses(hits+misses) +system.l2subsys0.cache2.ReadExReq_accesses::l0subsys3.tester0 16713 # number of ReadExReq accesses(hits+misses) +system.l2subsys0.cache2.ReadExReq_accesses::l0subsys3.tester1 16746 # number of ReadExReq accesses(hits+misses) +system.l2subsys0.cache2.ReadExReq_accesses::total 66345 # number of ReadExReq accesses(hits+misses) +system.l2subsys0.cache2.ReadSharedReq_accesses::l0subsys2.tester0 29339 # number of ReadSharedReq accesses(hits+misses) +system.l2subsys0.cache2.ReadSharedReq_accesses::l0subsys2.tester1 29184 # number of ReadSharedReq accesses(hits+misses) +system.l2subsys0.cache2.ReadSharedReq_accesses::l0subsys3.tester0 29768 # number of ReadSharedReq accesses(hits+misses) +system.l2subsys0.cache2.ReadSharedReq_accesses::l0subsys3.tester1 29358 # number of ReadSharedReq accesses(hits+misses) +system.l2subsys0.cache2.ReadSharedReq_accesses::total 117649 # number of ReadSharedReq accesses(hits+misses) +system.l2subsys0.cache2.demand_accesses::l0subsys2.tester0 45864 # number of demand (read+write) accesses +system.l2subsys0.cache2.demand_accesses::l0subsys2.tester1 45545 # number of demand (read+write) accesses +system.l2subsys0.cache2.demand_accesses::l0subsys3.tester0 46481 # number of demand (read+write) accesses +system.l2subsys0.cache2.demand_accesses::l0subsys3.tester1 46104 # number of demand (read+write) accesses +system.l2subsys0.cache2.demand_accesses::total 183994 # number of demand (read+write) accesses +system.l2subsys0.cache2.overall_accesses::l0subsys2.tester0 45864 # number of overall (read+write) accesses +system.l2subsys0.cache2.overall_accesses::l0subsys2.tester1 45545 # number of overall (read+write) accesses +system.l2subsys0.cache2.overall_accesses::l0subsys3.tester0 46481 # number of overall (read+write) accesses +system.l2subsys0.cache2.overall_accesses::l0subsys3.tester1 46104 # number of overall (read+write) accesses +system.l2subsys0.cache2.overall_accesses::total 183994 # number of overall (read+write) accesses +system.l2subsys0.cache2.UpgradeReq_miss_rate::l0subsys2.tester0 0.963834 # miss rate for UpgradeReq accesses +system.l2subsys0.cache2.UpgradeReq_miss_rate::l0subsys2.tester1 0.960128 # miss rate for UpgradeReq accesses +system.l2subsys0.cache2.UpgradeReq_miss_rate::l0subsys3.tester0 0.965655 # miss rate for UpgradeReq accesses +system.l2subsys0.cache2.UpgradeReq_miss_rate::l0subsys3.tester1 0.950054 # miss rate for UpgradeReq accesses +system.l2subsys0.cache2.UpgradeReq_miss_rate::total 0.959894 # miss rate for UpgradeReq accesses +system.l2subsys0.cache2.ReadExReq_miss_rate::l0subsys2.tester0 0.997277 # miss rate for ReadExReq accesses +system.l2subsys0.cache2.ReadExReq_miss_rate::l0subsys2.tester1 0.997800 # miss rate for ReadExReq accesses +system.l2subsys0.cache2.ReadExReq_miss_rate::l0subsys3.tester0 0.997068 # miss rate for ReadExReq accesses +system.l2subsys0.cache2.ReadExReq_miss_rate::l0subsys3.tester1 0.998209 # miss rate for ReadExReq accesses +system.l2subsys0.cache2.ReadExReq_miss_rate::total 0.997588 # miss rate for ReadExReq accesses +system.l2subsys0.cache2.ReadSharedReq_miss_rate::l0subsys2.tester0 0.978050 # miss rate for ReadSharedReq accesses +system.l2subsys0.cache2.ReadSharedReq_miss_rate::l0subsys2.tester1 0.975569 # miss rate for ReadSharedReq accesses +system.l2subsys0.cache2.ReadSharedReq_miss_rate::l0subsys3.tester0 0.975746 # miss rate for ReadSharedReq accesses +system.l2subsys0.cache2.ReadSharedReq_miss_rate::l0subsys3.tester1 0.975305 # miss rate for ReadSharedReq accesses +system.l2subsys0.cache2.ReadSharedReq_miss_rate::total 0.976166 # miss rate for ReadSharedReq accesses +system.l2subsys0.cache2.demand_miss_rate::l0subsys2.tester0 0.984977 # miss rate for demand accesses +system.l2subsys0.cache2.demand_miss_rate::l0subsys2.tester1 0.983555 # miss rate for demand accesses +system.l2subsys0.cache2.demand_miss_rate::l0subsys3.tester0 0.983413 # miss rate for demand accesses +system.l2subsys0.cache2.demand_miss_rate::l0subsys3.tester1 0.983624 # miss rate for demand accesses +system.l2subsys0.cache2.demand_miss_rate::total 0.983891 # miss rate for demand accesses +system.l2subsys0.cache2.overall_miss_rate::l0subsys2.tester0 0.984977 # miss rate for overall accesses +system.l2subsys0.cache2.overall_miss_rate::l0subsys2.tester1 0.983555 # miss rate for overall accesses +system.l2subsys0.cache2.overall_miss_rate::l0subsys3.tester0 0.983413 # miss rate for overall accesses +system.l2subsys0.cache2.overall_miss_rate::l0subsys3.tester1 0.983624 # miss rate for overall accesses +system.l2subsys0.cache2.overall_miss_rate::total 0.983891 # miss rate for overall accesses +system.l2subsys0.cache2.UpgradeReq_avg_miss_latency::l0subsys2.tester0 32455.559635 # average UpgradeReq miss latency +system.l2subsys0.cache2.UpgradeReq_avg_miss_latency::l0subsys2.tester1 33064.297659 # average UpgradeReq miss latency +system.l2subsys0.cache2.UpgradeReq_avg_miss_latency::l0subsys3.tester0 32822.571132 # average UpgradeReq miss latency +system.l2subsys0.cache2.UpgradeReq_avg_miss_latency::l0subsys3.tester1 33124.631143 # average UpgradeReq miss latency +system.l2subsys0.cache2.UpgradeReq_avg_miss_latency::total 32861.689354 # average UpgradeReq miss latency +system.l2subsys0.cache2.ReadExReq_avg_miss_latency::l0subsys2.tester0 94790.030158 # average ReadExReq miss latency +system.l2subsys0.cache2.ReadExReq_avg_miss_latency::l0subsys2.tester1 94919.132129 # average ReadExReq miss latency +system.l2subsys0.cache2.ReadExReq_avg_miss_latency::l0subsys3.tester0 95822.256481 # average ReadExReq miss latency +system.l2subsys0.cache2.ReadExReq_avg_miss_latency::l0subsys3.tester1 93318.196877 # average ReadExReq miss latency +system.l2subsys0.cache2.ReadExReq_avg_miss_latency::total 94710.033845 # average ReadExReq miss latency +system.l2subsys0.cache2.ReadSharedReq_avg_miss_latency::l0subsys2.tester0 95141.577696 # average ReadSharedReq miss latency +system.l2subsys0.cache2.ReadSharedReq_avg_miss_latency::l0subsys2.tester1 96707.413017 # average ReadSharedReq miss latency +system.l2subsys0.cache2.ReadSharedReq_avg_miss_latency::l0subsys3.tester0 95395.162432 # average ReadSharedReq miss latency +system.l2subsys0.cache2.ReadSharedReq_avg_miss_latency::l0subsys3.tester1 94114.697587 # average ReadSharedReq miss latency +system.l2subsys0.cache2.ReadSharedReq_avg_miss_latency::total 95337.875850 # average ReadSharedReq miss latency +system.l2subsys0.cache2.demand_avg_miss_latency::l0subsys2.tester0 95013.331909 # average overall miss latency +system.l2subsys0.cache2.demand_avg_miss_latency::l0subsys2.tester1 96055.710063 # average overall miss latency +system.l2subsys0.cache2.demand_avg_miss_latency::l0subsys3.tester0 95550.863487 # average overall miss latency +system.l2subsys0.cache2.demand_avg_miss_latency::l0subsys3.tester1 93821.101127 # average overall miss latency +system.l2subsys0.cache2.demand_avg_miss_latency::total 95108.335315 # average overall miss latency +system.l2subsys0.cache2.overall_avg_miss_latency::l0subsys2.tester0 95013.331909 # average overall miss latency +system.l2subsys0.cache2.overall_avg_miss_latency::l0subsys2.tester1 96055.710063 # average overall miss latency +system.l2subsys0.cache2.overall_avg_miss_latency::l0subsys3.tester0 95550.863487 # average overall miss latency +system.l2subsys0.cache2.overall_avg_miss_latency::l0subsys3.tester1 93821.101127 # average overall miss latency +system.l2subsys0.cache2.overall_avg_miss_latency::total 95108.335315 # average overall miss latency system.l2subsys0.cache2.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2subsys0.cache2.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2subsys0.cache2.blocked::no_mshrs 0 # number of cycles access was blocked system.l2subsys0.cache2.blocked::no_targets 0 # number of cycles access was blocked system.l2subsys0.cache2.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.l2subsys0.cache2.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.l2subsys0.cache2.writebacks::writebacks 44827 # number of writebacks -system.l2subsys0.cache2.writebacks::total 44827 # number of writebacks -system.l2subsys0.cache2.ReadExReq_mshr_hits::l0subsys2.tester0 237 # number of ReadExReq MSHR hits -system.l2subsys0.cache2.ReadExReq_mshr_hits::l0subsys2.tester1 298 # number of ReadExReq MSHR hits -system.l2subsys0.cache2.ReadExReq_mshr_hits::l0subsys3.tester0 265 # number of ReadExReq MSHR hits -system.l2subsys0.cache2.ReadExReq_mshr_hits::l0subsys3.tester1 283 # number of ReadExReq MSHR hits -system.l2subsys0.cache2.ReadExReq_mshr_hits::total 1083 # number of ReadExReq MSHR hits -system.l2subsys0.cache2.ReadSharedReq_mshr_hits::l0subsys2.tester0 402 # number of ReadSharedReq MSHR hits -system.l2subsys0.cache2.ReadSharedReq_mshr_hits::l0subsys2.tester1 551 # number of ReadSharedReq MSHR hits -system.l2subsys0.cache2.ReadSharedReq_mshr_hits::l0subsys3.tester0 515 # number of ReadSharedReq MSHR hits -system.l2subsys0.cache2.ReadSharedReq_mshr_hits::l0subsys3.tester1 507 # number of ReadSharedReq MSHR hits -system.l2subsys0.cache2.ReadSharedReq_mshr_hits::total 1975 # number of ReadSharedReq MSHR hits -system.l2subsys0.cache2.demand_mshr_hits::l0subsys2.tester0 639 # number of demand (read+write) MSHR hits -system.l2subsys0.cache2.demand_mshr_hits::l0subsys2.tester1 849 # number of demand (read+write) MSHR hits -system.l2subsys0.cache2.demand_mshr_hits::l0subsys3.tester0 780 # number of demand (read+write) MSHR hits -system.l2subsys0.cache2.demand_mshr_hits::l0subsys3.tester1 790 # number of demand (read+write) MSHR hits -system.l2subsys0.cache2.demand_mshr_hits::total 3058 # number of demand (read+write) MSHR hits -system.l2subsys0.cache2.overall_mshr_hits::l0subsys2.tester0 639 # number of overall MSHR hits -system.l2subsys0.cache2.overall_mshr_hits::l0subsys2.tester1 849 # number of overall MSHR hits -system.l2subsys0.cache2.overall_mshr_hits::l0subsys3.tester0 780 # number of overall MSHR hits -system.l2subsys0.cache2.overall_mshr_hits::l0subsys3.tester1 790 # number of overall MSHR hits -system.l2subsys0.cache2.overall_mshr_hits::total 3058 # number of overall MSHR hits -system.l2subsys0.cache2.CleanEvict_mshr_misses::writebacks 28677 # number of CleanEvict MSHR misses -system.l2subsys0.cache2.CleanEvict_mshr_misses::total 28677 # number of CleanEvict MSHR misses -system.l2subsys0.cache2.UpgradeReq_mshr_misses::l0subsys2.tester0 3779 # number of UpgradeReq MSHR misses -system.l2subsys0.cache2.UpgradeReq_mshr_misses::l0subsys2.tester1 3809 # number of UpgradeReq MSHR misses -system.l2subsys0.cache2.UpgradeReq_mshr_misses::l0subsys3.tester0 3732 # number of UpgradeReq MSHR misses -system.l2subsys0.cache2.UpgradeReq_mshr_misses::l0subsys3.tester1 3718 # number of UpgradeReq MSHR misses -system.l2subsys0.cache2.UpgradeReq_mshr_misses::total 15038 # number of UpgradeReq MSHR misses -system.l2subsys0.cache2.ReadExReq_mshr_misses::l0subsys2.tester0 15693 # number of ReadExReq MSHR misses -system.l2subsys0.cache2.ReadExReq_mshr_misses::l0subsys2.tester1 15837 # number of ReadExReq MSHR misses -system.l2subsys0.cache2.ReadExReq_mshr_misses::l0subsys3.tester0 16433 # number of ReadExReq MSHR misses -system.l2subsys0.cache2.ReadExReq_mshr_misses::l0subsys3.tester1 15729 # number of ReadExReq MSHR misses -system.l2subsys0.cache2.ReadExReq_mshr_misses::total 63692 # number of ReadExReq MSHR misses -system.l2subsys0.cache2.ReadSharedReq_mshr_misses::l0subsys2.tester0 28165 # number of ReadSharedReq MSHR misses -system.l2subsys0.cache2.ReadSharedReq_mshr_misses::l0subsys2.tester1 27559 # number of ReadSharedReq MSHR misses -system.l2subsys0.cache2.ReadSharedReq_mshr_misses::l0subsys3.tester0 28484 # number of ReadSharedReq MSHR misses -system.l2subsys0.cache2.ReadSharedReq_mshr_misses::l0subsys3.tester1 27499 # number of ReadSharedReq MSHR misses -system.l2subsys0.cache2.ReadSharedReq_mshr_misses::total 111707 # number of ReadSharedReq MSHR misses -system.l2subsys0.cache2.demand_mshr_misses::l0subsys2.tester0 43858 # number of demand (read+write) MSHR misses -system.l2subsys0.cache2.demand_mshr_misses::l0subsys2.tester1 43396 # number of demand (read+write) MSHR misses -system.l2subsys0.cache2.demand_mshr_misses::l0subsys3.tester0 44917 # number of demand (read+write) MSHR misses -system.l2subsys0.cache2.demand_mshr_misses::l0subsys3.tester1 43228 # number of demand (read+write) MSHR misses -system.l2subsys0.cache2.demand_mshr_misses::total 175399 # number of demand (read+write) MSHR misses -system.l2subsys0.cache2.overall_mshr_misses::l0subsys2.tester0 43858 # number of overall MSHR misses -system.l2subsys0.cache2.overall_mshr_misses::l0subsys2.tester1 43396 # number of overall MSHR misses -system.l2subsys0.cache2.overall_mshr_misses::l0subsys3.tester0 44917 # number of overall MSHR misses -system.l2subsys0.cache2.overall_mshr_misses::l0subsys3.tester1 43228 # number of overall MSHR misses -system.l2subsys0.cache2.overall_mshr_misses::total 175399 # number of overall MSHR misses -system.l2subsys0.cache2.UpgradeReq_mshr_miss_latency::l0subsys2.tester0 87716721 # number of UpgradeReq MSHR miss cycles -system.l2subsys0.cache2.UpgradeReq_mshr_miss_latency::l0subsys2.tester1 87523068 # number of UpgradeReq MSHR miss cycles -system.l2subsys0.cache2.UpgradeReq_mshr_miss_latency::l0subsys3.tester0 86908752 # number of UpgradeReq MSHR miss cycles -system.l2subsys0.cache2.UpgradeReq_mshr_miss_latency::l0subsys3.tester1 86127988 # number of UpgradeReq MSHR miss cycles -system.l2subsys0.cache2.UpgradeReq_mshr_miss_latency::total 348276529 # number of UpgradeReq MSHR miss cycles -system.l2subsys0.cache2.ReadExReq_mshr_miss_latency::l0subsys2.tester0 1378577336 # number of ReadExReq MSHR miss cycles -system.l2subsys0.cache2.ReadExReq_mshr_miss_latency::l0subsys2.tester1 1392761675 # number of ReadExReq MSHR miss cycles -system.l2subsys0.cache2.ReadExReq_mshr_miss_latency::l0subsys3.tester0 1410632488 # number of ReadExReq MSHR miss cycles -system.l2subsys0.cache2.ReadExReq_mshr_miss_latency::l0subsys3.tester1 1363736548 # number of ReadExReq MSHR miss cycles -system.l2subsys0.cache2.ReadExReq_mshr_miss_latency::total 5545708047 # number of ReadExReq MSHR miss cycles -system.l2subsys0.cache2.ReadSharedReq_mshr_miss_latency::l0subsys2.tester0 2460445117 # number of ReadSharedReq MSHR miss cycles -system.l2subsys0.cache2.ReadSharedReq_mshr_miss_latency::l0subsys2.tester1 2424688757 # number of ReadSharedReq MSHR miss cycles -system.l2subsys0.cache2.ReadSharedReq_mshr_miss_latency::l0subsys3.tester0 2480742193 # number of ReadSharedReq MSHR miss cycles -system.l2subsys0.cache2.ReadSharedReq_mshr_miss_latency::l0subsys3.tester1 2390942670 # number of ReadSharedReq MSHR miss cycles -system.l2subsys0.cache2.ReadSharedReq_mshr_miss_latency::total 9756818737 # number of ReadSharedReq MSHR miss cycles -system.l2subsys0.cache2.demand_mshr_miss_latency::l0subsys2.tester0 3839022453 # number of demand (read+write) MSHR miss cycles -system.l2subsys0.cache2.demand_mshr_miss_latency::l0subsys2.tester1 3817450432 # number of demand (read+write) MSHR miss cycles -system.l2subsys0.cache2.demand_mshr_miss_latency::l0subsys3.tester0 3891374681 # number of demand (read+write) MSHR miss cycles -system.l2subsys0.cache2.demand_mshr_miss_latency::l0subsys3.tester1 3754679218 # number of demand (read+write) MSHR miss cycles -system.l2subsys0.cache2.demand_mshr_miss_latency::total 15302526784 # number of demand (read+write) MSHR miss cycles -system.l2subsys0.cache2.overall_mshr_miss_latency::l0subsys2.tester0 3839022453 # number of overall MSHR miss cycles -system.l2subsys0.cache2.overall_mshr_miss_latency::l0subsys2.tester1 3817450432 # number of overall MSHR miss cycles -system.l2subsys0.cache2.overall_mshr_miss_latency::l0subsys3.tester0 3891374681 # number of overall MSHR miss cycles -system.l2subsys0.cache2.overall_mshr_miss_latency::l0subsys3.tester1 3754679218 # number of overall MSHR miss cycles -system.l2subsys0.cache2.overall_mshr_miss_latency::total 15302526784 # number of overall MSHR miss cycles +system.l2subsys0.cache2.writebacks::writebacks 44893 # number of writebacks +system.l2subsys0.cache2.writebacks::total 44893 # number of writebacks +system.l2subsys0.cache2.ReadExReq_mshr_hits::l0subsys2.tester0 353 # number of ReadExReq MSHR hits +system.l2subsys0.cache2.ReadExReq_mshr_hits::l0subsys2.tester1 327 # number of ReadExReq MSHR hits +system.l2subsys0.cache2.ReadExReq_mshr_hits::l0subsys3.tester0 327 # number of ReadExReq MSHR hits +system.l2subsys0.cache2.ReadExReq_mshr_hits::l0subsys3.tester1 345 # number of ReadExReq MSHR hits +system.l2subsys0.cache2.ReadExReq_mshr_hits::total 1352 # number of ReadExReq MSHR hits +system.l2subsys0.cache2.ReadSharedReq_mshr_hits::l0subsys2.tester0 566 # number of ReadSharedReq MSHR hits +system.l2subsys0.cache2.ReadSharedReq_mshr_hits::l0subsys2.tester1 596 # number of ReadSharedReq MSHR hits +system.l2subsys0.cache2.ReadSharedReq_mshr_hits::l0subsys3.tester0 556 # number of ReadSharedReq MSHR hits +system.l2subsys0.cache2.ReadSharedReq_mshr_hits::l0subsys3.tester1 587 # number of ReadSharedReq MSHR hits +system.l2subsys0.cache2.ReadSharedReq_mshr_hits::total 2305 # number of ReadSharedReq MSHR hits +system.l2subsys0.cache2.demand_mshr_hits::l0subsys2.tester0 919 # number of demand (read+write) MSHR hits +system.l2subsys0.cache2.demand_mshr_hits::l0subsys2.tester1 923 # number of demand (read+write) MSHR hits +system.l2subsys0.cache2.demand_mshr_hits::l0subsys3.tester0 883 # number of demand (read+write) MSHR hits +system.l2subsys0.cache2.demand_mshr_hits::l0subsys3.tester1 932 # number of demand (read+write) MSHR hits +system.l2subsys0.cache2.demand_mshr_hits::total 3657 # number of demand (read+write) MSHR hits +system.l2subsys0.cache2.overall_mshr_hits::l0subsys2.tester0 919 # number of overall MSHR hits +system.l2subsys0.cache2.overall_mshr_hits::l0subsys2.tester1 923 # number of overall MSHR hits +system.l2subsys0.cache2.overall_mshr_hits::l0subsys3.tester0 883 # number of overall MSHR hits +system.l2subsys0.cache2.overall_mshr_hits::l0subsys3.tester1 932 # number of overall MSHR hits +system.l2subsys0.cache2.overall_mshr_hits::total 3657 # number of overall MSHR hits +system.l2subsys0.cache2.CleanEvict_mshr_misses::writebacks 41439 # number of CleanEvict MSHR misses +system.l2subsys0.cache2.CleanEvict_mshr_misses::total 41439 # number of CleanEvict MSHR misses +system.l2subsys0.cache2.UpgradeReq_mshr_misses::l0subsys2.tester0 3731 # number of UpgradeReq MSHR misses +system.l2subsys0.cache2.UpgradeReq_mshr_misses::l0subsys2.tester1 3588 # number of UpgradeReq MSHR misses +system.l2subsys0.cache2.UpgradeReq_mshr_misses::l0subsys3.tester0 3374 # number of UpgradeReq MSHR misses +system.l2subsys0.cache2.UpgradeReq_mshr_misses::l0subsys3.tester1 3500 # number of UpgradeReq MSHR misses +system.l2subsys0.cache2.UpgradeReq_mshr_misses::total 14193 # number of UpgradeReq MSHR misses +system.l2subsys0.cache2.ReadExReq_mshr_misses::l0subsys2.tester0 16127 # number of ReadExReq MSHR misses +system.l2subsys0.cache2.ReadExReq_mshr_misses::l0subsys2.tester1 15998 # number of ReadExReq MSHR misses +system.l2subsys0.cache2.ReadExReq_mshr_misses::l0subsys3.tester0 16337 # number of ReadExReq MSHR misses +system.l2subsys0.cache2.ReadExReq_mshr_misses::l0subsys3.tester1 16371 # number of ReadExReq MSHR misses +system.l2subsys0.cache2.ReadExReq_mshr_misses::total 64833 # number of ReadExReq MSHR misses +system.l2subsys0.cache2.ReadSharedReq_mshr_misses::l0subsys2.tester0 28129 # number of ReadSharedReq MSHR misses +system.l2subsys0.cache2.ReadSharedReq_mshr_misses::l0subsys2.tester1 27875 # number of ReadSharedReq MSHR misses +system.l2subsys0.cache2.ReadSharedReq_mshr_misses::l0subsys3.tester0 28490 # number of ReadSharedReq MSHR misses +system.l2subsys0.cache2.ReadSharedReq_mshr_misses::l0subsys3.tester1 28046 # number of ReadSharedReq MSHR misses +system.l2subsys0.cache2.ReadSharedReq_mshr_misses::total 112540 # number of ReadSharedReq MSHR misses +system.l2subsys0.cache2.demand_mshr_misses::l0subsys2.tester0 44256 # number of demand (read+write) MSHR misses +system.l2subsys0.cache2.demand_mshr_misses::l0subsys2.tester1 43873 # number of demand (read+write) MSHR misses +system.l2subsys0.cache2.demand_mshr_misses::l0subsys3.tester0 44827 # number of demand (read+write) MSHR misses +system.l2subsys0.cache2.demand_mshr_misses::l0subsys3.tester1 44417 # number of demand (read+write) MSHR misses +system.l2subsys0.cache2.demand_mshr_misses::total 177373 # number of demand (read+write) MSHR misses +system.l2subsys0.cache2.overall_mshr_misses::l0subsys2.tester0 44256 # number of overall MSHR misses +system.l2subsys0.cache2.overall_mshr_misses::l0subsys2.tester1 43873 # number of overall MSHR misses +system.l2subsys0.cache2.overall_mshr_misses::l0subsys3.tester0 44827 # number of overall MSHR misses +system.l2subsys0.cache2.overall_mshr_misses::l0subsys3.tester1 44417 # number of overall MSHR misses +system.l2subsys0.cache2.overall_mshr_misses::total 177373 # number of overall MSHR misses +system.l2subsys0.cache2.UpgradeReq_mshr_miss_latency::l0subsys2.tester0 86821804 # number of UpgradeReq MSHR miss cycles +system.l2subsys0.cache2.UpgradeReq_mshr_miss_latency::l0subsys2.tester1 85216922 # number of UpgradeReq MSHR miss cycles +system.l2subsys0.cache2.UpgradeReq_mshr_miss_latency::l0subsys3.tester0 79514942 # number of UpgradeReq MSHR miss cycles +system.l2subsys0.cache2.UpgradeReq_mshr_miss_latency::l0subsys3.tester1 83404063 # number of UpgradeReq MSHR miss cycles +system.l2subsys0.cache2.UpgradeReq_mshr_miss_latency::total 334957731 # number of UpgradeReq MSHR miss cycles +system.l2subsys0.cache2.ReadExReq_mshr_miss_latency::l0subsys2.tester0 1390062688 # number of ReadExReq MSHR miss cycles +system.l2subsys0.cache2.ReadExReq_mshr_miss_latency::l0subsys2.tester1 1380024742 # number of ReadExReq MSHR miss cycles +system.l2subsys0.cache2.ReadExReq_mshr_miss_latency::l0subsys3.tester0 1423675349 # number of ReadExReq MSHR miss cycles +system.l2subsys0.cache2.ReadExReq_mshr_miss_latency::l0subsys3.tester1 1385907063 # number of ReadExReq MSHR miss cycles +system.l2subsys0.cache2.ReadExReq_mshr_miss_latency::total 5579669842 # number of ReadExReq MSHR miss cycles +system.l2subsys0.cache2.ReadSharedReq_mshr_miss_latency::l0subsys2.tester0 2433916719 # number of ReadSharedReq MSHR miss cycles +system.l2subsys0.cache2.ReadSharedReq_mshr_miss_latency::l0subsys2.tester1 2458901936 # number of ReadSharedReq MSHR miss cycles +system.l2subsys0.cache2.ReadSharedReq_mshr_miss_latency::l0subsys3.tester0 2472187719 # number of ReadSharedReq MSHR miss cycles +system.l2subsys0.cache2.ReadSharedReq_mshr_miss_latency::l0subsys3.tester1 2398872655 # number of ReadSharedReq MSHR miss cycles +system.l2subsys0.cache2.ReadSharedReq_mshr_miss_latency::total 9763879029 # number of ReadSharedReq MSHR miss cycles +system.l2subsys0.cache2.demand_mshr_miss_latency::l0subsys2.tester0 3823979407 # number of demand (read+write) MSHR miss cycles +system.l2subsys0.cache2.demand_mshr_miss_latency::l0subsys2.tester1 3838926678 # number of demand (read+write) MSHR miss cycles +system.l2subsys0.cache2.demand_mshr_miss_latency::l0subsys3.tester0 3895863068 # number of demand (read+write) MSHR miss cycles +system.l2subsys0.cache2.demand_mshr_miss_latency::l0subsys3.tester1 3784779718 # number of demand (read+write) MSHR miss cycles +system.l2subsys0.cache2.demand_mshr_miss_latency::total 15343548871 # number of demand (read+write) MSHR miss cycles +system.l2subsys0.cache2.overall_mshr_miss_latency::l0subsys2.tester0 3823979407 # number of overall MSHR miss cycles +system.l2subsys0.cache2.overall_mshr_miss_latency::l0subsys2.tester1 3838926678 # number of overall MSHR miss cycles +system.l2subsys0.cache2.overall_mshr_miss_latency::l0subsys3.tester0 3895863068 # number of overall MSHR miss cycles +system.l2subsys0.cache2.overall_mshr_miss_latency::l0subsys3.tester1 3784779718 # number of overall MSHR miss cycles +system.l2subsys0.cache2.overall_mshr_miss_latency::total 15343548871 # number of overall MSHR miss cycles system.l2subsys0.cache2.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.l2subsys0.cache2.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.l2subsys0.cache2.UpgradeReq_mshr_miss_rate::l0subsys2.tester0 1 # mshr miss rate for UpgradeReq accesses -system.l2subsys0.cache2.UpgradeReq_mshr_miss_rate::l0subsys2.tester1 1 # mshr miss rate for UpgradeReq accesses -system.l2subsys0.cache2.UpgradeReq_mshr_miss_rate::l0subsys3.tester0 1 # mshr miss rate for UpgradeReq accesses -system.l2subsys0.cache2.UpgradeReq_mshr_miss_rate::l0subsys3.tester1 1 # mshr miss rate for UpgradeReq accesses -system.l2subsys0.cache2.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses -system.l2subsys0.cache2.ReadExReq_mshr_miss_rate::l0subsys2.tester0 0.982840 # mshr miss rate for ReadExReq accesses -system.l2subsys0.cache2.ReadExReq_mshr_miss_rate::l0subsys2.tester1 0.978922 # mshr miss rate for ReadExReq accesses -system.l2subsys0.cache2.ReadExReq_mshr_miss_rate::l0subsys3.tester0 0.980957 # mshr miss rate for ReadExReq accesses -system.l2subsys0.cache2.ReadExReq_mshr_miss_rate::l0subsys3.tester1 0.978476 # mshr miss rate for ReadExReq accesses -system.l2subsys0.cache2.ReadExReq_mshr_miss_rate::total 0.980299 # mshr miss rate for ReadExReq accesses -system.l2subsys0.cache2.ReadSharedReq_mshr_miss_rate::l0subsys2.tester0 0.964852 # mshr miss rate for ReadSharedReq accesses -system.l2subsys0.cache2.ReadSharedReq_mshr_miss_rate::l0subsys2.tester1 0.958407 # mshr miss rate for ReadSharedReq accesses -system.l2subsys0.cache2.ReadSharedReq_mshr_miss_rate::l0subsys3.tester0 0.957832 # mshr miss rate for ReadSharedReq accesses -system.l2subsys0.cache2.ReadSharedReq_mshr_miss_rate::l0subsys3.tester1 0.958621 # mshr miss rate for ReadSharedReq accesses -system.l2subsys0.cache2.ReadSharedReq_mshr_miss_rate::total 0.959930 # mshr miss rate for ReadSharedReq accesses -system.l2subsys0.cache2.demand_mshr_miss_rate::l0subsys2.tester0 0.971212 # mshr miss rate for demand accesses -system.l2subsys0.cache2.demand_mshr_miss_rate::l0subsys2.tester1 0.965794 # mshr miss rate for demand accesses -system.l2subsys0.cache2.demand_mshr_miss_rate::l0subsys3.tester0 0.966165 # mshr miss rate for demand accesses -system.l2subsys0.cache2.demand_mshr_miss_rate::l0subsys3.tester1 0.965751 # mshr miss rate for demand accesses -system.l2subsys0.cache2.demand_mshr_miss_rate::total 0.967228 # mshr miss rate for demand accesses -system.l2subsys0.cache2.overall_mshr_miss_rate::l0subsys2.tester0 0.971212 # mshr miss rate for overall accesses -system.l2subsys0.cache2.overall_mshr_miss_rate::l0subsys2.tester1 0.965794 # mshr miss rate for overall accesses -system.l2subsys0.cache2.overall_mshr_miss_rate::l0subsys3.tester0 0.966165 # mshr miss rate for overall accesses -system.l2subsys0.cache2.overall_mshr_miss_rate::l0subsys3.tester1 0.965751 # mshr miss rate for overall accesses -system.l2subsys0.cache2.overall_mshr_miss_rate::total 0.967228 # mshr miss rate for overall accesses -system.l2subsys0.cache2.UpgradeReq_avg_mshr_miss_latency::l0subsys2.tester0 23211.622387 # average UpgradeReq mshr miss latency -system.l2subsys0.cache2.UpgradeReq_avg_mshr_miss_latency::l0subsys2.tester1 22977.964820 # average UpgradeReq mshr miss latency -system.l2subsys0.cache2.UpgradeReq_avg_mshr_miss_latency::l0subsys3.tester0 23287.446945 # average UpgradeReq mshr miss latency -system.l2subsys0.cache2.UpgradeReq_avg_mshr_miss_latency::l0subsys3.tester1 23165.139322 # average UpgradeReq mshr miss latency -system.l2subsys0.cache2.UpgradeReq_avg_mshr_miss_latency::total 23159.763865 # average UpgradeReq mshr miss latency -system.l2subsys0.cache2.ReadExReq_avg_mshr_miss_latency::l0subsys2.tester0 87846.640923 # average ReadExReq mshr miss latency -system.l2subsys0.cache2.ReadExReq_avg_mshr_miss_latency::l0subsys2.tester1 87943.529393 # average ReadExReq mshr miss latency -system.l2subsys0.cache2.ReadExReq_avg_mshr_miss_latency::l0subsys3.tester0 85841.446358 # average ReadExReq mshr miss latency -system.l2subsys0.cache2.ReadExReq_avg_mshr_miss_latency::l0subsys3.tester1 86702.050226 # average ReadExReq mshr miss latency -system.l2subsys0.cache2.ReadExReq_avg_mshr_miss_latency::total 87070.716055 # average ReadExReq mshr miss latency -system.l2subsys0.cache2.ReadSharedReq_avg_mshr_miss_latency::l0subsys2.tester0 87358.250204 # average ReadSharedReq mshr miss latency -system.l2subsys0.cache2.ReadSharedReq_avg_mshr_miss_latency::l0subsys2.tester1 87981.739432 # average ReadSharedReq mshr miss latency -system.l2subsys0.cache2.ReadSharedReq_avg_mshr_miss_latency::l0subsys3.tester0 87092.479743 # average ReadSharedReq mshr miss latency -system.l2subsys0.cache2.ReadSharedReq_avg_mshr_miss_latency::l0subsys3.tester1 86946.531510 # average ReadSharedReq mshr miss latency -system.l2subsys0.cache2.ReadSharedReq_avg_mshr_miss_latency::total 87342.948401 # average ReadSharedReq mshr miss latency -system.l2subsys0.cache2.demand_avg_mshr_miss_latency::l0subsys2.tester0 87533.003169 # average overall mshr miss latency -system.l2subsys0.cache2.demand_avg_mshr_miss_latency::l0subsys2.tester1 87967.795004 # average overall mshr miss latency -system.l2subsys0.cache2.demand_avg_mshr_miss_latency::l0subsys3.tester0 86634.785961 # average overall mshr miss latency -system.l2subsys0.cache2.demand_avg_mshr_miss_latency::l0subsys3.tester1 86857.574211 # average overall mshr miss latency -system.l2subsys0.cache2.demand_avg_mshr_miss_latency::total 87244.093661 # average overall mshr miss latency -system.l2subsys0.cache2.overall_avg_mshr_miss_latency::l0subsys2.tester0 87533.003169 # average overall mshr miss latency -system.l2subsys0.cache2.overall_avg_mshr_miss_latency::l0subsys2.tester1 87967.795004 # average overall mshr miss latency -system.l2subsys0.cache2.overall_avg_mshr_miss_latency::l0subsys3.tester0 86634.785961 # average overall mshr miss latency -system.l2subsys0.cache2.overall_avg_mshr_miss_latency::l0subsys3.tester1 86857.574211 # average overall mshr miss latency -system.l2subsys0.cache2.overall_avg_mshr_miss_latency::total 87244.093661 # average overall mshr miss latency +system.l2subsys0.cache2.UpgradeReq_mshr_miss_rate::l0subsys2.tester0 0.963834 # mshr miss rate for UpgradeReq accesses +system.l2subsys0.cache2.UpgradeReq_mshr_miss_rate::l0subsys2.tester1 0.960128 # mshr miss rate for UpgradeReq accesses +system.l2subsys0.cache2.UpgradeReq_mshr_miss_rate::l0subsys3.tester0 0.965655 # mshr miss rate for UpgradeReq accesses +system.l2subsys0.cache2.UpgradeReq_mshr_miss_rate::l0subsys3.tester1 0.950054 # mshr miss rate for UpgradeReq accesses +system.l2subsys0.cache2.UpgradeReq_mshr_miss_rate::total 0.959894 # mshr miss rate for UpgradeReq accesses +system.l2subsys0.cache2.ReadExReq_mshr_miss_rate::l0subsys2.tester0 0.975915 # mshr miss rate for ReadExReq accesses +system.l2subsys0.cache2.ReadExReq_mshr_miss_rate::l0subsys2.tester1 0.977813 # mshr miss rate for ReadExReq accesses +system.l2subsys0.cache2.ReadExReq_mshr_miss_rate::l0subsys3.tester0 0.977503 # mshr miss rate for ReadExReq accesses +system.l2subsys0.cache2.ReadExReq_mshr_miss_rate::l0subsys3.tester1 0.977607 # mshr miss rate for ReadExReq accesses +system.l2subsys0.cache2.ReadExReq_mshr_miss_rate::total 0.977210 # mshr miss rate for ReadExReq accesses +system.l2subsys0.cache2.ReadSharedReq_mshr_miss_rate::l0subsys2.tester0 0.958758 # mshr miss rate for ReadSharedReq accesses +system.l2subsys0.cache2.ReadSharedReq_mshr_miss_rate::l0subsys2.tester1 0.955147 # mshr miss rate for ReadSharedReq accesses +system.l2subsys0.cache2.ReadSharedReq_mshr_miss_rate::l0subsys3.tester0 0.957068 # mshr miss rate for ReadSharedReq accesses +system.l2subsys0.cache2.ReadSharedReq_mshr_miss_rate::l0subsys3.tester1 0.955310 # mshr miss rate for ReadSharedReq accesses +system.l2subsys0.cache2.ReadSharedReq_mshr_miss_rate::total 0.956574 # mshr miss rate for ReadSharedReq accesses +system.l2subsys0.cache2.demand_mshr_miss_rate::l0subsys2.tester0 0.964940 # mshr miss rate for demand accesses +system.l2subsys0.cache2.demand_mshr_miss_rate::l0subsys2.tester1 0.963289 # mshr miss rate for demand accesses +system.l2subsys0.cache2.demand_mshr_miss_rate::l0subsys3.tester0 0.964416 # mshr miss rate for demand accesses +system.l2subsys0.cache2.demand_mshr_miss_rate::l0subsys3.tester1 0.963409 # mshr miss rate for demand accesses +system.l2subsys0.cache2.demand_mshr_miss_rate::total 0.964015 # mshr miss rate for demand accesses +system.l2subsys0.cache2.overall_mshr_miss_rate::l0subsys2.tester0 0.964940 # mshr miss rate for overall accesses +system.l2subsys0.cache2.overall_mshr_miss_rate::l0subsys2.tester1 0.963289 # mshr miss rate for overall accesses +system.l2subsys0.cache2.overall_mshr_miss_rate::l0subsys3.tester0 0.964416 # mshr miss rate for overall accesses +system.l2subsys0.cache2.overall_mshr_miss_rate::l0subsys3.tester1 0.963409 # mshr miss rate for overall accesses +system.l2subsys0.cache2.overall_mshr_miss_rate::total 0.964015 # mshr miss rate for overall accesses +system.l2subsys0.cache2.UpgradeReq_avg_mshr_miss_latency::l0subsys2.tester0 23270.384347 # average UpgradeReq mshr miss latency +system.l2subsys0.cache2.UpgradeReq_avg_mshr_miss_latency::l0subsys2.tester1 23750.535674 # average UpgradeReq mshr miss latency +system.l2subsys0.cache2.UpgradeReq_avg_mshr_miss_latency::l0subsys3.tester0 23566.965619 # average UpgradeReq mshr miss latency +system.l2subsys0.cache2.UpgradeReq_avg_mshr_miss_latency::l0subsys3.tester1 23829.732286 # average UpgradeReq mshr miss latency +system.l2subsys0.cache2.UpgradeReq_avg_mshr_miss_latency::total 23600.206510 # average UpgradeReq mshr miss latency +system.l2subsys0.cache2.ReadExReq_avg_mshr_miss_latency::l0subsys2.tester0 86194.747194 # average ReadExReq mshr miss latency +system.l2subsys0.cache2.ReadExReq_avg_mshr_miss_latency::l0subsys2.tester1 86262.329166 # average ReadExReq mshr miss latency +system.l2subsys0.cache2.ReadExReq_avg_mshr_miss_latency::l0subsys3.tester0 87144.233886 # average ReadExReq mshr miss latency +system.l2subsys0.cache2.ReadExReq_avg_mshr_miss_latency::l0subsys3.tester1 84656.225215 # average ReadExReq mshr miss latency +system.l2subsys0.cache2.ReadExReq_avg_mshr_miss_latency::total 86062.188114 # average ReadExReq mshr miss latency +system.l2subsys0.cache2.ReadSharedReq_avg_mshr_miss_latency::l0subsys2.tester0 86526.955064 # average ReadSharedReq mshr miss latency +system.l2subsys0.cache2.ReadSharedReq_avg_mshr_miss_latency::l0subsys2.tester1 88211.728646 # average ReadSharedReq mshr miss latency +system.l2subsys0.cache2.ReadSharedReq_avg_mshr_miss_latency::l0subsys3.tester0 86773.875711 # average ReadSharedReq mshr miss latency +system.l2subsys0.cache2.ReadSharedReq_avg_mshr_miss_latency::l0subsys3.tester1 85533.504065 # average ReadSharedReq mshr miss latency +system.l2subsys0.cache2.ReadSharedReq_avg_mshr_miss_latency::total 86759.188102 # average ReadSharedReq mshr miss latency +system.l2subsys0.cache2.demand_avg_mshr_miss_latency::l0subsys2.tester0 86405.897664 # average overall mshr miss latency +system.l2subsys0.cache2.demand_avg_mshr_miss_latency::l0subsys2.tester1 87500.892987 # average overall mshr miss latency +system.l2subsys0.cache2.demand_avg_mshr_miss_latency::l0subsys3.tester0 86908.851094 # average overall mshr miss latency +system.l2subsys0.cache2.demand_avg_mshr_miss_latency::l0subsys3.tester1 85210.160929 # average overall mshr miss latency +system.l2subsys0.cache2.demand_avg_mshr_miss_latency::total 86504.422156 # average overall mshr miss latency +system.l2subsys0.cache2.overall_avg_mshr_miss_latency::l0subsys2.tester0 86405.897664 # average overall mshr miss latency +system.l2subsys0.cache2.overall_avg_mshr_miss_latency::l0subsys2.tester1 87500.892987 # average overall mshr miss latency +system.l2subsys0.cache2.overall_avg_mshr_miss_latency::l0subsys3.tester0 86908.851094 # average overall mshr miss latency +system.l2subsys0.cache2.overall_avg_mshr_miss_latency::l0subsys3.tester1 85210.160929 # average overall mshr miss latency +system.l2subsys0.cache2.overall_avg_mshr_miss_latency::total 86504.422156 # average overall mshr miss latency system.l2subsys0.cache3.tags.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states -system.l2subsys0.cache3.tags.replacements 130662 # number of replacements -system.l2subsys0.cache3.tags.tagsinuse 1489.946036 # Cycle average of tags in use -system.l2subsys0.cache3.tags.total_refs 67604 # Total number of references to valid blocks. -system.l2subsys0.cache3.tags.sampled_refs 132161 # Sample count of references to valid blocks. -system.l2subsys0.cache3.tags.avg_refs 0.511528 # Average number of references to valid blocks. -system.l2subsys0.cache3.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2subsys0.cache3.tags.occ_blocks::writebacks 425.979862 # Average occupied blocks per requestor -system.l2subsys0.cache3.tags.occ_blocks::l0subsys4.tester0 268.595502 # Average occupied blocks per requestor -system.l2subsys0.cache3.tags.occ_blocks::l0subsys4.tester1 251.873835 # Average occupied blocks per requestor -system.l2subsys0.cache3.tags.occ_blocks::l0subsys5.tester0 272.521788 # Average occupied blocks per requestor -system.l2subsys0.cache3.tags.occ_blocks::l0subsys5.tester1 270.975049 # Average occupied blocks per requestor -system.l2subsys0.cache3.tags.occ_percent::writebacks 0.277331 # Average percentage of cache occupancy -system.l2subsys0.cache3.tags.occ_percent::l0subsys4.tester0 0.174867 # Average percentage of cache occupancy -system.l2subsys0.cache3.tags.occ_percent::l0subsys4.tester1 0.163980 # Average percentage of cache occupancy -system.l2subsys0.cache3.tags.occ_percent::l0subsys5.tester0 0.177423 # Average percentage of cache occupancy -system.l2subsys0.cache3.tags.occ_percent::l0subsys5.tester1 0.176416 # Average percentage of cache occupancy -system.l2subsys0.cache3.tags.occ_percent::total 0.970017 # Average percentage of cache occupancy -system.l2subsys0.cache3.tags.occ_task_id_blocks::1024 1499 # Occupied blocks per task id -system.l2subsys0.cache3.tags.age_task_id_blocks_1024::0 200 # Occupied blocks per task id -system.l2subsys0.cache3.tags.age_task_id_blocks_1024::1 983 # Occupied blocks per task id -system.l2subsys0.cache3.tags.age_task_id_blocks_1024::2 316 # Occupied blocks per task id -system.l2subsys0.cache3.tags.occ_task_id_percent::1024 0.975911 # Percentage of cache occupancy per task id -system.l2subsys0.cache3.tags.tag_accesses 4225473 # Number of tag accesses -system.l2subsys0.cache3.tags.data_accesses 4225473 # Number of data accesses +system.l2subsys0.cache3.tags.replacements 154799 # number of replacements +system.l2subsys0.cache3.tags.tagsinuse 1523.428503 # Cycle average of tags in use +system.l2subsys0.cache3.tags.total_refs 83314 # Total number of references to valid blocks. +system.l2subsys0.cache3.tags.sampled_refs 156330 # Sample count of references to valid blocks. +system.l2subsys0.cache3.tags.avg_refs 0.532937 # Average number of references to valid blocks. +system.l2subsys0.cache3.tags.warmup_cycle 238966000 # Cycle when the warmup percentage was hit. +system.l2subsys0.cache3.tags.occ_blocks::writebacks 188.347514 # Average occupied blocks per requestor +system.l2subsys0.cache3.tags.occ_blocks::l0subsys4.tester0 343.217725 # Average occupied blocks per requestor +system.l2subsys0.cache3.tags.occ_blocks::l0subsys4.tester1 332.812126 # Average occupied blocks per requestor +system.l2subsys0.cache3.tags.occ_blocks::l0subsys5.tester0 334.052084 # Average occupied blocks per requestor +system.l2subsys0.cache3.tags.occ_blocks::l0subsys5.tester1 324.999055 # Average occupied blocks per requestor +system.l2subsys0.cache3.tags.occ_percent::writebacks 0.122622 # Average percentage of cache occupancy +system.l2subsys0.cache3.tags.occ_percent::l0subsys4.tester0 0.223449 # Average percentage of cache occupancy +system.l2subsys0.cache3.tags.occ_percent::l0subsys4.tester1 0.216675 # Average percentage of cache occupancy +system.l2subsys0.cache3.tags.occ_percent::l0subsys5.tester0 0.217482 # Average percentage of cache occupancy +system.l2subsys0.cache3.tags.occ_percent::l0subsys5.tester1 0.211588 # Average percentage of cache occupancy +system.l2subsys0.cache3.tags.occ_percent::total 0.991815 # Average percentage of cache occupancy +system.l2subsys0.cache3.tags.occ_task_id_blocks::1024 1531 # Occupied blocks per task id +system.l2subsys0.cache3.tags.age_task_id_blocks_1024::0 228 # Occupied blocks per task id +system.l2subsys0.cache3.tags.age_task_id_blocks_1024::1 1094 # Occupied blocks per task id +system.l2subsys0.cache3.tags.age_task_id_blocks_1024::2 209 # Occupied blocks per task id +system.l2subsys0.cache3.tags.occ_task_id_percent::1024 0.996745 # Percentage of cache occupancy per task id +system.l2subsys0.cache3.tags.tag_accesses 4224919 # Number of tag accesses +system.l2subsys0.cache3.tags.data_accesses 4224919 # Number of data accesses system.l2subsys0.cache3.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states -system.l2subsys0.cache3.WritebackDirty_hits::writebacks 47372 # number of WritebackDirty hits -system.l2subsys0.cache3.WritebackDirty_hits::total 47372 # number of WritebackDirty hits -system.l2subsys0.cache3.ReadExReq_hits::l0subsys4.tester0 45 # number of ReadExReq hits -system.l2subsys0.cache3.ReadExReq_hits::l0subsys4.tester1 48 # number of ReadExReq hits -system.l2subsys0.cache3.ReadExReq_hits::l0subsys5.tester0 51 # number of ReadExReq hits -system.l2subsys0.cache3.ReadExReq_hits::l0subsys5.tester1 43 # number of ReadExReq hits -system.l2subsys0.cache3.ReadExReq_hits::total 187 # number of ReadExReq hits -system.l2subsys0.cache3.ReadSharedReq_hits::l0subsys4.tester0 655 # number of ReadSharedReq hits -system.l2subsys0.cache3.ReadSharedReq_hits::l0subsys4.tester1 678 # number of ReadSharedReq hits -system.l2subsys0.cache3.ReadSharedReq_hits::l0subsys5.tester0 569 # number of ReadSharedReq hits -system.l2subsys0.cache3.ReadSharedReq_hits::l0subsys5.tester1 592 # number of ReadSharedReq hits -system.l2subsys0.cache3.ReadSharedReq_hits::total 2494 # number of ReadSharedReq hits -system.l2subsys0.cache3.demand_hits::l0subsys4.tester0 700 # number of demand (read+write) hits -system.l2subsys0.cache3.demand_hits::l0subsys4.tester1 726 # number of demand (read+write) hits -system.l2subsys0.cache3.demand_hits::l0subsys5.tester0 620 # number of demand (read+write) hits -system.l2subsys0.cache3.demand_hits::l0subsys5.tester1 635 # number of demand (read+write) hits -system.l2subsys0.cache3.demand_hits::total 2681 # number of demand (read+write) hits -system.l2subsys0.cache3.overall_hits::l0subsys4.tester0 700 # number of overall hits -system.l2subsys0.cache3.overall_hits::l0subsys4.tester1 726 # number of overall hits -system.l2subsys0.cache3.overall_hits::l0subsys5.tester0 620 # number of overall hits -system.l2subsys0.cache3.overall_hits::l0subsys5.tester1 635 # number of overall hits -system.l2subsys0.cache3.overall_hits::total 2681 # number of overall hits -system.l2subsys0.cache3.UpgradeReq_misses::l0subsys4.tester0 3869 # number of UpgradeReq misses -system.l2subsys0.cache3.UpgradeReq_misses::l0subsys4.tester1 3840 # number of UpgradeReq misses -system.l2subsys0.cache3.UpgradeReq_misses::l0subsys5.tester0 3845 # number of UpgradeReq misses -system.l2subsys0.cache3.UpgradeReq_misses::l0subsys5.tester1 3621 # number of UpgradeReq misses -system.l2subsys0.cache3.UpgradeReq_misses::total 15175 # number of UpgradeReq misses -system.l2subsys0.cache3.ReadExReq_misses::l0subsys4.tester0 16646 # number of ReadExReq misses -system.l2subsys0.cache3.ReadExReq_misses::l0subsys4.tester1 16118 # number of ReadExReq misses -system.l2subsys0.cache3.ReadExReq_misses::l0subsys5.tester0 16903 # number of ReadExReq misses -system.l2subsys0.cache3.ReadExReq_misses::l0subsys5.tester1 16518 # number of ReadExReq misses -system.l2subsys0.cache3.ReadExReq_misses::total 66185 # number of ReadExReq misses -system.l2subsys0.cache3.ReadSharedReq_misses::l0subsys4.tester0 28947 # number of ReadSharedReq misses -system.l2subsys0.cache3.ReadSharedReq_misses::l0subsys4.tester1 28300 # number of ReadSharedReq misses -system.l2subsys0.cache3.ReadSharedReq_misses::l0subsys5.tester0 30131 # number of ReadSharedReq misses -system.l2subsys0.cache3.ReadSharedReq_misses::l0subsys5.tester1 29474 # number of ReadSharedReq misses -system.l2subsys0.cache3.ReadSharedReq_misses::total 116852 # number of ReadSharedReq misses -system.l2subsys0.cache3.demand_misses::l0subsys4.tester0 45593 # number of demand (read+write) misses -system.l2subsys0.cache3.demand_misses::l0subsys4.tester1 44418 # number of demand (read+write) misses -system.l2subsys0.cache3.demand_misses::l0subsys5.tester0 47034 # number of demand (read+write) misses -system.l2subsys0.cache3.demand_misses::l0subsys5.tester1 45992 # number of demand (read+write) misses -system.l2subsys0.cache3.demand_misses::total 183037 # number of demand (read+write) misses -system.l2subsys0.cache3.overall_misses::l0subsys4.tester0 45593 # number of overall misses -system.l2subsys0.cache3.overall_misses::l0subsys4.tester1 44418 # number of overall misses -system.l2subsys0.cache3.overall_misses::l0subsys5.tester0 47034 # number of overall misses -system.l2subsys0.cache3.overall_misses::l0subsys5.tester1 45992 # number of overall misses -system.l2subsys0.cache3.overall_misses::total 183037 # number of overall misses -system.l2subsys0.cache3.UpgradeReq_miss_latency::l0subsys4.tester0 67607414 # number of UpgradeReq miss cycles -system.l2subsys0.cache3.UpgradeReq_miss_latency::l0subsys4.tester1 68853013 # number of UpgradeReq miss cycles -system.l2subsys0.cache3.UpgradeReq_miss_latency::l0subsys5.tester0 66475482 # number of UpgradeReq miss cycles -system.l2subsys0.cache3.UpgradeReq_miss_latency::l0subsys5.tester1 60231217 # number of UpgradeReq miss cycles -system.l2subsys0.cache3.UpgradeReq_miss_latency::total 263167126 # number of UpgradeReq miss cycles -system.l2subsys0.cache3.ReadExReq_miss_latency::l0subsys4.tester0 1638669668 # number of ReadExReq miss cycles -system.l2subsys0.cache3.ReadExReq_miss_latency::l0subsys4.tester1 1540778847 # number of ReadExReq miss cycles -system.l2subsys0.cache3.ReadExReq_miss_latency::l0subsys5.tester0 1613231527 # number of ReadExReq miss cycles -system.l2subsys0.cache3.ReadExReq_miss_latency::l0subsys5.tester1 1593631051 # number of ReadExReq miss cycles -system.l2subsys0.cache3.ReadExReq_miss_latency::total 6386311093 # number of ReadExReq miss cycles -system.l2subsys0.cache3.ReadSharedReq_miss_latency::l0subsys4.tester0 2855133335 # number of ReadSharedReq miss cycles -system.l2subsys0.cache3.ReadSharedReq_miss_latency::l0subsys4.tester1 2727374504 # number of ReadSharedReq miss cycles -system.l2subsys0.cache3.ReadSharedReq_miss_latency::l0subsys5.tester0 2876692746 # number of ReadSharedReq miss cycles -system.l2subsys0.cache3.ReadSharedReq_miss_latency::l0subsys5.tester1 2842735649 # number of ReadSharedReq miss cycles -system.l2subsys0.cache3.ReadSharedReq_miss_latency::total 11301936234 # number of ReadSharedReq miss cycles -system.l2subsys0.cache3.demand_miss_latency::l0subsys4.tester0 4493803003 # number of demand (read+write) miss cycles -system.l2subsys0.cache3.demand_miss_latency::l0subsys4.tester1 4268153351 # number of demand (read+write) miss cycles -system.l2subsys0.cache3.demand_miss_latency::l0subsys5.tester0 4489924273 # number of demand (read+write) miss cycles -system.l2subsys0.cache3.demand_miss_latency::l0subsys5.tester1 4436366700 # number of demand (read+write) miss cycles -system.l2subsys0.cache3.demand_miss_latency::total 17688247327 # number of demand (read+write) miss cycles -system.l2subsys0.cache3.overall_miss_latency::l0subsys4.tester0 4493803003 # number of overall miss cycles -system.l2subsys0.cache3.overall_miss_latency::l0subsys4.tester1 4268153351 # number of overall miss cycles -system.l2subsys0.cache3.overall_miss_latency::l0subsys5.tester0 4489924273 # number of overall miss cycles -system.l2subsys0.cache3.overall_miss_latency::l0subsys5.tester1 4436366700 # number of overall miss cycles -system.l2subsys0.cache3.overall_miss_latency::total 17688247327 # number of overall miss cycles -system.l2subsys0.cache3.WritebackDirty_accesses::writebacks 47372 # number of WritebackDirty accesses(hits+misses) -system.l2subsys0.cache3.WritebackDirty_accesses::total 47372 # number of WritebackDirty accesses(hits+misses) -system.l2subsys0.cache3.UpgradeReq_accesses::l0subsys4.tester0 3869 # number of UpgradeReq accesses(hits+misses) -system.l2subsys0.cache3.UpgradeReq_accesses::l0subsys4.tester1 3840 # number of UpgradeReq accesses(hits+misses) -system.l2subsys0.cache3.UpgradeReq_accesses::l0subsys5.tester0 3845 # number of UpgradeReq accesses(hits+misses) -system.l2subsys0.cache3.UpgradeReq_accesses::l0subsys5.tester1 3621 # number of UpgradeReq accesses(hits+misses) -system.l2subsys0.cache3.UpgradeReq_accesses::total 15175 # number of UpgradeReq accesses(hits+misses) -system.l2subsys0.cache3.ReadExReq_accesses::l0subsys4.tester0 16691 # number of ReadExReq accesses(hits+misses) -system.l2subsys0.cache3.ReadExReq_accesses::l0subsys4.tester1 16166 # number of ReadExReq accesses(hits+misses) -system.l2subsys0.cache3.ReadExReq_accesses::l0subsys5.tester0 16954 # number of ReadExReq accesses(hits+misses) -system.l2subsys0.cache3.ReadExReq_accesses::l0subsys5.tester1 16561 # number of ReadExReq accesses(hits+misses) -system.l2subsys0.cache3.ReadExReq_accesses::total 66372 # number of ReadExReq accesses(hits+misses) -system.l2subsys0.cache3.ReadSharedReq_accesses::l0subsys4.tester0 29602 # number of ReadSharedReq accesses(hits+misses) -system.l2subsys0.cache3.ReadSharedReq_accesses::l0subsys4.tester1 28978 # number of ReadSharedReq accesses(hits+misses) -system.l2subsys0.cache3.ReadSharedReq_accesses::l0subsys5.tester0 30700 # number of ReadSharedReq accesses(hits+misses) -system.l2subsys0.cache3.ReadSharedReq_accesses::l0subsys5.tester1 30066 # number of ReadSharedReq accesses(hits+misses) -system.l2subsys0.cache3.ReadSharedReq_accesses::total 119346 # number of ReadSharedReq accesses(hits+misses) -system.l2subsys0.cache3.demand_accesses::l0subsys4.tester0 46293 # number of demand (read+write) accesses -system.l2subsys0.cache3.demand_accesses::l0subsys4.tester1 45144 # number of demand (read+write) accesses -system.l2subsys0.cache3.demand_accesses::l0subsys5.tester0 47654 # number of demand (read+write) accesses -system.l2subsys0.cache3.demand_accesses::l0subsys5.tester1 46627 # number of demand (read+write) accesses -system.l2subsys0.cache3.demand_accesses::total 185718 # number of demand (read+write) accesses -system.l2subsys0.cache3.overall_accesses::l0subsys4.tester0 46293 # number of overall (read+write) accesses -system.l2subsys0.cache3.overall_accesses::l0subsys4.tester1 45144 # number of overall (read+write) accesses -system.l2subsys0.cache3.overall_accesses::l0subsys5.tester0 47654 # number of overall (read+write) accesses -system.l2subsys0.cache3.overall_accesses::l0subsys5.tester1 46627 # number of overall (read+write) accesses -system.l2subsys0.cache3.overall_accesses::total 185718 # number of overall (read+write) accesses -system.l2subsys0.cache3.UpgradeReq_miss_rate::l0subsys4.tester0 1 # miss rate for UpgradeReq accesses -system.l2subsys0.cache3.UpgradeReq_miss_rate::l0subsys4.tester1 1 # miss rate for UpgradeReq accesses -system.l2subsys0.cache3.UpgradeReq_miss_rate::l0subsys5.tester0 1 # miss rate for UpgradeReq accesses -system.l2subsys0.cache3.UpgradeReq_miss_rate::l0subsys5.tester1 1 # miss rate for UpgradeReq accesses -system.l2subsys0.cache3.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses -system.l2subsys0.cache3.ReadExReq_miss_rate::l0subsys4.tester0 0.997304 # miss rate for ReadExReq accesses -system.l2subsys0.cache3.ReadExReq_miss_rate::l0subsys4.tester1 0.997031 # miss rate for ReadExReq accesses -system.l2subsys0.cache3.ReadExReq_miss_rate::l0subsys5.tester0 0.996992 # miss rate for ReadExReq accesses -system.l2subsys0.cache3.ReadExReq_miss_rate::l0subsys5.tester1 0.997404 # miss rate for ReadExReq accesses -system.l2subsys0.cache3.ReadExReq_miss_rate::total 0.997183 # miss rate for ReadExReq accesses -system.l2subsys0.cache3.ReadSharedReq_miss_rate::l0subsys4.tester0 0.977873 # miss rate for ReadSharedReq accesses -system.l2subsys0.cache3.ReadSharedReq_miss_rate::l0subsys4.tester1 0.976603 # miss rate for ReadSharedReq accesses -system.l2subsys0.cache3.ReadSharedReq_miss_rate::l0subsys5.tester0 0.981466 # miss rate for ReadSharedReq accesses -system.l2subsys0.cache3.ReadSharedReq_miss_rate::l0subsys5.tester1 0.980310 # miss rate for ReadSharedReq accesses -system.l2subsys0.cache3.ReadSharedReq_miss_rate::total 0.979103 # miss rate for ReadSharedReq accesses -system.l2subsys0.cache3.demand_miss_rate::l0subsys4.tester0 0.984879 # miss rate for demand accesses -system.l2subsys0.cache3.demand_miss_rate::l0subsys4.tester1 0.983918 # miss rate for demand accesses -system.l2subsys0.cache3.demand_miss_rate::l0subsys5.tester0 0.986990 # miss rate for demand accesses -system.l2subsys0.cache3.demand_miss_rate::l0subsys5.tester1 0.986381 # miss rate for demand accesses -system.l2subsys0.cache3.demand_miss_rate::total 0.985564 # miss rate for demand accesses -system.l2subsys0.cache3.overall_miss_rate::l0subsys4.tester0 0.984879 # miss rate for overall accesses -system.l2subsys0.cache3.overall_miss_rate::l0subsys4.tester1 0.983918 # miss rate for overall accesses -system.l2subsys0.cache3.overall_miss_rate::l0subsys5.tester0 0.986990 # miss rate for overall accesses -system.l2subsys0.cache3.overall_miss_rate::l0subsys5.tester1 0.986381 # miss rate for overall accesses -system.l2subsys0.cache3.overall_miss_rate::total 0.985564 # miss rate for overall accesses -system.l2subsys0.cache3.UpgradeReq_avg_miss_latency::l0subsys4.tester0 17474.131300 # average UpgradeReq miss latency -system.l2subsys0.cache3.UpgradeReq_avg_miss_latency::l0subsys4.tester1 17930.472135 # average UpgradeReq miss latency -system.l2subsys0.cache3.UpgradeReq_avg_miss_latency::l0subsys5.tester0 17288.811964 # average UpgradeReq miss latency -system.l2subsys0.cache3.UpgradeReq_avg_miss_latency::l0subsys5.tester1 16633.862745 # average UpgradeReq miss latency -system.l2subsys0.cache3.UpgradeReq_avg_miss_latency::total 17342.149984 # average UpgradeReq miss latency -system.l2subsys0.cache3.ReadExReq_avg_miss_latency::l0subsys4.tester0 98442.248468 # average ReadExReq miss latency -system.l2subsys0.cache3.ReadExReq_avg_miss_latency::l0subsys4.tester1 95593.674587 # average ReadExReq miss latency -system.l2subsys0.cache3.ReadExReq_avg_miss_latency::l0subsys5.tester0 95440.544696 # average ReadExReq miss latency -system.l2subsys0.cache3.ReadExReq_avg_miss_latency::l0subsys5.tester1 96478.450842 # average ReadExReq miss latency -system.l2subsys0.cache3.ReadExReq_avg_miss_latency::total 96491.819793 # average ReadExReq miss latency -system.l2subsys0.cache3.ReadSharedReq_avg_miss_latency::l0subsys4.tester0 98633.134176 # average ReadSharedReq miss latency -system.l2subsys0.cache3.ReadSharedReq_avg_miss_latency::l0subsys4.tester1 96373.657385 # average ReadSharedReq miss latency -system.l2subsys0.cache3.ReadSharedReq_avg_miss_latency::l0subsys5.tester0 95472.860044 # average ReadSharedReq miss latency -system.l2subsys0.cache3.ReadSharedReq_avg_miss_latency::l0subsys5.tester1 96448.926138 # average ReadSharedReq miss latency -system.l2subsys0.cache3.ReadSharedReq_avg_miss_latency::total 96720.092373 # average ReadSharedReq miss latency -system.l2subsys0.cache3.demand_avg_miss_latency::l0subsys4.tester0 98563.441822 # average overall miss latency -system.l2subsys0.cache3.demand_avg_miss_latency::l0subsys4.tester1 96090.624319 # average overall miss latency -system.l2subsys0.cache3.demand_avg_miss_latency::l0subsys5.tester0 95461.246609 # average overall miss latency -system.l2subsys0.cache3.demand_avg_miss_latency::l0subsys5.tester1 96459.529918 # average overall miss latency -system.l2subsys0.cache3.demand_avg_miss_latency::total 96637.550479 # average overall miss latency -system.l2subsys0.cache3.overall_avg_miss_latency::l0subsys4.tester0 98563.441822 # average overall miss latency -system.l2subsys0.cache3.overall_avg_miss_latency::l0subsys4.tester1 96090.624319 # average overall miss latency -system.l2subsys0.cache3.overall_avg_miss_latency::l0subsys5.tester0 95461.246609 # average overall miss latency -system.l2subsys0.cache3.overall_avg_miss_latency::l0subsys5.tester1 96459.529918 # average overall miss latency -system.l2subsys0.cache3.overall_avg_miss_latency::total 96637.550479 # average overall miss latency +system.l2subsys0.cache3.WritebackDirty_hits::writebacks 46868 # number of WritebackDirty hits +system.l2subsys0.cache3.WritebackDirty_hits::total 46868 # number of WritebackDirty hits +system.l2subsys0.cache3.UpgradeReq_hits::l0subsys4.tester0 165 # number of UpgradeReq hits +system.l2subsys0.cache3.UpgradeReq_hits::l0subsys4.tester1 191 # number of UpgradeReq hits +system.l2subsys0.cache3.UpgradeReq_hits::l0subsys5.tester0 147 # number of UpgradeReq hits +system.l2subsys0.cache3.UpgradeReq_hits::l0subsys5.tester1 196 # number of UpgradeReq hits +system.l2subsys0.cache3.UpgradeReq_hits::total 699 # number of UpgradeReq hits +system.l2subsys0.cache3.ReadExReq_hits::l0subsys4.tester0 40 # number of ReadExReq hits +system.l2subsys0.cache3.ReadExReq_hits::l0subsys4.tester1 33 # number of ReadExReq hits +system.l2subsys0.cache3.ReadExReq_hits::l0subsys5.tester0 37 # number of ReadExReq hits +system.l2subsys0.cache3.ReadExReq_hits::l0subsys5.tester1 40 # number of ReadExReq hits +system.l2subsys0.cache3.ReadExReq_hits::total 150 # number of ReadExReq hits +system.l2subsys0.cache3.ReadSharedReq_hits::l0subsys4.tester0 559 # number of ReadSharedReq hits +system.l2subsys0.cache3.ReadSharedReq_hits::l0subsys4.tester1 814 # number of ReadSharedReq hits +system.l2subsys0.cache3.ReadSharedReq_hits::l0subsys5.tester0 645 # number of ReadSharedReq hits +system.l2subsys0.cache3.ReadSharedReq_hits::l0subsys5.tester1 658 # number of ReadSharedReq hits +system.l2subsys0.cache3.ReadSharedReq_hits::total 2676 # number of ReadSharedReq hits +system.l2subsys0.cache3.demand_hits::l0subsys4.tester0 599 # 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number of UpgradeReq misses +system.l2subsys0.cache3.UpgradeReq_misses::l0subsys5.tester1 3509 # number of UpgradeReq misses +system.l2subsys0.cache3.UpgradeReq_misses::total 13774 # number of UpgradeReq misses +system.l2subsys0.cache3.ReadExReq_misses::l0subsys4.tester0 16336 # number of ReadExReq misses +system.l2subsys0.cache3.ReadExReq_misses::l0subsys4.tester1 17077 # number of ReadExReq misses +system.l2subsys0.cache3.ReadExReq_misses::l0subsys5.tester0 17011 # number of ReadExReq misses +system.l2subsys0.cache3.ReadExReq_misses::l0subsys5.tester1 16732 # number of ReadExReq misses +system.l2subsys0.cache3.ReadExReq_misses::total 67156 # number of ReadExReq misses +system.l2subsys0.cache3.ReadSharedReq_misses::l0subsys4.tester0 29044 # number of ReadSharedReq misses +system.l2subsys0.cache3.ReadSharedReq_misses::l0subsys4.tester1 29836 # number of ReadSharedReq misses +system.l2subsys0.cache3.ReadSharedReq_misses::l0subsys5.tester0 30115 # number of ReadSharedReq misses +system.l2subsys0.cache3.ReadSharedReq_misses::l0subsys5.tester1 29435 # number of ReadSharedReq misses +system.l2subsys0.cache3.ReadSharedReq_misses::total 118430 # number of ReadSharedReq misses +system.l2subsys0.cache3.demand_misses::l0subsys4.tester0 45380 # number of demand (read+write) misses +system.l2subsys0.cache3.demand_misses::l0subsys4.tester1 46913 # number of demand (read+write) misses +system.l2subsys0.cache3.demand_misses::l0subsys5.tester0 47126 # number of demand (read+write) misses +system.l2subsys0.cache3.demand_misses::l0subsys5.tester1 46167 # number of demand (read+write) misses +system.l2subsys0.cache3.demand_misses::total 185586 # number of demand (read+write) misses +system.l2subsys0.cache3.overall_misses::l0subsys4.tester0 45380 # number of overall misses +system.l2subsys0.cache3.overall_misses::l0subsys4.tester1 46913 # number of overall misses +system.l2subsys0.cache3.overall_misses::l0subsys5.tester0 47126 # number of overall misses +system.l2subsys0.cache3.overall_misses::l0subsys5.tester1 46167 # number of overall misses +system.l2subsys0.cache3.overall_misses::total 185586 # number of overall misses +system.l2subsys0.cache3.UpgradeReq_miss_latency::l0subsys4.tester0 113966013 # number of UpgradeReq miss cycles +system.l2subsys0.cache3.UpgradeReq_miss_latency::l0subsys4.tester1 112016969 # number of UpgradeReq miss cycles +system.l2subsys0.cache3.UpgradeReq_miss_latency::l0subsys5.tester0 112091322 # number of UpgradeReq miss cycles +system.l2subsys0.cache3.UpgradeReq_miss_latency::l0subsys5.tester1 114062531 # number of UpgradeReq miss cycles +system.l2subsys0.cache3.UpgradeReq_miss_latency::total 452136835 # number of UpgradeReq miss cycles +system.l2subsys0.cache3.ReadExReq_miss_latency::l0subsys4.tester0 1573749171 # number of ReadExReq miss cycles +system.l2subsys0.cache3.ReadExReq_miss_latency::l0subsys4.tester1 1609992551 # number of ReadExReq miss cycles +system.l2subsys0.cache3.ReadExReq_miss_latency::l0subsys5.tester0 1612917211 # number of ReadExReq miss cycles +system.l2subsys0.cache3.ReadExReq_miss_latency::l0subsys5.tester1 1594343846 # number of ReadExReq miss cycles +system.l2subsys0.cache3.ReadExReq_miss_latency::total 6391002779 # number of ReadExReq miss cycles +system.l2subsys0.cache3.ReadSharedReq_miss_latency::l0subsys4.tester0 2825020785 # number of ReadSharedReq miss cycles +system.l2subsys0.cache3.ReadSharedReq_miss_latency::l0subsys4.tester1 2832936908 # number of ReadSharedReq miss cycles +system.l2subsys0.cache3.ReadSharedReq_miss_latency::l0subsys5.tester0 2869238005 # number of ReadSharedReq miss cycles +system.l2subsys0.cache3.ReadSharedReq_miss_latency::l0subsys5.tester1 2817936974 # number of ReadSharedReq miss cycles +system.l2subsys0.cache3.ReadSharedReq_miss_latency::total 11345132672 # number of ReadSharedReq miss cycles +system.l2subsys0.cache3.demand_miss_latency::l0subsys4.tester0 4398769956 # number of demand (read+write) miss cycles +system.l2subsys0.cache3.demand_miss_latency::l0subsys4.tester1 4442929459 # number of demand (read+write) miss cycles +system.l2subsys0.cache3.demand_miss_latency::l0subsys5.tester0 4482155216 # number of demand (read+write) miss cycles +system.l2subsys0.cache3.demand_miss_latency::l0subsys5.tester1 4412280820 # number of demand (read+write) miss cycles +system.l2subsys0.cache3.demand_miss_latency::total 17736135451 # number of demand (read+write) miss cycles +system.l2subsys0.cache3.overall_miss_latency::l0subsys4.tester0 4398769956 # number of overall miss cycles +system.l2subsys0.cache3.overall_miss_latency::l0subsys4.tester1 4442929459 # number of overall miss cycles +system.l2subsys0.cache3.overall_miss_latency::l0subsys5.tester0 4482155216 # number of overall miss cycles +system.l2subsys0.cache3.overall_miss_latency::l0subsys5.tester1 4412280820 # number of overall miss cycles +system.l2subsys0.cache3.overall_miss_latency::total 17736135451 # number of overall miss cycles +system.l2subsys0.cache3.WritebackDirty_accesses::writebacks 46868 # number of WritebackDirty accesses(hits+misses) +system.l2subsys0.cache3.WritebackDirty_accesses::total 46868 # number of WritebackDirty accesses(hits+misses) +system.l2subsys0.cache3.UpgradeReq_accesses::l0subsys4.tester0 3560 # number of UpgradeReq accesses(hits+misses) +system.l2subsys0.cache3.UpgradeReq_accesses::l0subsys4.tester1 3612 # number of UpgradeReq accesses(hits+misses) +system.l2subsys0.cache3.UpgradeReq_accesses::l0subsys5.tester0 3596 # number of UpgradeReq accesses(hits+misses) +system.l2subsys0.cache3.UpgradeReq_accesses::l0subsys5.tester1 3705 # number of UpgradeReq accesses(hits+misses) +system.l2subsys0.cache3.UpgradeReq_accesses::total 14473 # number of UpgradeReq accesses(hits+misses) +system.l2subsys0.cache3.ReadExReq_accesses::l0subsys4.tester0 16376 # number of ReadExReq accesses(hits+misses) +system.l2subsys0.cache3.ReadExReq_accesses::l0subsys4.tester1 17110 # number of ReadExReq accesses(hits+misses) +system.l2subsys0.cache3.ReadExReq_accesses::l0subsys5.tester0 17048 # number of ReadExReq accesses(hits+misses) +system.l2subsys0.cache3.ReadExReq_accesses::l0subsys5.tester1 16772 # number of ReadExReq accesses(hits+misses) +system.l2subsys0.cache3.ReadExReq_accesses::total 67306 # number of ReadExReq accesses(hits+misses) +system.l2subsys0.cache3.ReadSharedReq_accesses::l0subsys4.tester0 29603 # number of ReadSharedReq accesses(hits+misses) +system.l2subsys0.cache3.ReadSharedReq_accesses::l0subsys4.tester1 30650 # number of ReadSharedReq accesses(hits+misses) +system.l2subsys0.cache3.ReadSharedReq_accesses::l0subsys5.tester0 30760 # number of ReadSharedReq accesses(hits+misses) +system.l2subsys0.cache3.ReadSharedReq_accesses::l0subsys5.tester1 30093 # number of ReadSharedReq accesses(hits+misses) +system.l2subsys0.cache3.ReadSharedReq_accesses::total 121106 # number of ReadSharedReq accesses(hits+misses) +system.l2subsys0.cache3.demand_accesses::l0subsys4.tester0 45979 # number of demand (read+write) accesses +system.l2subsys0.cache3.demand_accesses::l0subsys4.tester1 47760 # number of demand (read+write) accesses +system.l2subsys0.cache3.demand_accesses::l0subsys5.tester0 47808 # number of demand (read+write) accesses +system.l2subsys0.cache3.demand_accesses::l0subsys5.tester1 46865 # number of demand (read+write) accesses +system.l2subsys0.cache3.demand_accesses::total 188412 # number of demand (read+write) accesses +system.l2subsys0.cache3.overall_accesses::l0subsys4.tester0 45979 # number of overall (read+write) accesses +system.l2subsys0.cache3.overall_accesses::l0subsys4.tester1 47760 # number of overall (read+write) accesses +system.l2subsys0.cache3.overall_accesses::l0subsys5.tester0 47808 # number of overall (read+write) accesses +system.l2subsys0.cache3.overall_accesses::l0subsys5.tester1 46865 # number of overall (read+write) accesses +system.l2subsys0.cache3.overall_accesses::total 188412 # number of overall (read+write) accesses +system.l2subsys0.cache3.UpgradeReq_miss_rate::l0subsys4.tester0 0.953652 # miss rate for UpgradeReq accesses +system.l2subsys0.cache3.UpgradeReq_miss_rate::l0subsys4.tester1 0.947121 # miss rate for UpgradeReq accesses +system.l2subsys0.cache3.UpgradeReq_miss_rate::l0subsys5.tester0 0.959121 # miss rate for UpgradeReq accesses +system.l2subsys0.cache3.UpgradeReq_miss_rate::l0subsys5.tester1 0.947099 # miss rate for UpgradeReq accesses +system.l2subsys0.cache3.UpgradeReq_miss_rate::total 0.951703 # miss rate for UpgradeReq accesses +system.l2subsys0.cache3.ReadExReq_miss_rate::l0subsys4.tester0 0.997557 # miss rate for ReadExReq accesses +system.l2subsys0.cache3.ReadExReq_miss_rate::l0subsys4.tester1 0.998071 # miss rate for ReadExReq accesses +system.l2subsys0.cache3.ReadExReq_miss_rate::l0subsys5.tester0 0.997830 # miss rate for ReadExReq accesses +system.l2subsys0.cache3.ReadExReq_miss_rate::l0subsys5.tester1 0.997615 # miss rate for ReadExReq accesses +system.l2subsys0.cache3.ReadExReq_miss_rate::total 0.997771 # miss rate for ReadExReq accesses +system.l2subsys0.cache3.ReadSharedReq_miss_rate::l0subsys4.tester0 0.981117 # miss rate for ReadSharedReq accesses +system.l2subsys0.cache3.ReadSharedReq_miss_rate::l0subsys4.tester1 0.973442 # miss rate for ReadSharedReq accesses +system.l2subsys0.cache3.ReadSharedReq_miss_rate::l0subsys5.tester0 0.979031 # miss rate for ReadSharedReq accesses +system.l2subsys0.cache3.ReadSharedReq_miss_rate::l0subsys5.tester1 0.978134 # miss rate for ReadSharedReq accesses +system.l2subsys0.cache3.ReadSharedReq_miss_rate::total 0.977904 # miss rate for ReadSharedReq accesses +system.l2subsys0.cache3.demand_miss_rate::l0subsys4.tester0 0.986972 # miss rate for demand accesses +system.l2subsys0.cache3.demand_miss_rate::l0subsys4.tester1 0.982265 # miss rate for demand accesses +system.l2subsys0.cache3.demand_miss_rate::l0subsys5.tester0 0.985735 # miss rate for demand accesses +system.l2subsys0.cache3.demand_miss_rate::l0subsys5.tester1 0.985106 # miss rate for demand accesses +system.l2subsys0.cache3.demand_miss_rate::total 0.985001 # miss rate for demand accesses +system.l2subsys0.cache3.overall_miss_rate::l0subsys4.tester0 0.986972 # miss rate for overall accesses +system.l2subsys0.cache3.overall_miss_rate::l0subsys4.tester1 0.982265 # miss rate for overall accesses +system.l2subsys0.cache3.overall_miss_rate::l0subsys5.tester0 0.985735 # miss rate for overall accesses +system.l2subsys0.cache3.overall_miss_rate::l0subsys5.tester1 0.985106 # miss rate for overall accesses +system.l2subsys0.cache3.overall_miss_rate::total 0.985001 # miss rate for overall accesses +system.l2subsys0.cache3.UpgradeReq_avg_miss_latency::l0subsys4.tester0 33568.781443 # average UpgradeReq miss latency +system.l2subsys0.cache3.UpgradeReq_avg_miss_latency::l0subsys4.tester1 32743.925460 # average UpgradeReq miss latency +system.l2subsys0.cache3.UpgradeReq_avg_miss_latency::l0subsys5.tester0 32499.658452 # average UpgradeReq miss latency +system.l2subsys0.cache3.UpgradeReq_avg_miss_latency::l0subsys5.tester1 32505.708464 # average UpgradeReq miss latency +system.l2subsys0.cache3.UpgradeReq_avg_miss_latency::total 32825.383694 # average UpgradeReq miss latency +system.l2subsys0.cache3.ReadExReq_avg_miss_latency::l0subsys4.tester0 96336.261692 # average ReadExReq miss latency +system.l2subsys0.cache3.ReadExReq_avg_miss_latency::l0subsys4.tester1 94278.418399 # average ReadExReq miss latency +system.l2subsys0.cache3.ReadExReq_avg_miss_latency::l0subsys5.tester0 94816.131386 # average ReadExReq miss latency +system.l2subsys0.cache3.ReadExReq_avg_miss_latency::l0subsys5.tester1 95287.105307 # average ReadExReq miss latency +system.l2subsys0.cache3.ReadExReq_avg_miss_latency::total 95166.519432 # average ReadExReq miss latency +system.l2subsys0.cache3.ReadSharedReq_avg_miss_latency::l0subsys4.tester0 97266.932413 # average ReadSharedReq miss latency +system.l2subsys0.cache3.ReadSharedReq_avg_miss_latency::l0subsys4.tester1 94950.291862 # average ReadSharedReq miss latency +system.l2subsys0.cache3.ReadSharedReq_avg_miss_latency::l0subsys5.tester0 95276.042006 # average ReadSharedReq miss latency +system.l2subsys0.cache3.ReadSharedReq_avg_miss_latency::l0subsys5.tester1 95734.227077 # average ReadSharedReq miss latency +system.l2subsys0.cache3.ReadSharedReq_avg_miss_latency::total 95796.104636 # average ReadSharedReq miss latency +system.l2subsys0.cache3.demand_avg_miss_latency::l0subsys4.tester0 96931.907360 # average overall miss latency +system.l2subsys0.cache3.demand_avg_miss_latency::l0subsys4.tester1 94705.720355 # average overall miss latency +system.l2subsys0.cache3.demand_avg_miss_latency::l0subsys5.tester0 95110.028774 # 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number of cycles access was blocked system.l2subsys0.cache3.blocked::no_targets 0 # number of cycles access was blocked system.l2subsys0.cache3.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.l2subsys0.cache3.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.l2subsys0.cache3.writebacks::writebacks 46539 # number of writebacks -system.l2subsys0.cache3.writebacks::total 46539 # number of writebacks -system.l2subsys0.cache3.ReadExReq_mshr_hits::l0subsys4.tester0 245 # number of ReadExReq MSHR hits -system.l2subsys0.cache3.ReadExReq_mshr_hits::l0subsys4.tester1 276 # number of ReadExReq MSHR hits -system.l2subsys0.cache3.ReadExReq_mshr_hits::l0subsys5.tester0 228 # number of ReadExReq MSHR hits -system.l2subsys0.cache3.ReadExReq_mshr_hits::l0subsys5.tester1 276 # number of ReadExReq MSHR hits -system.l2subsys0.cache3.ReadExReq_mshr_hits::total 1025 # number of ReadExReq MSHR hits -system.l2subsys0.cache3.ReadSharedReq_mshr_hits::l0subsys4.tester0 453 # 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number of writebacks +system.l2subsys0.cache3.ReadExReq_mshr_hits::l0subsys4.tester0 265 # number of ReadExReq MSHR hits +system.l2subsys0.cache3.ReadExReq_mshr_hits::l0subsys4.tester1 407 # number of ReadExReq MSHR hits +system.l2subsys0.cache3.ReadExReq_mshr_hits::l0subsys5.tester0 288 # number of ReadExReq MSHR hits +system.l2subsys0.cache3.ReadExReq_mshr_hits::l0subsys5.tester1 291 # number of ReadExReq MSHR hits +system.l2subsys0.cache3.ReadExReq_mshr_hits::total 1251 # number of ReadExReq MSHR hits +system.l2subsys0.cache3.ReadSharedReq_mshr_hits::l0subsys4.tester0 482 # number of ReadSharedReq MSHR hits +system.l2subsys0.cache3.ReadSharedReq_mshr_hits::l0subsys4.tester1 692 # number of ReadSharedReq MSHR hits +system.l2subsys0.cache3.ReadSharedReq_mshr_hits::l0subsys5.tester0 543 # number of ReadSharedReq MSHR hits +system.l2subsys0.cache3.ReadSharedReq_mshr_hits::l0subsys5.tester1 541 # number of ReadSharedReq MSHR hits +system.l2subsys0.cache3.ReadSharedReq_mshr_hits::total 2258 # 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number of ReadExReq MSHR misses +system.l2subsys0.cache3.ReadExReq_mshr_misses::l0subsys5.tester1 16441 # number of ReadExReq MSHR misses +system.l2subsys0.cache3.ReadExReq_mshr_misses::total 65905 # number of ReadExReq MSHR misses +system.l2subsys0.cache3.ReadSharedReq_mshr_misses::l0subsys4.tester0 28562 # number of ReadSharedReq MSHR misses +system.l2subsys0.cache3.ReadSharedReq_mshr_misses::l0subsys4.tester1 29144 # number of ReadSharedReq MSHR misses +system.l2subsys0.cache3.ReadSharedReq_mshr_misses::l0subsys5.tester0 29572 # number of ReadSharedReq MSHR misses +system.l2subsys0.cache3.ReadSharedReq_mshr_misses::l0subsys5.tester1 28894 # number of ReadSharedReq MSHR misses +system.l2subsys0.cache3.ReadSharedReq_mshr_misses::total 116172 # number of ReadSharedReq MSHR misses +system.l2subsys0.cache3.demand_mshr_misses::l0subsys4.tester0 44633 # number of demand (read+write) MSHR misses +system.l2subsys0.cache3.demand_mshr_misses::l0subsys4.tester1 45814 # number of demand (read+write) MSHR misses +system.l2subsys0.cache3.demand_mshr_misses::l0subsys5.tester0 46295 # number of demand (read+write) MSHR misses +system.l2subsys0.cache3.demand_mshr_misses::l0subsys5.tester1 45335 # number of demand (read+write) MSHR misses +system.l2subsys0.cache3.demand_mshr_misses::total 182077 # number of demand (read+write) MSHR misses +system.l2subsys0.cache3.overall_mshr_misses::l0subsys4.tester0 44633 # number of overall MSHR misses +system.l2subsys0.cache3.overall_mshr_misses::l0subsys4.tester1 45814 # number of overall MSHR misses +system.l2subsys0.cache3.overall_mshr_misses::l0subsys5.tester0 46295 # number of overall MSHR misses +system.l2subsys0.cache3.overall_mshr_misses::l0subsys5.tester1 45335 # number of overall MSHR misses +system.l2subsys0.cache3.overall_mshr_misses::total 182077 # number of overall MSHR misses +system.l2subsys0.cache3.UpgradeReq_mshr_miss_latency::l0subsys4.tester0 81963023 # number of UpgradeReq MSHR miss cycles +system.l2subsys0.cache3.UpgradeReq_mshr_miss_latency::l0subsys4.tester1 80624239 # number of UpgradeReq MSHR miss cycles +system.l2subsys0.cache3.UpgradeReq_mshr_miss_latency::l0subsys5.tester0 80607785 # number of UpgradeReq MSHR miss cycles +system.l2subsys0.cache3.UpgradeReq_mshr_miss_latency::l0subsys5.tester1 81849121 # number of UpgradeReq MSHR miss cycles +system.l2subsys0.cache3.UpgradeReq_mshr_miss_latency::total 325044168 # number of UpgradeReq MSHR miss cycles +system.l2subsys0.cache3.ReadExReq_mshr_miss_latency::l0subsys4.tester0 1404906880 # number of ReadExReq MSHR miss cycles +system.l2subsys0.cache3.ReadExReq_mshr_miss_latency::l0subsys4.tester1 1431588330 # number of ReadExReq MSHR miss cycles +system.l2subsys0.cache3.ReadExReq_mshr_miss_latency::l0subsys5.tester0 1436530645 # number of ReadExReq MSHR miss cycles +system.l2subsys0.cache3.ReadExReq_mshr_miss_latency::l0subsys5.tester1 1420292171 # number of ReadExReq MSHR miss cycles +system.l2subsys0.cache3.ReadExReq_mshr_miss_latency::total 5693318026 # number of ReadExReq MSHR miss cycles +system.l2subsys0.cache3.ReadSharedReq_mshr_miss_latency::l0subsys4.tester0 2526781875 # number of ReadSharedReq MSHR miss cycles +system.l2subsys0.cache3.ReadSharedReq_mshr_miss_latency::l0subsys4.tester1 2523316581 # number of ReadSharedReq MSHR miss cycles +system.l2subsys0.cache3.ReadSharedReq_mshr_miss_latency::l0subsys5.tester0 2559586993 # number of ReadSharedReq MSHR miss cycles +system.l2subsys0.cache3.ReadSharedReq_mshr_miss_latency::l0subsys5.tester1 2514975762 # number of ReadSharedReq MSHR miss cycles +system.l2subsys0.cache3.ReadSharedReq_mshr_miss_latency::total 10124661211 # number of ReadSharedReq MSHR miss cycles +system.l2subsys0.cache3.demand_mshr_miss_latency::l0subsys4.tester0 3931688755 # number of demand (read+write) MSHR miss cycles +system.l2subsys0.cache3.demand_mshr_miss_latency::l0subsys4.tester1 3954904911 # number of demand (read+write) MSHR miss cycles +system.l2subsys0.cache3.demand_mshr_miss_latency::l0subsys5.tester0 3996117638 # number of demand (read+write) MSHR miss cycles +system.l2subsys0.cache3.demand_mshr_miss_latency::l0subsys5.tester1 3935267933 # number of demand (read+write) MSHR miss cycles +system.l2subsys0.cache3.demand_mshr_miss_latency::total 15817979237 # number of demand (read+write) MSHR miss cycles +system.l2subsys0.cache3.overall_mshr_miss_latency::l0subsys4.tester0 3931688755 # number of overall MSHR miss cycles +system.l2subsys0.cache3.overall_mshr_miss_latency::l0subsys4.tester1 3954904911 # number of overall MSHR miss cycles +system.l2subsys0.cache3.overall_mshr_miss_latency::l0subsys5.tester0 3996117638 # number of overall MSHR miss cycles +system.l2subsys0.cache3.overall_mshr_miss_latency::l0subsys5.tester1 3935267933 # number of overall MSHR miss cycles +system.l2subsys0.cache3.overall_mshr_miss_latency::total 15817979237 # number of overall MSHR miss cycles system.l2subsys0.cache3.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.l2subsys0.cache3.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.l2subsys0.cache3.UpgradeReq_mshr_miss_rate::l0subsys4.tester0 1 # mshr miss rate for UpgradeReq accesses -system.l2subsys0.cache3.UpgradeReq_mshr_miss_rate::l0subsys4.tester1 1 # mshr miss rate for UpgradeReq accesses -system.l2subsys0.cache3.UpgradeReq_mshr_miss_rate::l0subsys5.tester0 1 # mshr miss rate for UpgradeReq accesses -system.l2subsys0.cache3.UpgradeReq_mshr_miss_rate::l0subsys5.tester1 1 # mshr miss rate for UpgradeReq accesses -system.l2subsys0.cache3.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses -system.l2subsys0.cache3.ReadExReq_mshr_miss_rate::l0subsys4.tester0 0.982625 # mshr miss rate for ReadExReq accesses -system.l2subsys0.cache3.ReadExReq_mshr_miss_rate::l0subsys4.tester1 0.979958 # mshr miss rate for ReadExReq accesses -system.l2subsys0.cache3.ReadExReq_mshr_miss_rate::l0subsys5.tester0 0.983544 # mshr miss rate for ReadExReq accesses -system.l2subsys0.cache3.ReadExReq_mshr_miss_rate::l0subsys5.tester1 0.980738 # mshr miss rate for ReadExReq accesses -system.l2subsys0.cache3.ReadExReq_mshr_miss_rate::total 0.981739 # mshr miss rate for ReadExReq accesses -system.l2subsys0.cache3.ReadSharedReq_mshr_miss_rate::l0subsys4.tester0 0.962570 # mshr miss rate for ReadSharedReq accesses -system.l2subsys0.cache3.ReadSharedReq_mshr_miss_rate::l0subsys4.tester1 0.958141 # mshr miss rate for ReadSharedReq accesses -system.l2subsys0.cache3.ReadSharedReq_mshr_miss_rate::l0subsys5.tester0 0.968990 # mshr miss rate for ReadSharedReq accesses -system.l2subsys0.cache3.ReadSharedReq_mshr_miss_rate::l0subsys5.tester1 0.963447 # mshr miss rate for ReadSharedReq accesses -system.l2subsys0.cache3.ReadSharedReq_mshr_miss_rate::total 0.963367 # mshr miss rate for ReadSharedReq accesses -system.l2subsys0.cache3.demand_mshr_miss_rate::l0subsys4.tester0 0.969801 # mshr miss rate for demand accesses -system.l2subsys0.cache3.demand_mshr_miss_rate::l0subsys4.tester1 0.965953 # mshr miss rate for demand accesses -system.l2subsys0.cache3.demand_mshr_miss_rate::l0subsys5.tester0 0.974168 # mshr miss rate for demand accesses -system.l2subsys0.cache3.demand_mshr_miss_rate::l0subsys5.tester1 0.969588 # mshr miss rate for demand accesses -system.l2subsys0.cache3.demand_mshr_miss_rate::total 0.969933 # mshr miss rate for demand accesses -system.l2subsys0.cache3.overall_mshr_miss_rate::l0subsys4.tester0 0.969801 # mshr miss rate for overall accesses -system.l2subsys0.cache3.overall_mshr_miss_rate::l0subsys4.tester1 0.965953 # mshr miss rate for overall accesses -system.l2subsys0.cache3.overall_mshr_miss_rate::l0subsys5.tester0 0.974168 # mshr miss rate for overall accesses -system.l2subsys0.cache3.overall_mshr_miss_rate::l0subsys5.tester1 0.969588 # mshr miss rate for overall accesses -system.l2subsys0.cache3.overall_mshr_miss_rate::total 0.969933 # mshr miss rate for overall accesses -system.l2subsys0.cache3.UpgradeReq_avg_mshr_miss_latency::l0subsys4.tester0 23749.444301 # average UpgradeReq mshr miss latency -system.l2subsys0.cache3.UpgradeReq_avg_mshr_miss_latency::l0subsys4.tester1 23651.172396 # average UpgradeReq mshr miss latency -system.l2subsys0.cache3.UpgradeReq_avg_mshr_miss_latency::l0subsys5.tester0 23367.687126 # average UpgradeReq mshr miss latency -system.l2subsys0.cache3.UpgradeReq_avg_mshr_miss_latency::l0subsys5.tester1 23231.726043 # average UpgradeReq mshr miss latency -system.l2subsys0.cache3.UpgradeReq_avg_mshr_miss_latency::total 23504.312290 # average UpgradeReq mshr miss latency -system.l2subsys0.cache3.ReadExReq_avg_mshr_miss_latency::l0subsys4.tester0 89412.807207 # average ReadExReq mshr miss latency -system.l2subsys0.cache3.ReadExReq_avg_mshr_miss_latency::l0subsys4.tester1 86725.556937 # average ReadExReq mshr miss latency -system.l2subsys0.cache3.ReadExReq_avg_mshr_miss_latency::l0subsys5.tester0 86275.348906 # average ReadExReq mshr miss latency -system.l2subsys0.cache3.ReadExReq_avg_mshr_miss_latency::l0subsys5.tester1 87595.089275 # average ReadExReq mshr miss latency -system.l2subsys0.cache3.ReadExReq_avg_mshr_miss_latency::total 87503.477701 # average ReadExReq mshr miss latency -system.l2subsys0.cache3.ReadSharedReq_avg_mshr_miss_latency::l0subsys4.tester0 89779.850811 # average ReadSharedReq mshr miss latency -system.l2subsys0.cache3.ReadSharedReq_avg_mshr_miss_latency::l0subsys4.tester1 87746.774320 # average ReadSharedReq mshr miss latency -system.l2subsys0.cache3.ReadSharedReq_avg_mshr_miss_latency::l0subsys5.tester0 86368.250908 # average ReadSharedReq mshr miss latency -system.l2subsys0.cache3.ReadSharedReq_avg_mshr_miss_latency::l0subsys5.tester1 87673.229813 # average ReadSharedReq mshr miss latency -system.l2subsys0.cache3.ReadSharedReq_avg_mshr_miss_latency::total 87875.427784 # average ReadSharedReq mshr miss latency -system.l2subsys0.cache3.demand_avg_mshr_miss_latency::l0subsys4.tester0 89645.762780 # average overall mshr miss latency -system.l2subsys0.cache3.demand_avg_mshr_miss_latency::l0subsys4.tester1 87375.775953 # average overall mshr miss latency -system.l2subsys0.cache3.demand_avg_mshr_miss_latency::l0subsys5.tester0 86334.880792 # average overall mshr miss latency -system.l2subsys0.cache3.demand_avg_mshr_miss_latency::l0subsys5.tester1 87645.156672 # average overall mshr miss latency -system.l2subsys0.cache3.demand_avg_mshr_miss_latency::total 87740.882016 # average overall mshr miss latency -system.l2subsys0.cache3.overall_avg_mshr_miss_latency::l0subsys4.tester0 89645.762780 # average overall mshr miss latency -system.l2subsys0.cache3.overall_avg_mshr_miss_latency::l0subsys4.tester1 87375.775953 # average overall mshr miss latency -system.l2subsys0.cache3.overall_avg_mshr_miss_latency::l0subsys5.tester0 86334.880792 # average overall mshr miss latency -system.l2subsys0.cache3.overall_avg_mshr_miss_latency::l0subsys5.tester1 87645.156672 # average overall mshr miss latency -system.l2subsys0.cache3.overall_avg_mshr_miss_latency::total 87740.882016 # average overall mshr miss latency +system.l2subsys0.cache3.UpgradeReq_mshr_miss_rate::l0subsys4.tester0 0.953652 # mshr miss rate for UpgradeReq accesses +system.l2subsys0.cache3.UpgradeReq_mshr_miss_rate::l0subsys4.tester1 0.947121 # mshr miss rate for UpgradeReq accesses +system.l2subsys0.cache3.UpgradeReq_mshr_miss_rate::l0subsys5.tester0 0.959121 # mshr miss rate for UpgradeReq accesses +system.l2subsys0.cache3.UpgradeReq_mshr_miss_rate::l0subsys5.tester1 0.947099 # mshr miss rate for UpgradeReq accesses +system.l2subsys0.cache3.UpgradeReq_mshr_miss_rate::total 0.951703 # mshr miss rate for UpgradeReq accesses +system.l2subsys0.cache3.ReadExReq_mshr_miss_rate::l0subsys4.tester0 0.981375 # mshr miss rate for ReadExReq accesses +system.l2subsys0.cache3.ReadExReq_mshr_miss_rate::l0subsys4.tester1 0.974284 # mshr miss rate for ReadExReq accesses +system.l2subsys0.cache3.ReadExReq_mshr_miss_rate::l0subsys5.tester0 0.980936 # mshr miss rate for ReadExReq accesses +system.l2subsys0.cache3.ReadExReq_mshr_miss_rate::l0subsys5.tester1 0.980265 # mshr miss rate for ReadExReq accesses +system.l2subsys0.cache3.ReadExReq_mshr_miss_rate::total 0.979185 # mshr miss rate for ReadExReq accesses +system.l2subsys0.cache3.ReadSharedReq_mshr_miss_rate::l0subsys4.tester0 0.964835 # mshr miss rate for ReadSharedReq accesses +system.l2subsys0.cache3.ReadSharedReq_mshr_miss_rate::l0subsys4.tester1 0.950865 # mshr miss rate for ReadSharedReq accesses +system.l2subsys0.cache3.ReadSharedReq_mshr_miss_rate::l0subsys5.tester0 0.961378 # mshr miss rate for ReadSharedReq accesses +system.l2subsys0.cache3.ReadSharedReq_mshr_miss_rate::l0subsys5.tester1 0.960157 # mshr miss rate for ReadSharedReq accesses +system.l2subsys0.cache3.ReadSharedReq_mshr_miss_rate::total 0.959259 # mshr miss rate for ReadSharedReq accesses +system.l2subsys0.cache3.demand_mshr_miss_rate::l0subsys4.tester0 0.970726 # mshr miss rate for demand accesses +system.l2subsys0.cache3.demand_mshr_miss_rate::l0subsys4.tester1 0.959255 # mshr miss rate for demand accesses +system.l2subsys0.cache3.demand_mshr_miss_rate::l0subsys5.tester0 0.968353 # mshr miss rate for demand accesses +system.l2subsys0.cache3.demand_mshr_miss_rate::l0subsys5.tester1 0.967353 # mshr miss rate for demand accesses +system.l2subsys0.cache3.demand_mshr_miss_rate::total 0.966377 # mshr miss rate for demand accesses +system.l2subsys0.cache3.overall_mshr_miss_rate::l0subsys4.tester0 0.970726 # mshr miss rate for overall accesses +system.l2subsys0.cache3.overall_mshr_miss_rate::l0subsys4.tester1 0.959255 # mshr miss rate for overall accesses +system.l2subsys0.cache3.overall_mshr_miss_rate::l0subsys5.tester0 0.968353 # mshr miss rate for overall accesses +system.l2subsys0.cache3.overall_mshr_miss_rate::l0subsys5.tester1 0.967353 # mshr miss rate for overall accesses +system.l2subsys0.cache3.overall_mshr_miss_rate::total 0.966377 # mshr miss rate for overall accesses +system.l2subsys0.cache3.UpgradeReq_avg_mshr_miss_latency::l0subsys4.tester0 24142.274816 # average UpgradeReq mshr miss latency +system.l2subsys0.cache3.UpgradeReq_avg_mshr_miss_latency::l0subsys4.tester1 23567.447822 # average UpgradeReq mshr miss latency +system.l2subsys0.cache3.UpgradeReq_avg_mshr_miss_latency::l0subsys5.tester0 23371.349667 # average UpgradeReq mshr miss latency +system.l2subsys0.cache3.UpgradeReq_avg_mshr_miss_latency::l0subsys5.tester1 23325.483329 # average UpgradeReq mshr miss latency +system.l2subsys0.cache3.UpgradeReq_avg_mshr_miss_latency::total 23598.385945 # average UpgradeReq mshr miss latency +system.l2subsys0.cache3.ReadExReq_avg_mshr_miss_latency::l0subsys4.tester0 87418.759256 # average ReadExReq mshr miss latency +system.l2subsys0.cache3.ReadExReq_avg_mshr_miss_latency::l0subsys4.tester1 85878.124175 # average ReadExReq mshr miss latency +system.l2subsys0.cache3.ReadExReq_avg_mshr_miss_latency::l0subsys5.tester0 85901.491658 # average ReadExReq mshr miss latency +system.l2subsys0.cache3.ReadExReq_avg_mshr_miss_latency::l0subsys5.tester1 86387.213126 # average ReadExReq mshr miss latency +system.l2subsys0.cache3.ReadExReq_avg_mshr_miss_latency::total 86386.738882 # average ReadExReq mshr miss latency +system.l2subsys0.cache3.ReadSharedReq_avg_mshr_miss_latency::l0subsys4.tester0 88466.559590 # average ReadSharedReq mshr miss latency +system.l2subsys0.cache3.ReadSharedReq_avg_mshr_miss_latency::l0subsys4.tester1 86580.997152 # average ReadSharedReq mshr miss latency +system.l2subsys0.cache3.ReadSharedReq_avg_mshr_miss_latency::l0subsys5.tester0 86554.409340 # average ReadSharedReq mshr miss latency +system.l2subsys0.cache3.ReadSharedReq_avg_mshr_miss_latency::l0subsys5.tester1 87041.453658 # average ReadSharedReq mshr miss latency +system.l2subsys0.cache3.ReadSharedReq_avg_mshr_miss_latency::total 87152.336286 # average ReadSharedReq mshr miss latency +system.l2subsys0.cache3.demand_avg_mshr_miss_latency::l0subsys4.tester0 88089.278225 # average overall mshr miss latency +system.l2subsys0.cache3.demand_avg_mshr_miss_latency::l0subsys4.tester1 86325.247981 # average overall mshr miss latency +system.l2subsys0.cache3.demand_avg_mshr_miss_latency::l0subsys5.tester0 86318.557900 # average overall mshr miss latency +system.l2subsys0.cache3.demand_avg_mshr_miss_latency::l0subsys5.tester1 86804.189545 # average overall mshr miss latency +system.l2subsys0.cache3.demand_avg_mshr_miss_latency::total 86875.218929 # average overall mshr miss latency +system.l2subsys0.cache3.overall_avg_mshr_miss_latency::l0subsys4.tester0 88089.278225 # average overall mshr miss latency +system.l2subsys0.cache3.overall_avg_mshr_miss_latency::l0subsys4.tester1 86325.247981 # average overall mshr miss latency +system.l2subsys0.cache3.overall_avg_mshr_miss_latency::l0subsys5.tester0 86318.557900 # average overall mshr miss latency +system.l2subsys0.cache3.overall_avg_mshr_miss_latency::l0subsys5.tester1 86804.189545 # average overall mshr miss latency +system.l2subsys0.cache3.overall_avg_mshr_miss_latency::total 86875.218929 # average overall mshr miss latency system.l2subsys0.checkers.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states system.l2subsys0.tester.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states -system.l2subsys0.tester.numPackets 68517 # Number of packets generated -system.l2subsys0.tester.numRetries 121 # Number of retries -system.l2subsys0.tester.retryTicks 5829034 # Time spent waiting due to back-pressure (ticks) -system.l2subsys0.xbar.snoop_filter.tot_requests 1076493 # Total number of requests made to the snoop filter. -system.l2subsys0.xbar.snoop_filter.hit_single_requests 529775 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.l2subsys0.xbar.snoop_filter.hit_multi_requests 120892 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.l2subsys0.tester.numPackets 67448 # Number of packets generated +system.l2subsys0.tester.numRetries 90 # Number of retries +system.l2subsys0.tester.retryTicks 3855703 # Time spent waiting due to back-pressure (ticks) +system.l2subsys0.xbar.snoop_filter.tot_requests 1069827 # Total number of requests made to the snoop filter. +system.l2subsys0.xbar.snoop_filter.hit_single_requests 521153 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.l2subsys0.xbar.snoop_filter.hit_multi_requests 129649 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.l2subsys0.xbar.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.l2subsys0.xbar.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.l2subsys0.xbar.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.l2subsys0.xbar.pwrStateResidencyTicks::UNDEFINED 10000000000 # Cumulative time (in ticks) in various power states -system.l2subsys0.xbar.trans_dist::ReadResp 374921 # Transaction distribution -system.l2subsys0.xbar.trans_dist::ReadRespWithInvalidate 1348 # Transaction distribution -system.l2subsys0.xbar.trans_dist::WritebackDirty 151339 # Transaction distribution -system.l2subsys0.xbar.trans_dist::CleanEvict 272890 # Transaction distribution -system.l2subsys0.xbar.trans_dist::UpgradeReq 55357 # Transaction distribution -system.l2subsys0.xbar.trans_dist::UpgradeResp 28680 # Transaction distribution -system.l2subsys0.xbar.trans_dist::ReadExReq 220635 # Transaction distribution -system.l2subsys0.xbar.trans_dist::ReadExResp 216743 # Transaction distribution -system.l2subsys0.xbar.trans_dist::ReadSharedReq 376272 # Transaction distribution -system.l2subsys0.xbar.pkt_count_system.l2subsys0.cache1.mem_side::system.physmem.port 471947 # Packet count per connected master and slave (bytes) -system.l2subsys0.xbar.pkt_count_system.l2subsys0.cache2.mem_side::system.physmem.port 447710 # Packet count per connected master and slave (bytes) -system.l2subsys0.xbar.pkt_count_system.l2subsys0.cache3.mem_side::system.physmem.port 461540 # Packet count per connected master and slave (bytes) -system.l2subsys0.xbar.pkt_count_system.l2subsys0.cache0.mem_side::system.physmem.port 125522 # Packet count per connected master and slave (bytes) -system.l2subsys0.xbar.pkt_count::total 1506719 # Packet count per connected master and slave (bytes) -system.l2subsys0.xbar.pkt_size_system.l2subsys0.cache1.mem_side::system.physmem.port 11798528 # Cumulative packet size per connected master and slave (bytes) -system.l2subsys0.xbar.pkt_size_system.l2subsys0.cache2.mem_side::system.physmem.port 11044864 # Cumulative packet size per connected master and slave (bytes) -system.l2subsys0.xbar.pkt_size_system.l2subsys0.cache3.mem_side::system.physmem.port 11439552 # Cumulative packet size per connected master and slave (bytes) -system.l2subsys0.xbar.pkt_size_system.l2subsys0.cache0.mem_side::system.physmem.port 2937216 # Cumulative packet size per connected master and slave (bytes) -system.l2subsys0.xbar.pkt_size::total 37220160 # Cumulative packet size per connected master and slave (bytes) -system.l2subsys0.xbar.snoops 200506 # Total snoops (count) -system.l2subsys0.xbar.snoopTraffic 10418304 # Total snoop traffic (bytes) -system.l2subsys0.xbar.snoop_fanout::samples 652264 # Request fanout histogram -system.l2subsys0.xbar.snoop_fanout::mean 0.480016 # Request fanout histogram -system.l2subsys0.xbar.snoop_fanout::stdev 0.745912 # Request fanout histogram +system.l2subsys0.xbar.trans_dist::ReadResp 375461 # Transaction distribution +system.l2subsys0.xbar.trans_dist::ReadRespWithInvalidate 1760 # Transaction distribution +system.l2subsys0.xbar.trans_dist::WritebackDirty 148958 # Transaction distribution +system.l2subsys0.xbar.trans_dist::CleanEvict 268634 # Transaction distribution +system.l2subsys0.xbar.trans_dist::UpgradeReq 51775 # Transaction distribution +system.l2subsys0.xbar.trans_dist::UpgradeResp 28212 # Transaction distribution +system.l2subsys0.xbar.trans_dist::ReadExReq 223238 # Transaction distribution +system.l2subsys0.xbar.trans_dist::ReadExResp 218900 # Transaction distribution +system.l2subsys0.xbar.trans_dist::ReadSharedReq 377222 # Transaction distribution +system.l2subsys0.xbar.pkt_count_system.l2subsys0.cache1.mem_side::system.physmem.port 454786 # Packet count per connected master and slave (bytes) +system.l2subsys0.xbar.pkt_count_system.l2subsys0.cache2.mem_side::system.physmem.port 447989 # Packet count per connected master and slave (bytes) +system.l2subsys0.xbar.pkt_count_system.l2subsys0.cache3.mem_side::system.physmem.port 462519 # Packet count per connected master and slave (bytes) +system.l2subsys0.xbar.pkt_count_system.l2subsys0.cache0.mem_side::system.physmem.port 127384 # Packet count per connected master and slave (bytes) +system.l2subsys0.xbar.pkt_count::total 1492678 # Packet count per connected master and slave (bytes) +system.l2subsys0.xbar.pkt_size_system.l2subsys0.cache1.mem_side::system.physmem.port 11217984 # Cumulative packet size per connected master and slave (bytes) +system.l2subsys0.xbar.pkt_size_system.l2subsys0.cache2.mem_side::system.physmem.port 11005568 # Cumulative packet size per connected master and slave (bytes) +system.l2subsys0.xbar.pkt_size_system.l2subsys0.cache3.mem_side::system.physmem.port 11412416 # Cumulative packet size per connected master and slave (bytes) +system.l2subsys0.xbar.pkt_size_system.l2subsys0.cache0.mem_side::system.physmem.port 2959808 # Cumulative packet size per connected master and slave (bytes) +system.l2subsys0.xbar.pkt_size::total 36595776 # Cumulative packet size per connected master and slave (bytes) +system.l2subsys0.xbar.snoops 210714 # Total snoops (count) +system.l2subsys0.xbar.snoopTraffic 11089280 # Total snoop traffic (bytes) +system.l2subsys0.xbar.snoop_fanout::samples 652235 # Request fanout histogram +system.l2subsys0.xbar.snoop_fanout::mean 0.520105 # Request fanout histogram +system.l2subsys0.xbar.snoop_fanout::stdev 0.790254 # Request fanout histogram system.l2subsys0.xbar.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.l2subsys0.xbar.snoop_fanout::0 429345 65.82% 65.82% # Request fanout histogram -system.l2subsys0.xbar.snoop_fanout::1 142615 21.86% 87.69% # Request fanout histogram -system.l2subsys0.xbar.snoop_fanout::2 70430 10.80% 98.49% # Request fanout histogram -system.l2subsys0.xbar.snoop_fanout::3 9874 1.51% 100.00% # Request fanout histogram +system.l2subsys0.xbar.snoop_fanout::0 420662 64.50% 64.50% # Request fanout histogram +system.l2subsys0.xbar.snoop_fanout::1 138520 21.24% 85.73% # Request fanout histogram +system.l2subsys0.xbar.snoop_fanout::2 78448 12.03% 97.76% # Request fanout histogram +system.l2subsys0.xbar.snoop_fanout::3 14605 2.24% 100.00% # Request fanout histogram system.l2subsys0.xbar.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.l2subsys0.xbar.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.l2subsys0.xbar.snoop_fanout::min_value 0 # Request fanout histogram system.l2subsys0.xbar.snoop_fanout::max_value 3 # Request fanout histogram -system.l2subsys0.xbar.snoop_fanout::total 652264 # Request fanout histogram -system.l2subsys0.xbar.reqLayer0.occupancy 1612904465 # Layer occupancy (ticks) -system.l2subsys0.xbar.reqLayer0.utilization 16.1 # Layer utilization (%) -system.l2subsys0.xbar.respLayer0.occupancy 655215336 # Layer occupancy (ticks) -system.l2subsys0.xbar.respLayer0.utilization 6.6 # Layer utilization (%) -system.l2subsys0.xbar.respLayer1.occupancy 628908219 # Layer occupancy (ticks) -system.l2subsys0.xbar.respLayer1.utilization 6.3 # Layer utilization (%) -system.l2subsys0.xbar.respLayer2.occupancy 645551493 # Layer occupancy (ticks) +system.l2subsys0.xbar.snoop_fanout::total 652235 # Request fanout histogram +system.l2subsys0.xbar.reqLayer0.occupancy 1600277509 # Layer occupancy (ticks) +system.l2subsys0.xbar.reqLayer0.utilization 16.0 # Layer utilization (%) +system.l2subsys0.xbar.respLayer0.occupancy 643009360 # Layer occupancy (ticks) +system.l2subsys0.xbar.respLayer0.utilization 6.4 # Layer utilization (%) +system.l2subsys0.xbar.respLayer1.occupancy 635003682 # Layer occupancy (ticks) +system.l2subsys0.xbar.respLayer1.utilization 6.4 # Layer utilization (%) +system.l2subsys0.xbar.respLayer2.occupancy 652235888 # Layer occupancy (ticks) system.l2subsys0.xbar.respLayer2.utilization 6.5 # Layer utilization (%) -system.l2subsys0.xbar.respLayer3.occupancy 182844725 # Layer occupancy (ticks) -system.l2subsys0.xbar.respLayer3.utilization 1.8 # Layer utilization (%) +system.l2subsys0.xbar.respLayer3.occupancy 189829895 # Layer occupancy (ticks) +system.l2subsys0.xbar.respLayer3.utilization 1.9 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt b/tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt index 767676900..3247793b8 100644 --- a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.045952 # Nu sim_ticks 45951567500 # Number of ticks simulated final_tick 45951567500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1662720 # Simulator instruction rate (inst/s) -host_op_rate 1662720 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 831360258 # Simulator tick rate (ticks/s) -host_mem_usage 243160 # Number of bytes of host memory used -host_seconds 55.27 # Real time elapsed on the host +host_inst_rate 1661672 # Simulator instruction rate (inst/s) +host_op_rate 1661672 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 830836471 # Simulator tick rate (ticks/s) +host_mem_usage 246768 # Number of bytes of host memory used +host_seconds 55.31 # Real time elapsed on the host sim_insts 91903056 # Number of instructions simulated sim_ops 91903056 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -130,6 +130,12 @@ system.cpu.op_class::MemWrite 6501126 7.07% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 91903089 # Class of executed instruction +system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.pwrStateResidencyTicks::UNDEFINED 45951567500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 111899287 # Transaction distribution system.membus.trans_dist::ReadResp 111899287 # Transaction distribution @@ -144,14 +150,14 @@ system.membus.pkt_size::total 506870851 # Cu system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) system.membus.snoop_fanout::samples 118400390 # Request fanout histogram -system.membus.snoop_fanout::mean 0.776206 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.416786 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 26497301 22.38% 22.38% # Request fanout histogram -system.membus.snoop_fanout::1 91903089 77.62% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 118400390 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 118400390 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt b/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt index 7a58e848d..2c1174f11 100644 --- a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.118763 # Number of seconds simulated -sim_ticks 118762761500 # Number of ticks simulated -final_tick 118762761500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.118768 # Number of seconds simulated +sim_ticks 118767526500 # Number of ticks simulated +final_tick 118767526500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1076459 # Simulator instruction rate (inst/s) -host_op_rate 1076459 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1391065983 # Simulator tick rate (ticks/s) -host_mem_usage 253156 # Number of bytes of host memory used -host_seconds 85.38 # Real time elapsed on the host +host_inst_rate 1126977 # Simulator instruction rate (inst/s) +host_op_rate 1126976 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1456406210 # Simulator tick rate (ticks/s) +host_mem_usage 256508 # Number of bytes of host memory used +host_seconds 81.55 # Real time elapsed on the host sim_insts 91903056 # Number of instructions simulated sim_ops 91903056 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 118762761500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 118767526500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 167744 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 137216 # Number of bytes read from this memory system.physmem.bytes_read::total 304960 # Number of bytes read from this memory @@ -22,15 +22,15 @@ system.physmem.bytes_inst_read::total 167744 # Nu system.physmem.num_reads::cpu.inst 2621 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 2144 # Number of read requests responded to by this memory system.physmem.num_reads::total 4765 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1412429 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1155379 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2567808 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1412429 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1412429 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1412429 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1155379 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2567808 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 118762761500 # Cumulative time (in ticks) in various power states +system.physmem.bw_read::cpu.inst 1412373 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1155333 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2567705 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1412373 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1412373 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1412373 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1155333 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2567705 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 118767526500 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses @@ -65,8 +65,8 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 389 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 118762761500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 237525523 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 118767526500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 237535053 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 91903056 # Number of instructions committed @@ -85,7 +85,7 @@ system.cpu.num_mem_refs 26497334 # nu system.cpu.num_load_insts 19996208 # Number of load instructions system.cpu.num_store_insts 6501126 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 237525523 # Number of busy cycles +system.cpu.num_busy_cycles 237535053 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 10240685 # Number of branches fetched @@ -124,16 +124,16 @@ system.cpu.op_class::MemWrite 6501126 7.07% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 91903089 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 118762761500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 118767526500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 157 # number of replacements -system.cpu.dcache.tags.tagsinuse 1441.946319 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 1441.932454 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 26495078 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 2223 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 11918.613585 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1441.946319 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.352038 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.352038 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 1441.932454 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.352034 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.352034 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 2066 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 17 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 17 # Occupied blocks per task id @@ -143,7 +143,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::4 1372 system.cpu.dcache.tags.occ_task_id_percent::1024 0.504395 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 52996825 # Number of tag accesses system.cpu.dcache.tags.data_accesses 52996825 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 118762761500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 118767526500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 19995723 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 19995723 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 6499355 # number of WriteReq hits @@ -160,14 +160,14 @@ system.cpu.dcache.demand_misses::cpu.data 2223 # n system.cpu.dcache.demand_misses::total 2223 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 2223 # number of overall misses system.cpu.dcache.overall_misses::total 2223 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 26856500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 26856500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 107103000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 107103000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 133959500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 133959500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 133959500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 133959500 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 27278500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 27278500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 108825000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 108825000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 136103500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 136103500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 136103500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 136103500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 19996198 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 19996198 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) @@ -184,14 +184,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000084 system.cpu.dcache.demand_miss_rate::total 0.000084 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000084 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000084 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56540 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 56540 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61271.739130 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 61271.739130 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 60260.683761 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 60260.683761 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 60260.683761 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 60260.683761 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 57428.421053 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 57428.421053 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62256.864989 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 62256.864989 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 61225.146199 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 61225.146199 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 61225.146199 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 61225.146199 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -208,14 +208,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 2223 system.cpu.dcache.demand_mshr_misses::total 2223 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 2223 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 2223 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 26381500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 26381500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 105355000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 105355000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 131736500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 131736500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 131736500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 131736500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 26803500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 26803500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 107077000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 107077000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 133880500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 133880500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 133880500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 133880500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000269 # mshr miss rate for WriteReq accesses @@ -224,24 +224,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000084 system.cpu.dcache.demand_mshr_miss_rate::total 0.000084 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 55540 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 55540 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 60271.739130 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 60271.739130 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 59260.683761 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 59260.683761 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 59260.683761 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 59260.683761 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 118762761500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 56428.421053 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 56428.421053 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61256.864989 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61256.864989 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 60225.146199 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 60225.146199 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 60225.146199 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 60225.146199 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 118767526500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 6681 # number of replacements -system.cpu.icache.tags.tagsinuse 1417.953327 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1417.939126 # Cycle average of tags in use system.cpu.icache.tags.total_refs 91894580 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 8510 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 10798.423032 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1417.953327 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.692360 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.692360 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1417.939126 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.692353 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.692353 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1829 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id @@ -251,7 +251,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 953 system.cpu.icache.tags.occ_task_id_percent::1024 0.893066 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 183814690 # Number of tag accesses system.cpu.icache.tags.data_accesses 183814690 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 118762761500 # Cumulative time (in ticks) in various power states +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 118767526500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 91894580 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 91894580 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 91894580 # number of demand (read+write) hits @@ -264,12 +264,12 @@ system.cpu.icache.demand_misses::cpu.inst 8510 # n system.cpu.icache.demand_misses::total 8510 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 8510 # number of overall misses system.cpu.icache.overall_misses::total 8510 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 239145000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 239145000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 239145000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 239145000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 239145000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 239145000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 241766000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 241766000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 241766000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 241766000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 241766000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 241766000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 91903090 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 91903090 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 91903090 # number of demand (read+write) accesses @@ -282,12 +282,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000093 system.cpu.icache.demand_miss_rate::total 0.000093 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000093 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000093 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28101.645123 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 28101.645123 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 28101.645123 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 28101.645123 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 28101.645123 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 28101.645123 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28409.635723 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 28409.635723 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 28409.635723 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 28409.635723 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 28409.635723 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 28409.635723 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -302,48 +302,46 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 8510 system.cpu.icache.demand_mshr_misses::total 8510 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 8510 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 8510 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 230635000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 230635000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 230635000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 230635000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 230635000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 230635000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 233256000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 233256000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 233256000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 233256000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 233256000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 233256000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000093 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000093 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000093 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000093 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000093 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000093 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 27101.645123 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 27101.645123 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 27101.645123 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 27101.645123 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 27101.645123 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 27101.645123 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 118762761500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 27409.635723 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 27409.635723 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 27409.635723 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 27409.635723 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 27409.635723 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 27409.635723 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 118767526500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 2073.923151 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 12687 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 3109 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 4.080733 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 3172.251150 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 12806 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 4765 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 2.687513 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 17.795341 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1704.894227 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 351.233582 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.000543 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1704.876553 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 1467.374597 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.052029 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.010719 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.063291 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 3109 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 32 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 221 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 703 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2096 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.094879 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 145425 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 145425 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 118762761500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.occ_percent::cpu.data 0.044781 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.096809 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 4765 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 40 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 346 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1127 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3196 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.145416 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 145333 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 145333 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 118767526500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 107 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 107 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 6681 # number of WritebackClean hits @@ -372,18 +370,18 @@ system.cpu.l2cache.demand_misses::total 4765 # nu system.cpu.l2cache.overall_misses::cpu.inst 2621 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 2144 # number of overall misses system.cpu.l2cache.overall_misses::total 4765 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 102460000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 102460000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 155964000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 155964000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 25110500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 25110500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 155964000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 127570500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 283534500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 155964000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 127570500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 283534500 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 104182000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 104182000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 158585000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 158585000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 25532500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 25532500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 158585000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 129714500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 288299500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 158585000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 129714500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 288299500 # number of overall miss cycles system.cpu.l2cache.WritebackDirty_accesses::writebacks 107 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackDirty_accesses::total 107 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::writebacks 6681 # number of WritebackClean accesses(hits+misses) @@ -412,18 +410,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.443958 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.307991 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.964462 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.443958 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500.580720 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500.580720 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59505.532240 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59505.532240 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59503.554502 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59503.554502 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59505.532240 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59501.166045 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 59503.567681 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59505.532240 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59501.166045 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 59503.567681 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500.580720 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500.580720 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60505.532240 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60505.532240 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60503.554502 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60503.554502 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60505.532240 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60501.166045 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 60503.567681 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60505.532240 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60501.166045 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 60503.567681 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -442,18 +440,18 @@ system.cpu.l2cache.demand_mshr_misses::total 4765 system.cpu.l2cache.overall_mshr_misses::cpu.inst 2621 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 2144 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 4765 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 85240000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 85240000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 129754000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 129754000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 20890500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 20890500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 129754000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 106130500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 235884500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 129754000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 106130500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 235884500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 86962000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 86962000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 132375000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 132375000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 21312500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 21312500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 132375000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 108274500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 240649500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 132375000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 108274500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 240649500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.985126 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.985126 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.307991 # mshr miss rate for ReadCleanReq accesses @@ -466,25 +464,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.443958 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.307991 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964462 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.443958 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500.580720 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500.580720 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49505.532240 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49505.532240 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49503.554502 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49503.554502 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49505.532240 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49501.166045 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49503.567681 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49505.532240 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49501.166045 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49503.567681 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500.580720 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500.580720 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50505.532240 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50505.532240 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50503.554502 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50503.554502 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50505.532240 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50501.166045 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50503.567681 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50505.532240 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50501.166045 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50503.567681 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 17571 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 6838 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 118762761500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 118767526500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 8985 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 107 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 6681 # Transaction distribution @@ -518,7 +516,13 @@ system.cpu.toL2Bus.respLayer0.occupancy 12765000 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 3334500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 118762761500 # Cumulative time (in ticks) in various power states +system.membus.snoop_filter.tot_requests 4765 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 118767526500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 3043 # Transaction distribution system.membus.trans_dist::ReadExReq 1722 # Transaction distribution system.membus.trans_dist::ReadExResp 1722 # Transaction distribution diff --git a/tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt b/tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt index 1f598d967..1b2962550 100644 --- a/tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.099596 # Nu sim_ticks 99596491500 # Number of ticks simulated final_tick 99596491500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 985729 # Simulator instruction rate (inst/s) -host_op_rate 1039117 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 569734073 # Simulator tick rate (ticks/s) -host_mem_usage 259900 # Number of bytes of host memory used -host_seconds 174.81 # Real time elapsed on the host +host_inst_rate 1084851 # Simulator instruction rate (inst/s) +host_op_rate 1143608 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 627025223 # Simulator tick rate (ticks/s) +host_mem_usage 263772 # Number of bytes of host memory used +host_seconds 158.84 # Real time elapsed on the host sim_insts 172317410 # Number of instructions simulated sim_ops 181650342 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -220,6 +220,12 @@ system.cpu.op_class::MemWrite 12644635 6.96% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 181650743 # Class of executed instruction +system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.pwrStateResidencyTicks::UNDEFINED 99596491500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 217614903 # Transaction distribution system.membus.trans_dist::ReadResp 217637310 # Transaction distribution @@ -239,14 +245,14 @@ system.membus.pkt_size::total 915226809 # Cu system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) system.membus.snoop_fanout::samples 230024467 # Request fanout histogram -system.membus.snoop_fanout::mean 0.825391 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.379633 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 40164415 17.46% 17.46% # Request fanout histogram -system.membus.snoop_fanout::1 189860052 82.54% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 230024467 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 230024467 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/stats.txt index b87761f8a..21be26077 100644 --- a/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/stats.txt +++ b/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.230198 # Number of seconds simulated -sim_ticks 230197694500 # Number of ticks simulated -final_tick 230197694500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.230201 # Number of seconds simulated +sim_ticks 230201146500 # Number of ticks simulated +final_tick 230201146500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 688414 # Simulator instruction rate (inst/s) -host_op_rate 725763 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 922189750 # Simulator tick rate (ticks/s) -host_mem_usage 268612 # Number of bytes of host memory used -host_seconds 249.62 # Real time elapsed on the host +host_inst_rate 826360 # Simulator instruction rate (inst/s) +host_op_rate 871192 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1106995865 # Simulator tick rate (ticks/s) +host_mem_usage 273252 # Number of bytes of host memory used +host_seconds 207.95 # Real time elapsed on the host sim_insts 171842484 # Number of instructions simulated sim_ops 181165371 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 230197694500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 230201146500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 110656 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 110336 # Number of bytes read from this memory system.physmem.bytes_read::total 220992 # Number of bytes read from this memory @@ -22,17 +22,17 @@ system.physmem.bytes_inst_read::total 110656 # Nu system.physmem.num_reads::cpu.inst 1729 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 1724 # Number of read requests responded to by this memory system.physmem.num_reads::total 3453 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 480700 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 479310 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 960010 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 480700 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 480700 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 480700 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 479310 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 960010 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 230197694500 # Cumulative time (in ticks) in various power states +system.physmem.bw_read::cpu.inst 480693 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 479303 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 959995 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 480693 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 480693 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 480693 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 479303 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 959995 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 230201146500 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 230197694500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 230201146500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -62,7 +62,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 230197694500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 230201146500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -92,7 +92,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 230197694500 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 230201146500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -122,7 +122,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 230197694500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 230201146500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -153,8 +153,8 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 230197694500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 460395389 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 230201146500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 460402293 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 171842484 # Number of instructions committed @@ -175,7 +175,7 @@ system.cpu.num_mem_refs 40540779 # nu system.cpu.num_load_insts 27896144 # Number of load instructions system.cpu.num_store_insts 12644635 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 460395388.998000 # Number of busy cycles +system.cpu.num_busy_cycles 460402292.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 40300312 # Number of branches fetched @@ -214,16 +214,16 @@ system.cpu.op_class::MemWrite 12644635 6.96% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 181650743 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 230197694500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 230201146500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 40 # number of replacements -system.cpu.dcache.tags.tagsinuse 1363.571253 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 1363.564425 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 40162626 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 1789 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 22449.762996 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1363.571253 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.332903 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.332903 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 1363.564425 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.332901 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.332901 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 1749 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 14 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 21 # Occupied blocks per task id @@ -233,7 +233,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::4 1345 system.cpu.dcache.tags.occ_task_id_percent::1024 0.427002 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 80330619 # Number of tag accesses system.cpu.dcache.tags.data_accesses 80330619 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 230197694500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 230201146500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 27754163 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 27754163 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 12363187 # number of WriteReq hits @@ -258,14 +258,14 @@ system.cpu.dcache.demand_misses::cpu.data 1788 # n system.cpu.dcache.demand_misses::total 1788 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 1789 # number of overall misses system.cpu.dcache.overall_misses::total 1789 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 39940000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 39940000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 67838500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 67838500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 107778500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 107778500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 107778500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 107778500 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 40571000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 40571000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 68930500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 68930500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 109501500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 109501500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 109501500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 109501500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 27754851 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 27754851 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) @@ -290,14 +290,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000045 system.cpu.dcache.demand_miss_rate::total 0.000045 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000045 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000045 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 58052.325581 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 58052.325581 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61671.363636 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 61671.363636 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 60278.803132 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 60278.803132 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 60245.108999 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 60245.108999 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 58969.476744 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 58969.476744 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62664.090909 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 62664.090909 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 61242.449664 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 61242.449664 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 61208.216881 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 61208.216881 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -316,16 +316,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 1788 system.cpu.dcache.demand_mshr_misses::total 1788 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 1789 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 1789 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 39252000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 39252000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 66738500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 66738500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 61000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 61000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 105990500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 105990500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 106051500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 106051500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 39883000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 39883000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 67830500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 67830500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 62000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 62000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 107713500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 107713500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 107775500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 107775500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000025 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000089 # mshr miss rate for WriteReq accesses @@ -336,26 +336,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000045 system.cpu.dcache.demand_mshr_miss_rate::total 0.000045 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000045 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000045 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 57052.325581 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 57052.325581 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 60671.363636 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 60671.363636 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 61000 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 61000 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 59278.803132 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 59278.803132 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 59279.765232 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 59279.765232 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 230197694500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 57969.476744 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 57969.476744 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61664.090909 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61664.090909 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 62000 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 62000 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 60242.449664 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 60242.449664 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 60243.432085 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 60243.432085 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 230201146500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 1506 # number of replacements -system.cpu.icache.tags.tagsinuse 1147.958164 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1147.953271 # Cycle average of tags in use system.cpu.icache.tags.total_refs 189857002 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 3051 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 62227.794821 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1147.958164 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.560526 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.560526 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1147.953271 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.560524 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.560524 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1545 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 21 # Occupied blocks per task id @@ -365,7 +365,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 942 system.cpu.icache.tags.occ_task_id_percent::1024 0.754395 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 379723157 # Number of tag accesses system.cpu.icache.tags.data_accesses 379723157 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 230197694500 # Cumulative time (in ticks) in various power states +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 230201146500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 189857002 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 189857002 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 189857002 # number of demand (read+write) hits @@ -378,12 +378,12 @@ system.cpu.icache.demand_misses::cpu.inst 3051 # n system.cpu.icache.demand_misses::total 3051 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 3051 # number of overall misses system.cpu.icache.overall_misses::total 3051 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 124592000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 124592000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 124592000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 124592000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 124592000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 124592000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 126321000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 126321000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 126321000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 126321000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 126321000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 126321000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 189860053 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 189860053 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 189860053 # number of demand (read+write) accesses @@ -396,12 +396,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000016 system.cpu.icache.demand_miss_rate::total 0.000016 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000016 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000016 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 40836.447067 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 40836.447067 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 40836.447067 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 40836.447067 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 40836.447067 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 40836.447067 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 41403.146509 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 41403.146509 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 41403.146509 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 41403.146509 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 41403.146509 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 41403.146509 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -416,48 +416,46 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 3051 system.cpu.icache.demand_mshr_misses::total 3051 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 3051 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 3051 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 121541000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 121541000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 121541000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 121541000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 121541000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 121541000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 123270000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 123270000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 123270000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 123270000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 123270000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 123270000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000016 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000016 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000016 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 39836.447067 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 39836.447067 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 39836.447067 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 39836.447067 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 39836.447067 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 39836.447067 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 230197694500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 40403.146509 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 40403.146509 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 40403.146509 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 40403.146509 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 40403.146509 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 40403.146509 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 230201146500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 1675.610098 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 2846 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 2369 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 1.201351 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 2511.620011 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 2869 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 3453 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.830872 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 3.037805 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1169.001518 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 503.570775 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.000093 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1168.996513 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 1342.623498 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.035675 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.015368 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.051136 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 2369 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 18 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 320 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 322 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 1679 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.072296 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 54045 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 54045 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 230197694500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.occ_percent::cpu.data 0.040974 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.076649 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 3453 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 29 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 30 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 341 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 536 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2517 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.105377 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 54029 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 54029 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 230201146500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 16 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 16 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 1448 # number of WritebackClean hits @@ -486,18 +484,18 @@ system.cpu.l2cache.demand_misses::total 3453 # nu system.cpu.l2cache.overall_misses::cpu.inst 1729 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 1724 # number of overall misses system.cpu.l2cache.overall_misses::total 3453 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 65004500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 65004500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 102968000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 102968000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 37629500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 37629500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 102968000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 102634000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 205602000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 102968000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 102634000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 205602000 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 66096500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 66096500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 104697000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 104697000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 38261500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 38261500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 104697000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 104358000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 209055000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 104697000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 104358000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 209055000 # number of overall miss cycles system.cpu.l2cache.WritebackDirty_accesses::writebacks 16 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackDirty_accesses::total 16 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::writebacks 1448 # number of WritebackClean accesses(hits+misses) @@ -526,18 +524,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.713430 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.566699 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.963667 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.713430 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59527.930403 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59527.930403 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59553.499132 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59553.499132 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59540.348101 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59540.348101 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59553.499132 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59532.482599 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 59543.006082 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59553.499132 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59532.482599 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 59543.006082 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60527.930403 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60527.930403 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60553.499132 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60553.499132 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60540.348101 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60540.348101 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60553.499132 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60532.482599 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 60543.006082 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60553.499132 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60532.482599 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 60543.006082 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -556,18 +554,18 @@ system.cpu.l2cache.demand_mshr_misses::total 3453 system.cpu.l2cache.overall_mshr_misses::cpu.inst 1729 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 1724 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 3453 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 54084500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 54084500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 85678000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 85678000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 31309500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 31309500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 85678000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 85394000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 171072000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 85678000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 85394000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 171072000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 55176500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 55176500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 87407000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 87407000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 31941500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 31941500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 87407000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 87118000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 174525000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 87407000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 87118000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 174525000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.992727 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.992727 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.566699 # mshr miss rate for ReadCleanReq accesses @@ -580,25 +578,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.713430 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.566699 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.963667 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.713430 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49527.930403 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49527.930403 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49553.499132 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49553.499132 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49540.348101 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49540.348101 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49553.499132 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49532.482599 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49543.006082 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49553.499132 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49532.482599 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49543.006082 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50527.930403 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50527.930403 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50553.499132 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50553.499132 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50540.348101 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50540.348101 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50553.499132 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50532.482599 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50543.006082 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50553.499132 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50532.482599 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50543.006082 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 6386 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 1644 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 64 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 230197694500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 230201146500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 3740 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 16 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 1506 # Transaction distribution @@ -632,7 +630,13 @@ system.cpu.toL2Bus.respLayer0.occupancy 4576500 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 2683500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 230197694500 # Cumulative time (in ticks) in various power states +system.membus.snoop_filter.tot_requests 3453 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 230201146500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 2361 # Transaction distribution system.membus.trans_dist::ReadExReq 1092 # Transaction distribution system.membus.trans_dist::ReadExResp 1092 # Transaction distribution diff --git a/tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt b/tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt index 8e1219235..d03b1694b 100644 --- a/tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.096723 # Nu sim_ticks 96722945000 # Number of ticks simulated final_tick 96722945000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2018052 # Simulator instruction rate (inst/s) -host_op_rate 2018054 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1009032749 # Simulator tick rate (ticks/s) -host_mem_usage 243964 # Number of bytes of host memory used -host_seconds 95.86 # Real time elapsed on the host +host_inst_rate 2512744 # Simulator instruction rate (inst/s) +host_op_rate 2512747 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1256380653 # Simulator tick rate (ticks/s) +host_mem_usage 246048 # Number of bytes of host memory used +host_seconds 76.99 # Real time elapsed on the host sim_insts 193444518 # Number of instructions simulated sim_ops 193444756 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -100,6 +100,12 @@ system.cpu.op_class::MemWrite 18998867 9.82% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 193445773 # Class of executed instruction +system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.pwrStateResidencyTicks::UNDEFINED 96722945000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 251180603 # Transaction distribution system.membus.trans_dist::ReadResp 251180603 # Transaction distribution @@ -116,14 +122,14 @@ system.membus.pkt_size::total 1069490213 # Cu system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) system.membus.snoop_fanout::samples 270179448 # Request fanout histogram -system.membus.snoop_fanout::mean 0.715989 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.450942 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 76733913 28.40% 28.40% # Request fanout histogram -system.membus.snoop_fanout::1 193445535 71.60% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 270179448 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 270179448 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt index 68f4496ce..5920b739e 100644 --- a/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.270600 # Number of seconds simulated -sim_ticks 270599529500 # Number of ticks simulated -final_tick 270599529500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.270605 # Number of seconds simulated +sim_ticks 270604702500 # Number of ticks simulated +final_tick 270604702500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1216795 # Simulator instruction rate (inst/s) -host_op_rate 1216796 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1702111428 # Simulator tick rate (ticks/s) -host_mem_usage 252676 # Number of bytes of host memory used -host_seconds 158.98 # Real time elapsed on the host +host_inst_rate 1707855 # Simulator instruction rate (inst/s) +host_op_rate 1707857 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2389075229 # Simulator tick rate (ticks/s) +host_mem_usage 256284 # Number of bytes of host memory used +host_seconds 113.27 # Real time elapsed on the host sim_insts 193444518 # Number of instructions simulated sim_ops 193444756 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 270599529500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 270604702500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 230208 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 100864 # Number of bytes read from this memory system.physmem.bytes_read::total 331072 # Number of bytes read from this memory @@ -22,19 +22,19 @@ system.physmem.bytes_inst_read::total 230208 # Nu system.physmem.num_reads::cpu.inst 3597 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 1576 # Number of read requests responded to by this memory system.physmem.num_reads::total 5173 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 850733 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 372743 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1223476 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 850733 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 850733 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 850733 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 372743 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1223476 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 270599529500 # Cumulative time (in ticks) in various power states +system.physmem.bw_read::cpu.inst 850717 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 372736 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1223453 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 850717 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 850717 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 850717 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 372736 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1223453 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 270604702500 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.workload.num_syscalls 401 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 270599529500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 541199059 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 270604702500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 541209405 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 193444518 # Number of instructions committed @@ -53,7 +53,7 @@ system.cpu.num_mem_refs 76733958 # nu system.cpu.num_load_insts 57735091 # Number of load instructions system.cpu.num_store_insts 18998867 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 541199058.998000 # Number of busy cycles +system.cpu.num_busy_cycles 541209404.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 15132745 # Number of branches fetched @@ -92,16 +92,16 @@ system.cpu.op_class::MemWrite 18998867 9.82% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 193445773 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 270599529500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 270604702500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 2 # number of replacements -system.cpu.dcache.tags.tagsinuse 1237.159344 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 1237.152973 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 76732337 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 1576 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 48688.031091 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1237.159344 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.302041 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.302041 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 1237.152973 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.302039 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.302039 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 1574 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 5 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id @@ -111,7 +111,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::4 1237 system.cpu.dcache.tags.occ_task_id_percent::1024 0.384277 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 153469402 # Number of tag accesses system.cpu.dcache.tags.data_accesses 153469402 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 270599529500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 270604702500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 57734570 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 57734570 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 18975362 # number of WriteReq hits @@ -132,16 +132,16 @@ system.cpu.dcache.demand_misses::cpu.data 1575 # n system.cpu.dcache.demand_misses::total 1575 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 1575 # number of overall misses system.cpu.dcache.overall_misses::total 1575 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 30877500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 30877500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 66775000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 66775000 # number of WriteReq miss cycles -system.cpu.dcache.SwapReq_miss_latency::cpu.data 62000 # number of SwapReq miss cycles -system.cpu.dcache.SwapReq_miss_latency::total 62000 # number of SwapReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 97652500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 97652500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 97652500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 97652500 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 31375500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 31375500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 67852000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 67852000 # number of WriteReq miss cycles +system.cpu.dcache.SwapReq_miss_latency::cpu.data 63000 # number of SwapReq miss cycles +system.cpu.dcache.SwapReq_miss_latency::total 63000 # number of SwapReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 99227500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 99227500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 99227500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 99227500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 57735068 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 57735068 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 18976439 # number of WriteReq accesses(hits+misses) @@ -162,16 +162,16 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000021 system.cpu.dcache.demand_miss_rate::total 0.000021 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000021 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000021 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62003.012048 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 62003.012048 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62000.928505 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 62000.928505 # average WriteReq miss latency -system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 62000 # average SwapReq miss latency -system.cpu.dcache.SwapReq_avg_miss_latency::total 62000 # average SwapReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 62001.587302 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 62001.587302 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 62001.587302 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 62001.587302 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63003.012048 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 63003.012048 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63000.928505 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 63000.928505 # average WriteReq miss latency +system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 63000 # average SwapReq miss latency +system.cpu.dcache.SwapReq_avg_miss_latency::total 63000 # average SwapReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 63001.587302 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 63001.587302 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 63001.587302 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 63001.587302 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -190,16 +190,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 1575 system.cpu.dcache.demand_mshr_misses::total 1575 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 1575 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 1575 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 30379500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 30379500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 65698000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 65698000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 61000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.SwapReq_mshr_miss_latency::total 61000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 96077500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 96077500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 96077500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 96077500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 30877500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 30877500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 66775000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 66775000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 62000 # number of SwapReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency::total 62000 # number of SwapReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 97652500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 97652500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 97652500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 97652500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000009 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000057 # mshr miss rate for WriteReq accesses @@ -210,26 +210,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000021 system.cpu.dcache.demand_mshr_miss_rate::total 0.000021 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000021 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000021 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61003.012048 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61003.012048 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61000.928505 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61000.928505 # average WriteReq mshr miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 61000 # average SwapReq mshr miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 61000 # average SwapReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 61001.587302 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 61001.587302 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61001.587302 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 61001.587302 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 270599529500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 62003.012048 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 62003.012048 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62000.928505 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62000.928505 # average WriteReq mshr miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 62000 # average SwapReq mshr miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 62000 # average SwapReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 62001.587302 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 62001.587302 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 62001.587302 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 62001.587302 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 270604702500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 10362 # number of replacements -system.cpu.icache.tags.tagsinuse 1591.528232 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1591.520958 # Cycle average of tags in use system.cpu.icache.tags.total_refs 193433248 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 12288 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 15741.638021 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1591.528232 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.777113 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.777113 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1591.520958 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.777110 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.777110 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1926 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 50 # Occupied blocks per task id @@ -239,7 +239,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 687 system.cpu.icache.tags.occ_task_id_percent::1024 0.940430 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 386903360 # Number of tag accesses system.cpu.icache.tags.data_accesses 386903360 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 270599529500 # Cumulative time (in ticks) in various power states +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 270604702500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 193433248 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 193433248 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 193433248 # number of demand (read+write) hits @@ -252,12 +252,12 @@ system.cpu.icache.demand_misses::cpu.inst 12288 # n system.cpu.icache.demand_misses::total 12288 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 12288 # number of overall misses system.cpu.icache.overall_misses::total 12288 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 336231000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 336231000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 336231000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 336231000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 336231000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 336231000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 339828000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 339828000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 339828000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 339828000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 339828000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 339828000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 193445536 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 193445536 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 193445536 # number of demand (read+write) accesses @@ -270,12 +270,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000064 system.cpu.icache.demand_miss_rate::total 0.000064 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000064 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000064 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27362.548828 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 27362.548828 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 27362.548828 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 27362.548828 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 27362.548828 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 27362.548828 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27655.273438 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 27655.273438 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 27655.273438 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 27655.273438 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 27655.273438 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 27655.273438 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -290,48 +290,46 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 12288 system.cpu.icache.demand_mshr_misses::total 12288 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 12288 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 12288 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 323943000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 323943000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 323943000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 323943000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 323943000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 323943000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 327540000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 327540000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 327540000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 327540000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 327540000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 327540000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000064 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000064 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000064 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000064 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000064 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000064 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 26362.548828 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 26362.548828 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 26362.548828 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 26362.548828 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 26362.548828 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 26362.548828 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 270599529500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 26655.273438 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 26655.273438 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 26655.273438 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 26655.273438 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 26655.273438 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 26655.273438 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 270604702500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 2678.246108 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 19053 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 4097 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 4.650476 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 3512.345683 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 19055 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 5173 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 3.683549 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 0.000456 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2275.203530 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 403.042121 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.000000 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.069434 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.012300 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.081734 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 4097 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2275.192191 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 1237.153491 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.069433 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.037755 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.107188 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 5173 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 40 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 700 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 625 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2688 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.125031 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 198999 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 198999 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 270599529500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 54 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 719 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 833 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3523 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.157867 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 198997 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 198997 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 270604702500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 2 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 2 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 10362 # number of WritebackClean hits @@ -354,18 +352,18 @@ system.cpu.l2cache.demand_misses::total 5173 # nu system.cpu.l2cache.overall_misses::cpu.inst 3597 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 1576 # number of overall misses system.cpu.l2cache.overall_misses::total 5173 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 64142000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 64142000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 214049500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 214049500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 29632000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 29632000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 214049500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 93774000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 307823500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 214049500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 93774000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 307823500 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 65220000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 65220000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 217646500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 217646500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 30130000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 30130000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 217646500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 95350000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 312996500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 217646500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 95350000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 312996500 # number of overall miss cycles system.cpu.l2cache.WritebackDirty_accesses::writebacks 2 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackDirty_accesses::total 2 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::writebacks 10362 # number of WritebackClean accesses(hits+misses) @@ -394,18 +392,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.373125 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.292725 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.373125 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500.927644 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500.927644 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59507.784265 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59507.784265 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59502.008032 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59502.008032 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59507.784265 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59501.269036 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 59505.799343 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59507.784265 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59501.269036 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 59505.799343 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500.927644 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500.927644 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60507.784265 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60507.784265 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60502.008032 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60502.008032 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60507.784265 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60501.269036 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 60505.799343 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60507.784265 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60501.269036 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 60505.799343 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -424,18 +422,18 @@ system.cpu.l2cache.demand_mshr_misses::total 5173 system.cpu.l2cache.overall_mshr_misses::cpu.inst 3597 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 1576 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 5173 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 53362000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 53362000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 178079500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 178079500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 24652000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 24652000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 178079500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 78014000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 256093500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 178079500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 78014000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 256093500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 54440000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 54440000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 181676500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 181676500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 25150000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 25150000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 181676500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 79590000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 261266500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 181676500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 79590000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 261266500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.292725 # mshr miss rate for ReadCleanReq accesses @@ -448,25 +446,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.373125 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.292725 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.373125 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500.927644 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500.927644 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49507.784265 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49507.784265 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49502.008032 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49502.008032 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49507.784265 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49501.269036 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49505.799343 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49507.784265 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49501.269036 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49505.799343 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500.927644 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500.927644 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50507.784265 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50507.784265 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50502.008032 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50502.008032 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50507.784265 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50501.269036 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50505.799343 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50507.784265 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50501.269036 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50505.799343 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 24228 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 10365 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 270599529500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 270604702500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 12786 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 2 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 10362 # Transaction distribution @@ -499,7 +497,13 @@ system.cpu.toL2Bus.respLayer0.occupancy 18432000 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 2364000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 270599529500 # Cumulative time (in ticks) in various power states +system.membus.snoop_filter.tot_requests 5173 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 270604702500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 4095 # Transaction distribution system.membus.trans_dist::ReadExReq 1078 # Transaction distribution system.membus.trans_dist::ReadExResp 1078 # Transaction distribution diff --git a/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt b/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt index d9da66da0..24b1a8bcb 100644 --- a/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.131393 # Nu sim_ticks 131393279000 # Number of ticks simulated final_tick 131393279000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 762262 # Simulator instruction rate (inst/s) -host_op_rate 1277621 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 758349320 # Simulator tick rate (ticks/s) -host_mem_usage 285232 # Number of bytes of host memory used -host_seconds 173.26 # Real time elapsed on the host +host_inst_rate 1175193 # Simulator instruction rate (inst/s) +host_op_rate 1969730 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1169160517 # Simulator tick rate (ticks/s) +host_mem_usage 289616 # Number of bytes of host memory used +host_seconds 112.38 # Real time elapsed on the host sim_insts 132071193 # Number of instructions simulated sim_ops 221363385 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -104,6 +104,12 @@ system.cpu.op_class::MemWrite 20515717 9.27% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 221363385 # Class of executed instruction +system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.pwrStateResidencyTicks::UNDEFINED 131393279000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 230176372 # Transaction distribution system.membus.trans_dist::ReadResp 230176372 # Transaction distribution @@ -122,14 +128,14 @@ system.membus.pkt_size::total 1798200879 # Cu system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) system.membus.snoop_fanout::samples 250692103 # Request fanout histogram -system.membus.snoop_fanout::mean 0.692062 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.461641 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 77197736 30.79% 30.79% # Request fanout histogram -system.membus.snoop_fanout::1 173494367 69.21% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 250692103 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 250692103 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/stats.txt b/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/stats.txt index 1f70ed165..180cfa389 100644 --- a/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.250987 # Number of seconds simulated -sim_ticks 250987138500 # Number of ticks simulated -final_tick 250987138500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.250992 # Number of seconds simulated +sim_ticks 250991873500 # Number of ticks simulated +final_tick 250991873500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 493662 # Simulator instruction rate (inst/s) -host_op_rate 827423 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 938152393 # Simulator tick rate (ticks/s) -host_mem_usage 294200 # Number of bytes of host memory used -host_seconds 267.53 # Real time elapsed on the host +host_inst_rate 1054537 # Simulator instruction rate (inst/s) +host_op_rate 1767501 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2004072574 # Simulator tick rate (ticks/s) +host_mem_usage 299608 # Number of bytes of host memory used +host_seconds 125.24 # Real time elapsed on the host sim_insts 132071193 # Number of instructions simulated sim_ops 221363385 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 250987138500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 250991873500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 181760 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 121280 # Number of bytes read from this memory system.physmem.bytes_read::total 303040 # Number of bytes read from this memory @@ -22,23 +22,23 @@ system.physmem.bytes_inst_read::total 181760 # Nu system.physmem.num_reads::cpu.inst 2840 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 1895 # Number of read requests responded to by this memory system.physmem.num_reads::total 4735 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 724181 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 483212 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1207393 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 724181 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 724181 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 724181 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 483212 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1207393 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 250987138500 # Cumulative time (in ticks) in various power states +system.physmem.bw_read::cpu.inst 724167 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 483203 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1207370 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 724167 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 724167 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 724167 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 483203 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1207370 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 250991873500 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 250987138500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 250991873500 # Cumulative time (in ticks) in various power states system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 250987138500 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 250987138500 # Cumulative time (in ticks) in various power states +system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 250991873500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 250991873500 # Cumulative time (in ticks) in various power states system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 250987138500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 501974277 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 250991873500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 501983747 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 132071193 # Number of instructions committed @@ -59,7 +59,7 @@ system.cpu.num_mem_refs 77165304 # nu system.cpu.num_load_insts 56649587 # Number of load instructions system.cpu.num_store_insts 20515717 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 501974276.998000 # Number of busy cycles +system.cpu.num_busy_cycles 501983746.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 12326938 # Number of branches fetched @@ -98,16 +98,16 @@ system.cpu.op_class::MemWrite 20515717 9.27% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 221363385 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 250987138500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 250991873500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 41 # number of replacements -system.cpu.dcache.tags.tagsinuse 1363.414730 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 1363.408611 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 77195831 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 1905 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 40522.745932 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1363.414730 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.332865 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.332865 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 1363.408611 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.332863 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.332863 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 1864 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 7 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id @@ -117,7 +117,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::4 1328 system.cpu.dcache.tags.occ_task_id_percent::1024 0.455078 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 154397377 # Number of tag accesses system.cpu.dcache.tags.data_accesses 154397377 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 250987138500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 250991873500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 56681678 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 56681678 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 20514153 # number of WriteReq hits @@ -134,14 +134,14 @@ system.cpu.dcache.demand_misses::cpu.data 1905 # n system.cpu.dcache.demand_misses::total 1905 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 1905 # number of overall misses system.cpu.dcache.overall_misses::total 1905 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 19933500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 19933500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 97691000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 97691000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 117624500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 117624500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 117624500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 117624500 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 20253500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 20253500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 99266000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 99266000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 119519500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 119519500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 119519500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 119519500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 56682005 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 56682005 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 # number of WriteReq accesses(hits+misses) @@ -158,14 +158,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000025 system.cpu.dcache.demand_miss_rate::total 0.000025 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000025 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000025 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60958.715596 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 60958.715596 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61908.111534 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 61908.111534 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 61745.144357 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 61745.144357 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 61745.144357 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 61745.144357 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 61937.308869 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 61937.308869 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62906.210393 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 62906.210393 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 62739.895013 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 62739.895013 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 62739.895013 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 62739.895013 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -182,14 +182,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 1905 system.cpu.dcache.demand_mshr_misses::total 1905 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 1905 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 1905 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 19606500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 19606500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 96113000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 96113000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 115719500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 115719500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 115719500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 115719500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 19926500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 19926500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 97688000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 97688000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 117614500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 117614500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 117614500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 117614500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000006 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000006 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000077 # mshr miss rate for WriteReq accesses @@ -198,34 +198,34 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 59958.715596 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 59958.715596 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 60908.111534 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 60908.111534 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 60745.144357 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 60745.144357 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 60745.144357 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 60745.144357 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 250987138500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 60937.308869 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 60937.308869 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61906.210393 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61906.210393 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 61739.895013 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 61739.895013 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61739.895013 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 61739.895013 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 250991873500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 2836 # number of replacements -system.cpu.icache.tags.tagsinuse 1455.245085 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1455.237724 # Cycle average of tags in use system.cpu.icache.tags.total_refs 173489673 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 4694 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 36959.879207 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1455.245085 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.710569 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.710569 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1455.237724 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.710565 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.710565 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1858 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 60 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 477 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 415 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 470 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 422 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 869 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.907227 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 346993428 # Number of tag accesses system.cpu.icache.tags.data_accesses 346993428 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 250987138500 # Cumulative time (in ticks) in various power states +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 250991873500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 173489673 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 173489673 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 173489673 # number of demand (read+write) hits @@ -238,12 +238,12 @@ system.cpu.icache.demand_misses::cpu.inst 4694 # n system.cpu.icache.demand_misses::total 4694 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 4694 # number of overall misses system.cpu.icache.overall_misses::total 4694 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 200232500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 200232500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 200232500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 200232500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 200232500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 200232500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 203072500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 203072500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 203072500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 203072500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 203072500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 203072500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 173494367 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 173494367 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 173494367 # number of demand (read+write) accesses @@ -256,12 +256,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000027 system.cpu.icache.demand_miss_rate::total 0.000027 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000027 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000027 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42657.115467 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 42657.115467 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 42657.115467 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 42657.115467 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 42657.115467 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 42657.115467 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 43262.143161 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 43262.143161 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 43262.143161 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 43262.143161 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 43262.143161 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 43262.143161 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -276,48 +276,46 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 4694 system.cpu.icache.demand_mshr_misses::total 4694 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 4694 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 4694 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 195538500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 195538500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 195538500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 195538500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 195538500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 195538500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 198378500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 198378500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 198378500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 198378500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 198378500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 198378500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000027 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 41657.115467 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 41657.115467 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 41657.115467 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 41657.115467 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 41657.115467 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 41657.115467 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 250987138500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 42262.143161 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 42262.143161 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 42262.143161 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 42262.143161 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 42262.143161 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 42262.143161 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 250991873500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 2058.105553 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 4732 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 3164 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 1.495575 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 3195.628328 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 4741 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 4735 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 1.001267 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 0.021821 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1829.911143 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 228.172589 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.000001 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1829.901516 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 1365.726812 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.055844 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.006963 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.062808 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 3164 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 33 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 497 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 532 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2064 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.096558 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 80550 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 80550 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 250987138500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.occ_percent::cpu.data 0.041679 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.097523 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 4735 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 39 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 512 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 947 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3200 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.144501 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 80543 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 80543 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 250991873500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 7 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 7 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 2836 # number of WritebackClean hits @@ -346,18 +344,18 @@ system.cpu.l2cache.demand_misses::total 4735 # nu system.cpu.l2cache.overall_misses::cpu.inst 2840 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 1895 # number of overall misses system.cpu.l2cache.overall_misses::total 4735 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 93713500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 93713500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 169013000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 169013000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 19042000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 19042000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 169013000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 112755500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 281768500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 169013000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 112755500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 281768500 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 95288500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 95288500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 171853000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 171853000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 19362000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 19362000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 171853000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 114650500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 286503500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 171853000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 114650500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 286503500 # number of overall miss cycles system.cpu.l2cache.WritebackDirty_accesses::writebacks 7 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackDirty_accesses::total 7 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::writebacks 2836 # number of WritebackClean accesses(hits+misses) @@ -386,18 +384,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.717533 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.605028 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.994751 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.717533 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500.634921 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500.634921 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59511.619718 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59511.619718 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59506.250000 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59506.250000 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59511.619718 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59501.583113 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 59507.602957 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59511.619718 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59501.583113 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 59507.602957 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500.634921 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500.634921 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60511.619718 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60511.619718 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60506.250000 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60506.250000 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60511.619718 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60501.583113 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 60507.602957 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60511.619718 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60501.583113 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 60507.602957 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -416,18 +414,18 @@ system.cpu.l2cache.demand_mshr_misses::total 4735 system.cpu.l2cache.overall_mshr_misses::cpu.inst 2840 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 1895 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 4735 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 77963500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 77963500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 140613000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 140613000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 15842000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 15842000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 140613000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 93805500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 234418500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 140613000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 93805500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 234418500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 79538500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 79538500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 143453000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 143453000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 16162000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 16162000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 143453000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 95700500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 239153500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 143453000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 95700500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 239153500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.998099 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.998099 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.605028 # mshr miss rate for ReadCleanReq accesses @@ -440,25 +438,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.717533 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.605028 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.994751 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.717533 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500.634921 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500.634921 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49511.619718 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49511.619718 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49506.250000 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49506.250000 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49511.619718 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49501.583113 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49507.602957 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49511.619718 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49501.583113 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49507.602957 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500.634921 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500.634921 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50511.619718 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50511.619718 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50506.250000 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50506.250000 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50511.619718 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50501.583113 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50507.602957 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50511.619718 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50501.583113 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50507.602957 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 9476 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 2878 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 250987138500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 250991873500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 5021 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 7 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 2836 # Transaction distribution @@ -492,7 +490,13 @@ system.cpu.toL2Bus.respLayer0.occupancy 7041000 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 2857500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 250987138500 # Cumulative time (in ticks) in various power states +system.membus.snoop_filter.tot_requests 4735 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 250991873500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 3160 # Transaction distribution system.membus.trans_dist::ReadExReq 1575 # Transaction distribution system.membus.trans_dist::ReadExResp 1575 # Transaction distribution |