diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2016-04-09 12:13:40 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2016-04-09 12:13:40 -0400 |
| commit | d9193d1b2039739ef4fb264c742d37f9803817e5 (patch) | |
| tree | 7904829173102a8d8f654873d5cefb790e148298 /tests/quick/se | |
| parent | 1d61224a8ba60a2c8cb06e9877b7e548d47bb99a (diff) | |
| download | gem5-d9193d1b2039739ef4fb264c742d37f9803817e5.tar.xz | |
stats: Match current behaviour
Small changes to the branch predictor and BTB caused stats changes
throughout.
Diffstat (limited to 'tests/quick/se')
3 files changed, 2439 insertions, 2409 deletions
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt index d32749ad1..39184c503 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000038 # Number of seconds simulated -sim_ticks 37629000 # Number of ticks simulated -final_tick 37629000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000037 # Number of seconds simulated +sim_ticks 37494000 # Number of ticks simulated +final_tick 37494000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 36642 # Simulator instruction rate (inst/s) -host_op_rate 36638 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 214955628 # Simulator tick rate (ticks/s) -host_mem_usage 227692 # Number of bytes of host memory used -host_seconds 0.18 # Real time elapsed on the host +host_inst_rate 257461 # Simulator instruction rate (inst/s) +host_op_rate 257361 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1504149892 # Simulator tick rate (ticks/s) +host_mem_usage 252900 # Number of bytes of host memory used +host_seconds 0.03 # Real time elapsed on the host sim_insts 6413 # Number of instructions simulated sim_ops 6413 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt index 15e66dc76..69eab7f94 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000023 # Nu sim_ticks 22532000 # Number of ticks simulated final_tick 22532000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 22135 # Simulator instruction rate (inst/s) -host_op_rate 22134 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 99411388 # Simulator tick rate (ticks/s) -host_mem_usage 226732 # Number of bytes of host memory used -host_seconds 0.23 # Real time elapsed on the host +host_inst_rate 106399 # Simulator instruction rate (inst/s) +host_op_rate 106364 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 479269632 # Simulator tick rate (ticks/s) +host_mem_usage 251364 # Number of bytes of host memory used +host_seconds 0.05 # Real time elapsed on the host sim_insts 4999 # Number of instructions simulated sim_ops 4999 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -889,10 +889,10 @@ system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 22234500 system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6512000 # number of ReadSharedReq MSHR miss cycles system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 6512000 # number of ReadSharedReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22234500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10019000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10019000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::total 32253500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22234500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10019000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10019000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::total 32253500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses @@ -933,7 +933,7 @@ system.cpu.toL2Bus.trans_dist::ReadCleanReq 332 # system.cpu.toL2Bus.trans_dist::ReadSharedReq 90 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 681 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 280 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 959 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 961 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 22336 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8960 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size::total 31296 # Cumulative packet size per connected master and slave (bytes) @@ -959,9 +959,9 @@ system.membus.trans_dist::ReadResp 419 # Tr system.membus.trans_dist::ReadExReq 50 # Transaction distribution system.membus.trans_dist::ReadExResp 50 # Transaction distribution system.membus.trans_dist::ReadSharedReq 419 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 936 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 938 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 938 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 29952 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30016 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size::total 30016 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoop_fanout::samples 469 # Request fanout histogram diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt index 79e5e5930..a8bc405b3 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt @@ -1,92 +1,92 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000108 # Number of seconds simulated -sim_ticks 107700000 # Number of ticks simulated -final_tick 107700000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000126 # Number of seconds simulated +sim_ticks 125889000 # Number of ticks simulated +final_tick 125889000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 68250 # Simulator instruction rate (inst/s) -host_op_rate 68250 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 7391011 # Simulator tick rate (ticks/s) -host_mem_usage 243816 # Number of bytes of host memory used -host_seconds 14.57 # Real time elapsed on the host -sim_insts 994522 # Number of instructions simulated -sim_ops 994522 # Number of ops (including micro ops) simulated +host_inst_rate 271253 # Simulator instruction rate (inst/s) +host_op_rate 271253 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 29155299 # Simulator tick rate (ticks/s) +host_mem_usage 267160 # Number of bytes of host memory used +host_seconds 4.32 # Real time elapsed on the host +sim_insts 1171234 # Number of instructions simulated +sim_ops 1171234 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.inst 23040 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 10816 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 5248 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 1280 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 384 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 832 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.inst 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.data 832 # Number of bytes read from this memory -system.physmem.bytes_read::total 42560 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 23040 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 5248 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 384 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu3.inst 128 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 28800 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu0.inst 360 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 169 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 82 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 20 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 6 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 13 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.inst 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.data 13 # Number of read requests responded to by this memory -system.physmem.num_reads::total 665 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu0.inst 213927577 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 100427112 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 48727948 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 11884865 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 3565460 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 7725162 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.inst 1188487 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.data 7725162 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 395171773 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 213927577 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 48727948 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 3565460 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu3.inst 1188487 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 267409471 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 213927577 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 100427112 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 48727948 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 11884865 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 3565460 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 7725162 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.inst 1188487 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.data 7725162 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 395171773 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 666 # Number of read requests accepted +system.physmem.bytes_read::cpu0.inst 24000 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 10880 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 1536 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 896 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 5824 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 1344 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.inst 256 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.data 960 # Number of bytes read from this memory +system.physmem.bytes_read::total 45696 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 24000 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 1536 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 5824 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu3.inst 256 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 31616 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu0.inst 375 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 170 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 24 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 14 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 91 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 21 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.inst 4 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.data 15 # Number of read requests responded to by this memory +system.physmem.num_reads::total 714 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu0.inst 190644139 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 86425343 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 12201225 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 7117381 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 46262978 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 10676072 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.inst 2033537 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.data 7625766 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 362986440 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 190644139 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 12201225 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 46262978 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu3.inst 2033537 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 251141879 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 190644139 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 86425343 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 12201225 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 7117381 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 46262978 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 10676072 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.inst 2033537 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.data 7625766 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 362986440 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 714 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 666 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 714 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 42624 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 45696 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 42624 # Total read bytes from the system interface side +system.physmem.bytesReadSys 45696 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 114 # Per bank write bursts -system.physmem.perBankRdBursts::1 42 # Per bank write bursts -system.physmem.perBankRdBursts::2 30 # Per bank write bursts -system.physmem.perBankRdBursts::3 60 # Per bank write bursts -system.physmem.perBankRdBursts::4 66 # Per bank write bursts -system.physmem.perBankRdBursts::5 27 # Per bank write bursts -system.physmem.perBankRdBursts::6 18 # Per bank write bursts -system.physmem.perBankRdBursts::7 24 # Per bank write bursts +system.physmem.perBankRdBursts::0 120 # Per bank write bursts +system.physmem.perBankRdBursts::1 45 # Per bank write bursts +system.physmem.perBankRdBursts::2 34 # Per bank write bursts +system.physmem.perBankRdBursts::3 62 # Per bank write bursts +system.physmem.perBankRdBursts::4 68 # Per bank write bursts +system.physmem.perBankRdBursts::5 28 # Per bank write bursts +system.physmem.perBankRdBursts::6 19 # Per bank write bursts +system.physmem.perBankRdBursts::7 28 # Per bank write bursts system.physmem.perBankRdBursts::8 7 # Per bank write bursts -system.physmem.perBankRdBursts::9 28 # Per bank write bursts +system.physmem.perBankRdBursts::9 31 # Per bank write bursts system.physmem.perBankRdBursts::10 23 # Per bank write bursts system.physmem.perBankRdBursts::11 13 # Per bank write bursts -system.physmem.perBankRdBursts::12 61 # Per bank write bursts -system.physmem.perBankRdBursts::13 38 # Per bank write bursts -system.physmem.perBankRdBursts::14 18 # Per bank write bursts -system.physmem.perBankRdBursts::15 97 # Per bank write bursts +system.physmem.perBankRdBursts::12 69 # Per bank write bursts +system.physmem.perBankRdBursts::13 47 # Per bank write bursts +system.physmem.perBankRdBursts::14 19 # Per bank write bursts +system.physmem.perBankRdBursts::15 101 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts system.physmem.perBankWrBursts::2 0 # Per bank write bursts @@ -105,14 +105,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 107672000 # Total gap between requests +system.physmem.totGap 125655000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 666 # Read request sizes (log2) +system.physmem.readPktSize::6 714 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -120,10 +120,10 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 396 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 199 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 431 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 209 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 54 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 13 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 16 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -216,968 +216,977 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 145 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 274.537931 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 187.244268 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 251.506931 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 44 30.34% 30.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 37 25.52% 55.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 28 19.31% 75.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 11 7.59% 82.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 7 4.83% 87.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 8 5.52% 93.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 2 1.38% 94.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 3 2.07% 96.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 5 3.45% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 145 # Bytes accessed per row activation -system.physmem.totQLat 6586250 # Total ticks spent queuing -system.physmem.totMemAccLat 19073750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 3330000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9889.26 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 181 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 245.392265 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 162.885057 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 238.848920 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 70 38.67% 38.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 41 22.65% 61.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 29 16.02% 77.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 15 8.29% 85.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 9 4.97% 90.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 7 3.87% 94.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 3 1.66% 96.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2 1.10% 97.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 5 2.76% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 181 # Bytes accessed per row activation +system.physmem.totQLat 8022250 # Total ticks spent queuing +system.physmem.totMemAccLat 21409750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 3570000 # Total ticks spent in databus transfers +system.physmem.avgQLat 11235.64 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28639.26 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 395.77 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 29985.64 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 362.99 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 395.77 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 362.99 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 3.09 # Data bus utilization in percentage -system.physmem.busUtilRead 3.09 # Data bus utilization in percentage for reads +system.physmem.busUtil 2.84 # Data bus utilization in percentage +system.physmem.busUtilRead 2.84 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.29 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.25 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 510 # Number of row buffer hits during reads +system.physmem.readRowHits 529 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 76.58 # Row buffer hit rate for reads +system.physmem.readRowHitRate 74.09 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 161669.67 # Average gap between requests -system.physmem.pageHitRate 76.58 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 710640 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 387750 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 2769000 # Energy for read commands per rank (pJ) +system.physmem.avgGap 175987.39 # Average gap between requests +system.physmem.pageHitRate 74.09 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 914760 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 499125 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 3088800 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 6611280 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 38199690 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 27380250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 76058610 # Total energy per rank (pJ) -system.physmem_0.averagePower 749.484363 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 47670750 # Time in different power states -system.physmem_0.memoryStateTime::REF 3380000 # Time in different power states +system.physmem_0.refreshEnergy 8136960 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 61236810 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 21187500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 95063955 # Total energy per rank (pJ) +system.physmem_0.averagePower 761.486343 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 34878500 # Time in different power states +system.physmem_0.memoryStateTime::REF 4160000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 52812250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 85815250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 355320 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 193875 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 2028000 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 453600 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 247500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 2324400 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 6611280 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 32151420 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 32685750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 74025645 # Total energy per rank (pJ) -system.physmem_1.averagePower 729.451450 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 57549250 # Time in different power states -system.physmem_1.memoryStateTime::REF 3380000 # Time in different power states +system.physmem_1.refreshEnergy 8136960 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 43234785 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 36978750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 91375995 # Total energy per rank (pJ) +system.physmem_1.averagePower 731.944849 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 61171750 # Time in different power states +system.physmem_1.memoryStateTime::REF 4160000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 43929750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 59522000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu0.branchPred.lookups 81595 # Number of BP lookups -system.cpu0.branchPred.condPredicted 78953 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 1100 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 78929 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 76214 # Number of BTB hits +system.cpu0.branchPred.lookups 99978 # Number of BP lookups +system.cpu0.branchPred.condPredicted 95393 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 1592 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 97255 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 0 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 96.560200 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 645 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 1133 # Number of times the RAS was used to get a target. system.cpu0.branchPred.RASInCorrect 128 # Number of incorrect RAS predictions. +system.cpu0.branchPred.indirectLookups 97255 # Number of indirect predictor lookups. +system.cpu0.branchPred.indirectHits 89772 # Number of indirect target hits. +system.cpu0.branchPred.indirectMisses 7483 # Number of indirect misses. +system.cpu0.branchPredindirectMispredicted 1066 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.workload.num_syscalls 89 # Number of system calls -system.cpu0.numCycles 215401 # number of cpu cycles simulated +system.cpu0.numCycles 251779 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 19727 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 482343 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 81595 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 76859 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 165670 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 2501 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 96 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 1993 # Number of stall cycles due to pending traps -system.cpu0.fetch.CacheLines 6732 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 621 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.icacheStallCycles 22796 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 589750 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 99978 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 90905 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 197463 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 3483 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 64 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 2183 # Number of stall cycles due to pending traps +system.cpu0.fetch.IcacheWaitRetryStallCycles 8 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 8051 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 854 # Number of outstanding Icache misses that were squashed system.cpu0.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 188739 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 2.555609 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.213598 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::samples 224259 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 2.629772 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.263592 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 30459 16.14% 16.14% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 78270 41.47% 57.61% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 797 0.42% 58.03% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 1203 0.64% 58.67% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 613 0.32% 58.99% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 73671 39.03% 98.03% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 671 0.36% 98.38% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 403 0.21% 98.59% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 2652 1.41% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 34588 15.42% 15.42% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 92788 41.38% 56.80% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 690 0.31% 57.11% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 1001 0.45% 57.55% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 509 0.23% 57.78% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 88318 39.38% 97.16% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 733 0.33% 97.49% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 501 0.22% 97.71% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 5131 2.29% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 188739 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.378805 # Number of branch fetches per cycle -system.cpu0.fetch.rate 2.239279 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 15463 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 18382 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 152999 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 645 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1250 # Number of cycles decode is squashing -system.cpu0.decode.DecodedInsts 471851 # Number of instructions handled by decode -system.cpu0.rename.SquashCycles 1250 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 16060 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 2005 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 15072 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 152998 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 1354 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 468673 # Number of instructions processed by rename +system.cpu0.fetch.rateDist::total 224259 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.397086 # Number of branch fetches per cycle +system.cpu0.fetch.rate 2.342332 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 17767 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 19916 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 184006 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 829 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1741 # Number of cycles decode is squashing +system.cpu0.decode.DecodedInsts 571897 # Number of instructions handled by decode +system.cpu0.rename.SquashCycles 1741 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 18447 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 2370 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 16226 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 184143 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 1332 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 566816 # Number of instructions processed by rename system.cpu0.rename.IQFullEvents 11 # Number of times rename has blocked due to IQ full system.cpu0.rename.LQFullEvents 11 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 851 # Number of times rename has blocked due to SQ full -system.cpu0.rename.RenamedOperands 320440 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 934717 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 705961 # Number of integer rename lookups -system.cpu0.rename.CommittedMaps 307367 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 13073 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 821 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 831 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 4337 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 149926 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 75817 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 73307 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 72919 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 392051 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 889 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 388622 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 31 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 12300 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 11714 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 330 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 188739 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 2.059045 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.124370 # Number of insts issued each cycle +system.cpu0.rename.SQFullEvents 855 # Number of times rename has blocked due to SQ full +system.cpu0.rename.RenamedOperands 387804 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 1129387 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 853087 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 2 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 368443 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 19361 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 1077 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 1101 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 5304 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 180818 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 91318 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 88191 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 87908 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 472586 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1109 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 468485 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 119 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 16710 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 13548 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 550 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 224259 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 2.089035 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.110026 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 33524 17.76% 17.76% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 4207 2.23% 19.99% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 74141 39.28% 59.27% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 73776 39.09% 98.36% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 1579 0.84% 99.20% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 884 0.47% 99.67% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 404 0.21% 99.88% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 147 0.08% 99.96% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 77 0.04% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 37572 16.75% 16.75% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 4453 1.99% 18.74% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 89499 39.91% 58.65% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 89119 39.74% 98.39% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 1731 0.77% 99.16% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 984 0.44% 99.60% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 574 0.26% 99.85% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 227 0.10% 99.96% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 100 0.04% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 188739 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 224259 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 61 21.18% 21.18% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 0 0.00% 21.18% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 21.18% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 21.18% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 21.18% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 21.18% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 21.18% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 21.18% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 21.18% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 21.18% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 21.18% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 21.18% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 21.18% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 21.18% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 21.18% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 21.18% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 21.18% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 21.18% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 21.18% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 21.18% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 21.18% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 21.18% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 21.18% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 21.18% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 21.18% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 21.18% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 21.18% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 21.18% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 21.18% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 124 43.06% 64.24% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 103 35.76% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 140 42.68% 42.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 0 0.00% 42.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 42.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 42.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 42.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 42.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 42.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 42.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 42.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 42.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 42.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 42.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 42.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 42.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 42.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 42.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 42.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 42.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 42.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 42.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 42.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 42.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 42.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 42.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 42.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 42.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 42.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 42.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 42.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 69 21.04% 63.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 119 36.28% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 164274 42.27% 42.27% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.27% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.27% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.27% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.27% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.27% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.27% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.27% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.27% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 42.27% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 42.27% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 42.27% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 42.27% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 42.27% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 42.27% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 42.27% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 42.27% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 42.27% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 42.27% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 42.27% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.27% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.27% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.27% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.27% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.27% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.27% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.27% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.27% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.27% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 149282 38.41% 80.68% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 75066 19.32% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 197740 42.21% 42.21% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.21% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.21% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.21% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.21% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.21% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.21% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.21% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.21% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 42.21% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 42.21% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 42.21% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 42.21% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 42.21% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 42.21% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 42.21% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 42.21% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 42.21% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 42.21% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 42.21% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.21% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.21% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.21% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.21% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.21% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.21% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.21% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.21% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.21% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 180204 38.47% 80.67% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 90541 19.33% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 388622 # Type of FU issued -system.cpu0.iq.rate 1.804179 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 288 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.000741 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 966302 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 405302 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 386770 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.FU_type_0::total 468485 # Type of FU issued +system.cpu0.iq.rate 1.860699 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 328 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.000700 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 1161676 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 490453 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 465867 # Number of integer instruction queue wakeup accesses system.cpu0.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_writes 4 # Number of floating instruction queue writes system.cpu0.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 388910 # Number of integer alu accesses +system.cpu0.iq.int_alu_accesses 468813 # Number of integer alu accesses system.cpu0.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 72419 # Number of loads that had data forwarded from stores +system.cpu0.iew.lsq.thread0.forwLoads 87651 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 2653 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 63 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 1674 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 3007 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 8 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 54 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 1906 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu0.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 22 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.cacheBlocked 11 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1250 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 1969 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 38 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 466549 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 243 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 149926 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 75817 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 770 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 46 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewSquashCycles 1741 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 2371 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 27 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 562514 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 182 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 180818 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 91318 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 990 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 27 # Number of times the IQ has become full, causing a stall system.cpu0.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 63 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 318 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 991 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 1309 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 387610 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 148943 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 1012 # Number of squashed instructions skipped in execute +system.cpu0.iew.memOrderViolationEvents 54 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 236 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 1703 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 1939 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 466997 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 179835 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 1488 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 73609 # number of nop insts executed -system.cpu0.iew.exec_refs 223859 # number of memory reference insts executed -system.cpu0.iew.exec_branches 76931 # Number of branches executed -system.cpu0.iew.exec_stores 74916 # Number of stores executed -system.cpu0.iew.exec_rate 1.799481 # Inst execution rate -system.cpu0.iew.wb_sent 387178 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 386770 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 229443 # num instructions producing a value -system.cpu0.iew.wb_consumers 232488 # num instructions consuming a value -system.cpu0.iew.wb_rate 1.795581 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.986903 # average fanout of values written-back -system.cpu0.commit.commitSquashedInsts 13089 # The number of squashed insts skipped by commit +system.cpu0.iew.exec_nop 88819 # number of nop insts executed +system.cpu0.iew.exec_refs 270170 # number of memory reference insts executed +system.cpu0.iew.exec_branches 92803 # Number of branches executed +system.cpu0.iew.exec_stores 90335 # Number of stores executed +system.cpu0.iew.exec_rate 1.854789 # Inst execution rate +system.cpu0.iew.wb_sent 466340 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 465867 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 276291 # num instructions producing a value +system.cpu0.iew.wb_consumers 279830 # num instructions consuming a value +system.cpu0.iew.wb_rate 1.850301 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.987353 # average fanout of values written-back +system.cpu0.commit.commitSquashedInsts 17414 # The number of squashed insts skipped by commit system.cpu0.commit.commitNonSpecStalls 559 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 1100 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 186278 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 2.434007 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 2.148610 # Number of insts commited each cycle +system.cpu0.commit.branchMispredicts 1592 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 220844 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 2.467878 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 2.142709 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 33753 18.12% 18.12% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 76007 40.80% 58.92% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 1940 1.04% 59.96% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 664 0.36% 60.32% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 518 0.28% 60.60% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 72154 38.73% 99.33% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 496 0.27% 99.60% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 263 0.14% 99.74% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 483 0.26% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 37532 16.99% 16.99% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 91545 41.45% 58.45% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 2011 0.91% 59.36% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 623 0.28% 59.64% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 506 0.23% 59.87% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 87423 39.59% 99.45% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 455 0.21% 99.66% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 281 0.13% 99.79% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 468 0.21% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 186278 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 453402 # Number of instructions committed -system.cpu0.commit.committedOps 453402 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 220844 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 545016 # Number of instructions committed +system.cpu0.commit.committedOps 545016 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 221416 # Number of memory references committed -system.cpu0.commit.loads 147273 # Number of loads committed +system.cpu0.commit.refs 267223 # Number of memory references committed +system.cpu0.commit.loads 177811 # Number of loads committed system.cpu0.commit.membars 84 # Number of memory barriers committed -system.cpu0.commit.branches 76030 # Number of branches committed +system.cpu0.commit.branches 91299 # Number of branches committed system.cpu0.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 305698 # Number of committed integer instructions. +system.cpu0.commit.int_insts 366774 # Number of committed integer instructions. system.cpu0.commit.function_calls 223 # Number of function calls committed. -system.cpu0.commit.op_class_0::No_OpClass 72762 16.05% 16.05% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 159140 35.10% 51.15% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 0 0.00% 51.15% # Class of committed instruction -system.cpu0.commit.op_class_0::IntDiv 0 0.00% 51.15% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 51.15% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 51.15% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 51.15% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMult 0 0.00% 51.15% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 51.15% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 51.15% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 51.15% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 51.15% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 51.15% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 51.15% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 51.15% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 51.15% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMult 0 0.00% 51.15% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 51.15% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShift 0 0.00% 51.15% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 51.15% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 51.15% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 51.15% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 51.15% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 51.15% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 51.15% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 51.15% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 51.15% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 51.15% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 51.15% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 51.15% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 147357 32.50% 83.65% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 74143 16.35% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::No_OpClass 88031 16.15% 16.15% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 189678 34.80% 50.95% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 0 0.00% 50.95% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 0 0.00% 50.95% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 50.95% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 50.95% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 50.95% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMult 0 0.00% 50.95% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 50.95% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 50.95% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 50.95% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 50.95% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 50.95% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 50.95% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 50.95% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 50.95% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMult 0 0.00% 50.95% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 50.95% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShift 0 0.00% 50.95% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 50.95% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 50.95% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 50.95% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 50.95% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 50.95% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 50.95% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 50.95% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 50.95% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 50.95% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 50.95% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 50.95% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 177895 32.64% 83.59% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 89412 16.41% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 453402 # Class of committed instruction -system.cpu0.commit.bw_lim_events 483 # number cycles where commit BW limit reached -system.cpu0.rob.rob_reads 651125 # The number of ROB reads -system.cpu0.rob.rob_writes 935459 # The number of ROB writes -system.cpu0.timesIdled 313 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 26662 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.committedInsts 380556 # Number of Instructions Simulated -system.cpu0.committedOps 380556 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 0.566017 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 0.566017 # CPI: Total CPI of All Threads -system.cpu0.ipc 1.766733 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 1.766733 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 693490 # number of integer regfile reads -system.cpu0.int_regfile_writes 312678 # number of integer regfile writes +system.cpu0.commit.op_class_0::total 545016 # Class of committed instruction +system.cpu0.commit.bw_lim_events 468 # number cycles where commit BW limit reached +system.cpu0.rob.rob_reads 781645 # The number of ROB reads +system.cpu0.rob.rob_writes 1128336 # The number of ROB writes +system.cpu0.timesIdled 327 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 27520 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.committedInsts 456901 # Number of Instructions Simulated +system.cpu0.committedOps 456901 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 0.551058 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 0.551058 # CPI: Total CPI of All Threads +system.cpu0.ipc 1.814691 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 1.814691 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 834795 # number of integer regfile reads +system.cpu0.int_regfile_writes 376287 # number of integer regfile writes system.cpu0.fp_regfile_reads 192 # number of floating regfile reads -system.cpu0.misc_regfile_reads 225727 # number of misc regfile reads +system.cpu0.misc_regfile_reads 272308 # number of misc regfile reads system.cpu0.misc_regfile_writes 564 # number of misc regfile writes system.cpu0.dcache.tags.replacements 2 # number of replacements -system.cpu0.dcache.tags.tagsinuse 141.118700 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 149407 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 171 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 873.725146 # Average number of references to valid blocks. +system.cpu0.dcache.tags.tagsinuse 143.015419 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 180238 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 172 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 1047.895349 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 141.118700 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.275622 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.275622 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 169 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 67 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 84 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 0.330078 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 602739 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 602739 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 75912 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 75912 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 73546 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 73546 # number of WriteReq hits -system.cpu0.dcache.SwapReq_hits::cpu0.data 16 # number of SwapReq hits -system.cpu0.dcache.SwapReq_hits::total 16 # number of SwapReq hits -system.cpu0.dcache.demand_hits::cpu0.data 149458 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 149458 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 149458 # number of overall hits -system.cpu0.dcache.overall_hits::total 149458 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 553 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 553 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 555 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 555 # number of WriteReq misses -system.cpu0.dcache.SwapReq_misses::cpu0.data 26 # number of SwapReq misses -system.cpu0.dcache.SwapReq_misses::total 26 # number of SwapReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1108 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1108 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1108 # number of overall misses -system.cpu0.dcache.overall_misses::total 1108 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 16789000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 16789000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 34744480 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 34744480 # number of WriteReq miss cycles -system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 472500 # number of SwapReq miss cycles -system.cpu0.dcache.SwapReq_miss_latency::total 472500 # number of SwapReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 51533480 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 51533480 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 51533480 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 51533480 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 76465 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 76465 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 74101 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 74101 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.tags.occ_blocks::cpu0.data 143.015419 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.279327 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.279327 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 170 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 143 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 0.332031 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 726286 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 726286 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 91504 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 91504 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 88818 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 88818 # number of WriteReq hits +system.cpu0.dcache.SwapReq_hits::cpu0.data 19 # number of SwapReq hits +system.cpu0.dcache.SwapReq_hits::total 19 # number of SwapReq hits +system.cpu0.dcache.demand_hits::cpu0.data 180322 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 180322 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 180322 # number of overall hits +system.cpu0.dcache.overall_hits::total 180322 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 576 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 576 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 552 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 552 # number of WriteReq misses +system.cpu0.dcache.SwapReq_misses::cpu0.data 23 # number of SwapReq misses +system.cpu0.dcache.SwapReq_misses::total 23 # number of SwapReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1128 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1128 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1128 # number of overall misses +system.cpu0.dcache.overall_misses::total 1128 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 18232000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 18232000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 36205990 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 36205990 # number of WriteReq miss cycles +system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 589500 # number of SwapReq miss cycles +system.cpu0.dcache.SwapReq_miss_latency::total 589500 # number of SwapReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 54437990 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 54437990 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 54437990 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 54437990 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 92080 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 92080 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 89370 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 89370 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses) system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 150566 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 150566 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 150566 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 150566 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.007232 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.007232 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007490 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.007490 # miss rate for WriteReq accesses -system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.619048 # miss rate for SwapReq accesses -system.cpu0.dcache.SwapReq_miss_rate::total 0.619048 # miss rate for SwapReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.007359 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.007359 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.007359 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.007359 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 30359.855335 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 30359.855335 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 62602.666667 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 62602.666667 # average WriteReq miss latency -system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 18173.076923 # average SwapReq miss latency -system.cpu0.dcache.SwapReq_avg_miss_latency::total 18173.076923 # average SwapReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 46510.361011 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 46510.361011 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 46510.361011 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 46510.361011 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 891 # number of cycles access was blocked +system.cpu0.dcache.demand_accesses::cpu0.data 181450 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 181450 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 181450 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 181450 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.006255 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.006255 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.006177 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.006177 # miss rate for WriteReq accesses +system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.547619 # miss rate for SwapReq accesses +system.cpu0.dcache.SwapReq_miss_rate::total 0.547619 # miss rate for SwapReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.006217 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.006217 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.006217 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.006217 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 31652.777778 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 31652.777778 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 65590.561594 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 65590.561594 # average WriteReq miss latency +system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 25630.434783 # average SwapReq miss latency +system.cpu0.dcache.SwapReq_avg_miss_latency::total 25630.434783 # average SwapReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 48260.629433 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 48260.629433 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 48260.629433 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 48260.629433 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 818 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 27 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 22 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 33 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 37.181818 # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks system.cpu0.dcache.writebacks::total 1 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 370 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 370 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 378 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 378 # number of WriteReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 748 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 748 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 748 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 748 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 183 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 183 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 177 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 177 # number of WriteReq MSHR misses -system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 26 # number of SwapReq MSHR misses -system.cpu0.dcache.SwapReq_mshr_misses::total 26 # number of SwapReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 360 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 360 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 360 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 360 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 6853000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6853000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 8423500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8423500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 446500 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.SwapReq_mshr_miss_latency::total 446500 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 15276500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 15276500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 15276500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 15276500 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002393 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002393 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002389 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002389 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.619048 # mshr miss rate for SwapReq accesses -system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.619048 # mshr miss rate for SwapReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002391 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.002391 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002391 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.002391 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 37448.087432 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 37448.087432 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 47590.395480 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 47590.395480 # average WriteReq mshr miss latency -system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 17173.076923 # average SwapReq mshr miss latency -system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 17173.076923 # average SwapReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 42434.722222 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 42434.722222 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 42434.722222 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 42434.722222 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 380 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 380 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 386 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 386 # number of WriteReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 766 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 766 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 766 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 766 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 196 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 196 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 166 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 166 # number of WriteReq MSHR misses +system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 23 # number of SwapReq MSHR misses +system.cpu0.dcache.SwapReq_mshr_misses::total 23 # number of SwapReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 362 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 362 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 362 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 362 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 7598500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 7598500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 8576000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8576000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 566500 # number of SwapReq MSHR miss cycles +system.cpu0.dcache.SwapReq_mshr_miss_latency::total 566500 # number of SwapReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 16174500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 16174500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 16174500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 16174500 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002129 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002129 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.001857 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.001857 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.547619 # mshr miss rate for SwapReq accesses +system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.547619 # mshr miss rate for SwapReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.001995 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.001995 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.001995 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.001995 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 38767.857143 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 38767.857143 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 51662.650602 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 51662.650602 # average WriteReq mshr miss latency +system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 24630.434783 # average SwapReq mshr miss latency +system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 24630.434783 # average SwapReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 44680.939227 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 44680.939227 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 44680.939227 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 44680.939227 # average overall mshr miss latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 315 # number of replacements -system.cpu0.icache.tags.tagsinuse 241.159002 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 5949 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 607 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 9.800659 # Average number of references to valid blocks. +system.cpu0.icache.tags.replacements 403 # number of replacements +system.cpu0.icache.tags.tagsinuse 251.059263 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 7130 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 705 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 10.113475 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 241.159002 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.471014 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.471014 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_task_id_blocks::1024 292 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 177 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 56 # Occupied blocks per task id -system.cpu0.icache.tags.occ_task_id_percent::1024 0.570312 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 7339 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 7339 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 5949 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 5949 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 5949 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 5949 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 5949 # number of overall hits -system.cpu0.icache.overall_hits::total 5949 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 783 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 783 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 783 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 783 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 783 # number of overall misses -system.cpu0.icache.overall_misses::total 783 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 40394500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 40394500 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 40394500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 40394500 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 40394500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 40394500 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 6732 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 6732 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 6732 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 6732 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 6732 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 6732 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.116310 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.116310 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.116310 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.116310 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.116310 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.116310 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 51589.399745 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 51589.399745 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 51589.399745 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 51589.399745 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 51589.399745 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 51589.399745 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 4 # number of cycles access was blocked +system.cpu0.icache.tags.occ_blocks::cpu0.inst 251.059263 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.490350 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.490350 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_task_id_blocks::1024 302 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 70 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 39 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 193 # Occupied blocks per task id +system.cpu0.icache.tags.occ_task_id_percent::1024 0.589844 # Percentage of cache occupancy per task id +system.cpu0.icache.tags.tag_accesses 8756 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 8756 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 7130 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 7130 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 7130 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 7130 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 7130 # number of overall hits +system.cpu0.icache.overall_hits::total 7130 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 921 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 921 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 921 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 921 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 921 # number of overall misses +system.cpu0.icache.overall_misses::total 921 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 43922000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 43922000 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 43922000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 43922000 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 43922000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 43922000 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 8051 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 8051 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 8051 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 8051 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 8051 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 8051 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.114396 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.114396 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.114396 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.114396 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.114396 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.114396 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 47689.467970 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 47689.467970 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 47689.467970 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 47689.467970 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 47689.467970 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 47689.467970 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 113 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 1 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 4 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 4 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 28.250000 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.writebacks::writebacks 315 # number of writebacks -system.cpu0.icache.writebacks::total 315 # number of writebacks -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 175 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 175 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 175 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 175 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 175 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 175 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 608 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 608 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 608 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 608 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 608 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 608 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 31312500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 31312500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 31312500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 31312500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 31312500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 31312500 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.090315 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.090315 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.090315 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.090315 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.090315 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.090315 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 51500.822368 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 51500.822368 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 51500.822368 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 51500.822368 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 51500.822368 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 51500.822368 # average overall mshr miss latency +system.cpu0.icache.writebacks::writebacks 403 # number of writebacks +system.cpu0.icache.writebacks::total 403 # number of writebacks +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 215 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 215 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 215 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 215 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 215 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 215 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 706 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 706 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 706 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 706 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 706 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 706 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 33748500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 33748500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 33748500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 33748500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 33748500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 33748500 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.087691 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.087691 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.087691 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.087691 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.087691 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.087691 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 47802.407932 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 47802.407932 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 47802.407932 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 47802.407932 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 47802.407932 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 47802.407932 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 52270 # Number of BP lookups -system.cpu1.branchPred.condPredicted 48857 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 1261 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 45038 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 43957 # Number of BTB hits +system.cpu1.branchPred.lookups 75929 # Number of BP lookups +system.cpu1.branchPred.condPredicted 68631 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 2222 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 68395 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 0 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 97.599805 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 912 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 1839 # Number of times the RAS was used to get a target. system.cpu1.branchPred.RASInCorrect 231 # Number of incorrect RAS predictions. -system.cpu1.numCycles 162626 # number of cpu cycles simulated +system.cpu1.branchPred.indirectLookups 68395 # Number of indirect predictor lookups. +system.cpu1.branchPred.indirectHits 58396 # Number of indirect target hits. +system.cpu1.branchPred.indirectMisses 9999 # Number of indirect misses. +system.cpu1.branchPredindirectMispredicted 1194 # Number of mispredicted indirect branches. +system.cpu1.numCycles 196540 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 30636 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 289541 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 52270 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 44869 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 123502 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 2677 # Number of cycles fetch has spent squashing -system.cpu1.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.icacheStallCycles 32617 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 424540 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 75929 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 60235 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 157282 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 4599 # Number of cycles fetch has spent squashing +system.cpu1.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu1.fetch.NoActiveThreadStallCycles 10 # Number of stall cycles due to no active thread to fetch from -system.cpu1.fetch.PendingTrapStallCycles 1084 # Number of stall cycles due to pending traps -system.cpu1.fetch.IcacheWaitRetryStallCycles 11 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 21117 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 458 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 156585 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 1.849098 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.199028 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.PendingTrapStallCycles 1756 # Number of stall cycles due to pending traps +system.cpu1.fetch.CacheLines 22091 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 889 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 193967 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 2.188723 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.372433 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 55186 35.24% 35.24% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 51235 32.72% 67.96% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 6397 4.09% 72.05% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 3507 2.24% 74.29% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 942 0.60% 74.89% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 33361 21.31% 96.20% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 1213 0.77% 96.97% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 812 0.52% 97.49% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 3932 2.51% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 56525 29.14% 29.14% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 66630 34.35% 63.49% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 5516 2.84% 66.34% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 3688 1.90% 68.24% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 688 0.35% 68.59% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 50225 25.89% 94.49% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 1136 0.59% 95.07% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 1351 0.70% 95.77% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 8208 4.23% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 156585 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.321412 # Number of branch fetches per cycle -system.cpu1.fetch.rate 1.780410 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 17913 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 54188 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 79912 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 3224 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 1338 # Number of cycles decode is squashing -system.cpu1.decode.DecodedInsts 274398 # Number of instructions handled by decode -system.cpu1.rename.SquashCycles 1338 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 18610 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 24678 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 13550 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 81416 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 16983 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 271226 # Number of instructions processed by rename -system.cpu1.rename.IQFullEvents 15241 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 15 # Number of times rename has blocked due to LQ full -system.cpu1.rename.FullRegisterEvents 6 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 191192 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 520363 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 405271 # Number of integer rename lookups -system.cpu1.rename.CommittedMaps 177667 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 13525 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 1180 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 1251 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 21370 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 76128 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 36144 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 36135 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 31079 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 225686 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 6135 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 227404 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 8 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 12625 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 10115 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 706 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 156585 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 1.452272 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.380275 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 193967 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.386328 # Number of branch fetches per cycle +system.cpu1.fetch.rate 2.160069 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 20990 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 50963 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 116406 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 3299 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 2299 # Number of cycles decode is squashing +system.cpu1.decode.DecodedInsts 394135 # Number of instructions handled by decode +system.cpu1.rename.SquashCycles 2299 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 22042 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 22361 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 14616 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 117990 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 14649 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 387817 # Number of instructions processed by rename +system.cpu1.rename.IQFullEvents 13215 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 19 # Number of times rename has blocked due to LQ full +system.cpu1.rename.RenamedOperands 272713 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 753683 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 582463 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 32 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 245854 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 26859 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 1602 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 1739 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 20098 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 111716 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 54519 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 52739 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 48254 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 321016 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 5993 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 319557 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 54 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 23622 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 18296 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 1159 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 193967 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 1.647481 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.362491 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 58755 37.52% 37.52% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 20747 13.25% 50.77% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 35642 22.76% 73.53% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 35172 22.46% 96.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 3374 2.15% 98.15% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1612 1.03% 99.18% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 878 0.56% 99.74% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 207 0.13% 99.87% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 198 0.13% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 60994 31.45% 31.45% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 19742 10.18% 41.62% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 53241 27.45% 69.07% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 52847 27.25% 96.32% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 3638 1.88% 98.19% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1763 0.91% 99.10% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 1052 0.54% 99.64% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 407 0.21% 99.85% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 283 0.15% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 156585 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 193967 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 79 24.01% 24.01% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 24.01% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 24.01% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 24.01% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 24.01% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 24.01% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 24.01% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 24.01% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 24.01% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 24.01% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 24.01% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 24.01% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 24.01% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 24.01% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 24.01% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 24.01% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 24.01% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 24.01% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 24.01% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 24.01% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 24.01% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 24.01% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 24.01% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 24.01% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 24.01% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 24.01% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 24.01% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 24.01% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 24.01% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 41 12.46% 36.47% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 209 63.53% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 169 37.31% 37.31% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 37.31% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 37.31% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 37.31% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 37.31% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 37.31% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 37.31% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 37.31% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 37.31% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 37.31% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 37.31% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 37.31% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 37.31% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 37.31% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 37.31% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 37.31% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 37.31% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 37.31% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 37.31% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 37.31% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 37.31% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 37.31% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 37.31% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 37.31% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 37.31% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 37.31% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 37.31% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 37.31% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 37.31% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 58 12.80% 50.11% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 226 49.89% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 111654 49.10% 49.10% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 0 0.00% 49.10% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 49.10% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 49.10% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 49.10% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 49.10% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 49.10% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 49.10% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 49.10% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 49.10% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 49.10% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 49.10% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 49.10% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 49.10% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 49.10% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 49.10% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 49.10% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 49.10% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.10% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 49.10% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.10% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.10% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.10% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.10% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.10% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.10% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 49.10% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.10% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.10% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 80158 35.25% 84.35% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 35592 15.65% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 151236 47.33% 47.33% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 0 0.00% 47.33% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.33% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.33% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.33% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 47.33% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 47.33% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 47.33% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 47.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 47.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 47.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 47.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 47.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 47.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 47.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 47.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 47.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.33% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 114807 35.93% 83.25% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 53514 16.75% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 227404 # Type of FU issued -system.cpu1.iq.rate 1.398325 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 329 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.001447 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 611730 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 244482 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 225916 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.FU_type_0::total 319557 # Type of FU issued +system.cpu1.iq.rate 1.625913 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 453 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.001418 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 833588 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 350606 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 315974 # Number of integer instruction queue wakeup accesses system.cpu1.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_writes 64 # Number of floating instruction queue writes system.cpu1.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 227733 # Number of integer alu accesses +system.cpu1.iq.int_alu_accesses 320010 # Number of integer alu accesses system.cpu1.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 30932 # Number of loads that had data forwarded from stores +system.cpu1.iew.lsq.thread0.forwLoads 48132 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 2495 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 36 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 1427 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 4290 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 32 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 39 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 2608 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu1.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu1.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 1338 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 7175 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 65 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 268817 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 146 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 76128 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 36144 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 1126 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 38 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewSquashCycles 2299 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 7227 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 50 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 380950 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 338 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 111716 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 54519 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 1500 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 40 # Number of times the IQ has become full, causing a stall system.cpu1.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 36 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 440 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 1052 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 1492 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 226425 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 75137 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 979 # Number of squashed instructions skipped in execute +system.cpu1.iew.memOrderViolationEvents 39 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 429 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 2382 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 2811 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 317250 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 110168 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 2307 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 36996 # number of nop insts executed -system.cpu1.iew.exec_refs 110644 # number of memory reference insts executed -system.cpu1.iew.exec_branches 46426 # Number of branches executed -system.cpu1.iew.exec_stores 35507 # Number of stores executed -system.cpu1.iew.exec_rate 1.392305 # Inst execution rate -system.cpu1.iew.wb_sent 226182 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 225916 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 128242 # num instructions producing a value -system.cpu1.iew.wb_consumers 134834 # num instructions consuming a value -system.cpu1.iew.wb_rate 1.389175 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.951110 # average fanout of values written-back -system.cpu1.commit.commitSquashedInsts 13383 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 5429 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 1261 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 154086 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 1.657380 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 2.063453 # Number of insts commited each cycle +system.cpu1.iew.exec_nop 53941 # number of nop insts executed +system.cpu1.iew.exec_refs 163396 # number of memory reference insts executed +system.cpu1.iew.exec_branches 64160 # Number of branches executed +system.cpu1.iew.exec_stores 53228 # Number of stores executed +system.cpu1.iew.exec_rate 1.614175 # Inst execution rate +system.cpu1.iew.wb_sent 316458 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 315974 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 181395 # num instructions producing a value +system.cpu1.iew.wb_consumers 189019 # num instructions consuming a value +system.cpu1.iew.wb_rate 1.607683 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.959665 # average fanout of values written-back +system.cpu1.commit.commitSquashedInsts 24733 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 4834 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 2222 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 189334 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 1.881189 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 2.115429 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 63982 41.52% 41.52% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 43006 27.91% 69.43% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 5237 3.40% 72.83% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 6258 4.06% 76.89% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1532 0.99% 77.89% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 30979 20.11% 97.99% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 844 0.55% 98.54% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 946 0.61% 99.16% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1302 0.84% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 65341 34.51% 34.51% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 60499 31.95% 66.46% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 5361 2.83% 69.30% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 5469 2.89% 72.18% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1297 0.69% 72.87% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 48347 25.54% 98.40% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 750 0.40% 98.80% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 1038 0.55% 99.35% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1232 0.65% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 154086 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 255379 # Number of instructions committed -system.cpu1.commit.committedOps 255379 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 189334 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 356173 # Number of instructions committed +system.cpu1.commit.committedOps 356173 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 108350 # Number of memory references committed -system.cpu1.commit.loads 73633 # Number of loads committed -system.cpu1.commit.membars 4715 # Number of memory barriers committed -system.cpu1.commit.branches 45393 # Number of branches committed +system.cpu1.commit.refs 159337 # Number of memory references committed +system.cpu1.commit.loads 107426 # Number of loads committed +system.cpu1.commit.membars 4118 # Number of memory barriers committed +system.cpu1.commit.branches 61998 # Number of branches committed system.cpu1.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 175866 # Number of committed integer instructions. +system.cpu1.commit.int_insts 243452 # Number of committed integer instructions. system.cpu1.commit.function_calls 322 # Number of function calls committed. -system.cpu1.commit.op_class_0::No_OpClass 36183 14.17% 14.17% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 106131 41.56% 55.73% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 0 0.00% 55.73% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 0 0.00% 55.73% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 55.73% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 55.73% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 55.73% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 55.73% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 55.73% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 55.73% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 55.73% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 55.73% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 55.73% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 55.73% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 55.73% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 55.73% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 55.73% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 55.73% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 55.73% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 55.73% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 55.73% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 55.73% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 55.73% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 55.73% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 55.73% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 55.73% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 55.73% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 55.73% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 55.73% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 55.73% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 78348 30.68% 86.41% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 34717 13.59% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::No_OpClass 52786 14.82% 14.82% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 139932 39.29% 54.11% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 0 0.00% 54.11% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 0 0.00% 54.11% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 54.11% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 54.11% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 54.11% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 54.11% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 54.11% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 54.11% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 54.11% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 54.11% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 54.11% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 54.11% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 54.11% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 54.11% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 54.11% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 54.11% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 54.11% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 54.11% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 54.11% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 54.11% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 54.11% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 54.11% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 54.11% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 54.11% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 54.11% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 54.11% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 54.11% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 54.11% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 111544 31.32% 85.43% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 51911 14.57% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 255379 # Class of committed instruction -system.cpu1.commit.bw_lim_events 1302 # number cycles where commit BW limit reached -system.cpu1.rob.rob_reads 420960 # The number of ROB reads -system.cpu1.rob.rob_writes 540023 # The number of ROB writes -system.cpu1.timesIdled 227 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 6041 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 45271 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 214481 # Number of Instructions Simulated -system.cpu1.committedOps 214481 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 0.758230 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 0.758230 # CPI: Total CPI of All Threads -system.cpu1.ipc 1.318860 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 1.318860 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 391734 # number of integer regfile reads -system.cpu1.int_regfile_writes 183502 # number of integer regfile writes +system.cpu1.commit.op_class_0::total 356173 # Class of committed instruction +system.cpu1.commit.bw_lim_events 1232 # number cycles where commit BW limit reached +system.cpu1.rob.rob_reads 568422 # The number of ROB reads +system.cpu1.rob.rob_writes 766486 # The number of ROB writes +system.cpu1.timesIdled 207 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 2573 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 46533 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 299269 # Number of Instructions Simulated +system.cpu1.committedOps 299269 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 0.656734 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 0.656734 # CPI: Total CPI of All Threads +system.cpu1.ipc 1.522687 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 1.522687 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 554283 # number of integer regfile reads +system.cpu1.int_regfile_writes 257020 # number of integer regfile writes system.cpu1.fp_regfile_writes 64 # number of floating regfile writes -system.cpu1.misc_regfile_reads 112279 # number of misc regfile reads +system.cpu1.misc_regfile_reads 165298 # number of misc regfile reads system.cpu1.misc_regfile_writes 648 # number of misc regfile writes system.cpu1.dcache.tags.replacements 0 # number of replacements -system.cpu1.dcache.tags.tagsinuse 25.736588 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 40830 # Total number of references to valid blocks. +system.cpu1.dcache.tags.tagsinuse 25.915239 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 58936 # Total number of references to valid blocks. system.cpu1.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 1407.931034 # Average number of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 2032.275862 # Average number of references to valid blocks. system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 25.736588 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.050267 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.050267 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_blocks::cpu1.data 25.915239 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.050616 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.050616 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 25 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id system.cpu1.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 315852 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 315852 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 43688 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 43688 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 34492 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 34492 # number of WriteReq hits -system.cpu1.dcache.SwapReq_hits::cpu1.data 17 # number of SwapReq hits -system.cpu1.dcache.SwapReq_hits::total 17 # number of SwapReq hits -system.cpu1.dcache.demand_hits::cpu1.data 78180 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 78180 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 78180 # number of overall hits -system.cpu1.dcache.overall_hits::total 78180 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 495 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 495 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 157 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 157 # number of WriteReq misses -system.cpu1.dcache.SwapReq_misses::cpu1.data 51 # number of SwapReq misses -system.cpu1.dcache.SwapReq_misses::total 51 # number of SwapReq misses -system.cpu1.dcache.demand_misses::cpu1.data 652 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 652 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 652 # number of overall misses -system.cpu1.dcache.overall_misses::total 652 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 8967000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 8967000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3364000 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 3364000 # number of WriteReq miss cycles -system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 599000 # number of SwapReq miss cycles -system.cpu1.dcache.SwapReq_miss_latency::total 599000 # number of SwapReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 12331000 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 12331000 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 12331000 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 12331000 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 44183 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 44183 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 34649 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 34649 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SwapReq_accesses::cpu1.data 68 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.SwapReq_accesses::total 68 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 78832 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 78832 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 78832 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 78832 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.011203 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.011203 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.004531 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.004531 # miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.750000 # miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_miss_rate::total 0.750000 # miss rate for SwapReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.008271 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.008271 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.008271 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.008271 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 18115.151515 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 18115.151515 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 21426.751592 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 21426.751592 # average WriteReq miss latency -system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 11745.098039 # average SwapReq miss latency -system.cpu1.dcache.SwapReq_avg_miss_latency::total 11745.098039 # average SwapReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 18912.576687 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 18912.576687 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18912.576687 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 18912.576687 # average overall miss latency +system.cpu1.dcache.tags.tag_accesses 455882 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 455882 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 61472 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 61472 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 51691 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 51691 # number of WriteReq hits +system.cpu1.dcache.SwapReq_hits::cpu1.data 10 # number of SwapReq hits +system.cpu1.dcache.SwapReq_hits::total 10 # number of SwapReq hits +system.cpu1.dcache.demand_hits::cpu1.data 113163 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 113163 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 113163 # number of overall hits +system.cpu1.dcache.overall_hits::total 113163 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 523 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 523 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 150 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 150 # number of WriteReq misses +system.cpu1.dcache.SwapReq_misses::cpu1.data 60 # number of SwapReq misses +system.cpu1.dcache.SwapReq_misses::total 60 # number of SwapReq misses +system.cpu1.dcache.demand_misses::cpu1.data 673 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 673 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 673 # number of overall misses +system.cpu1.dcache.overall_misses::total 673 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 8464500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 8464500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2960500 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 2960500 # number of WriteReq miss cycles +system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 828000 # number of SwapReq miss cycles +system.cpu1.dcache.SwapReq_miss_latency::total 828000 # number of SwapReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 11425000 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 11425000 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 11425000 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 11425000 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 61995 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 61995 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 51841 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 51841 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_accesses::cpu1.data 70 # number of SwapReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_accesses::total 70 # number of SwapReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 113836 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 113836 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 113836 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 113836 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.008436 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.008436 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.002893 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.002893 # miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.857143 # miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_miss_rate::total 0.857143 # miss rate for SwapReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.005912 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.005912 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.005912 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.005912 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16184.512428 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 16184.512428 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 19736.666667 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 19736.666667 # average WriteReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 13800 # average SwapReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::total 13800 # average SwapReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 16976.225854 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 16976.225854 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16976.225854 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 16976.225854 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1186,517 +1195,526 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 331 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 331 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 51 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 51 # number of WriteReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 382 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 382 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 382 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 382 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 164 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 164 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 106 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 106 # number of WriteReq MSHR misses -system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 51 # number of SwapReq MSHR misses -system.cpu1.dcache.SwapReq_mshr_misses::total 51 # number of SwapReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 270 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 270 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 270 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 270 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1988000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1988000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1748500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1748500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 548000 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::total 548000 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3736500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 3736500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3736500 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 3736500 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003712 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003712 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.003059 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.003059 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.750000 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.750000 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.003425 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.003425 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.003425 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.003425 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12121.951220 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12121.951220 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16495.283019 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16495.283019 # average WriteReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 10745.098039 # average SwapReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 10745.098039 # average SwapReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 13838.888889 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 13838.888889 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 13838.888889 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 13838.888889 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 362 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 362 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 43 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 43 # number of WriteReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 405 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 405 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 405 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 405 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 161 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 161 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 107 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 107 # number of WriteReq MSHR misses +system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 60 # number of SwapReq MSHR misses +system.cpu1.dcache.SwapReq_mshr_misses::total 60 # number of SwapReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 268 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 268 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 268 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 268 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1530000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1530000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1517000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1517000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 768000 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::total 768000 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3047000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 3047000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3047000 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 3047000 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.002597 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.002597 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.002064 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.002064 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.857143 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.857143 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.002354 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.002354 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.002354 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.002354 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 9503.105590 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 9503.105590 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 14177.570093 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 14177.570093 # average WriteReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 12800 # average SwapReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 12800 # average SwapReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 11369.402985 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 11369.402985 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 11369.402985 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 11369.402985 # average overall mshr miss latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 383 # number of replacements -system.cpu1.icache.tags.tagsinuse 84.417280 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 20534 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 496 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 41.399194 # Average number of references to valid blocks. +system.cpu1.icache.tags.replacements 548 # number of replacements +system.cpu1.icache.tags.tagsinuse 97.609803 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 21265 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 682 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 31.180352 # Average number of references to valid blocks. system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 84.417280 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.164877 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.164877 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_task_id_blocks::1024 113 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 102 # Occupied blocks per task id -system.cpu1.icache.tags.occ_task_id_percent::1024 0.220703 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 21613 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 21613 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 20534 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 20534 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 20534 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 20534 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 20534 # number of overall hits -system.cpu1.icache.overall_hits::total 20534 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 583 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 583 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 583 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 583 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 583 # number of overall misses -system.cpu1.icache.overall_misses::total 583 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 14299500 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 14299500 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 14299500 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 14299500 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 14299500 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 14299500 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 21117 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 21117 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 21117 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 21117 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 21117 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 21117 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.027608 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.027608 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.027608 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.027608 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.027608 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.027608 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 24527.444254 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 24527.444254 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 24527.444254 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 24527.444254 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 24527.444254 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 24527.444254 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 128 # number of cycles access was blocked +system.cpu1.icache.tags.occ_blocks::cpu1.inst 97.609803 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.190644 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.190644 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_task_id_blocks::1024 134 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 113 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 12 # Occupied blocks per task id +system.cpu1.icache.tags.occ_task_id_percent::1024 0.261719 # Percentage of cache occupancy per task id +system.cpu1.icache.tags.tag_accesses 22773 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 22773 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 21265 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 21265 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 21265 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 21265 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 21265 # number of overall hits +system.cpu1.icache.overall_hits::total 21265 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 826 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 826 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 826 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 826 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 826 # number of overall misses +system.cpu1.icache.overall_misses::total 826 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 13533000 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 13533000 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 13533000 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 13533000 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 13533000 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 13533000 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 22091 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 22091 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 22091 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 22091 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 22091 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 22091 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.037391 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.037391 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.037391 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.037391 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.037391 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.037391 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 16383.777240 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 16383.777240 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 16383.777240 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 16383.777240 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 16383.777240 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 16383.777240 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 15 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 2 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 1 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 64 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 15 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.writebacks::writebacks 383 # number of writebacks -system.cpu1.icache.writebacks::total 383 # number of writebacks -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 87 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 87 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 87 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 87 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 87 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 87 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 496 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 496 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 496 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 496 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 496 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 496 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 11785500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 11785500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 11785500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 11785500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 11785500 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 11785500 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.023488 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.023488 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.023488 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.023488 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.023488 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.023488 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 23761.088710 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 23761.088710 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 23761.088710 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 23761.088710 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 23761.088710 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 23761.088710 # average overall mshr miss latency +system.cpu1.icache.writebacks::writebacks 548 # number of writebacks +system.cpu1.icache.writebacks::total 548 # number of writebacks +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 144 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 144 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 144 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 144 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 144 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 144 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 682 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 682 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 682 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 682 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 682 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 682 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 10822000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 10822000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 10822000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 10822000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 10822000 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 10822000 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.030872 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.030872 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.030872 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.030872 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.030872 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.030872 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 15868.035191 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 15868.035191 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 15868.035191 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 15868.035191 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 15868.035191 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 15868.035191 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.branchPred.lookups 51016 # Number of BP lookups -system.cpu2.branchPred.condPredicted 47608 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 1273 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 43707 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 42688 # Number of BTB hits +system.cpu2.branchPred.lookups 65577 # Number of BP lookups +system.cpu2.branchPred.condPredicted 57724 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 2464 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 57712 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 0 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 97.668566 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 903 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 1983 # Number of times the RAS was used to get a target. system.cpu2.branchPred.RASInCorrect 231 # Number of incorrect RAS predictions. -system.cpu2.numCycles 162253 # number of cpu cycles simulated +system.cpu2.branchPred.indirectLookups 57712 # Number of indirect predictor lookups. +system.cpu2.branchPred.indirectHits 46848 # Number of indirect target hits. +system.cpu2.branchPred.indirectMisses 10864 # Number of indirect misses. +system.cpu2.branchPredindirectMispredicted 1379 # Number of mispredicted indirect branches. +system.cpu2.numCycles 195641 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 31836 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 280333 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 51016 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 43591 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 126252 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 2703 # Number of cycles fetch has spent squashing -system.cpu2.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.icacheStallCycles 39175 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 357136 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 65577 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 48831 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 146036 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 5085 # Number of cycles fetch has spent squashing +system.cpu2.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu2.fetch.NoActiveThreadStallCycles 10 # Number of stall cycles due to no active thread to fetch from -system.cpu2.fetch.PendingTrapStallCycles 1153 # Number of stall cycles due to pending traps -system.cpu2.fetch.CacheLines 22874 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 441 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.rateDist::samples 160605 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.745481 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.165535 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.PendingTrapStallCycles 2246 # Number of stall cycles due to pending traps +system.cpu2.fetch.IcacheWaitRetryStallCycles 31 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 27545 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 945 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.rateDist::samples 190045 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.879218 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.350973 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 60810 37.86% 37.86% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 50841 31.66% 69.52% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 7311 4.55% 74.07% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 3498 2.18% 76.25% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 961 0.60% 76.85% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 31234 19.45% 96.30% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 1226 0.76% 97.06% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 786 0.49% 97.55% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 3938 2.45% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 72125 37.95% 37.95% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 57864 30.45% 68.40% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 8007 4.21% 72.61% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 3378 1.78% 74.39% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 697 0.37% 74.76% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 36524 19.22% 93.98% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 1219 0.64% 94.62% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 1446 0.76% 95.38% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 8785 4.62% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 160605 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.314423 # Number of branch fetches per cycle -system.cpu2.fetch.rate 1.727752 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 17488 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 62772 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 75260 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 3724 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 1351 # Number of cycles decode is squashing -system.cpu2.decode.DecodedInsts 265175 # Number of instructions handled by decode -system.cpu2.rename.SquashCycles 1351 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 18185 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 29493 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 13900 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 76790 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 20876 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 262017 # Number of instructions processed by rename -system.cpu2.rename.IQFullEvents 18650 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LQFullEvents 17 # Number of times rename has blocked due to LQ full +system.cpu2.fetch.rateDist::total 190045 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.335190 # Number of branch fetches per cycle +system.cpu2.fetch.rate 1.825466 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 23115 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 69586 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 90388 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 4404 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 2542 # Number of cycles decode is squashing +system.cpu2.decode.DecodedInsts 325134 # Number of instructions handled by decode +system.cpu2.rename.SquashCycles 2542 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 24144 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 33213 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 15151 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 91754 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 23231 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 318523 # Number of instructions processed by rename +system.cpu2.rename.IQFullEvents 20453 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LQFullEvents 14 # Number of times rename has blocked due to LQ full system.cpu2.rename.FullRegisterEvents 3 # Number of times there has been no free registers -system.cpu2.rename.RenamedOperands 183428 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 498093 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 388599 # Number of integer rename lookups -system.cpu2.rename.CommittedMaps 169446 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 13982 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 1189 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 1258 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 25354 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 72684 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 33991 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 34917 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 28890 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 216663 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 7106 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 219007 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 19 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 13119 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 11098 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 687 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 160605 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 1.363637 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.376138 # Number of insts issued each cycle +system.cpu2.rename.RenamedOperands 223607 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 605589 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 472031 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 26 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 193721 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 29886 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 1685 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 1831 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 29018 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 87037 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 41099 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 41296 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 34595 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 259686 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 8253 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 260132 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 104 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 25858 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 19408 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 1214 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 190045 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 1.368792 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.393545 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 64456 40.13% 40.13% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 23625 14.71% 54.84% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 33318 20.75% 75.59% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 32915 20.49% 96.08% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 3374 2.10% 98.18% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 1611 1.00% 99.19% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 893 0.56% 99.74% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 212 0.13% 99.87% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 201 0.13% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 77002 40.52% 40.52% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 26562 13.98% 54.49% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 39729 20.91% 75.40% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 39504 20.79% 96.19% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 3584 1.89% 98.07% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 1794 0.94% 99.02% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 1114 0.59% 99.60% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 438 0.23% 99.83% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 318 0.17% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 160605 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 190045 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 80 23.32% 23.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 0 0.00% 23.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 23.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 23.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 23.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 23.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 23.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 23.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 23.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 23.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 23.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 23.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 23.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 23.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 23.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 23.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 23.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 23.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 23.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 23.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 23.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 23.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 23.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 23.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 23.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 23.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 23.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 23.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 23.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 54 15.74% 39.07% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 209 60.93% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 198 41.51% 41.51% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 0 0.00% 41.51% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 41.51% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 41.51% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 41.51% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 41.51% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 41.51% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 41.51% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 41.51% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 41.51% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 41.51% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 41.51% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 41.51% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 41.51% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 41.51% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 41.51% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 41.51% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 41.51% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 41.51% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 41.51% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 41.51% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 41.51% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 41.51% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 41.51% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 41.51% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 41.51% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 41.51% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 41.51% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 41.51% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 44 9.22% 50.73% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 235 49.27% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 108075 49.35% 49.35% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 0 0.00% 49.35% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 49.35% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 49.35% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 49.35% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 49.35% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 49.35% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 49.35% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 49.35% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 49.35% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 49.35% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 49.35% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 49.35% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 49.35% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 49.35% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 49.35% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 49.35% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 49.35% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.35% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 49.35% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.35% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.35% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.35% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.35% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.35% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.35% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 49.35% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.35% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.35% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 77606 35.44% 84.78% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 33326 15.22% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 127776 49.12% 49.12% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 0 0.00% 49.12% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 49.12% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 49.12% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 49.12% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 49.12% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 49.12% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 49.12% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 49.12% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 49.12% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 49.12% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 49.12% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 49.12% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 49.12% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 49.12% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 49.12% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 49.12% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 49.12% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.12% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 49.12% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.12% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.12% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.12% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.12% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.12% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.12% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 49.12% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.12% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.12% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 92295 35.48% 84.60% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 40061 15.40% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 219007 # Type of FU issued -system.cpu2.iq.rate 1.349787 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 343 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.001566 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 598981 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 236927 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 217448 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.FU_type_0::total 260132 # Type of FU issued +system.cpu2.iq.rate 1.329639 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 477 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.001834 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 710890 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 293781 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 256087 # Number of integer instruction queue wakeup accesses system.cpu2.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_writes 52 # Number of floating instruction queue writes system.cpu2.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 219350 # Number of integer alu accesses +system.cpu2.iq.int_alu_accesses 260609 # Number of integer alu accesses system.cpu2.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 28643 # Number of loads that had data forwarded from stores +system.cpu2.iew.lsq.thread0.forwLoads 34538 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 2671 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 39 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 1575 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 4572 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 34 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 36 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 2770 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu2.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu2.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 1351 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 8096 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 66 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 259522 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 168 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 72684 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 33991 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 1139 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 40 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewSquashCycles 2542 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 9787 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 53 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 310555 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 374 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 87037 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 41099 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 1544 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 30 # Number of times the IQ has become full, causing a stall system.cpu2.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 39 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 443 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 1062 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 1505 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 217972 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 71586 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 1035 # Number of squashed instructions skipped in execute +system.cpu2.iew.memOrderViolationEvents 36 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 461 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 2649 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 3110 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 257554 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 85462 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 2578 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 35753 # number of nop insts executed -system.cpu2.iew.exec_refs 104818 # number of memory reference insts executed -system.cpu2.iew.exec_branches 45124 # Number of branches executed -system.cpu2.iew.exec_stores 33232 # Number of stores executed -system.cpu2.iew.exec_rate 1.343408 # Inst execution rate -system.cpu2.iew.wb_sent 217734 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 217448 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 122408 # num instructions producing a value -system.cpu2.iew.wb_consumers 129014 # num instructions consuming a value -system.cpu2.iew.wb_rate 1.340179 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.948796 # average fanout of values written-back -system.cpu2.commit.commitSquashedInsts 13957 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 6419 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 1273 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 158015 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 1.553777 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 2.025126 # Number of insts commited each cycle +system.cpu2.iew.exec_nop 42616 # number of nop insts executed +system.cpu2.iew.exec_refs 125205 # number of memory reference insts executed +system.cpu2.iew.exec_branches 53054 # Number of branches executed +system.cpu2.iew.exec_stores 39743 # Number of stores executed +system.cpu2.iew.exec_rate 1.316462 # Inst execution rate +system.cpu2.iew.wb_sent 256619 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 256087 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 143359 # num instructions producing a value +system.cpu2.iew.wb_consumers 151246 # num instructions consuming a value +system.cpu2.iew.wb_rate 1.308964 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.947853 # average fanout of values written-back +system.cpu2.commit.commitSquashedInsts 27054 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 7039 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 2464 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 184962 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 1.532661 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 2.012592 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 70555 44.65% 44.65% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 41677 26.38% 71.03% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 5250 3.32% 74.35% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 7214 4.57% 78.91% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 1535 0.97% 79.89% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 28695 18.16% 98.05% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 838 0.53% 98.58% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 950 0.60% 99.18% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 1301 0.82% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 83513 45.15% 45.15% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 49247 26.63% 71.78% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 5539 2.99% 74.77% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 7621 4.12% 78.89% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 1289 0.70% 79.59% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 34776 18.80% 98.39% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 735 0.40% 98.79% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 1086 0.59% 99.38% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 1156 0.62% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 158015 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 245520 # Number of instructions committed -system.cpu2.commit.committedOps 245520 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 184962 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 283484 # Number of instructions committed +system.cpu2.commit.committedOps 283484 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 102429 # Number of memory references committed -system.cpu2.commit.loads 70013 # Number of loads committed -system.cpu2.commit.membars 5702 # Number of memory barriers committed -system.cpu2.commit.branches 44083 # Number of branches committed +system.cpu2.commit.refs 120794 # Number of memory references committed +system.cpu2.commit.loads 82465 # Number of loads committed +system.cpu2.commit.membars 6325 # Number of memory barriers committed +system.cpu2.commit.branches 50613 # Number of branches committed system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 168630 # Number of committed integer instructions. +system.cpu2.commit.int_insts 193531 # Number of committed integer instructions. system.cpu2.commit.function_calls 322 # Number of function calls committed. -system.cpu2.commit.op_class_0::No_OpClass 34870 14.20% 14.20% # Class of committed instruction -system.cpu2.commit.op_class_0::IntAlu 102519 41.76% 55.96% # Class of committed instruction -system.cpu2.commit.op_class_0::IntMult 0 0.00% 55.96% # Class of committed instruction -system.cpu2.commit.op_class_0::IntDiv 0 0.00% 55.96% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 55.96% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 55.96% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 55.96% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatMult 0 0.00% 55.96% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 55.96% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 55.96% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 55.96% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 55.96% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 55.96% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 55.96% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 55.96% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 55.96% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMult 0 0.00% 55.96% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 55.96% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShift 0 0.00% 55.96% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 55.96% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 55.96% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 55.96% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 55.96% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 55.96% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 55.96% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 55.96% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 55.96% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 55.96% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 55.96% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 55.96% # Class of committed instruction -system.cpu2.commit.op_class_0::MemRead 75715 30.84% 86.80% # Class of committed instruction -system.cpu2.commit.op_class_0::MemWrite 32416 13.20% 100.00% # Class of committed instruction +system.cpu2.commit.op_class_0::No_OpClass 41403 14.61% 14.61% # Class of committed instruction +system.cpu2.commit.op_class_0::IntAlu 114962 40.55% 55.16% # Class of committed instruction +system.cpu2.commit.op_class_0::IntMult 0 0.00% 55.16% # Class of committed instruction +system.cpu2.commit.op_class_0::IntDiv 0 0.00% 55.16% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 55.16% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 55.16% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 55.16% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatMult 0 0.00% 55.16% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 55.16% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 55.16% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 55.16% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 55.16% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 55.16% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 55.16% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 55.16% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 55.16% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMult 0 0.00% 55.16% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 55.16% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShift 0 0.00% 55.16% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 55.16% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 55.16% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 55.16% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 55.16% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 55.16% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 55.16% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 55.16% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 55.16% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 55.16% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 55.16% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 55.16% # Class of committed instruction +system.cpu2.commit.op_class_0::MemRead 88790 31.32% 86.48% # Class of committed instruction +system.cpu2.commit.op_class_0::MemWrite 38329 13.52% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu2.commit.op_class_0::total 245520 # Class of committed instruction -system.cpu2.commit.bw_lim_events 1301 # number cycles where commit BW limit reached -system.cpu2.rob.rob_reads 415605 # The number of ROB reads -system.cpu2.rob.rob_writes 521544 # The number of ROB writes -system.cpu2.timesIdled 214 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 1648 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 45643 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 204948 # Number of Instructions Simulated -system.cpu2.committedOps 204948 # Number of Ops (including micro ops) Simulated -system.cpu2.cpi 0.791679 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 0.791679 # CPI: Total CPI of All Threads -system.cpu2.ipc 1.263138 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 1.263138 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 374158 # number of integer regfile reads -system.cpu2.int_regfile_writes 175347 # number of integer regfile writes +system.cpu2.commit.op_class_0::total 283484 # Class of committed instruction +system.cpu2.commit.bw_lim_events 1156 # number cycles where commit BW limit reached +system.cpu2.rob.rob_reads 493758 # The number of ROB reads +system.cpu2.rob.rob_writes 626207 # The number of ROB writes +system.cpu2.timesIdled 224 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 5596 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 47431 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 235756 # Number of Instructions Simulated +system.cpu2.committedOps 235756 # Number of Ops (including micro ops) Simulated +system.cpu2.cpi 0.829845 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 0.829845 # CPI: Total CPI of All Threads +system.cpu2.ipc 1.205044 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 1.205044 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 440950 # number of integer regfile reads +system.cpu2.int_regfile_writes 206257 # number of integer regfile writes system.cpu2.fp_regfile_writes 64 # number of floating regfile writes -system.cpu2.misc_regfile_reads 106430 # number of misc regfile reads +system.cpu2.misc_regfile_reads 127194 # number of misc regfile reads system.cpu2.misc_regfile_writes 648 # number of misc regfile writes system.cpu2.dcache.tags.replacements 0 # number of replacements -system.cpu2.dcache.tags.tagsinuse 23.147052 # Cycle average of tags in use -system.cpu2.dcache.tags.total_refs 38440 # Total number of references to valid blocks. -system.cpu2.dcache.tags.sampled_refs 28 # Sample count of references to valid blocks. -system.cpu2.dcache.tags.avg_refs 1372.857143 # Average number of references to valid blocks. +system.cpu2.dcache.tags.tagsinuse 26.976674 # Cycle average of tags in use +system.cpu2.dcache.tags.total_refs 45756 # Total number of references to valid blocks. +system.cpu2.dcache.tags.sampled_refs 30 # Sample count of references to valid blocks. +system.cpu2.dcache.tags.avg_refs 1525.200000 # Average number of references to valid blocks. system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.dcache.tags.occ_blocks::cpu2.data 23.147052 # Average occupied blocks per requestor -system.cpu2.dcache.tags.occ_percent::cpu2.data 0.045209 # Average percentage of cache occupancy -system.cpu2.dcache.tags.occ_percent::total 0.045209 # Average percentage of cache occupancy -system.cpu2.dcache.tags.occ_task_id_blocks::1024 28 # Occupied blocks per task id -system.cpu2.dcache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id -system.cpu2.dcache.tags.occ_task_id_percent::1024 0.054688 # Percentage of cache occupancy per task id -system.cpu2.dcache.tags.tag_accesses 301603 # Number of tag accesses -system.cpu2.dcache.tags.data_accesses 301603 # Number of data accesses -system.cpu2.dcache.ReadReq_hits::cpu2.data 42391 # number of ReadReq hits -system.cpu2.dcache.ReadReq_hits::total 42391 # number of ReadReq hits -system.cpu2.dcache.WriteReq_hits::cpu2.data 32186 # number of WriteReq hits -system.cpu2.dcache.WriteReq_hits::total 32186 # number of WriteReq hits -system.cpu2.dcache.SwapReq_hits::cpu2.data 13 # number of SwapReq hits -system.cpu2.dcache.SwapReq_hits::total 13 # number of SwapReq hits -system.cpu2.dcache.demand_hits::cpu2.data 74577 # number of demand (read+write) hits -system.cpu2.dcache.demand_hits::total 74577 # number of demand (read+write) hits -system.cpu2.dcache.overall_hits::cpu2.data 74577 # number of overall hits -system.cpu2.dcache.overall_hits::total 74577 # number of overall hits -system.cpu2.dcache.ReadReq_misses::cpu2.data 529 # number of ReadReq misses -system.cpu2.dcache.ReadReq_misses::total 529 # number of ReadReq misses -system.cpu2.dcache.WriteReq_misses::cpu2.data 159 # number of WriteReq misses -system.cpu2.dcache.WriteReq_misses::total 159 # number of WriteReq misses -system.cpu2.dcache.SwapReq_misses::cpu2.data 58 # number of SwapReq misses -system.cpu2.dcache.SwapReq_misses::total 58 # number of SwapReq misses -system.cpu2.dcache.demand_misses::cpu2.data 688 # number of demand (read+write) misses -system.cpu2.dcache.demand_misses::total 688 # number of demand (read+write) misses -system.cpu2.dcache.overall_misses::cpu2.data 688 # number of overall misses -system.cpu2.dcache.overall_misses::total 688 # number of overall misses -system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 8601000 # number of ReadReq miss cycles -system.cpu2.dcache.ReadReq_miss_latency::total 8601000 # number of ReadReq miss cycles -system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 3593000 # number of WriteReq miss cycles -system.cpu2.dcache.WriteReq_miss_latency::total 3593000 # number of WriteReq miss cycles -system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 655000 # number of SwapReq miss cycles -system.cpu2.dcache.SwapReq_miss_latency::total 655000 # number of SwapReq miss cycles -system.cpu2.dcache.demand_miss_latency::cpu2.data 12194000 # number of demand (read+write) miss cycles -system.cpu2.dcache.demand_miss_latency::total 12194000 # number of demand (read+write) miss cycles -system.cpu2.dcache.overall_miss_latency::cpu2.data 12194000 # number of overall miss cycles -system.cpu2.dcache.overall_miss_latency::total 12194000 # number of overall miss cycles -system.cpu2.dcache.ReadReq_accesses::cpu2.data 42920 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.ReadReq_accesses::total 42920 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_accesses::cpu2.data 32345 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_accesses::total 32345 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.SwapReq_accesses::cpu2.data 71 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.SwapReq_accesses::total 71 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.demand_accesses::cpu2.data 75265 # number of demand (read+write) accesses -system.cpu2.dcache.demand_accesses::total 75265 # number of demand (read+write) accesses -system.cpu2.dcache.overall_accesses::cpu2.data 75265 # number of overall (read+write) accesses -system.cpu2.dcache.overall_accesses::total 75265 # number of overall (read+write) accesses -system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.012325 # miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_miss_rate::total 0.012325 # miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.004916 # miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_miss_rate::total 0.004916 # miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.816901 # miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_miss_rate::total 0.816901 # miss rate for SwapReq accesses -system.cpu2.dcache.demand_miss_rate::cpu2.data 0.009141 # miss rate for demand accesses -system.cpu2.dcache.demand_miss_rate::total 0.009141 # miss rate for demand accesses -system.cpu2.dcache.overall_miss_rate::cpu2.data 0.009141 # miss rate for overall accesses -system.cpu2.dcache.overall_miss_rate::total 0.009141 # miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 16258.979206 # average ReadReq miss latency -system.cpu2.dcache.ReadReq_avg_miss_latency::total 16258.979206 # average ReadReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 22597.484277 # average WriteReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency::total 22597.484277 # average WriteReq miss latency -system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 11293.103448 # average SwapReq miss latency -system.cpu2.dcache.SwapReq_avg_miss_latency::total 11293.103448 # average SwapReq miss latency -system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 17723.837209 # average overall miss latency -system.cpu2.dcache.demand_avg_miss_latency::total 17723.837209 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 17723.837209 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::total 17723.837209 # average overall miss latency +system.cpu2.dcache.tags.occ_blocks::cpu2.data 26.976674 # Average occupied blocks per requestor +system.cpu2.dcache.tags.occ_percent::cpu2.data 0.052689 # Average percentage of cache occupancy +system.cpu2.dcache.tags.occ_percent::total 0.052689 # Average percentage of cache occupancy +system.cpu2.dcache.tags.occ_task_id_blocks::1024 30 # Occupied blocks per task id +system.cpu2.dcache.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id +system.cpu2.dcache.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id +system.cpu2.dcache.tags.age_task_id_blocks_1024::2 15 # Occupied blocks per task id +system.cpu2.dcache.tags.occ_task_id_percent::1024 0.058594 # Percentage of cache occupancy per task id +system.cpu2.dcache.tags.tag_accesses 357076 # Number of tag accesses +system.cpu2.dcache.tags.data_accesses 357076 # Number of data accesses +system.cpu2.dcache.ReadReq_hits::cpu2.data 50413 # number of ReadReq hits +system.cpu2.dcache.ReadReq_hits::total 50413 # number of ReadReq hits +system.cpu2.dcache.WriteReq_hits::cpu2.data 38109 # number of WriteReq hits +system.cpu2.dcache.WriteReq_hits::total 38109 # number of WriteReq hits +system.cpu2.dcache.SwapReq_hits::cpu2.data 15 # number of SwapReq hits +system.cpu2.dcache.SwapReq_hits::total 15 # number of SwapReq hits +system.cpu2.dcache.demand_hits::cpu2.data 88522 # number of demand (read+write) hits +system.cpu2.dcache.demand_hits::total 88522 # number of demand (read+write) hits +system.cpu2.dcache.overall_hits::cpu2.data 88522 # number of overall hits +system.cpu2.dcache.overall_hits::total 88522 # number of overall hits +system.cpu2.dcache.ReadReq_misses::cpu2.data 463 # number of ReadReq misses +system.cpu2.dcache.ReadReq_misses::total 463 # number of ReadReq misses +system.cpu2.dcache.WriteReq_misses::cpu2.data 152 # number of WriteReq misses +system.cpu2.dcache.WriteReq_misses::total 152 # number of WriteReq misses +system.cpu2.dcache.SwapReq_misses::cpu2.data 53 # number of SwapReq misses +system.cpu2.dcache.SwapReq_misses::total 53 # number of SwapReq misses +system.cpu2.dcache.demand_misses::cpu2.data 615 # number of demand (read+write) misses +system.cpu2.dcache.demand_misses::total 615 # number of demand (read+write) misses +system.cpu2.dcache.overall_misses::cpu2.data 615 # number of overall misses +system.cpu2.dcache.overall_misses::total 615 # number of overall misses +system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 8046000 # number of ReadReq miss cycles +system.cpu2.dcache.ReadReq_miss_latency::total 8046000 # number of ReadReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 3843000 # number of WriteReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::total 3843000 # number of WriteReq miss cycles +system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 809500 # number of SwapReq miss cycles +system.cpu2.dcache.SwapReq_miss_latency::total 809500 # number of SwapReq miss cycles +system.cpu2.dcache.demand_miss_latency::cpu2.data 11889000 # number of demand (read+write) miss cycles +system.cpu2.dcache.demand_miss_latency::total 11889000 # number of demand (read+write) miss cycles +system.cpu2.dcache.overall_miss_latency::cpu2.data 11889000 # number of overall miss cycles +system.cpu2.dcache.overall_miss_latency::total 11889000 # number of overall miss cycles +system.cpu2.dcache.ReadReq_accesses::cpu2.data 50876 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.ReadReq_accesses::total 50876 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses::cpu2.data 38261 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses::total 38261 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.SwapReq_accesses::cpu2.data 68 # number of SwapReq accesses(hits+misses) +system.cpu2.dcache.SwapReq_accesses::total 68 # number of SwapReq accesses(hits+misses) +system.cpu2.dcache.demand_accesses::cpu2.data 89137 # number of demand (read+write) accesses +system.cpu2.dcache.demand_accesses::total 89137 # number of demand (read+write) accesses +system.cpu2.dcache.overall_accesses::cpu2.data 89137 # number of overall (read+write) accesses +system.cpu2.dcache.overall_accesses::total 89137 # number of overall (read+write) accesses +system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.009101 # miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_miss_rate::total 0.009101 # miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.003973 # miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_miss_rate::total 0.003973 # miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.779412 # miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_miss_rate::total 0.779412 # miss rate for SwapReq accesses +system.cpu2.dcache.demand_miss_rate::cpu2.data 0.006899 # miss rate for demand accesses +system.cpu2.dcache.demand_miss_rate::total 0.006899 # miss rate for demand accesses +system.cpu2.dcache.overall_miss_rate::cpu2.data 0.006899 # miss rate for overall accesses +system.cpu2.dcache.overall_miss_rate::total 0.006899 # miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 17377.969762 # average ReadReq miss latency +system.cpu2.dcache.ReadReq_avg_miss_latency::total 17377.969762 # average ReadReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 25282.894737 # average WriteReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::total 25282.894737 # average WriteReq miss latency +system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 15273.584906 # average SwapReq miss latency +system.cpu2.dcache.SwapReq_avg_miss_latency::total 15273.584906 # average SwapReq miss latency +system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 19331.707317 # average overall miss latency +system.cpu2.dcache.demand_avg_miss_latency::total 19331.707317 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 19331.707317 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::total 19331.707317 # average overall miss latency system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1705,517 +1723,525 @@ system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.dcache.fast_writes 0 # number of fast writes performed system.cpu2.dcache.cache_copies 0 # number of cache copies performed -system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 359 # number of ReadReq MSHR hits -system.cpu2.dcache.ReadReq_mshr_hits::total 359 # number of ReadReq MSHR hits -system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 53 # number of WriteReq MSHR hits -system.cpu2.dcache.WriteReq_mshr_hits::total 53 # number of WriteReq MSHR hits -system.cpu2.dcache.demand_mshr_hits::cpu2.data 412 # number of demand (read+write) MSHR hits -system.cpu2.dcache.demand_mshr_hits::total 412 # number of demand (read+write) MSHR hits -system.cpu2.dcache.overall_mshr_hits::cpu2.data 412 # number of overall MSHR hits -system.cpu2.dcache.overall_mshr_hits::total 412 # number of overall MSHR hits -system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 170 # number of ReadReq MSHR misses -system.cpu2.dcache.ReadReq_mshr_misses::total 170 # number of ReadReq MSHR misses -system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 106 # number of WriteReq MSHR misses -system.cpu2.dcache.WriteReq_mshr_misses::total 106 # number of WriteReq MSHR misses -system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 58 # number of SwapReq MSHR misses -system.cpu2.dcache.SwapReq_mshr_misses::total 58 # number of SwapReq MSHR misses -system.cpu2.dcache.demand_mshr_misses::cpu2.data 276 # number of demand (read+write) MSHR misses -system.cpu2.dcache.demand_mshr_misses::total 276 # number of demand (read+write) MSHR misses -system.cpu2.dcache.overall_mshr_misses::cpu2.data 276 # number of overall MSHR misses -system.cpu2.dcache.overall_mshr_misses::total 276 # number of overall MSHR misses -system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1653000 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1653000 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1845000 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1845000 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 597000 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency::total 597000 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3498000 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::total 3498000 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3498000 # number of overall MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::total 3498000 # number of overall MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003961 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003961 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.003277 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.003277 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.816901 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.816901 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.003667 # mshr miss rate for demand accesses -system.cpu2.dcache.demand_mshr_miss_rate::total 0.003667 # mshr miss rate for demand accesses -system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.003667 # mshr miss rate for overall accesses -system.cpu2.dcache.overall_mshr_miss_rate::total 0.003667 # mshr miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 9723.529412 # average ReadReq mshr miss latency -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 9723.529412 # average ReadReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 17405.660377 # average WriteReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 17405.660377 # average WriteReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 10293.103448 # average SwapReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 10293.103448 # average SwapReq mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 12673.913043 # average overall mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::total 12673.913043 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 12673.913043 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::total 12673.913043 # average overall mshr miss latency +system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 298 # number of ReadReq MSHR hits +system.cpu2.dcache.ReadReq_mshr_hits::total 298 # number of ReadReq MSHR hits +system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 47 # number of WriteReq MSHR hits +system.cpu2.dcache.WriteReq_mshr_hits::total 47 # number of WriteReq MSHR hits +system.cpu2.dcache.SwapReq_mshr_hits::cpu2.data 5 # number of SwapReq MSHR hits +system.cpu2.dcache.SwapReq_mshr_hits::total 5 # number of SwapReq MSHR hits +system.cpu2.dcache.demand_mshr_hits::cpu2.data 345 # number of demand (read+write) MSHR hits +system.cpu2.dcache.demand_mshr_hits::total 345 # number of demand (read+write) MSHR hits +system.cpu2.dcache.overall_mshr_hits::cpu2.data 345 # number of overall MSHR hits +system.cpu2.dcache.overall_mshr_hits::total 345 # number of overall MSHR hits +system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 165 # number of ReadReq MSHR misses +system.cpu2.dcache.ReadReq_mshr_misses::total 165 # number of ReadReq MSHR misses +system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 105 # number of WriteReq MSHR misses +system.cpu2.dcache.WriteReq_mshr_misses::total 105 # number of WriteReq MSHR misses +system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 48 # number of SwapReq MSHR misses +system.cpu2.dcache.SwapReq_mshr_misses::total 48 # number of SwapReq MSHR misses +system.cpu2.dcache.demand_mshr_misses::cpu2.data 270 # number of demand (read+write) MSHR misses +system.cpu2.dcache.demand_mshr_misses::total 270 # number of demand (read+write) MSHR misses +system.cpu2.dcache.overall_mshr_misses::cpu2.data 270 # number of overall MSHR misses +system.cpu2.dcache.overall_mshr_misses::total 270 # number of overall MSHR misses +system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1997000 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1997000 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1762500 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1762500 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 756500 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::total 756500 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3759500 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::total 3759500 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3759500 # number of overall MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::total 3759500 # number of overall MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003243 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003243 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.002744 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.002744 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.705882 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.705882 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.003029 # mshr miss rate for demand accesses +system.cpu2.dcache.demand_mshr_miss_rate::total 0.003029 # mshr miss rate for demand accesses +system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.003029 # mshr miss rate for overall accesses +system.cpu2.dcache.overall_mshr_miss_rate::total 0.003029 # mshr miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 12103.030303 # average ReadReq mshr miss latency +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 12103.030303 # average ReadReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 16785.714286 # average WriteReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 16785.714286 # average WriteReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 15760.416667 # average SwapReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 15760.416667 # average SwapReq mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 13924.074074 # average overall mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::total 13924.074074 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 13924.074074 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::total 13924.074074 # average overall mshr miss latency system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.icache.tags.replacements 386 # number of replacements -system.cpu2.icache.tags.tagsinuse 77.661611 # Cycle average of tags in use -system.cpu2.icache.tags.total_refs 22304 # Total number of references to valid blocks. -system.cpu2.icache.tags.sampled_refs 500 # Sample count of references to valid blocks. -system.cpu2.icache.tags.avg_refs 44.608000 # Average number of references to valid blocks. +system.cpu2.icache.tags.replacements 555 # number of replacements +system.cpu2.icache.tags.tagsinuse 101.261159 # Cycle average of tags in use +system.cpu2.icache.tags.total_refs 26702 # Total number of references to valid blocks. +system.cpu2.icache.tags.sampled_refs 694 # Sample count of references to valid blocks. +system.cpu2.icache.tags.avg_refs 38.475504 # Average number of references to valid blocks. system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.icache.tags.occ_blocks::cpu2.inst 77.661611 # Average occupied blocks per requestor -system.cpu2.icache.tags.occ_percent::cpu2.inst 0.151683 # Average percentage of cache occupancy -system.cpu2.icache.tags.occ_percent::total 0.151683 # Average percentage of cache occupancy -system.cpu2.icache.tags.occ_task_id_blocks::1024 114 # Occupied blocks per task id -system.cpu2.icache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id -system.cpu2.icache.tags.age_task_id_blocks_1024::1 103 # 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number of demand (read+write) accesses -system.cpu2.icache.overall_accesses::cpu2.inst 22874 # number of overall (read+write) accesses -system.cpu2.icache.overall_accesses::total 22874 # number of overall (read+write) accesses -system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.024919 # miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_miss_rate::total 0.024919 # miss rate for ReadReq accesses -system.cpu2.icache.demand_miss_rate::cpu2.inst 0.024919 # miss rate for demand accesses -system.cpu2.icache.demand_miss_rate::total 0.024919 # miss rate for demand accesses -system.cpu2.icache.overall_miss_rate::cpu2.inst 0.024919 # miss rate for overall accesses -system.cpu2.icache.overall_miss_rate::total 0.024919 # miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 14201.754386 # average ReadReq miss latency -system.cpu2.icache.ReadReq_avg_miss_latency::total 14201.754386 # average ReadReq miss latency -system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 14201.754386 # average overall miss latency -system.cpu2.icache.demand_avg_miss_latency::total 14201.754386 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 14201.754386 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::total 14201.754386 # average overall miss latency -system.cpu2.icache.blocked_cycles::no_mshrs 5 # number of cycles access was blocked +system.cpu2.icache.tags.occ_blocks::cpu2.inst 101.261159 # Average occupied blocks per requestor +system.cpu2.icache.tags.occ_percent::cpu2.inst 0.197776 # Average percentage of cache occupancy +system.cpu2.icache.tags.occ_percent::total 0.197776 # Average percentage of cache occupancy +system.cpu2.icache.tags.occ_task_id_blocks::1024 139 # Occupied blocks per task id +system.cpu2.icache.tags.age_task_id_blocks_1024::0 21 # Occupied blocks per task id +system.cpu2.icache.tags.age_task_id_blocks_1024::1 90 # Occupied blocks per task id +system.cpu2.icache.tags.age_task_id_blocks_1024::2 28 # Occupied blocks per task id +system.cpu2.icache.tags.occ_task_id_percent::1024 0.271484 # Percentage of cache occupancy per task id +system.cpu2.icache.tags.tag_accesses 28239 # Number of tag accesses +system.cpu2.icache.tags.data_accesses 28239 # Number of data accesses +system.cpu2.icache.ReadReq_hits::cpu2.inst 26702 # number of ReadReq hits +system.cpu2.icache.ReadReq_hits::total 26702 # number of ReadReq hits +system.cpu2.icache.demand_hits::cpu2.inst 26702 # number of demand (read+write) hits +system.cpu2.icache.demand_hits::total 26702 # number of demand (read+write) hits +system.cpu2.icache.overall_hits::cpu2.inst 26702 # number of overall hits +system.cpu2.icache.overall_hits::total 26702 # number of overall hits +system.cpu2.icache.ReadReq_misses::cpu2.inst 843 # number of ReadReq misses +system.cpu2.icache.ReadReq_misses::total 843 # number of ReadReq misses +system.cpu2.icache.demand_misses::cpu2.inst 843 # number of demand (read+write) misses +system.cpu2.icache.demand_misses::total 843 # number of demand (read+write) misses +system.cpu2.icache.overall_misses::cpu2.inst 843 # number of overall misses +system.cpu2.icache.overall_misses::total 843 # number of overall misses +system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 19527000 # number of ReadReq miss cycles +system.cpu2.icache.ReadReq_miss_latency::total 19527000 # number of ReadReq miss cycles +system.cpu2.icache.demand_miss_latency::cpu2.inst 19527000 # number of demand (read+write) miss cycles +system.cpu2.icache.demand_miss_latency::total 19527000 # number of demand (read+write) miss cycles +system.cpu2.icache.overall_miss_latency::cpu2.inst 19527000 # number of overall miss cycles +system.cpu2.icache.overall_miss_latency::total 19527000 # number of overall miss cycles +system.cpu2.icache.ReadReq_accesses::cpu2.inst 27545 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.ReadReq_accesses::total 27545 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.demand_accesses::cpu2.inst 27545 # number of demand (read+write) accesses +system.cpu2.icache.demand_accesses::total 27545 # number of demand (read+write) accesses +system.cpu2.icache.overall_accesses::cpu2.inst 27545 # number of overall (read+write) accesses +system.cpu2.icache.overall_accesses::total 27545 # number of overall (read+write) accesses +system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.030604 # miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_miss_rate::total 0.030604 # miss rate for ReadReq accesses +system.cpu2.icache.demand_miss_rate::cpu2.inst 0.030604 # miss rate for demand accesses +system.cpu2.icache.demand_miss_rate::total 0.030604 # miss rate for demand accesses +system.cpu2.icache.overall_miss_rate::cpu2.inst 0.030604 # miss rate for overall accesses +system.cpu2.icache.overall_miss_rate::total 0.030604 # miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 23163.701068 # average ReadReq miss latency +system.cpu2.icache.ReadReq_avg_miss_latency::total 23163.701068 # average ReadReq miss latency +system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 23163.701068 # average overall miss latency +system.cpu2.icache.demand_avg_miss_latency::total 23163.701068 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 23163.701068 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::total 23163.701068 # average overall miss latency +system.cpu2.icache.blocked_cycles::no_mshrs 220 # number of cycles access was blocked system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu2.icache.blocked::no_mshrs 1 # number of cycles access was blocked +system.cpu2.icache.blocked::no_mshrs 7 # number of cycles access was blocked system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu2.icache.avg_blocked_cycles::no_mshrs 5 # average number of cycles each access was blocked +system.cpu2.icache.avg_blocked_cycles::no_mshrs 31.428571 # average number of cycles each access was blocked system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.icache.fast_writes 0 # number of fast writes performed system.cpu2.icache.cache_copies 0 # number of cache copies performed -system.cpu2.icache.writebacks::writebacks 386 # number of writebacks -system.cpu2.icache.writebacks::total 386 # number of writebacks -system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst 70 # number of ReadReq MSHR hits -system.cpu2.icache.ReadReq_mshr_hits::total 70 # number of ReadReq MSHR hits -system.cpu2.icache.demand_mshr_hits::cpu2.inst 70 # number of demand (read+write) MSHR hits -system.cpu2.icache.demand_mshr_hits::total 70 # number of demand (read+write) MSHR hits -system.cpu2.icache.overall_mshr_hits::cpu2.inst 70 # number of overall MSHR hits -system.cpu2.icache.overall_mshr_hits::total 70 # number of overall MSHR hits -system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 500 # number of ReadReq MSHR misses -system.cpu2.icache.ReadReq_mshr_misses::total 500 # number of ReadReq MSHR misses -system.cpu2.icache.demand_mshr_misses::cpu2.inst 500 # number of demand (read+write) MSHR misses -system.cpu2.icache.demand_mshr_misses::total 500 # number of demand (read+write) MSHR misses -system.cpu2.icache.overall_mshr_misses::cpu2.inst 500 # number of overall MSHR misses -system.cpu2.icache.overall_mshr_misses::total 500 # number of overall MSHR misses -system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 7049500 # number of ReadReq MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_latency::total 7049500 # number of ReadReq MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 7049500 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::total 7049500 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 7049500 # number of overall MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::total 7049500 # number of overall MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.021859 # mshr miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.021859 # mshr miss rate for ReadReq accesses -system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.021859 # mshr miss rate for demand accesses -system.cpu2.icache.demand_mshr_miss_rate::total 0.021859 # mshr miss rate for demand accesses -system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.021859 # mshr miss rate for overall accesses -system.cpu2.icache.overall_mshr_miss_rate::total 0.021859 # mshr miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 14099 # average ReadReq mshr miss latency -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 14099 # average ReadReq mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 14099 # average overall mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::total 14099 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 14099 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::total 14099 # average overall mshr miss latency +system.cpu2.icache.writebacks::writebacks 555 # number of writebacks +system.cpu2.icache.writebacks::total 555 # number of writebacks +system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst 149 # number of ReadReq MSHR hits +system.cpu2.icache.ReadReq_mshr_hits::total 149 # number of ReadReq MSHR hits +system.cpu2.icache.demand_mshr_hits::cpu2.inst 149 # number of demand (read+write) MSHR hits +system.cpu2.icache.demand_mshr_hits::total 149 # number of demand (read+write) MSHR hits +system.cpu2.icache.overall_mshr_hits::cpu2.inst 149 # number of overall MSHR hits +system.cpu2.icache.overall_mshr_hits::total 149 # number of overall MSHR hits +system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 694 # number of ReadReq MSHR misses +system.cpu2.icache.ReadReq_mshr_misses::total 694 # number of ReadReq MSHR misses +system.cpu2.icache.demand_mshr_misses::cpu2.inst 694 # number of demand (read+write) MSHR misses +system.cpu2.icache.demand_mshr_misses::total 694 # number of demand (read+write) MSHR misses +system.cpu2.icache.overall_mshr_misses::cpu2.inst 694 # number of overall MSHR misses +system.cpu2.icache.overall_mshr_misses::total 694 # number of overall MSHR misses +system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 15501500 # number of ReadReq MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_latency::total 15501500 # number of ReadReq MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 15501500 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::total 15501500 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 15501500 # number of overall MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::total 15501500 # number of overall MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.025195 # mshr miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.025195 # mshr miss rate for ReadReq accesses +system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.025195 # mshr miss rate for demand accesses +system.cpu2.icache.demand_mshr_miss_rate::total 0.025195 # mshr miss rate for demand accesses +system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.025195 # mshr miss rate for overall accesses +system.cpu2.icache.overall_mshr_miss_rate::total 0.025195 # mshr miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 22336.455331 # average ReadReq mshr miss latency +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 22336.455331 # average ReadReq mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 22336.455331 # average overall mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::total 22336.455331 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 22336.455331 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::total 22336.455331 # average overall mshr miss latency system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.branchPred.lookups 49230 # Number of BP lookups -system.cpu3.branchPred.condPredicted 45728 # Number of conditional branches predicted -system.cpu3.branchPred.condIncorrect 1271 # Number of conditional branches incorrect -system.cpu3.branchPred.BTBLookups 41796 # Number of BTB lookups -system.cpu3.branchPred.BTBHits 40803 # Number of BTB hits +system.cpu3.branchPred.lookups 57182 # Number of BP lookups +system.cpu3.branchPred.condPredicted 48797 # Number of conditional branches predicted +system.cpu3.branchPred.condIncorrect 2586 # Number of conditional branches incorrect +system.cpu3.branchPred.BTBLookups 48362 # Number of BTB lookups +system.cpu3.branchPred.BTBHits 0 # Number of BTB hits system.cpu3.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu3.branchPred.BTBHitPct 97.624175 # BTB Hit Percentage -system.cpu3.branchPred.usedRAS 906 # Number of times the RAS was used to get a target. +system.cpu3.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage +system.cpu3.branchPred.usedRAS 2121 # Number of times the RAS was used to get a target. system.cpu3.branchPred.RASInCorrect 231 # Number of incorrect RAS predictions. -system.cpu3.numCycles 161890 # number of cpu cycles simulated +system.cpu3.branchPred.indirectLookups 48362 # Number of indirect predictor lookups. +system.cpu3.branchPred.indirectHits 37349 # Number of indirect target hits. +system.cpu3.branchPred.indirectMisses 11013 # Number of indirect misses. +system.cpu3.branchPredindirectMispredicted 1473 # Number of mispredicted indirect branches. +system.cpu3.numCycles 195288 # number of cpu cycles simulated system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu3.fetch.icacheStallCycles 32992 # Number of cycles fetch is stalled on an Icache miss -system.cpu3.fetch.Insts 268412 # Number of instructions fetch has processed -system.cpu3.fetch.Branches 49230 # Number of branches that fetch encountered -system.cpu3.fetch.predictedBranches 41709 # Number of branches that fetch has predicted taken -system.cpu3.fetch.Cycles 124419 # Number of cycles fetch has run and was not squashing or blocked -system.cpu3.fetch.SquashCycles 2697 # Number of cycles fetch has spent squashing +system.cpu3.fetch.icacheStallCycles 45700 # Number of cycles fetch is stalled on an Icache miss +system.cpu3.fetch.Insts 298023 # Number of instructions fetch has processed +system.cpu3.fetch.Branches 57182 # Number of branches that fetch encountered +system.cpu3.fetch.predictedBranches 39470 # Number of branches that fetch has predicted taken +system.cpu3.fetch.Cycles 143366 # Number of cycles fetch has run and was not squashing or blocked +system.cpu3.fetch.SquashCycles 5327 # Number of cycles fetch has spent squashing system.cpu3.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu3.fetch.NoActiveThreadStallCycles 10 # Number of stall cycles due to no active thread to fetch from -system.cpu3.fetch.PendingTrapStallCycles 1165 # Number of stall cycles due to pending traps -system.cpu3.fetch.CacheLines 24017 # Number of cache lines fetched -system.cpu3.fetch.IcacheSquashes 451 # Number of outstanding Icache misses that were squashed -system.cpu3.fetch.rateDist::samples 159937 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::mean 1.678236 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::stdev 2.146445 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.PendingTrapStallCycles 1948 # Number of stall cycles due to pending traps +system.cpu3.fetch.CacheLines 34377 # Number of cache lines fetched +system.cpu3.fetch.IcacheSquashes 1007 # Number of outstanding Icache misses that were squashed +system.cpu3.fetch.rateDist::samples 193690 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::mean 1.538660 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::stdev 2.252819 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::0 63357 39.61% 39.61% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::1 49486 30.94% 70.55% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::2 7847 4.91% 75.46% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::3 3455 2.16% 77.62% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::4 942 0.59% 78.21% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::5 28830 18.03% 96.24% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::6 1207 0.75% 96.99% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::7 797 0.50% 97.49% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::8 4016 2.51% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::0 90820 46.89% 46.89% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::1 51773 26.73% 73.62% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::2 11180 5.77% 79.39% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::3 3385 1.75% 81.14% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::4 629 0.32% 81.46% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::5 24090 12.44% 93.90% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::6 1143 0.59% 94.49% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::7 1449 0.75% 95.24% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::8 9221 4.76% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::total 159937 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.branchRate 0.304095 # Number of branch fetches per cycle -system.cpu3.fetch.rate 1.657990 # Number of inst fetches per cycle -system.cpu3.decode.IdleCycles 17620 # Number of cycles decode is idle -system.cpu3.decode.BlockedCycles 66098 # Number of cycles decode is blocked -system.cpu3.decode.RunCycles 70935 # Number of cycles decode is running -system.cpu3.decode.UnblockCycles 3926 # Number of cycles decode is unblocking -system.cpu3.decode.SquashCycles 1348 # Number of cycles decode is squashing -system.cpu3.decode.DecodedInsts 252986 # Number of instructions handled by decode -system.cpu3.rename.SquashCycles 1348 # Number of cycles rename is squashing -system.cpu3.rename.IdleCycles 18323 # Number of cycles rename is idle -system.cpu3.rename.BlockCycles 31370 # Number of cycles rename is blocking -system.cpu3.rename.serializeStallCycles 13970 # count of cycles rename stalled for serializing inst -system.cpu3.rename.RunCycles 72885 # Number of cycles rename is running -system.cpu3.rename.UnblockCycles 22031 # Number of cycles rename is unblocking -system.cpu3.rename.RenamedInsts 249675 # Number of instructions processed by rename -system.cpu3.rename.IQFullEvents 20026 # Number of times rename has blocked due to IQ full -system.cpu3.rename.LQFullEvents 15 # Number of times rename has blocked due to LQ full -system.cpu3.rename.FullRegisterEvents 3 # Number of times there has been no free registers -system.cpu3.rename.RenamedOperands 174506 # Number of destination operands rename has renamed -system.cpu3.rename.RenameLookups 471658 # Number of register rename lookups that rename has made -system.cpu3.rename.int_rename_lookups 368736 # Number of integer rename lookups -system.cpu3.rename.CommittedMaps 160859 # Number of HB maps that are committed -system.cpu3.rename.UndoneMaps 13647 # Number of HB maps that are undone due to squashing -system.cpu3.rename.serializingInsts 1202 # count of serializing insts renamed -system.cpu3.rename.tempSerializingInsts 1275 # count of temporary serializing insts renamed -system.cpu3.rename.skidInsts 26657 # count of insts added to the skid buffer -system.cpu3.memDep0.insertedLoads 68456 # Number of loads inserted to the mem dependence unit. -system.cpu3.memDep0.insertedStores 31644 # Number of stores inserted to the mem dependence unit. -system.cpu3.memDep0.conflictingLoads 33001 # Number of conflicting loads. -system.cpu3.memDep0.conflictingStores 26549 # Number of conflicting stores. -system.cpu3.iq.iqInstsAdded 205848 # Number of instructions added to the IQ (excludes non-spec) -system.cpu3.iq.iqNonSpecInstsAdded 7559 # Number of non-speculative instructions added to the IQ -system.cpu3.iq.iqInstsIssued 208921 # Number of instructions issued -system.cpu3.iq.iqSquashedInstsIssued 4 # Number of squashed instructions issued -system.cpu3.iq.iqSquashedInstsExamined 12739 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu3.iq.iqSquashedOperandsExamined 10220 # Number of squashed operands that are examined and possibly removed from graph -system.cpu3.iq.iqSquashedNonSpecRemoved 712 # Number of squashed non-spec instructions that were removed -system.cpu3.iq.issued_per_cycle::samples 159937 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::mean 1.306271 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::stdev 1.372225 # Number of insts issued each cycle +system.cpu3.fetch.rateDist::total 193690 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.branchRate 0.292809 # Number of branch fetches per cycle +system.cpu3.fetch.rate 1.526069 # Number of inst fetches per cycle +system.cpu3.decode.IdleCycles 23670 # Number of cycles decode is idle +system.cpu3.decode.BlockedCycles 95373 # Number of cycles decode is blocked +system.cpu3.decode.RunCycles 66026 # Number of cycles decode is running +system.cpu3.decode.UnblockCycles 5948 # Number of cycles decode is unblocking +system.cpu3.decode.SquashCycles 2663 # Number of cycles decode is squashing +system.cpu3.decode.DecodedInsts 265184 # Number of instructions handled by decode +system.cpu3.rename.SquashCycles 2663 # Number of cycles rename is squashing +system.cpu3.rename.IdleCycles 24704 # Number of cycles rename is idle +system.cpu3.rename.BlockCycles 48500 # Number of cycles rename is blocking +system.cpu3.rename.serializeStallCycles 15195 # count of cycles rename stalled for serializing inst +system.cpu3.rename.RunCycles 67410 # Number of cycles rename is running +system.cpu3.rename.UnblockCycles 35208 # Number of cycles rename is unblocking +system.cpu3.rename.RenamedInsts 258083 # Number of instructions processed by rename +system.cpu3.rename.IQFullEvents 30956 # Number of times rename has blocked due to IQ full +system.cpu3.rename.LQFullEvents 14 # Number of times rename has blocked due to LQ full +system.cpu3.rename.RenamedOperands 178302 # Number of destination operands rename has renamed +system.cpu3.rename.RenameLookups 471983 # Number of register rename lookups that rename has made +system.cpu3.rename.int_rename_lookups 372133 # Number of integer rename lookups +system.cpu3.rename.fp_rename_lookups 28 # Number of floating rename lookups +system.cpu3.rename.CommittedMaps 146703 # Number of HB maps that are committed +system.cpu3.rename.UndoneMaps 31599 # Number of HB maps that are undone due to squashing +system.cpu3.rename.serializingInsts 1744 # count of serializing insts renamed +system.cpu3.rename.tempSerializingInsts 1884 # count of temporary serializing insts renamed +system.cpu3.rename.skidInsts 41025 # count of insts added to the skid buffer +system.cpu3.memDep0.insertedLoads 65361 # Number of loads inserted to the mem dependence unit. +system.cpu3.memDep0.insertedStores 28681 # Number of stores inserted to the mem dependence unit. +system.cpu3.memDep0.conflictingLoads 31955 # Number of conflicting loads. +system.cpu3.memDep0.conflictingStores 22074 # Number of conflicting stores. +system.cpu3.iq.iqInstsAdded 204469 # Number of instructions added to the IQ (excludes non-spec) +system.cpu3.iq.iqNonSpecInstsAdded 11525 # Number of non-speculative instructions added to the IQ +system.cpu3.iq.iqInstsIssued 207359 # Number of instructions issued +system.cpu3.iq.iqSquashedInstsIssued 114 # Number of squashed instructions issued +system.cpu3.iq.iqSquashedInstsExamined 27267 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu3.iq.iqSquashedOperandsExamined 21384 # Number of squashed operands that are examined and possibly removed from graph +system.cpu3.iq.iqSquashedNonSpecRemoved 1390 # Number of squashed non-spec instructions that were removed +system.cpu3.iq.issued_per_cycle::samples 193690 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::mean 1.070572 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::stdev 1.351583 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::0 67005 41.89% 41.89% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::1 24940 15.59% 57.49% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::2 31075 19.43% 76.92% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::3 30637 19.16% 96.07% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::4 3376 2.11% 98.18% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::5 1620 1.01% 99.20% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::6 871 0.54% 99.74% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::7 214 0.13% 99.88% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::8 199 0.12% 100.00% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::0 96267 49.70% 49.70% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::1 35951 18.56% 68.26% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::2 27208 14.05% 82.31% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::3 26919 13.90% 96.21% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::4 3677 1.90% 98.11% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::5 1713 0.88% 98.99% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::6 1079 0.56% 99.55% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::7 520 0.27% 99.82% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::8 356 0.18% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::total 159937 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::total 193690 # Number of insts issued each cycle system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntAlu 82 24.70% 24.70% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntMult 0 0.00% 24.70% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntDiv 0 0.00% 24.70% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatAdd 0 0.00% 24.70% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCmp 0 0.00% 24.70% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCvt 0 0.00% 24.70% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatMult 0 0.00% 24.70% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatDiv 0 0.00% 24.70% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 24.70% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAdd 0 0.00% 24.70% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 24.70% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAlu 0 0.00% 24.70% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCmp 0 0.00% 24.70% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCvt 0 0.00% 24.70% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMisc 0 0.00% 24.70% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMult 0 0.00% 24.70% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 24.70% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShift 0 0.00% 24.70% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 24.70% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 24.70% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 24.70% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 24.70% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 24.70% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 24.70% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 24.70% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 24.70% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 24.70% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 24.70% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 24.70% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemRead 41 12.35% 37.05% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemWrite 209 62.95% 100.00% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntAlu 253 45.42% 45.42% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntMult 0 0.00% 45.42% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntDiv 0 0.00% 45.42% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatAdd 0 0.00% 45.42% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCmp 0 0.00% 45.42% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCvt 0 0.00% 45.42% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatMult 0 0.00% 45.42% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatDiv 0 0.00% 45.42% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 45.42% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAdd 0 0.00% 45.42% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 45.42% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAlu 0 0.00% 45.42% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCmp 0 0.00% 45.42% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCvt 0 0.00% 45.42% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMisc 0 0.00% 45.42% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMult 0 0.00% 45.42% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 45.42% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShift 0 0.00% 45.42% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 45.42% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 45.42% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 45.42% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 45.42% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 45.42% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 45.42% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 45.42% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 45.42% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 45.42% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 45.42% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 45.42% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemRead 65 11.67% 57.09% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemWrite 239 42.91% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu3.iq.FU_type_0::IntAlu 103999 49.78% 49.78% # Type of FU issued -system.cpu3.iq.FU_type_0::IntMult 0 0.00% 49.78% # Type of FU issued -system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 49.78% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 49.78% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 49.78% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 49.78% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 49.78% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 49.78% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 49.78% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 49.78% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 49.78% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 49.78% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 49.78% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 49.78% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 49.78% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 49.78% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 49.78% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 49.78% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.78% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 49.78% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.78% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.78% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.78% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.78% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.78% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.78% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 49.78% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.78% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.78% # Type of FU issued -system.cpu3.iq.FU_type_0::MemRead 73864 35.35% 85.13% # Type of FU issued -system.cpu3.iq.FU_type_0::MemWrite 31058 14.87% 100.00% # Type of FU issued +system.cpu3.iq.FU_type_0::IntAlu 106203 51.22% 51.22% # Type of FU issued +system.cpu3.iq.FU_type_0::IntMult 0 0.00% 51.22% # Type of FU issued +system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 51.22% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 51.22% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 51.22% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 51.22% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 51.22% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 51.22% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 51.22% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 51.22% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 51.22% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 51.22% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 51.22% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 51.22% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 51.22% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 51.22% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 51.22% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 51.22% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 51.22% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 51.22% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 51.22% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 51.22% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 51.22% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 51.22% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 51.22% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 51.22% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 51.22% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 51.22% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 51.22% # Type of FU issued +system.cpu3.iq.FU_type_0::MemRead 73580 35.48% 86.70% # Type of FU issued +system.cpu3.iq.FU_type_0::MemWrite 27576 13.30% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu3.iq.FU_type_0::total 208921 # Type of FU issued -system.cpu3.iq.rate 1.290512 # Inst issue rate -system.cpu3.iq.fu_busy_cnt 332 # FU busy when requested -system.cpu3.iq.fu_busy_rate 0.001589 # FU busy rate (busy events/executed inst) -system.cpu3.iq.int_inst_queue_reads 578115 # Number of integer instruction queue reads -system.cpu3.iq.int_inst_queue_writes 226182 # Number of integer instruction queue writes -system.cpu3.iq.int_inst_queue_wakeup_accesses 207437 # Number of integer instruction queue wakeup accesses +system.cpu3.iq.FU_type_0::total 207359 # Type of FU issued +system.cpu3.iq.rate 1.061811 # Inst issue rate +system.cpu3.iq.fu_busy_cnt 557 # FU busy when requested +system.cpu3.iq.fu_busy_rate 0.002686 # FU busy rate (busy events/executed inst) +system.cpu3.iq.int_inst_queue_reads 609079 # Number of integer instruction queue reads +system.cpu3.iq.int_inst_queue_writes 243241 # Number of integer instruction queue writes +system.cpu3.iq.int_inst_queue_wakeup_accesses 202956 # Number of integer instruction queue wakeup accesses system.cpu3.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads -system.cpu3.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes +system.cpu3.iq.fp_inst_queue_writes 56 # Number of floating instruction queue writes system.cpu3.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu3.iq.int_alu_accesses 209253 # Number of integer alu accesses +system.cpu3.iq.int_alu_accesses 207916 # Number of integer alu accesses system.cpu3.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu3.iew.lsq.thread0.forwLoads 26373 # Number of loads that had data forwarded from stores +system.cpu3.iew.lsq.thread0.forwLoads 22032 # Number of loads that had data forwarded from stores system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu3.iew.lsq.thread0.squashedLoads 2521 # Number of loads squashed -system.cpu3.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed +system.cpu3.iew.lsq.thread0.squashedLoads 4860 # Number of loads squashed +system.cpu3.iew.lsq.thread0.ignoredResponses 37 # Number of memory responses ignored because the instruction is squashed system.cpu3.iew.lsq.thread0.memOrderViolation 36 # Number of memory ordering violations -system.cpu3.iew.lsq.thread0.squashedStores 1480 # Number of stores squashed +system.cpu3.iew.lsq.thread0.squashedStores 2877 # Number of stores squashed system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu3.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu3.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu3.iew.iewSquashCycles 1348 # Number of cycles IEW is squashing -system.cpu3.iew.iewBlockCycles 8395 # Number of cycles IEW is blocking -system.cpu3.iew.iewUnblockCycles 63 # Number of cycles IEW is unblocking -system.cpu3.iew.iewDispatchedInsts 247262 # Number of instructions dispatched to IQ -system.cpu3.iew.iewDispSquashedInsts 160 # Number of squashed instructions skipped by dispatch -system.cpu3.iew.iewDispLoadInsts 68456 # Number of dispatched load instructions -system.cpu3.iew.iewDispStoreInsts 31644 # Number of dispatched store instructions -system.cpu3.iew.iewDispNonSpecInsts 1148 # Number of dispatched non-speculative instructions -system.cpu3.iew.iewIQFullEvents 36 # Number of times the IQ has become full, causing a stall +system.cpu3.iew.iewSquashCycles 2663 # Number of cycles IEW is squashing +system.cpu3.iew.iewBlockCycles 13076 # Number of cycles IEW is blocking +system.cpu3.iew.iewUnblockCycles 57 # Number of cycles IEW is unblocking +system.cpu3.iew.iewDispatchedInsts 249222 # Number of instructions dispatched to IQ +system.cpu3.iew.iewDispSquashedInsts 349 # Number of squashed instructions skipped by dispatch +system.cpu3.iew.iewDispLoadInsts 65361 # Number of dispatched load instructions +system.cpu3.iew.iewDispStoreInsts 28681 # Number of dispatched store instructions +system.cpu3.iew.iewDispNonSpecInsts 1596 # Number of dispatched non-speculative instructions +system.cpu3.iew.iewIQFullEvents 28 # Number of times the IQ has become full, causing a stall system.cpu3.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu3.iew.memOrderViolationEvents 36 # Number of memory order violations -system.cpu3.iew.predictedTakenIncorrect 438 # Number of branches that were predicted taken incorrectly -system.cpu3.iew.predictedNotTakenIncorrect 1065 # Number of branches that were predicted not taken incorrectly -system.cpu3.iew.branchMispredicts 1503 # Number of branch mispredicts detected at execute -system.cpu3.iew.iewExecutedInsts 207928 # Number of executed instructions -system.cpu3.iew.iewExecLoadInsts 67431 # Number of load instructions executed -system.cpu3.iew.iewExecSquashedInsts 993 # Number of squashed instructions skipped in execute +system.cpu3.iew.predictedTakenIncorrect 455 # Number of branches that were predicted taken incorrectly +system.cpu3.iew.predictedNotTakenIncorrect 2781 # Number of branches that were predicted not taken incorrectly +system.cpu3.iew.branchMispredicts 3236 # Number of branch mispredicts detected at execute +system.cpu3.iew.iewExecutedInsts 204483 # Number of executed instructions +system.cpu3.iew.iewExecLoadInsts 63509 # Number of load instructions executed +system.cpu3.iew.iewExecSquashedInsts 2876 # Number of squashed instructions skipped in execute system.cpu3.iew.exec_swp 0 # number of swp insts executed -system.cpu3.iew.exec_nop 33855 # number of nop insts executed -system.cpu3.iew.exec_refs 98404 # number of memory reference insts executed -system.cpu3.iew.exec_branches 43312 # Number of branches executed -system.cpu3.iew.exec_stores 30973 # Number of stores executed -system.cpu3.iew.exec_rate 1.284378 # Inst execution rate -system.cpu3.iew.wb_sent 207701 # cumulative count of insts sent to commit -system.cpu3.iew.wb_count 207437 # cumulative count of insts written-back -system.cpu3.iew.wb_producers 116002 # num instructions producing a value -system.cpu3.iew.wb_consumers 122598 # num instructions consuming a value -system.cpu3.iew.wb_rate 1.281345 # insts written-back per cycle -system.cpu3.iew.wb_fanout 0.946198 # average fanout of values written-back -system.cpu3.commit.commitSquashedInsts 13505 # The number of squashed insts skipped by commit -system.cpu3.commit.commitNonSpecStalls 6847 # The number of times commit has been forced to stall to communicate backwards -system.cpu3.commit.branchMispredicts 1271 # The number of times a branch was mispredicted -system.cpu3.commit.committed_per_cycle::samples 157409 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::mean 1.484744 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::stdev 1.997930 # Number of insts commited each cycle +system.cpu3.iew.exec_nop 33228 # number of nop insts executed +system.cpu3.iew.exec_refs 90738 # number of memory reference insts executed +system.cpu3.iew.exec_branches 43690 # Number of branches executed +system.cpu3.iew.exec_stores 27229 # Number of stores executed +system.cpu3.iew.exec_rate 1.047084 # Inst execution rate +system.cpu3.iew.wb_sent 203493 # cumulative count of insts sent to commit +system.cpu3.iew.wb_count 202956 # cumulative count of insts written-back +system.cpu3.iew.wb_producers 108735 # num instructions producing a value +system.cpu3.iew.wb_consumers 116603 # num instructions consuming a value +system.cpu3.iew.wb_rate 1.039265 # insts written-back per cycle +system.cpu3.iew.wb_fanout 0.932523 # average fanout of values written-back +system.cpu3.commit.commitSquashedInsts 28499 # The number of squashed insts skipped by commit +system.cpu3.commit.commitNonSpecStalls 10135 # The number of times commit has been forced to stall to communicate backwards +system.cpu3.commit.branchMispredicts 2586 # The number of times a branch was mispredicted +system.cpu3.commit.committed_per_cycle::samples 188297 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::mean 1.172069 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::stdev 1.830514 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::0 73609 46.76% 46.76% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::1 39844 25.31% 72.08% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::2 5242 3.33% 75.41% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::3 7652 4.86% 80.27% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::4 1542 0.98% 81.25% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::5 26417 16.78% 98.03% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::6 849 0.54% 98.57% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::7 951 0.60% 99.17% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::8 1303 0.83% 100.00% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::0 105729 56.15% 56.15% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::1 39844 21.16% 77.31% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::2 5499 2.92% 80.23% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::3 10725 5.70% 85.93% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::4 1244 0.66% 86.59% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::5 22268 11.83% 98.41% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::6 755 0.40% 98.81% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::7 1030 0.55% 99.36% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::8 1203 0.64% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::total 157409 # Number of insts commited each cycle -system.cpu3.commit.committedInsts 233712 # Number of instructions committed -system.cpu3.commit.committedOps 233712 # Number of ops (including micro ops) committed +system.cpu3.commit.committed_per_cycle::total 188297 # Number of insts commited each cycle +system.cpu3.commit.committedInsts 220697 # Number of instructions committed +system.cpu3.commit.committedOps 220697 # Number of ops (including micro ops) committed system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu3.commit.refs 96099 # Number of memory references committed -system.cpu3.commit.loads 65935 # Number of loads committed -system.cpu3.commit.membars 6131 # Number of memory barriers committed -system.cpu3.commit.branches 42256 # Number of branches committed +system.cpu3.commit.refs 86305 # Number of memory references committed +system.cpu3.commit.loads 60501 # Number of loads committed +system.cpu3.commit.membars 9419 # Number of memory barriers committed +system.cpu3.commit.branches 41182 # Number of branches committed system.cpu3.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu3.commit.int_insts 160475 # Number of committed integer instructions. +system.cpu3.commit.int_insts 149608 # Number of committed integer instructions. system.cpu3.commit.function_calls 322 # Number of function calls committed. -system.cpu3.commit.op_class_0::No_OpClass 33044 14.14% 14.14% # Class of committed instruction -system.cpu3.commit.op_class_0::IntAlu 98438 42.12% 56.26% # Class of committed instruction -system.cpu3.commit.op_class_0::IntMult 0 0.00% 56.26% # Class of committed instruction -system.cpu3.commit.op_class_0::IntDiv 0 0.00% 56.26% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 56.26% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 56.26% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 56.26% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatMult 0 0.00% 56.26% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 56.26% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 56.26% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 56.26% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 56.26% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdAlu 0 0.00% 56.26% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdCmp 0 0.00% 56.26% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdCvt 0 0.00% 56.26% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdMisc 0 0.00% 56.26% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdMult 0 0.00% 56.26% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 56.26% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdShift 0 0.00% 56.26% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 56.26% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 56.26% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 56.26% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 56.26% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 56.26% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 56.26% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 56.26% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatMisc 0 0.00% 56.26% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 56.26% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 56.26% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 56.26% # Class of committed instruction -system.cpu3.commit.op_class_0::MemRead 72066 30.84% 87.09% # Class of committed instruction -system.cpu3.commit.op_class_0::MemWrite 30164 12.91% 100.00% # Class of committed instruction +system.cpu3.commit.op_class_0::No_OpClass 31970 14.49% 14.49% # Class of committed instruction +system.cpu3.commit.op_class_0::IntAlu 93003 42.14% 56.63% # Class of committed instruction +system.cpu3.commit.op_class_0::IntMult 0 0.00% 56.63% # Class of committed instruction +system.cpu3.commit.op_class_0::IntDiv 0 0.00% 56.63% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 56.63% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 56.63% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 56.63% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatMult 0 0.00% 56.63% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 56.63% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 56.63% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 56.63% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 56.63% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdAlu 0 0.00% 56.63% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdCmp 0 0.00% 56.63% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdCvt 0 0.00% 56.63% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdMisc 0 0.00% 56.63% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdMult 0 0.00% 56.63% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 56.63% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdShift 0 0.00% 56.63% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 56.63% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 56.63% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 56.63% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 56.63% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 56.63% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 56.63% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 56.63% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMisc 0 0.00% 56.63% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 56.63% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 56.63% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 56.63% # Class of committed instruction +system.cpu3.commit.op_class_0::MemRead 69920 31.68% 88.31% # Class of committed instruction +system.cpu3.commit.op_class_0::MemWrite 25804 11.69% 100.00% # Class of committed instruction system.cpu3.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu3.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu3.commit.op_class_0::total 233712 # Class of committed instruction -system.cpu3.commit.bw_lim_events 1303 # number cycles where commit BW limit reached -system.cpu3.rob.rob_reads 402737 # The number of ROB reads -system.cpu3.rob.rob_writes 496962 # The number of ROB writes -system.cpu3.timesIdled 208 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu3.idleCycles 1953 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu3.quiesceCycles 46007 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu3.committedInsts 194537 # Number of Instructions Simulated -system.cpu3.committedOps 194537 # Number of Ops (including micro ops) Simulated -system.cpu3.cpi 0.832181 # CPI: Cycles Per Instruction -system.cpu3.cpi_total 0.832181 # CPI: Total CPI of All Threads -system.cpu3.ipc 1.201662 # IPC: Instructions Per Cycle -system.cpu3.ipc_total 1.201662 # IPC: Total IPC of All Threads -system.cpu3.int_regfile_reads 355006 # number of integer regfile reads -system.cpu3.int_regfile_writes 166699 # number of integer regfile writes +system.cpu3.commit.op_class_0::total 220697 # Class of committed instruction +system.cpu3.commit.bw_lim_events 1203 # number cycles where commit BW limit reached +system.cpu3.rob.rob_reads 435704 # The number of ROB reads +system.cpu3.rob.rob_writes 503857 # The number of ROB writes +system.cpu3.timesIdled 220 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu3.idleCycles 1598 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu3.quiesceCycles 47785 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu3.committedInsts 179308 # Number of Instructions Simulated +system.cpu3.committedOps 179308 # Number of Ops (including micro ops) Simulated +system.cpu3.cpi 1.089120 # CPI: Cycles Per Instruction +system.cpu3.cpi_total 1.089120 # CPI: Total CPI of All Threads +system.cpu3.ipc 0.918172 # IPC: Instructions Per Cycle +system.cpu3.ipc_total 0.918172 # IPC: Total IPC of All Threads +system.cpu3.int_regfile_reads 337868 # number of integer regfile reads +system.cpu3.int_regfile_writes 159407 # number of integer regfile writes system.cpu3.fp_regfile_writes 64 # number of floating regfile writes -system.cpu3.misc_regfile_reads 100037 # number of misc regfile reads +system.cpu3.misc_regfile_reads 92688 # number of misc regfile reads system.cpu3.misc_regfile_writes 648 # number of misc regfile writes system.cpu3.dcache.tags.replacements 0 # number of replacements -system.cpu3.dcache.tags.tagsinuse 24.251319 # Cycle average of tags in use -system.cpu3.dcache.tags.total_refs 36167 # Total number of references to valid blocks. -system.cpu3.dcache.tags.sampled_refs 28 # Sample count of references to valid blocks. -system.cpu3.dcache.tags.avg_refs 1291.678571 # Average number of references to valid blocks. +system.cpu3.dcache.tags.tagsinuse 25.364861 # Cycle average of tags in use +system.cpu3.dcache.tags.total_refs 33092 # Total number of references to valid blocks. +system.cpu3.dcache.tags.sampled_refs 30 # Sample count of references to valid blocks. +system.cpu3.dcache.tags.avg_refs 1103.066667 # Average number of references to valid blocks. system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.dcache.tags.occ_blocks::cpu3.data 24.251319 # Average occupied blocks per requestor -system.cpu3.dcache.tags.occ_percent::cpu3.data 0.047366 # Average percentage of cache occupancy -system.cpu3.dcache.tags.occ_percent::total 0.047366 # Average percentage of cache occupancy -system.cpu3.dcache.tags.occ_task_id_blocks::1024 28 # Occupied blocks per task id -system.cpu3.dcache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id -system.cpu3.dcache.tags.occ_task_id_percent::1024 0.054688 # Percentage of cache occupancy per task id -system.cpu3.dcache.tags.tag_accesses 285043 # Number of tag accesses -system.cpu3.dcache.tags.data_accesses 285043 # Number of data accesses -system.cpu3.dcache.ReadReq_hits::cpu3.data 40546 # number of ReadReq hits -system.cpu3.dcache.ReadReq_hits::total 40546 # number of ReadReq hits -system.cpu3.dcache.WriteReq_hits::cpu3.data 29945 # number of WriteReq hits -system.cpu3.dcache.WriteReq_hits::total 29945 # number of WriteReq hits -system.cpu3.dcache.SwapReq_hits::cpu3.data 17 # number of SwapReq hits -system.cpu3.dcache.SwapReq_hits::total 17 # number of SwapReq hits -system.cpu3.dcache.demand_hits::cpu3.data 70491 # number of demand (read+write) hits -system.cpu3.dcache.demand_hits::total 70491 # number of demand (read+write) hits -system.cpu3.dcache.overall_hits::cpu3.data 70491 # number of overall hits -system.cpu3.dcache.overall_hits::total 70491 # number of overall hits -system.cpu3.dcache.ReadReq_misses::cpu3.data 489 # number of ReadReq misses -system.cpu3.dcache.ReadReq_misses::total 489 # number of ReadReq misses -system.cpu3.dcache.WriteReq_misses::cpu3.data 149 # number of WriteReq misses -system.cpu3.dcache.WriteReq_misses::total 149 # number of WriteReq misses -system.cpu3.dcache.SwapReq_misses::cpu3.data 53 # number of SwapReq misses -system.cpu3.dcache.SwapReq_misses::total 53 # number of SwapReq misses -system.cpu3.dcache.demand_misses::cpu3.data 638 # number of demand (read+write) misses -system.cpu3.dcache.demand_misses::total 638 # number of demand (read+write) misses -system.cpu3.dcache.overall_misses::cpu3.data 638 # number of overall misses -system.cpu3.dcache.overall_misses::total 638 # number of overall misses -system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 8138500 # number of ReadReq miss cycles -system.cpu3.dcache.ReadReq_miss_latency::total 8138500 # number of ReadReq miss cycles -system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 3781500 # number of WriteReq miss cycles -system.cpu3.dcache.WriteReq_miss_latency::total 3781500 # number of WriteReq miss cycles -system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 606500 # number of SwapReq miss cycles -system.cpu3.dcache.SwapReq_miss_latency::total 606500 # number of SwapReq miss cycles -system.cpu3.dcache.demand_miss_latency::cpu3.data 11920000 # number of demand (read+write) miss cycles -system.cpu3.dcache.demand_miss_latency::total 11920000 # number of demand (read+write) miss cycles -system.cpu3.dcache.overall_miss_latency::cpu3.data 11920000 # number of overall miss cycles -system.cpu3.dcache.overall_miss_latency::total 11920000 # number of overall miss cycles -system.cpu3.dcache.ReadReq_accesses::cpu3.data 41035 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.ReadReq_accesses::total 41035 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_accesses::cpu3.data 30094 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_accesses::total 30094 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.tags.occ_blocks::cpu3.data 25.364861 # Average occupied blocks per requestor +system.cpu3.dcache.tags.occ_percent::cpu3.data 0.049541 # Average percentage of cache occupancy +system.cpu3.dcache.tags.occ_percent::total 0.049541 # Average percentage of cache occupancy +system.cpu3.dcache.tags.occ_task_id_blocks::1024 30 # Occupied blocks per task id +system.cpu3.dcache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id +system.cpu3.dcache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id +system.cpu3.dcache.tags.occ_task_id_percent::1024 0.058594 # Percentage of cache occupancy per task id +system.cpu3.dcache.tags.tag_accesses 269290 # Number of tag accesses +system.cpu3.dcache.tags.data_accesses 269290 # Number of data accesses +system.cpu3.dcache.ReadReq_hits::cpu3.data 40990 # number of ReadReq hits +system.cpu3.dcache.ReadReq_hits::total 40990 # number of ReadReq hits +system.cpu3.dcache.WriteReq_hits::cpu3.data 25593 # number of WriteReq hits +system.cpu3.dcache.WriteReq_hits::total 25593 # number of WriteReq hits +system.cpu3.dcache.SwapReq_hits::cpu3.data 15 # number of SwapReq hits +system.cpu3.dcache.SwapReq_hits::total 15 # number of SwapReq hits +system.cpu3.dcache.demand_hits::cpu3.data 66583 # number of demand (read+write) hits +system.cpu3.dcache.demand_hits::total 66583 # number of demand (read+write) hits +system.cpu3.dcache.overall_hits::cpu3.data 66583 # number of overall hits +system.cpu3.dcache.overall_hits::total 66583 # number of overall hits +system.cpu3.dcache.ReadReq_misses::cpu3.data 463 # number of ReadReq misses +system.cpu3.dcache.ReadReq_misses::total 463 # number of ReadReq misses +system.cpu3.dcache.WriteReq_misses::cpu3.data 141 # number of WriteReq misses +system.cpu3.dcache.WriteReq_misses::total 141 # number of WriteReq misses +system.cpu3.dcache.SwapReq_misses::cpu3.data 55 # number of SwapReq misses +system.cpu3.dcache.SwapReq_misses::total 55 # number of SwapReq misses +system.cpu3.dcache.demand_misses::cpu3.data 604 # number of demand (read+write) misses +system.cpu3.dcache.demand_misses::total 604 # number of demand (read+write) misses +system.cpu3.dcache.overall_misses::cpu3.data 604 # number of overall misses +system.cpu3.dcache.overall_misses::total 604 # number of overall misses +system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 7157000 # number of ReadReq miss cycles +system.cpu3.dcache.ReadReq_miss_latency::total 7157000 # number of ReadReq miss cycles +system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 3001000 # number of WriteReq miss cycles +system.cpu3.dcache.WriteReq_miss_latency::total 3001000 # number of WriteReq miss cycles +system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 868000 # number of SwapReq miss cycles +system.cpu3.dcache.SwapReq_miss_latency::total 868000 # number of SwapReq miss cycles +system.cpu3.dcache.demand_miss_latency::cpu3.data 10158000 # number of demand (read+write) miss cycles +system.cpu3.dcache.demand_miss_latency::total 10158000 # number of demand (read+write) miss cycles +system.cpu3.dcache.overall_miss_latency::cpu3.data 10158000 # number of overall miss cycles +system.cpu3.dcache.overall_miss_latency::total 10158000 # number of overall miss cycles +system.cpu3.dcache.ReadReq_accesses::cpu3.data 41453 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.ReadReq_accesses::total 41453 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_accesses::cpu3.data 25734 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_accesses::total 25734 # number of WriteReq accesses(hits+misses) system.cpu3.dcache.SwapReq_accesses::cpu3.data 70 # number of SwapReq accesses(hits+misses) system.cpu3.dcache.SwapReq_accesses::total 70 # number of SwapReq accesses(hits+misses) -system.cpu3.dcache.demand_accesses::cpu3.data 71129 # number of demand (read+write) accesses -system.cpu3.dcache.demand_accesses::total 71129 # number of demand (read+write) accesses -system.cpu3.dcache.overall_accesses::cpu3.data 71129 # number of overall (read+write) accesses -system.cpu3.dcache.overall_accesses::total 71129 # number of overall (read+write) accesses -system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.011917 # miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_miss_rate::total 0.011917 # miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.004951 # miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_miss_rate::total 0.004951 # miss rate for WriteReq accesses -system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.757143 # miss rate for SwapReq accesses -system.cpu3.dcache.SwapReq_miss_rate::total 0.757143 # miss rate for SwapReq accesses -system.cpu3.dcache.demand_miss_rate::cpu3.data 0.008970 # miss rate for demand accesses -system.cpu3.dcache.demand_miss_rate::total 0.008970 # miss rate for demand accesses -system.cpu3.dcache.overall_miss_rate::cpu3.data 0.008970 # miss rate for overall accesses -system.cpu3.dcache.overall_miss_rate::total 0.008970 # miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 16643.149284 # average ReadReq miss latency -system.cpu3.dcache.ReadReq_avg_miss_latency::total 16643.149284 # average ReadReq miss latency -system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 25379.194631 # average WriteReq miss latency -system.cpu3.dcache.WriteReq_avg_miss_latency::total 25379.194631 # average WriteReq miss latency -system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 11443.396226 # average SwapReq miss latency -system.cpu3.dcache.SwapReq_avg_miss_latency::total 11443.396226 # average SwapReq miss latency -system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 18683.385580 # average overall miss latency -system.cpu3.dcache.demand_avg_miss_latency::total 18683.385580 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 18683.385580 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency::total 18683.385580 # average overall miss latency +system.cpu3.dcache.demand_accesses::cpu3.data 67187 # number of demand (read+write) accesses +system.cpu3.dcache.demand_accesses::total 67187 # number of demand (read+write) accesses +system.cpu3.dcache.overall_accesses::cpu3.data 67187 # number of overall (read+write) accesses +system.cpu3.dcache.overall_accesses::total 67187 # number of overall (read+write) accesses +system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.011169 # miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_miss_rate::total 0.011169 # miss rate for ReadReq accesses +system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.005479 # miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_miss_rate::total 0.005479 # miss rate for WriteReq accesses +system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.785714 # miss rate for SwapReq accesses +system.cpu3.dcache.SwapReq_miss_rate::total 0.785714 # miss rate for SwapReq accesses +system.cpu3.dcache.demand_miss_rate::cpu3.data 0.008990 # miss rate for demand accesses +system.cpu3.dcache.demand_miss_rate::total 0.008990 # miss rate for demand accesses +system.cpu3.dcache.overall_miss_rate::cpu3.data 0.008990 # miss rate for overall accesses +system.cpu3.dcache.overall_miss_rate::total 0.008990 # miss rate for overall accesses +system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 15457.883369 # average ReadReq miss latency +system.cpu3.dcache.ReadReq_avg_miss_latency::total 15457.883369 # average ReadReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 21283.687943 # average WriteReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::total 21283.687943 # average WriteReq miss latency +system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 15781.818182 # average SwapReq miss latency +system.cpu3.dcache.SwapReq_avg_miss_latency::total 15781.818182 # average SwapReq miss latency +system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 16817.880795 # average overall miss latency +system.cpu3.dcache.demand_avg_miss_latency::total 16817.880795 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 16817.880795 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::total 16817.880795 # average overall miss latency system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -2224,106 +2250,109 @@ system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.dcache.fast_writes 0 # number of fast writes performed system.cpu3.dcache.cache_copies 0 # number of cache copies performed -system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data 328 # number of ReadReq MSHR hits -system.cpu3.dcache.ReadReq_mshr_hits::total 328 # number of ReadReq MSHR hits -system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data 46 # number of WriteReq MSHR hits -system.cpu3.dcache.WriteReq_mshr_hits::total 46 # number of WriteReq MSHR hits -system.cpu3.dcache.demand_mshr_hits::cpu3.data 374 # number of demand (read+write) MSHR hits -system.cpu3.dcache.demand_mshr_hits::total 374 # number of demand (read+write) MSHR hits -system.cpu3.dcache.overall_mshr_hits::cpu3.data 374 # number of overall MSHR hits -system.cpu3.dcache.overall_mshr_hits::total 374 # number of overall MSHR hits -system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 161 # number of ReadReq MSHR misses -system.cpu3.dcache.ReadReq_mshr_misses::total 161 # number of ReadReq MSHR misses -system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 103 # number of WriteReq MSHR misses -system.cpu3.dcache.WriteReq_mshr_misses::total 103 # number of WriteReq MSHR misses -system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 53 # number of SwapReq MSHR misses -system.cpu3.dcache.SwapReq_mshr_misses::total 53 # number of SwapReq MSHR misses -system.cpu3.dcache.demand_mshr_misses::cpu3.data 264 # number of demand (read+write) MSHR misses -system.cpu3.dcache.demand_mshr_misses::total 264 # number of demand (read+write) MSHR misses -system.cpu3.dcache.overall_mshr_misses::cpu3.data 264 # number of overall MSHR misses -system.cpu3.dcache.overall_mshr_misses::total 264 # number of overall MSHR misses -system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 1609000 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_latency::total 1609000 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 2139500 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency::total 2139500 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 553500 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.SwapReq_mshr_miss_latency::total 553500 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 3748500 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::total 3748500 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 3748500 # number of overall MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::total 3748500 # number of overall MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003923 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003923 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.003423 # mshr miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.003423 # mshr miss rate for WriteReq accesses -system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.757143 # mshr miss rate for SwapReq accesses -system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.757143 # mshr miss rate for SwapReq accesses -system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.003712 # mshr miss rate for demand accesses -system.cpu3.dcache.demand_mshr_miss_rate::total 0.003712 # mshr miss rate for demand accesses -system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.003712 # mshr miss rate for overall accesses -system.cpu3.dcache.overall_mshr_miss_rate::total 0.003712 # mshr miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 9993.788820 # average ReadReq mshr miss latency -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 9993.788820 # average ReadReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 20771.844660 # average WriteReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 20771.844660 # average WriteReq mshr miss latency -system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 10443.396226 # average SwapReq mshr miss latency -system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 10443.396226 # average SwapReq mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 14198.863636 # average overall mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency::total 14198.863636 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 14198.863636 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::total 14198.863636 # average overall mshr miss latency +system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data 291 # number of ReadReq MSHR hits +system.cpu3.dcache.ReadReq_mshr_hits::total 291 # number of ReadReq MSHR hits +system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data 35 # number of WriteReq MSHR hits +system.cpu3.dcache.WriteReq_mshr_hits::total 35 # number of WriteReq MSHR hits +system.cpu3.dcache.SwapReq_mshr_hits::cpu3.data 4 # number of SwapReq MSHR hits +system.cpu3.dcache.SwapReq_mshr_hits::total 4 # number of SwapReq MSHR hits +system.cpu3.dcache.demand_mshr_hits::cpu3.data 326 # number of demand (read+write) MSHR hits +system.cpu3.dcache.demand_mshr_hits::total 326 # number of demand (read+write) MSHR hits +system.cpu3.dcache.overall_mshr_hits::cpu3.data 326 # number of overall MSHR hits +system.cpu3.dcache.overall_mshr_hits::total 326 # number of overall MSHR hits +system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 172 # number of ReadReq MSHR misses +system.cpu3.dcache.ReadReq_mshr_misses::total 172 # number of ReadReq MSHR misses +system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 106 # number of WriteReq MSHR misses +system.cpu3.dcache.WriteReq_mshr_misses::total 106 # number of WriteReq MSHR misses +system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 51 # number of SwapReq MSHR misses +system.cpu3.dcache.SwapReq_mshr_misses::total 51 # number of SwapReq MSHR misses +system.cpu3.dcache.demand_mshr_misses::cpu3.data 278 # number of demand (read+write) MSHR misses +system.cpu3.dcache.demand_mshr_misses::total 278 # number of demand (read+write) MSHR misses +system.cpu3.dcache.overall_mshr_misses::cpu3.data 278 # number of overall MSHR misses +system.cpu3.dcache.overall_mshr_misses::total 278 # number of overall MSHR misses +system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 1798500 # number of ReadReq MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_latency::total 1798500 # number of ReadReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1645500 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1645500 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 813000 # number of SwapReq MSHR miss cycles +system.cpu3.dcache.SwapReq_mshr_miss_latency::total 813000 # number of SwapReq MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 3444000 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_latency::total 3444000 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 3444000 # number of overall MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::total 3444000 # number of overall MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.004149 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.004149 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.004119 # mshr miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.004119 # mshr miss rate for WriteReq accesses +system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.728571 # mshr miss rate for SwapReq accesses +system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.728571 # mshr miss rate for SwapReq accesses +system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.004138 # mshr miss rate for demand accesses +system.cpu3.dcache.demand_mshr_miss_rate::total 0.004138 # mshr miss rate for demand accesses +system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.004138 # mshr miss rate for overall accesses +system.cpu3.dcache.overall_mshr_miss_rate::total 0.004138 # mshr miss rate for overall accesses +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 10456.395349 # average ReadReq mshr miss latency +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 10456.395349 # average ReadReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 15523.584906 # average WriteReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 15523.584906 # average WriteReq mshr miss latency +system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 15941.176471 # average SwapReq mshr miss latency +system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 15941.176471 # average SwapReq mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 12388.489209 # average overall mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency::total 12388.489209 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 12388.489209 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency::total 12388.489209 # average overall mshr miss latency system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.icache.tags.replacements 384 # number of replacements -system.cpu3.icache.tags.tagsinuse 80.879647 # Cycle average of tags in use -system.cpu3.icache.tags.total_refs 23443 # Total number of references to valid blocks. -system.cpu3.icache.tags.sampled_refs 498 # Sample count of references to valid blocks. -system.cpu3.icache.tags.avg_refs 47.074297 # Average number of references to valid blocks. +system.cpu3.icache.tags.replacements 608 # number of replacements +system.cpu3.icache.tags.tagsinuse 93.738869 # Cycle average of tags in use +system.cpu3.icache.tags.total_refs 33506 # Total number of references to valid blocks. +system.cpu3.icache.tags.sampled_refs 743 # Sample count of references to valid blocks. +system.cpu3.icache.tags.avg_refs 45.095559 # Average number of references to valid blocks. system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.icache.tags.occ_blocks::cpu3.inst 80.879647 # Average occupied blocks per requestor -system.cpu3.icache.tags.occ_percent::cpu3.inst 0.157968 # Average percentage of cache occupancy -system.cpu3.icache.tags.occ_percent::total 0.157968 # Average percentage of cache occupancy -system.cpu3.icache.tags.occ_task_id_blocks::1024 114 # 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Occupied blocks per task id +system.cpu3.icache.tags.age_task_id_blocks_1024::2 12 # Occupied blocks per task id +system.cpu3.icache.tags.occ_task_id_percent::1024 0.263672 # Percentage of cache occupancy per task id +system.cpu3.icache.tags.tag_accesses 35120 # Number of tag accesses +system.cpu3.icache.tags.data_accesses 35120 # Number of data accesses +system.cpu3.icache.ReadReq_hits::cpu3.inst 33506 # number of ReadReq hits +system.cpu3.icache.ReadReq_hits::total 33506 # number of ReadReq hits +system.cpu3.icache.demand_hits::cpu3.inst 33506 # number of demand (read+write) hits +system.cpu3.icache.demand_hits::total 33506 # number of demand (read+write) hits +system.cpu3.icache.overall_hits::cpu3.inst 33506 # number of overall hits +system.cpu3.icache.overall_hits::total 33506 # number of overall hits +system.cpu3.icache.ReadReq_misses::cpu3.inst 871 # number of ReadReq misses +system.cpu3.icache.ReadReq_misses::total 871 # number of ReadReq misses +system.cpu3.icache.demand_misses::cpu3.inst 871 # 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average ReadReq miss latency +system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 13385.763490 # average overall miss latency +system.cpu3.icache.demand_avg_miss_latency::total 13385.763490 # average overall miss latency +system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13385.763490 # average overall miss latency +system.cpu3.icache.overall_avg_miss_latency::total 13385.763490 # average overall miss latency system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -2332,219 +2361,219 @@ system.cpu3.icache.avg_blocked_cycles::no_mshrs nan system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.icache.fast_writes 0 # number of fast writes performed system.cpu3.icache.cache_copies 0 # number of cache copies performed -system.cpu3.icache.writebacks::writebacks 384 # number of writebacks -system.cpu3.icache.writebacks::total 384 # number of writebacks -system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst 76 # number of ReadReq MSHR hits -system.cpu3.icache.ReadReq_mshr_hits::total 76 # number of ReadReq MSHR hits -system.cpu3.icache.demand_mshr_hits::cpu3.inst 76 # number of demand (read+write) MSHR hits -system.cpu3.icache.demand_mshr_hits::total 76 # number of demand (read+write) MSHR hits -system.cpu3.icache.overall_mshr_hits::cpu3.inst 76 # number of overall MSHR hits -system.cpu3.icache.overall_mshr_hits::total 76 # number of overall MSHR hits -system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 498 # number of ReadReq MSHR misses -system.cpu3.icache.ReadReq_mshr_misses::total 498 # number of ReadReq MSHR misses -system.cpu3.icache.demand_mshr_misses::cpu3.inst 498 # number of demand (read+write) MSHR misses -system.cpu3.icache.demand_mshr_misses::total 498 # number of demand (read+write) MSHR misses -system.cpu3.icache.overall_mshr_misses::cpu3.inst 498 # number of overall MSHR misses -system.cpu3.icache.overall_mshr_misses::total 498 # number of overall MSHR misses -system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 6640500 # number of ReadReq MSHR miss cycles -system.cpu3.icache.ReadReq_mshr_miss_latency::total 6640500 # number of ReadReq MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 6640500 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_latency::total 6640500 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 6640500 # number of overall MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_latency::total 6640500 # number of overall MSHR miss cycles -system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.020735 # mshr miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.020735 # mshr miss rate for ReadReq accesses -system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.020735 # mshr miss rate for demand accesses -system.cpu3.icache.demand_mshr_miss_rate::total 0.020735 # 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number of ReadReq MSHR hits +system.cpu3.icache.ReadReq_mshr_hits::total 128 # number of ReadReq MSHR hits +system.cpu3.icache.demand_mshr_hits::cpu3.inst 128 # number of demand (read+write) MSHR hits +system.cpu3.icache.demand_mshr_hits::total 128 # number of demand (read+write) MSHR hits +system.cpu3.icache.overall_mshr_hits::cpu3.inst 128 # number of overall MSHR hits +system.cpu3.icache.overall_mshr_hits::total 128 # number of overall MSHR hits +system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 743 # number of ReadReq MSHR misses +system.cpu3.icache.ReadReq_mshr_misses::total 743 # number of ReadReq MSHR misses +system.cpu3.icache.demand_mshr_misses::cpu3.inst 743 # number of demand (read+write) MSHR misses +system.cpu3.icache.demand_mshr_misses::total 743 # number of demand (read+write) MSHR misses +system.cpu3.icache.overall_mshr_misses::cpu3.inst 743 # number of overall MSHR misses +system.cpu3.icache.overall_mshr_misses::total 743 # number of overall MSHR misses +system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 10055000 # 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mshr miss rate for overall accesses +system.cpu3.icache.overall_mshr_miss_rate::total 0.021613 # mshr miss rate for overall accesses +system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 13532.974428 # average ReadReq mshr miss latency +system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 13532.974428 # average ReadReq mshr miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 13532.974428 # average overall mshr miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency::total 13532.974428 # average overall mshr miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 13532.974428 # average overall mshr miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency::total 13532.974428 # average overall mshr miss latency system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.l2c.tags.replacements 0 # number of replacements -system.l2c.tags.tagsinuse 419.138543 # Cycle average of tags in use -system.l2c.tags.total_refs 2347 # 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Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 2.559109 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 0.677187 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.inst 1.231634 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.data 0.717957 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::writebacks 0.811695 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 303.236105 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 58.939439 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 17.006196 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 1.379366 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 67.599671 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 5.915132 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.inst 1.812120 # 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Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 343 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 138 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.008118 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 25618 # Number of tag accesses -system.l2c.tags.data_accesses 25618 # Number of data accesses +system.l2c.tags.occ_percent::cpu0.inst 0.004627 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.000899 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.000259 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.000021 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.inst 0.001031 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.data 0.000090 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3.inst 0.000028 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3.data 0.000028 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.006997 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1024 581 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 100 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 428 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1024 0.008865 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 32091 # Number of tag accesses +system.l2c.tags.data_accesses 32091 # Number of data accesses system.l2c.WritebackDirty_hits::writebacks 1 # number of WritebackDirty hits system.l2c.WritebackDirty_hits::total 1 # number of WritebackDirty hits -system.l2c.WritebackClean_hits::writebacks 676 # number of WritebackClean hits -system.l2c.WritebackClean_hits::total 676 # number of WritebackClean hits +system.l2c.WritebackClean_hits::writebacks 751 # number of WritebackClean hits +system.l2c.WritebackClean_hits::total 751 # number of WritebackClean hits system.l2c.UpgradeReq_hits::cpu0.data 3 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 3 # number of UpgradeReq hits -system.l2c.ReadCleanReq_hits::cpu0.inst 246 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu1.inst 410 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu2.inst 489 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu3.inst 493 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::total 1638 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu0.inst 329 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu1.inst 654 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu2.inst 595 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu3.inst 735 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::total 2313 # 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average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 71461.538462 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 90833.333333 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 107041.666667 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 76229.007634 # average ReadExReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 66174.515235 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 66091.463415 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 72750 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 72750 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 66276.053215 # average ReadCleanReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 69753.333333 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 67142.857143 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 72500 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 86500 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 69767.857143 # average ReadSharedReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 66174.515235 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 70497.041420 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 66091.463415 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 69950 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 72750 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 89423.076923 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 72750 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.data 105461.538462 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 68674.174174 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 66174.515235 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 70497.041420 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 66091.463415 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 69950 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 72750 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 89423.076923 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 72750 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.data 105461.538462 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 68674.174174 # average overall mshr miss latency +system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.532578 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.035191 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst 0.131124 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu3.inst 0.005384 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::total 0.175221 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.938272 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.153846 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data 0.615385 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu3.data 0.214286 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.735537 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.532578 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.971429 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.035191 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.560000 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.131124 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.data 0.807692 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.inst 0.005384 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.data 0.576923 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.232369 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.532578 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.971429 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.035191 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.560000 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.131124 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.807692 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.inst 0.005384 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.data 0.576923 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.232369 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19021.739130 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 19000 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 19045.454545 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 19041.666667 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 19028.089888 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 74813.829787 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 65166.666667 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 70615.384615 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 67250 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 72820.610687 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 67163.563830 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 80604.166667 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 69873.626374 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 77375 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 68395.959596 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 75967.105263 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 72750 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 69312.500000 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 77333.333333 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 75342.696629 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 67163.563830 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 75329.411765 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 80604.166667 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 66250 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 69873.626374 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 70119.047619 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 77375 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.data 69266.666667 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 70071.328671 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 67163.563830 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 75329.411765 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 80604.166667 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 66250 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 69873.626374 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 70119.047619 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 77375 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.data 69266.666667 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 70071.328671 # average overall mshr miss latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadResp 534 # Transaction distribution -system.membus.trans_dist::UpgradeReq 291 # Transaction distribution -system.membus.trans_dist::ReadExReq 159 # Transaction distribution +system.membus.trans_dist::ReadResp 583 # Transaction distribution +system.membus.trans_dist::UpgradeReq 286 # Transaction distribution +system.membus.trans_dist::ReadExReq 182 # Transaction distribution system.membus.trans_dist::ReadExResp 131 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 535 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1650 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1650 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 42560 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 42560 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 230 # Total snoops (count) -system.membus.snoop_fanout::samples 985 # Request fanout histogram +system.membus.trans_dist::ReadSharedReq 583 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1765 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1765 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 45696 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 45696 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 248 # Total snoops (count) +system.membus.snoop_fanout::samples 1051 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 985 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 1051 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 985 # Request fanout histogram -system.membus.reqLayer0.occupancy 928501 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.9 # Layer utilization (%) -system.membus.respLayer1.occupancy 3534750 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 3.3 # Layer utilization (%) -system.toL2Bus.snoop_filter.tot_requests 4931 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 1335 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 2366 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_fanout::total 1051 # Request fanout histogram +system.membus.reqLayer0.occupancy 998006 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.8 # Layer utilization (%) +system.membus.respLayer1.occupancy 3803500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 3.0 # Layer utilization (%) +system.toL2Bus.snoop_filter.tot_requests 6324 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 1712 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 3265 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.trans_dist::ReadResp 2779 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 3513 # Transaction distribution +system.toL2Bus.trans_dist::ReadRespWithInvalidate 6 # Transaction distribution system.toL2Bus.trans_dist::WritebackDirty 1 # Transaction distribution -system.toL2Bus.trans_dist::WritebackClean 1468 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 2114 # Transaction distribution system.toL2Bus.trans_dist::CleanEvict 1 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 294 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 294 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 387 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 387 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 2102 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 678 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1530 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 593 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1375 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 365 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 1386 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 379 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 1380 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 363 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 7371 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 59008 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 11200 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 56256 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.trans_dist::UpgradeReq 289 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 289 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 399 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 399 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 2825 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 695 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1814 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 602 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1912 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 373 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 1943 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 371 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 2094 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 383 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 9492 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 70912 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 11264 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 78720 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 56704 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 1536 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 56448 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 1536 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 244288 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 1020 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 3461 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.293268 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 1.185819 # Request fanout histogram +system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 79936 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 1664 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 86464 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 1664 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 332224 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 1039 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 4208 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.288736 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 1.116485 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 1230 35.54% 35.54% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 830 23.98% 59.52% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 557 16.09% 75.61% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 844 24.39% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 1347 32.01% 32.01% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 1142 27.14% 59.15% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 876 20.82% 79.97% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 843 20.03% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::5 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram @@ -2866,24 +2896,24 @@ system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Re system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 3461 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 3950967 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 3.7 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 911498 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 4208 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 5296461 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 4.2 # Layer utilization (%) +system.toL2Bus.respLayer0.occupancy 1058997 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.8 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 505495 # Layer occupancy (ticks) -system.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 746494 # Layer occupancy (ticks) -system.toL2Bus.respLayer2.utilization 0.7 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 429965 # Layer occupancy (ticks) -system.toL2Bus.respLayer3.utilization 0.4 # Layer utilization (%) -system.toL2Bus.respLayer4.occupancy 752493 # Layer occupancy (ticks) -system.toL2Bus.respLayer4.utilization 0.7 # Layer utilization (%) -system.toL2Bus.respLayer5.occupancy 440466 # Layer occupancy (ticks) -system.toL2Bus.respLayer5.utilization 0.4 # Layer utilization (%) -system.toL2Bus.respLayer6.occupancy 748497 # Layer occupancy (ticks) -system.toL2Bus.respLayer6.utilization 0.7 # Layer utilization (%) -system.toL2Bus.respLayer7.occupancy 422962 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 523496 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%) +system.toL2Bus.respLayer2.occupancy 1025493 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.utilization 0.8 # Layer utilization (%) +system.toL2Bus.respLayer3.occupancy 437958 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.utilization 0.3 # Layer utilization (%) +system.toL2Bus.respLayer4.occupancy 1044987 # Layer occupancy (ticks) +system.toL2Bus.respLayer4.utilization 0.8 # Layer utilization (%) +system.toL2Bus.respLayer5.occupancy 431472 # Layer occupancy (ticks) +system.toL2Bus.respLayer5.utilization 0.3 # Layer utilization (%) +system.toL2Bus.respLayer6.occupancy 1116994 # Layer occupancy (ticks) +system.toL2Bus.respLayer6.utilization 0.9 # Layer utilization (%) +system.toL2Bus.respLayer7.occupancy 444965 # Layer occupancy (ticks) system.toL2Bus.respLayer7.utilization 0.4 # Layer utilization (%) ---------- End Simulation Statistics ---------- |