diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2015-07-30 03:42:27 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2015-07-30 03:42:27 -0400 |
| commit | d8f732273ecda73122ad3ba184e358ed265fa875 (patch) | |
| tree | 6ef605febd4e2299d75d76897386ff4ad7288fec /tests/quick | |
| parent | 6fac40ceb03d4ab5b13affac3927cd876947cc78 (diff) | |
| download | gem5-d8f732273ecda73122ad3ba184e358ed265fa875.tar.xz | |
stats: Update stats for clean eviction addition
Diffstat (limited to 'tests/quick')
3 files changed, 2549 insertions, 2575 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt index eec67c0c4..d1669be2b 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.802895 # Nu sim_ticks 2802894699500 # Number of ticks simulated final_tick 2802894699500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1243628 # Simulator instruction rate (inst/s) -host_op_rate 1515342 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 23740372608 # Simulator tick rate (ticks/s) -host_mem_usage 632596 # Number of bytes of host memory used -host_seconds 118.06 # Real time elapsed on the host +host_inst_rate 1692608 # Simulator instruction rate (inst/s) +host_op_rate 2062417 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 32311218818 # Simulator tick rate (ticks/s) +host_mem_usage 579900 # Number of bytes of host memory used +host_seconds 86.75 # Real time elapsed on the host sim_insts 146828240 # Number of instructions simulated sim_ops 178908039 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -1387,7 +1387,7 @@ system.membus.trans_dist::ReadResp 75378 # Tr system.membus.trans_dist::WriteReq 30846 # Transaction distribution system.membus.trans_dist::WriteResp 30846 # Transaction distribution system.membus.trans_dist::Writeback 132426 # Transaction distribution -system.membus.trans_dist::CleanEvict 15436 # Transaction distribution +system.membus.trans_dist::CleanEvict 15452 # Transaction distribution system.membus.trans_dist::UpgradeReq 60361 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 40917 # Transaction distribution system.membus.trans_dist::UpgradeResp 15653 # Transaction distribution @@ -1399,11 +1399,11 @@ system.membus.trans_dist::InvalidateResp 36224 # Tr system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107876 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13474 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 666939 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 788323 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 666955 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 788339 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109394 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 109394 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 897717 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 897733 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162766 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 26948 # Cumulative packet size per connected master and slave (bytes) @@ -1413,17 +1413,17 @@ system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2332288 system.membus.pkt_size_system.iocache.mem_side::total 2332288 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size::total 20456418 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 587643 # Request fanout histogram +system.membus.snoop_fanout::samples 587659 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 587643 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 587659 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 587643 # Request fanout histogram +system.membus.snoop_fanout::total 587659 # Request fanout histogram system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt index b0093ef47..3792a44c9 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt @@ -1,161 +1,157 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.868721 # Number of seconds simulated -sim_ticks 2868720569000 # Number of ticks simulated -final_tick 2868720569000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.868749 # Number of seconds simulated +sim_ticks 2868748596000 # Number of ticks simulated +final_tick 2868748596000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 718623 # Simulator instruction rate (inst/s) -host_op_rate 869205 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 15661016649 # Simulator tick rate (ticks/s) -host_mem_usage 645712 # Number of bytes of host memory used -host_seconds 183.18 # Real time elapsed on the host -sim_insts 131634295 # Number of instructions simulated -sim_ops 159217322 # Number of ops (including micro ops) simulated +host_inst_rate 811357 # Simulator instruction rate (inst/s) +host_op_rate 981408 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 17699889488 # Simulator tick rate (ticks/s) +host_mem_usage 595428 # Number of bytes of host memory used +host_seconds 162.08 # Real time elapsed on the host +sim_insts 131502488 # Number of instructions simulated +sim_ops 159063828 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu0.dtb.walker 448 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 1149540 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 1292388 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 8590592 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 151892 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 585104 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 399936 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 1184036 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 1278116 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 8584576 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 111060 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 568976 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 412800 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 12171052 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 1149540 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 151892 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1301432 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8736704 # Number of bytes written to this memory +system.physmem.bytes_read::total 12141100 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 1184036 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 111060 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1295096 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8715904 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory -system.physmem.bytes_written::total 8754268 # Number of bytes written to this memory +system.physmem.bytes_written::total 8733468 # Number of bytes written to this memory system.physmem.num_reads::cpu0.dtb.walker 7 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 26415 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 20713 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 134228 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2528 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 9162 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 6249 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 26954 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 20490 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 134134 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 1890 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 8910 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 6450 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 199320 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 136511 # Number of write requests responded to by this memory +system.physmem.num_reads::total 198852 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 136186 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory -system.physmem.num_writes::total 140902 # Number of write requests responded to by this memory +system.physmem.num_writes::total 140577 # Number of write requests responded to by this memory system.physmem.bw_read::cpu0.dtb.walker 156 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 45 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 400715 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 450510 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 2994573 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 22 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 52948 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 203960 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 139413 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 412736 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 445531 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 2992446 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 38714 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 198336 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 143895 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 335 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4242676 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 400715 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 52948 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 453663 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3045505 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4232194 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 412736 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 38714 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 451450 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3038225 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 6109 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3051628 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3045505 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 3044348 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3038225 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 156 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 45 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 400715 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 456619 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 2994573 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 22 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 52948 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 203974 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 139413 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 412736 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 451639 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 2992446 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 38714 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 198350 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 143895 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 335 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7294304 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 199320 # Number of read requests accepted -system.physmem.writeReqs 140902 # Number of write requests accepted -system.physmem.readBursts 199320 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 140902 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 12746944 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 9536 # Total number of bytes read from write queue -system.physmem.bytesWritten 8766656 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 12171052 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 8754268 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 149 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::total 7276541 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 198852 # Number of read requests accepted +system.physmem.writeReqs 140577 # Number of write requests accepted +system.physmem.readBursts 198852 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 140577 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 12717568 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 8960 # Total number of bytes read from write queue +system.physmem.bytesWritten 8745536 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 12141100 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 8733468 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 140 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 3896 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 49030 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 12070 # Per bank write bursts -system.physmem.perBankRdBursts::1 11831 # Per bank write bursts -system.physmem.perBankRdBursts::2 12274 # Per bank write bursts -system.physmem.perBankRdBursts::3 12388 # Per bank write bursts -system.physmem.perBankRdBursts::4 20676 # Per bank write bursts -system.physmem.perBankRdBursts::5 12594 # Per bank write bursts -system.physmem.perBankRdBursts::6 12033 # Per bank write bursts -system.physmem.perBankRdBursts::7 12197 # Per bank write bursts -system.physmem.perBankRdBursts::8 12580 # Per bank write bursts -system.physmem.perBankRdBursts::9 12376 # Per bank write bursts -system.physmem.perBankRdBursts::10 11749 # Per bank write bursts -system.physmem.perBankRdBursts::11 11049 # Per bank write bursts -system.physmem.perBankRdBursts::12 11595 # Per bank write bursts -system.physmem.perBankRdBursts::13 11646 # Per bank write bursts -system.physmem.perBankRdBursts::14 10943 # Per bank write bursts -system.physmem.perBankRdBursts::15 11170 # Per bank write bursts -system.physmem.perBankWrBursts::0 8793 # Per bank write bursts -system.physmem.perBankWrBursts::1 8761 # Per bank write bursts -system.physmem.perBankWrBursts::2 9161 # Per bank write bursts -system.physmem.perBankWrBursts::3 8988 # Per bank write bursts -system.physmem.perBankWrBursts::4 8395 # Per bank write bursts -system.physmem.perBankWrBursts::5 9123 # Per bank write bursts -system.physmem.perBankWrBursts::6 8851 # Per bank write bursts -system.physmem.perBankWrBursts::7 8630 # Per bank write bursts -system.physmem.perBankWrBursts::8 9078 # Per bank write bursts -system.physmem.perBankWrBursts::9 8912 # Per bank write bursts -system.physmem.perBankWrBursts::10 8485 # Per bank write bursts -system.physmem.perBankWrBursts::11 8089 # Per bank write bursts -system.physmem.perBankWrBursts::12 8403 # Per bank write bursts -system.physmem.perBankWrBursts::13 8019 # Per bank write bursts -system.physmem.perBankWrBursts::14 7666 # Per bank write bursts -system.physmem.perBankWrBursts::15 7625 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 48892 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 12039 # Per bank write bursts +system.physmem.perBankRdBursts::1 11932 # Per bank write bursts +system.physmem.perBankRdBursts::2 12219 # Per bank write bursts +system.physmem.perBankRdBursts::3 12193 # Per bank write bursts +system.physmem.perBankRdBursts::4 20606 # Per bank write bursts +system.physmem.perBankRdBursts::5 12429 # Per bank write bursts +system.physmem.perBankRdBursts::6 12151 # Per bank write bursts +system.physmem.perBankRdBursts::7 12313 # Per bank write bursts +system.physmem.perBankRdBursts::8 12521 # Per bank write bursts +system.physmem.perBankRdBursts::9 12643 # Per bank write bursts +system.physmem.perBankRdBursts::10 11981 # Per bank write bursts +system.physmem.perBankRdBursts::11 11107 # Per bank write bursts +system.physmem.perBankRdBursts::12 11212 # Per bank write bursts +system.physmem.perBankRdBursts::13 11639 # Per bank write bursts +system.physmem.perBankRdBursts::14 10708 # Per bank write bursts +system.physmem.perBankRdBursts::15 11019 # Per bank write bursts +system.physmem.perBankWrBursts::0 8788 # Per bank write bursts +system.physmem.perBankWrBursts::1 8813 # Per bank write bursts +system.physmem.perBankWrBursts::2 9145 # Per bank write bursts +system.physmem.perBankWrBursts::3 8891 # Per bank write bursts +system.physmem.perBankWrBursts::4 8356 # Per bank write bursts +system.physmem.perBankWrBursts::5 8969 # Per bank write bursts +system.physmem.perBankWrBursts::6 8864 # Per bank write bursts +system.physmem.perBankWrBursts::7 8722 # Per bank write bursts +system.physmem.perBankWrBursts::8 9036 # Per bank write bursts +system.physmem.perBankWrBursts::9 9148 # Per bank write bursts +system.physmem.perBankWrBursts::10 8611 # Per bank write bursts +system.physmem.perBankWrBursts::11 8177 # Per bank write bursts +system.physmem.perBankWrBursts::12 8063 # Per bank write bursts +system.physmem.perBankWrBursts::13 7981 # Per bank write bursts +system.physmem.perBankWrBursts::14 7509 # Per bank write bursts +system.physmem.perBankWrBursts::15 7576 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 43 # Number of times write queue was full causing retry -system.physmem.totGap 2868720108500 # Total gap between requests +system.physmem.numWrRetry 39 # Number of times write queue was full causing retry +system.physmem.totGap 2868748135500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 9731 # Read request sizes (log2) system.physmem.readPktSize::3 28 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 189561 # Read request sizes (log2) +system.physmem.readPktSize::6 189093 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4391 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 136511 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 138723 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 15961 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 10493 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 8947 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 7139 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 5591 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 4693 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 3946 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3444 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 97 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 69 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 37 # What read queue length does an incoming req see +system.physmem.writePktSize::6 136186 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 138565 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 16001 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 10431 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 8838 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 7035 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 5529 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 4705 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 3918 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3439 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 106 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 73 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 39 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 18 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 8 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 6 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see @@ -184,156 +180,158 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2740 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3251 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4887 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5950 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6428 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6725 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6970 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 8417 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 8666 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 9995 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 9375 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 9280 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 8482 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8751 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 10022 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 8140 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7549 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7221 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 312 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 261 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 257 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 214 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 148 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 179 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 159 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 188 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 159 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 161 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 129 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 140 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 117 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 153 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 129 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 101 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 89 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 101 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 88 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 97 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 62 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 114 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 81 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 62 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 71 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 71 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 77 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 62 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 90 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 131 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 88863 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 242.097791 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 137.224347 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 303.120448 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 46751 52.61% 52.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 18086 20.35% 72.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6032 6.79% 79.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3695 4.16% 83.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2426 2.73% 86.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1553 1.75% 88.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1048 1.18% 89.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 926 1.04% 90.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8346 9.39% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 88863 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6835 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 29.139722 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 544.203282 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 6833 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 2660 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3121 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4817 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5889 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6298 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6719 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6977 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 8373 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 8663 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 9929 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 9268 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 9147 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 8525 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8846 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 10151 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 8179 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 7567 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 7217 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 283 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 196 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 252 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 187 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 153 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 188 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 177 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 245 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 165 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 148 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 145 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 165 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 127 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 158 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 160 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 115 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 144 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 121 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 128 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 118 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 128 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 96 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 153 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 79 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 54 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 75 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 49 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 51 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 67 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 60 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 133 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 88033 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 243.806754 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 138.095781 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 304.392225 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 45989 52.24% 52.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 18103 20.56% 72.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5912 6.72% 79.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3673 4.17% 83.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2470 2.81% 86.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1565 1.78% 88.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 995 1.13% 89.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 958 1.09% 90.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8368 9.51% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 88033 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6795 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 29.243709 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 545.811163 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6793 99.97% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-4095 1 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::43008-45055 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6835 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6835 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.040819 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.588322 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 11.942463 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5790 84.71% 84.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 288 4.21% 88.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 181 2.65% 91.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 61 0.89% 92.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 66 0.97% 93.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 161 2.36% 95.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 22 0.32% 96.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 10 0.15% 96.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 10 0.15% 96.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 9 0.13% 96.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 9 0.13% 96.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 11 0.16% 96.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 163 2.38% 99.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 7 0.10% 99.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 5 0.07% 99.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 8 0.12% 99.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 6 0.09% 99.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 1 0.01% 99.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 3 0.04% 99.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 1 0.01% 99.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.01% 99.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 13 0.19% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 2 0.03% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 1 0.01% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 4 0.06% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 2 0.03% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6835 # Writes before turning the bus around for reads -system.physmem.totQLat 4713712824 # Total ticks spent queuing -system.physmem.totMemAccLat 8448169074 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 995855000 # Total ticks spent in databus transfers -system.physmem.avgQLat 23666.66 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 6795 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6795 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.110228 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.616765 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 12.492638 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 5748 84.59% 84.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 291 4.28% 88.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 178 2.62% 91.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 60 0.88% 92.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 79 1.16% 93.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 156 2.30% 95.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 28 0.41% 96.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 7 0.10% 96.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 12 0.18% 96.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 7 0.10% 96.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 9 0.13% 96.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 7 0.10% 96.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 161 2.37% 99.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 3 0.04% 99.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 4 0.06% 99.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 11 0.16% 99.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 3 0.04% 99.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 1 0.01% 99.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 2 0.03% 99.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 1 0.01% 99.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 1 0.01% 99.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 3 0.04% 99.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 11 0.16% 99.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 1 0.01% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 4 0.06% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 1 0.01% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 5 0.07% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::204-207 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6795 # Writes before turning the bus around for reads +system.physmem.totQLat 4722732900 # Total ticks spent queuing +system.physmem.totMemAccLat 8448582900 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 993560000 # Total ticks spent in databus transfers +system.physmem.avgQLat 23766.72 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 42416.66 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 4.44 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 3.06 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 4.24 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 3.05 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 42516.72 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 4.43 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 3.05 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 4.23 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 3.04 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.06 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.08 # Average read queue length when enqueuing -system.physmem.avgWrQLen 27.14 # Average write queue length when enqueuing -system.physmem.readRowHits 166377 # Number of row buffer hits during reads -system.physmem.writeRowHits 80909 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.53 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 59.06 # Row buffer hit rate for writes -system.physmem.avgGap 8431906.54 # Average gap between requests -system.physmem.pageHitRate 73.56 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 348886440 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 190364625 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 827283600 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 458148960 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 187370795040 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 84523956795 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1647087865500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1920807300960 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.569582 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2739939393002 # Time in different power states -system.physmem_0.memoryStateTime::REF 95792840000 # Time in different power states +system.physmem.avgRdQLen 1.10 # Average read queue length when enqueuing +system.physmem.avgWrQLen 22.76 # Average write queue length when enqueuing +system.physmem.readRowHits 166188 # Number of row buffer hits during reads +system.physmem.writeRowHits 81139 # Number of row buffer hits during writes +system.physmem.readRowHitRate 83.63 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 59.36 # Row buffer hit rate for writes +system.physmem.avgGap 8451688.38 # Average gap between requests +system.physmem.pageHitRate 73.74 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 346580640 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 189106500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 825871800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 457151040 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 187372320720 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 84248156880 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1647343810500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1920782998080 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.555658 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2740372132788 # Time in different power states +system.physmem_0.memoryStateTime::REF 95793620000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 32988240498 # Time in different power states +system.physmem_0.memoryStateTime::ACT 32582747712 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 322917840 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 176195250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 726242400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 429474960 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 187370795040 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 83768933655 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1647750166500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1920544725645 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.478051 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2741046257852 # Time in different power states -system.physmem_1.memoryStateTime::REF 95792840000 # Time in different power states +system.physmem_1.actEnergy 318948840 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 174029625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 724074000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 428334480 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 187372320720 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 83576818575 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1647932703750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1920527229990 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.466501 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2741353761866 # Time in different power states +system.physmem_1.memoryStateTime::REF 95793620000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 31880394648 # Time in different power states +system.physmem_1.memoryStateTime::ACT 31595469384 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory @@ -389,57 +387,57 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 7828 # Table walker walks requested -system.cpu0.dtb.walker.walksShort 7828 # Table walker walks initiated with short descriptors -system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 1457 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 6371 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walkWaitTime::samples 7828 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 7828 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 7828 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 6434 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 10362.060926 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 9317.145265 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 5859.670820 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-16383 6278 97.58% 97.58% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::16384-32767 144 2.24% 99.81% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::32768-49151 7 0.11% 99.92% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::81920-98303 4 0.06% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::212992-229375 1 0.02% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 6434 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walks 7824 # Table walker walks requested +system.cpu0.dtb.walker.walksShort 7824 # Table walker walks initiated with short descriptors +system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 1442 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 6382 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walkWaitTime::samples 7824 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 7824 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 7824 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 6430 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 10325.194401 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 9252.413387 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 6597.669693 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-32767 6417 99.80% 99.80% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::32768-65535 7 0.11% 99.91% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::65536-98303 2 0.03% 99.94% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::98304-131071 3 0.05% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::294912-327679 1 0.02% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 6430 # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walksPending::samples 1109412500 # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::0 1109412500 100.00% 100.00% # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::total 1109412500 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 5016 77.96% 77.96% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::1M 1418 22.04% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 6434 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 7828 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkPageSizes::4K 5027 78.18% 78.18% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 1403 21.82% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 6430 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 7824 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 7828 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6434 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 7824 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6430 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6434 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 14262 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6430 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 14254 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 22804186 # DTB read hits -system.cpu0.dtb.read_misses 6713 # DTB read misses -system.cpu0.dtb.write_hits 17553531 # DTB write hits -system.cpu0.dtb.write_misses 1115 # DTB write misses +system.cpu0.dtb.read_hits 25236580 # DTB read hits +system.cpu0.dtb.read_misses 6707 # DTB read misses +system.cpu0.dtb.write_hits 18793560 # DTB write hits +system.cpu0.dtb.write_misses 1117 # DTB write misses system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 3455 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 3444 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 1817 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 1747 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dtb.perms_faults 282 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 22810899 # DTB read accesses -system.cpu0.dtb.write_accesses 17554646 # DTB write accesses +system.cpu0.dtb.read_accesses 25243287 # DTB read accesses +system.cpu0.dtb.write_accesses 18794677 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 40357717 # DTB hits -system.cpu0.dtb.misses 7828 # DTB misses -system.cpu0.dtb.accesses 40365545 # DTB accesses +system.cpu0.dtb.hits 44030140 # DTB hits +system.cpu0.dtb.misses 7824 # DTB misses +system.cpu0.dtb.accesses 44037964 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -477,15 +475,14 @@ system.cpu0.itb.walker.walkWaitTime::samples 3348 system.cpu0.itb.walker.walkWaitTime::0 3348 100.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu0.itb.walker.walkWaitTime::total 3348 # Table walker wait (enqueue to first request) latency system.cpu0.itb.walker.walkCompletionTime::samples 2332 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 10683.319039 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 9538.524469 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 5751.182189 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-8191 887 38.04% 38.04% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::8192-16383 1322 56.69% 94.73% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::16384-24575 85 3.64% 98.37% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::24576-32767 28 1.20% 99.57% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::32768-40959 7 0.30% 99.87% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::40960-49151 1 0.04% 99.91% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 10655.874786 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 9465.333686 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 5846.917058 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-8191 920 39.45% 39.45% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::8192-16383 1284 55.06% 94.51% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::16384-24575 84 3.60% 98.11% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::24576-32767 34 1.46% 99.57% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::32768-40959 8 0.34% 99.91% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::90112-98303 1 0.04% 99.96% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::114688-122879 1 0.04% 100.00% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::total 2332 # Table walker service (enqueue to completion) latency @@ -502,7 +499,7 @@ system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2332 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2332 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin::total 5680 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 108563333 # ITB inst hits +system.cpu0.itb.inst_hits 119342617 # ITB inst hits system.cpu0.itb.inst_misses 3348 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses @@ -519,172 +516,172 @@ system.cpu0.itb.domain_faults 0 # Nu system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 108566681 # ITB inst accesses -system.cpu0.itb.hits 108563333 # DTB hits +system.cpu0.itb.inst_accesses 119345965 # ITB inst accesses +system.cpu0.itb.hits 119342617 # DTB hits system.cpu0.itb.misses 3348 # DTB misses -system.cpu0.itb.accesses 108566681 # DTB accesses -system.cpu0.numCycles 5737441138 # number of cpu cycles simulated +system.cpu0.itb.accesses 119345965 # DTB accesses +system.cpu0.numCycles 5737497192 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 105480509 # Number of instructions committed -system.cpu0.committedOps 127164191 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 112285314 # Number of integer alu accesses +system.cpu0.committedInsts 115654281 # Number of instructions committed +system.cpu0.committedOps 139770289 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 123734710 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 9820 # Number of float alu accesses -system.cpu0.num_func_calls 10414111 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 14574473 # number of instructions that are conditional controls -system.cpu0.num_int_insts 112285314 # number of integer instructions +system.cpu0.num_func_calls 12768418 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 15718242 # number of instructions that are conditional controls +system.cpu0.num_int_insts 123734710 # number of integer instructions system.cpu0.num_fp_insts 9820 # number of float instructions -system.cpu0.num_int_register_reads 205015592 # number of times the integer registers were read -system.cpu0.num_int_register_writes 77505457 # number of times the integer registers were written +system.cpu0.num_int_register_reads 227859200 # number of times the integer registers were read +system.cpu0.num_int_register_writes 85998639 # number of times the integer registers were written system.cpu0.num_fp_register_reads 7560 # number of times the floating registers were read system.cpu0.num_fp_register_writes 2264 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 459494635 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 48916829 # number of times the CC registers were written -system.cpu0.num_mem_refs 41493426 # number of memory refs -system.cpu0.num_load_insts 23055800 # Number of load instructions -system.cpu0.num_store_insts 18437626 # Number of store instructions -system.cpu0.num_idle_cycles 5489199817.904087 # Number of idle cycles -system.cpu0.num_busy_cycles 248241320.095913 # Number of busy cycles -system.cpu0.not_idle_fraction 0.043267 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.956733 # Percentage of idle cycles -system.cpu0.Branches 25703635 # Number of branches fetched +system.cpu0.num_cc_register_reads 506429091 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 52352971 # number of times the CC registers were written +system.cpu0.num_mem_refs 45168124 # number of memory refs +system.cpu0.num_load_insts 25488908 # Number of load instructions +system.cpu0.num_store_insts 19679216 # Number of store instructions +system.cpu0.num_idle_cycles 5463941135.084096 # Number of idle cycles +system.cpu0.num_busy_cycles 273556056.915905 # Number of busy cycles +system.cpu0.not_idle_fraction 0.047679 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.952321 # Percentage of idle cycles +system.cpu0.Branches 29223626 # Number of branches fetched system.cpu0.op_class::No_OpClass 2273 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 88750967 68.09% 68.09% # Class of executed instruction -system.cpu0.op_class::IntMult 92819 0.07% 68.16% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 68.16% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 68.16% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 68.16% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 68.16% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 68.16% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 68.16% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 68.16% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 68.16% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 68.16% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 68.16% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 68.16% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 68.16% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 68.16% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 68.16% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 68.16% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 68.16% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.16% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 68.16% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 68.16% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.16% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.16% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.16% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.16% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 8217 0.01% 68.17% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 68.17% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.17% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.17% # Class of executed instruction -system.cpu0.op_class::MemRead 23055800 17.69% 85.86% # Class of executed instruction -system.cpu0.op_class::MemWrite 18437626 14.14% 100.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 98271812 68.45% 68.45% # Class of executed instruction +system.cpu0.op_class::IntMult 109732 0.08% 68.53% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 8207 0.01% 68.54% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 68.54% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.54% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.54% # Class of executed instruction +system.cpu0.op_class::MemRead 25488908 17.75% 86.29% # Class of executed instruction +system.cpu0.op_class::MemWrite 19679216 13.71% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 130347702 # Class of executed instruction +system.cpu0.op_class::total 143560148 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 1862 # number of quiesce instructions executed -system.cpu0.dcache.tags.replacements 694931 # number of replacements -system.cpu0.dcache.tags.tagsinuse 494.123274 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 39503506 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 695443 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 56.803370 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 1135131000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 494.123274 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.965085 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.965085 # Average percentage of cache occupancy +system.cpu0.kern.inst.quiesce 1875 # number of quiesce instructions executed +system.cpu0.dcache.tags.replacements 696532 # number of replacements +system.cpu0.dcache.tags.tagsinuse 491.305468 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 43154174 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 697044 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 61.910258 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 1135377000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 491.305468 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.959581 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.959581 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 319 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 89 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 107 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 308 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 97 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 81393420 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 81393420 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 21551304 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 21551304 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 16831338 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 16831338 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 318322 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 318322 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 365658 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 365658 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 362750 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 362750 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 38382642 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 38382642 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 38700964 # number of overall hits -system.cpu0.dcache.overall_hits::total 38700964 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 398253 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 398253 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 324071 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 324071 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 128299 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 128299 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21791 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 21791 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 19751 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 19751 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 722324 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 722324 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 850623 # number of overall misses -system.cpu0.dcache.overall_misses::total 850623 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5056802000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 5056802000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 5106772500 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 5106772500 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 332740500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 332740500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 437773500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 437773500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 1801500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1801500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 10163574500 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 10163574500 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 10163574500 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 10163574500 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 21949557 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 21949557 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 17155409 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 17155409 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 446621 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 446621 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 387449 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 387449 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 382501 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 382501 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 39104966 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 39104966 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 39551587 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 39551587 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.018144 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.018144 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018890 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.018890 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.287266 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.287266 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.056242 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.056242 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.051636 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.051636 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.018471 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.018471 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.021507 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.021507 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 12697.461162 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 12697.461162 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 15758.190335 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 15758.190335 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15269.629664 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15269.629664 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22164.624576 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22164.624576 # average StoreCondReq miss latency +system.cpu0.dcache.tags.tag_accesses 88699037 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 88699037 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 23972048 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 23972048 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 18061887 # 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number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5067389500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 5067389500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 5162627000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 5162627000 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 330228000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 330228000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 435506500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 435506500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 1585500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1585500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 10230016500 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 10230016500 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 10230016500 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 10230016500 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 24370724 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 24370724 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 18386551 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 18386551 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 446763 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 446763 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 387309 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 387309 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 382355 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 382355 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 42757275 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 42757275 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 43204038 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 43204038 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.016359 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.016359 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.017658 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.017658 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.287945 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.287945 # miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.056043 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.056043 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.051541 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.051541 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.016917 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.016917 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.019720 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.019720 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 12710.545656 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 12710.545656 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 15901.445802 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 15901.445802 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15213.673639 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15213.673639 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22099.076470 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22099.076470 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 14070.658735 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 14070.658735 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 11948.389004 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 11948.389004 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 14142.749606 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 14142.749606 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 12007.301202 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 12007.301202 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -693,147 +690,147 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 507088 # number of writebacks -system.cpu0.dcache.writebacks::total 507088 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 25317 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 25317 # number of ReadReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 15125 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 15125 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 25317 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 25317 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 25317 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 25317 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 372936 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 372936 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 324071 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 324071 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 100997 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 100997 # number of SoftPFReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6666 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6666 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 19751 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 19751 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 697007 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 697007 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 798004 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 798004 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 21110 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 21110 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 19686 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 19686 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 40796 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 40796 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4291277500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4291277500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4782701500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4782701500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1606991500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1606991500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 101428000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 101428000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 418075500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 418075500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1748500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1748500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9073979000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 9073979000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10680970500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 10680970500 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 4433767500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 4433767500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 3394597500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 3394597500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 7828365000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 7828365000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.016991 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.016991 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018890 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018890 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.226136 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.226136 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.017205 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.017205 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.051636 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051636 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.017824 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.017824 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.020176 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.020176 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11506.739762 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11506.739762 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 14758.190335 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 14758.190335 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 15911.279543 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15911.279543 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15215.721572 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15215.721572 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 21167.307984 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 21167.307984 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 508357 # number of writebacks +system.cpu0.dcache.writebacks::total 508357 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 25412 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 25412 # number of ReadReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 15099 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 15099 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 25412 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 25412 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 25412 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 25412 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 373264 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 373264 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 324664 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 324664 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 101205 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 101205 # number of SoftPFReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6607 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6607 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 19707 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 19707 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 697928 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 697928 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 799133 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 799133 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 32335 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 32335 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 28719 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 28719 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 61054 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 61054 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4299217000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4299217000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4837963000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4837963000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1611370000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1611370000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 100016000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 100016000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 415846500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 415846500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1538500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1538500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9137180000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 9137180000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10748550000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 10748550000 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6362298500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6362298500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 4936759500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4936759500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 11299058000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11299058000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.015316 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.015316 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.017658 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.017658 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.226530 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.226530 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.017059 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.017059 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.051541 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051541 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.016323 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.016323 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.018497 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.018497 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11517.898860 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11517.898860 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 14901.445802 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 14901.445802 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 15921.841806 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15921.841806 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15137.884062 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15137.884062 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 21101.461410 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 21101.461410 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13018.490489 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13018.490489 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 13384.607721 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 13384.607721 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 210031.620085 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 210031.620085 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 172437.138068 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 172437.138068 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 191890.503971 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 191890.503971 # average overall mshr uncacheable latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13091.866210 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13091.866210 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 13450.264224 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 13450.264224 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 196761.976187 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 196761.976187 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 171898.725582 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 171898.725582 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 185066.629541 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 185066.629541 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 1106064 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.455953 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 107456748 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1106576 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 97.107427 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 13496677000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.455953 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998937 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.998937 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 1105972 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.454897 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 118236124 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 1106484 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 106.857509 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 13516114000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.454897 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998935 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.998935 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 90 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 208 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 92 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 206 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::2 214 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 218233251 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 218233251 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 107456748 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 107456748 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 107456748 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 107456748 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 107456748 # number of overall hits -system.cpu0.icache.overall_hits::total 107456748 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 1106585 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1106585 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 1106585 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1106585 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 1106585 # number of overall misses -system.cpu0.icache.overall_misses::total 1106585 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 10879255500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 10879255500 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 10879255500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 10879255500 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 10879255500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 10879255500 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 108563333 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 108563333 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 108563333 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 108563333 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 108563333 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 108563333 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.010193 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.010193 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.010193 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.010193 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.010193 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.010193 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 9831.378069 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 9831.378069 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 9831.378069 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 9831.378069 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 9831.378069 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 9831.378069 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 239791727 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 239791727 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 118236124 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 118236124 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 118236124 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 118236124 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 118236124 # number of overall hits +system.cpu0.icache.overall_hits::total 118236124 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 1106493 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1106493 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 1106493 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 1106493 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 1106493 # number of overall misses +system.cpu0.icache.overall_misses::total 1106493 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 10938029500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 10938029500 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 10938029500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 10938029500 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 10938029500 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 10938029500 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 119342617 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 119342617 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 119342617 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 119342617 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 119342617 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 119342617 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.009272 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.009272 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.009272 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.009272 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.009272 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.009272 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 9885.312876 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 9885.312876 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 9885.312876 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 9885.312876 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 9885.312876 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 9885.312876 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -842,448 +839,448 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1106585 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 1106585 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 1106585 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 1106585 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 1106585 # 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number of overall MSHR uncacheable misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10325963000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 10325963000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10325963000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 10325963000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10325963000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 10325963000 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10384783000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 10384783000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10384783000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 10384783000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10384783000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 10384783000 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 800795500 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 800795500 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 800795500 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 800795500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.010193 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.010193 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.010193 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.010193 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.010193 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.010193 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9331.378069 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9331.378069 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9331.378069 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 9331.378069 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9331.378069 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 9331.378069 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.009272 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.009272 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.009272 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.009272 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.009272 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.009272 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9385.312876 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9385.312876 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9385.312876 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 9385.312876 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9385.312876 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 9385.312876 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 88760.308136 # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 88760.308136 # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 88760.308136 # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 88760.308136 # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.l2cache.prefetcher.num_hwpf_issued 1850657 # number of hwpf issued -system.cpu0.l2cache.prefetcher.pfIdentified 1850711 # number of prefetch candidates identified -system.cpu0.l2cache.prefetcher.pfBufferHit 45 # number of redundant prefetches already in prefetch queue +system.cpu0.l2cache.prefetcher.num_hwpf_issued 1841098 # number of hwpf issued +system.cpu0.l2cache.prefetcher.pfIdentified 1841106 # number of prefetch candidates identified +system.cpu0.l2cache.prefetcher.pfBufferHit 7 # number of redundant prefetches already in prefetch queue system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu0.l2cache.prefetcher.pfSpanPage 237577 # number of prefetches not generated due to page crossing -system.cpu0.l2cache.tags.replacements 266648 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 16090.167348 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 3241094 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 282873 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 11.457771 # Average number of references to valid blocks. -system.cpu0.l2cache.tags.warmup_cycle 2844827650500 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 7840.907632 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 1.369036 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.138555 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 4562.781634 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.data 1957.525775 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1727.444715 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.478571 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000084 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000008 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.278490 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.119478 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.105435 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.982066 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1088 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 7 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15130 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 11 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 286 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 359 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 432 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id +system.cpu0.l2cache.prefetcher.pfSpanPage 237750 # number of prefetches not generated due to page crossing +system.cpu0.l2cache.tags.replacements 269395 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 16110.328705 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 3241181 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 285612 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 11.348196 # Average number of references to valid blocks. +system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu0.l2cache.tags.occ_blocks::writebacks 7729.941983 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 2.543117 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.104661 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 4692.501202 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.data 1977.796502 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1707.441239 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.471798 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000155 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000006 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.286408 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.120715 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.104214 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::total 0.983296 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1097 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1023 6 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15114 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 9 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 275 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 382 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 431 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 118 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 3231 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7855 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 3884 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.066406 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000427 # 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number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 4264886500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 4998017000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 3246952500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 3246952500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 6103617500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 6836748000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 4721367000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 4721367000 # number of WriteReq MSHR uncacheable cycles system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 733130500 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 7511839000 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 8244969500 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.027822 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.029698 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.028404 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 10824984500 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 11558115000 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.027010 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.031207 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.028310 # mshr miss rate for ReadReq accesses system.cpu0.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu0.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.478697 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.478697 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.915633 # mshr miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.915633 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.475877 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.475877 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.911860 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.911860 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.149988 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.149988 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.042186 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.042186 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.196440 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.196440 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.027822 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.029698 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.042186 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.179743 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::total 0.097324 # mshr miss rate for demand accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.027822 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.029698 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.042186 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.179743 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.148708 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.148708 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.043412 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.043412 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.196393 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.196393 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.027010 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.031207 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.043412 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.179231 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.097908 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.027010 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.031207 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.043412 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.179231 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.228360 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 17663.755459 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 16790.909091 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 17380.530973 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 56777.995843 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 56777.995843 # average HardPFReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20076.499059 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20076.499059 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 14905.563852 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14905.563852 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 337249 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 337249 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 39292.533993 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 39292.533993 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 43635.769676 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 43635.769676 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 23272.399877 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 23272.399877 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 17663.755459 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 16790.909091 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 43635.769676 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 28077.525415 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 32050.824720 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 17663.755459 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 16790.909091 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 43635.769676 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 28077.525415 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 56777.995843 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 46239.596402 # average overall mshr miss latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.228935 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 18575 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 16807.017544 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 17971.556886 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 56080.431658 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 56080.431658 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20097.617754 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20097.617754 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 14895.796214 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14895.796214 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 107499.363636 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 107499.363636 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 40970.516581 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 40970.516581 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 43657.624649 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 43657.624649 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 23317.538103 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 23317.538103 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 18575 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 16807.017544 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 43657.624649 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 28589.082892 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 32523.378397 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 18575 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 16807.017544 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 43657.624649 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 28589.082892 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 56080.431658 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 46005.871762 # average overall mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 81260.308136 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 202031.572714 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 165870.735431 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 164937.138068 # average WriteReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 164937.138068 # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 188761.945261 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 165310.539933 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 164398.725582 # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 164398.725582 # average WriteReq mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 81260.308136 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 184131.753113 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 165501.816612 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 177301.806597 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 164936.854273 # average overall mshr uncacheable latency system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.trans_dist::ReadReq 64679 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 1685922 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 30913 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 19686 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::Writeback 869596 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::CleanEvict 1383128 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 312557 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 88259 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42246 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 111569 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 44 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 93 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 298532 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 285304 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1106585 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadSharedReq 579491 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadReq 64646 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 1697156 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 30874 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 28719 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::Writeback 871288 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::CleanEvict 1384656 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 292494 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 87584 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42065 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 111017 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 56 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 92 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 299003 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 286103 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1106493 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadSharedReq 579158 # Transaction distribution system.cpu0.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3316089 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2519725 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 10102 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 22430 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 5868346 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 70857528 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 84663704 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 14816 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 32924 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 155568972 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 1147635 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 4840235 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 1.218671 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.413345 # Request fanout histogram +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3315880 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2563217 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 10051 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 22351 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 5911499 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 70851640 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 84881644 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 14612 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 32580 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 155780476 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 1106596 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 4822448 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 1.211081 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.408076 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 3781818 78.13% 78.13% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 1058417 21.87% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 3804521 78.89% 78.89% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 1017927 21.11% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 4840235 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 2418139995 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 4822448 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 2435282990 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 114234000 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 113496000 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 1668899500 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 1668761500 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 1193519480 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 1211060981 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu0.toL2Bus.respLayer2.occupancy 6398000 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 14203990 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 14212986 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -1314,58 +1311,60 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 3364 # Table walker walks requested -system.cpu1.dtb.walker.walksShort 3364 # Table walker walks initiated with short descriptors -system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 665 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 2699 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walkWaitTime::samples 3364 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 3364 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 3364 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 2594 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 10057.247494 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 9203.479719 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 5035.039152 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-8191 1036 39.94% 39.94% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::8192-16383 1440 55.51% 95.45% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::16384-24575 55 2.12% 97.57% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::24576-32767 56 2.16% 99.73% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::40960-49151 6 0.23% 99.96% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::90112-98303 1 0.04% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 2594 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 1650887468 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 1650887468 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 1650887468 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 1937 74.67% 74.67% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::1M 657 25.33% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 2594 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 3364 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walks 3357 # Table walker walks requested +system.cpu1.dtb.walker.walksShort 3357 # Table walker walks initiated with short descriptors +system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 663 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 2694 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walkWaitTime::samples 3357 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 3357 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 3357 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 2587 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 9934.866641 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 9080.760096 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 4767.740714 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-4095 19 0.73% 0.73% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::4096-8191 1032 39.89% 40.63% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::8192-12287 1082 41.82% 82.45% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::12288-16383 330 12.76% 95.21% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::20480-24575 64 2.47% 97.68% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::24576-28671 39 1.51% 99.19% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::28672-32767 16 0.62% 99.81% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::40960-45055 5 0.19% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 2587 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 1655632468 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 1655632468 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 1655632468 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 1932 74.68% 74.68% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::1M 655 25.32% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 2587 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 3357 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 3364 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2594 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 3357 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2587 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2594 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 5958 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2587 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 5944 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 6310579 # DTB read hits -system.cpu1.dtb.read_misses 2859 # DTB read misses -system.cpu1.dtb.write_hits 4631996 # DTB write hits -system.cpu1.dtb.write_misses 505 # DTB write misses +system.cpu1.dtb.read_hits 3844486 # DTB read hits +system.cpu1.dtb.read_misses 2847 # DTB read misses +system.cpu1.dtb.write_hits 3369243 # DTB write hits +system.cpu1.dtb.write_misses 510 # DTB write misses system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 2036 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 2034 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 323 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 293 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 163 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 6313438 # DTB read accesses -system.cpu1.dtb.write_accesses 4632501 # DTB write accesses +system.cpu1.dtb.read_accesses 3847333 # DTB read accesses +system.cpu1.dtb.write_accesses 3369753 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 10942575 # DTB hits -system.cpu1.dtb.misses 3364 # DTB misses -system.cpu1.dtb.accesses 10945939 # DTB accesses +system.cpu1.dtb.hits 7213729 # DTB hits +system.cpu1.dtb.misses 3357 # DTB misses +system.cpu1.dtb.accesses 7217086 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1403,22 +1402,23 @@ system.cpu1.itb.walker.walkWaitTime::samples 1746 system.cpu1.itb.walker.walkWaitTime::0 1746 100.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu1.itb.walker.walkWaitTime::total 1746 # Table walker wait (enqueue to first request) latency system.cpu1.itb.walker.walkCompletionTime::samples 1107 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 10738.482385 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 9680.648713 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 5669.589944 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::4096-8191 351 31.71% 31.71% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::8192-12287 484 43.72% 75.43% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::12288-16383 202 18.25% 93.68% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::16384-20479 20 1.81% 95.48% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::20480-24575 1 0.09% 95.57% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::24576-28671 23 2.08% 97.65% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::28672-32767 15 1.36% 99.01% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 10678.410117 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 9623.001262 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 5682.967955 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::4096-8191 356 32.16% 32.16% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::8192-12287 499 45.08% 77.24% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::12288-16383 181 16.35% 93.59% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::16384-20479 17 1.54% 95.12% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::20480-24575 1 0.09% 95.21% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::24576-28671 30 2.71% 97.92% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::28672-32767 12 1.08% 99.01% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::32768-36863 5 0.45% 99.46% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::40960-45055 6 0.54% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::40960-45055 5 0.45% 99.91% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::45056-49151 1 0.09% 100.00% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::total 1107 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples 1650350468 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 1650350468 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total 1650350468 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::samples 1655094468 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 1655094468 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 1655094468 # Table walker pending requests distribution system.cpu1.itb.walker.walkPageSizes::4K 939 84.82% 84.82% # Table walker page sizes translated system.cpu1.itb.walker.walkPageSizes::1M 168 15.18% 100.00% # Table walker page sizes translated system.cpu1.itb.walker.walkPageSizes::total 1107 # Table walker page sizes translated @@ -1429,7 +1429,7 @@ system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1107 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1107 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin::total 2853 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 27093131 # ITB inst hits +system.cpu1.itb.inst_hits 16180944 # ITB inst hits system.cpu1.itb.inst_misses 1746 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses @@ -1446,171 +1446,171 @@ system.cpu1.itb.domain_faults 0 # Nu system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 27094877 # ITB inst accesses -system.cpu1.itb.hits 27093131 # DTB hits +system.cpu1.itb.inst_accesses 16182690 # ITB inst accesses +system.cpu1.itb.hits 16180944 # DTB hits system.cpu1.itb.misses 1746 # DTB misses -system.cpu1.itb.accesses 27094877 # DTB accesses -system.cpu1.numCycles 5736521358 # number of cpu cycles simulated +system.cpu1.itb.accesses 16182690 # DTB accesses +system.cpu1.numCycles 5736568944 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 26153786 # Number of instructions committed -system.cpu1.committedOps 32053131 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 28968286 # Number of integer alu accesses +system.cpu1.committedInsts 15848207 # Number of instructions committed +system.cpu1.committedOps 19293539 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 17383760 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 1857 # Number of float alu accesses -system.cpu1.num_func_calls 3299674 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 2947168 # number of instructions that are conditional controls -system.cpu1.num_int_insts 28968286 # number of integer instructions +system.cpu1.num_func_calls 938177 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 1786282 # number of instructions that are conditional controls +system.cpu1.num_int_insts 17383760 # number of integer instructions system.cpu1.num_fp_insts 1857 # number of float instructions -system.cpu1.num_int_register_reads 54552282 # number of times the integer registers were read -system.cpu1.num_int_register_writes 20759353 # number of times the integer registers were written +system.cpu1.num_int_register_reads 31469136 # number of times the integer registers were read +system.cpu1.num_int_register_writes 12170371 # number of times the integer registers were written system.cpu1.num_fp_register_reads 1341 # number of times the floating registers were read system.cpu1.num_fp_register_writes 516 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 117965505 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 9826508 # number of times the CC registers were written -system.cpu1.num_mem_refs 11178844 # number of memory refs -system.cpu1.num_load_insts 6422284 # Number of load instructions -system.cpu1.num_store_insts 4756560 # Number of store instructions -system.cpu1.num_idle_cycles 5660914446.273914 # Number of idle cycles -system.cpu1.num_busy_cycles 75606911.726086 # Number of busy cycles -system.cpu1.not_idle_fraction 0.013180 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.986820 # Percentage of idle cycles -system.cpu1.Branches 6348758 # Number of branches fetched +system.cpu1.num_cc_register_reads 70461385 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 6330901 # number of times the CC registers were written +system.cpu1.num_mem_refs 7446495 # number of memory refs +system.cpu1.num_load_insts 3955836 # Number of load instructions +system.cpu1.num_store_insts 3490659 # Number of store instructions +system.cpu1.num_idle_cycles 5686521745.715384 # Number of idle cycles +system.cpu1.num_busy_cycles 50047198.284615 # Number of busy cycles +system.cpu1.not_idle_fraction 0.008724 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.991276 # Percentage of idle cycles +system.cpu1.Branches 2803460 # Number of branches fetched system.cpu1.op_class::No_OpClass 66 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 21763864 65.97% 65.97% # Class of executed instruction -system.cpu1.op_class::IntMult 43243 0.13% 66.10% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 66.10% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 66.10% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 66.10% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 66.10% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 66.10% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 66.10% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 66.10% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 66.10% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 66.10% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 66.10% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 66.10% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 66.10% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 66.10% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 66.10% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 66.10% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 66.10% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 66.10% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 66.10% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 66.10% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 66.10% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 66.10% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 66.10% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 66.10% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 3315 0.01% 66.11% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 66.11% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 66.11% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 66.11% # Class of executed instruction -system.cpu1.op_class::MemRead 6422284 19.47% 85.58% # Class of executed instruction -system.cpu1.op_class::MemWrite 4756560 14.42% 100.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 12144730 61.90% 61.90% # Class of executed instruction +system.cpu1.op_class::IntMult 26187 0.13% 62.03% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 62.03% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 62.03% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 62.03% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 62.03% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 62.03% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 62.03% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 62.03% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 62.03% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 62.03% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 62.03% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 62.03% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 62.03% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 62.03% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 62.03% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 62.03% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 62.03% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 62.03% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 62.03% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 62.03% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 62.03% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 62.03% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 62.03% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 62.03% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 3277 0.02% 62.05% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 62.05% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 62.05% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 62.05% # Class of executed instruction +system.cpu1.op_class::MemRead 3955836 20.16% 82.21% # Class of executed instruction +system.cpu1.op_class::MemWrite 3490659 17.79% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 32989332 # Class of executed instruction +system.cpu1.op_class::total 19620755 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2773 # number of quiesce instructions executed -system.cpu1.dcache.tags.replacements 185916 # number of replacements -system.cpu1.dcache.tags.tagsinuse 465.807736 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 10656106 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 186281 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 57.204471 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 104850302500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 465.807736 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.909781 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.909781 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 365 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 299 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::3 66 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.712891 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 22064450 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 22064450 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 5988472 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 5988472 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 4434786 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 4434786 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 48931 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 48931 # number of SoftPFReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 78766 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 78766 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 70801 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 70801 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 10423258 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 10423258 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 10472189 # number of overall hits -system.cpu1.dcache.overall_hits::total 10472189 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 133050 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 133050 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 91601 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 91601 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30372 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 30372 # number of SoftPFReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 17242 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 17242 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23381 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 23381 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 224651 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 224651 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 255023 # number of overall misses -system.cpu1.dcache.overall_misses::total 255023 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1943965500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 1943965500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2376775500 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 2376775500 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 323304000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 323304000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 547906000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 547906000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 2312500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 2312500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 4320741000 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 4320741000 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 4320741000 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 4320741000 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 6121522 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 6121522 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 4526387 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 4526387 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 79303 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 79303 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 96008 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 96008 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 94182 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 94182 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 10647909 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 10647909 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 10727212 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 10727212 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.021735 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.021735 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.020237 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.020237 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.382987 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.382987 # miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.179589 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.179589 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.248253 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.248253 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.021098 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.021098 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.023773 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.023773 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14610.789177 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 14610.789177 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 25947.047521 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 25947.047521 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18750.956966 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18750.956966 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23433.813780 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23433.813780 # average StoreCondReq miss latency +system.cpu1.kern.inst.quiesce 2725 # number of quiesce instructions executed +system.cpu1.dcache.tags.replacements 186869 # number of replacements +system.cpu1.dcache.tags.tagsinuse 468.718276 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 6945303 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 187221 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 37.096816 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 104852682500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 468.718276 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.915465 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.915465 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 352 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 283 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::3 69 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.687500 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 14648138 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 14648138 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 3533706 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 3533706 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 3181686 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 3181686 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 48716 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 48716 # number of SoftPFReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 78610 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 78610 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 70554 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 70554 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 6715392 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 6715392 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 6764108 # number of overall hits +system.cpu1.dcache.overall_hits::total 6764108 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 133537 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 133537 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 91347 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 91347 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30388 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 30388 # number of SoftPFReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 17048 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 17048 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23285 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 23285 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 224884 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 224884 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 255272 # number of overall misses +system.cpu1.dcache.overall_misses::total 255272 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1938354000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 1938354000 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2351393500 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 2351393500 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 319800000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 319800000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 544967000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 544967000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 2548000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 2548000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 4289747500 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 4289747500 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 4289747500 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 4289747500 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 3667243 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 3667243 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 3273033 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 3273033 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 79104 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 79104 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 95658 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 95658 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 93839 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 93839 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 6940276 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 6940276 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 7019380 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 7019380 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.036413 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.036413 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.027909 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.027909 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.384153 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.384153 # miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.178218 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.178218 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.248138 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.248138 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.032403 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.032403 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.036367 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.036367 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14515.482600 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 14515.482600 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 25741.332501 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 25741.332501 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18758.798686 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18758.798686 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23404.208718 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23404.208718 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19233.126049 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 19233.126049 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16942.554201 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 16942.554201 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19075.378862 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 19075.378862 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16804.614294 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 16804.614294 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1619,147 +1619,147 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 116022 # number of writebacks -system.cpu1.dcache.writebacks::total 116022 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 266 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 266 # number of ReadReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 12054 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 12054 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 266 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 266 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 266 # 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number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 4663 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1799290500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1799290500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2260046500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2260046500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 487726000 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 487726000 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 90112000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 90112000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 521727000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 521727000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2503000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2503000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4059337000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 4059337000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4547063000 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 4547063000 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 302228000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 302228000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 224553500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 224553500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 526781500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 526781500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036341 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036341 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027909 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027909 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.374355 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.374355 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.054758 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.054758 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.248138 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.248138 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.032364 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.032364 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.036218 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.036218 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13501.091769 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13501.091769 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 24741.332501 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 24741.332501 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16469.996285 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 16469.996285 # average SoftPFReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17203.512791 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17203.512791 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22406.141293 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22406.141293 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18225.273525 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18225.273525 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18046.889150 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18046.889150 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 162108.182676 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 162108.182676 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 157509.307918 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 157509.307918 # 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Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.973775 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.973775 # Average percentage of cache occupancy +system.cpu1.icache.tags.replacements 501529 # number of replacements +system.cpu1.icache.tags.tagsinuse 498.573325 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 15678898 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 502041 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 31.230314 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 84707327000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.573325 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.973776 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.973776 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 392 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::3 117 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 387 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::3 122 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::4 3 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 54692301 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 54692301 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 26587077 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 26587077 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 26587077 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 26587077 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 26587077 # 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number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 4455517000 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 27093126 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 27093126 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 27093126 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 27093126 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 27093126 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 27093126 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.018678 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.018678 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.018678 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.018678 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.018678 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.018678 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8804.516954 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 8804.516954 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8804.516954 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 8804.516954 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8804.516954 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 8804.516954 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 32863919 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 32863919 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 15678898 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 15678898 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 15678898 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 15678898 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 15678898 # number of overall hits +system.cpu1.icache.overall_hits::total 15678898 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 502041 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 502041 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 502041 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 502041 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 502041 # number of overall misses +system.cpu1.icache.overall_misses::total 502041 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4374235500 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 4374235500 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 4374235500 # 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number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1768,237 +1768,237 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 506049 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 506049 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 506049 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 506049 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 506049 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 506049 # 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number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4123215000 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 4123215000 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 15225000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 15225000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 15225000 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 15225000 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.031027 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.031027 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.031027 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.031027 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.031027 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.031027 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8212.904922 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8212.904922 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8212.904922 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 8212.904922 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8212.904922 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 8212.904922 # average overall mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 86016.949153 # average ReadReq mshr uncacheable latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 86016.949153 # average ReadReq mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 86016.949153 # average overall mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 86016.949153 # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.l2cache.prefetcher.num_hwpf_issued 199458 # number of hwpf issued -system.cpu1.l2cache.prefetcher.pfIdentified 199458 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.num_hwpf_issued 199800 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 199800 # number of prefetch candidates identified system.cpu1.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu1.l2cache.prefetcher.pfSpanPage 58862 # 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average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15489.483960 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 986250 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 986250 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 32335.537906 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 32335.537906 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 29797.201018 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 29797.201018 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 15846.044556 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 15846.044556 # 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average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 35381.481391 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 24538.704054 # average overall mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 79166.666667 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 154108.182676 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 153157.311828 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 150009.307918 # average WriteReq mshr uncacheable latency -system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 150009.307918 # average WriteReq mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 79166.666667 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 152267.460000 # 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average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15482.397823 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15482.397823 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 1082750 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 1082750 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 32240.143683 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 32240.143683 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 26963.756732 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 26963.756732 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 15739.450869 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 15739.450869 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 14105.263158 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14043.165468 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 26963.756732 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 21281.601585 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 21899.528115 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 14105.263158 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14043.165468 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 26963.756732 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 21281.601585 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 35399.651782 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 24221.103470 # average overall mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 78516.949153 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 112505.582137 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 110264.990689 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 96701.160093 # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 96701.160093 # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 78516.949153 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 105201.586961 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 104225.723140 # average overall mshr uncacheable latency system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.toL2Bus.trans_dist::ReadReq 53469 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 734633 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 30913 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 11227 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::Writeback 478531 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::CleanEvict 680350 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 29761 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 73690 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41411 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 85868 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 55 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 93 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 84408 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 66733 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadCleanReq 506049 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadSharedReq 504061 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadReq 53417 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 719726 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 30874 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 2155 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::Writeback 479672 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::CleanEvict 677908 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 29213 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 72925 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41207 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 85236 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 49 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 92 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 84437 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 66918 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadCleanReq 502041 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadSharedReq 506824 # Transaction distribution system.cpu1.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1509072 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 874243 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 5299 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 9468 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 2398082 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 32387844 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 24934344 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 7900 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 13620 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 57343708 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 1094784 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 2530004 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 1.405048 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.490902 # Request fanout histogram +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1497175 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 834504 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 5289 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 9415 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 2346383 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 32131332 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 24936310 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 7860 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 13456 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 57088958 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 1117653 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 2525896 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 1.414848 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.492696 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 1505230 59.50% 59.50% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 1024774 40.50% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 1478032 58.52% 58.52% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 1047864 41.48% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 2530004 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 878944000 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 2525896 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 861521000 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 80122000 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 79810000 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 759250500 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 753238500 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 390308000 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 375346000 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu1.toL2Bus.respLayer2.occupancy 3324000 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 6063998 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 6051499 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.trans_dist::ReadReq 31015 # Transaction distribution system.iobus.trans_dist::ReadResp 31015 # Transaction distribution -system.iobus.trans_dist::WriteReq 59422 # Transaction distribution -system.iobus.trans_dist::WriteResp 59422 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56602 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::WriteReq 59423 # Transaction distribution +system.iobus.trans_dist::WriteResp 59423 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56604 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) @@ -2232,11 +2232,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 107916 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 107918 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72958 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ide.dma::total 72958 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 180874 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71546 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 180876 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71548 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) @@ -2257,11 +2257,11 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 162796 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 162798 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321272 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::total 2321272 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2484068 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 40091000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 2484070 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 40093000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 90000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -2301,23 +2301,23 @@ system.iobus.reqLayer25.occupancy 30680000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 187549442 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 187554192 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 84718000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 84719000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer3.occupancy 36782000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 36445 # number of replacements -system.iocache.tags.tagsinuse 14.390664 # Cycle average of tags in use +system.iocache.tags.tagsinuse 14.390549 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36461 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 288350117000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 14.390664 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.899417 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.899417 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 288373025000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 14.390549 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.899409 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.899409 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -2331,14 +2331,14 @@ system.iocache.demand_misses::realview.ide 255 # system.iocache.demand_misses::total 255 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 255 # number of overall misses system.iocache.overall_misses::total 255 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 32656876 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 32656876 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 4281964566 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4281964566 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ide 32656876 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 32656876 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 32656876 # number of overall miss cycles -system.iocache.overall_miss_latency::total 32656876 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 32657877 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 32657877 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 4277536315 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4277536315 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ide 32657877 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 32657877 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 32657877 # number of overall miss cycles +system.iocache.overall_miss_latency::total 32657877 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 255 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 255 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) @@ -2355,19 +2355,19 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 128066.180392 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 128066.180392 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118207.944070 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 118207.944070 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 128066.180392 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 128066.180392 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 128066.180392 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 128066.180392 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 265 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 128070.105882 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 128070.105882 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118085.697742 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 118085.697742 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 128070.105882 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 128070.105882 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 128070.105882 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 128070.105882 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 7 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 2 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 132.500000 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 3.500000 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -2381,14 +2381,14 @@ system.iocache.demand_mshr_misses::realview.ide 255 system.iocache.demand_mshr_misses::total 255 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ide 255 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 255 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 19906876 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 19906876 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2470764566 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2470764566 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 19906876 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 19906876 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 19906876 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 19906876 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 19907877 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 19907877 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2466336315 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2466336315 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 19907877 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 19907877 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 19907877 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 19907877 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses @@ -2397,303 +2397,289 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 78066.180392 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 78066.180392 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68207.944070 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68207.944070 # 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Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 32052 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::2 225 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::3 4677 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 27406 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 5 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 276 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 1819 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 29951 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1022 0.492981 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1023 0.000061 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.489075 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 5325589 # Number of tag accesses +system.l2c.tags.data_accesses 5325589 # Number of data accesses +system.l2c.Writeback_hits::writebacks 226708 # number of Writeback hits +system.l2c.Writeback_hits::total 226708 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 2021 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 691 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 2712 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 141 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 160 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 301 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 3915 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 1420 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 5335 # number of ReadExReq hits +system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 81 # 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mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.545731 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.553570 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20812.552251 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20771.243116 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20802.931745 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 20969.665272 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 20786.610879 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 20838.912134 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 86073.326295 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 71707.020590 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 80112.074734 # average ReadExReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 106571.428571 # average ReadSharedReq mshr miss latency system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 73000 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 70603.908046 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 76490.873016 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 87379.261351 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 72500 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 72020.101566 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 79298.832272 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 106662.375100 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 85549.157073 # average ReadSharedReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 76642.857143 # average overall mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 70538.435810 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 77000.510493 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 86379.337344 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 73609.275362 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 78974.735605 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 105312.464651 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 84774.691047 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 106571.428571 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 73000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 70603.908046 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 77341.004902 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 87379.261351 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 72500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 72020.101566 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 71929.991263 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 106662.375100 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 84462.906625 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 76642.857143 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 70538.435810 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 82110.544049 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 86379.337344 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 73609.275362 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 72400.931224 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 105312.464651 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 84296.701714 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 106571.428571 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 73000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 70603.908046 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 77341.004902 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 87379.261351 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 72500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 72020.101566 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 71929.991263 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 106662.375100 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 84462.906625 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 70538.435810 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 82110.544049 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 86379.337344 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 73609.275362 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 72400.931224 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 105312.464651 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 84296.701714 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 63260.252716 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 184031.146376 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 61166.666667 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 136148.703610 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 143860.644766 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 147937.087270 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 133009.129776 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 142515.543622 # average WriteReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 170761.620535 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 60516.949153 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 94661.741214 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 143967.834597 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 147398.638532 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 79700.928074 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 142673.349744 # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 63260.252716 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 166614.055300 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 61166.666667 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 134738.558169 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 143306.163406 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 159771.980542 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 60516.949153 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 87741.682765 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 143434.329613 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 44078 # Transaction distribution -system.membus.trans_dist::ReadResp 214515 # Transaction distribution -system.membus.trans_dist::WriteReq 30913 # Transaction distribution -system.membus.trans_dist::WriteResp 30913 # Transaction distribution -system.membus.trans_dist::Writeback 136511 # Transaction distribution -system.membus.trans_dist::CleanEvict 15728 # Transaction distribution -system.membus.trans_dist::UpgradeReq 75283 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 40251 # Transaction distribution -system.membus.trans_dist::UpgradeResp 12822 # Transaction distribution -system.membus.trans_dist::SCUpgradeFailReq 4 # Transaction distribution -system.membus.trans_dist::ReadExReq 40262 # Transaction distribution -system.membus.trans_dist::ReadExResp 19712 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 170437 # Transaction distribution +system.membus.trans_dist::ReadReq 44038 # Transaction distribution +system.membus.trans_dist::ReadResp 214387 # Transaction distribution +system.membus.trans_dist::WriteReq 30874 # Transaction distribution +system.membus.trans_dist::WriteResp 30874 # Transaction distribution +system.membus.trans_dist::Writeback 136186 # Transaction distribution +system.membus.trans_dist::CleanEvict 15507 # Transaction distribution +system.membus.trans_dist::UpgradeReq 74602 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 39992 # Transaction distribution +system.membus.trans_dist::UpgradeResp 12685 # Transaction distribution +system.membus.trans_dist::SCUpgradeFailReq 7 # Transaction distribution +system.membus.trans_dist::ReadExReq 39841 # Transaction distribution +system.membus.trans_dist::ReadExResp 19332 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 170349 # Transaction distribution system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107916 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107918 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13732 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 672670 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 794352 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13572 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 670072 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 791596 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108921 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 108921 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 903273 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162796 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 900517 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162798 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27464 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18608200 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 18798528 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27144 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18557448 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 18747458 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 21115648 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 123870 # Total snoops (count) -system.membus.snoop_fanout::samples 589976 # Request fanout histogram +system.membus.pkt_size::total 21064578 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 123030 # Total snoops (count) +system.membus.snoop_fanout::samples 587901 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 589976 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 587901 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 589976 # Request fanout histogram -system.membus.reqLayer0.occupancy 88273000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 587901 # Request fanout histogram +system.membus.reqLayer0.occupancy 88280499 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 19000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 11464500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 11327500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 1021914451 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 983138119 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1141120383 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1138149025 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 64390592 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 64374606 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -2999,46 +2973,46 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.trans_dist::ReadReq 44082 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 479204 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 30913 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 30913 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 362509 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 82484 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 77999 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 40531 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 118530 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 93 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 93 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 51218 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 51218 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 435137 # Transaction distribution +system.toL2Bus.trans_dist::ReadReq 44042 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 480570 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 30874 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 30874 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 362932 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 82945 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 77217 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 40293 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 117510 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 92 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 92 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 50721 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 50721 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 436543 # Transaction distribution system.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1069100 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 319954 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 1389054 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 31596740 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 4900924 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 36497664 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 452334 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 1194337 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.170309 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.375904 # Request fanout histogram +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1115711 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 276298 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 1392009 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 31905816 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 4776938 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 36682754 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 449881 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 1195846 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.169748 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.375411 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 990931 82.97% 82.97% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 203406 17.03% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 992854 83.03% 83.03% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 202992 16.97% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 1194337 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 799819351 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 1195846 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 812251839 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) system.toL2Bus.snoopLayer0.occupancy 360000 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 609335323 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 627943021 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 239074701 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 221271516 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt index 65214b87e..c7177147a 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt @@ -4,10 +4,10 @@ sim_seconds 0.000018 # Nu sim_ticks 17777000 # Number of ticks simulated final_tick 17777000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 63568 # Simulator instruction rate (inst/s) -host_op_rate 74435 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 246000775 # Simulator tick rate (ticks/s) -host_mem_usage 307848 # Number of bytes of host memory used +host_inst_rate 63242 # Simulator instruction rate (inst/s) +host_op_rate 74054 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 244740900 # Simulator tick rate (ticks/s) +host_mem_usage 307828 # Number of bytes of host memory used host_seconds 0.07 # Real time elapsed on the host sim_insts 4592 # Number of instructions simulated sim_ops 5378 # Number of ops (including micro ops) simulated @@ -94,16 +94,16 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 224 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 225 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 126 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 30 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 13 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 12 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see @@ -204,12 +204,12 @@ system.physmem.bytesPerActivate::768-895 3 5.08% 79.66% # By system.physmem.bytesPerActivate::896-1023 2 3.39% 83.05% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 10 16.95% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 59 # Bytes accessed per row activation -system.physmem.totQLat 3256492 # Total ticks spent queuing -system.physmem.totMemAccLat 10887742 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 3130500 # Total ticks spent queuing +system.physmem.totMemAccLat 10761750 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2035000 # Total ticks spent in databus transfers -system.physmem.avgQLat 8001.21 # Average queueing delay per DRAM burst +system.physmem.avgQLat 7691.65 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26751.21 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 26441.65 # Average memory access latency per DRAM burst system.physmem.avgRdBW 1465.26 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 1465.26 # Average system read bandwidth in MiByte/s @@ -218,7 +218,7 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 11.45 # Data bus utilization in percentage system.physmem.busUtilRead 11.45 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.77 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.81 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing system.physmem.readRowHits 340 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes @@ -231,28 +231,28 @@ system.physmem_0.preEnergy 160875 # En system.physmem_0.readEnergy 2043600 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 10756755 # Energy for active background per rank (pJ) +system.physmem_0.actBackEnergy 10766160 # Energy for active background per rank (pJ) system.physmem_0.preBackEnergy 63750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 14336940 # Total energy per rank (pJ) -system.physmem_0.averagePower 905.538607 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 334000 # Time in different power states +system.physmem_0.totalEnergy 14346345 # Total energy per rank (pJ) +system.physmem_0.averagePower 905.346375 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 321250 # Time in different power states system.physmem_0.memoryStateTime::REF 520000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 15275500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 15288250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.physmem_1.actEnergy 128520 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 70125 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 795600 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 10156545 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 590250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 12758160 # Total energy per rank (pJ) -system.physmem_1.averagePower 805.820938 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 942000 # Time in different power states +system.physmem_1.actBackEnergy 10149705 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 596250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 12757320 # Total energy per rank (pJ) +system.physmem_1.averagePower 805.767883 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 952000 # Time in different power states system.physmem_1.memoryStateTime::REF 520000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 14384250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 14374250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.branchPred.lookups 2336 # Number of BP lookups system.cpu.branchPred.condPredicted 1386 # Number of conditional branches predicted @@ -384,80 +384,80 @@ system.cpu.workload.num_syscalls 13 # Nu system.cpu.numCycles 35555 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 6172 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.icacheStallCycles 6171 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.Insts 11259 # Number of instructions fetch has processed system.cpu.fetch.Branches 2336 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 731 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 7501 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.Cycles 7640 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 1059 # Number of cycles fetch has spent squashing system.cpu.fetch.MiscStallCycles 155 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 303 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 318 # Number of stall cycles due to full MSHR system.cpu.fetch.CacheLines 3825 # Number of cache lines fetched system.cpu.fetch.IcacheSquashes 176 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 14978 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.878021 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.210560 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::samples 15116 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.870204 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.208015 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 8782 58.63% 58.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2458 16.41% 75.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 521 3.48% 78.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 3217 21.48% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 8919 59.00% 59.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2458 16.26% 75.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 521 3.45% 78.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 3218 21.29% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 14978 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 15116 # Number of instructions fetched each cycle (Total) system.cpu.fetch.branchRate 0.065701 # Number of branch fetches per cycle system.cpu.fetch.rate 0.316664 # Number of inst fetches per cycle system.cpu.decode.IdleCycles 5920 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 3520 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 5039 # Number of cycles decode is running +system.cpu.decode.BlockedCycles 3659 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 5038 # Number of cycles decode is running system.cpu.decode.UnblockCycles 131 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 368 # Number of cycles decode is squashing system.cpu.decode.BranchResolved 329 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 164 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 9859 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 1620 # Number of squashed instructions handled by decode +system.cpu.decode.DecodedInsts 9862 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 1622 # Number of squashed instructions handled by decode system.cpu.rename.SquashCycles 368 # Number of cycles rename is squashing system.cpu.rename.IdleCycles 6989 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 960 # Number of cycles rename is blocking +system.cpu.rename.BlockCycles 961 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 1965 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 4095 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 601 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 8880 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 409 # Number of squashed instructions processed by rename +system.cpu.rename.RunCycles 4094 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 739 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 8883 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 411 # Number of squashed instructions processed by rename system.cpu.rename.ROBFullEvents 15 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 1 # Number of times rename has blocked due to IQ full system.cpu.rename.LQFullEvents 9 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 527 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 9231 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 40283 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 9759 # Number of integer rename lookups +system.cpu.rename.SQFullEvents 665 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 9235 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 40294 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 9761 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 17 # Number of floating rename lookups system.cpu.rename.CommittedMaps 5494 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 3737 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 3741 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 30 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 28 # count of temporary serializing insts renamed system.cpu.rename.skidInsts 299 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 1806 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedLoads 1807 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 1277 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 8347 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 8348 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 39 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 7144 # Number of instructions issued +system.cpu.iq.iqInstsIssued 7146 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 184 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 3008 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 7841 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedInstsExamined 3009 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 7843 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 14978 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.476966 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 0.861224 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 15116 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.472744 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 0.858488 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 10780 71.97% 71.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1947 13.00% 84.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 1601 10.69% 95.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 605 4.04% 99.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 10916 72.21% 72.21% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1949 12.89% 85.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 1601 10.59% 95.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 605 4.00% 99.70% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::4 45 0.30% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle @@ -466,90 +466,90 @@ system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Nu system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 4 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 14978 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 15116 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 411 28.90% 28.90% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 28.90% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 28.90% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 28.90% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 28.90% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 28.90% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 28.90% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 28.90% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 28.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 28.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 28.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 28.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 28.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 28.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 28.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 28.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 28.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 28.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 28.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 28.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 28.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 28.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 28.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 28.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 28.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 28.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 28.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 28.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 28.90% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 464 32.63% 61.53% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 547 38.47% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 412 28.93% 28.93% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 28.93% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 28.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 28.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 28.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 28.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 28.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 28.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 28.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 28.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 28.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 28.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 28.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 28.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 28.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 28.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 28.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 28.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 28.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 28.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 28.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 28.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 28.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 28.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 28.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 28.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 28.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 28.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 28.93% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 465 32.65% 61.59% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 547 38.41% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 4467 62.53% 62.53% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 5 0.07% 62.60% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.60% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.60% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.60% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.60% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.60% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.60% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.60% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 4468 62.52% 62.52% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 5 0.07% 62.59% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.59% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.59% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.59% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.59% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.59% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.59% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.59% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 62.64% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.64% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.64% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.64% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 1588 22.23% 84.87% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 1589 22.24% 84.87% # Type of FU issued system.cpu.iq.FU_type_0::MemWrite 1081 15.13% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 7144 # Type of FU issued -system.cpu.iq.rate 0.200928 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1422 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.199048 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 30828 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 11385 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 6550 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 7146 # Type of FU issued +system.cpu.iq.rate 0.200984 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1424 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.199272 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 30972 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 11387 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 6551 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 44 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 8538 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 8542 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 28 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 10 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 779 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 780 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 7 # Number of memory ordering violations system.cpu.iew.lsq.thread0.squashedStores 339 # Number of stores squashed @@ -559,11 +559,11 @@ system.cpu.iew.lsq.thread0.rescheduledLoads 5 # system.cpu.iew.lsq.thread0.cacheBlocked 18 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewSquashCycles 368 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 356 # Number of cycles IEW is blocking +system.cpu.iew.iewBlockCycles 357 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 10 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 8400 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispatchedInsts 8401 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 1806 # Number of dispatched load instructions +system.cpu.iew.iewDispLoadInsts 1807 # Number of dispatched load instructions system.cpu.iew.iewDispStoreInsts 1277 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 27 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall @@ -572,43 +572,43 @@ system.cpu.iew.memOrderViolationEvents 7 # Nu system.cpu.iew.predictedTakenIncorrect 67 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 294 # Number of branches that were predicted not taken incorrectly system.cpu.iew.branchMispredicts 361 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 6741 # Number of executed instructions +system.cpu.iew.iewExecutedInsts 6742 # Number of executed instructions system.cpu.iew.iewExecLoadInsts 1404 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 403 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecSquashedInsts 404 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 14 # number of nop insts executed system.cpu.iew.exec_refs 2427 # number of memory reference insts executed system.cpu.iew.exec_branches 1272 # Number of branches executed system.cpu.iew.exec_stores 1023 # Number of stores executed -system.cpu.iew.exec_rate 0.189594 # Inst execution rate -system.cpu.iew.wb_sent 6608 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 6566 # cumulative count of insts written-back -system.cpu.iew.wb_producers 2973 # num instructions producing a value -system.cpu.iew.wb_consumers 5368 # num instructions consuming a value +system.cpu.iew.exec_rate 0.189622 # Inst execution rate +system.cpu.iew.wb_sent 6609 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 6567 # cumulative count of insts written-back +system.cpu.iew.wb_producers 2975 # num instructions producing a value +system.cpu.iew.wb_consumers 5372 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.184672 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.553838 # average fanout of values written-back +system.cpu.iew.wb_rate 0.184700 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.553797 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 2565 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 2568 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 347 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 14437 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.372515 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.021269 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 14574 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.369013 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.017093 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 11787 81.64% 81.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1388 9.61% 91.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 602 4.17% 95.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 293 2.03% 97.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 168 1.16% 98.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 78 0.54% 99.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 45 0.31% 99.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 11924 81.82% 81.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1388 9.52% 91.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 602 4.13% 95.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 293 2.01% 97.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 168 1.15% 98.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 78 0.54% 99.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 45 0.31% 99.48% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::7 33 0.23% 99.70% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::8 43 0.30% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 14437 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 14574 # Number of insts commited each cycle system.cpu.commit.committedInsts 4592 # Number of instructions committed system.cpu.commit.committedOps 5378 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -655,32 +655,32 @@ system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Cl system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 5378 # Class of committed instruction system.cpu.commit.bw_lim_events 43 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 22180 # The number of ROB reads -system.cpu.rob.rob_writes 16432 # The number of ROB writes +system.cpu.rob.rob_reads 22320 # The number of ROB reads +system.cpu.rob.rob_writes 16439 # The number of ROB writes system.cpu.timesIdled 214 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 20577 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 20439 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 4592 # Number of Instructions Simulated system.cpu.committedOps 5378 # Number of Ops (including micro ops) Simulated system.cpu.cpi 7.742814 # CPI: Cycles Per Instruction system.cpu.cpi_total 7.742814 # CPI: Total CPI of All Threads system.cpu.ipc 0.129152 # IPC: Instructions Per Cycle system.cpu.ipc_total 0.129152 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 6717 # number of integer regfile reads +system.cpu.int_regfile_reads 6718 # number of integer regfile reads system.cpu.int_regfile_writes 3745 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.cc_regfile_reads 23956 # number of cc regfile reads -system.cpu.cc_regfile_writes 2895 # number of cc regfile writes +system.cpu.cc_regfile_reads 23959 # number of cc regfile reads +system.cpu.cc_regfile_writes 2898 # number of cc regfile writes system.cpu.misc_regfile_reads 2607 # number of misc regfile reads system.cpu.misc_regfile_writes 24 # number of misc regfile writes system.cpu.dcache.tags.replacements 1 # number of replacements -system.cpu.dcache.tags.tagsinuse 84.382295 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 84.292966 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1915 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 142 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 13.485915 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 84.382295 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.164809 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.164809 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 84.292966 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.164635 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.164635 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 141 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 88 # Occupied blocks per task id @@ -711,14 +711,14 @@ system.cpu.dcache.overall_misses::cpu.data 358 # system.cpu.dcache.overall_misses::total 358 # number of overall misses system.cpu.dcache.ReadReq_miss_latency::cpu.data 9199500 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 9199500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 7245500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 7245500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 7717500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 7717500 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 125000 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 125000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 16445000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 16445000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 16445000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 16445000 # number of overall miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 16917000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 16917000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 16917000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 16917000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1340 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1340 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) @@ -743,20 +743,20 @@ system.cpu.dcache.overall_miss_rate::cpu.data 0.158899 system.cpu.dcache.overall_miss_rate::total 0.158899 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55086.826347 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 55086.826347 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37934.554974 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 37934.554974 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 40405.759162 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 40405.759162 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 62500 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 62500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 45935.754190 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 45935.754190 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 45935.754190 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 45935.754190 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 47254.189944 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 47254.189944 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 47254.189944 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 47254.189944 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 731 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 829 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 18 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 40.611111 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 46.055556 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.ReadReq_mshr_hits::cpu.data 65 # number of ReadReq MSHR hits @@ -779,12 +779,12 @@ system.cpu.dcache.overall_mshr_misses::cpu.data 143 system.cpu.dcache.overall_mshr_misses::total 143 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5829500 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 5829500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2385500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2385500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8215000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 8215000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8215000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 8215000 # number of overall MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2454500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2454500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8284000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 8284000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8284000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 8284000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076119 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076119 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044907 # mshr miss rate for WriteReq accesses @@ -795,25 +795,25 @@ system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.063471 system.cpu.dcache.overall_mshr_miss_rate::total 0.063471 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 57151.960784 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 57151.960784 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 58182.926829 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 58182.926829 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 57447.552448 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 57447.552448 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 57447.552448 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 57447.552448 # average overall mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59865.853659 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59865.853659 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 57930.069930 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 57930.069930 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 57930.069930 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 57930.069930 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 42 # number of replacements -system.cpu.icache.tags.tagsinuse 136.424572 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 136.256883 # Cycle average of tags in use system.cpu.icache.tags.total_refs 3459 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 295 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 11.725424 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 136.424572 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.266454 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.266454 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 136.256883 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.266127 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.266127 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 253 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 161 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 92 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 162 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 91 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.494141 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 7941 # Number of tag accesses system.cpu.icache.tags.data_accesses 7941 # Number of data accesses @@ -829,12 +829,12 @@ system.cpu.icache.demand_misses::cpu.inst 364 # n system.cpu.icache.demand_misses::total 364 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 364 # number of overall misses system.cpu.icache.overall_misses::total 364 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 21691493 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 21691493 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 21691493 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 21691493 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 21691493 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 21691493 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 21567493 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 21567493 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 21567493 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 21567493 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 21567493 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 21567493 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 3823 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 3823 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 3823 # number of demand (read+write) accesses @@ -847,17 +847,17 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.095213 system.cpu.icache.demand_miss_rate::total 0.095213 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.095213 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.095213 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 59592.013736 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 59592.013736 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 59592.013736 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 59592.013736 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 59592.013736 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 59592.013736 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 8521 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 59251.354396 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 59251.354396 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 59251.354396 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 59251.354396 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 59251.354396 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 59251.354396 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 8431 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 33 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 89 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 95.741573 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 94.730337 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets 33 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed @@ -873,24 +873,24 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 296 system.cpu.icache.demand_mshr_misses::total 296 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 296 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 296 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 18899993 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 18899993 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 18899993 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 18899993 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 18899993 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 18899993 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 18780993 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 18780993 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 18780993 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 18780993 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 18780993 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 18780993 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.077426 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.077426 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.077426 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.077426 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.077426 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.077426 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 63851.327703 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 63851.327703 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 63851.327703 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 63851.327703 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 63851.327703 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 63851.327703 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 63449.300676 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 63449.300676 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 63449.300676 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 63449.300676 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 63449.300676 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 63449.300676 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.prefetcher.num_hwpf_issued 112 # number of hwpf issued system.cpu.l2cache.prefetcher.pfIdentified 112 # number of prefetch candidates identified @@ -899,24 +899,24 @@ system.cpu.l2cache.prefetcher.pfInCache 0 # nu system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size system.cpu.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 193.028614 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 192.829480 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 74 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 364 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.203297 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 138.716720 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 45.124038 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 9.187855 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.008467 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.002754 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.000561 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.011782 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 138.531593 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 45.093662 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 9.204225 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.008455 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.002752 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.000562 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.011769 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1022 16 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_blocks::1024 348 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1022::0 8 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1022::1 8 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 180 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 168 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 182 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 166 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1022 0.000977 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.021240 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 7941 # Number of tag accesses @@ -945,18 +945,18 @@ system.cpu.l2cache.demand_misses::total 386 # nu system.cpu.l2cache.overall_misses::cpu.inst 273 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 113 # number of overall misses system.cpu.l2cache.overall_misses::total 386 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2251000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 2251000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 18451000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 18451000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2320000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 2320000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 18332000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 18332000 # number of ReadCleanReq miss cycles system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 5549000 # number of ReadSharedReq miss cycles system.cpu.l2cache.ReadSharedReq_miss_latency::total 5549000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 18451000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7800000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 26251000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 18451000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7800000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 26251000 # number of overall miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 18332000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 7869000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 26201000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 18332000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 7869000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 26201000 # number of overall miss cycles system.cpu.l2cache.ReadExReq_accesses::cpu.data 41 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 41 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 296 # number of ReadCleanReq accesses(hits+misses) @@ -981,18 +981,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.879271 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.922297 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.790210 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.879271 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75033.333333 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75033.333333 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 67586.080586 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 67586.080586 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77333.333333 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77333.333333 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 67150.183150 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 67150.183150 # average ReadCleanReq miss latency system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 66855.421687 # average ReadSharedReq miss latency system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 66855.421687 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67586.080586 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69026.548673 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 68007.772021 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67586.080586 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69026.548673 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 68007.772021 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67150.183150 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69637.168142 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 67878.238342 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67150.183150 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69637.168142 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 67878.238342 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1026,21 +1026,21 @@ system.cpu.l2cache.overall_mshr_misses::cpu.inst 272 system.cpu.l2cache.overall_mshr_misses::cpu.data 108 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 48 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 428 # number of overall MSHR misses -system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 1697924 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 1697924 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2071000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2071000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 16769500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 16769500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 1625926 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 1625926 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2140000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2140000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 16650500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 16650500 # number of ReadCleanReq MSHR miss cycles system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4788500 # number of ReadSharedReq MSHR miss cycles system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4788500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16769500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6859500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 23629000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16769500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6859500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 1697924 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 25326924 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16650500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6928500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 23579000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16650500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6928500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 1625926 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 25204926 # number of overall MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.731707 # mshr miss rate for ReadExReq accesses @@ -1056,21 +1056,21 @@ system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.918919 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.755245 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.974943 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 35373.416667 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 35373.416667 # average HardPFReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69033.333333 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69033.333333 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 61652.573529 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 61652.573529 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 33873.458333 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 33873.458333 # average HardPFReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71333.333333 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71333.333333 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 61215.073529 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 61215.073529 # average ReadCleanReq mshr miss latency system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 61391.025641 # average ReadSharedReq mshr miss latency system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 61391.025641 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61652.573529 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63513.888889 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62181.578947 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61652.573529 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63513.888889 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 35373.416667 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59175.056075 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61215.073529 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64152.777778 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62050 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61215.073529 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64152.777778 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 33873.458333 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58890.014019 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadResp 396 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 32 # Transaction distribution @@ -1122,9 +1122,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 407 # Request fanout histogram -system.membus.reqLayer0.occupancy 510442 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 514444 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.9 # Layer utilization (%) -system.membus.respLayer1.occupancy 2136258 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2136000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 12.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- |