diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2014-12-23 09:31:20 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2014-12-23 09:31:20 -0500 |
| commit | df8df4fd0a95763cb0658cbe77615e7deac391d3 (patch) | |
| tree | 0c8776db2ef482a4f6e5db099133105f9af799d7 /tests/quick | |
| parent | b2342c5d9aea0b732f6d5a5b6c9c3961940ed8e7 (diff) | |
| download | gem5-df8df4fd0a95763cb0658cbe77615e7deac391d3.tar.xz | |
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes
Changes due to speculative execution of an unaligned PC, introduction
of TLB stats, changes and re-work of the prefetcher, and the
introduction of rank-wise refresh in the DRAM controller.
Diffstat (limited to 'tests/quick')
56 files changed, 25247 insertions, 23727 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt index 9ca2241e2..7159169af 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt @@ -1,118 +1,118 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.962845 # Number of seconds simulated -sim_ticks 1962844580000 # Number of ticks simulated -final_tick 1962844580000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.962843 # Number of seconds simulated +sim_ticks 1962842856000 # Number of ticks simulated +final_tick 1962842856000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1184099 # Simulator instruction rate (inst/s) -host_op_rate 1184098 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 38148129943 # Simulator tick rate (ticks/s) -host_mem_usage 318172 # Number of bytes of host memory used -host_seconds 51.45 # Real time elapsed on the host -sim_insts 60925667 # Number of instructions simulated -sim_ops 60925667 # Number of ops (including micro ops) simulated +host_inst_rate 1228880 # Simulator instruction rate (inst/s) +host_op_rate 1228880 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 39594262798 # Simulator tick rate (ticks/s) +host_mem_usage 373652 # Number of bytes of host memory used +host_seconds 49.57 # Real time elapsed on the host +sim_insts 60920382 # Number of instructions simulated +sim_ops 60920382 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.inst 823168 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24882816 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 41728 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 386368 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 823232 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24883392 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 41664 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 386496 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 26135040 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 823168 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 41728 # Number of instructions bytes read from this memory +system.physmem.bytes_read::total 26135744 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 823232 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 41664 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 864896 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7758336 # Number of bytes written to this memory -system.physmem.bytes_written::total 7758336 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 12862 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 388794 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 652 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 6037 # Number of read requests responded to by this memory +system.physmem.bytes_written::writebacks 7759040 # Number of bytes written to this memory +system.physmem.bytes_written::total 7759040 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 12863 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 388803 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 651 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 6039 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 408360 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 121224 # Number of write requests responded to by this memory -system.physmem.num_writes::total 121224 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 419375 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 12676916 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 21259 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 196841 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::total 408371 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 121235 # Number of write requests responded to by this memory +system.physmem.num_writes::total 121235 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 419408 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 12677221 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 21226 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 196906 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 489 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13314880 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 419375 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 21259 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 13315250 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 419408 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 21226 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 440634 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3952598 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3952598 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3952598 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 419375 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 12676916 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 21259 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 196841 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::writebacks 3952960 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3952960 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3952960 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 419408 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 12677221 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 21226 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 196906 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 489 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17267478 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 408360 # Number of read requests accepted -system.physmem.writeReqs 162776 # Number of write requests accepted -system.physmem.readBursts 408360 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 162776 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 26127936 # Total number of bytes read from DRAM +system.physmem.bw_total::total 17268211 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 408371 # Number of read requests accepted +system.physmem.writeReqs 162787 # Number of write requests accepted +system.physmem.readBursts 408371 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 162787 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 26128640 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 7104 # Total number of bytes read from write queue -system.physmem.bytesWritten 10271680 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 26135040 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 10417664 # Total written bytes from the system interface side +system.physmem.bytesWritten 10277440 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 26135744 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 10418368 # Total written bytes from the system interface side system.physmem.servicedByWrQ 111 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2254 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 7048 # Number of requests that are neither read nor write +system.physmem.mergedWrBursts 2175 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 7051 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 25705 # Per bank write bursts system.physmem.perBankRdBursts::1 25985 # Per bank write bursts -system.physmem.perBankRdBursts::2 25732 # Per bank write bursts -system.physmem.perBankRdBursts::3 25537 # Per bank write bursts +system.physmem.perBankRdBursts::2 25737 # Per bank write bursts +system.physmem.perBankRdBursts::3 25534 # Per bank write bursts system.physmem.perBankRdBursts::4 24847 # Per bank write bursts -system.physmem.perBankRdBursts::5 24747 # Per bank write bursts +system.physmem.perBankRdBursts::5 24754 # Per bank write bursts system.physmem.perBankRdBursts::6 25534 # Per bank write bursts -system.physmem.perBankRdBursts::7 25495 # Per bank write bursts +system.physmem.perBankRdBursts::7 25489 # Per bank write bursts system.physmem.perBankRdBursts::8 25150 # Per bank write bursts system.physmem.perBankRdBursts::9 25518 # Per bank write bursts system.physmem.perBankRdBursts::10 25462 # Per bank write bursts -system.physmem.perBankRdBursts::11 25292 # Per bank write bursts +system.physmem.perBankRdBursts::11 25296 # Per bank write bursts system.physmem.perBankRdBursts::12 25577 # Per bank write bursts system.physmem.perBankRdBursts::13 25454 # Per bank write bursts system.physmem.perBankRdBursts::14 26241 # Per bank write bursts -system.physmem.perBankRdBursts::15 25973 # Per bank write bursts -system.physmem.perBankWrBursts::0 10613 # Per bank write bursts -system.physmem.perBankWrBursts::1 10753 # Per bank write bursts -system.physmem.perBankWrBursts::2 9796 # Per bank write bursts -system.physmem.perBankWrBursts::3 9387 # Per bank write bursts -system.physmem.perBankWrBursts::4 8893 # Per bank write bursts -system.physmem.perBankWrBursts::5 9110 # Per bank write bursts -system.physmem.perBankWrBursts::6 9958 # Per bank write bursts -system.physmem.perBankWrBursts::7 9669 # Per bank write bursts -system.physmem.perBankWrBursts::8 9689 # Per bank write bursts -system.physmem.perBankWrBursts::9 9901 # Per bank write bursts -system.physmem.perBankWrBursts::10 9876 # Per bank write bursts -system.physmem.perBankWrBursts::11 10215 # Per bank write bursts -system.physmem.perBankWrBursts::12 10815 # Per bank write bursts -system.physmem.perBankWrBursts::13 10652 # Per bank write bursts -system.physmem.perBankWrBursts::14 10531 # Per bank write bursts -system.physmem.perBankWrBursts::15 10637 # Per bank write bursts +system.physmem.perBankRdBursts::15 25977 # Per bank write bursts +system.physmem.perBankWrBursts::0 10598 # Per bank write bursts +system.physmem.perBankWrBursts::1 10761 # Per bank write bursts +system.physmem.perBankWrBursts::2 9727 # Per bank write bursts +system.physmem.perBankWrBursts::3 9433 # Per bank write bursts +system.physmem.perBankWrBursts::4 8910 # Per bank write bursts +system.physmem.perBankWrBursts::5 9140 # Per bank write bursts +system.physmem.perBankWrBursts::6 9908 # Per bank write bursts +system.physmem.perBankWrBursts::7 9771 # Per bank write bursts +system.physmem.perBankWrBursts::8 9710 # Per bank write bursts +system.physmem.perBankWrBursts::9 9867 # Per bank write bursts +system.physmem.perBankWrBursts::10 9923 # Per bank write bursts +system.physmem.perBankWrBursts::11 10306 # Per bank write bursts +system.physmem.perBankWrBursts::12 10733 # Per bank write bursts +system.physmem.perBankWrBursts::13 10678 # Per bank write bursts +system.physmem.perBankWrBursts::14 10553 # Per bank write bursts +system.physmem.perBankWrBursts::15 10567 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 1962839541500 # Total gap between requests +system.physmem.totGap 1962837817500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 408360 # Read request sizes (log2) +system.physmem.readPktSize::6 408371 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 162776 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 408168 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 68 # What read queue length does an incoming req see +system.physmem.writePktSize::6 162787 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 408177 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 70 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see @@ -158,173 +158,178 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2297 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4384 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 8312 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 9464 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 10119 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 10932 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 11465 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 12365 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 11871 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 11907 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 10784 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 10008 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 8529 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8090 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6890 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6447 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6307 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6230 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 345 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 313 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 293 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 281 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 266 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 222 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 199 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 227 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 212 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 223 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 206 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 191 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 177 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 154 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 142 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2283 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 4404 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 8320 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 9433 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 10077 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 10961 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 11550 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 12406 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 11941 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 12017 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 10895 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 10072 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 8581 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8107 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6888 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6429 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6271 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6194 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 291 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 265 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 272 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 253 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 226 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 202 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 193 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 201 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 189 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 194 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 193 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 184 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 163 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 141 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 130 # What write queue length does an incoming req see system.physmem.wrQLenPdf::48 124 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 103 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 94 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 80 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 52 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 117 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 106 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 92 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 76 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 59 # What write queue length does an incoming req see system.physmem.wrQLenPdf::54 45 # What write queue length does an incoming req see system.physmem.wrQLenPdf::55 26 # What write queue length does an incoming req see system.physmem.wrQLenPdf::56 18 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 3 # What write queue length does an incoming req see system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 69162 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 526.295017 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 318.923666 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 416.254848 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 16035 23.18% 23.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 12178 17.61% 40.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5186 7.50% 48.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3086 4.46% 52.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 3308 4.78% 57.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1800 2.60% 60.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1507 2.18% 62.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1316 1.90% 64.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 24746 35.78% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 69162 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5880 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 69.428401 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2107.963348 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-4095 5875 99.91% 99.91% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 69318 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 525.203843 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 317.866807 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 416.347675 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 16137 23.28% 23.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 12161 17.54% 40.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5284 7.62% 48.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3087 4.45% 52.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 3309 4.77% 57.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1757 2.53% 60.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1519 2.19% 62.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1296 1.87% 64.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 24768 35.73% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 69318 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5881 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 69.418466 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2107.784288 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-4095 5876 99.91% 99.91% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::4096-8191 1 0.02% 99.93% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-45055 1 0.02% 99.95% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-61439 1 0.02% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::73728-77823 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::122880-126975 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5880 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5880 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 27.295068 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 20.802481 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 33.368634 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 4837 82.26% 82.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 186 3.16% 85.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 281 4.78% 90.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 57 0.97% 91.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 98 1.67% 92.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 42 0.71% 93.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 21 0.36% 93.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 12 0.20% 94.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 21 0.36% 94.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 6 0.10% 94.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 10 0.17% 94.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 8 0.14% 94.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-119 13 0.22% 95.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-127 5 0.09% 95.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 22 0.37% 95.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-143 44 0.75% 96.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-151 23 0.39% 96.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-159 6 0.10% 96.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-167 80 1.36% 98.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 40 0.68% 98.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 14 0.24% 99.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-191 24 0.41% 99.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-199 14 0.24% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-207 2 0.03% 99.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-215 5 0.09% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-223 1 0.02% 99.86% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 5881 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5881 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 27.305730 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 20.811619 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 33.369719 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 4828 82.09% 82.09% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 189 3.21% 85.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 283 4.81% 90.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 60 1.02% 91.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-55 106 1.80% 92.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-63 43 0.73% 93.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-71 17 0.29% 93.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-79 8 0.14% 94.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-87 22 0.37% 94.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-95 7 0.12% 94.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-103 14 0.24% 94.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-111 3 0.05% 94.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-119 16 0.27% 95.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-127 2 0.03% 95.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-135 15 0.26% 95.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-143 48 0.82% 96.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-151 18 0.31% 96.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-159 12 0.20% 96.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-167 85 1.45% 98.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-175 44 0.75% 98.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-183 9 0.15% 99.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-191 24 0.41% 99.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-199 10 0.17% 99.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-207 3 0.05% 99.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-215 5 0.09% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::216-223 2 0.03% 99.86% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::224-231 2 0.03% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::232-239 1 0.02% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::240-247 4 0.07% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-263 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5880 # Writes before turning the bus around for reads -system.physmem.totQLat 2202002500 # Total ticks spent queuing -system.physmem.totMemAccLat 9856671250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2041245000 # Total ticks spent in databus transfers -system.physmem.avgQLat 5393.77 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::232-239 2 0.03% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-247 3 0.05% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::264-271 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5881 # Writes before turning the bus around for reads +system.physmem.totQLat 2189518000 # Total ticks spent queuing +system.physmem.totMemAccLat 9844393000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2041300000 # Total ticks spent in databus transfers +system.physmem.avgQLat 5363.05 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 24143.77 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 24113.05 # Average memory access latency per DRAM burst system.physmem.avgRdBW 13.31 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 5.23 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 13.31 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBW 5.24 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 13.32 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 5.31 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.14 # Data bus utilization in percentage system.physmem.busUtilRead 0.10 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.04 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 26.11 # Average write queue length when enqueuing -system.physmem.readRowHits 365785 # Number of row buffer hits during reads -system.physmem.writeRowHits 133797 # Number of row buffer hits during writes -system.physmem.readRowHitRate 89.60 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 83.35 # Row buffer hit rate for writes -system.physmem.avgGap 3436728.80 # Average gap between requests -system.physmem.pageHitRate 87.84 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 1840639787000 # Time in different power states -system.physmem.memoryStateTime::REF 65543660000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 56660375500 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 257115600 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 265749120 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 140291250 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 145002000 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 1587939600 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 1596402600 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 506599920 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 533407680 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 128203398960 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 128203398960 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 65563204050 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 65997539775 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 1120194702750 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 1119813706500 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 1316453252130 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 1316555206635 # Total energy per rank (pJ) -system.physmem.averagePower::0 670.686708 # Core power per rank (mW) -system.physmem.averagePower::1 670.738650 # Core power per rank (mW) +system.physmem.avgWrQLen 25.78 # Average write queue length when enqueuing +system.physmem.readRowHits 365775 # Number of row buffer hits during reads +system.physmem.writeRowHits 133752 # Number of row buffer hits during writes +system.physmem.readRowHitRate 89.59 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 83.28 # Row buffer hit rate for writes +system.physmem.avgGap 3436593.41 # Average gap between requests +system.physmem.pageHitRate 87.81 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 258098400 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 140827500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1587963000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 507047040 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 128202890400 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 65554579665 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1120197596250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1316449002255 # Total energy per rank (pJ) +system.physmem_0.averagePower 670.687203 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1863305388500 # Time in different power states +system.physmem_0.memoryStateTime::REF 65543400000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 33987247750 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 265945680 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 145109250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1596465000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 533543760 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 128202890400 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 65970100260 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1119833096250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1316547150600 # Total energy per rank (pJ) +system.physmem_1.averagePower 670.737211 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1862702158750 # Time in different power states +system.physmem_1.memoryStateTime::REF 65543400000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 34590463750 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 7534386 # DTB read hits +system.cpu0.dtb.read_hits 7535038 # DTB read hits system.cpu0.dtb.read_misses 7765 # DTB read misses system.cpu0.dtb.read_acv 210 # DTB read access violations system.cpu0.dtb.read_accesses 524069 # DTB read accesses -system.cpu0.dtb.write_hits 5126601 # DTB write hits +system.cpu0.dtb.write_hits 5127057 # DTB write hits system.cpu0.dtb.write_misses 910 # DTB write misses system.cpu0.dtb.write_acv 133 # DTB write access violations system.cpu0.dtb.write_accesses 202595 # DTB write accesses -system.cpu0.dtb.data_hits 12660987 # DTB hits +system.cpu0.dtb.data_hits 12662095 # DTB hits system.cpu0.dtb.data_misses 8675 # DTB misses system.cpu0.dtb.data_acv 343 # DTB access violations system.cpu0.dtb.data_accesses 726664 # DTB accesses @@ -344,32 +349,32 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 3925689160 # number of cpu cycles simulated +system.cpu0.numCycles 3925685712 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 47974635 # Number of instructions committed -system.cpu0.committedOps 47974635 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 44501266 # Number of integer alu accesses +system.cpu0.committedInsts 47981838 # Number of instructions committed +system.cpu0.committedOps 47981838 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 44508329 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 212945 # Number of float alu accesses -system.cpu0.num_func_calls 1202793 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 5632199 # number of instructions that are conditional controls -system.cpu0.num_int_insts 44501266 # number of integer instructions +system.cpu0.num_func_calls 1202945 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 5633344 # number of instructions that are conditional controls +system.cpu0.num_int_insts 44508329 # number of integer instructions system.cpu0.num_fp_insts 212945 # number of float instructions -system.cpu0.num_int_register_reads 61193579 # number of times the integer registers were read -system.cpu0.num_int_register_writes 33138119 # number of times the integer registers were written +system.cpu0.num_int_register_reads 61205329 # number of times the integer registers were read +system.cpu0.num_int_register_writes 33143507 # number of times the integer registers were written system.cpu0.num_fp_register_reads 104073 # number of times the floating registers were read system.cpu0.num_fp_register_writes 105864 # number of times the floating registers were written -system.cpu0.num_mem_refs 12702031 # number of memory refs -system.cpu0.num_load_insts 7562183 # Number of load instructions -system.cpu0.num_store_insts 5139848 # Number of store instructions -system.cpu0.num_idle_cycles 3702096779.998114 # Number of idle cycles -system.cpu0.num_busy_cycles 223592380.001886 # Number of busy cycles +system.cpu0.num_mem_refs 12703139 # number of memory refs +system.cpu0.num_load_insts 7562835 # Number of load instructions +system.cpu0.num_store_insts 5140304 # Number of store instructions +system.cpu0.num_idle_cycles 3702094605.998114 # Number of idle cycles +system.cpu0.num_busy_cycles 223591106.001886 # Number of busy cycles system.cpu0.not_idle_fraction 0.056956 # Percentage of non-idle cycles system.cpu0.idle_fraction 0.943044 # Percentage of idle cycles -system.cpu0.Branches 7223323 # Number of branches fetched -system.cpu0.op_class::No_OpClass 2734296 5.70% 5.70% # Class of executed instruction -system.cpu0.op_class::IntAlu 31541688 65.73% 71.43% # Class of executed instruction -system.cpu0.op_class::IntMult 52334 0.11% 71.54% # Class of executed instruction +system.cpu0.Branches 7224625 # Number of branches fetched +system.cpu0.op_class::No_OpClass 2734428 5.70% 5.70% # Class of executed instruction +system.cpu0.op_class::IntAlu 31547561 65.74% 71.43% # Class of executed instruction +system.cpu0.op_class::IntMult 52422 0.11% 71.54% # Class of executed instruction system.cpu0.op_class::IntDiv 0 0.00% 71.54% # Class of executed instruction system.cpu0.op_class::FloatAdd 26783 0.06% 71.60% # Class of executed instruction system.cpu0.op_class::FloatCmp 0 0.00% 71.60% # Class of executed instruction @@ -397,11 +402,11 @@ system.cpu0.op_class::SimdFloatMisc 0 0.00% 71.60% # Cl system.cpu0.op_class::SimdFloatMult 0 0.00% 71.60% # Class of executed instruction system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 71.60% # Class of executed instruction system.cpu0.op_class::SimdFloatSqrt 0 0.00% 71.60% # Class of executed instruction -system.cpu0.op_class::MemRead 7738218 16.13% 87.73% # Class of executed instruction -system.cpu0.op_class::MemWrite 5145965 10.72% 98.45% # Class of executed instruction +system.cpu0.op_class::MemRead 7738872 16.13% 87.73% # Class of executed instruction +system.cpu0.op_class::MemWrite 5146421 10.72% 98.45% # Class of executed instruction system.cpu0.op_class::IprAccess 742486 1.55% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 47983653 # Class of executed instruction +system.cpu0.op_class::total 47990856 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 6794 # number of quiesce instructions executed system.cpu0.kern.inst.hwrei 165589 # number of hwrei instructions executed @@ -417,12 +422,12 @@ system.cpu0.kern.ipl_good::22 1976 1.72% 50.92% # nu system.cpu0.kern.ipl_good::30 424 0.37% 51.29% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::31 55969 48.71% 100.00% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::total 114892 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1903342573000 96.97% 96.97% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 94358500 0.00% 96.97% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 767882500 0.04% 97.01% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 314406500 0.02% 97.03% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 58324587500 2.97% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1962843808000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::0 1903333022000 96.97% 96.97% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 94388000 0.00% 96.97% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 768238500 0.04% 97.01% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 314332500 0.02% 97.03% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 58332103000 2.97% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1962842084000 # number of cycles we spent at this ipl system.cpu0.kern.ipl_used::0 0.990637 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl @@ -487,98 +492,98 @@ system.cpu0.kern.mode_switch_good::kernel 0.195209 # f system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::total 0.326733 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1959059969000 99.81% 99.81% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 3783834500 0.19% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::kernel 1959061538500 99.81% 99.81% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 3780541000 0.19% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode system.cpu0.kern.swap_context 3098 # number of times the context was actually changed -system.cpu0.dcache.tags.replacements 1190018 # number of replacements -system.cpu0.dcache.tags.tagsinuse 505.199068 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 11465472 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1190530 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 9.630561 # Average number of references to valid blocks. +system.cpu0.dcache.tags.replacements 1190069 # number of replacements +system.cpu0.dcache.tags.tagsinuse 505.197532 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 11466522 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1190581 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 9.631031 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 108210250 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.199068 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.986717 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.986717 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.197532 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.986714 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.986714 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 117 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 328 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 120 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 325 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 51888213 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 51888213 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 6450398 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6450398 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 4712072 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 4712072 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 140773 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 140773 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 148356 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 148356 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 11162470 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 11162470 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 11162470 # number of overall hits -system.cpu0.dcache.overall_hits::total 11162470 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 942246 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 942246 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 257610 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 257610 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13707 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 13707 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 5575 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 5575 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1199856 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1199856 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1199856 # number of overall misses -system.cpu0.dcache.overall_misses::total 1199856 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 27226306250 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 27226306250 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 10348541688 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 10348541688 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 149709000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 149709000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 42660894 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 42660894 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 37574847938 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 37574847938 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 37574847938 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 37574847938 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 7392644 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 7392644 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 4969682 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 4969682 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 154480 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 154480 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 153931 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 153931 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 12362326 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 12362326 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 12362326 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 12362326 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.127457 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.127457 # miss rate for ReadReq accesses +system.cpu0.dcache.tags.tag_accesses 51892703 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 51892703 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 6451021 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6451021 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 4712504 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 4712504 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 140772 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 140772 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 148353 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 148353 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 11163525 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 11163525 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 11163525 # number of overall hits +system.cpu0.dcache.overall_hits::total 11163525 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 942274 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 942274 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 257633 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 257633 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13709 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 13709 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 5579 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 5579 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1199907 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1199907 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1199907 # number of overall misses +system.cpu0.dcache.overall_misses::total 1199907 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 27224956000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 27224956000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 10342084186 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 10342084186 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 150000000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 150000000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 42703895 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 42703895 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 37567040186 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 37567040186 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 37567040186 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 37567040186 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 7393295 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 7393295 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 4970137 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 4970137 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 154481 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 154481 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 153932 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 153932 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 12363432 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 12363432 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 12363432 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 12363432 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.127450 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.127450 # miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.051836 # miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_miss_rate::total 0.051836 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.088730 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.088730 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.036218 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.036218 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.097057 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.097057 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.097057 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.097057 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 28895.114705 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 28895.114705 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 40171.350833 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 40171.350833 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10922.083607 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10922.083607 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7652.178296 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7652.178296 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 31316.131217 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 31316.131217 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 31316.131217 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 31316.131217 # average overall miss latency +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.088742 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.088742 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.036243 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.036243 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.097053 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.097053 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.097053 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.097053 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 28892.823107 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 28892.823107 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 40142.699833 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 40142.699833 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10941.717120 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10941.717120 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7654.399534 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7654.399534 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 31308.293214 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 31308.293214 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 31308.293214 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 31308.293214 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -587,62 +592,62 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 685854 # number of writebacks -system.cpu0.dcache.writebacks::total 685854 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 942246 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 942246 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 257610 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 257610 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 13707 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 13707 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 5575 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 5575 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 1199856 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 1199856 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 1199856 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 1199856 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 25216322750 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 25216322750 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 9780175312 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 9780175312 # number of WriteReq MSHR miss cycles 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cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1461499500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2267126500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2267126500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3728626000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3728626000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.127457 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.127457 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.writebacks::writebacks 685914 # number of writebacks +system.cpu0.dcache.writebacks::total 685914 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 942274 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 942274 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 257633 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 257633 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 13709 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 13709 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 5579 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 5579 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 1199907 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 1199907 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 1199907 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 1199907 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 25214933000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 25214933000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 9773693814 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 9773693814 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 122568000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 122568000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 31544105 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 31544105 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 34988626814 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 34988626814 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 34988626814 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 34988626814 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1461501000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1461501000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2267119000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2267119000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3728620000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3728620000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.127450 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.127450 # mshr miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051836 # mshr miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051836 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.088730 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.088730 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.036218 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.036218 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.097057 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.097057 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.097057 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.097057 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26761.931332 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26761.931332 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 37965.045270 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 37965.045270 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8921.062231 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8921.062231 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5651.857578 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5651.857578 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 29167.248455 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 29167.248455 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 29167.248455 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 29167.248455 # average overall mshr miss latency +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.088742 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.088742 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.036243 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.036243 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.097053 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.097053 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.097053 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.097053 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26759.661203 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26759.661203 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 37936.498096 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 37936.498096 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8940.695893 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8940.695893 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5654.078688 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5654.078688 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 29159.448869 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 29159.448869 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 29159.448869 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 29159.448869 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -650,13 +655,13 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 699671 # number of replacements -system.cpu0.icache.tags.tagsinuse 508.391653 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 47283349 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 700182 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 67.530084 # Average number of references to valid blocks. +system.cpu0.icache.tags.replacements 699791 # number of replacements +system.cpu0.icache.tags.tagsinuse 508.391652 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 47290432 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 700302 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 67.528626 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 40276505250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 508.391653 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu0.inst 508.391652 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.992952 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.992952 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id @@ -665,44 +670,44 @@ system.cpu0.icache.tags.age_task_id_blocks_1024::1 1 system.cpu0.icache.tags.age_task_id_blocks_1024::2 436 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::3 9 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 48683959 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 48683959 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 47283349 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 47283349 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 47283349 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 47283349 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 47283349 # number of overall hits -system.cpu0.icache.overall_hits::total 47283349 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 700305 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 700305 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 700305 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 700305 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 700305 # number of overall misses -system.cpu0.icache.overall_misses::total 700305 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 9967517496 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 9967517496 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 9967517496 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 9967517496 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 9967517496 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 9967517496 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 47983654 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 47983654 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 47983654 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 47983654 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 47983654 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 47983654 # number of overall (read+write) accesses +system.cpu0.icache.tags.tag_accesses 48691282 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 48691282 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 47290432 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 47290432 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 47290432 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 47290432 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 47290432 # number of overall hits +system.cpu0.icache.overall_hits::total 47290432 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 700425 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 700425 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 700425 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 700425 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 700425 # number of overall misses +system.cpu0.icache.overall_misses::total 700425 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 9965953746 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 9965953746 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 9965953746 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 9965953746 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 9965953746 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 9965953746 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 47990857 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 47990857 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 47990857 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 47990857 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 47990857 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 47990857 # number of overall (read+write) accesses system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014595 # miss rate for ReadReq accesses system.cpu0.icache.ReadReq_miss_rate::total 0.014595 # miss rate for ReadReq accesses system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014595 # miss rate for demand accesses system.cpu0.icache.demand_miss_rate::total 0.014595 # miss rate for demand accesses system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014595 # miss rate for overall accesses system.cpu0.icache.overall_miss_rate::total 0.014595 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14233.109140 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 14233.109140 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14233.109140 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 14233.109140 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14233.109140 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 14233.109140 # average overall miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14228.438085 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 14228.438085 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14228.438085 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 14228.438085 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14228.438085 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 14228.438085 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -711,51 +716,51 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 700305 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 700305 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 700305 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 700305 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 700305 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 700305 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 8561918504 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 8561918504 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 8561918504 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 8561918504 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 8561918504 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 8561918504 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 700425 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 700425 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 700425 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 700425 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 700425 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 700425 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 8560109254 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 8560109254 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 8560109254 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 8560109254 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 8560109254 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 8560109254 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014595 # mshr miss rate for ReadReq accesses system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014595 # mshr miss rate for ReadReq accesses system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014595 # mshr miss rate for demand accesses system.cpu0.icache.demand_mshr_miss_rate::total 0.014595 # mshr miss rate for demand accesses system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014595 # mshr miss rate for overall accesses system.cpu0.icache.overall_mshr_miss_rate::total 0.014595 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12225.985112 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12225.985112 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12225.985112 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12225.985112 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12225.985112 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12225.985112 # average overall mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12221.307426 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12221.307426 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12221.307426 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12221.307426 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12221.307426 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12221.307426 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 2382379 # DTB read hits +system.cpu1.dtb.read_hits 2381610 # DTB read hits system.cpu1.dtb.read_misses 2620 # DTB read misses system.cpu1.dtb.read_acv 0 # DTB read access violations system.cpu1.dtb.read_accesses 205337 # DTB read accesses -system.cpu1.dtb.write_hits 1702197 # DTB write hits +system.cpu1.dtb.write_hits 1701782 # DTB write hits system.cpu1.dtb.write_misses 235 # DTB write misses system.cpu1.dtb.write_acv 24 # DTB write access violations system.cpu1.dtb.write_accesses 89739 # DTB write accesses -system.cpu1.dtb.data_hits 4084576 # DTB hits +system.cpu1.dtb.data_hits 4083392 # DTB hits system.cpu1.dtb.data_misses 2855 # DTB misses system.cpu1.dtb.data_acv 24 # DTB access violations system.cpu1.dtb.data_accesses 295076 # DTB accesses -system.cpu1.itb.fetch_hits 1808740 # ITB hits +system.cpu1.itb.fetch_hits 1808769 # ITB hits system.cpu1.itb.fetch_misses 1064 # ITB misses system.cpu1.itb.fetch_acv 0 # ITB acv -system.cpu1.itb.fetch_accesses 1809804 # ITB accesses +system.cpu1.itb.fetch_accesses 1809833 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -768,87 +773,87 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 3923834014 # number of cpu cycles simulated +system.cpu1.numCycles 3923834021 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 12951032 # Number of instructions committed -system.cpu1.committedOps 12951032 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 11936898 # Number of integer alu accesses +system.cpu1.committedInsts 12938544 # Number of instructions committed +system.cpu1.committedOps 12938544 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 11924615 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 171199 # Number of float alu accesses -system.cpu1.num_func_calls 411532 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 1284277 # number of instructions that are conditional controls -system.cpu1.num_int_insts 11936898 # number of integer instructions +system.cpu1.num_func_calls 411382 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 1282019 # number of instructions that are conditional controls +system.cpu1.num_int_insts 11924615 # number of integer instructions system.cpu1.num_fp_insts 171199 # number of float instructions -system.cpu1.num_int_register_reads 16412569 # number of times the integer registers were read -system.cpu1.num_int_register_writes 8783541 # number of times the integer registers were written +system.cpu1.num_int_register_reads 16391744 # number of times the integer registers were read +system.cpu1.num_int_register_writes 8774012 # number of times the integer registers were written system.cpu1.num_fp_register_reads 88996 # number of times the floating registers were read system.cpu1.num_fp_register_writes 90942 # number of times the floating registers were written -system.cpu1.num_mem_refs 4107226 # number of memory refs -system.cpu1.num_load_insts 2395961 # Number of load instructions -system.cpu1.num_store_insts 1711265 # Number of store instructions -system.cpu1.num_idle_cycles 3874307298.691787 # Number of idle cycles -system.cpu1.num_busy_cycles 49526715.308213 # Number of busy cycles -system.cpu1.not_idle_fraction 0.012622 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.987378 # Percentage of idle cycles -system.cpu1.Branches 1849703 # Number of branches fetched -system.cpu1.op_class::No_OpClass 699491 5.40% 5.40% # Class of executed instruction -system.cpu1.op_class::IntAlu 7680347 59.29% 64.69% # Class of executed instruction -system.cpu1.op_class::IntMult 22457 0.17% 64.86% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 64.86% # Class of executed instruction -system.cpu1.op_class::FloatAdd 13113 0.10% 64.96% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 64.96% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 64.96% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 64.96% # Class of executed instruction -system.cpu1.op_class::FloatDiv 1759 0.01% 64.98% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 64.98% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 64.98% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 64.98% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 64.98% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 64.98% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 64.98% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 64.98% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 64.98% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 64.98% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 64.98% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 64.98% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 64.98% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 64.98% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 64.98% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 64.98% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 64.98% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 64.98% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 0 0.00% 64.98% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 64.98% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 64.98% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 64.98% # Class of executed instruction -system.cpu1.op_class::MemRead 2467292 19.05% 84.02% # Class of executed instruction -system.cpu1.op_class::MemWrite 1712246 13.22% 97.24% # Class of executed instruction -system.cpu1.op_class::IprAccess 357206 2.76% 100.00% # Class of executed instruction +system.cpu1.num_mem_refs 4106042 # number of memory refs +system.cpu1.num_load_insts 2395192 # Number of load instructions +system.cpu1.num_store_insts 1710850 # Number of store instructions +system.cpu1.num_idle_cycles 3874343491.006502 # Number of idle cycles +system.cpu1.num_busy_cycles 49490529.993498 # Number of busy cycles +system.cpu1.not_idle_fraction 0.012613 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.987387 # Percentage of idle cycles +system.cpu1.Branches 1847277 # Number of branches fetched +system.cpu1.op_class::No_OpClass 699299 5.40% 5.40% # Class of executed instruction +system.cpu1.op_class::IntAlu 7669413 59.26% 64.67% # Class of executed instruction +system.cpu1.op_class::IntMult 22263 0.17% 64.84% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 64.84% # Class of executed instruction +system.cpu1.op_class::FloatAdd 13113 0.10% 64.94% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 64.94% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 64.94% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 64.94% # Class of executed instruction +system.cpu1.op_class::FloatDiv 1759 0.01% 64.95% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 64.95% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 64.95% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 64.95% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 64.95% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 64.95% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 64.95% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 64.95% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 64.95% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 64.95% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 64.95% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 64.95% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 64.95% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 64.95% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 64.95% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 64.95% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 64.95% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 64.95% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 0 0.00% 64.95% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 64.95% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 64.95% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 64.95% # Class of executed instruction +system.cpu1.op_class::MemRead 2466523 19.06% 84.01% # Class of executed instruction +system.cpu1.op_class::MemWrite 1711831 13.23% 97.24% # Class of executed instruction +system.cpu1.op_class::IprAccess 357222 2.76% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 12953911 # Class of executed instruction +system.cpu1.op_class::total 12941423 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2765 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 77892 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 26462 38.26% 38.26% # number of times we switched to this ipl +system.cpu1.kern.inst.quiesce 2766 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 77895 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 26463 38.26% 38.26% # number of times we switched to this ipl system.cpu1.kern.ipl_count::22 1970 2.85% 41.11% # number of times we switched to this ipl system.cpu1.kern.ipl_count::30 512 0.74% 41.85% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 40213 58.15% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 69157 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 25618 48.15% 48.15% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_count::31 40215 58.15% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 69160 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 25619 48.15% 48.15% # number of times we switched to this ipl from a different ipl system.cpu1.kern.ipl_good::22 1970 3.70% 51.85% # number of times we switched to this ipl from a different ipl system.cpu1.kern.ipl_good::30 512 0.96% 52.81% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 25106 47.19% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 53206 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1910435586500 97.38% 97.38% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 701157000 0.04% 97.41% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 358940000 0.02% 97.43% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 50421293500 2.57% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1961916977000 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.968105 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_good::31 25107 47.19% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 53208 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1910451046000 97.38% 97.38% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 701160000 0.04% 97.41% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 358891000 0.02% 97.43% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 50405883500 2.57% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1961916980500 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.968106 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.624325 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.769351 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::31 0.624319 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.769346 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.syscall::3 10 10.87% 10.87% # number of syscalls executed system.cpu1.kern.syscall::6 9 9.78% 20.65% # number of syscalls executed system.cpu1.kern.syscall::15 1 1.09% 21.74% # number of syscalls executed @@ -870,7 +875,7 @@ system.cpu1.kern.callpal::wrfen 1 0.00% 0.60% # nu system.cpu1.kern.callpal::swpctx 1967 2.75% 3.35% # number of callpals executed system.cpu1.kern.callpal::tbi 3 0.00% 3.35% # number of callpals executed system.cpu1.kern.callpal::wrent 7 0.01% 3.36% # number of callpals executed -system.cpu1.kern.callpal::swpipl 62982 88.13% 91.49% # number of callpals executed +system.cpu1.kern.callpal::swpipl 62985 88.13% 91.49% # number of callpals executed system.cpu1.kern.callpal::rdps 2216 3.10% 94.59% # number of callpals executed system.cpu1.kern.callpal::wrkgp 1 0.00% 94.60% # number of callpals executed system.cpu1.kern.callpal::wrusp 3 0.00% 94.60% # number of callpals executed @@ -879,108 +884,108 @@ system.cpu1.kern.callpal::rti 3692 5.17% 99.77% # nu system.cpu1.kern.callpal::callsys 121 0.17% 99.94% # number of callpals executed system.cpu1.kern.callpal::imb 42 0.06% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 71465 # number of callpals executed +system.cpu1.kern.callpal::total 71468 # number of callpals executed system.cpu1.kern.mode_switch::kernel 1923 # number of protection mode switches -system.cpu1.kern.mode_switch::user 367 # number of protection mode switches +system.cpu1.kern.mode_switch::user 368 # number of protection mode switches system.cpu1.kern.mode_switch::idle 2902 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 803 -system.cpu1.kern.mode_good::user 367 +system.cpu1.kern.mode_good::kernel 804 +system.cpu1.kern.mode_good::user 368 system.cpu1.kern.mode_good::idle 436 -system.cpu1.kern.mode_switch_good::kernel 0.417577 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::kernel 0.418097 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::idle 0.150241 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.309322 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 17997631500 0.92% 0.92% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 1494992000 0.08% 0.99% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1941547962000 99.01% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.mode_switch_good::total 0.309648 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 17982324500 0.92% 0.92% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 1495094500 0.08% 0.99% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1941563117500 99.01% 100.00% # number of ticks spent at the given mode system.cpu1.kern.swap_context 1968 # number of times the context was actually changed -system.cpu1.dcache.tags.replacements 157269 # number of replacements -system.cpu1.dcache.tags.tagsinuse 486.065602 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 3912422 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 157596 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 24.825643 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 1048852145500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 486.065602 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.949347 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.949347 # Average percentage of cache occupancy +system.cpu1.dcache.tags.replacements 157282 # number of replacements +system.cpu1.dcache.tags.tagsinuse 486.069018 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 3911225 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 157609 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 24.816000 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 1048852201500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 486.069018 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.949354 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.949354 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_task_id_blocks::1024 327 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::2 32 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::3 295 # Occupied blocks per task id system.cpu1.dcache.tags.occ_task_id_percent::1024 0.638672 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 16561703 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 16561703 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 2221454 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 2221454 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 1590675 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 1590675 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 47775 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 47775 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 50240 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 50240 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 3812129 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 3812129 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 3812129 # number of overall hits -system.cpu1.dcache.overall_hits::total 3812129 # number of overall hits +system.cpu1.dcache.tags.tag_accesses 16556980 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 16556980 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 2220683 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 2220683 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 1590246 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 1590246 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 47776 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 47776 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 50237 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 50237 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 3810929 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 3810929 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 3810929 # number of overall hits +system.cpu1.dcache.overall_hits::total 3810929 # number of overall hits system.cpu1.dcache.ReadReq_misses::cpu1.data 115097 # number of ReadReq misses system.cpu1.dcache.ReadReq_misses::total 115097 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 57126 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 57126 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 8902 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 8902 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 5962 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 5962 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 172223 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 172223 # number of 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overall miss latency +system.cpu1.dcache.WriteReq_misses::cpu1.data 57138 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 57138 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 8903 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 8903 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 5967 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 5967 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 172235 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 172235 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 172235 # number of overall misses +system.cpu1.dcache.overall_misses::total 172235 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1388298999 # number of ReadReq miss cycles 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0.106167 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.043241 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.043241 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.043241 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.043241 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12061.991181 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 12061.991181 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18890.673492 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 18890.673492 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9051.274851 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9051.274851 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7346.307525 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7346.307525 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14327.368427 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 14327.368427 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14327.368427 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 14327.368427 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -989,62 +994,62 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 107940 # number of writebacks -system.cpu1.dcache.writebacks::total 107940 # number of writebacks +system.cpu1.dcache.writebacks::writebacks 107942 # number of writebacks +system.cpu1.dcache.writebacks::total 107942 # number of writebacks system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 115097 # number of ReadReq MSHR misses system.cpu1.dcache.ReadReq_mshr_misses::total 115097 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 57126 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 57126 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 8902 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 8902 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 5962 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 5962 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 172223 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 172223 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 172223 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 172223 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1159712501 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1159712501 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 962952701 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 962952701 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 62788000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 62788000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 31865584 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 31865584 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2122665202 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 2122665202 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2122665202 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 2122665202 # number of overall MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 57138 # number of WriteReq MSHR misses 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accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.049259 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.034668 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.034668 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.157065 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.157065 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.106082 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.106082 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.043225 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.043225 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.043225 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.043225 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10075.957679 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10075.957679 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16856.644978 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16856.644978 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7053.246461 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7053.246461 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5344.780946 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5344.780946 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12325.097124 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12325.097124 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 12325.097124 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12325.097124 # average overall mshr miss latency +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 726754500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 726754500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 749201000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 749201000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.049276 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.049276 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.034684 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.034684 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.157078 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.157078 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.106167 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.106167 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.043241 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.043241 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.043241 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.043241 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10061.200561 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10061.200561 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16845.789107 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16845.789107 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7051.274851 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7051.274851 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5346.000168 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5346.000168 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12311.949946 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12311.949946 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 12311.949946 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12311.949946 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1052,13 +1057,13 @@ system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 318302 # number of replacements -system.cpu1.icache.tags.tagsinuse 446.541764 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 12635057 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 318814 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 39.631437 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 1956986830500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 446.541764 # Average occupied blocks per requestor +system.cpu1.icache.tags.replacements 318148 # number of replacements +system.cpu1.icache.tags.tagsinuse 446.541580 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 12622723 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 318660 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 39.611884 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 1956986313500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 446.541580 # Average occupied blocks per requestor system.cpu1.icache.tags.occ_percent::cpu1.inst 0.872152 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_percent::total 0.872152 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id @@ -1066,44 +1071,44 @@ system.cpu1.icache.tags.age_task_id_blocks_1024::2 72 system.cpu1.icache.tags.age_task_id_blocks_1024::3 439 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 13272765 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 13272765 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 12635057 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 12635057 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 12635057 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 12635057 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 12635057 # number of overall hits -system.cpu1.icache.overall_hits::total 12635057 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 318854 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 318854 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 318854 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 318854 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 318854 # number of overall misses -system.cpu1.icache.overall_misses::total 318854 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4204550742 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 4204550742 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 4204550742 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 4204550742 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 4204550742 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 4204550742 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 12953911 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 12953911 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 12953911 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 12953911 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 12953911 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 12953911 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024614 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.024614 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024614 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.024614 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024614 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.024614 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13186.445025 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13186.445025 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13186.445025 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13186.445025 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13186.445025 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13186.445025 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 13260123 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 13260123 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 12622723 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 12622723 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 12622723 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 12622723 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 12622723 # number of overall hits +system.cpu1.icache.overall_hits::total 12622723 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 318700 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 318700 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 318700 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 318700 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 318700 # number of overall misses +system.cpu1.icache.overall_misses::total 318700 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4202225742 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 4202225742 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 4202225742 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 4202225742 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 4202225742 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 4202225742 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 12941423 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 12941423 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 12941423 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 12941423 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 12941423 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 12941423 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024626 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.024626 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024626 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.024626 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024626 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.024626 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13185.521625 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13185.521625 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13185.521625 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13185.521625 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13185.521625 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13185.521625 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1112,30 +1117,30 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 318854 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 318854 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 318854 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 318854 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 318854 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 318854 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3566590258 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 3566590258 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3566590258 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 3566590258 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3566590258 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 3566590258 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024614 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024614 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024614 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.024614 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024614 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.024614 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11185.653177 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11185.653177 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11185.653177 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11185.653177 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11185.653177 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11185.653177 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 318700 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 318700 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 318700 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 318700 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 318700 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 318700 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3564575258 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 3564575258 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3564575258 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 3564575258 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3564575258 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 3564575258 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024626 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024626 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024626 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.024626 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024626 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.024626 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11184.735670 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11184.735670 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11184.735670 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11184.735670 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11184.735670 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11184.735670 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -1208,7 +1213,7 @@ system.iobus.reqLayer27.occupancy 76000 # La system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 406206788 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 406213784 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) @@ -1217,14 +1222,14 @@ system.iobus.respLayer0.utilization 0.0 # La system.iobus.respLayer1.occupancy 42016500 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 41696 # number of replacements -system.iocache.tags.tagsinuse 0.577792 # Cycle average of tags in use +system.iocache.tags.tagsinuse 0.577776 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41712 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1755504938000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 0.577792 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.036112 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.036112 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1755504098000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 0.577776 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.036111 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.036111 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -1240,8 +1245,8 @@ system.iocache.overall_misses::tsunami.ide 176 # system.iocache.overall_misses::total 176 # number of overall misses system.iocache.ReadReq_miss_latency::tsunami.ide 21474383 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 21474383 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide 13634244905 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 13634244905 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide 13634467901 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 13634467901 # number of WriteInvalidateReq miss cycles system.iocache.demand_miss_latency::tsunami.ide 21474383 # number of demand (read+write) miss cycles system.iocache.demand_miss_latency::total 21474383 # number of demand (read+write) miss cycles system.iocache.overall_miss_latency::tsunami.ide 21474383 # number of overall miss cycles @@ -1264,17 +1269,17 @@ system.iocache.overall_miss_rate::tsunami.ide 1 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122013.539773 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total 122013.539773 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 328124.877383 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 328124.877383 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 328130.244056 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 328130.244056 # average WriteInvalidateReq miss latency system.iocache.demand_avg_miss_latency::tsunami.ide 122013.539773 # average overall miss latency system.iocache.demand_avg_miss_latency::total 122013.539773 # average overall miss latency system.iocache.overall_avg_miss_latency::tsunami.ide 122013.539773 # average overall miss latency system.iocache.overall_avg_miss_latency::total 122013.539773 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 206283 # number of cycles access was blocked +system.iocache.blocked_cycles::no_mshrs 206274 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 23550 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 23554 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8.759363 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 8.757493 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -1290,8 +1295,8 @@ system.iocache.overall_mshr_misses::tsunami.ide 176 system.iocache.overall_mshr_misses::total 176 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12321383 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::total 12321383 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 11473540905 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 11473540905 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 11473763901 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 11473763901 # number of WriteInvalidateReq MSHR miss cycles system.iocache.demand_mshr_miss_latency::tsunami.ide 12321383 # number of demand (read+write) MSHR miss cycles system.iocache.demand_mshr_miss_latency::total 12321383 # number of demand (read+write) MSHR miss cycles system.iocache.overall_mshr_miss_latency::tsunami.ide 12321383 # number of overall MSHR miss cycles @@ -1306,187 +1311,187 @@ system.iocache.overall_mshr_miss_rate::tsunami.ide 1 system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70007.857955 # average ReadReq mshr miss latency system.iocache.ReadReq_avg_mshr_miss_latency::total 70007.857955 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 276124.877383 # average WriteInvalidateReq mshr miss latency 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+system.l2c.WriteReq_mshr_uncacheable_latency::total 2824911500 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3507297000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 707989500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 4215286500 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.018365 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.288975 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.002043 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.002777 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::total 0.138232 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.942057 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.765820 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.867130 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.954109 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.975506 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.964819 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.475999 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.119678 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.417896 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.018367 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.328016 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.002045 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.039472 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.173317 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.018367 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.328016 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.002045 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.039472 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.173317 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 60793.986161 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 52556.207467 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 60230.828221 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 58242.320819 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 52950.882923 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10053.381548 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10008.588533 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10036.562896 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10035.675615 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10015.192140 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10025.309392 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 56475.322591 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 61281.194151 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 56699.748311 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 60793.986161 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 53743.165348 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 60230.828221 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 61134.555501 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 54084.877339 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 60793.986161 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 53743.165348 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 60230.828221 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 61134.555501 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 54084.877339 # average overall mshr miss latency +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.942939 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.766781 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.867973 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.954158 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.975532 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.964856 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.475985 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.119692 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.417881 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.018365 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.328008 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.002043 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.039486 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.173319 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.018365 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.328008 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.002043 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.039486 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.173319 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 60538.871181 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 52550.828390 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 59734.254992 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 59817.406143 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 52934.752136 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10053.230223 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10008.575758 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10036.442405 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10037.871508 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10015.176663 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10026.386313 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 56413.793892 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 61161.826847 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 56635.575673 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 60538.871181 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 53720.845810 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 59734.254992 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 61096.974152 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 54054.286512 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 60538.871181 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 53720.845810 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 59734.254992 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 61096.974152 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 54054.286512 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1621,96 +1626,96 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 292732 # Transaction distribution -system.membus.trans_dist::ReadResp 292732 # Transaction distribution +system.membus.trans_dist::ReadReq 292731 # Transaction distribution +system.membus.trans_dist::ReadResp 292731 # Transaction distribution system.membus.trans_dist::WriteReq 14079 # Transaction distribution system.membus.trans_dist::WriteResp 14079 # Transaction distribution -system.membus.trans_dist::Writeback 121224 # Transaction distribution +system.membus.trans_dist::Writeback 121235 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution -system.membus.trans_dist::UpgradeReq 16421 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 11471 # Transaction distribution -system.membus.trans_dist::UpgradeResp 7051 # Transaction distribution -system.membus.trans_dist::ReadExReq 124094 # Transaction distribution -system.membus.trans_dist::ReadExResp 123249 # Transaction distribution +system.membus.trans_dist::UpgradeReq 16420 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 11480 # Transaction distribution +system.membus.trans_dist::UpgradeResp 7054 # Transaction distribution +system.membus.trans_dist::ReadExReq 124107 # Transaction distribution +system.membus.trans_dist::ReadExResp 123261 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 42552 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 932442 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 974994 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 932487 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 975039 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124815 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 124815 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1099809 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1099854 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 82034 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31235136 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 31317170 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31236544 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 31318578 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 5317568 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 5317568 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 36634738 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 22113 # Total snoops (count) -system.membus.snoop_fanout::samples 600297 # Request fanout histogram +system.membus.pkt_size::total 36636146 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 22119 # Total snoops (count) +system.membus.snoop_fanout::samples 600328 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 600297 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 600328 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 600297 # Request fanout histogram -system.membus.reqLayer0.occupancy 40801500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 600328 # Request fanout histogram +system.membus.reqLayer0.occupancy 40794500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1914880000 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1915022000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 3840416202 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 3840524699 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) system.membus.respLayer2.occupancy 43136500 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.trans_dist::ReadReq 2106484 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2106469 # Transaction distribution +system.toL2Bus.trans_dist::ReadReq 2106481 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2106466 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 14079 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 14079 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 793794 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 793856 # Transaction distribution system.toL2Bus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 16644 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 11537 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 28181 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 298092 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 298092 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1400589 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3132441 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 637707 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 458977 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 5629714 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 44818176 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 119962112 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 20406592 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 16779186 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 201966066 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 99450 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 3260906 # Request fanout histogram +system.toL2Bus.trans_dist::UpgradeReq 16639 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 11546 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 28185 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 298132 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 298132 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1400829 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3132611 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 637399 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 458996 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 5629835 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 44825856 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 119969536 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 20396736 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 16779122 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 201971250 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 99473 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 3261009 # Request fanout histogram system.toL2Bus.snoop_fanout::mean 3.012796 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.112395 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.112394 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 3219178 98.72% 98.72% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 3219281 98.72% 98.72% # Request fanout histogram system.toL2Bus.snoop_fanout::4 41728 1.28% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 3260906 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 4802513358 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 3261009 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 4802800383 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) system.toL2Bus.snoopLayer0.occupancy 724500 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 3153866996 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 3154409746 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 5532423832 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 5532665081 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.3 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 1434969242 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 1434275242 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 787756714 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 787817718 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt index 166d29f48..5c3a9c7d0 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt @@ -1,107 +1,107 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.920428 # Number of seconds simulated -sim_ticks 1920427877000 # Number of ticks simulated -final_tick 1920427877000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.920419 # Number of seconds simulated +sim_ticks 1920418772000 # Number of ticks simulated +final_tick 1920418772000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 694902 # Simulator instruction rate (inst/s) -host_op_rate 694902 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 23785763794 # Simulator tick rate (ticks/s) -host_mem_usage 317148 # Number of bytes of host memory used -host_seconds 80.74 # Real time elapsed on the host -sim_insts 56105324 # Number of instructions simulated -sim_ops 56105324 # Number of ops (including micro ops) simulated +host_inst_rate 1235696 # Simulator instruction rate (inst/s) +host_op_rate 1235696 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 42298287542 # Simulator tick rate (ticks/s) +host_mem_usage 370580 # Number of bytes of host memory used +host_seconds 45.40 # Real time elapsed on the host +sim_insts 56102800 # Number of instructions simulated +sim_ops 56102800 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 850752 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24858304 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 850560 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24857984 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 25710016 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 850752 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 850752 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7404096 # Number of bytes written to this memory -system.physmem.bytes_written::total 7404096 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 13293 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 388411 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 25709504 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 850560 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 850560 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7403648 # Number of bytes written to this memory +system.physmem.bytes_written::total 7403648 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 13290 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 388406 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 401719 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 115689 # Number of write requests responded to by this memory -system.physmem.num_writes::total 115689 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 443001 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 12944149 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::total 401711 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 115682 # Number of write requests responded to by this memory +system.physmem.num_writes::total 115682 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 442903 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 12944043 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 500 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13387650 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 443001 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 443001 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3855441 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3855441 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3855441 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 443001 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 12944149 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 13387447 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 442903 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 442903 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3855226 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3855226 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3855226 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 442903 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 12944043 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 500 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17243091 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 401719 # Number of read requests accepted -system.physmem.writeReqs 157241 # Number of write requests accepted -system.physmem.readBursts 401719 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 157241 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 25703424 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 6592 # Total number of bytes read from write queue -system.physmem.bytesWritten 9932992 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 25710016 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 10063424 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 103 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2011 # Number of DRAM write bursts merged with an existing one +system.physmem.bw_total::total 17242673 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 401711 # Number of read requests accepted +system.physmem.writeReqs 157234 # Number of write requests accepted +system.physmem.readBursts 401711 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 157234 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 25703040 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 6464 # Total number of bytes read from write queue +system.physmem.bytesWritten 9922432 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 25709504 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 10062976 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 101 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 2169 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 130 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 25160 # Per bank write bursts system.physmem.perBankRdBursts::1 25539 # Per bank write bursts system.physmem.perBankRdBursts::2 25602 # Per bank write bursts -system.physmem.perBankRdBursts::3 25522 # Per bank write bursts +system.physmem.perBankRdBursts::3 25523 # Per bank write bursts system.physmem.perBankRdBursts::4 24974 # Per bank write bursts -system.physmem.perBankRdBursts::5 24970 # Per bank write bursts +system.physmem.perBankRdBursts::5 24969 # Per bank write bursts system.physmem.perBankRdBursts::6 24210 # Per bank write bursts -system.physmem.perBankRdBursts::7 24489 # Per bank write bursts +system.physmem.perBankRdBursts::7 24487 # Per bank write bursts system.physmem.perBankRdBursts::8 25140 # Per bank write bursts system.physmem.perBankRdBursts::9 24800 # Per bank write bursts -system.physmem.perBankRdBursts::10 25361 # Per bank write bursts -system.physmem.perBankRdBursts::11 24836 # Per bank write bursts +system.physmem.perBankRdBursts::10 25360 # Per bank write bursts +system.physmem.perBankRdBursts::11 24834 # Per bank write bursts system.physmem.perBankRdBursts::12 24395 # Per bank write bursts system.physmem.perBankRdBursts::13 25368 # Per bank write bursts system.physmem.perBankRdBursts::14 25772 # Per bank write bursts -system.physmem.perBankRdBursts::15 25478 # Per bank write bursts -system.physmem.perBankWrBursts::0 10040 # Per bank write bursts -system.physmem.perBankWrBursts::1 9905 # Per bank write bursts -system.physmem.perBankWrBursts::2 10447 # Per bank write bursts -system.physmem.perBankWrBursts::3 9982 # Per bank write bursts -system.physmem.perBankWrBursts::4 9551 # Per bank write bursts -system.physmem.perBankWrBursts::5 9392 # Per bank write bursts -system.physmem.perBankWrBursts::6 8805 # Per bank write bursts -system.physmem.perBankWrBursts::7 8555 # Per bank write bursts -system.physmem.perBankWrBursts::8 9942 # Per bank write bursts -system.physmem.perBankWrBursts::9 8777 # Per bank write bursts -system.physmem.perBankWrBursts::10 9524 # Per bank write bursts -system.physmem.perBankWrBursts::11 9288 # Per bank write bursts -system.physmem.perBankWrBursts::12 9847 # Per bank write bursts -system.physmem.perBankWrBursts::13 10608 # Per bank write bursts -system.physmem.perBankWrBursts::14 10278 # Per bank write bursts -system.physmem.perBankWrBursts::15 10262 # Per bank write bursts +system.physmem.perBankRdBursts::15 25477 # Per bank write bursts +system.physmem.perBankWrBursts::0 10048 # Per bank write bursts +system.physmem.perBankWrBursts::1 9910 # Per bank write bursts +system.physmem.perBankWrBursts::2 10442 # Per bank write bursts +system.physmem.perBankWrBursts::3 9959 # Per bank write bursts +system.physmem.perBankWrBursts::4 9552 # Per bank write bursts +system.physmem.perBankWrBursts::5 9342 # Per bank write bursts +system.physmem.perBankWrBursts::6 8789 # Per bank write bursts +system.physmem.perBankWrBursts::7 8561 # Per bank write bursts +system.physmem.perBankWrBursts::8 9905 # Per bank write bursts +system.physmem.perBankWrBursts::9 8742 # Per bank write bursts +system.physmem.perBankWrBursts::10 9526 # Per bank write bursts +system.physmem.perBankWrBursts::11 9262 # Per bank write bursts +system.physmem.perBankWrBursts::12 9811 # Per bank write bursts +system.physmem.perBankWrBursts::13 10568 # Per bank write bursts +system.physmem.perBankWrBursts::14 10305 # Per bank write bursts +system.physmem.perBankWrBursts::15 10316 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 1920415956000 # Total gap between requests +system.physmem.totGap 1920406851000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 401719 # Read request sizes (log2) +system.physmem.readPktSize::6 401711 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 157241 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 401602 # What read queue length does an incoming req see +system.physmem.writePktSize::6 157234 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 401596 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see @@ -149,119 +149,118 @@ system.physmem.wrQLenPdf::12 1 # Wh system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::15 2241 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4297 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 7960 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 9080 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 9749 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 10574 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 11119 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 12096 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 11614 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 11639 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 10464 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 9678 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 8171 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7710 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6526 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6096 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5950 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5885 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 334 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 334 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 336 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 315 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 291 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 274 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 265 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 251 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 211 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 210 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 205 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 194 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 177 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 146 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 133 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 123 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 114 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 109 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 95 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 77 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 58 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 42 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 26 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 24 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 4336 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 7978 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 9053 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 9729 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 10585 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 11129 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 12018 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 11559 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 11623 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 10445 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 9597 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 8159 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7669 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6479 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6050 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5940 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5895 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 361 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 368 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 365 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 334 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 315 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 271 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 246 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 254 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 231 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 229 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 216 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 197 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 173 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 155 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 135 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 126 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 118 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 97 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 75 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 61 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 49 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 25 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 66429 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 536.458715 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 326.725513 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 417.454187 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 15065 22.68% 22.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 11458 17.25% 39.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4677 7.04% 46.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3146 4.74% 51.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 3014 4.54% 56.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1853 2.79% 59.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1319 1.99% 61.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1472 2.22% 63.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 24425 36.77% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 66429 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5535 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 72.556098 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2836.858046 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 5532 99.95% 99.95% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 66451 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 536.116417 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 326.833533 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 417.088244 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 15015 22.60% 22.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 11499 17.30% 39.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4712 7.09% 46.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3144 4.73% 51.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 3072 4.62% 56.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1860 2.80% 59.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1297 1.95% 61.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1463 2.20% 63.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 24389 36.70% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 66451 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5539 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 72.502618 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2835.834060 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 5536 99.95% 99.95% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5535 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5535 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 28.040289 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 21.079799 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 34.913440 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 4499 81.28% 81.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 176 3.18% 84.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 297 5.37% 89.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 50 0.90% 90.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 97 1.75% 92.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 48 0.87% 93.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 11 0.20% 93.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 7 0.13% 93.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 21 0.38% 94.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 7 0.13% 94.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 14 0.25% 94.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 6 0.11% 94.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-119 14 0.25% 94.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-127 3 0.05% 94.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 11 0.20% 95.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-143 48 0.87% 95.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-151 16 0.29% 96.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-159 19 0.34% 96.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-167 91 1.64% 98.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 36 0.65% 98.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 6 0.11% 98.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-191 14 0.25% 99.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-199 14 0.25% 99.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-207 5 0.09% 99.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-215 9 0.16% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-223 3 0.05% 99.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-231 5 0.09% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::232-239 1 0.02% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::240-247 3 0.05% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::248-255 2 0.04% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-263 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::264-271 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5535 # Writes before turning the bus around for reads -system.physmem.totQLat 2119831750 # Total ticks spent queuing -system.physmem.totMemAccLat 9650131750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2008080000 # Total ticks spent in databus transfers -system.physmem.avgQLat 5278.26 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5539 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5539 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 27.990251 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 21.086567 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 34.704660 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 4497 81.19% 81.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 178 3.21% 84.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 301 5.43% 89.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 51 0.92% 90.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-55 99 1.79% 92.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-63 47 0.85% 93.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-71 17 0.31% 93.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-79 11 0.20% 93.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-87 12 0.22% 94.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-95 4 0.07% 94.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-103 17 0.31% 94.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-111 7 0.13% 94.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-119 14 0.25% 94.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-127 6 0.11% 94.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-135 9 0.16% 95.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-143 38 0.69% 95.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-151 16 0.29% 96.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-159 19 0.34% 96.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-167 88 1.59% 98.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-175 43 0.78% 98.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-183 11 0.20% 99.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-191 20 0.36% 99.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-199 10 0.18% 99.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-207 3 0.05% 99.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-215 3 0.05% 99.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::216-223 4 0.07% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-231 4 0.07% 99.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::232-239 5 0.09% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-247 3 0.05% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::248-255 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-263 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5539 # Writes before turning the bus around for reads +system.physmem.totQLat 2115529750 # Total ticks spent queuing +system.physmem.totMemAccLat 9645717250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2008050000 # Total ticks spent in databus transfers +system.physmem.avgQLat 5267.62 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 24028.26 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 24017.62 # Average memory access latency per DRAM burst system.physmem.avgRdBW 13.38 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 5.17 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 13.39 # Average system read bandwidth in MiByte/s @@ -271,57 +270,62 @@ system.physmem.busUtil 0.14 # Da system.physmem.busUtilRead 0.10 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.04 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.55 # Average write queue length when enqueuing -system.physmem.readRowHits 359880 # Number of row buffer hits during reads -system.physmem.writeRowHits 130510 # Number of row buffer hits during writes -system.physmem.readRowHitRate 89.61 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 84.08 # Row buffer hit rate for writes -system.physmem.avgGap 3435694.78 # Average gap between requests -system.physmem.pageHitRate 88.07 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 1801057353000 # Time in different power states -system.physmem.memoryStateTime::REF 64127180000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 55239785750 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 245964600 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 256238640 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 134206875 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 139812750 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 1563634800 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 1568970000 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 496866960 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 508848480 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 125432764080 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 125432764080 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 64118860245 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 64485707400 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 1096009968750 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 1095688173000 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 1288002266310 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 1288080514350 # Total energy per rank (pJ) -system.physmem.averagePower::0 670.686297 # Core power per rank (mW) -system.physmem.averagePower::1 670.727042 # Core power per rank (mW) +system.physmem.avgWrQLen 25.84 # Average write queue length when enqueuing +system.physmem.readRowHits 359951 # Number of row buffer hits during reads +system.physmem.writeRowHits 130246 # Number of row buffer hits during writes +system.physmem.readRowHitRate 89.63 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 83.99 # Row buffer hit rate for writes +system.physmem.avgGap 3435770.69 # Average gap between requests +system.physmem.pageHitRate 88.06 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 245601720 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 134008875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1563619200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 496387440 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 125432255520 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 64124070615 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1096000726500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1287996669870 # Total energy per rank (pJ) +system.physmem_0.averagePower 670.686102 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1823056528000 # Time in different power states +system.physmem_0.memoryStateTime::REF 64126920000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 33233084500 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 256767840 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 140101500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1568938800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 508258800 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 125432255520 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 64541926215 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1095634186500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1288082435175 # Total energy per rank (pJ) +system.physmem_1.averagePower 670.730762 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1822448681750 # Time in different power states +system.physmem_1.memoryStateTime::REF 64126920000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 33840930750 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 9053154 # DTB read hits -system.cpu.dtb.read_misses 10325 # DTB read misses +system.cpu.dtb.read_hits 9052701 # DTB read hits +system.cpu.dtb.read_misses 10312 # DTB read misses system.cpu.dtb.read_acv 210 # DTB read access violations -system.cpu.dtb.read_accesses 728854 # DTB read accesses -system.cpu.dtb.write_hits 6349573 # DTB write hits -system.cpu.dtb.write_misses 1142 # DTB write misses +system.cpu.dtb.read_accesses 728817 # DTB read accesses +system.cpu.dtb.write_hits 6349364 # DTB write hits +system.cpu.dtb.write_misses 1140 # DTB write misses system.cpu.dtb.write_acv 157 # DTB write access violations -system.cpu.dtb.write_accesses 291931 # DTB write accesses -system.cpu.dtb.data_hits 15402727 # DTB hits -system.cpu.dtb.data_misses 11467 # DTB misses +system.cpu.dtb.write_accesses 291929 # DTB write accesses +system.cpu.dtb.data_hits 15402065 # DTB hits +system.cpu.dtb.data_misses 11452 # DTB misses system.cpu.dtb.data_acv 367 # DTB access violations -system.cpu.dtb.data_accesses 1020785 # DTB accesses -system.cpu.itb.fetch_hits 4974627 # ITB hits -system.cpu.itb.fetch_misses 5010 # ITB misses +system.cpu.dtb.data_accesses 1020746 # DTB accesses +system.cpu.itb.fetch_hits 4973977 # ITB hits +system.cpu.itb.fetch_misses 4997 # ITB misses system.cpu.itb.fetch_acv 184 # ITB acv -system.cpu.itb.fetch_accesses 4979637 # ITB accesses +system.cpu.itb.fetch_accesses 4978974 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -334,34 +338,34 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 3840855754 # number of cpu cycles simulated +system.cpu.numCycles 3840837544 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 56105324 # Number of instructions committed -system.cpu.committedOps 56105324 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 51980283 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 324527 # Number of float alu accesses -system.cpu.num_func_calls 1481352 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 6461346 # number of instructions that are conditional controls -system.cpu.num_int_insts 51980283 # number of integer instructions -system.cpu.num_fp_insts 324527 # number of float instructions -system.cpu.num_int_register_reads 71211532 # number of times the integer registers were read -system.cpu.num_int_register_writes 38461399 # number of times the integer registers were written -system.cpu.num_fp_register_reads 163675 # number of times the floating registers were read -system.cpu.num_fp_register_writes 166554 # number of times the floating registers were written -system.cpu.num_mem_refs 15455353 # number of memory refs -system.cpu.num_load_insts 9090013 # Number of load instructions -system.cpu.num_store_insts 6365340 # Number of store instructions -system.cpu.num_idle_cycles 3589191785.998131 # Number of idle cycles -system.cpu.num_busy_cycles 251663968.001869 # Number of busy cycles -system.cpu.not_idle_fraction 0.065523 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.934477 # Percentage of idle cycles -system.cpu.Branches 8413247 # Number of branches fetched -system.cpu.op_class::No_OpClass 3197750 5.70% 5.70% # Class of executed instruction -system.cpu.op_class::IntAlu 36174854 64.46% 70.16% # Class of executed instruction -system.cpu.op_class::IntMult 61015 0.11% 70.27% # Class of executed instruction +system.cpu.committedInsts 56102800 # Number of instructions committed +system.cpu.committedOps 56102800 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 51978055 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 324393 # Number of float alu accesses +system.cpu.num_func_calls 1481300 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 6461124 # number of instructions that are conditional controls +system.cpu.num_int_insts 51978055 # number of integer instructions +system.cpu.num_fp_insts 324393 # number of float instructions +system.cpu.num_int_register_reads 71208426 # number of times the integer registers were read +system.cpu.num_int_register_writes 38459690 # number of times the integer registers were written +system.cpu.num_fp_register_reads 163609 # number of times the floating registers were read +system.cpu.num_fp_register_writes 166486 # number of times the floating registers were written +system.cpu.num_mem_refs 15454652 # number of memory refs +system.cpu.num_load_insts 9089529 # Number of load instructions +system.cpu.num_store_insts 6365123 # Number of store instructions +system.cpu.num_idle_cycles 3589204507.998131 # Number of idle cycles +system.cpu.num_busy_cycles 251633036.001869 # Number of busy cycles +system.cpu.not_idle_fraction 0.065515 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.934485 # Percentage of idle cycles +system.cpu.Branches 8412940 # Number of branches fetched +system.cpu.op_class::No_OpClass 3197536 5.70% 5.70% # Class of executed instruction +system.cpu.op_class::IntAlu 36173540 64.46% 70.16% # Class of executed instruction +system.cpu.op_class::IntMult 60992 0.11% 70.27% # Class of executed instruction system.cpu.op_class::IntDiv 0 0.00% 70.27% # Class of executed instruction -system.cpu.op_class::FloatAdd 38089 0.07% 70.34% # Class of executed instruction +system.cpu.op_class::FloatAdd 38085 0.07% 70.34% # Class of executed instruction system.cpu.op_class::FloatCmp 0 0.00% 70.34% # Class of executed instruction system.cpu.op_class::FloatCvt 0 0.00% 70.34% # Class of executed instruction system.cpu.op_class::FloatMult 0 0.00% 70.34% # Class of executed instruction @@ -387,34 +391,34 @@ system.cpu.op_class::SimdFloatMisc 0 0.00% 70.34% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 70.34% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 70.34% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::MemRead 9317103 16.60% 86.95% # Class of executed instruction -system.cpu.op_class::MemWrite 6371414 11.35% 98.30% # Class of executed instruction -system.cpu.op_class::IprAccess 953297 1.70% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 9316603 16.60% 86.95% # Class of executed instruction +system.cpu.op_class::MemWrite 6371197 11.35% 98.30% # Class of executed instruction +system.cpu.op_class::IprAccess 953030 1.70% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 56117158 # Class of executed instruction +system.cpu.op_class::total 56114619 # Class of executed instruction system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6382 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 212003 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74898 40.89% 40.89% # number of times we switched to this ipl +system.cpu.kern.inst.quiesce 6379 # number of quiesce instructions executed +system.cpu.kern.inst.hwrei 211965 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74895 40.89% 40.89% # number of times we switched to this ipl system.cpu.kern.ipl_count::21 131 0.07% 40.96% # number of times we switched to this ipl system.cpu.kern.ipl_count::22 1932 1.05% 42.01% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 106222 57.99% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 183183 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73531 49.31% 49.31% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_count::31 106217 57.99% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 183175 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73528 49.31% 49.31% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::21 131 0.09% 49.40% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::22 1932 1.30% 50.69% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73531 49.31% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 149125 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1858233349500 96.76% 96.76% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 91228000 0.00% 96.77% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 737074000 0.04% 96.80% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 61365491500 3.20% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1920427143000 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981749 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_good::31 73528 49.31% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 149119 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1858230927500 96.76% 96.76% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 91348000 0.00% 96.77% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 737130000 0.04% 96.80% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 61358632500 3.20% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1920418038000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981748 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.692239 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.814077 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.692243 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.814079 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -450,10 +454,10 @@ system.cpu.kern.callpal::cserve 1 0.00% 0.00% # nu system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal::swpctx 4178 2.17% 2.17% # number of callpals executed -system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed +system.cpu.kern.callpal::swpctx 4176 2.16% 2.17% # number of callpals executed +system.cpu.kern.callpal::tbi 54 0.03% 2.19% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed -system.cpu.kern.callpal::swpipl 175962 91.21% 93.41% # number of callpals executed +system.cpu.kern.callpal::swpipl 175954 91.22% 93.41% # number of callpals executed system.cpu.kern.callpal::rdps 6833 3.54% 96.96% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.96% # number of callpals executed @@ -462,26 +466,26 @@ system.cpu.kern.callpal::whami 2 0.00% 96.97% # nu system.cpu.kern.callpal::rti 5157 2.67% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 192910 # number of callpals executed +system.cpu.kern.callpal::total 192900 # number of callpals executed system.cpu.kern.mode_switch::kernel 5901 # number of protection mode switches system.cpu.kern.mode_switch::user 1743 # number of protection mode switches -system.cpu.kern.mode_switch::idle 2100 # number of protection mode switches -system.cpu.kern.mode_good::kernel 1914 +system.cpu.kern.mode_switch::idle 2098 # number of protection mode switches +system.cpu.kern.mode_good::kernel 1913 system.cpu.kern.mode_good::user 1743 -system.cpu.kern.mode_good::idle 171 -system.cpu.kern.mode_switch_good::kernel 0.324352 # fraction of useful protection mode switches +system.cpu.kern.mode_good::idle 170 +system.cpu.kern.mode_switch_good::kernel 0.324182 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.081429 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.392857 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 46106755000 2.40% 2.40% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 5190620000 0.27% 2.67% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1869129766000 97.33% 100.00% # number of ticks spent at the given mode -system.cpu.kern.swap_context 4179 # number of times the context was actually changed -system.cpu.dcache.tags.replacements 1390139 # number of replacements +system.cpu.kern.mode_switch_good::idle 0.081030 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::total 0.392732 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 46109911500 2.40% 2.40% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 5189208000 0.27% 2.67% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1869118916500 97.33% 100.00% # number of ticks spent at the given mode +system.cpu.kern.swap_context 4177 # number of times the context was actually changed +system.cpu.dcache.tags.replacements 1389979 # number of replacements system.cpu.dcache.tags.tagsinuse 511.978885 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 14031130 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1390651 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 10.089613 # Average number of references to valid blocks. +system.cpu.dcache.tags.total_refs 14030604 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1390491 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 10.090395 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 107775250 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::cpu.data 511.978885 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999959 # Average percentage of cache occupancy @@ -491,72 +495,72 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0 187 system.cpu.dcache.tags.age_task_id_blocks_1024::1 257 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 68 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 63077780 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 63077780 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 7803062 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7803062 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 5845783 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 5845783 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 183030 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 183030 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 199238 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 199238 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 13648845 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 13648845 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 13648845 # number of overall hits -system.cpu.dcache.overall_hits::total 13648845 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1069228 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1069228 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 304213 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 304213 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 17228 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 17228 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1373441 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1373441 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1373441 # number of overall misses -system.cpu.dcache.overall_misses::total 1373441 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 29002641750 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 29002641750 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 10915376130 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 10915376130 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 228802500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 228802500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 39918017880 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 39918017880 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 39918017880 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 39918017880 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 8872290 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 8872290 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 6149996 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6149996 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200258 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 200258 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 199238 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 199238 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 15022286 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15022286 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 15022286 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15022286 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120513 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.120513 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049466 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.049466 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086029 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086029 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.091427 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.091427 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.091427 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.091427 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 27124.843111 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 27124.843111 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35880.702435 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 35880.702435 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13280.850940 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13280.850940 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 29064.239294 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 29064.239294 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 29064.239294 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 29064.239294 # average overall miss latency +system.cpu.dcache.tags.tag_accesses 63074876 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 63074876 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 7802731 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7802731 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 5845607 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 5845607 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 183026 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 183026 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 199223 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 199223 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 13648338 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 13648338 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 13648338 # number of overall hits +system.cpu.dcache.overall_hits::total 13648338 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1069103 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1069103 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 304189 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 304189 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 17217 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 17217 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1373292 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1373292 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1373292 # number of overall misses +system.cpu.dcache.overall_misses::total 1373292 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 29000817500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 29000817500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 10906930630 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 10906930630 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 228178000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 228178000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 39907748130 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 39907748130 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 39907748130 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 39907748130 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 8871834 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 8871834 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6149796 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6149796 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200243 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 200243 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 199223 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 199223 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 15021630 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15021630 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15021630 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15021630 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120505 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.120505 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049463 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.049463 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.085981 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.085981 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.091421 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.091421 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.091421 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.091421 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 27126.308223 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 27126.308223 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35855.769374 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 35855.769374 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13253.063832 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13253.063832 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 29059.914519 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 29059.914519 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 29059.914519 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 29059.914519 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -565,54 +569,54 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 834534 # number of writebacks -system.cpu.dcache.writebacks::total 834534 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1069228 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1069228 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304213 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 304213 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17228 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 17228 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1373441 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1373441 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1373441 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1373441 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 26738553250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 26738553250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10254282870 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 10254282870 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 194333500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 194333500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 36992836120 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 36992836120 # number of demand (read+write) MSHR miss cycles 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latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25007.344785 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33707.576172 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33707.576172 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11280.096355 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11280.096355 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26934.419549 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 26934.419549 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26934.419549 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 26934.419549 # average overall mshr miss latency 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percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id @@ -635,44 +639,44 @@ system.cpu.icache.tags.age_task_id_blocks_1024::1 1 system.cpu.icache.tags.age_task_id_blocks_1024::2 438 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 9 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 57045788 # Number of tag accesses -system.cpu.icache.tags.data_accesses 57045788 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 55188530 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 55188530 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 55188530 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 55188530 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 55188530 # number of overall hits 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number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6615159119 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 800925500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 20916723869 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 21717649369 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 800925500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 20916723869 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 21717649369 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1334183000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1334183000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1893600000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1893600000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3227783000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3227783000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014315 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.250318 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.141560 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6607051619 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6607051619 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 802917750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 20907900119 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 21710817869 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 802917750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 20907900119 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 21710817869 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1334182500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1334182500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1893599000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1893599000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3227781500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3227781500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014316 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.250348 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.141588 # mshr miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.764706 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.764706 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.384101 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.384101 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014315 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.279582 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.173372 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014315 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.279582 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.173372 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60251.673813 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 52587.208918 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 52944.379882 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.384118 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.384118 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014316 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.279610 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.173402 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014316 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.279610 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.173402 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60415.180587 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 52584.768604 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 52949.595615 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17693.153846 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17693.153846 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56616.277700 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56616.277700 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60251.673813 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53798.019730 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54011.373880 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60251.673813 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53798.019730 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54011.373880 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56548.825031 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56548.825031 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60415.180587 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53776.016520 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53995.458357 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60415.180587 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53776.016520 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53995.458357 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -885,41 +889,41 @@ system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 2022188 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2022171 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 2021758 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2021741 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 9650 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 9650 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 834534 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 834368 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 17 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 17 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 304196 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 304196 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1857238 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3649188 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 5506426 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 59430976 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142466452 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 201897428 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadExReq 304172 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 304172 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1856650 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3648702 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 5505352 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 59412160 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142445588 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 201857748 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 41901 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 3195557 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.013057 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.113520 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 3194937 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.013060 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.113530 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 3153832 98.69% 98.69% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 3153212 98.69% 98.69% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 41725 1.31% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 3195557 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 2424565000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 3194937 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 2424089000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 234000 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1395517500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1395084250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2186897880 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2186669630 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -992,7 +996,7 @@ system.iobus.reqLayer27.occupancy 76000 # La system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 406189794 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 406198788 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) @@ -1001,14 +1005,14 @@ system.iobus.respLayer0.utilization 0.0 # La system.iobus.respLayer1.occupancy 42010500 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.352352 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.352284 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1753525032000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.352352 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.084522 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.084522 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1753525494000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.352284 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.084518 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.084518 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -1022,14 +1026,14 @@ system.iocache.demand_misses::tsunami.ide 173 # n system.iocache.demand_misses::total 173 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 173 # number of overall misses system.iocache.overall_misses::total 173 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21133383 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21133383 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide 13634918911 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 13634918911 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 21133383 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 21133383 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 21133383 # number of overall miss cycles -system.iocache.overall_miss_latency::total 21133383 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 23338383 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 23338383 # number of ReadReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide 13635239905 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 13635239905 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 23338383 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 23338383 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 23338383 # number of overall miss cycles +system.iocache.overall_miss_latency::total 23338383 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41552 # number of WriteInvalidateReq accesses(hits+misses) @@ -1046,19 +1050,19 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122158.283237 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 122158.283237 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 328141.098166 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 328141.098166 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 122158.283237 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 122158.283237 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 122158.283237 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 122158.283237 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 206323 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 134903.947977 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 134903.947977 # average ReadReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 328148.823282 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 328148.823282 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 134903.947977 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 134903.947977 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 134903.947977 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 134903.947977 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 206255 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 23561 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8.756971 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 8.754085 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -1072,14 +1076,14 @@ system.iocache.demand_mshr_misses::tsunami.ide 173 system.iocache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 173 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12136383 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 12136383 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 11474214911 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 11474214911 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 12136383 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 12136383 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 12136383 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 12136383 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 14341383 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 14341383 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 11474535905 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 11474535905 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 14341383 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 14341383 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 14341383 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 14341383 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteInvalidateReq accesses @@ -1088,55 +1092,55 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 70152.502890 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 276141.098166 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 276141.098166 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 70152.502890 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 70152.502890 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 82898.167630 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 82898.167630 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 276148.823282 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 276148.823282 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 82898.167630 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 82898.167630 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 82898.167630 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 82898.167630 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 292355 # Transaction distribution -system.membus.trans_dist::ReadResp 292355 # Transaction distribution +system.membus.trans_dist::ReadReq 292351 # Transaction distribution +system.membus.trans_dist::ReadResp 292351 # Transaction distribution system.membus.trans_dist::WriteReq 9650 # Transaction distribution system.membus.trans_dist::WriteResp 9650 # Transaction distribution -system.membus.trans_dist::Writeback 115689 # Transaction distribution +system.membus.trans_dist::Writeback 115682 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution system.membus.trans_dist::UpgradeReq 132 # Transaction distribution system.membus.trans_dist::UpgradeResp 132 # Transaction distribution -system.membus.trans_dist::ReadExReq 116723 # Transaction distribution -system.membus.trans_dist::ReadExResp 116723 # Transaction distribution +system.membus.trans_dist::ReadExReq 116719 # Transaction distribution +system.membus.trans_dist::ReadExResp 116719 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33160 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 878118 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 911278 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 878095 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 911255 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124804 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 124804 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1036082 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1036059 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44564 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30456384 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30500948 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30455424 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30499988 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 5317056 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 5317056 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 35818004 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 35817044 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 431 # Total snoops (count) -system.membus.snoop_fanout::samples 559521 # Request fanout histogram +system.membus.snoop_fanout::samples 559506 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 559521 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 559506 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 559521 # Request fanout histogram -system.membus.reqLayer0.occupancy 30373000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 559506 # Request fanout histogram +system.membus.reqLayer0.occupancy 30371500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1824623000 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1824515500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 3751921620 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 3751827620 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) system.membus.respLayer2.occupancy 43109500 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt index a51b2d079..def60114c 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.802895 # Nu sim_ticks 2802895103500 # Number of ticks simulated final_tick 2802895103500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 967895 # Simulator instruction rate (inst/s) -host_op_rate 1179365 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 18476638236 # Simulator tick rate (ticks/s) -host_mem_usage 571628 # Number of bytes of host memory used -host_seconds 151.70 # Real time elapsed on the host +host_inst_rate 834307 # Simulator instruction rate (inst/s) +host_op_rate 1016590 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 15926512431 # Simulator tick rate (ticks/s) +host_mem_usage 572876 # Number of bytes of host memory used +host_seconds 175.99 # Real time elapsed on the host sim_insts 146829031 # Number of instructions simulated sim_ops 178908942 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -93,6 +93,14 @@ system.cf0.dma_write_full_pages 540 # Nu system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -114,6 +122,24 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu0.dtb.walker.walks 7967 # Table walker walks requested +system.cpu0.dtb.walker.walksShort 7967 # Table walker walks initiated with short descriptors +system.cpu0.dtb.walker.walkWaitTime::samples 7967 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 7967 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 7967 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walksPending::samples 6705500 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 6705500 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 6705500 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 5082 77.32% 77.32% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 1491 22.68% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 6573 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 7967 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 7967 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6573 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6573 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 14540 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses system.cpu0.dtb.read_hits 20339962 # DTB read hits @@ -135,6 +161,14 @@ system.cpu0.dtb.inst_accesses 0 # IT system.cpu0.dtb.hits 36731133 # DTB hits system.cpu0.dtb.misses 7967 # DTB misses system.cpu0.dtb.accesses 36739100 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -156,6 +190,24 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu0.itb.walker.walks 3358 # Table walker walks requested +system.cpu0.itb.walker.walksShort 3358 # Table walker walks initiated with short descriptors +system.cpu0.itb.walker.walkWaitTime::samples 3358 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 3358 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 3358 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walksPending::samples 6702500 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 6702500 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 6702500 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 2040 87.11% 87.11% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::1M 302 12.89% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 2342 # Table walker page sizes translated +system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3358 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3358 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2342 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2342 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 5700 # Table walker requests started/completed, data/inst system.cpu0.itb.inst_hits 97440315 # ITB inst hits system.cpu0.itb.inst_misses 3358 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits @@ -371,15 +423,12 @@ system.cpu0.icache.avg_blocked_cycles::no_targets nan system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu0.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu0.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified +system.cpu0.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue +system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped +system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size +system.cpu0.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing system.cpu0.l2cache.tags.replacements 252403 # number of replacements system.cpu0.l2cache.tags.tagsinuse 16129.283805 # Cycle average of tags in use system.cpu0.l2cache.tags.total_refs 1810262 # Total number of references to valid blocks. @@ -544,6 +593,14 @@ system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::total 2656528 # Request fanout histogram +system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -565,6 +622,24 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu1.dtb.walker.walks 3358 # Table walker walks requested +system.cpu1.dtb.walker.walksShort 3358 # Table walker walks initiated with short descriptors +system.cpu1.dtb.walker.walkWaitTime::samples 3358 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 3358 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 3358 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walksPending::samples -1804206736 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 -1804206736 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total -1804206736 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 1919 74.15% 74.15% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::1M 669 25.85% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 2588 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 3358 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 3358 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2588 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2588 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 5946 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses system.cpu1.dtb.read_hits 12173884 # DTB read hits @@ -586,6 +661,14 @@ system.cpu1.dtb.inst_accesses 0 # IT system.cpu1.dtb.hits 19761077 # DTB hits system.cpu1.dtb.misses 3358 # DTB misses system.cpu1.dtb.accesses 19764435 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -607,6 +690,24 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu1.itb.walker.walks 1734 # Table walker walks requested +system.cpu1.itb.walker.walksShort 1734 # Table walker walks initiated with short descriptors +system.cpu1.itb.walker.walkWaitTime::samples 1734 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 1734 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 1734 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walksPending::samples -1804209236 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 -1804209236 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total -1804209236 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 935 85.39% 85.39% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::1M 160 14.61% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 1095 # Table walker page sizes translated +system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 1734 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 1734 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1095 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1095 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 2829 # Table walker requests started/completed, data/inst system.cpu1.itb.inst_hits 53671431 # ITB inst hits system.cpu1.itb.inst_misses 1734 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits @@ -820,15 +921,12 @@ system.cpu1.icache.avg_blocked_cycles::no_targets nan system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu1.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue +system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped +system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size +system.cpu1.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing system.cpu1.l2cache.tags.replacements 48598 # number of replacements system.cpu1.l2cache.tags.tagsinuse 15305.342188 # Cycle average of tags in use system.cpu1.l2cache.tags.total_refs 716678 # Total number of references to valid blocks. diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt index 5c160a43e..fb9bec115 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.783867 # Nu sim_ticks 2783867165000 # Number of ticks simulated final_tick 2783867165000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1064003 # Simulator instruction rate (inst/s) -host_op_rate 1295252 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 20746494205 # Simulator tick rate (ticks/s) -host_mem_usage 558936 # Number of bytes of host memory used -host_seconds 134.19 # Real time elapsed on the host +host_inst_rate 1374338 # Simulator instruction rate (inst/s) +host_op_rate 1673035 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 26797569978 # Simulator tick rate (ticks/s) +host_mem_usage 615488 # Number of bytes of host memory used +host_seconds 103.89 # Real time elapsed on the host sim_insts 142773109 # Number of instructions simulated sim_ops 173803334 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -70,6 +70,14 @@ system.cf0.dma_write_full_pages 540 # Nu system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -91,6 +99,24 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 10029 # Table walker walks requested +system.cpu.dtb.walker.walksShort 10029 # Table walker walks initiated with short descriptors +system.cpu.dtb.walker.walkWaitTime::samples 10029 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0 10029 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::total 10029 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walksPending::samples 6705500 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::0 6705500 100.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::total 6705500 # Table walker pending requests distribution +system.cpu.dtb.walker.walkPageSizes::4K 6354 80.79% 80.79% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::1M 1511 19.21% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 7865 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 10029 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 10029 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7865 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7865 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 17894 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 31526301 # DTB read hits @@ -112,6 +138,14 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 54650764 # DTB hits system.cpu.dtb.misses 10029 # DTB misses system.cpu.dtb.accesses 54660793 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -133,6 +167,24 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 4762 # Table walker walks requested +system.cpu.itb.walker.walksShort 4762 # Table walker walks initiated with short descriptors +system.cpu.itb.walker.walkWaitTime::samples 4762 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0 4762 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::total 4762 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walksPending::samples 6702500 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::0 6702500 100.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::total 6702500 # Table walker pending requests distribution +system.cpu.itb.walker.walkPageSizes::4K 2798 90.05% 90.05% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::1M 309 9.95% 100.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 3107 # Table walker page sizes translated +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 4762 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 4762 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3107 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 3107 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 7869 # Table walker requests started/completed, data/inst system.cpu.itb.inst_hits 147039592 # ITB inst hits system.cpu.itb.inst_misses 4762 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt index ede2b82db..391769400 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt @@ -1,164 +1,160 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.867049 # Number of seconds simulated -sim_ticks 2867048515500 # Number of ticks simulated -final_tick 2867048515500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.868319 # Number of seconds simulated +sim_ticks 2868318696500 # Number of ticks simulated +final_tick 2868318696500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 753572 # Simulator instruction rate (inst/s) -host_op_rate 911512 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 16376301643 # Simulator tick rate (ticks/s) -host_mem_usage 607016 # Number of bytes of host memory used -host_seconds 175.07 # Real time elapsed on the host -sim_insts 131930165 # Number of instructions simulated -sim_ops 159581077 # Number of ops (including micro ops) simulated +host_inst_rate 534652 # Simulator instruction rate (inst/s) +host_op_rate 646675 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 11631340017 # Simulator tick rate (ticks/s) +host_mem_usage 586476 # Number of bytes of host memory used +host_seconds 246.60 # Real time elapsed on the host +sim_insts 131846562 # Number of instructions simulated +sim_ops 159471778 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 512 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 233060 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 810048 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 9243456 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 256 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 53844 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 455584 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 1704320 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 448 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 1173796 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 1283584 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 8628800 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 156308 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 605472 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 378048 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 12502168 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 233060 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 53844 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 286904 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8696768 # Number of bytes written to this memory +system.physmem.bytes_read::total 12227608 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 1173796 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 156308 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1330104 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8654400 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17704 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory -system.physmem.bytes_written::total 8714512 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 8 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 12095 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 13183 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 144429 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 4 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 996 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 7142 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 26630 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 8672144 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 7 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 26794 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 20582 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 134825 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 2597 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 9484 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 5907 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 204504 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 135887 # Number of write requests responded to by this memory +system.physmem.num_reads::total 200214 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 135225 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4426 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory -system.physmem.num_writes::total 140323 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 179 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 22 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 81289 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 282537 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 3224032 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 89 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 22 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 18780 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 158903 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 594451 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 139661 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 156 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 45 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 409228 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 447504 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 3008313 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 22 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 54495 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 211090 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 131801 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 335 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4360641 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 81289 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 18780 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 100069 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3033352 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 6175 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4262988 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 409228 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 54495 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 463723 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3017238 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 6172 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3039541 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3033352 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 179 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 81289 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 288712 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 3224032 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 89 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 18780 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 158917 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 594451 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 3023424 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3017238 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 156 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 45 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 409228 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 453676 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 3008313 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 22 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 54495 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 211103 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 131801 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 335 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7400182 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 204505 # Number of read requests accepted -system.physmem.writeReqs 176547 # Number of write requests accepted -system.physmem.readBursts 204505 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 176547 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 13079232 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 9088 # Total number of bytes read from write queue -system.physmem.bytesWritten 10932800 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 12502232 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 11032848 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 142 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 5691 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 15171 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 12666 # Per bank write bursts -system.physmem.perBankRdBursts::1 12263 # Per bank write bursts -system.physmem.perBankRdBursts::2 12897 # Per bank write bursts -system.physmem.perBankRdBursts::3 12449 # Per bank write bursts -system.physmem.perBankRdBursts::4 21010 # Per bank write bursts -system.physmem.perBankRdBursts::5 12626 # Per bank write bursts -system.physmem.perBankRdBursts::6 12991 # Per bank write bursts -system.physmem.perBankRdBursts::7 13024 # Per bank write bursts -system.physmem.perBankRdBursts::8 12039 # Per bank write bursts -system.physmem.perBankRdBursts::9 12109 # Per bank write bursts -system.physmem.perBankRdBursts::10 12276 # Per bank write bursts -system.physmem.perBankRdBursts::11 10996 # Per bank write bursts -system.physmem.perBankRdBursts::12 11725 # Per bank write bursts -system.physmem.perBankRdBursts::13 12231 # Per bank write bursts -system.physmem.perBankRdBursts::14 11672 # Per bank write bursts -system.physmem.perBankRdBursts::15 11389 # Per bank write bursts -system.physmem.perBankWrBursts::0 10702 # Per bank write bursts -system.physmem.perBankWrBursts::1 10814 # Per bank write bursts -system.physmem.perBankWrBursts::2 11122 # Per bank write bursts -system.physmem.perBankWrBursts::3 10684 # Per bank write bursts -system.physmem.perBankWrBursts::4 10817 # Per bank write bursts -system.physmem.perBankWrBursts::5 11014 # Per bank write bursts -system.physmem.perBankWrBursts::6 11094 # Per bank write bursts -system.physmem.perBankWrBursts::7 11085 # Per bank write bursts -system.physmem.perBankWrBursts::8 10650 # Per bank write bursts -system.physmem.perBankWrBursts::9 11040 # Per bank write bursts -system.physmem.perBankWrBursts::10 10845 # Per bank write bursts -system.physmem.perBankWrBursts::11 10150 # Per bank write bursts -system.physmem.perBankWrBursts::12 10760 # Per bank write bursts -system.physmem.perBankWrBursts::13 10359 # Per bank write bursts -system.physmem.perBankWrBursts::14 10115 # Per bank write bursts -system.physmem.perBankWrBursts::15 9574 # Per bank write bursts +system.physmem.bw_total::total 7286412 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 200214 # Number of read requests accepted +system.physmem.writeReqs 175885 # Number of write requests accepted +system.physmem.readBursts 200214 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 175885 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 12804096 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 9600 # Total number of bytes read from write queue +system.physmem.bytesWritten 10892544 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 12227608 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 10990480 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 150 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 5671 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 13850 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 12188 # Per bank write bursts +system.physmem.perBankRdBursts::1 12046 # Per bank write bursts +system.physmem.perBankRdBursts::2 12591 # Per bank write bursts +system.physmem.perBankRdBursts::3 12330 # Per bank write bursts +system.physmem.perBankRdBursts::4 20750 # Per bank write bursts +system.physmem.perBankRdBursts::5 12582 # Per bank write bursts +system.physmem.perBankRdBursts::6 12043 # Per bank write bursts +system.physmem.perBankRdBursts::7 12246 # Per bank write bursts +system.physmem.perBankRdBursts::8 12442 # Per bank write bursts +system.physmem.perBankRdBursts::9 12402 # Per bank write bursts +system.physmem.perBankRdBursts::10 11722 # Per bank write bursts +system.physmem.perBankRdBursts::11 11146 # Per bank write bursts +system.physmem.perBankRdBursts::12 11467 # Per bank write bursts +system.physmem.perBankRdBursts::13 11916 # Per bank write bursts +system.physmem.perBankRdBursts::14 10852 # Per bank write bursts +system.physmem.perBankRdBursts::15 11341 # Per bank write bursts +system.physmem.perBankWrBursts::0 10835 # Per bank write bursts +system.physmem.perBankWrBursts::1 11264 # Per bank write bursts +system.physmem.perBankWrBursts::2 11493 # Per bank write bursts +system.physmem.perBankWrBursts::3 10899 # Per bank write bursts +system.physmem.perBankWrBursts::4 10487 # Per bank write bursts +system.physmem.perBankWrBursts::5 11152 # Per bank write bursts +system.physmem.perBankWrBursts::6 11024 # Per bank write bursts +system.physmem.perBankWrBursts::7 10595 # Per bank write bursts +system.physmem.perBankWrBursts::8 10782 # Per bank write bursts +system.physmem.perBankWrBursts::9 10958 # Per bank write bursts +system.physmem.perBankWrBursts::10 10716 # Per bank write bursts +system.physmem.perBankWrBursts::11 10408 # Per bank write bursts +system.physmem.perBankWrBursts::12 10444 # Per bank write bursts +system.physmem.perBankWrBursts::13 9906 # Per bank write bursts +system.physmem.perBankWrBursts::14 9416 # Per bank write bursts +system.physmem.perBankWrBursts::15 9817 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2867048141000 # Total gap between requests +system.physmem.numWrRetry 1 # Number of times write queue was full causing retry +system.physmem.totGap 2868318254500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 9742 # Read request sizes (log2) system.physmem.readPktSize::3 28 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 194735 # Read request sizes (log2) +system.physmem.readPktSize::6 190444 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4436 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 172111 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 120800 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 21636 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 13302 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 11154 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 9500 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 8185 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 6994 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 6210 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 5370 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 523 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 257 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 166 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 124 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 70 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 45 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 23 # What read queue length does an incoming req see +system.physmem.writePktSize::6 171449 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 138850 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 16077 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 10399 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 9072 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 7297 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 5697 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 4782 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 4036 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3549 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 129 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 88 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 52 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 20 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 8 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see @@ -188,178 +184,179 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2981 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4683 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 6009 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 8149 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 9072 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 10204 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 10828 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 11783 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 11696 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 12526 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 11858 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 11537 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 10823 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 10903 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 8826 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 8488 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 8264 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7768 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 596 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 465 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 355 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 278 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 265 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 233 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 220 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 228 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 214 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 199 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 183 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 149 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 154 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 151 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 129 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 116 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 103 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 103 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 85 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2909 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 4636 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 6298 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 8259 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 9096 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 10239 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 10826 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 11796 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 11771 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 12530 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 11837 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 11533 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 10810 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 10665 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 8741 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 8334 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 8094 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 7730 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 533 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 391 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 344 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 288 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 237 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 218 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 213 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 197 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 169 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 169 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 151 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 144 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 133 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 120 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 106 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 107 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 93 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 83 # What write queue length does an incoming req see system.physmem.wrQLenPdf::52 65 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 52 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 39 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 60 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 46 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 26 # What write queue length does an incoming req see system.physmem.wrQLenPdf::56 22 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 83215 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 288.553362 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 159.296581 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 336.078048 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 39267 47.19% 47.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 16171 19.43% 66.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6480 7.79% 74.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3347 4.02% 78.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 3132 3.76% 82.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1913 2.30% 84.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1073 1.29% 85.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1034 1.24% 87.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 10798 12.98% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 83215 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 7042 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 29.019171 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 531.269210 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 7040 99.97% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-4095 1 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::57 23 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 13 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 2 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 90415 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 262.086778 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 144.561031 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 323.181928 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 46335 51.25% 51.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 17813 19.70% 70.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6067 6.71% 77.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3600 3.98% 81.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2534 2.80% 84.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1568 1.73% 86.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1031 1.14% 87.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 985 1.09% 88.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 10482 11.59% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 90415 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 7120 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 28.098736 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 516.724228 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 7117 99.96% 99.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-4095 2 0.03% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::43008-45055 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 7042 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 7042 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 24.258023 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 20.337274 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 22.786425 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5509 78.23% 78.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 384 5.45% 83.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 77 1.09% 84.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 222 3.15% 87.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 122 1.73% 89.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 57 0.81% 90.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 43 0.61% 91.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 37 0.53% 91.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 124 1.76% 93.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 15 0.21% 93.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 18 0.26% 93.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 16 0.23% 94.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 34 0.48% 94.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 16 0.23% 94.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 7 0.10% 94.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 27 0.38% 95.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 62 0.88% 96.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 11 0.16% 96.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 6 0.09% 96.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 10 0.14% 96.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 88 1.25% 97.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 4 0.06% 97.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 12 0.17% 98.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 6 0.09% 98.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 19 0.27% 98.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 2 0.03% 98.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 11 0.16% 98.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 4 0.06% 98.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 36 0.51% 99.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 11 0.16% 99.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 4 0.06% 99.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 7 0.10% 99.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 5 0.07% 99.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 2 0.03% 99.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 1 0.01% 99.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 7 0.10% 99.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 2 0.03% 99.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 4 0.06% 99.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 4 0.06% 99.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 1 0.01% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-187 2 0.03% 99.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 1 0.01% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-195 2 0.03% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::196-199 1 0.01% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::204-207 1 0.01% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::212-215 2 0.03% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-219 1 0.01% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-227 1 0.01% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::228-231 1 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::232-235 1 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::248-251 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::252-255 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 7042 # Writes before turning the bus around for reads -system.physmem.totQLat 5974898500 # Total ticks spent queuing -system.physmem.totMemAccLat 9806704750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1021815000 # Total ticks spent in databus transfers -system.physmem.avgQLat 29236.69 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 7120 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 7120 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 23.903933 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 20.122109 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 22.073987 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 5764 80.96% 80.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 237 3.33% 84.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 43 0.60% 84.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 234 3.29% 88.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 121 1.70% 89.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 62 0.87% 90.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 31 0.44% 91.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 36 0.51% 91.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 117 1.64% 93.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 18 0.25% 93.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 25 0.35% 93.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 16 0.22% 94.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 40 0.56% 94.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 10 0.14% 94.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 17 0.24% 95.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 28 0.39% 95.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 58 0.81% 96.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 14 0.20% 96.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 7 0.10% 96.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 6 0.08% 96.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 88 1.24% 97.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 4 0.06% 97.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 12 0.17% 98.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 1 0.01% 98.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 15 0.21% 98.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 6 0.08% 98.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 14 0.20% 98.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 9 0.13% 98.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 35 0.49% 99.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 6 0.08% 99.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 1 0.01% 99.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 4 0.06% 99.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 8 0.11% 99.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 2 0.03% 99.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 3 0.04% 99.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 1 0.01% 99.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 8 0.11% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 2 0.03% 99.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-171 1 0.01% 99.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 1 0.01% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 4 0.06% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::180-183 1 0.01% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-187 1 0.01% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::196-199 1 0.01% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-203 1 0.01% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-211 1 0.01% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-227 3 0.04% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::228-231 3 0.04% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 7120 # Writes before turning the bus around for reads +system.physmem.totQLat 4855930250 # Total ticks spent queuing +system.physmem.totMemAccLat 8607130250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1000320000 # Total ticks spent in databus transfers +system.physmem.avgQLat 24271.88 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 47986.69 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 4.56 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 3.81 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 4.36 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 3.85 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 43021.88 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 4.46 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 3.80 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 4.26 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 3.83 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.07 # Data bus utilization in percentage -system.physmem.busUtilRead 0.04 # Data bus utilization in percentage for reads +system.physmem.busUtil 0.06 # Data bus utilization in percentage +system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 2.01 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.00 # Average write queue length when enqueuing -system.physmem.readRowHits 174382 # Number of row buffer hits during reads -system.physmem.writeRowHits 117590 # Number of row buffer hits during writes -system.physmem.readRowHitRate 85.33 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 68.82 # Row buffer hit rate for writes -system.physmem.avgGap 7524033.84 # Average gap between requests -system.physmem.pageHitRate 77.81 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 2731090191250 # Time in different power states -system.physmem.memoryStateTime::REF 95736940000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 40221363750 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 330432480 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 298672920 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 180295500 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 162966375 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 857422800 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 736600800 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 565911360 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 541034640 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 187261454640 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 187261454640 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 82724898285 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 81530993385 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 1647661560750 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 1648708845750 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 1919581975815 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 1919240568510 # Total energy per rank (pJ) -system.physmem.averagePower::0 669.533155 # Core power per rank (mW) -system.physmem.averagePower::1 669.414075 # Core power per rank (mW) +system.physmem.avgRdQLen 1.07 # Average read queue length when enqueuing +system.physmem.avgWrQLen 22.69 # Average write queue length when enqueuing +system.physmem.readRowHits 167229 # Number of row buffer hits during reads +system.physmem.writeRowHits 112615 # Number of row buffer hits during writes +system.physmem.readRowHitRate 83.59 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 66.16 # Row buffer hit rate for writes +system.physmem.avgGap 7626497.96 # Average gap between requests +system.physmem.pageHitRate 75.58 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 354707640 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 193540875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 832845000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 568613520 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 187344349920 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 84727272375 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1646666587500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1920687916830 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.622475 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2739235632500 # Time in different power states +system.physmem_0.memoryStateTime::REF 95779320000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 33303656000 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 328829760 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 179421000 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 727646400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 534256560 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 187344349920 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 83962556955 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1647337390500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1920414451095 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.527135 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2740355751000 # Time in different power states +system.physmem_1.memoryStateTime::REF 95779320000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 32179536500 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory @@ -385,6 +382,14 @@ system.cf0.dma_write_full_pages 540 # Nu system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -406,27 +411,65 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu0.dtb.walker.walks 7749 # Table walker walks requested +system.cpu0.dtb.walker.walksShort 7749 # Table walker walks initiated with short descriptors +system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 1459 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 6290 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walkWaitTime::samples 7749 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 7749 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 7749 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 6355 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 8363.375452 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 7097.000757 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 5454.838397 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-16383 6203 97.61% 97.61% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::16384-32767 142 2.23% 99.84% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::32768-49151 6 0.09% 99.94% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::81920-98303 3 0.05% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::180224-196607 1 0.02% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 6355 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 987959000 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 987959000 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 987959000 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 4935 77.66% 77.66% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 1420 22.34% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 6355 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 7749 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 7749 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6355 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6355 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 14104 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 22739909 # DTB read hits -system.cpu0.dtb.read_misses 4142 # DTB read misses -system.cpu0.dtb.write_hits 16676295 # DTB write hits -system.cpu0.dtb.write_misses 677 # DTB write misses +system.cpu0.dtb.read_hits 19044092 # DTB read hits +system.cpu0.dtb.read_misses 6608 # DTB read misses +system.cpu0.dtb.write_hits 15688894 # DTB write hits +system.cpu0.dtb.write_misses 1141 # DTB write misses system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 2392 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 3442 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 1346 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 1734 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 187 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 22744051 # DTB read accesses -system.cpu0.dtb.write_accesses 16676972 # DTB write accesses +system.cpu0.dtb.perms_faults 282 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 19050700 # DTB read accesses +system.cpu0.dtb.write_accesses 15690035 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 39416204 # DTB hits -system.cpu0.dtb.misses 4819 # DTB misses -system.cpu0.dtb.accesses 39421023 # DTB accesses +system.cpu0.dtb.hits 34732986 # DTB hits +system.cpu0.dtb.misses 7749 # DTB misses +system.cpu0.dtb.accesses 34740735 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -448,8 +491,40 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.inst_hits 107931670 # ITB inst hits -system.cpu0.itb.inst_misses 2300 # ITB inst misses +system.cpu0.itb.walker.walks 3348 # Table walker walks requested +system.cpu0.itb.walker.walksShort 3348 # Table walker walks initiated with short descriptors +system.cpu0.itb.walker.walksShortTerminationLevel::Level1 298 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3050 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walkWaitTime::samples 3348 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 3348 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 3348 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 2332 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 8781.732419 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 7396.194245 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 5559.104899 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-8191 1469 62.99% 62.99% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::8192-16383 817 35.03% 98.03% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::16384-24575 4 0.17% 98.20% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::24576-32767 39 1.67% 99.87% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::40960-49151 1 0.04% 99.91% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::81920-90111 1 0.04% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::106496-114687 1 0.04% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 2332 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksPending::samples 987617000 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 987617000 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 987617000 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 2034 87.22% 87.22% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::1M 298 12.78% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 2332 # Table walker page sizes translated +system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3348 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3348 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2332 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2332 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 5680 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 91510827 # ITB inst hits +system.cpu0.itb.inst_misses 3348 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -458,178 +533,179 @@ system.cpu0.itb.flush_tlb 66 # Nu system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1397 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2150 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 107933970 # ITB inst accesses -system.cpu0.itb.hits 107931670 # DTB hits -system.cpu0.itb.misses 2300 # DTB misses -system.cpu0.itb.accesses 107933970 # DTB accesses -system.cpu0.numCycles 5733190951 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 91514175 # ITB inst accesses +system.cpu0.itb.hits 91510827 # DTB hits +system.cpu0.itb.misses 3348 # DTB misses +system.cpu0.itb.accesses 91514175 # DTB accesses +system.cpu0.numCycles 5736637393 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 104697045 # Number of instructions committed -system.cpu0.committedOps 126437300 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 112138973 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 4560 # Number of float alu accesses -system.cpu0.num_func_calls 12218983 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 14112779 # number of instructions that are conditional controls -system.cpu0.num_int_insts 112138973 # number of integer instructions -system.cpu0.num_fp_insts 4560 # number of float instructions -system.cpu0.num_int_register_reads 207168140 # number of times the integer registers were read -system.cpu0.num_int_register_writes 78157614 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 3646 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 916 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 458862041 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 46623468 # number of times the CC registers were written -system.cpu0.num_mem_refs 40473955 # number of memory refs -system.cpu0.num_load_insts 22968630 # Number of load instructions -system.cpu0.num_store_insts 17505325 # Number of store instructions -system.cpu0.num_idle_cycles 5494072814.437573 # Number of idle cycles -system.cpu0.num_busy_cycles 239118136.562427 # Number of busy cycles -system.cpu0.not_idle_fraction 0.041708 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.958292 # Percentage of idle cycles -system.cpu0.Branches 26957408 # Number of branches fetched -system.cpu0.op_class::No_OpClass 2171 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 89486890 68.80% 68.80% # Class of executed instruction -system.cpu0.op_class::IntMult 99356 0.08% 68.88% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 6997 0.01% 68.88% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.88% # Class of executed instruction -system.cpu0.op_class::MemRead 22968630 17.66% 86.54% # Class of executed instruction -system.cpu0.op_class::MemWrite 17505325 13.46% 100.00% # Class of executed instruction +system.cpu0.committedInsts 89363678 # Number of instructions committed +system.cpu0.committedOps 107297883 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 94350928 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 9820 # Number of float alu accesses +system.cpu0.num_func_calls 6606472 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 12627044 # number of instructions that are conditional controls +system.cpu0.num_int_insts 94350928 # number of integer instructions +system.cpu0.num_fp_insts 9820 # number of float instructions +system.cpu0.num_int_register_reads 169124164 # number of times the integer registers were read +system.cpu0.num_int_register_writes 64348180 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 7560 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 2264 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 385798415 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 43074064 # number of times the CC registers were written +system.cpu0.num_mem_refs 35866705 # number of memory refs +system.cpu0.num_load_insts 19295047 # Number of load instructions +system.cpu0.num_store_insts 16571658 # Number of store instructions +system.cpu0.num_idle_cycles 5512519658.266078 # Number of idle cycles +system.cpu0.num_busy_cycles 224117734.733922 # Number of busy cycles +system.cpu0.not_idle_fraction 0.039068 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.960932 # Percentage of idle cycles +system.cpu0.Branches 19970568 # Number of branches fetched +system.cpu0.op_class::No_OpClass 2273 0.00% 0.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 73557669 67.15% 67.15% # Class of executed instruction +system.cpu0.op_class::IntMult 108302 0.10% 67.25% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 8177 0.01% 67.26% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 67.26% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 67.26% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 67.26% # Class of executed instruction +system.cpu0.op_class::MemRead 19295047 17.61% 84.87% # Class of executed instruction +system.cpu0.op_class::MemWrite 16571658 15.13% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 130069369 # Class of executed instruction +system.cpu0.op_class::total 109543126 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 1990 # number of quiesce instructions executed -system.cpu0.dcache.tags.replacements 555287 # number of replacements -system.cpu0.dcache.tags.tagsinuse 484.900335 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 38705991 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 555652 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 69.658691 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 1015660000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 484.900335 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.947071 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.947071 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 365 # Occupied blocks per task id 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(read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 7946376701 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 7946376701 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 21959658 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 21959658 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 16304261 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 16304261 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 396965 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 396965 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 354406 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 354406 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 350005 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 350005 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 38263919 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 38263919 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 38660884 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 38660884 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.013885 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.013885 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.016156 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.016156 # miss rate for WriteReq accesses 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12844.804468 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 12844.804468 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 15298.277570 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 15298.277570 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16066.841106 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16066.841106 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22341.448587 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22341.448587 # average StoreCondReq miss latency +system.cpu0.kern.inst.quiesce 1879 # number of quiesce instructions executed +system.cpu0.dcache.tags.replacements 690539 # number of replacements +system.cpu0.dcache.tags.tagsinuse 487.185772 # Cycle average of tags in use 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13981.976494 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 12029.356993 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 12029.356993 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 13810.670579 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 13810.670579 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 11728.239826 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 11728.239826 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -638,82 +714,82 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets 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cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 86260500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 86260500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 420440307 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 420440307 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1400500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1400500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6726360299 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 6726360299 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7766691538 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 7766691538 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5556589244 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5556589244 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 4171949493 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4171949493 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 9728538737 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 9728538737 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.013557 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.013557 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.016156 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.016156 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.210152 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.210152 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016755 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016755 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.059156 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.059156 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.014664 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.014664 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.016672 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.016672 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 10856.637969 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 10856.637969 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 13265.336154 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 13265.336154 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 12470.556549 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 12470.556549 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14526.860896 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14526.860896 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 20306.221058 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 20306.221058 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 504116 # number of writebacks +system.cpu0.dcache.writebacks::total 504116 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 25128 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 25128 # number of ReadReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 15248 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 15248 # number of LoadLockedReq MSHR hits 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+system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6462 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 20007 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 20007 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 694258 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 694258 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 794728 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 794728 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 3859056498 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 3859056498 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4283066685 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4283066685 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1502769500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1502769500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 90797250 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 90797250 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 403751255 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 403751255 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1480500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1480500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 8142123183 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 8142123183 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 9644892683 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 9644892683 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5991645999 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5991645999 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 4628507500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4628507500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 10620153499 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10620153499 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.020339 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.020339 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.021231 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.021231 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.225139 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.225139 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016713 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016713 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.052414 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.052414 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.020746 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.020746 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.023436 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.023436 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 10436.172336 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 10436.172336 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 13199.745702 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 13199.745702 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 14957.395242 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14957.395242 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14050.951718 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14050.951718 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 20180.499575 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 20180.499575 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 11987.404274 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 11987.404274 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 12049.938620 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 12049.938620 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 11727.806065 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 11727.806065 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 12136.092705 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 12136.092705 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -721,58 +797,58 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 945322 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.483250 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 106985827 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 945834 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 113.112689 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 12806917500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.483250 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998991 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.998991 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 1099798 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.479276 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 90410508 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 1100310 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 82.168214 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 13323414750 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.479276 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998983 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.998983 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 390 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::3 113 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::4 9 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 91 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 206 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 215 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 216809183 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 216809183 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 106985827 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 106985827 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 106985827 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 106985827 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 106985827 # number of overall hits -system.cpu0.icache.overall_hits::total 106985827 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 945843 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 945843 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 945843 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 945843 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 945843 # number of overall misses -system.cpu0.icache.overall_misses::total 945843 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 8025066767 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 8025066767 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 8025066767 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 8025066767 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 8025066767 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 8025066767 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 107931670 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 107931670 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 107931670 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 107931670 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 107931670 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 107931670 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.008763 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.008763 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.008763 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.008763 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.008763 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.008763 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 8484.565374 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 8484.565374 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 8484.565374 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 8484.565374 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 8484.565374 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 8484.565374 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 184121973 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 184121973 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 90410508 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 90410508 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 90410508 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 90410508 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 90410508 # number of overall hits +system.cpu0.icache.overall_hits::total 90410508 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 1100319 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1100319 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 1100319 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 1100319 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 1100319 # number of overall misses +system.cpu0.icache.overall_misses::total 1100319 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 10739818993 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 10739818993 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 10739818993 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 10739818993 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 10739818993 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 10739818993 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 91510827 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 91510827 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 91510827 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 91510827 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 91510827 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 91510827 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.012024 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.012024 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.012024 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.012024 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.012024 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.012024 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 9760.641226 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 9760.641226 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 9760.641226 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 9760.641226 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 9760.641226 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 9760.641226 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # 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+system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.150199 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.150199 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.026912 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.032690 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.042852 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.181442 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.098416 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.026912 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.032690 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.042852 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.181442 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.337710 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 14777.142857 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 13642.857143 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 38461.796703 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 20786.539028 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 22948.970488 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 41504.638547 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 41504.638547 # average HardPFReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 16022.760491 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16022.760491 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 13487.284200 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13487.284200 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 135061.875000 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 135061.875000 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 25088.846516 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 25088.846516 # average ReadExReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 14777.142857 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 13642.857143 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 38461.796703 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 22295.614310 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 23632.150845 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 14777.142857 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 13642.857143 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 38461.796703 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 22295.614310 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 41504.638547 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 37234.830640 # average overall mshr miss latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.230973 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 15787.209302 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 15241.803279 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 39810.184365 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 21210.648570 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 27355.831422 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 56455.149661 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 56455.149661 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 16861.304032 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16861.304032 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 13443.888901 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13443.888901 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 139061.875000 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 139061.875000 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 34119.787657 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 34119.787657 # average ReadExReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 15787.209302 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 15241.803279 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 39810.184365 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 25069.984593 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 28852.904128 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 15787.209302 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 15241.803279 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 39810.184365 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 25069.984593 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 56455.149661 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 44694.051386 # average overall mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1140,58 +1213,66 @@ system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.trans_dist::ReadReq 1585084 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 1436635 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 26190 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 26190 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::Writeback 420867 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 537670 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 82377 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 43315 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 100677 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadReq 1737767 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 1686227 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 27891 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 27891 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::Writeback 504114 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 316054 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 36225 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 89164 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42476 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 112407 # Transaction distribution system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 43 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 75 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 246727 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 235853 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 1909730 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 1979159 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 7030 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 14021 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 3909940 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 60570040 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 70330266 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 10652 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 21224 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 130932182 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 972661 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 2913864 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 5.296127 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.456548 # Request fanout histogram +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 81 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 298764 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 285064 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 2218682 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2366147 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 10130 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 22028 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 4616987 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 70456504 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 84324454 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 14928 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 31956 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 154827842 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 648932 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 2984532 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 5.180419 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.384536 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::5 2050990 70.39% 70.39% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::6 862874 29.61% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::5 2446067 81.96% 81.96% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::6 538465 18.04% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 2913864 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 1492069922 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 2984532 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 1775358935 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 116074499 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 115165999 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 1430234267 # Layer occupancy (ticks) -system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 995136418 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 1664866493 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) +system.cpu0.toL2Bus.respLayer1.occupancy 1209535062 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 4367000 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 6398000 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 8715750 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 14039749 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) +system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1213,27 +1294,67 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu1.dtb.walker.walks 3332 # Table walker walks requested +system.cpu1.dtb.walker.walksShort 3332 # Table walker walks initiated with short descriptors +system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 642 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 2690 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walkWaitTime::samples 3332 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 3332 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 3332 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 2562 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 8324.355972 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 7260.502547 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 4990.324891 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-8191 2067 80.68% 80.68% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::8192-16383 375 14.64% 95.32% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::16384-24575 62 2.42% 97.74% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::24576-32767 50 1.95% 99.69% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::32768-40959 4 0.16% 99.84% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::40960-49151 3 0.12% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::81920-90111 1 0.04% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 2562 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 1455144968 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 1455144968 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 1455144968 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 1928 75.25% 75.25% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::1M 634 24.75% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 2562 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 3332 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 3332 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2562 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2562 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 5894 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 6438534 # DTB read hits -system.cpu1.dtb.read_misses 5066 # DTB read misses -system.cpu1.dtb.write_hits 5578600 # DTB write hits -system.cpu1.dtb.write_misses 983 # DTB write misses +system.cpu1.dtb.read_hits 10115566 # DTB read hits +system.cpu1.dtb.read_misses 2828 # DTB read misses +system.cpu1.dtb.write_hits 6544640 # DTB write hits +system.cpu1.dtb.write_misses 504 # DTB write misses system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 3048 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 2029 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 541 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 346 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 258 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 6443600 # DTB read accesses -system.cpu1.dtb.write_accesses 5579583 # DTB write accesses +system.cpu1.dtb.perms_faults 163 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 10118394 # DTB read accesses +system.cpu1.dtb.write_accesses 6545144 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 12017134 # DTB hits -system.cpu1.dtb.misses 6049 # DTB misses -system.cpu1.dtb.accesses 12023183 # DTB accesses +system.cpu1.dtb.hits 16660206 # DTB hits +system.cpu1.dtb.misses 3332 # DTB misses +system.cpu1.dtb.accesses 16663538 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1255,8 +1376,42 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.inst_hits 28023624 # ITB inst hits -system.cpu1.itb.inst_misses 2794 # ITB inst misses +system.cpu1.itb.walker.walks 1746 # Table walker walks requested +system.cpu1.itb.walker.walksShort 1746 # Table walker walks initiated with short descriptors +system.cpu1.itb.walker.walksShortTerminationLevel::Level1 168 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walksShortTerminationLevel::Level2 1578 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 1746 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 1746 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 1746 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 1107 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 8955.736224 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 7685.889357 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 5645.921496 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-4095 191 17.25% 17.25% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::4096-8191 643 58.08% 75.34% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::12288-16383 217 19.60% 94.94% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::16384-20479 1 0.09% 95.03% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::20480-24575 3 0.27% 95.30% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::24576-28671 27 2.44% 97.74% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::28672-32767 19 1.72% 99.46% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::36864-40959 3 0.27% 99.73% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::40960-45055 3 0.27% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 1107 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples 1454651968 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 1454651968 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 1454651968 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 939 84.82% 84.82% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::1M 168 15.18% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 1107 # Table walker page sizes translated +system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 1746 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 1746 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1107 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1107 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 2853 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 44359905 # ITB inst hits +system.cpu1.itb.inst_misses 1746 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1265,179 +1420,178 @@ system.cpu1.itb.flush_tlb 66 # Nu system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1901 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1148 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 28026418 # ITB inst accesses -system.cpu1.itb.hits 28023624 # DTB hits -system.cpu1.itb.misses 2794 # DTB misses -system.cpu1.itb.accesses 28026418 # DTB accesses -system.cpu1.numCycles 5734097031 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 44361651 # ITB inst accesses +system.cpu1.itb.hits 44359905 # DTB hits +system.cpu1.itb.misses 1746 # DTB misses +system.cpu1.itb.accesses 44361651 # DTB accesses +system.cpu1.numCycles 5735725430 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 27233120 # Number of instructions committed -system.cpu1.committedOps 33143777 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 29468029 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 6988 # Number of float alu accesses -system.cpu1.num_func_calls 1518648 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 3438745 # number of instructions that are conditional controls -system.cpu1.num_int_insts 29468029 # number of integer instructions -system.cpu1.num_fp_insts 6988 # number of float instructions -system.cpu1.num_int_register_reads 53045981 # number of times the integer registers were read -system.cpu1.num_int_register_writes 20334319 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 5190 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 1800 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 119969216 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 12226644 # number of times the CC registers were written -system.cpu1.num_mem_refs 12358568 # number of memory refs -system.cpu1.num_load_insts 6575418 # Number of load instructions -system.cpu1.num_store_insts 5783150 # Number of store instructions -system.cpu1.num_idle_cycles 5655719559.150027 # Number of idle cycles -system.cpu1.num_busy_cycles 78377471.849973 # Number of busy cycles -system.cpu1.not_idle_fraction 0.013669 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.986331 # Percentage of idle cycles -system.cpu1.Branches 5151142 # Number of branches fetched -system.cpu1.op_class::No_OpClass 168 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 21257809 63.16% 63.16% # Class of executed instruction -system.cpu1.op_class::IntMult 38403 0.11% 63.27% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 63.27% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 63.27% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 63.27% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 63.27% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 63.27% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 63.27% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 63.27% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 63.27% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 63.27% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 63.27% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 63.27% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 63.27% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 63.27% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 63.27% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 63.27% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 63.27% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 63.27% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 63.27% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 63.27% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 63.27% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 63.27% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 63.27% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 63.27% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 4420 0.01% 63.28% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 63.28% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 63.28% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 63.28% # Class of executed instruction -system.cpu1.op_class::MemRead 6575418 19.54% 82.82% # Class of executed instruction -system.cpu1.op_class::MemWrite 5783150 17.18% 100.00% # Class of executed instruction +system.cpu1.committedInsts 42482884 # Number of instructions committed +system.cpu1.committedOps 52173895 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 47161467 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 1857 # Number of float alu accesses +system.cpu1.num_func_calls 7121857 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 4915281 # number of instructions that are conditional controls +system.cpu1.num_int_insts 47161467 # number of integer instructions +system.cpu1.num_fp_insts 1857 # number of float instructions +system.cpu1.num_int_register_reads 90906541 # number of times the integer registers were read +system.cpu1.num_int_register_writes 34070734 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 1341 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 516 # number of times the floating registers were written +system.cpu1.num_cc_register_reads 192636366 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 15749934 # number of times the CC registers were written +system.cpu1.num_mem_refs 16924073 # number of memory refs +system.cpu1.num_load_insts 10229886 # Number of load instructions +system.cpu1.num_store_insts 6694187 # Number of store instructions +system.cpu1.num_idle_cycles 5637554126.704413 # Number of idle cycles +system.cpu1.num_busy_cycles 98171303.295587 # Number of busy cycles +system.cpu1.not_idle_fraction 0.017116 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.982884 # Percentage of idle cycles +system.cpu1.Branches 12116511 # Number of branches fetched +system.cpu1.op_class::No_OpClass 66 0.00% 0.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 37117349 68.64% 68.64% # Class of executed instruction +system.cpu1.op_class::IntMult 29132 0.05% 68.70% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 68.70% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 68.70% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 68.70% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 68.70% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 68.70% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 68.70% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 68.70% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 68.70% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 68.70% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 68.70% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 68.70% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 68.70% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 68.70% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 68.70% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 68.70% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 68.70% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 68.70% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 68.70% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 68.70% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 68.70% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 68.70% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 68.70% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 68.70% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 3361 0.01% 68.70% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 68.70% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 68.70% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 68.70% # Class of executed instruction +system.cpu1.op_class::MemRead 10229886 18.92% 87.62% # Class of executed instruction +system.cpu1.op_class::MemWrite 6694187 12.38% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 33659368 # Class of executed instruction +system.cpu1.op_class::total 54073981 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2818 # number of quiesce instructions executed -system.cpu1.dcache.tags.replacements 321673 # number of replacements -system.cpu1.dcache.tags.tagsinuse 481.284483 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 11622088 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 322185 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 36.072716 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 104113347000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 481.284483 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.940009 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.940009 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 118 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 275 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 119 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 24380907 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 24380907 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 5961630 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 5961630 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 5307193 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 5307193 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 82380 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 82380 # number of SoftPFReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 110885 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 110885 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 104150 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 104150 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 11268823 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 11268823 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 11351203 # number of overall hits -system.cpu1.dcache.overall_hits::total 11351203 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 210202 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 210202 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 138084 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 138084 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 48251 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 48251 # number of SoftPFReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 19527 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 19527 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23870 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 23870 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 348286 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 348286 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 396537 # number of overall misses -system.cpu1.dcache.overall_misses::total 396537 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2787267513 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 2787267513 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2672172287 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 2672172287 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 339794001 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 339794001 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 550321118 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 550321118 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1627000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1627000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 5459439800 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 5459439800 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 5459439800 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 5459439800 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 6171832 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 6171832 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 5445277 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 5445277 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 130631 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 130631 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 130412 # number of LoadLockedReq accesses(hits+misses) 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replacements +system.cpu1.dcache.tags.tagsinuse 472.360308 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 16390617 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 191421 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 85.626013 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 104654883500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 472.360308 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.922579 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.922579 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 363 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 312 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::3 51 # Occupied blocks per task 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15675.162941 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 13767.794178 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 13767.794178 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 18868.199815 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 18868.199815 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16668.130651 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 16668.130651 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1446,82 +1600,82 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 197265 # number of writebacks -system.cpu1.dcache.writebacks::total 197265 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 459 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 459 # number of ReadReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 13505 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 13505 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 459 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 459 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 459 # number of overall MSHR hits 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number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 5382315699 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 968585999 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 968585999 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 845308497 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 845308497 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1813894496 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1813894496 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033984 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.033984 # 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+system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5147 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23379 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 23379 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 230274 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 230274 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 259932 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 259932 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1715737747 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1715737747 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2159697659 # number of WriteReq MSHR miss cycles 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uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 905040500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.013803 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.013803 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014450 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.014450 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.369999 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.369999 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.053129 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.053129 # mshr miss rate for LoadLockedReq accesses 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23185.906782 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 15754.922786 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 15754.922786 # average SoftPFReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 15975.568292 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15975.568292 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 21023.042346 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21023.042346 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 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system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1529,58 +1683,58 @@ system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 680772 # number of replacements -system.cpu1.icache.tags.tagsinuse 498.691095 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 27342334 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 681284 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 40.133533 # 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cycles access was blocked @@ -1589,361 +1743,347 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 681285 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 681285 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 681285 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 681285 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 681285 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 681285 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4634848490 # number of ReadReq MSHR miss cycles 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mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 6803.097808 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 6803.097808 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 527235 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 527235 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 527235 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 527235 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 527235 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 527235 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3826248740 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 3826248740 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3826248740 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 3826248740 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3826248740 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 3826248740 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 13994500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 13994500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 13994500 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 13994500 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.011885 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.011885 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.011885 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.011885 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.011885 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.011885 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 7257.197910 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 7257.197910 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 7257.197910 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 7257.197910 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 7257.197910 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 7257.197910 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified 5735095 # number of hwpf identified -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 38649 # number of hwpf that were already in mshr -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 5537320 # number of hwpf that were already in the cache -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 267 # number of hwpf that were already in the prefetch queue -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 19 # number of hwpf removed because MSHR allocated -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 158840 # number of hwpf issued -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 604377 # number of hwpf spanning a virtual page -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu1.l2cache.tags.replacements 130093 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 15612.463834 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 1076740 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 146334 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 7.358099 # Average number of references to valid blocks. +system.cpu1.l2cache.prefetcher.num_hwpf_issued 199846 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 199846 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue +system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped +system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size +system.cpu1.l2cache.prefetcher.pfSpanPage 59474 # number of prefetches not generated due to page crossing +system.cpu1.l2cache.tags.replacements 47689 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 15083.724459 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 731618 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 62301 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 11.743279 # Average number of references to valid blocks. system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 4806.943324 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 3.120223 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 1.343631 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 874.835505 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.data 1500.703163 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 8425.517990 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.293393 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000190 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000082 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.053396 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.091596 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.514253 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.952909 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 7913 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 4 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 8324 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::0 47 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 90 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 2030 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 4783 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 963 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 1 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 129 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 2875 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4662 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 602 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.482971 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.000244 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.508057 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 21325891 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 21325891 # Number of data accesses -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 5234 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 2693 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.inst 672894 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.data 186024 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 866845 # number of ReadReq hits -system.cpu1.l2cache.Writeback_hits::writebacks 197265 # number of Writeback hits -system.cpu1.l2cache.Writeback_hits::total 197265 # number of Writeback hits -system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 2024 # number of UpgradeReq hits -system.cpu1.l2cache.UpgradeReq_hits::total 2024 # number of UpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 1217 # number of SCUpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::total 1217 # number of SCUpgradeReq hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.data 69989 # number of ReadExReq hits -system.cpu1.l2cache.ReadExReq_hits::total 69989 # number of ReadExReq hits -system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 5234 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.itb.walker 2693 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.inst 672894 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.data 256013 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::total 936834 # number of demand (read+write) hits -system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 5234 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.itb.walker 2693 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 672894 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.data 256013 # number of overall hits -system.cpu1.l2cache.overall_hits::total 936834 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 261 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 216 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.inst 8391 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.data 76389 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 85257 # number of ReadReq misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 29955 # number of UpgradeReq misses -system.cpu1.l2cache.UpgradeReq_misses::total 29955 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22648 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::total 22648 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 5 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::total 5 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.ReadExReq_misses::cpu1.data 36116 # number of ReadExReq misses -system.cpu1.l2cache.ReadExReq_misses::total 36116 # number of ReadExReq misses -system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 261 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.itb.walker 216 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.inst 8391 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.data 112505 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::total 121373 # number of demand (read+write) misses -system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 261 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.itb.walker 216 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.inst 8391 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.data 112505 # number of overall misses -system.cpu1.l2cache.overall_misses::total 121373 # number of overall misses -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 5754999 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 4668500 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 255474477 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data 1702549656 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::total 1968447632 # number of ReadReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 542491459 # number of UpgradeReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::total 542491459 # number of UpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 444517157 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 444517157 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 1522000 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 1522000 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1159011538 # number of ReadExReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::total 1159011538 # number of ReadExReq miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 5754999 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 4668500 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.inst 255474477 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.data 2861561194 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::total 3127459170 # number of demand (read+write) miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 5754999 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 4668500 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.inst 255474477 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.data 2861561194 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::total 3127459170 # number of overall miss cycles -system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 5495 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 2909 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 681285 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.data 262413 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::total 952102 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::writebacks 197265 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::total 197265 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 31979 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::total 31979 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23865 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::total 23865 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 5 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 5 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 106105 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::total 106105 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 5495 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 2909 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.inst 681285 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.data 368518 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::total 1058207 # number of demand (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 5495 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 2909 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.inst 681285 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.data 368518 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::total 1058207 # number of overall (read+write) accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.047498 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.074252 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.012316 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.291102 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::total 0.089546 # miss rate for ReadReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.936708 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.936708 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.949005 # miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.949005 # miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.tags.occ_blocks::writebacks 8757.920968 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 3.140482 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.100736 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3269.623984 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.data 2111.182929 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 939.755359 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.534541 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000192 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000128 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.199562 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.128856 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.057358 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::total 0.920637 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1198 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1023 23 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13391 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 29 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 1169 # Occupied blocks per task id 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miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 18155.154600 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 27298.605103 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 23562.702529 # average overall mshr miss latency +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.186269 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 12841.121495 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 12641.304348 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 27247.926535 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 14329.890366 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 16489.633445 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 33922.593888 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 33922.593888 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 14198.385511 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14198.385511 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 13595.618508 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13595.618508 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 447000 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 447000 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 29385.354164 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 29385.354164 # average ReadExReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 12841.121495 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 12641.304348 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 27247.926535 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 19396.677396 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 20293.588805 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 12841.121495 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 12641.304348 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 27247.926535 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 19396.677396 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 33922.593888 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 22582.097681 # average overall mshr miss latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1953,69 +2093,69 @@ system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.toL2Bus.trans_dist::ReadReq 1351518 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 1008638 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 4998 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 4998 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::Writeback 197265 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 224398 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 84264 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 42890 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 91097 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 45 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 75 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 123576 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 111434 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1362924 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 1150758 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 8243 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 16496 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 2538421 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 43602948 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 39320783 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 11636 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 21980 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 82957347 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 826396 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 2054321 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 5.357816 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.479358 # Request fanout histogram +system.cpu1.toL2Bus.trans_dist::ReadReq 1051189 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 750269 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 3091 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 3091 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::Writeback 118649 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 33325 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 36225 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 74679 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41637 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 85827 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 49 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 81 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 85544 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 68027 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1054824 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 784590 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 5329 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 9434 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 1854177 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 33743748 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 25394480 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 8020 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 13648 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 59159896 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 572639 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 1437265 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 5.343414 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.474848 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::5 1319253 64.22% 64.22% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::6 735068 35.78% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::5 943688 65.66% 65.66% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::6 493577 34.34% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 2054321 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 864974439 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 1437265 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 595732734 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 89802999 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 80038500 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 1022245510 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 791497760 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 593726174 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 388635637 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 5334000 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 3324000 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 11001001 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 6022000 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 31015 # Transaction distribution -system.iobus.trans_dist::ReadResp 31015 # Transaction distribution -system.iobus.trans_dist::WriteReq 59437 # Transaction distribution -system.iobus.trans_dist::WriteResp 23213 # Transaction distribution +system.iobus.trans_dist::ReadReq 31024 # Transaction distribution +system.iobus.trans_dist::ReadResp 31024 # Transaction distribution +system.iobus.trans_dist::WriteReq 59440 # Transaction distribution +system.iobus.trans_dist::WriteResp 23216 # Transaction distribution system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56642 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56656 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 844 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) @@ -2031,16 +2171,16 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 107950 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72954 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 72954 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 180904 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71586 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 107970 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72958 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 72958 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 180928 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71600 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 446 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -2056,11 +2196,11 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 162833 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321256 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 2321256 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2484089 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 40126000 # Layer occupancy (ticks) +system.iobus.pkt_size_system.bridge.master::total 162850 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321272 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 2321272 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2484122 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 40136000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 90000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -2070,7 +2210,7 @@ system.iobus.reqLayer3.occupancy 12000 # La system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 503000 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 506000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) @@ -2100,52 +2240,52 @@ system.iobus.reqLayer25.occupancy 30680000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 347096127 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 347109131 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 84737000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 84754000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36842563 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 36846525 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 36459 # number of replacements -system.iocache.tags.tagsinuse 14.453181 # Cycle average of tags in use +system.iocache.tags.replacements 36445 # number of replacements +system.iocache.tags.tagsinuse 14.387294 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 36475 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 36461 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 277163175000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 14.453181 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.903324 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.903324 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 287959539000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 14.387294 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.899206 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.899206 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 328293 # Number of tag accesses -system.iocache.tags.data_accesses 328293 # Number of data accesses -system.iocache.ReadReq_misses::realview.ide 253 # number of ReadReq misses -system.iocache.ReadReq_misses::total 253 # number of ReadReq misses +system.iocache.tags.tag_accesses 328311 # Number of tag accesses +system.iocache.tags.data_accesses 328311 # Number of data accesses +system.iocache.ReadReq_misses::realview.ide 255 # number of ReadReq misses +system.iocache.ReadReq_misses::total 255 # number of ReadReq misses system.iocache.WriteInvalidateReq_misses::realview.ide 36224 # number of WriteInvalidateReq misses system.iocache.WriteInvalidateReq_misses::total 36224 # number of WriteInvalidateReq misses -system.iocache.demand_misses::realview.ide 253 # number of demand (read+write) misses -system.iocache.demand_misses::total 253 # number of demand (read+write) misses -system.iocache.overall_misses::realview.ide 253 # number of overall misses -system.iocache.overall_misses::total 253 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 31619377 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 31619377 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::realview.ide 9617084187 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 9617084187 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::realview.ide 31619377 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 31619377 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 31619377 # number of overall miss cycles -system.iocache.overall_miss_latency::total 31619377 # number of overall miss cycles -system.iocache.ReadReq_accesses::realview.ide 253 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 253 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::realview.ide 255 # number of demand (read+write) misses +system.iocache.demand_misses::total 255 # number of demand (read+write) misses +system.iocache.overall_misses::realview.ide 255 # number of overall misses +system.iocache.overall_misses::total 255 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ide 31782377 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 31782377 # number of ReadReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::realview.ide 9599974229 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 9599974229 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::realview.ide 31782377 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 31782377 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 31782377 # number of overall miss cycles +system.iocache.overall_miss_latency::total 31782377 # number of overall miss cycles +system.iocache.ReadReq_accesses::realview.ide 255 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 255 # number of ReadReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::total 36224 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.demand_accesses::realview.ide 253 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 253 # number of demand (read+write) accesses -system.iocache.overall_accesses::realview.ide 253 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 253 # number of overall (read+write) accesses +system.iocache.demand_accesses::realview.ide 255 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 255 # number of demand (read+write) accesses +system.iocache.overall_accesses::realview.ide 255 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 255 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses @@ -2154,40 +2294,40 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 124977.774704 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 124977.774704 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 265489.294032 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 265489.294032 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 124977.774704 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 124977.774704 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 124977.774704 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 124977.774704 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 56586 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 124636.772549 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 124636.772549 # average ReadReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 265016.956410 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 265016.956410 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 124636.772549 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 124636.772549 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 124636.772549 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 124636.772549 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 55555 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 7227 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 7160 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 7.829805 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 7.759078 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 36206 # number of writebacks -system.iocache.writebacks::total 36206 # number of writebacks -system.iocache.ReadReq_mshr_misses::realview.ide 253 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 253 # number of ReadReq MSHR misses +system.iocache.writebacks::writebacks 36190 # number of writebacks +system.iocache.writebacks::total 36190 # number of writebacks +system.iocache.ReadReq_mshr_misses::realview.ide 255 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 255 # number of ReadReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 36224 # number of WriteInvalidateReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::total 36224 # number of WriteInvalidateReq MSHR misses -system.iocache.demand_mshr_misses::realview.ide 253 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 253 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::realview.ide 253 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 253 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 18462377 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 18462377 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 7733310313 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 7733310313 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 18462377 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 18462377 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 18462377 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 18462377 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::realview.ide 255 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 255 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::realview.ide 255 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 255 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ide 18521377 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 18521377 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 7716276279 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 7716276279 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 18521377 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 18521377 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 18521377 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 18521377 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses @@ -2196,517 +2336,491 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 72973.822134 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 72973.822134 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 213485.819153 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 213485.819153 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 72973.822134 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 72973.822134 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 72973.822134 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 72973.822134 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 72632.850980 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 72632.850980 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 213015.577490 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 213015.577490 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 72632.850980 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 72632.850980 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 72632.850980 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 72632.850980 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 132552 # number of replacements -system.l2c.tags.tagsinuse 64217.240538 # Cycle average of tags in use -system.l2c.tags.total_refs 486427 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 197317 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 2.465206 # Average number of references to valid blocks. +system.l2c.tags.replacements 130735 # number of replacements +system.l2c.tags.tagsinuse 63966.604731 # Cycle average of tags in use +system.l2c.tags.total_refs 343053 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 195063 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 1.758678 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 12673.098262 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 4.830088 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.037001 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 1135.719993 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 1432.608438 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 38719.774998 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 2.654088 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 0.007784 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 545.091140 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 913.810052 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 8789.608693 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.193376 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000074 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.000001 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.017330 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.021860 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.590817 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000040 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.008317 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.013944 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.134119 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.979877 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 45108 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 19652 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 175 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 5031 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 39902 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 6 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 175 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 1352 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 18116 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.688293 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.299866 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 6110572 # Number of tag accesses -system.l2c.tags.data_accesses 6110572 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 83 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 80 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 7661 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 21794 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 138574 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 103 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 107 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 6377 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 17292 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 75612 # number of ReadReq hits -system.l2c.ReadReq_hits::total 267683 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 239712 # number of Writeback hits -system.l2c.Writeback_hits::total 239712 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 8881 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 1415 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 10296 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 213 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 148 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 361 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 3683 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 2891 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 6574 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 83 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 80 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 7661 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 25477 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.l2cache.prefetcher 138574 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 103 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 107 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 6377 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 20183 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.l2cache.prefetcher 75612 # number of demand (read+write) hits -system.l2c.demand_hits::total 274257 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 83 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 80 # number of overall hits -system.l2c.overall_hits::cpu0.inst 7661 # number of overall hits -system.l2c.overall_hits::cpu0.data 25477 # number of overall hits -system.l2c.overall_hits::cpu0.l2cache.prefetcher 138574 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 103 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 107 # number of overall hits -system.l2c.overall_hits::cpu1.inst 6377 # number of overall hits -system.l2c.overall_hits::cpu1.data 20183 # number of overall hits -system.l2c.overall_hits::cpu1.l2cache.prefetcher 75612 # number of overall hits -system.l2c.overall_hits::total 274257 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 8 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 3079 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 6828 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 144642 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 4 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.itb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 831 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 1568 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 26632 # number of ReadReq misses -system.l2c.ReadReq_misses::total 183594 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 7063 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 5704 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 12767 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 818 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 1393 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 2211 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 6032 # number of ReadExReq misses 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Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::2 170 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::3 4524 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 28295 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 8 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 11 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 254 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 1895 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 29170 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1022 0.503372 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1023 0.000122 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.478073 # Percentage of cache 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for overall accesses +system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.747950 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.028571 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.172671 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.485963 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.505217 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.556718 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 70678.571429 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 74750 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 73110.874909 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 79675.258376 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 96811.751111 # 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uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 5183212748 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 9260500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 424539000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 6093677248 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 3944737000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 304049000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 4248786000 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 476665000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 9127949748 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 9260500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 728588000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 10342463248 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.078652 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.030769 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.377065 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.163313 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.747950 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.028571 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.172458 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.097558 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.505217 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.538254 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.790063 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.790076 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.790066 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.822126 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.880554 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.857081 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.746737 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.851178 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.788249 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.078652 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.030769 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.377065 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.290938 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.747950 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.028571 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.172458 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.485912 # mshr miss rate for demand accesses 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84364.293409 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 79081.226233 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 71413.583546 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 99256.705231 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 87711.162986 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10136.063146 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10038.865884 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10092.637660 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10162.975550 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10028.996411 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10078.564450 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 66867.098475 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 59414.478284 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 63258.032062 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 62343.750000 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 62460.730674 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 72782.231853 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 103009.293889 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 81259.023827 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10136.837890 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10036.709800 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10112.219988 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10172.500000 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10004.720430 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10069.375699 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 65540.206815 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 60643.193880 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 63438.436062 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 58392.857143 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 74894.283534 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 68574.540280 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 86919.130959 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 60504.907194 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 66273.437355 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 84364.293409 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 79081.226233 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 62016.054204 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 99256.705231 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 86246.639722 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 62343.750000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 62460.730674 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 61824.462414 # average overall mshr miss latency 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+system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 84364.293409 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 79081.226233 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 62016.054204 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 99256.705231 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 86246.639722 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 62460.730674 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 61824.462414 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 103009.293889 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 79396.679517 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -2721,58 +2835,58 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 228161 # Transaction distribution -system.membus.trans_dist::ReadResp 228160 # Transaction distribution -system.membus.trans_dist::WriteReq 31188 # Transaction distribution -system.membus.trans_dist::WriteResp 31188 # Transaction distribution -system.membus.trans_dist::Writeback 135887 # Transaction distribution +system.membus.trans_dist::ReadReq 215303 # Transaction distribution +system.membus.trans_dist::ReadResp 215303 # Transaction distribution +system.membus.trans_dist::WriteReq 30982 # Transaction distribution +system.membus.trans_dist::WriteResp 30982 # Transaction distribution +system.membus.trans_dist::Writeback 135225 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.membus.trans_dist::UpgradeReq 85485 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 41282 # Transaction distribution -system.membus.trans_dist::UpgradeResp 15173 # Transaction distribution +system.membus.trans_dist::UpgradeReq 76008 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 40410 # Transaction distribution +system.membus.trans_dist::UpgradeResp 13867 # Transaction distribution system.membus.trans_dist::SCUpgradeFailReq 5 # Transaction distribution -system.membus.trans_dist::ReadExReq 28446 # Transaction distribution -system.membus.trans_dist::ReadExResp 11501 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107950 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::ReadExReq 40350 # Transaction distribution +system.membus.trans_dist::ReadExResp 19836 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107970 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14612 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 676793 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 799389 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108922 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 108922 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 908311 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162833 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13762 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 659440 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 781206 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108908 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 108908 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 890114 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162850 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 29224 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18898536 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 19090661 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4636480 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 4636480 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 23727141 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 129157 # Total snoops (count) -system.membus.snoop_fanout::samples 511174 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27524 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18582632 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 18773074 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4635456 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 4635456 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 23408530 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 123675 # Total snoops (count) +system.membus.snoop_fanout::samples 499419 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 511174 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 499419 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 511174 # Request fanout histogram -system.membus.reqLayer0.occupancy 88144997 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 499419 # Request fanout histogram +system.membus.reqLayer0.occupancy 88165000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 18500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 12118496 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 11453500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 1838586997 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 1828859499 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 1967573382 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1931425684 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.1 # Layer utilization (%) -system.membus.respLayer3.occupancy 38564437 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 38544475 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -2805,44 +2919,44 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.trans_dist::ReadReq 630354 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 630338 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 31188 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 31188 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 239712 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 95586 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 41643 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 137229 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 75 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 75 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 39856 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 39856 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1145062 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 504022 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 1649084 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 33792786 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 11864019 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 45656805 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 304478 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 1039135 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.035103 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.184041 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 482729 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 482714 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 30982 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 30982 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 227719 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 36225 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 79027 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 40738 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 119765 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 81 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 81 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 51496 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 51496 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1065854 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 282098 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 1347952 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 31837086 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 4944756 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 36781842 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 286323 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 873908 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.041744 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.200003 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 1002658 96.49% 96.49% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 36477 3.51% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 837428 95.83% 95.83% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 36480 4.17% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 1039135 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 1515175521 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 873908 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 1446151615 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 1071000 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 1080000 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1922628953 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 1735034184 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1047459467 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 618323353 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt index 5265a0ac0..b3648bdab 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt @@ -1,120 +1,120 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.902845 # Number of seconds simulated -sim_ticks 2902845442000 # Number of ticks simulated -final_tick 2902845442000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.902862 # Number of seconds simulated +sim_ticks 2902861767000 # Number of ticks simulated +final_tick 2902861767000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 666753 # Simulator instruction rate (inst/s) -host_op_rate 803907 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 17201244826 # Simulator tick rate (ticks/s) -host_mem_usage 558784 # Number of bytes of host memory used -host_seconds 168.76 # Real time elapsed on the host -sim_insts 112519801 # Number of instructions simulated -sim_ops 135665611 # Number of ops (including micro ops) simulated +host_inst_rate 747193 # Simulator instruction rate (inst/s) +host_op_rate 900893 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 19275657141 # Simulator tick rate (ticks/s) +host_mem_usage 615228 # Number of bytes of host memory used +host_seconds 150.60 # Real time elapsed on the host +sim_insts 112525269 # Number of instructions simulated +sim_ops 135672104 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.dtb.walker 448 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1190500 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1191332 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 8985828 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 10177864 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1190500 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1190500 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7575744 # Number of bytes written to this memory +system.physmem.bytes_read::total 10178696 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1191332 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1191332 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7576000 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory -system.physmem.bytes_written::total 7593268 # Number of bytes written to this memory +system.physmem.bytes_written::total 7593524 # Number of bytes written to this memory system.physmem.num_reads::cpu.dtb.walker 7 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 27055 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 27068 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 140923 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 168002 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 118371 # Number of write requests responded to by this memory +system.physmem.num_reads::total 168015 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 118375 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory -system.physmem.num_writes::total 122752 # Number of write requests responded to by this memory +system.physmem.num_writes::total 122756 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.dtb.walker 154 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 44 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 410115 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3095524 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 410399 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3095507 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 331 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3506168 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 410115 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 410115 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2609765 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3506435 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 410399 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 410399 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2609838 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 6037 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2615802 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2609765 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 2615875 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2609838 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 154 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 44 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 410115 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3101561 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 410399 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3101543 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 331 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6121970 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 168002 # Number of read requests accepted -system.physmem.writeReqs 158976 # Number of write requests accepted -system.physmem.readBursts 168002 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 158976 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10744064 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 8064 # Total number of bytes read from write queue -system.physmem.bytesWritten 9803776 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10177864 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 9911604 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 126 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 5765 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 4503 # Number of requests that are neither read nor write +system.physmem.bw_total::total 6122310 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 168015 # Number of read requests accepted +system.physmem.writeReqs 158980 # Number of write requests accepted +system.physmem.readBursts 168015 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 158980 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 10745280 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 7680 # Total number of bytes read from write queue +system.physmem.bytesWritten 9814400 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10178696 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 9911860 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 120 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 5603 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 4500 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 9689 # Per bank write bursts -system.physmem.perBankRdBursts::1 9233 # Per bank write bursts -system.physmem.perBankRdBursts::2 10196 # Per bank write bursts -system.physmem.perBankRdBursts::3 10261 # Per bank write bursts +system.physmem.perBankRdBursts::1 9230 # Per bank write bursts +system.physmem.perBankRdBursts::2 10198 # Per bank write bursts +system.physmem.perBankRdBursts::3 10267 # Per bank write bursts system.physmem.perBankRdBursts::4 18984 # Per bank write bursts -system.physmem.perBankRdBursts::5 10217 # Per bank write bursts -system.physmem.perBankRdBursts::6 10550 # Per bank write bursts -system.physmem.perBankRdBursts::7 10349 # Per bank write bursts -system.physmem.perBankRdBursts::8 9691 # Per bank write bursts +system.physmem.perBankRdBursts::5 10226 # Per bank write bursts +system.physmem.perBankRdBursts::6 10551 # Per bank write bursts +system.physmem.perBankRdBursts::7 10350 # Per bank write bursts +system.physmem.perBankRdBursts::8 9702 # Per bank write bursts system.physmem.perBankRdBursts::9 9930 # Per bank write bursts -system.physmem.perBankRdBursts::10 9906 # Per bank write bursts -system.physmem.perBankRdBursts::11 8846 # Per bank write bursts -system.physmem.perBankRdBursts::12 9937 # Per bank write bursts -system.physmem.perBankRdBursts::13 10409 # Per bank write bursts -system.physmem.perBankRdBursts::14 9928 # Per bank write bursts +system.physmem.perBankRdBursts::10 9908 # Per bank write bursts +system.physmem.perBankRdBursts::11 8848 # Per bank write bursts +system.physmem.perBankRdBursts::12 9929 # Per bank write bursts +system.physmem.perBankRdBursts::13 10408 # Per bank write bursts +system.physmem.perBankRdBursts::14 9925 # Per bank write bursts system.physmem.perBankRdBursts::15 9750 # Per bank write bursts -system.physmem.perBankWrBursts::0 9383 # Per bank write bursts -system.physmem.perBankWrBursts::1 8873 # Per bank write bursts -system.physmem.perBankWrBursts::2 10202 # Per bank write bursts -system.physmem.perBankWrBursts::3 10003 # Per bank write bursts -system.physmem.perBankWrBursts::4 9293 # Per bank write bursts -system.physmem.perBankWrBursts::5 9372 # Per bank write bursts -system.physmem.perBankWrBursts::6 9902 # Per bank write bursts -system.physmem.perBankWrBursts::7 9747 # Per bank write bursts -system.physmem.perBankWrBursts::8 9662 # Per bank write bursts -system.physmem.perBankWrBursts::9 9936 # Per bank write bursts -system.physmem.perBankWrBursts::10 9764 # Per bank write bursts -system.physmem.perBankWrBursts::11 9057 # Per bank write bursts -system.physmem.perBankWrBursts::12 9756 # Per bank write bursts -system.physmem.perBankWrBursts::13 9847 # Per bank write bursts -system.physmem.perBankWrBursts::14 9332 # Per bank write bursts -system.physmem.perBankWrBursts::15 9055 # Per bank write bursts +system.physmem.perBankWrBursts::0 9389 # Per bank write bursts +system.physmem.perBankWrBursts::1 8975 # Per bank write bursts +system.physmem.perBankWrBursts::2 10251 # Per bank write bursts +system.physmem.perBankWrBursts::3 9953 # Per bank write bursts +system.physmem.perBankWrBursts::4 9418 # Per bank write bursts +system.physmem.perBankWrBursts::5 9499 # Per bank write bursts +system.physmem.perBankWrBursts::6 9770 # Per bank write bursts +system.physmem.perBankWrBursts::7 9764 # Per bank write bursts +system.physmem.perBankWrBursts::8 9682 # Per bank write bursts +system.physmem.perBankWrBursts::9 9836 # Per bank write bursts +system.physmem.perBankWrBursts::10 9791 # Per bank write bursts +system.physmem.perBankWrBursts::11 9091 # Per bank write bursts +system.physmem.perBankWrBursts::12 9681 # Per bank write bursts +system.physmem.perBankWrBursts::13 9852 # Per bank write bursts +system.physmem.perBankWrBursts::14 9372 # Per bank write bursts +system.physmem.perBankWrBursts::15 9026 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2902845065500 # Total gap between requests +system.physmem.totGap 2902861390500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 9558 # Read request sizes (log2) system.physmem.readPktSize::3 14 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 158430 # Read request sizes (log2) +system.physmem.readPktSize::6 158443 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4381 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 154595 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 167074 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 546 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 244 # What read queue length does an incoming req see +system.physmem.writePktSize::6 154599 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 167093 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 544 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 246 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see @@ -159,114 +159,135 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2275 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4010 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 7794 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 8553 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 8920 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 9728 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 10123 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 10886 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 10725 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 11224 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 10377 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 9848 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 8741 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8288 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7158 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6857 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6734 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6646 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 405 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 375 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 282 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 258 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 268 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 258 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 239 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 224 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 214 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 188 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 176 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 166 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 149 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 135 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 130 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 96 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 82 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 62 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 48 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 34 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 20 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2326 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 4056 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 7902 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 8734 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 8985 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 9766 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 10233 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 10902 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 10695 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 11219 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 10360 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 9893 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 8867 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8350 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 7190 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6866 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6730 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6660 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 386 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 329 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 285 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 251 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 241 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 234 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 197 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 206 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 175 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 181 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 158 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 144 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 128 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 114 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 108 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 101 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 91 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 74 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 62 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 57 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 45 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 24 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::60 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::61 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 60629 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 338.910027 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 195.312314 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 353.501529 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 21458 35.39% 35.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 14532 23.97% 59.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5550 9.15% 68.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3471 5.72% 74.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2318 3.82% 78.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1576 2.60% 80.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1018 1.68% 82.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1077 1.78% 84.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 9629 15.88% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 60629 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6199 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 27.078561 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 543.579220 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 6197 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 60962 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 337.252977 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 194.461800 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 352.629111 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 21587 35.41% 35.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 14795 24.27% 59.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5550 9.10% 68.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3419 5.61% 74.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2349 3.85% 78.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1576 2.59% 80.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1011 1.66% 82.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1092 1.79% 84.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 9583 15.72% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 60962 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6214 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 27.016254 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 542.923852 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6212 99.97% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-4095 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-43007 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6199 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6199 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 24.711082 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 20.355367 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 23.633562 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 5127 82.71% 82.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 245 3.95% 86.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 162 2.61% 89.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 57 0.92% 90.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 142 2.29% 92.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 31 0.50% 92.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 44 0.71% 93.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 53 0.85% 94.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 77 1.24% 95.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 20 0.32% 96.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 101 1.63% 97.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 12 0.19% 97.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-119 30 0.48% 98.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-127 13 0.21% 98.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 38 0.61% 99.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-143 11 0.18% 99.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-151 15 0.24% 99.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-159 2 0.03% 99.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-167 3 0.05% 99.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 2 0.03% 99.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 3 0.05% 99.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-199 2 0.03% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-207 1 0.02% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-215 2 0.03% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-223 2 0.03% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-231 3 0.05% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::272-279 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6199 # Writes before turning the bus around for reads -system.physmem.totQLat 1496514000 # Total ticks spent queuing -system.physmem.totMemAccLat 4644189000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 839380000 # Total ticks spent in databus transfers -system.physmem.avgQLat 8914.40 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 6214 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6214 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 24.678146 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 20.366342 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 23.738225 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 5089 81.90% 81.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 32 0.51% 82.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 24 0.39% 82.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 212 3.41% 86.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 128 2.06% 88.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 65 1.05% 89.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 41 0.66% 89.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 30 0.48% 90.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 138 2.22% 92.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 16 0.26% 92.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 13 0.21% 93.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 16 0.26% 93.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 29 0.47% 93.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 17 0.27% 94.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 11 0.18% 94.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 29 0.47% 94.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 66 1.06% 95.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 8 0.13% 95.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 3 0.05% 96.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 17 0.27% 96.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 91 1.46% 97.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 1 0.02% 97.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 15 0.24% 98.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 2 0.03% 98.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 8 0.13% 98.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 6 0.10% 98.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 11 0.18% 98.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 1 0.02% 98.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 39 0.63% 99.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 7 0.11% 99.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 2 0.03% 99.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 4 0.06% 99.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 9 0.14% 99.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 3 0.05% 99.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 1 0.02% 99.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 5 0.08% 99.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 2 0.03% 99.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 3 0.05% 99.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 5 0.08% 99.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::180-183 1 0.02% 99.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::188-191 3 0.05% 99.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::196-199 1 0.02% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-211 1 0.02% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::220-223 4 0.06% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-227 2 0.03% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::228-231 1 0.02% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::232-235 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::252-255 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6214 # Writes before turning the bus around for reads +system.physmem.totQLat 1487834250 # Total ticks spent queuing +system.physmem.totMemAccLat 4635865500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 839475000 # Total ticks spent in databus transfers +system.physmem.avgQLat 8861.69 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 27664.40 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 27611.69 # Average memory access latency per DRAM burst system.physmem.avgRdBW 3.70 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 3.38 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 3.51 # Average system read bandwidth in MiByte/s @@ -276,36 +297,41 @@ system.physmem.busUtil 0.06 # Da system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 27.52 # Average write queue length when enqueuing -system.physmem.readRowHits 138272 # Number of row buffer hits during reads -system.physmem.writeRowHits 122158 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.37 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 79.73 # Row buffer hit rate for writes -system.physmem.avgGap 8877799.32 # Average gap between requests -system.physmem.pageHitRate 81.11 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 2755332461750 # Time in different power states -system.physmem.memoryStateTime::REF 96932160000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 50580729750 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 234216360 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 224138880 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 127796625 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 122298000 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 697936200 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 611488800 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 497502000 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 495130320 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 189599304960 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 189599304960 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 86744243025 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 85632450615 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 1665611854500 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 1666587111000 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 1943512853670 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 1943271922575 # Total energy per rank (pJ) -system.physmem.averagePower::0 669.521448 # Core power per rank (mW) -system.physmem.averagePower::1 669.438449 # Core power per rank (mW) +system.physmem.avgWrQLen 25.07 # Average write queue length when enqueuing +system.physmem.readRowHits 138089 # Number of row buffer hits during reads +system.physmem.writeRowHits 122193 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.25 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 79.67 # Row buffer hit rate for writes +system.physmem.avgGap 8877387.70 # Average gap between requests +system.physmem.pageHitRate 81.02 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 235320120 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 128398875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 698061000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 499083120 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 189600322080 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 86740865775 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1665624160500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1943526211470 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.522458 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2770750790000 # Time in different power states +system.physmem_0.memoryStateTime::REF 96932680000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 35170942500 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 225552600 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 123069375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 611512200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 494624880 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 189600322080 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 85548905145 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1666669740000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1943273726280 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.435479 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2772511956000 # Time in different power states +system.physmem_1.memoryStateTime::REF 96932680000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 33417040500 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory @@ -325,6 +351,14 @@ system.cf0.dma_write_full_pages 540 # Nu system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -346,11 +380,41 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 9552 # Table walker walks requested +system.cpu.dtb.walker.walksShort 9552 # Table walker walks initiated with short descriptors +system.cpu.dtb.walker.walksShortTerminationLevel::Level1 1261 # Level at which table walker walks with short descriptors terminate +system.cpu.dtb.walker.walksShortTerminationLevel::Level2 8291 # Level at which table walker walks with short descriptors terminate +system.cpu.dtb.walker.walkWaitTime::samples 9552 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0 9552 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::total 9552 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkCompletionTime::samples 7388 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 9945.756632 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 7345.780525 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 7322.338006 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::0-16383 5745 77.76% 77.76% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::16384-32767 1639 22.18% 99.95% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::65536-81919 2 0.03% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::98304-114687 1 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::147456-163839 1 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::total 7388 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walksPending::samples 809108000 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::0 809108000 100.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::total 809108000 # Table walker pending requests distribution +system.cpu.dtb.walker.walkPageSizes::4K 6174 83.57% 83.57% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::1M 1214 16.43% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 7388 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 9552 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 9552 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7388 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7388 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 16940 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 24536392 # DTB read hits -system.cpu.dtb.read_misses 8144 # DTB read misses -system.cpu.dtb.write_hits 19617454 # DTB write hits +system.cpu.dtb.read_hits 24537663 # DTB read hits +system.cpu.dtb.read_misses 8142 # DTB read misses +system.cpu.dtb.write_hits 19618927 # DTB write hits system.cpu.dtb.write_misses 1410 # DTB write misses system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA @@ -358,15 +422,23 @@ system.cpu.dtb.flush_tlb_mva_asid 0 # Nu system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu.dtb.flush_entries 4273 # Number of entries that have been flushed from TLB system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 1630 # Number of TLB faults due to prefetch +system.cpu.dtb.prefetch_faults 1664 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 24544536 # DTB read accesses -system.cpu.dtb.write_accesses 19618864 # DTB write accesses +system.cpu.dtb.read_accesses 24545805 # DTB read accesses +system.cpu.dtb.write_accesses 19620337 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 44153846 # DTB hits -system.cpu.dtb.misses 9554 # DTB misses -system.cpu.dtb.accesses 44163400 # DTB accesses +system.cpu.dtb.hits 44156590 # DTB hits +system.cpu.dtb.misses 9552 # DTB misses +system.cpu.dtb.accesses 44166142 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -388,7 +460,37 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.inst_hits 115618887 # ITB inst hits +system.cpu.itb.walker.walks 4762 # Table walker walks requested +system.cpu.itb.walker.walksShort 4762 # Table walker walks initiated with short descriptors +system.cpu.itb.walker.walksShortTerminationLevel::Level1 309 # Level at which table walker walks with short descriptors terminate +system.cpu.itb.walker.walksShortTerminationLevel::Level2 4453 # Level at which table walker walks with short descriptors terminate +system.cpu.itb.walker.walkWaitTime::samples 4762 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0 4762 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::total 4762 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkCompletionTime::samples 3107 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::mean 9893.949147 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::gmean 7210.941913 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::stdev 7351.443657 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::0-8191 1400 45.06% 45.06% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::8192-16383 1004 32.31% 77.37% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::16384-24575 701 22.56% 99.94% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::73728-81919 1 0.03% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::81920-90111 1 0.03% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::total 3107 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walksPending::samples 808810000 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::0 808810000 100.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::total 808810000 # Table walker pending requests distribution +system.cpu.itb.walker.walkPageSizes::4K 2798 90.05% 90.05% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::1M 309 9.95% 100.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 3107 # Table walker page sizes translated +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 4762 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 4762 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3107 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 3107 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 7869 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 115624412 # ITB inst hits system.cpu.itb.inst_misses 4762 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses @@ -405,38 +507,38 @@ system.cpu.itb.domain_faults 0 # Nu system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 115623649 # ITB inst accesses -system.cpu.itb.hits 115618887 # DTB hits +system.cpu.itb.inst_accesses 115629174 # ITB inst accesses +system.cpu.itb.hits 115624412 # DTB hits system.cpu.itb.misses 4762 # DTB misses -system.cpu.itb.accesses 115623649 # DTB accesses -system.cpu.numCycles 5805690884 # number of cpu cycles simulated +system.cpu.itb.accesses 115629174 # DTB accesses +system.cpu.numCycles 5805723534 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 112519801 # Number of instructions committed -system.cpu.committedOps 135665611 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 119963928 # Number of integer alu accesses +system.cpu.committedInsts 112525269 # Number of instructions committed +system.cpu.committedOps 135672104 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 119969678 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 11290 # Number of float alu accesses -system.cpu.num_func_calls 9899743 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 15237612 # number of instructions that are conditional controls -system.cpu.num_int_insts 119963928 # number of integer instructions +system.cpu.num_func_calls 9899985 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 15238216 # number of instructions that are conditional controls +system.cpu.num_int_insts 119969678 # number of integer instructions system.cpu.num_fp_insts 11290 # number of float instructions -system.cpu.num_int_register_reads 218192496 # number of times the integer registers were read -system.cpu.num_int_register_writes 82697523 # number of times the integer registers were written +system.cpu.num_int_register_reads 218203287 # number of times the integer registers were read +system.cpu.num_int_register_writes 82701548 # number of times the integer registers were written system.cpu.num_fp_register_reads 8578 # number of times the floating registers were read system.cpu.num_fp_register_writes 2716 # number of times the floating registers were written -system.cpu.num_cc_register_reads 490031044 # number of times the CC registers were read -system.cpu.num_cc_register_writes 51919223 # number of times the CC registers were written -system.cpu.num_mem_refs 45435185 # number of memory refs -system.cpu.num_load_insts 24859277 # Number of load instructions -system.cpu.num_store_insts 20575908 # Number of store instructions -system.cpu.num_idle_cycles 5386811452.570145 # Number of idle cycles -system.cpu.num_busy_cycles 418879431.429856 # Number of busy cycles -system.cpu.not_idle_fraction 0.072150 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.927850 # Percentage of idle cycles -system.cpu.Branches 25931479 # Number of branches fetched +system.cpu.num_cc_register_reads 490054820 # number of times the CC registers were read +system.cpu.num_cc_register_writes 51921339 # number of times the CC registers were written +system.cpu.num_mem_refs 45438019 # number of memory refs +system.cpu.num_load_insts 24860597 # Number of load instructions +system.cpu.num_store_insts 20577422 # Number of store instructions +system.cpu.num_idle_cycles 5386825418.146145 # Number of idle cycles +system.cpu.num_busy_cycles 418898115.853856 # Number of busy cycles +system.cpu.not_idle_fraction 0.072153 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.927847 # Percentage of idle cycles +system.cpu.Branches 25932360 # Number of branches fetched system.cpu.op_class::No_OpClass 2337 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 93227451 67.17% 67.17% # Class of executed instruction -system.cpu.op_class::IntMult 114534 0.08% 67.26% # Class of executed instruction +system.cpu.op_class::IntAlu 93231199 67.17% 67.17% # Class of executed instruction +system.cpu.op_class::IntMult 114517 0.08% 67.26% # Class of executed instruction system.cpu.op_class::IntDiv 0 0.00% 67.26% # Class of executed instruction system.cpu.op_class::FloatAdd 0 0.00% 67.26% # Class of executed instruction system.cpu.op_class::FloatCmp 0 0.00% 67.26% # Class of executed instruction @@ -460,24 +562,24 @@ system.cpu.op_class::SimdFloatAlu 0 0.00% 67.26% # Cl system.cpu.op_class::SimdFloatCmp 0 0.00% 67.26% # Class of executed instruction system.cpu.op_class::SimdFloatCvt 0 0.00% 67.26% # Class of executed instruction system.cpu.op_class::SimdFloatDiv 0 0.00% 67.26% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 8511 0.01% 67.26% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 8515 0.01% 67.26% # Class of executed instruction system.cpu.op_class::SimdFloatMult 0 0.00% 67.26% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.26% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.26% # Class of executed instruction -system.cpu.op_class::MemRead 24859277 17.91% 85.17% # Class of executed instruction -system.cpu.op_class::MemWrite 20575908 14.83% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 24860597 17.91% 85.17% # Class of executed instruction +system.cpu.op_class::MemWrite 20577422 14.83% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 138788018 # Class of executed instruction +system.cpu.op_class::total 138794587 # Class of executed instruction system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 3037 # number of quiesce instructions executed -system.cpu.dcache.tags.replacements 823273 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.850546 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 43258722 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 823785 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 52.512151 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 823321 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.850573 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 43261398 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 823833 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 52.512339 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 876905250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.850546 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 511.850573 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999708 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999708 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id @@ -486,168 +588,168 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::1 368 system.cpu.dcache.tags.age_task_id_blocks_1024::2 82 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 177222055 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 177222055 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 23125535 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 23125535 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 18834160 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 18834160 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 392158 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 392158 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 443620 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 443620 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 460509 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 460509 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 41959695 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 41959695 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 42351853 # number of overall hits -system.cpu.dcache.overall_hits::total 42351853 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 402606 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 402606 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 299098 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 299098 # number of WriteReq misses +system.cpu.dcache.tags.tag_accesses 177233078 # Number of tag accesses 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uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 10221080250 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017088 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017088 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015627 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015627 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.228872 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.228872 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.018202 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.018202 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000004 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000004 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016433 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.016433 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.018949 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.018949 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12679.106028 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12679.106028 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36790.790132 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36790.790132 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12086.469523 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12086.469523 # average SoftPFReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11761.833097 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11761.833097 # average LoadLockedReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12679.667797 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12679.667797 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36769.808106 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36769.808106 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12058.878321 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12058.878321 # average SoftPFReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11781.364118 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11781.364118 # average LoadLockedReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 73000 # average StoreCondReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 73000 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22965.920563 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 22965.920563 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21409.703280 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 21409.703280 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22954.210069 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 22954.210069 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21395.768805 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 21395.768805 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -655,13 +757,13 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 1700967 # number of replacements -system.cpu.icache.tags.tagsinuse 510.782035 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 113917402 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1701479 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 66.951988 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 1701491 # number of replacements +system.cpu.icache.tags.tagsinuse 510.782044 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 113922403 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1702003 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 66.934314 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 25181626250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.782035 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 510.782044 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.997621 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.997621 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id @@ -670,44 +772,44 @@ system.cpu.icache.tags.age_task_id_blocks_1024::1 195 system.cpu.icache.tags.age_task_id_blocks_1024::2 264 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 117320372 # Number of tag accesses -system.cpu.icache.tags.data_accesses 117320372 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 113917402 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 113917402 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 113917402 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 113917402 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 113917402 # number of overall hits -system.cpu.icache.overall_hits::total 113917402 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1701485 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1701485 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1701485 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1701485 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1701485 # number of overall misses -system.cpu.icache.overall_misses::total 1701485 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 23258305750 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 23258305750 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 23258305750 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 23258305750 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 23258305750 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 23258305750 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 115618887 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 115618887 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 115618887 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 115618887 # number of demand (read+write) accesses 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latency -system.cpu.icache.demand_avg_miss_latency::total 13669.415687 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13669.415687 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13669.415687 # average overall miss latency +system.cpu.icache.tags.tag_accesses 117326421 # Number of tag accesses +system.cpu.icache.tags.data_accesses 117326421 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 113922403 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 113922403 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 113922403 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 113922403 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 113922403 # number of overall hits +system.cpu.icache.overall_hits::total 113922403 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1702009 # number of ReadReq misses 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accesses +system.cpu.icache.overall_miss_rate::total 0.014720 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13671.050212 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13671.050212 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13671.050212 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13671.050212 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13671.050212 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13671.050212 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -716,196 +818,196 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan 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-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19848767250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 19848767250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19848767250 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 19848767250 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1702009 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1702009 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1702009 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1702009 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1702009 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1702009 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19857660500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 19857660500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19857660500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 19857660500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19857660500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 19857660500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 597905000 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 597905000 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 597905000 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::total 597905000 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.014716 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.014716 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014716 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.014716 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014716 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.014716 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11665.555236 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11665.555236 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11665.555236 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11665.555236 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11665.555236 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11665.555236 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.014720 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.014720 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014720 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.014720 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014720 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.014720 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11667.188893 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11667.188893 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11667.188893 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11667.188893 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11667.188893 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11667.188893 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 88871 # number of replacements -system.cpu.l2cache.tags.tagsinuse 64932.261061 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 2762491 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 154137 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 17.922309 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 88884 # number of replacements +system.cpu.l2cache.tags.tagsinuse 64931.599128 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 2763158 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 154151 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 17.925009 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was 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+system.cpu.l2cache.overall_avg_miss_latency::total 69903.158728 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -914,50 +1016,50 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 82181 # number of writebacks -system.cpu.l2cache.writebacks::total 82181 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 82185 # number of writebacks +system.cpu.l2cache.writebacks::total 82185 # number of writebacks system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 7 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 18040 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 12191 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 30240 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2715 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 2715 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 18053 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 12189 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 30251 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2710 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 2710 # number of UpgradeReq MSHR misses system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 2 # number of SCUpgradeReq MSHR misses system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 130240 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 130240 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 130244 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 130244 # number of ReadExReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 7 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 18040 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 142431 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 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miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 775288750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1866093500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 27282710 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 27282710 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 120000 # number of SCUpgradeReq MSHR miss cycles system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 120000 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7353282038 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7353282038 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 467000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7345006540 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7345006540 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 408750 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 125000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1087188750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8131188288 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 9218969038 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 467000 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1090271000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8120295290 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 9211100040 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 408750 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 125000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1087188750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8131188288 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 9218969038 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1090271000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8120295290 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 9211100040 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 474215000 # number of ReadReq MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5385925500 # number of ReadReq MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 5860140500 # number of ReadReq MSHR uncacheable cycles @@ -966,48 +1068,48 @@ system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4098165500 system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 474215000 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 9484091000 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_latency::total 9958306000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.001003 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.001001 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000546 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.010603 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.023113 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.013503 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.991600 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.991600 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.010607 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.023103 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.013504 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.991584 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.991584 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.439466 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.439466 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.001003 # mshr miss rate for demand accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.439589 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.439589 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.001001 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000546 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.010603 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.172890 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.063283 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.001003 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.010607 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.172883 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.063274 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.001001 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000546 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010603 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.172890 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.063283 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 66714.285714 # average ReadReq mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010607 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.172883 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.063274 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 58392.857143 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 62500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60265.451774 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63809.880240 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61695.998677 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10058.458564 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10058.458564 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60392.787902 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63605.607515 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61687.002083 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10067.420664 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10067.420664 # average UpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 60000 # average SCUpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 60000 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56459.475107 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56459.475107 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 66714.285714 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56394.202727 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56394.202727 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 58392.857143 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60265.451774 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57088.613350 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57446.217834 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 66714.285714 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60392.787902 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57011.333680 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57391.819309 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 58392.857143 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60265.451774 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57088.613350 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57446.217834 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60392.787902 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57011.333680 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57391.819309 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1017,54 +1119,54 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 2296418 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2296403 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 2297061 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2297046 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 27618 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 27618 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 686473 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 686487 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2738 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2733 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2740 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 296360 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 296360 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3420989 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2457362 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::UpgradeResp 2735 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 296286 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 296286 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3422037 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2457460 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 12875 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 24821 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 5916047 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 108929528 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96856201 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 24836 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 5917208 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 108963064 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96860105 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 14640 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 27904 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 205828273 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 53126 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 3278039 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5.011122 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.104872 # Request fanout histogram +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 27972 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 205865781 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 53107 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 3278617 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 5.011120 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.104863 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 3241581 98.89% 98.89% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 3242159 98.89% 98.89% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::6 36458 1.11% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 3278039 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 2354969500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 3278617 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 2355272500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 328500 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 2566643750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 2567431500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1312602003 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1312657000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer2.occupancy 9215000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 17845000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 17843250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.trans_dist::ReadReq 30195 # Transaction distribution system.iobus.trans_dist::ReadResp 30195 # Transaction distribution @@ -1161,23 +1263,23 @@ system.iobus.reqLayer25.occupancy 30680000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 347056142 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 347060139 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 82736000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36804505 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 36804507 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 36424 # number of replacements -system.iocache.tags.tagsinuse 1.134557 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.134613 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36440 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 298397320000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 1.134557 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.070910 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.070910 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 298400039000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 1.134613 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.070913 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.070913 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -1193,8 +1295,8 @@ system.iocache.overall_misses::realview.ide 234 # system.iocache.overall_misses::total 234 # number of overall misses system.iocache.ReadReq_miss_latency::realview.ide 28034377 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 28034377 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::realview.ide 9588161260 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 9588161260 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::realview.ide 9587408255 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 9587408255 # number of WriteInvalidateReq miss cycles system.iocache.demand_miss_latency::realview.ide 28034377 # number of demand (read+write) miss cycles system.iocache.demand_miss_latency::total 28034377 # number of demand (read+write) miss cycles system.iocache.overall_miss_latency::realview.ide 28034377 # number of overall miss cycles @@ -1217,17 +1319,17 @@ system.iocache.overall_miss_rate::realview.ide 1 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::realview.ide 119805.029915 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total 119805.029915 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 264690.847504 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 264690.847504 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 264670.060043 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 264670.060043 # average WriteInvalidateReq miss latency system.iocache.demand_avg_miss_latency::realview.ide 119805.029915 # average overall miss latency system.iocache.demand_avg_miss_latency::total 119805.029915 # average overall miss latency system.iocache.overall_avg_miss_latency::realview.ide 119805.029915 # average overall miss latency system.iocache.overall_avg_miss_latency::total 119805.029915 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 55275 # number of cycles access was blocked +system.iocache.blocked_cycles::no_mshrs 55358 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 7147 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 7146 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 7.734014 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 7.746711 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -1243,8 +1345,8 @@ system.iocache.overall_mshr_misses::realview.ide 234 system.iocache.overall_mshr_misses::total 234 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::realview.ide 15865377 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::total 15865377 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 7704503270 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 7704503270 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 7703746269 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 7703746269 # number of WriteInvalidateReq MSHR miss cycles system.iocache.demand_mshr_miss_latency::realview.ide 15865377 # number of demand (read+write) MSHR miss cycles system.iocache.demand_mshr_miss_latency::total 15865377 # number of demand (read+write) MSHR miss cycles system.iocache.overall_mshr_miss_latency::realview.ide 15865377 # number of overall MSHR miss cycles @@ -1259,64 +1361,64 @@ system.iocache.overall_mshr_miss_rate::realview.ide 1 system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 67800.756410 # average ReadReq mshr miss latency system.iocache.ReadReq_avg_mshr_miss_latency::total 67800.756410 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 212690.571720 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 212690.571720 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 212669.673945 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 212669.673945 # average WriteInvalidateReq mshr miss latency system.iocache.demand_avg_mshr_miss_latency::realview.ide 67800.756410 # average overall mshr miss latency system.iocache.demand_avg_mshr_miss_latency::total 67800.756410 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::realview.ide 67800.756410 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::total 67800.756410 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 70650 # Transaction distribution -system.membus.trans_dist::ReadResp 70650 # Transaction distribution +system.membus.trans_dist::ReadReq 70661 # Transaction distribution +system.membus.trans_dist::ReadResp 70661 # Transaction distribution system.membus.trans_dist::WriteReq 27618 # Transaction distribution system.membus.trans_dist::WriteResp 27618 # Transaction distribution -system.membus.trans_dist::Writeback 118371 # Transaction distribution +system.membus.trans_dist::Writeback 118375 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4503 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4500 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4505 # Transaction distribution -system.membus.trans_dist::ReadExReq 128452 # Transaction distribution -system.membus.trans_dist::ReadExResp 128452 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4502 # Transaction distribution +system.membus.trans_dist::ReadExReq 128454 # Transaction distribution +system.membus.trans_dist::ReadExResp 128454 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105550 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2122 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 436202 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 543884 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 436226 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 543908 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108887 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 108887 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 652771 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 652795 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159197 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4244 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15454012 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 15617473 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15455100 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 15618561 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4635456 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 4635456 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 20252929 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 20254017 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 498 # Total snoops (count) -system.membus.snoop_fanout::samples 318026 # Request fanout histogram +system.membus.snoop_fanout::samples 318040 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 318026 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 318040 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 318026 # Request fanout histogram +system.membus.snoop_fanout::total 318040 # Request fanout histogram system.membus.reqLayer0.occupancy 86773500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 5000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1756500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1758500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 1589715500 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 1589750000 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 1594842247 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1594947750 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.1 # Layer utilization (%) -system.membus.respLayer3.occupancy 38335495 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 38337493 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt index b2b55eb3a..f0c87683a 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.783867 # Nu sim_ticks 2783867165000 # Number of ticks simulated final_tick 2783867165000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1108011 # Simulator instruction rate (inst/s) -host_op_rate 1348825 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 21604583679 # Simulator tick rate (ticks/s) -host_mem_usage 560868 # Number of bytes of host memory used -host_seconds 128.86 # Real time elapsed on the host +host_inst_rate 1311458 # Simulator instruction rate (inst/s) +host_op_rate 1596489 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 25571502260 # Simulator tick rate (ticks/s) +host_mem_usage 616488 # Number of bytes of host memory used +host_seconds 108.87 # Real time elapsed on the host sim_insts 142773109 # Number of instructions simulated sim_ops 173803334 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -87,6 +87,14 @@ system.cf0.dma_write_full_pages 540 # Nu system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -108,6 +116,24 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu0.dtb.walker.walks 5682 # Table walker walks requested +system.cpu0.dtb.walker.walksShort 5682 # Table walker walks initiated with short descriptors +system.cpu0.dtb.walker.walkWaitTime::samples 5682 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 5682 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 5682 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walksPending::samples 6705500 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 6705500 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 6705500 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 3049 65.42% 65.42% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 1612 34.58% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 4661 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 5682 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 5682 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 4661 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 4661 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 10343 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses system.cpu0.dtb.read_hits 15994592 # DTB read hits @@ -129,6 +155,14 @@ system.cpu0.dtb.inst_accesses 0 # IT system.cpu0.dtb.hits 27280368 # DTB hits system.cpu0.dtb.misses 5682 # DTB misses system.cpu0.dtb.accesses 27286050 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -150,6 +184,24 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu0.itb.walker.walks 2611 # Table walker walks requested +system.cpu0.itb.walker.walksShort 2611 # Table walker walks initiated with short descriptors +system.cpu0.itb.walker.walkWaitTime::samples 2611 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 2611 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 2611 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walksPending::samples 6702500 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 6702500 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 6702500 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 1374 72.85% 72.85% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::1M 512 27.15% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 1886 # Table walker page sizes translated +system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 2611 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 2611 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 1886 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 1886 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 4497 # Table walker requests started/completed, data/inst system.cpu0.itb.inst_hits 74779253 # ITB inst hits system.cpu0.itb.inst_misses 2611 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits @@ -408,6 +460,14 @@ system.cpu0.icache.avg_blocked_cycles::no_targets nan system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -429,6 +489,24 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu1.dtb.walker.walks 6203 # Table walker walks requested +system.cpu1.dtb.walker.walksShort 6203 # Table walker walks initiated with short descriptors +system.cpu1.dtb.walker.walkWaitTime::samples 6203 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 6203 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 6203 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walksPending::samples 1000002000 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 1000002000 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 1000002000 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 3703 73.18% 73.18% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::1M 1357 26.82% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 5060 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 6203 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 6203 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 5060 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 5060 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 11263 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses system.cpu1.dtb.read_hits 15530019 # DTB read hits @@ -450,6 +528,14 @@ system.cpu1.dtb.inst_accesses 0 # IT system.cpu1.dtb.hits 27368468 # DTB hits system.cpu1.dtb.misses 6203 # DTB misses system.cpu1.dtb.accesses 27374671 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -471,6 +557,24 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu1.itb.walker.walks 3040 # Table walker walks requested +system.cpu1.itb.walker.walksShort 3040 # Table walker walks initiated with short descriptors +system.cpu1.itb.walker.walkWaitTime::samples 3040 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 3040 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 3040 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walksPending::samples 1000000500 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 1000000500 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 1000000500 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 1720 81.52% 81.52% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::1M 390 18.48% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 2110 # Table walker page sizes translated +system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 3040 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 3040 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 2110 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 2110 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 5150 # Table walker requests started/completed, data/inst system.cpu1.itb.inst_hits 72259450 # ITB inst hits system.cpu1.itb.inst_misses 3040 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt index 818a22f67..83b8a4ab7 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt @@ -4,11 +4,11 @@ sim_seconds 47.177080 # Nu sim_ticks 47177080006500 # Number of ticks simulated final_tick 47177080006500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1024538 # Simulator instruction rate (inst/s) -host_op_rate 1205255 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 49483118923 # Simulator tick rate (ticks/s) -host_mem_usage 669884 # Number of bytes of host memory used -host_seconds 953.40 # Real time elapsed on the host +host_inst_rate 1049876 # Simulator instruction rate (inst/s) +host_op_rate 1235062 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 50706899360 # Simulator tick rate (ticks/s) +host_mem_usage 670076 # Number of bytes of host memory used +host_seconds 930.39 # Real time elapsed on the host sim_insts 976792036 # Number of instructions simulated sim_ops 1149086878 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -105,6 +105,14 @@ system.cf0.dma_write_full_pages 1667 # Nu system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1670 # Number of DMA write transactions. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -126,6 +134,24 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu0.dtb.walker.walks 123914 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 123914 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walkWaitTime::samples 123914 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 123914 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 123914 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walksPending::samples 22846000 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 22846000 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 22846000 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 95376 89.74% 89.74% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 10905 10.26% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 106281 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 123914 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 123914 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 106281 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 106281 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 230195 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses system.cpu0.dtb.read_hits 91355479 # DTB read hits @@ -147,6 +173,14 @@ system.cpu0.dtb.inst_accesses 0 # IT system.cpu0.dtb.hits 175957422 # DTB hits system.cpu0.dtb.misses 123914 # DTB misses system.cpu0.dtb.accesses 176081336 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -168,6 +202,24 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu0.itb.walker.walks 60226 # Table walker walks requested +system.cpu0.itb.walker.walksLong 60226 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walkWaitTime::samples 60226 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 60226 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 60226 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walksPending::samples 22844500 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 22844500 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 22844500 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 54190 98.81% 98.81% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 654 1.19% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 54844 # Table walker page sizes translated +system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 60226 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 60226 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 54844 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 54844 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 115070 # Table walker requests started/completed, data/inst system.cpu0.itb.inst_hits 491372488 # ITB inst hits system.cpu0.itb.inst_misses 60226 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits @@ -392,15 +444,12 @@ system.cpu0.icache.avg_blocked_cycles::no_targets nan system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu0.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu0.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified +system.cpu0.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue +system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped +system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size +system.cpu0.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing system.cpu0.l2cache.tags.replacements 2648971 # number of replacements system.cpu0.l2cache.tags.tagsinuse 16219.904236 # Cycle average of tags in use system.cpu0.l2cache.tags.total_refs 11415809 # Total number of references to valid blocks. @@ -576,6 +625,14 @@ system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::total 20196192 # Request fanout histogram +system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -597,6 +654,24 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu1.dtb.walker.walks 144852 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 144852 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walkWaitTime::samples 144852 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 144852 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 144852 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walksPending::samples -274403872 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 -274403872 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total -274403872 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 112422 89.02% 89.02% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 13865 10.98% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 126287 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 144852 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 144852 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 126287 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 126287 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 271139 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses system.cpu1.dtb.read_hits 91720002 # DTB read hits @@ -618,6 +693,14 @@ system.cpu1.dtb.inst_accesses 0 # IT system.cpu1.dtb.hits 174219015 # DTB hits system.cpu1.dtb.misses 144852 # DTB misses system.cpu1.dtb.accesses 174363867 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -639,6 +722,24 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu1.itb.walker.walks 61939 # Table walker walks requested +system.cpu1.itb.walker.walksLong 61939 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walkWaitTime::samples 61939 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 61939 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 61939 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walksPending::samples -274404872 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 -274404872 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total -274404872 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 54929 99.06% 99.06% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 521 0.94% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 55450 # Table walker page sizes translated +system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 61939 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 61939 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 55450 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 55450 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 117389 # Table walker requests started/completed, data/inst system.cpu1.itb.inst_hits 485906850 # ITB inst hits system.cpu1.itb.inst_misses 61939 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits @@ -861,15 +962,12 @@ system.cpu1.icache.avg_blocked_cycles::no_targets nan system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified 0 # number of hwpf identified -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 0 # number of hwpf issued -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu1.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue +system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped +system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size +system.cpu1.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing system.cpu1.l2cache.tags.replacements 2333825 # number of replacements system.cpu1.l2cache.tags.tagsinuse 13484.024344 # Cycle average of tags in use system.cpu1.l2cache.tags.total_refs 11006559 # Total number of references to valid blocks. diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/stats.txt index 09df20817..70b8700c6 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 51.111151 # Nu sim_ticks 51111150553500 # Number of ticks simulated final_tick 51111150553500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1176583 # Simulator instruction rate (inst/s) -host_op_rate 1382679 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 61065327647 # Simulator tick rate (ticks/s) -host_mem_usage 656288 # Number of bytes of host memory used -host_seconds 836.99 # Real time elapsed on the host +host_inst_rate 1336104 # Simulator instruction rate (inst/s) +host_op_rate 1570142 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 69344550867 # Simulator tick rate (ticks/s) +host_mem_usage 712616 # Number of bytes of host memory used +host_seconds 737.06 # Real time elapsed on the host sim_insts 984789519 # Number of instructions simulated sim_ops 1157289961 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -74,6 +74,14 @@ system.cf0.dma_write_full_pages 1666 # Nu system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1669 # Number of DMA write transactions. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -95,6 +103,24 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 265618 # Table walker walks requested +system.cpu.dtb.walker.walksLong 265618 # Table walker walks initiated with long descriptors +system.cpu.dtb.walker.walkWaitTime::samples 265618 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0 265618 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::total 265618 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walksPending::samples 22846000 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::0 22846000 100.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::total 22846000 # Table walker pending requests distribution +system.cpu.dtb.walker.walkPageSizes::4K 204344 89.54% 89.54% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::2M 23878 10.46% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 228222 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 265618 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 265618 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 228222 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 228222 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 493840 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 184057973 # DTB read hits @@ -116,6 +142,14 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 352334273 # DTB hits system.cpu.dtb.misses 265618 # DTB misses system.cpu.dtb.accesses 352599891 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -137,6 +171,24 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 126829 # Table walker walks requested +system.cpu.itb.walker.walksLong 126829 # Table walker walks initiated with long descriptors +system.cpu.itb.walker.walkWaitTime::samples 126829 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0 126829 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::total 126829 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walksPending::samples 22844500 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::0 22844500 100.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::total 22844500 # Table walker pending requests distribution +system.cpu.itb.walker.walkPageSizes::4K 113566 99.02% 99.02% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::2M 1125 0.98% 100.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 114691 # Table walker page sizes translated +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 126829 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 126829 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 114691 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 114691 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 241520 # Table walker requests started/completed, data/inst system.cpu.itb.inst_hits 985266544 # ITB inst hits system.cpu.itb.inst_misses 126829 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt index 2d0abc648..cd0cb8f17 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt @@ -1,172 +1,172 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 47.398431 # Number of seconds simulated -sim_ticks 47398431268500 # Number of ticks simulated -final_tick 47398431268500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 47.410782 # Number of seconds simulated +sim_ticks 47410781652000 # Number of ticks simulated +final_tick 47410781652000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 671569 # Simulator instruction rate (inst/s) -host_op_rate 790318 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 37657329129 # Simulator tick rate (ticks/s) -host_mem_usage 861000 # Number of bytes of host memory used -host_seconds 1258.68 # Real time elapsed on the host -sim_insts 845288376 # Number of instructions simulated -sim_ops 994755388 # Number of ops (including micro ops) simulated +host_inst_rate 787433 # Simulator instruction rate (inst/s) +host_op_rate 926573 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 41969003911 # Simulator tick rate (ticks/s) +host_mem_usage 699232 # Number of bytes of host memory used +host_seconds 1129.66 # Real time elapsed on the host +sim_insts 889532971 # Number of instructions simulated +sim_ops 1046714541 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 36416 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 41984 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 768052 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 7936536 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 44723840 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 83456 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 97984 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 589368 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 8667104 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 21031552 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 441920 # Number of bytes read from this memory -system.physmem.bytes_read::total 84418212 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 768052 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 589368 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1357420 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 65101248 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.dtb.walker 154432 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 156800 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 3551860 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 14084888 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 14587840 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 66560 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 59904 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 2809592 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 8562400 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 11943680 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 428992 # Number of bytes read from this memory +system.physmem.bytes_read::total 56406948 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 3551860 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 2809592 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 6361452 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 74353408 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 20812 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory -system.physmem.bytes_written::total 65122064 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 569 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 656 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 52408 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 124030 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 698810 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 1304 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 1531 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 9297 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 135438 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 328618 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6905 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1359566 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1017207 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 74374224 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 2413 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 2450 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 95905 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 220098 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 227935 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 1040 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 936 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 43988 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 133802 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 186620 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6703 # Number of read requests responded to by this memory +system.physmem.num_reads::total 921890 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1161772 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 2602 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1019810 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 768 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 886 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 16204 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 167443 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 943572 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 1761 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 2067 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 12434 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 182856 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 443718 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 9324 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1781034 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 16204 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 12434 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 28639 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1373490 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1164375 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 3257 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 3307 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 74917 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 297082 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 307690 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 1404 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 1264 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 59261 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 180600 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 251919 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 9048 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1189749 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 74917 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 59261 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 134177 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1568281 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 439 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1373929 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1373490 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 768 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 886 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 16204 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 167882 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 943572 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 1761 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 2067 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 12434 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 182856 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 443718 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 9324 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3154963 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1359566 # Number of read requests accepted -system.physmem.writeReqs 1139623 # Number of write requests accepted -system.physmem.readBursts 1359566 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1139623 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 86962304 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 49920 # Total number of bytes read from write queue -system.physmem.bytesWritten 72439488 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 84418212 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 72790096 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 780 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 7732 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 85004 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 81504 # Per bank write bursts -system.physmem.perBankRdBursts::1 94599 # Per bank write bursts -system.physmem.perBankRdBursts::2 79086 # Per bank write bursts -system.physmem.perBankRdBursts::3 89082 # Per bank write bursts -system.physmem.perBankRdBursts::4 90127 # Per bank write bursts -system.physmem.perBankRdBursts::5 94039 # Per bank write bursts -system.physmem.perBankRdBursts::6 78740 # Per bank write bursts -system.physmem.perBankRdBursts::7 79772 # Per bank write bursts -system.physmem.perBankRdBursts::8 80197 # Per bank write bursts -system.physmem.perBankRdBursts::9 124149 # Per bank write bursts -system.physmem.perBankRdBursts::10 71869 # Per bank write bursts -system.physmem.perBankRdBursts::11 83577 # Per bank write bursts -system.physmem.perBankRdBursts::12 73174 # Per bank write bursts -system.physmem.perBankRdBursts::13 83519 # Per bank write bursts -system.physmem.perBankRdBursts::14 78794 # Per bank write bursts -system.physmem.perBankRdBursts::15 76558 # Per bank write bursts -system.physmem.perBankWrBursts::0 70549 # Per bank write bursts -system.physmem.perBankWrBursts::1 76959 # Per bank write bursts -system.physmem.perBankWrBursts::2 69527 # Per bank write bursts -system.physmem.perBankWrBursts::3 76268 # Per bank write bursts -system.physmem.perBankWrBursts::4 71760 # Per bank write bursts -system.physmem.perBankWrBursts::5 76111 # Per bank write bursts -system.physmem.perBankWrBursts::6 67646 # Per bank write bursts -system.physmem.perBankWrBursts::7 68141 # Per bank write bursts -system.physmem.perBankWrBursts::8 69345 # Per bank write bursts -system.physmem.perBankWrBursts::9 72887 # Per bank write bursts -system.physmem.perBankWrBursts::10 65485 # Per bank write bursts -system.physmem.perBankWrBursts::11 73987 # Per bank write bursts -system.physmem.perBankWrBursts::12 65828 # Per bank write bursts -system.physmem.perBankWrBursts::13 73935 # Per bank write bursts -system.physmem.perBankWrBursts::14 66021 # Per bank write bursts -system.physmem.perBankWrBursts::15 67418 # Per bank write bursts +system.physmem.bw_write::total 1568720 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1568281 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 3257 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 3307 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 74917 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 297521 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 307690 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 1404 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 1264 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 59261 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 180600 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 251919 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 9048 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2758469 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 921890 # Number of read requests accepted +system.physmem.writeReqs 1829645 # Number of write requests accepted +system.physmem.readBursts 921890 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1829645 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 58978368 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 22592 # Total number of bytes read from write queue +system.physmem.bytesWritten 116660480 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 56406948 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 116951504 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 353 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 6803 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 114603 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 54393 # Per bank write bursts +system.physmem.perBankRdBursts::1 56084 # Per bank write bursts +system.physmem.perBankRdBursts::2 54659 # Per bank write bursts +system.physmem.perBankRdBursts::3 58883 # Per bank write bursts +system.physmem.perBankRdBursts::4 54974 # Per bank write bursts +system.physmem.perBankRdBursts::5 58047 # Per bank write bursts +system.physmem.perBankRdBursts::6 51881 # Per bank write bursts +system.physmem.perBankRdBursts::7 58759 # Per bank write bursts +system.physmem.perBankRdBursts::8 52533 # Per bank write bursts +system.physmem.perBankRdBursts::9 95950 # Per bank write bursts +system.physmem.perBankRdBursts::10 53815 # Per bank write bursts +system.physmem.perBankRdBursts::11 56993 # Per bank write bursts +system.physmem.perBankRdBursts::12 52328 # Per bank write bursts +system.physmem.perBankRdBursts::13 55917 # Per bank write bursts +system.physmem.perBankRdBursts::14 52932 # Per bank write bursts +system.physmem.perBankRdBursts::15 53389 # Per bank write bursts +system.physmem.perBankWrBursts::0 113787 # Per bank write bursts +system.physmem.perBankWrBursts::1 117144 # Per bank write bursts +system.physmem.perBankWrBursts::2 115098 # Per bank write bursts +system.physmem.perBankWrBursts::3 118536 # Per bank write bursts +system.physmem.perBankWrBursts::4 116769 # Per bank write bursts +system.physmem.perBankWrBursts::5 120895 # Per bank write bursts +system.physmem.perBankWrBursts::6 109520 # Per bank write bursts +system.physmem.perBankWrBursts::7 112924 # Per bank write bursts +system.physmem.perBankWrBursts::8 111914 # Per bank write bursts +system.physmem.perBankWrBursts::9 117541 # Per bank write bursts +system.physmem.perBankWrBursts::10 111832 # Per bank write bursts +system.physmem.perBankWrBursts::11 116807 # Per bank write bursts +system.physmem.perBankWrBursts::12 108182 # Per bank write bursts +system.physmem.perBankWrBursts::13 109739 # Per bank write bursts +system.physmem.perBankWrBursts::14 110202 # Per bank write bursts +system.physmem.perBankWrBursts::15 111930 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 5 # Number of times write queue was full causing retry -system.physmem.totGap 47398428076000 # Total gap between requests +system.physmem.numWrRetry 2 # Number of times write queue was full causing retry +system.physmem.totGap 47410778671000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 43195 # Read request sizes (log2) system.physmem.readPktSize::3 37 # Read request sizes (log2) system.physmem.readPktSize::4 5 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1316329 # Read request sizes (log2) +system.physmem.readPktSize::6 878653 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 2 # Write request sizes (log2) system.physmem.writePktSize::3 2601 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1137020 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 566894 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 282234 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 134057 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 101972 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 67644 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 58693 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 53670 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 46721 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 35916 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 3762 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1955 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1465 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1125 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 882 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 709 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 471 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 229 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 184 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 107 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 75 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 7 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::25 2 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1827042 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 652905 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 75815 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 40303 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 33479 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 29162 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 25818 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 22543 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 19321 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 15689 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 2492 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1008 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 754 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 600 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 460 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 351 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 292 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 214 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 179 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 82 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 63 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see @@ -188,158 +188,182 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 16911 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 22466 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 30737 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 39170 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 44059 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 50283 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 58139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 68202 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 72051 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 76579 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 76851 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 78478 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 78341 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 80363 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 74556 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 75992 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 78312 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 75395 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 11828 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 7611 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 4129 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 1848 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 1099 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 916 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 777 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 712 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 642 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 648 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 562 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 544 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 505 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 463 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 418 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 372 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 356 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 314 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 286 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 239 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 192 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 151 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 77 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 60 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 45 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 34 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 28 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 5 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 648906 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 245.646870 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 142.183985 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 295.195613 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 325424 50.15% 50.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 135792 20.93% 71.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 50411 7.77% 78.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 26706 4.12% 82.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 22287 3.43% 86.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 16108 2.48% 88.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 10950 1.69% 90.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 13619 2.10% 92.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 47609 7.34% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 648906 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 58676 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 23.156827 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 139.787244 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 58673 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 54841 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 74169 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 96317 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 106970 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 112981 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 116642 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 107891 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 106380 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 105711 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 108843 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 109894 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 108607 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 105867 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 106408 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 98436 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 96529 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 94372 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 91211 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 4176 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 3101 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 2283 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 1802 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 1394 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 1150 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 899 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 725 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 589 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 554 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 484 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 413 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 392 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 373 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 345 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 326 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 302 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 273 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 268 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 219 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 188 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 154 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 80 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 55 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 39 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 26 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 23 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 6 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 1000117 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 175.617981 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 106.594305 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 248.236984 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 645970 64.59% 64.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 191036 19.10% 83.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 45051 4.50% 88.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 21747 2.17% 90.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 15328 1.53% 91.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 10644 1.06% 92.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 8285 0.83% 93.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 7295 0.73% 94.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 54761 5.48% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1000117 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 87721 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 10.505238 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 108.849756 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 87718 100.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::20480-21503 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::24576-25599 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 58676 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 58676 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 19.290119 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.850822 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 13.308232 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 54948 93.65% 93.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 970 1.65% 95.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 598 1.02% 96.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 219 0.37% 96.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 626 1.07% 97.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 147 0.25% 98.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 195 0.33% 98.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 132 0.22% 98.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 184 0.31% 98.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 81 0.14% 99.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 205 0.35% 99.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 24 0.04% 99.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-119 63 0.11% 99.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-127 38 0.06% 99.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 129 0.22% 99.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-143 15 0.03% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-151 27 0.05% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-159 11 0.02% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-167 19 0.03% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 8 0.01% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 11 0.02% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-191 1 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-199 2 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-207 5 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-215 6 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-223 3 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-231 4 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::232-239 2 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::248-255 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-263 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::272-279 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 58676 # Writes before turning the bus around for reads -system.physmem.totQLat 69966976258 # Total ticks spent queuing -system.physmem.totMemAccLat 95444213758 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 6793930000 # Total ticks spent in databus transfers -system.physmem.avgQLat 51492.27 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::23552-24575 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 87721 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 87721 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.779745 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 19.605058 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 11.125024 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 56948 64.92% 64.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 16031 18.27% 83.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 6972 7.95% 91.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 3738 4.26% 95.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 1084 1.24% 96.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 357 0.41% 97.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 239 0.27% 97.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 271 0.31% 97.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 649 0.74% 98.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 108 0.12% 98.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 85 0.10% 98.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 76 0.09% 98.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 135 0.15% 98.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 76 0.09% 98.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 51 0.06% 98.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 73 0.08% 99.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 134 0.15% 99.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 41 0.05% 99.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 31 0.04% 99.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 49 0.06% 99.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 179 0.20% 99.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 16 0.02% 99.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 31 0.04% 99.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 14 0.02% 99.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 43 0.05% 99.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 12 0.01% 99.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 20 0.02% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 30 0.03% 99.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 97 0.11% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 18 0.02% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 14 0.02% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 10 0.01% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 13 0.01% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 11 0.01% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 6 0.01% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 6 0.01% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 14 0.02% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 1 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-171 2 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 3 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 12 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-187 2 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::188-191 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-195 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-203 3 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::204-207 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::212-215 3 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::220-223 3 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-227 4 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::228-231 3 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 87721 # Writes before turning the bus around for reads +system.physmem.totQLat 32913462781 # Total ticks spent queuing +system.physmem.totMemAccLat 50192281531 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 4607685000 # Total ticks spent in databus transfers +system.physmem.avgQLat 35715.83 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 70242.27 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.83 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.53 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.78 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.54 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 54465.83 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.24 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.46 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.19 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.47 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.73 # Average read queue length when enqueuing -system.physmem.avgWrQLen 23.44 # Average write queue length when enqueuing -system.physmem.readRowHits 1114788 # Number of row buffer hits during reads -system.physmem.writeRowHits 726958 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.04 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 64.23 # Row buffer hit rate for writes -system.physmem.avgGap 18965523.65 # Average gap between requests -system.physmem.pageHitRate 73.95 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 45538400789750 # Time in different power states -system.physmem.memoryStateTime::REF 1582737780000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 277292625250 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 2564850960 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 2340878400 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 1399472250 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 1277265000 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 5358202200 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 5240320800 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 3738707280 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 3595790880 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 3095835097680 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 3095835097680 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 1171174509540 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 1161726671475 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 27411712647750 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 27420000225000 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 31691783487660 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 31690016249235 # Total energy per rank (pJ) -system.physmem.averagePower::0 668.625157 # Core power per rank (mW) -system.physmem.averagePower::1 668.587872 # Core power per rank (mW) +system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.25 # Average read queue length when enqueuing +system.physmem.avgWrQLen 25.28 # Average write queue length when enqueuing +system.physmem.readRowHits 687654 # Number of row buffer hits during reads +system.physmem.writeRowHits 1056585 # Number of row buffer hits during writes +system.physmem.readRowHitRate 74.62 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 57.96 # Row buffer hit rate for writes +system.physmem.avgGap 17230665.31 # Average gap between requests +system.physmem.pageHitRate 63.56 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 3832851960 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 2091337875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 3491865000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 5991881040 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3096641673840 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1200455054145 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 27393437346750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 31705942010610 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.749637 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 45570820980751 # Time in different power states +system.physmem_0.memoryStateTime::REF 1583150140000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 256810103749 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 3728032560 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2034144750 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 3696084600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 5819992560 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3096641673840 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1191404828700 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 27401376141000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 31704700898010 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.723459 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 45584059811251 # Time in different power states +system.physmem_1.memoryStateTime::REF 1583150140000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 243570222499 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 64 # Number of bytes read from this memory @@ -373,6 +397,14 @@ system.cf0.dma_write_full_pages 1670 # Nu system.cf0.dma_write_bytes 6842880 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1673 # Number of DMA write transactions. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -394,27 +426,74 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu0.dtb.walker.walks 107972 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 107972 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 9276 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 83163 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksSquashedBefore 9 # Table walks squashed before starting +system.cpu0.dtb.walker.walkWaitTime::samples 107963 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 107963 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 107963 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 92448 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 17595.764614 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 15306.328665 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 15454.252367 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-65535 91009 98.44% 98.44% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::65536-131071 1235 1.34% 99.78% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-196607 66 0.07% 99.85% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::196608-262143 55 0.06% 99.91% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::262144-327679 65 0.07% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::327680-393215 12 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::393216-458751 3 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 92448 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples -2398441544 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 0.163884 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::stdev 0.370170 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 -2005375084 83.61% 83.61% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::1 -393066460 16.39% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total -2398441544 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 83163 89.97% 89.97% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 9276 10.03% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 92439 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 107972 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 107972 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 92439 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 92439 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 200411 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 74706058 # DTB read hits -system.cpu0.dtb.read_misses 64792 # DTB read misses -system.cpu0.dtb.write_hits 67192400 # DTB write hits -system.cpu0.dtb.write_misses 21129 # DTB write misses +system.cpu0.dtb.read_hits 83792624 # DTB read hits +system.cpu0.dtb.read_misses 78614 # DTB read misses +system.cpu0.dtb.write_hits 76883618 # DTB write hits +system.cpu0.dtb.write_misses 29358 # DTB write misses system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 37660 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 1002 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 33482 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_tlb_mva_asid 41330 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 1050 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 38297 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 3817 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 4651 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 8375 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 74770850 # DTB read accesses -system.cpu0.dtb.write_accesses 67213529 # DTB write accesses +system.cpu0.dtb.perms_faults 10679 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 83871238 # DTB read accesses +system.cpu0.dtb.write_accesses 76912976 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 141898458 # DTB hits -system.cpu0.dtb.misses 85921 # DTB misses -system.cpu0.dtb.accesses 141984379 # DTB accesses +system.cpu0.dtb.hits 160676242 # DTB hits +system.cpu0.dtb.misses 107972 # DTB misses +system.cpu0.dtb.accesses 160784214 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -436,201 +515,236 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.inst_hits 397874920 # ITB inst hits -system.cpu0.itb.inst_misses 49120 # ITB inst misses +system.cpu0.itb.walker.walks 64255 # Table walker walks requested +system.cpu0.itb.walker.walksLong 64255 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walksLongTerminationLevel::Level2 637 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksLongTerminationLevel::Level3 58227 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walkWaitTime::samples 64255 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 64255 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 64255 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 58864 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 20635.902164 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 17664.674655 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 19771.927470 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-65535 57276 97.30% 97.30% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::65536-131071 1371 2.33% 99.63% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::131072-196607 47 0.08% 99.71% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::196608-262143 91 0.15% 99.87% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::262144-327679 53 0.09% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::327680-393215 19 0.03% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::393216-458751 5 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 58864 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksPending::samples -673300296 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 -673300296 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total -673300296 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 58227 98.92% 98.92% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 637 1.08% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 58864 # Table walker page sizes translated +system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 64255 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 64255 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 58864 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 58864 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 123119 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 448595101 # ITB inst hits +system.cpu0.itb.inst_misses 64255 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 37660 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 1002 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 23760 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 41330 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 1050 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 26739 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 397924040 # ITB inst accesses -system.cpu0.itb.hits 397874920 # DTB hits -system.cpu0.itb.misses 49120 # DTB misses -system.cpu0.itb.accesses 397924040 # DTB accesses -system.cpu0.numCycles 94796862537 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 448659356 # ITB inst accesses +system.cpu0.itb.hits 448595101 # DTB hits +system.cpu0.itb.misses 64255 # DTB misses +system.cpu0.itb.accesses 448659356 # DTB accesses +system.cpu0.numCycles 94821563304 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 397643174 # Number of instructions committed -system.cpu0.committedOps 466635553 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 429030148 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 322477 # Number of float alu accesses -system.cpu0.num_func_calls 23930039 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 59901605 # number of instructions that are conditional controls -system.cpu0.num_int_insts 429030148 # number of integer instructions -system.cpu0.num_fp_insts 322477 # number of float instructions -system.cpu0.num_int_register_reads 621630892 # number of times the integer registers were read -system.cpu0.num_int_register_writes 340702516 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 547437 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 211832 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 102593685 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 102325899 # number of times the CC registers were written -system.cpu0.num_mem_refs 141893093 # number of memory refs -system.cpu0.num_load_insts 74704433 # Number of load instructions -system.cpu0.num_store_insts 67188660 # Number of store instructions -system.cpu0.num_idle_cycles 93886429062.298019 # Number of idle cycles -system.cpu0.num_busy_cycles 910433474.701981 # Number of busy cycles -system.cpu0.not_idle_fraction 0.009604 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.990396 # Percentage of idle cycles -system.cpu0.Branches 88352328 # Number of branches fetched -system.cpu0.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 323823287 69.35% 69.35% # Class of executed instruction -system.cpu0.op_class::IntMult 1114929 0.24% 69.59% # Class of executed instruction -system.cpu0.op_class::IntDiv 56737 0.01% 69.61% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 22377 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.61% # Class of executed instruction -system.cpu0.op_class::MemRead 74704433 16.00% 85.61% # Class of executed instruction -system.cpu0.op_class::MemWrite 67188660 14.39% 100.00% # Class of executed instruction +system.cpu0.committedInsts 448345930 # Number of instructions committed +system.cpu0.committedOps 527651436 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 484594714 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 558267 # Number of float alu accesses +system.cpu0.num_func_calls 26890258 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 68074268 # number of instructions that are conditional controls +system.cpu0.num_int_insts 484594714 # number of integer instructions +system.cpu0.num_fp_insts 558267 # number of float instructions +system.cpu0.num_int_register_reads 706750752 # number of times the integer registers were read +system.cpu0.num_int_register_writes 384547382 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 893879 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 490056 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 117567828 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 117277075 # number of times the CC registers were written +system.cpu0.num_mem_refs 160668093 # number of memory refs +system.cpu0.num_load_insts 83788812 # Number of load instructions +system.cpu0.num_store_insts 76879281 # Number of store instructions +system.cpu0.num_idle_cycles 93729284290.716034 # Number of idle cycles +system.cpu0.num_busy_cycles 1092279013.283977 # Number of busy cycles +system.cpu0.not_idle_fraction 0.011519 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.988481 # Percentage of idle cycles +system.cpu0.Branches 100174256 # Number of branches fetched +system.cpu0.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 365953478 69.32% 69.32% # Class of executed instruction +system.cpu0.op_class::IntMult 1186010 0.22% 69.54% # Class of executed instruction +system.cpu0.op_class::IntDiv 57830 0.01% 69.55% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 69.55% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 69.55% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 69.55% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 69.55% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 69.55% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 69.55% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 69.55% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 69.55% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 69.55% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 69.55% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 69.55% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 69.55% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 69.55% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 69.55% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 69.55% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.55% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 69.55% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 8 0.00% 69.55% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.55% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 13 0.00% 69.55% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 21 0.00% 69.55% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.55% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 78277 0.01% 69.57% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 69.57% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.57% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.57% # Class of executed instruction +system.cpu0.op_class::MemRead 83788812 15.87% 85.44% # Class of executed instruction +system.cpu0.op_class::MemWrite 76879281 14.56% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 466910423 # Class of executed instruction +system.cpu0.op_class::total 527943731 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 5105 # number of quiesce instructions executed -system.cpu0.dcache.tags.replacements 4859280 # number of replacements -system.cpu0.dcache.tags.tagsinuse 480.680410 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 136835586 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 4859789 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 28.156693 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 3644536500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 480.680410 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.938829 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.938829 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 509 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 94 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 406 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 9 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 0.994141 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 288671468 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 288671468 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 69599952 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 69599952 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 63413457 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 63413457 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 173858 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 173858 # number of SoftPFReq hits -system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 133135 # number of WriteInvalidateReq hits -system.cpu0.dcache.WriteInvalidateReq_hits::total 133135 # number of WriteInvalidateReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1596886 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 1596886 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1561841 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 1561841 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 133013409 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 133013409 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 133187267 # number of overall hits -system.cpu0.dcache.overall_hits::total 133187267 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 2622769 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 2622769 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1185607 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1185607 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 553155 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 553155 # number of SoftPFReq misses -system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data 697992 # number of WriteInvalidateReq misses -system.cpu0.dcache.WriteInvalidateReq_misses::total 697992 # number of WriteInvalidateReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 145021 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 145021 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 178721 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 178721 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 3808376 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 3808376 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 4361531 # number of overall misses -system.cpu0.dcache.overall_misses::total 4361531 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 36725560788 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 36725560788 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 18496940456 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 18496940456 # number of WriteReq miss cycles -system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu0.data 11951080104 # number of WriteInvalidateReq miss cycles -system.cpu0.dcache.WriteInvalidateReq_miss_latency::total 11951080104 # number of WriteInvalidateReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2007745317 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 2007745317 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 3807661334 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 3807661334 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 927000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 927000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 55222501244 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 55222501244 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 55222501244 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 55222501244 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 72222721 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 72222721 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 64599064 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 64599064 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 727013 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 727013 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data 831127 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.dcache.WriteInvalidateReq_accesses::total 831127 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1741907 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 1741907 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1740562 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 1740562 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 136821785 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 136821785 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 137548798 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 137548798 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.036315 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.036315 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018353 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.018353 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.760860 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.760860 # miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data 0.839814 # miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.WriteInvalidateReq_miss_rate::total 0.839814 # miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.083254 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.083254 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.102680 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.102680 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.027835 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.027835 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.031709 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.031709 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14002.590693 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 14002.590693 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 15601.240931 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 15601.240931 # average WriteReq miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu0.data 17122.087508 # average WriteInvalidateReq miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::total 17122.087508 # average WriteInvalidateReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13844.514360 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13844.514360 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 21305.058354 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21305.058354 # average StoreCondReq miss latency +system.cpu0.kern.inst.quiesce 5474 # number of quiesce instructions executed +system.cpu0.dcache.tags.replacements 5753925 # number of replacements +system.cpu0.dcache.tags.tagsinuse 509.684776 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 154679022 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 5754435 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 26.879967 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 3644714000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 509.684776 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.995478 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.995478 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 390 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 55 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 327127592 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 327127592 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 77833401 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 77833401 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 72535559 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 72535559 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 180949 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 180949 # number of SoftPFReq hits +system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 117408 # number of WriteInvalidateReq hits +system.cpu0.dcache.WriteInvalidateReq_hits::total 117408 # number of WriteInvalidateReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1813577 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 1813577 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1784599 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 1784599 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 150368960 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 150368960 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 150549909 # number of overall hits +system.cpu0.dcache.overall_hits::total 150549909 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 3079415 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 3079415 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1439122 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1439122 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 698265 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 698265 # number of SoftPFReq misses +system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data 782756 # number of WriteInvalidateReq misses +system.cpu0.dcache.WriteInvalidateReq_misses::total 782756 # number of WriteInvalidateReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 172905 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 172905 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 200615 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 200615 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 4518537 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 4518537 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 5216802 # number of overall misses +system.cpu0.dcache.overall_misses::total 5216802 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 45365631768 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 45365631768 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 25986134990 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 25986134990 # number of WriteReq miss cycles +system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu0.data 26026367891 # number of WriteInvalidateReq miss cycles +system.cpu0.dcache.WriteInvalidateReq_miss_latency::total 26026367891 # number of WriteInvalidateReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2610218258 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 2610218258 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4265500897 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 4265500897 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 2243000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 2243000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 71351766758 # number of demand (read+write) miss cycles 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for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.038058 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.019454 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.019454 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.794192 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.794192 # miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data 0.869570 # miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.WriteInvalidateReq_miss_rate::total 0.869570 # miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.087041 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.087041 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.101055 # miss rate for StoreCondReq accesses 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+system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::total 33249.656203 # average WriteInvalidateReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15096.256661 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15096.256661 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 21262.123455 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21262.123455 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 14500.275510 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 14500.275510 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 12661.265332 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 12661.265332 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 15790.900187 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 15790.900187 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 13677.300146 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 13677.300146 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -639,92 +753,92 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 3276433 # number of writebacks -system.cpu0.dcache.writebacks::total 3276433 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 20828 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 20828 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 21424 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 21424 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 36174 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 36174 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 42252 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 42252 # number of demand (read+write) MSHR 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3440508666 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 879000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 879000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 46208703669 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 46208703669 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 57732968781 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 57732968781 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 2384094697 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 2384094697 # number of ReadReq MSHR uncacheable cycles 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-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.758494 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.839814 # mshr miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.839814 # mshr miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.062487 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.062487 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.102680 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.102680 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027526 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.027526 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.031389 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.031389 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11745.684807 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11745.684807 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 13440.434019 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 13440.434019 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 20898.682731 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 20898.682731 # average SoftPFReq mshr miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 15103.489576 # average WriteInvalidateReq mshr miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 15103.489576 # average WriteInvalidateReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11345.358228 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11345.358228 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 19250.724123 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19250.724123 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 3895213 # number of writebacks +system.cpu0.dcache.writebacks::total 3895213 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 35120 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 35120 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 21470 # number of WriteReq MSHR hits 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number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 74608980433 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 74608980433 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 2287793998 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 2287793998 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2244465248 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2244465248 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 4532259246 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 4532259246 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.037624 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.037624 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019164 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019164 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.787787 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.787787 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.869570 # mshr miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.869570 # mshr miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.063415 # mshr miss rate for LoadLockedReq accesses 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15927.337782 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 15927.337782 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 20550.874232 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 20550.874232 # average SoftPFReq mshr miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 31246.207131 # average WriteInvalidateReq mshr miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 31246.207131 # average WriteInvalidateReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12422.044137 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12422.044137 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 19207.318012 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19207.318012 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 12269.565120 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 12269.565120 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 13371.668756 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 13371.668756 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13531.036286 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13531.036286 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 14474.308369 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 14474.308369 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -732,59 +846,58 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 4269396 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.932974 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 393605012 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 4269908 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 92.181146 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 18918806750 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.932974 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999869 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999869 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 5166576 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.910022 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 443428013 # Total number of references to valid blocks. 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+system.cpu0.icache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 324 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 127 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 800019748 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 800019748 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 393605012 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 393605012 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 393605012 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 393605012 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 393605012 # number of overall hits -system.cpu0.icache.overall_hits::total 393605012 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 4269908 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 4269908 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 4269908 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 4269908 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 4269908 # number of overall misses -system.cpu0.icache.overall_misses::total 4269908 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 37643365597 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 37643365597 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 37643365597 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 37643365597 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 37643365597 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 37643365597 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 397874920 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 397874920 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 397874920 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 397874920 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 397874920 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 397874920 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.010732 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.010732 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.010732 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.010732 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.010732 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.010732 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 8815.966432 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 8815.966432 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 8815.966432 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 8815.966432 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 8815.966432 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 8815.966432 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 902357290 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 902357290 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 443428013 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 443428013 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 443428013 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 443428013 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 443428013 # number of overall hits +system.cpu0.icache.overall_hits::total 443428013 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 5167088 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 5167088 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 5167088 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 5167088 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 5167088 # number of overall misses +system.cpu0.icache.overall_misses::total 5167088 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 53694723563 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 53694723563 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 53694723563 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 53694723563 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 53694723563 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 53694723563 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 448595101 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 448595101 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 448595101 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 448595101 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 448595101 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 448595101 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011518 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.011518 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011518 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.011518 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011518 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.011518 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10391.679717 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 10391.679717 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10391.679717 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 10391.679717 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10391.679717 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 10391.679717 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -793,384 +906,383 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 4269908 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 4269908 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 4269908 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 4269908 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 4269908 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 4269908 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 31235618425 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 31235618425 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 31235618425 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 31235618425 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 31235618425 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 31235618425 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 5167088 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 5167088 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 5167088 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 5167088 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 5167088 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 5167088 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 45925261947 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 45925261947 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 45925261947 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 45925261947 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 45925261947 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 45925261947 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 3405609750 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 3405609750 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 3405609750 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 3405609750 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.010732 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.010732 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.010732 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.010732 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.010732 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.010732 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 7315.290733 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 7315.290733 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 7315.290733 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 7315.290733 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 7315.290733 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 7315.290733 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.011518 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.011518 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.011518 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.011518 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.011518 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.011518 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 8888.035572 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 8888.035572 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 8888.035572 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 8888.035572 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 8888.035572 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 8888.035572 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified 45505774 # number of hwpf identified -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 2657797 # number of hwpf that were already in mshr -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 39900232 # number of hwpf that were already in the cache -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 8744 # number of hwpf that were already in the prefetch queue -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 580 # number of hwpf removed because MSHR allocated -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 2938421 # number of hwpf issued -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 3808538 # number of hwpf spanning a virtual page -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu0.l2cache.tags.replacements 3291824 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 16191.272385 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 9909292 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 3307923 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 2.995624 # Average number of references to valid blocks. -system.cpu0.l2cache.tags.warmup_cycle 16044231500 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 5217.724609 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 49.949148 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 58.574202 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 727.292976 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.data 2667.900561 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 7469.830889 # Average occupied blocks per requestor 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# average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 23328.795643 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 19129.700667 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 21397.343606 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 21780.932052 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 23590.654453 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 43752.426923 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 37852.554233 # average overall mshr miss latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.231978 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 31456.355779 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 34671.120177 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 22958.552072 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 26026.451805 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 25072.510487 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 49425.192319 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 49425.192319 # average HardPFReq mshr miss latency +system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 34326.997887 # average WriteInvalidateReq mshr miss latency +system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 34326.997887 # average WriteInvalidateReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 16986.530742 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16986.530742 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 13741.236699 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13741.236699 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 214125 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 214125 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 36924.550389 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 36924.550389 # average ReadExReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 31456.355779 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 34671.120177 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 22958.552072 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 28227.276368 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 26740.395420 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 31456.355779 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 34671.120177 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 22958.552072 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 28227.276368 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 49425.192319 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 33232.542850 # average overall mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1180,59 +1292,67 @@ system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.trans_dist::ReadReq 11465749 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 8074092 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 15773 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 15773 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::Writeback 3276433 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 4228803 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 811507 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp 696929 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 407420 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 328722 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 423022 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 30 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 53 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 1108208 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 995011 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 8626066 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 14109371 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 260774 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 426575 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 23422786 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 273446612 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 532438419 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 912728 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1410280 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 808208039 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 8581549 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 21569506 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 5.385644 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.486747 # Request fanout histogram +system.cpu0.toL2Bus.trans_dist::ReadReq 11541292 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 9690709 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 15329 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 15329 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::Writeback 3895213 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 1069383 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 1166255 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp 781481 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 444610 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 368177 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 498972 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 55 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 100 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 1328849 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 1215209 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 10420426 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 16690518 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 351532 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 549297 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 28011773 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 330866132 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 630631769 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1276280 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1881728 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 964655909 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 4194903 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 19756578 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 5.197801 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.398341 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::5 13251364 61.44% 61.44% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::6 8318142 38.56% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::5 15848715 80.22% 80.22% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::6 3907863 19.78% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 21569506 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 10644176370 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 19756578 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 12645685295 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 173370992 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 194485993 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 6459583336 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 7813325558 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 6973558574 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 8298663367 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 146771777 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 192341003 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 250366041 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 314436506 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) +system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1254,27 +1374,82 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu1.dtb.walker.walks 99527 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 99527 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 9603 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 74573 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksSquashedBefore 9 # Table walks squashed before starting +system.cpu1.dtb.walker.walkWaitTime::samples 99518 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::mean 0.271308 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::stdev 67.169326 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0-2047 99516 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::6144-8191 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::18432-20479 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 99518 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 84185 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 16581.674289 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 15037.130908 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 10932.627488 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-32767 81471 96.78% 96.78% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::32768-65535 2185 2.60% 99.37% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::65536-98303 285 0.34% 99.71% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::98304-131071 159 0.19% 99.90% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::131072-163839 19 0.02% 99.92% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::163840-196607 14 0.02% 99.94% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::196608-229375 18 0.02% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::229376-262143 4 0.00% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::262144-294911 15 0.02% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::294912-327679 5 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::327680-360447 5 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::360448-393215 3 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 84185 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples -1589468256 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::mean 0.778279 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::stdev 0.415405 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 -352419148 22.17% 22.17% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::1 -1237049108 77.83% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total -1589468256 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 74574 88.59% 88.59% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 9603 11.41% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 84177 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 99527 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 99527 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 84177 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 84177 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 183704 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 84980512 # DTB read hits -system.cpu1.dtb.read_misses 74547 # DTB read misses -system.cpu1.dtb.write_hits 77969612 # DTB write hits -system.cpu1.dtb.write_misses 26781 # DTB write misses +system.cpu1.dtb.read_hits 83767099 # DTB read hits +system.cpu1.dtb.read_misses 74857 # DTB read misses +system.cpu1.dtb.write_hits 75685520 # DTB write hits +system.cpu1.dtb.write_misses 24670 # DTB write misses system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 37660 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 1002 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 37319 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_tlb_mva_asid 41330 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 1050 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 36584 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 4156 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 4104 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 10210 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 85055059 # DTB read accesses -system.cpu1.dtb.write_accesses 77996393 # DTB write accesses +system.cpu1.dtb.perms_faults 9015 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 83841956 # DTB read accesses +system.cpu1.dtb.write_accesses 75710190 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 162950124 # DTB hits -system.cpu1.dtb.misses 101328 # DTB misses -system.cpu1.dtb.accesses 163051452 # DTB accesses +system.cpu1.dtb.hits 159452619 # DTB hits +system.cpu1.dtb.misses 99527 # DTB misses +system.cpu1.dtb.accesses 159552146 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1296,201 +1471,239 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.inst_hits 447940407 # ITB inst hits -system.cpu1.itb.inst_misses 68561 # ITB inst misses +system.cpu1.itb.walker.walks 55326 # Table walker walks requested +system.cpu1.itb.walker.walksLong 55326 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walksLongTerminationLevel::Level2 571 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksLongTerminationLevel::Level3 49211 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 55326 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 55326 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 55326 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 49782 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 18533.691816 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 16693.913266 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 13345.941074 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-32767 47101 94.61% 94.61% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::32768-65535 2168 4.35% 98.97% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::65536-98303 178 0.36% 99.33% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::98304-131071 248 0.50% 99.83% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::131072-163839 12 0.02% 99.85% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::163840-196607 16 0.03% 99.88% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::196608-229375 24 0.05% 99.93% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::229376-262143 6 0.01% 99.94% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::262144-294911 18 0.04% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::294912-327679 3 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::327680-360447 4 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::360448-393215 3 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 49782 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples -1199136648 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 -1199136648 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total -1199136648 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 49211 98.85% 98.85% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 571 1.15% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 49782 # Table walker page sizes translated +system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 55326 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 55326 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 49782 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 49782 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 105108 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 441493680 # ITB inst hits +system.cpu1.itb.inst_misses 55326 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 37660 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 1002 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 26339 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 41330 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 1050 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 25739 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 448008968 # ITB inst accesses -system.cpu1.itb.hits 447940407 # DTB hits -system.cpu1.itb.misses 68561 # DTB misses -system.cpu1.itb.accesses 448008968 # DTB accesses -system.cpu1.numCycles 94796862537 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 441549006 # ITB inst accesses +system.cpu1.itb.hits 441493680 # DTB hits +system.cpu1.itb.misses 55326 # DTB misses +system.cpu1.itb.accesses 441549006 # DTB accesses +system.cpu1.numCycles 94821563303 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 447645202 # Number of instructions committed -system.cpu1.committedOps 528119835 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 486291398 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 624474 # Number of float alu accesses -system.cpu1.num_func_calls 27450761 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 67545606 # number of instructions that are conditional controls -system.cpu1.num_int_insts 486291398 # number of integer instructions -system.cpu1.num_fp_insts 624474 # number of float instructions -system.cpu1.num_int_register_reads 698728829 # number of times the integer registers were read -system.cpu1.num_int_register_writes 384530758 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 985803 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 576512 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 114161169 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 113813296 # number of times the CC registers were written -system.cpu1.num_mem_refs 162934099 # number of memory refs -system.cpu1.num_load_insts 84972579 # Number of load instructions -system.cpu1.num_store_insts 77961520 # Number of store instructions -system.cpu1.num_idle_cycles 93770083152.566025 # Number of idle cycles -system.cpu1.num_busy_cycles 1026779384.433978 # Number of busy cycles -system.cpu1.not_idle_fraction 0.010831 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.989169 # Percentage of idle cycles -system.cpu1.Branches 100081816 # Number of branches fetched -system.cpu1.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 364276895 68.94% 68.94% # Class of executed instruction -system.cpu1.op_class::IntMult 1051011 0.20% 69.14% # Class of executed instruction -system.cpu1.op_class::IntDiv 60606 0.01% 69.15% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 69.15% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 69.15% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 69.15% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 69.15% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 69.15% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 69.15% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 69.15% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 69.15% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 69.15% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 69.15% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 69.15% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 69.15% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 69.15% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 69.15% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 69.15% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.15% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 69.15% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.15% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.15% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.15% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 21 0.00% 69.15% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.15% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 92495 0.02% 69.17% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 69.17% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.17% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.17% # Class of executed instruction -system.cpu1.op_class::MemRead 84972579 16.08% 85.25% # Class of executed instruction -system.cpu1.op_class::MemWrite 77961520 14.75% 100.00% # Class of executed instruction +system.cpu1.committedInsts 441187041 # Number of instructions committed +system.cpu1.committedOps 519063105 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 477531543 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 364386 # Number of float alu accesses +system.cpu1.num_func_calls 26570520 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 66815511 # number of instructions that are conditional controls +system.cpu1.num_int_insts 477531543 # number of integer instructions +system.cpu1.num_fp_insts 364386 # number of float instructions +system.cpu1.num_int_register_reads 690361032 # number of times the integer registers were read +system.cpu1.num_int_register_writes 378560518 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 602629 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 273816 # number of times the floating registers were written +system.cpu1.num_cc_register_reads 113424708 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 113111436 # number of times the CC registers were written +system.cpu1.num_mem_refs 159443034 # number of memory refs +system.cpu1.num_load_insts 83763663 # Number of load instructions +system.cpu1.num_store_insts 75679371 # Number of store instructions +system.cpu1.num_idle_cycles 93795188251.508850 # Number of idle cycles +system.cpu1.num_busy_cycles 1026375051.491154 # Number of busy cycles +system.cpu1.not_idle_fraction 0.010824 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.989176 # Percentage of idle cycles +system.cpu1.Branches 98214896 # Number of branches fetched +system.cpu1.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 358777055 69.08% 69.08% # Class of executed instruction +system.cpu1.op_class::IntMult 1052972 0.20% 69.28% # Class of executed instruction +system.cpu1.op_class::IntDiv 61499 0.01% 69.29% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 69.29% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 69.29% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 69.29% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 69.29% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 69.29% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 69.29% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 69.29% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 69.29% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 69.29% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 69.29% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 69.29% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 69.29% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 69.29% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 69.29% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 69.29% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.29% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 69.29% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 69.29% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.29% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 69.29% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 69.29% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.29% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 35293 0.01% 69.30% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 69.30% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.30% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.30% # Class of executed instruction +system.cpu1.op_class::MemRead 83763663 16.13% 85.43% # Class of executed instruction +system.cpu1.op_class::MemWrite 75679371 14.57% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 528415149 # Class of executed instruction +system.cpu1.op_class::total 519369853 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 13701 # number of quiesce instructions executed -system.cpu1.dcache.tags.replacements 5194711 # number of replacements -system.cpu1.dcache.tags.tagsinuse 457.134068 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 157559099 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 5195223 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 30.327687 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 8367548601000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 457.134068 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.892840 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.892840 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 67 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 415 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 331059949 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 331059949 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 79405575 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 79405575 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 74066119 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 74066119 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 191889 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 191889 # number of SoftPFReq hits -system.cpu1.dcache.WriteInvalidateReq_hits::cpu1.data 197632 # number of WriteInvalidateReq hits -system.cpu1.dcache.WriteInvalidateReq_hits::total 197632 # number of WriteInvalidateReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1669680 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 1669680 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1654141 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 1654141 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 153471694 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 153471694 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 153663583 # number of overall hits -system.cpu1.dcache.overall_hits::total 153663583 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 2946837 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 2946837 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 1283113 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 1283113 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 571898 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 571898 # number of SoftPFReq misses -system.cpu1.dcache.WriteInvalidateReq_misses::cpu1.data 550709 # number of WriteInvalidateReq misses -system.cpu1.dcache.WriteInvalidateReq_misses::total 550709 # number of WriteInvalidateReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 171203 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 171203 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 185528 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 185528 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 4229950 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 4229950 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 4801848 # number of overall misses -system.cpu1.dcache.overall_misses::total 4801848 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 41215882509 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 41215882509 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 19312866378 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 19312866378 # number of WriteReq miss cycles -system.cpu1.dcache.WriteInvalidateReq_miss_latency::cpu1.data 6595698094 # number of WriteInvalidateReq miss cycles -system.cpu1.dcache.WriteInvalidateReq_miss_latency::total 6595698094 # number of WriteInvalidateReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2383654561 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 2383654561 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 3901847697 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 3901847697 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1095500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1095500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 60528748887 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 60528748887 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 60528748887 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 60528748887 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 82352412 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 82352412 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 75349232 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 75349232 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 763787 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 763787 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.data 748341 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu1.dcache.WriteInvalidateReq_accesses::total 748341 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1840883 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 1840883 # number of LoadLockedReq accesses(hits+misses) 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average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 21031.044893 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 21031.044893 # average StoreCondReq miss latency +system.cpu1.kern.inst.quiesce 13999 # number of quiesce instructions executed +system.cpu1.dcache.tags.replacements 4977655 # number of replacements +system.cpu1.dcache.tags.tagsinuse 421.597899 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 154271186 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 4978165 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 30.989569 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 8379002972500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 421.597899 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.823433 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.823433 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 442 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 323862009 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 323862009 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 78232018 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 78232018 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 71864508 # number of WriteReq hits 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miss cycles +system.cpu1.dcache.WriteInvalidateReq_miss_latency::total 12119187041 # number of WriteInvalidateReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2308132257 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 2308132257 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4261474455 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 4261474455 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1966000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1966000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 59961592307 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 59961592307 # number of demand (read+write) miss cycles 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accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1874166 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 1874166 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1872599 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 1872599 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 154202419 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 154202419 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 154969001 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 154969001 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.035388 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.035388 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.016906 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.016906 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.749932 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.749932 # miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteInvalidateReq_miss_rate::cpu1.data 0.689160 # miss rate for WriteInvalidateReq accesses +system.cpu1.dcache.WriteInvalidateReq_miss_rate::total 0.689160 # miss rate for WriteInvalidateReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.086146 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.086146 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.106476 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.106476 # miss rate for StoreCondReq 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12605.302976 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14603.788337 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 14603.788337 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 12810.179230 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 12810.179230 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1499,92 +1712,92 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 3397427 # number of writebacks -system.cpu1.dcache.writebacks::total 3397427 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 14736 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 14736 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 407 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 407 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 48814 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 48814 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 15143 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 15143 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 15143 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 15143 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2932101 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 2932101 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1282706 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 1282706 # number of WriteReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 571898 # number of SoftPFReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::total 571898 # number of SoftPFReq MSHR misses -system.cpu1.dcache.WriteInvalidateReq_mshr_misses::cpu1.data 550709 # number of WriteInvalidateReq MSHR misses -system.cpu1.dcache.WriteInvalidateReq_mshr_misses::total 550709 # number of WriteInvalidateReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 122389 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 122389 # number of LoadLockedReq MSHR misses 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-system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 11612454284 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 11612454284 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 5490664906 # number of WriteInvalidateReq MSHR miss cycles -system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::total 5490664906 # number of WriteInvalidateReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1373965707 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1373965707 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 3521472303 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3521472303 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1037500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1037500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 51359578044 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 51359578044 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 62972032328 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 62972032328 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3972621225 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 3972621225 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 3807943973 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 3807943973 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 7780565198 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 7780565198 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035604 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035604 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.017023 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.017023 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.748766 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.748766 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.735906 # mshr miss rate for WriteInvalidateReq accesses -system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.735906 # mshr miss rate for WriteInvalidateReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.066484 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.066484 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.100849 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.100849 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026726 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.026726 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.030207 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.030207 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11822.914496 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11822.914496 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 13014.360756 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 13014.360756 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 20305.114346 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 20305.114346 # average SoftPFReq mshr miss latency -system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 9970.174640 # average WriteInvalidateReq mshr miss latency -system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 9970.174640 # average WriteInvalidateReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11226.218917 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11226.218917 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 18980.813155 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 18980.813155 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 3230902 # number of writebacks +system.cpu1.dcache.writebacks::total 3230902 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 11797 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 11797 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 280 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 280 # number of WriteReq MSHR hits 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+system.cpu1.dcache.SoftPFReq_mshr_misses::total 574884 # number of SoftPFReq MSHR misses +system.cpu1.dcache.WriteInvalidateReq_mshr_misses::cpu1.data 468795 # number of WriteInvalidateReq MSHR misses +system.cpu1.dcache.WriteInvalidateReq_mshr_misses::total 468795 # number of WriteInvalidateReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 118652 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 118652 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 199386 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 199386 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 4093816 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 4093816 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 4668700 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 4668700 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 33045194740 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 33045194740 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 18021373474 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 18021373474 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 10397149259 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 10397149259 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 11178014959 # number of WriteInvalidateReq MSHR miss cycles +system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::total 11178014959 # number of WriteInvalidateReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1426804491 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1426804491 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 3852246545 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3852246545 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1872000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1872000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 51066568214 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 51066568214 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 61463717473 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 61463717473 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 4074474250 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 4074474250 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 3958410750 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 3958410750 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 8032885000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 8032885000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035243 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035243 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.016902 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.016902 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.749932 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.749932 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.689160 # mshr miss rate for WriteInvalidateReq accesses +system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.689160 # mshr miss rate for WriteInvalidateReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.063309 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.063309 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.106476 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.106476 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026548 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.026548 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.030127 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.030127 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11561.350275 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11561.350275 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 14585.485290 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 14585.485290 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 18085.647294 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 18085.647294 # average SoftPFReq mshr miss latency +system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 23844.142875 # average WriteInvalidateReq mshr miss latency +system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 23844.142875 # average WriteInvalidateReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12025.119602 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12025.119602 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 19320.546804 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 19320.546804 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12185.511233 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12185.511233 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 13155.611705 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 13155.611705 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12474.075096 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12474.075096 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 13165.060396 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 13165.060396 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1592,59 +1805,59 @@ system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 5786522 # number of replacements -system.cpu1.icache.tags.tagsinuse 496.339295 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 442153368 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 5787034 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 76.404142 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 8367526246000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 496.339295 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.969413 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.969413 # Average percentage of cache occupancy +system.cpu1.icache.tags.replacements 4937125 # number of replacements +system.cpu1.icache.tags.tagsinuse 496.391317 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 436556038 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 4937637 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 88.413960 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 8378975635000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 496.391317 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.969514 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.969514 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 339 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 108 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 7 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 262 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 239 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 901667853 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 901667853 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 442153368 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 442153368 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 442153368 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 442153368 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 442153368 # number of overall hits -system.cpu1.icache.overall_hits::total 442153368 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 5787039 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 5787039 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 5787039 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 5787039 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 5787039 # number of overall misses -system.cpu1.icache.overall_misses::total 5787039 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 50052191468 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 50052191468 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 50052191468 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 50052191468 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 50052191468 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 50052191468 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 447940407 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 447940407 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 447940407 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 447940407 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 447940407 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 447940407 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.012919 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.012919 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.012919 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.012919 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.012919 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.012919 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8649.015752 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 8649.015752 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8649.015752 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 8649.015752 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8649.015752 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 8649.015752 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 887925002 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 887925002 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 436556038 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 436556038 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 436556038 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 436556038 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 436556038 # number of overall hits +system.cpu1.icache.overall_hits::total 436556038 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 4937642 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 4937642 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 4937642 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 4937642 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 4937642 # number of overall misses +system.cpu1.icache.overall_misses::total 4937642 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 50835870381 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 50835870381 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 50835870381 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 50835870381 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 50835870381 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 50835870381 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 441493680 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 441493680 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 441493680 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 441493680 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 441493680 # number of overall (read+write) accesses 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overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10295.576387 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 10295.576387 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1653,384 +1866,377 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 5787039 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 5787039 # number of ReadReq MSHR misses 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0.011184 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8792.521537 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8792.521537 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8792.521537 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 8792.521537 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8792.521537 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 8792.521537 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall 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per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 65.675774 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 758.406628 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.data 2477.157386 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 6824.630764 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.216571 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.003566 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.004009 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.046289 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.151194 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.416542 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.838171 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 8592 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 40 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 7474 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::0 93 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 541 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 2721 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 4842 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 395 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 15 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 20 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 810 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 3409 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 2963 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 229 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.524414 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.002441 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.456177 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 249010603 # Number of tag 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0.099533 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.240390 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.153988 # mshr miss rate for ReadReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.087836 # mshr miss rate for WriteInvalidateReq accesses -system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.087836 # mshr miss rate for WriteInvalidateReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.591620 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.591620 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.808666 # mshr miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.808666 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.611609 # mshr miss rate for WriteInvalidateReq accesses +system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.611609 # mshr miss rate for WriteInvalidateReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.682408 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.682408 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.840661 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.840661 # mshr miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.176371 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.176371 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.051364 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.057789 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.026944 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.237888 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::total 0.119344 # mshr miss rate for demand accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.051364 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.057789 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.026944 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.237888 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.193226 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.193226 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.041303 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.052181 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.099533 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.229620 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.158158 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.041303 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.052181 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.099533 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.229620 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.370592 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 23590.774025 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 26697.193393 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 21030.079325 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 22855.890509 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 22639.849443 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 25466.057437 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 25466.057437 # average HardPFReq mshr miss latency -system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 15325.803477 # average WriteInvalidateReq mshr miss latency -system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 15325.803477 # average WriteInvalidateReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 16571.950039 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16571.950039 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 13824.139322 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13824.139322 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 201375 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 201375 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 27369.696466 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 27369.696466 # average ReadExReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 23590.774025 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 26697.193393 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 21030.079325 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 23632.313965 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 23342.822566 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 23590.774025 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 26697.193393 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 21030.079325 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 23632.313965 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 25466.057437 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 24782.300723 # average overall mshr miss latency +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.222784 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 22828.151261 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 24354.897355 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 22000.738481 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 22345.362493 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 22234.428550 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 46551.597527 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 46551.597527 # average HardPFReq mshr miss latency +system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 27079.147948 # average WriteInvalidateReq mshr miss latency +system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 27079.147948 # average WriteInvalidateReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 16917.663474 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16917.663474 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 13665.224287 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13665.224287 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 249333.166667 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 249333.166667 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 30989.120825 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 30989.120825 # average ReadExReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 22828.151261 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 24354.897355 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 22000.738481 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 24006.292202 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 23371.034447 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 22828.151261 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 24354.897355 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 22000.738481 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 24006.292202 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 46551.597527 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 30095.390338 # average overall mshr miss latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -2040,65 +2246,66 @@ system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.toL2Bus.trans_dist::ReadReq 13482596 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 10019474 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 22090 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 22090 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::Writeback 3397427 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 3948207 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 669175 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp 549365 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 394300 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 332875 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 429984 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 28 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 53 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 1203009 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 1101184 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 11574298 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 14922836 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 373561 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 511408 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 27382103 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 370370936 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 560535931 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1349320 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1724480 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 933980667 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 8332859 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 23404111 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 5.344949 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.475352 # Request fanout histogram +system.cpu1.toL2Bus.trans_dist::ReadReq 11132088 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 9059631 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 23142 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 23142 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::Writeback 3230902 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 957658 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 1110389 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp 467130 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 407372 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 365584 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 452132 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 59 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 100 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 1208854 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 1057926 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 9875504 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 14402767 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 299311 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 504421 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 25082003 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 316009528 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 537745480 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1072416 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1728704 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 856556128 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 4579678 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 18388489 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 5.234421 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.423637 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::5 15330876 65.51% 65.51% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::6 8073235 34.49% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::5 14077834 76.56% 76.56% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::6 4310655 23.44% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 23404111 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 11646725084 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 18388489 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 10772824519 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 158989494 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 181931492 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 8682146940 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 7414134377 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 7623277083 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 7417250282 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 205120292 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 165377004 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 296049290 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 288475000 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 40487 # Transaction distribution -system.iobus.trans_dist::ReadResp 40487 # Transaction distribution -system.iobus.trans_dist::WriteReq 137083 # Transaction distribution -system.iobus.trans_dist::WriteResp 30163 # Transaction distribution +system.iobus.trans_dist::ReadReq 40416 # Transaction distribution +system.iobus.trans_dist::ReadResp 40416 # Transaction distribution +system.iobus.trans_dist::WriteReq 136984 # Transaction distribution +system.iobus.trans_dist::WriteResp 30064 # Transaction distribution system.iobus.trans_dist::WriteInvalidateResp 106920 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 48390 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 48038 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) @@ -2108,18 +2315,18 @@ system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29756 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29704 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 123480 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231580 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 231580 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 123076 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231644 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231644 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 355140 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 48410 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 354800 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 48058 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -2129,18 +2336,18 @@ system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17674 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17645 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 156518 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7351088 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7351088 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 156137 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7351344 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7351344 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7509692 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 36789000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7509567 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 36527000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -2160,7 +2367,7 @@ system.iobus.reqLayer16.occupancy 12000 # La system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 22103000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 22064000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) @@ -2168,71 +2375,71 @@ system.iobus.reqLayer25.occupancy 32658000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 1044839337 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 1044902599 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 93320000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 93015000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 179372271 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 179432954 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 297000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 115786 # number of replacements -system.iocache.tags.tagsinuse 11.223287 # Cycle average of tags in use +system.iocache.tags.replacements 115804 # number of replacements +system.iocache.tags.tagsinuse 11.285754 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115802 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115820 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 9123835798000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 7.412555 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 3.810732 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.463285 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.238171 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.701455 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 9175904776000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.836841 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 7.448912 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.239803 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.465557 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.705360 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1042467 # Number of tag accesses -system.iocache.tags.data_accesses 1042467 # Number of data accesses +system.iocache.tags.tag_accesses 1042755 # Number of tag accesses +system.iocache.tags.data_accesses 1042755 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8870 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8907 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8902 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8939 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteInvalidateReq_misses::realview.ide 106920 # number of WriteInvalidateReq misses system.iocache.WriteInvalidateReq_misses::total 106920 # number of WriteInvalidateReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8870 # number of demand (read+write) misses -system.iocache.demand_misses::total 8910 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8902 # number of demand (read+write) misses +system.iocache.demand_misses::total 8942 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8870 # number of overall misses -system.iocache.overall_misses::total 8910 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ethernet 5627000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1958941092 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1964568092 # number of ReadReq miss cycles +system.iocache.overall_misses::realview.ide 8902 # number of overall misses +system.iocache.overall_misses::total 8942 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ethernet 5707000 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1942659591 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1948366591 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 357000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 357000 # number of WriteReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::realview.ide 28897474974 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 28897474974 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 5984000 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 1958941092 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 1964925092 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 5984000 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 1958941092 # number of overall miss cycles -system.iocache.overall_miss_latency::total 1964925092 # number of overall miss cycles +system.iocache.WriteInvalidateReq_miss_latency::realview.ide 28987663054 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 28987663054 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 6064000 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 1942659591 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1948723591 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 6064000 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 1942659591 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1948723591 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8870 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8907 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8902 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8939 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::realview.ide 106920 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::total 106920 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8870 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8910 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8902 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8942 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8870 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8910 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8902 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8942 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -2246,55 +2453,55 @@ system.iocache.demand_miss_rate::total 1 # mi system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 152081.081081 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 220850.179481 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 220564.510161 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 154243.243243 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 218227.318692 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 217962.478018 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 119000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 119000 # average WriteReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 270271.932043 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 270271.932043 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 149600 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 220850.179481 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 220530.313356 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 149600 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 220850.179481 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 220530.313356 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 225288 # number of cycles access was blocked +system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 271115.441957 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 271115.441957 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 151600 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 218227.318692 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 217929.276560 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 151600 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 218227.318692 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 217929.276560 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 228501 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 27401 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 27689 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8.221890 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 8.252411 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 106886 # number of writebacks -system.iocache.writebacks::total 106886 # number of writebacks +system.iocache.writebacks::writebacks 106887 # number of writebacks +system.iocache.writebacks::total 106887 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8870 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8907 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8902 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8939 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 106920 # number of WriteInvalidateReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::total 106920 # number of WriteInvalidateReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 8870 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 8910 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 8902 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 8942 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 8870 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 8910 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3703000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1497575112 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1501278112 # number of ReadReq MSHR miss cycles +system.iocache.overall_mshr_misses::realview.ide 8902 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 8942 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3783000 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1479616613 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1483399613 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 23337113496 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 23337113496 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ethernet 3904000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 1497575112 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 1501479112 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ethernet 3904000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 1497575112 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 1501479112 # number of overall MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 23427435940 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 23427435940 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ethernet 3984000 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 1479616613 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 1483600613 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ethernet 3984000 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 1479616613 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 1483600613 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -2308,567 +2515,560 @@ system.iocache.demand_mshr_miss_rate::total 1 # system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 100081.081081 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 168835.976550 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 168550.366229 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 102243.243243 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 166211.706695 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 165946.930641 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 218267.054770 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 218267.054770 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 97600 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 168835.976550 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 168516.174186 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 97600 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 168835.976550 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 168516.174186 # average overall mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 219111.821362 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 219111.821362 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 99600 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 166211.706695 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 165913.734399 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 99600 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 166211.706695 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 165913.734399 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 1310456 # number of replacements -system.l2c.tags.tagsinuse 64677.337118 # Cycle average of tags in use -system.l2c.tags.total_refs 7257968 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1373726 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 5.283418 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 5621833500 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 9998.305247 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 56.991260 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 77.146603 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 791.679733 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 4513.780403 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 23818.675732 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 150.211809 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 222.184258 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 784.998757 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 7219.989726 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 17043.373589 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.152562 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000870 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.001177 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.012080 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.068875 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.363444 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.002292 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.003390 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.011978 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.110168 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.260061 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.986898 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 38915 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 205 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 24150 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::0 26 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::1 26 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 487 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 8729 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 29647 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::3 17 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 188 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 21 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 161 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 550 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 5282 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 18136 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.593796 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.003128 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.368500 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 74054042 # Number of tag accesses -system.l2c.tags.data_accesses 74054042 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 5514 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 4407 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 131001 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 549137 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 1653135 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 7096 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 6374 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 146834 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 607953 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 1853450 # number of ReadReq hits -system.l2c.ReadReq_hits::total 4964901 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 2477309 # number of Writeback hits -system.l2c.Writeback_hits::total 2477309 # number of Writeback hits -system.l2c.WriteInvalidateReq_hits::cpu0.data 3452 # number of WriteInvalidateReq hits -system.l2c.WriteInvalidateReq_hits::cpu1.data 4029 # number of WriteInvalidateReq hits -system.l2c.WriteInvalidateReq_hits::total 7481 # number of WriteInvalidateReq hits -system.l2c.UpgradeReq_hits::cpu0.data 31717 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 34608 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 66325 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 7299 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 8593 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 15892 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 45918 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 59655 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 105573 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 5514 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 4407 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 131001 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 595055 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.l2cache.prefetcher 1653135 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 7096 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 6374 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 146834 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 667608 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.l2cache.prefetcher 1853450 # number of demand (read+write) hits -system.l2c.demand_hits::total 5070474 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 5514 # number of overall hits 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ReadReq misses -system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 698997 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 1304 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.itb.walker 1531 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 9213 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 99987 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 328949 # number of ReadReq misses -system.l2c.ReadReq_misses::total 1237733 # number of ReadReq misses -system.l2c.WriteInvalidateReq_misses::cpu0.data 9435 # number of WriteInvalidateReq misses -system.l2c.WriteInvalidateReq_misses::cpu1.data 3626 # number of WriteInvalidateReq misses -system.l2c.WriteInvalidateReq_misses::total 13061 # number of WriteInvalidateReq misses -system.l2c.UpgradeReq_misses::cpu0.data 30881 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 31286 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 62167 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 9976 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 9599 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 19575 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 38485 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 37338 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 75823 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.dtb.walker 569 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 656 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 9314 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 125698 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.l2cache.prefetcher 698997 # number of demand (read+write) misses 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ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 812177995 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 7981910698 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 38448513875 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 155563490387 # number of ReadReq miss cycles -system.l2c.WriteInvalidateReq_miss_latency::cpu0.data 1840421 # number of WriteInvalidateReq miss cycles -system.l2c.WriteInvalidateReq_miss_latency::cpu1.data 2071411 # number of WriteInvalidateReq miss cycles -system.l2c.WriteInvalidateReq_miss_latency::total 3911832 # number of WriteInvalidateReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 134255920 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 141850516 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 276106436 # number of UpgradeReq miss cycles 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(read+write) accesses -system.l2c.overall_accesses::cpu1.l2cache.prefetcher 2182399 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 6384030 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.093539 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.129567 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.066379 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.137052 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.297176 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.155238 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.193675 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.059040 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.141237 # miss rate for ReadReq accesses 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0.170604 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.150728 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.205757 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 81580.404218 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 85663.109756 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 90745.731265 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 81075.836687 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 143164.885379 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 80811.348926 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 81644.349445 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 88155.649083 # average ReadReq miss latency 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latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 5142.455568 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 5038.612771 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 74003.580564 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 73149.808908 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 73583.152381 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 81580.404218 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.itb.walker 85663.109756 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 90745.731265 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 78910.521591 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 143164.885379 # average overall miss latency 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blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 2392.943065 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 3574.441825 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 5977.605096 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.301650 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.003482 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.004999 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.067191 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.199529 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.217905 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.001239 # Average percentage of cache occupancy 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task id +system.l2c.tags.age_task_id_blocks_1023::3 3 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 259 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 29 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 239 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 991 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 9958 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 38095 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1022 0.173050 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1023 0.004013 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.752441 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 56299103 # Number of tag accesses +system.l2c.tags.data_accesses 56299103 # Number of data accesses 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(read+write) hits +system.l2c.demand_hits::cpu0.inst 461305 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 613871 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.l2cache.prefetcher 286198 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 4527 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 3561 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 447471 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 522616 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.l2cache.prefetcher 267354 # number of demand (read+write) hits +system.l2c.demand_hits::total 2616823 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 5350 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 4570 # number of overall hits +system.l2c.overall_hits::cpu0.inst 461305 # number of overall hits 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+system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 20243.971628 # average WriteInvalidateReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total 21892.569988 # average WriteInvalidateReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10081.122986 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10172.643319 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10127.734904 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10094.514924 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10170.084593 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10131.367291 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 66785.676932 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 63285.951301 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 65436.965728 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 68440.219644 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 69325.509796 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 64762.763882 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 69412.984539 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 115369.864860 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 68654.805769 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 70250.533120 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 64112.168470 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 67729.415418 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 117769.320522 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 90866.823975 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 68440.219644 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 69325.509796 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 64762.763882 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 69412.984539 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 115369.864860 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 68654.805769 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 70250.533120 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 64112.168470 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 67729.415418 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 117769.320522 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 90866.823975 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -2883,58 +3083,58 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 1327465 # Transaction distribution -system.membus.trans_dist::ReadResp 1327465 # Transaction distribution -system.membus.trans_dist::WriteReq 37863 # Transaction distribution -system.membus.trans_dist::WriteResp 37863 # Transaction distribution -system.membus.trans_dist::Writeback 1017207 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 119813 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 119813 # Transaction distribution -system.membus.trans_dist::UpgradeReq 367379 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 281461 # Transaction distribution -system.membus.trans_dist::UpgradeResp 85028 # Transaction distribution -system.membus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution -system.membus.trans_dist::ReadExReq 87184 # Transaction distribution -system.membus.trans_dist::ReadExResp 72708 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 123480 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 841910 # Transaction distribution +system.membus.trans_dist::ReadResp 841910 # Transaction distribution +system.membus.trans_dist::WriteReq 38471 # Transaction distribution +system.membus.trans_dist::WriteResp 38471 # Transaction distribution +system.membus.trans_dist::Writeback 1161772 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 665270 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 665270 # Transaction distribution +system.membus.trans_dist::UpgradeReq 386597 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 321242 # Transaction distribution +system.membus.trans_dist::UpgradeResp 114625 # Transaction distribution +system.membus.trans_dist::SCUpgradeFailReq 2 # Transaction distribution +system.membus.trans_dist::ReadExReq 138806 # Transaction distribution +system.membus.trans_dist::ReadExResp 121371 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 123076 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 92 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 22714 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4395675 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4541961 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 336541 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 336541 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4878502 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 156518 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 25442 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4847759 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4996369 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 336372 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 336372 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5332741 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 156137 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 204 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 45428 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 143082804 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 143284954 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14125504 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 14125504 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 157410458 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 581037 # Total snoops (count) -system.membus.snoop_fanout::samples 3119395 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 50884 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 159245812 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 159453037 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14112640 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 14112640 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 173565677 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 613627 # Total snoops (count) +system.membus.snoop_fanout::samples 3433927 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 3119395 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 3433927 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 3119395 # Request fanout histogram -system.membus.reqLayer0.occupancy 101251489 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 3433927 # Request fanout histogram +system.membus.reqLayer0.occupancy 100976496 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 55500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 19693498 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 22065500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 11963097483 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 18062213474 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 12443113804 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 9212060141 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 187409729 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 187637046 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted @@ -2978,45 +3178,45 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 13 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.trans_dist::ReadReq 7096727 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 7089473 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 37863 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 37863 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 2477309 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 127465 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateResp 20542 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 430421 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 297353 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 727774 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 53 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 53 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 228196 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 228196 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8832957 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 8435767 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 17268724 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 294458407 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 274483891 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 568942298 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 1532220 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 10576474 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.010952 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.104077 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 4185645 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 4178412 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 38471 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 38471 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 2302237 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 921111 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateResp 814190 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 436280 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 333774 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 770054 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 100 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 100 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 280654 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 280654 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 7279651 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 5709072 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 12988723 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 243910125 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 179631296 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 423541421 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 1593139 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 8378399 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.013829 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.116780 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 10460641 98.90% 98.90% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 115833 1.10% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 8262536 98.62% 98.62% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 115863 1.38% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 10576474 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 15316484616 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 8378399 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 16938572035 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 7440499 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 7678500 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 16737915607 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 11018810399 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 16438547163 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 9692180196 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt index e087cdc41..11eb5dd0c 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt @@ -1,138 +1,138 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 51.821204 # Number of seconds simulated -sim_ticks 51821203872000 # Number of ticks simulated -final_tick 51821203872000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 51.821157 # Number of seconds simulated +sim_ticks 51821157171000 # Number of ticks simulated +final_tick 51821157171000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 797175 # Simulator instruction rate (inst/s) -host_op_rate 936716 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 46008450754 # Simulator tick rate (ticks/s) -host_mem_usage 656028 # Number of bytes of host memory used -host_seconds 1126.34 # Real time elapsed on the host -sim_insts 897890420 # Number of instructions simulated -sim_ops 1055061464 # Number of ops (including micro ops) simulated +host_inst_rate 734878 # Simulator instruction rate (inst/s) +host_op_rate 863519 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 42416153440 # Simulator tick rate (ticks/s) +host_mem_usage 712380 # Number of bytes of host memory used +host_seconds 1221.73 # Real time elapsed on the host +sim_insts 897823750 # Number of instructions simulated +sim_ops 1054987960 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.dtb.walker 274944 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 280896 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 5219828 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 52654408 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 402752 # Number of bytes read from this memory -system.physmem.bytes_read::total 58832828 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 5219828 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 5219828 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 79485888 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.dtb.walker 267456 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 270528 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 5250612 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 52674824 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 383808 # Number of bytes read from this memory +system.physmem.bytes_read::total 58847228 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 5250612 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 5250612 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 79637568 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory -system.physmem.bytes_written::total 79506468 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 4296 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 4389 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 121967 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 822738 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6293 # Number of read requests responded to by this memory -system.physmem.num_reads::total 959683 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1241967 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 79658148 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 4179 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 4227 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 122448 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 823057 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 5997 # Number of read requests responded to by this memory +system.physmem.num_reads::total 959908 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1244337 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1244540 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 5306 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 5420 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 100728 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1016078 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 7772 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1135304 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 100728 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 100728 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1533849 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1246910 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 5161 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 5220 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 101322 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1016473 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 7406 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1135583 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 101322 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 101322 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1536777 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 397 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1534246 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1533849 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 5306 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 5420 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 100728 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1016476 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 7772 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2669550 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 959683 # Number of read requests accepted -system.physmem.writeReqs 1860672 # Number of write requests accepted -system.physmem.readBursts 959683 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1860672 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 61376064 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 43648 # Total number of bytes read from write queue -system.physmem.bytesWritten 118595648 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 58832828 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 118938916 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 682 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 7593 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 36288 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 56975 # Per bank write bursts -system.physmem.perBankRdBursts::1 58359 # Per bank write bursts -system.physmem.perBankRdBursts::2 58716 # Per bank write bursts -system.physmem.perBankRdBursts::3 57264 # Per bank write bursts -system.physmem.perBankRdBursts::4 61545 # Per bank write bursts -system.physmem.perBankRdBursts::5 66145 # Per bank write bursts -system.physmem.perBankRdBursts::6 57228 # Per bank write bursts -system.physmem.perBankRdBursts::7 52937 # Per bank write bursts -system.physmem.perBankRdBursts::8 52189 # Per bank write bursts -system.physmem.perBankRdBursts::9 99547 # Per bank write bursts -system.physmem.perBankRdBursts::10 57680 # Per bank write bursts -system.physmem.perBankRdBursts::11 61393 # Per bank write bursts -system.physmem.perBankRdBursts::12 54506 # Per bank write bursts -system.physmem.perBankRdBursts::13 60286 # Per bank write bursts -system.physmem.perBankRdBursts::14 51564 # Per bank write bursts -system.physmem.perBankRdBursts::15 52667 # Per bank write bursts -system.physmem.perBankWrBursts::0 114739 # Per bank write bursts -system.physmem.perBankWrBursts::1 115397 # Per bank write bursts -system.physmem.perBankWrBursts::2 117633 # Per bank write bursts -system.physmem.perBankWrBursts::3 119136 # Per bank write bursts -system.physmem.perBankWrBursts::4 120318 # Per bank write bursts -system.physmem.perBankWrBursts::5 121968 # Per bank write bursts -system.physmem.perBankWrBursts::6 116613 # Per bank write bursts -system.physmem.perBankWrBursts::7 113695 # Per bank write bursts -system.physmem.perBankWrBursts::8 109286 # Per bank write bursts -system.physmem.perBankWrBursts::9 116370 # Per bank write bursts -system.physmem.perBankWrBursts::10 115629 # Per bank write bursts -system.physmem.perBankWrBursts::11 118249 # Per bank write bursts -system.physmem.perBankWrBursts::12 111968 # Per bank write bursts -system.physmem.perBankWrBursts::13 117797 # Per bank write bursts -system.physmem.perBankWrBursts::14 110347 # Per bank write bursts -system.physmem.perBankWrBursts::15 113912 # Per bank write bursts +system.physmem.bw_write::total 1537174 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1536777 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 5161 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 5220 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 101322 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1016870 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 7406 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2672757 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 959908 # Number of read requests accepted +system.physmem.writeReqs 1865455 # Number of write requests accepted +system.physmem.readBursts 959908 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1865455 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 61382336 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 51776 # Total number of bytes read from write queue +system.physmem.bytesWritten 118954432 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 58847228 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 119245028 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 809 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 6774 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 36275 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 56974 # Per bank write bursts +system.physmem.perBankRdBursts::1 60608 # Per bank write bursts +system.physmem.perBankRdBursts::2 56247 # Per bank write bursts +system.physmem.perBankRdBursts::3 58787 # Per bank write bursts +system.physmem.perBankRdBursts::4 55621 # Per bank write bursts +system.physmem.perBankRdBursts::5 61105 # Per bank write bursts +system.physmem.perBankRdBursts::6 53454 # Per bank write bursts +system.physmem.perBankRdBursts::7 55202 # Per bank write bursts +system.physmem.perBankRdBursts::8 54549 # Per bank write bursts +system.physmem.perBankRdBursts::9 101006 # Per bank write bursts +system.physmem.perBankRdBursts::10 57136 # Per bank write bursts +system.physmem.perBankRdBursts::11 59250 # Per bank write bursts +system.physmem.perBankRdBursts::12 54470 # Per bank write bursts +system.physmem.perBankRdBursts::13 61564 # Per bank write bursts +system.physmem.perBankRdBursts::14 57688 # Per bank write bursts +system.physmem.perBankRdBursts::15 55438 # Per bank write bursts +system.physmem.perBankWrBursts::0 113578 # Per bank write bursts +system.physmem.perBankWrBursts::1 118177 # Per bank write bursts +system.physmem.perBankWrBursts::2 119014 # Per bank write bursts +system.physmem.perBankWrBursts::3 122732 # Per bank write bursts +system.physmem.perBankWrBursts::4 115108 # Per bank write bursts +system.physmem.perBankWrBursts::5 118421 # Per bank write bursts +system.physmem.perBankWrBursts::6 110433 # Per bank write bursts +system.physmem.perBankWrBursts::7 110649 # Per bank write bursts +system.physmem.perBankWrBursts::8 111009 # Per bank write bursts +system.physmem.perBankWrBursts::9 115530 # Per bank write bursts +system.physmem.perBankWrBursts::10 116272 # Per bank write bursts +system.physmem.perBankWrBursts::11 116171 # Per bank write bursts +system.physmem.perBankWrBursts::12 116950 # Per bank write bursts +system.physmem.perBankWrBursts::13 121923 # Per bank write bursts +system.physmem.perBankWrBursts::14 117171 # Per bank write bursts +system.physmem.perBankWrBursts::15 115525 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 1 # Number of times write queue was full causing retry -system.physmem.totGap 51821201316000 # Total gap between requests +system.physmem.totGap 51821154615000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 43101 # Read request sizes (log2) system.physmem.readPktSize::3 13 # Read request sizes (log2) system.physmem.readPktSize::4 2 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 916567 # Read request sizes (log2) +system.physmem.readPktSize::6 916792 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 1 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1858099 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 925038 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 28111 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 2104 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 593 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 706 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 405 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 375 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 306 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 221 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 147 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 137 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 124 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 112 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 112 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 109 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 100 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 90 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 88 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 64 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 56 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 3 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1862882 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 923488 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 30071 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 2080 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 548 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 693 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 382 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 338 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 271 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 197 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 132 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 122 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 113 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 103 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 102 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 100 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 96 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 84 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 78 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 56 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 45 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -159,120 +159,140 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 58079 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 70983 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 101652 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 104342 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 108305 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 122410 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 126456 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 111805 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 113098 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 110863 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 108761 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 105735 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 102887 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 101533 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 96838 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 95973 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 95806 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 94380 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 3424 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 2906 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 2427 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 2200 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 1880 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 1660 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 1358 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 1197 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 1022 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 916 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 704 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 565 # What write queue length does an incoming req see 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+system.physmem.wrQLenPdf::55 51 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 35 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 17 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 1 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 617611 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 291.399266 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 166.446996 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 330.841680 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 256797 41.58% 41.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 151085 24.46% 66.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 51876 8.40% 74.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 29038 4.70% 79.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 19766 3.20% 82.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 13229 2.14% 84.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 10059 1.63% 86.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 9064 1.47% 87.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 76697 12.42% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 617611 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 92036 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 10.419705 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 106.178395 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 92034 100.00% 100.00% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 618930 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 291.368084 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 166.608476 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 330.498173 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 256436 41.43% 41.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 152224 24.59% 66.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 51996 8.40% 74.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 28892 4.67% 79.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 20098 3.25% 82.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 13547 2.19% 84.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 10018 1.62% 86.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 9306 1.50% 87.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 76413 12.35% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 618930 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 92468 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 10.372118 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 105.903641 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 92466 100.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::20480-21503 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::23552-24575 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 92036 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 92036 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.134045 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 19.130429 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 10.695121 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 84651 91.98% 91.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 3801 4.13% 96.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 1276 1.39% 97.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 446 0.48% 97.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 607 0.66% 98.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 136 0.15% 98.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 198 0.22% 99.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 105 0.11% 99.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 166 0.18% 99.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 53 0.06% 99.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 197 0.21% 99.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 35 0.04% 99.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-119 54 0.06% 99.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-127 56 0.06% 99.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 137 0.15% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-143 24 0.03% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-151 33 0.04% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-159 9 0.01% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-167 16 0.02% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 5 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 6 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-191 4 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-199 2 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-207 2 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-215 2 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-223 8 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-231 2 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::232-239 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::240-247 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::248-255 2 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::272-279 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 92036 # Writes before turning the bus around for reads -system.physmem.totQLat 12714966775 # Total ticks spent queuing -system.physmem.totMemAccLat 30696235525 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 4795005000 # Total ticks spent in databus transfers -system.physmem.avgQLat 13258.55 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 92468 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 92468 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.100608 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 19.118632 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 10.444453 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 55053 59.54% 59.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 30512 33.00% 92.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 2134 2.31% 94.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 1149 1.24% 96.09% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 862 0.93% 97.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 455 0.49% 97.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 271 0.29% 97.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 154 0.17% 97.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 523 0.57% 98.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 85 0.09% 98.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 63 0.07% 98.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 90 0.10% 98.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 138 0.15% 98.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 53 0.06% 99.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 45 0.05% 99.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 77 0.08% 99.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 126 0.14% 99.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 47 0.05% 99.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 24 0.03% 99.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 42 0.05% 99.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 157 0.17% 99.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 6 0.01% 99.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 21 0.02% 99.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 16 0.02% 99.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 59 0.06% 99.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 9 0.01% 99.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 28 0.03% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 35 0.04% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 128 0.14% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 15 0.02% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 2 0.00% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 6 0.01% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 16 0.02% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 15 0.02% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 3 0.00% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 7 0.01% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 10 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 3 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-171 3 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 5 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 3 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::180-183 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::188-191 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-195 2 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::196-199 4 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-203 2 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-211 3 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::212-215 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::216-219 2 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::228-231 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::248-251 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 92468 # Writes before turning the bus around for reads +system.physmem.totQLat 12424177254 # Total ticks spent queuing +system.physmem.totMemAccLat 30407283504 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 4795495000 # Total ticks spent in databus transfers +system.physmem.avgQLat 12954.01 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 32008.55 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 31704.01 # Average memory access latency per DRAM burst system.physmem.avgRdBW 1.18 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.29 # Average achieved write bandwidth in MiByte/s +system.physmem.avgWrBW 2.30 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 1.14 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 2.30 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s @@ -280,36 +300,41 @@ system.physmem.busUtil 0.03 # Da system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 23.23 # Average write queue length when enqueuing -system.physmem.readRowHits 722338 # Number of row buffer hits during reads -system.physmem.writeRowHits 1472108 # Number of row buffer hits during writes -system.physmem.readRowHitRate 75.32 # Row buffer hit rate for reads +system.physmem.avgWrQLen 24.29 # Average write queue length when enqueuing +system.physmem.readRowHits 722238 # Number of row buffer hits during reads +system.physmem.writeRowHits 1476593 # Number of row buffer hits during writes +system.physmem.readRowHitRate 75.30 # Row buffer hit rate for reads system.physmem.writeRowHitRate 79.44 # Row buffer hit rate for writes -system.physmem.avgGap 18373999.48 # Average gap between requests -system.physmem.pageHitRate 78.04 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 49686658091000 # Time in different power states -system.physmem.memoryStateTime::REF 1730423760000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 404121645500 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 2414648880 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 2254490280 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 1317516750 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 1230128625 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 3659518200 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 3820650600 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 6087953520 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 5919855840 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 3384708874560 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 3384708874560 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 1312804436175 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 1305168623550 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 29941137312000 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 29947835393250 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 34652130260085 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 34650938016705 # Total energy per rank (pJ) -system.physmem.averagePower::0 668.686370 # Core power per rank (mW) -system.physmem.averagePower::1 668.663363 # Core power per rank (mW) +system.physmem.avgGap 18341414.75 # Average gap between requests +system.physmem.pageHitRate 78.03 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 2336584320 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1274922000 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 3572345400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 6014165760 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3384705823200 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1308692927565 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 29944715868000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 34651312636245 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.671195 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 49815023694250 # Time in different power states +system.physmem_0.memoryStateTime::REF 1730422200000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 275710901250 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 2342526480 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1278164250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 3908587800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 6029970480 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3384705823200 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1310912306640 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 29942769044250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 34651946423100 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.683425 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 49811721549250 # Time in different power states +system.physmem_1.memoryStateTime::REF 1730422200000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 279009798250 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu.inst 96 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 132 # Number of bytes read from this memory @@ -333,6 +358,14 @@ system.cf0.dma_write_full_pages 1666 # Nu system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1669 # Number of DMA write transactions. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -354,27 +387,81 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 215397 # Table walker walks requested +system.cpu.dtb.walker.walksLong 215397 # Table walker walks initiated with long descriptors +system.cpu.dtb.walker.walksLongTerminationLevel::Level2 16603 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walksLongTerminationLevel::Level3 166513 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walksSquashedBefore 14 # Table walks squashed before starting +system.cpu.dtb.walker.walkWaitTime::samples 215383 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::mean 0.157858 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::stdev 54.935133 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0-2047 215381 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::10240-12287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::22528-24575 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::total 215383 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkCompletionTime::samples 183130 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 21825.061432 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 17519.574906 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 14463.524428 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::0-32767 181175 98.93% 98.93% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::32768-65535 4 0.00% 98.93% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::65536-98303 1496 0.82% 99.75% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::98304-131071 183 0.10% 99.85% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::131072-163839 74 0.04% 99.89% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::163840-196607 58 0.03% 99.92% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::196608-229375 49 0.03% 99.95% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::229376-262143 36 0.02% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::262144-294911 18 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::294912-327679 14 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::327680-360447 8 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::360448-393215 11 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::458752-491519 3 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::total 183130 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walksPending::samples 800972760 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::mean 2.488036 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::0 -1191876296 -148.80% -148.80% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::1 1992849056 248.80% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::total 800972760 # Table walker pending requests distribution +system.cpu.dtb.walker.walkPageSizes::4K 166514 90.93% 90.93% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::2M 16603 9.07% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 183117 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 215397 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 215397 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 183117 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 183117 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 398514 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 168646043 # DTB read hits -system.cpu.dtb.read_misses 158497 # DTB read misses -system.cpu.dtb.write_hits 153371607 # DTB write hits -system.cpu.dtb.write_misses 56347 # DTB write misses +system.cpu.dtb.read_hits 168647599 # DTB read hits +system.cpu.dtb.read_misses 158984 # DTB read misses +system.cpu.dtb.write_hits 153347297 # DTB write hits +system.cpu.dtb.write_misses 56413 # DTB write misses system.cpu.dtb.flush_tlb 10 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 43049 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_mva_asid 43021 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 1067 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 74830 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_entries 74349 # Number of entries that have been flushed from TLB system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 7977 # Number of TLB faults due to prefetch +system.cpu.dtb.prefetch_faults 8039 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 19966 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 168804540 # DTB read accesses -system.cpu.dtb.write_accesses 153427954 # DTB write accesses +system.cpu.dtb.perms_faults 19949 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 168806583 # DTB read accesses +system.cpu.dtb.write_accesses 153403710 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 322017650 # DTB hits -system.cpu.dtb.misses 214844 # DTB misses -system.cpu.dtb.accesses 322232494 # DTB accesses +system.cpu.dtb.hits 321994896 # DTB hits +system.cpu.dtb.misses 215397 # DTB misses +system.cpu.dtb.accesses 322210293 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -396,56 +483,91 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.inst_hits 898442559 # ITB inst hits -system.cpu.itb.inst_misses 123457 # ITB inst misses +system.cpu.itb.walker.walks 123370 # Table walker walks requested +system.cpu.itb.walker.walksLong 123370 # Table walker walks initiated with long descriptors +system.cpu.itb.walker.walksLongTerminationLevel::Level2 1120 # Level at which table walker walks with long descriptors terminate +system.cpu.itb.walker.walksLongTerminationLevel::Level3 111048 # Level at which table walker walks with long descriptors terminate +system.cpu.itb.walker.walkWaitTime::samples 123370 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0 123370 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::total 123370 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkCompletionTime::samples 112168 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::mean 24898.509379 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::gmean 20785.013360 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::stdev 17155.421945 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::0-65535 109848 97.93% 97.93% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::65536-131071 2031 1.81% 99.74% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::131072-196607 132 0.12% 99.86% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::196608-262143 101 0.09% 99.95% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::262144-327679 23 0.02% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::327680-393215 19 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::393216-458751 7 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::458752-524287 5 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::total 112168 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walksPending::samples -1257598296 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::0 -1257598296 100.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::total -1257598296 # Table walker pending requests distribution +system.cpu.itb.walker.walkPageSizes::4K 111048 99.00% 99.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::2M 1120 1.00% 100.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 112168 # Table walker page sizes translated +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 123370 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 123370 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 112168 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 112168 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 235538 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 898375907 # ITB inst hits +system.cpu.itb.inst_misses 123370 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.itb.flush_tlb 10 # Number of times complete TLB was flushed system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 43049 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_mva_asid 43021 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 1067 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 53017 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 52826 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 898566016 # ITB inst accesses -system.cpu.itb.hits 898442559 # DTB hits -system.cpu.itb.misses 123457 # DTB misses -system.cpu.itb.accesses 898566016 # DTB accesses -system.cpu.numCycles 103642407744 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 898499277 # ITB inst accesses +system.cpu.itb.hits 898375907 # DTB hits +system.cpu.itb.misses 123370 # DTB misses +system.cpu.itb.accesses 898499277 # DTB accesses +system.cpu.numCycles 103642314342 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 897890420 # Number of instructions committed -system.cpu.committedOps 1055061464 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 968615704 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 900077 # Number of float alu accesses -system.cpu.num_func_calls 53165114 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 137212632 # number of instructions that are conditional controls -system.cpu.num_int_insts 968615704 # number of integer instructions -system.cpu.num_fp_insts 900077 # number of float instructions -system.cpu.num_int_register_reads 1413530400 # number of times the integer registers were read -system.cpu.num_int_register_writes 768471074 # number of times the integer registers were written -system.cpu.num_fp_register_reads 1450010 # number of times the floating registers were read -system.cpu.num_fp_register_writes 764580 # number of times the floating registers were written -system.cpu.num_cc_register_reads 236283447 # number of times the CC registers were read -system.cpu.num_cc_register_writes 235682818 # number of times the CC registers were written -system.cpu.num_mem_refs 322001322 # number of memory refs -system.cpu.num_load_insts 168639088 # Number of load instructions -system.cpu.num_store_insts 153362234 # Number of store instructions -system.cpu.num_idle_cycles 100472196154.122070 # Number of idle cycles -system.cpu.num_busy_cycles 3170211589.877939 # Number of busy cycles -system.cpu.not_idle_fraction 0.030588 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.969412 # Percentage of idle cycles -system.cpu.Branches 200577010 # Number of branches fetched +system.cpu.committedInsts 897823750 # Number of instructions committed +system.cpu.committedOps 1054987960 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 968534129 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 900653 # Number of float alu accesses +system.cpu.num_func_calls 53156799 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 137185420 # number of instructions that are conditional controls +system.cpu.num_int_insts 968534129 # number of integer instructions +system.cpu.num_fp_insts 900653 # number of float instructions +system.cpu.num_int_register_reads 1413400107 # number of times the integer registers were read +system.cpu.num_int_register_writes 768429309 # number of times the integer registers were written +system.cpu.num_fp_register_reads 1451290 # number of times the floating registers were read +system.cpu.num_fp_register_writes 764324 # number of times the floating registers were written +system.cpu.num_cc_register_reads 236274909 # number of times the CC registers were read +system.cpu.num_cc_register_writes 235673566 # number of times the CC registers were written +system.cpu.num_mem_refs 321978685 # number of memory refs +system.cpu.num_load_insts 168640749 # Number of load instructions +system.cpu.num_store_insts 153337936 # Number of store instructions +system.cpu.num_idle_cycles 100474351324.032059 # Number of idle cycles +system.cpu.num_busy_cycles 3167963017.967939 # Number of busy cycles +system.cpu.not_idle_fraction 0.030566 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.969434 # Percentage of idle cycles +system.cpu.Branches 200551202 # Number of branches fetched system.cpu.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 731218910 69.27% 69.27% # Class of executed instruction -system.cpu.op_class::IntMult 2226806 0.21% 69.48% # Class of executed instruction -system.cpu.op_class::IntDiv 99223 0.01% 69.49% # Class of executed instruction +system.cpu.op_class::IntAlu 731167173 69.27% 69.27% # Class of executed instruction +system.cpu.op_class::IntMult 2227672 0.21% 69.48% # Class of executed instruction +system.cpu.op_class::IntDiv 99245 0.01% 69.49% # Class of executed instruction system.cpu.op_class::FloatAdd 0 0.00% 69.49% # Class of executed instruction system.cpu.op_class::FloatCmp 0 0.00% 69.49% # Class of executed instruction system.cpu.op_class::FloatCvt 0 0.00% 69.49% # Class of executed instruction @@ -472,122 +594,122 @@ system.cpu.op_class::SimdFloatMisc 110423 0.01% 69.50% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 69.50% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 69.50% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 69.50% # Class of executed instruction -system.cpu.op_class::MemRead 168639088 15.97% 85.47% # Class of executed instruction -system.cpu.op_class::MemWrite 153362234 14.53% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 168640749 15.98% 85.47% # Class of executed instruction +system.cpu.op_class::MemWrite 153337936 14.53% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 1055656727 # Class of executed instruction +system.cpu.op_class::total 1055583241 # Class of executed instruction system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 16365 # number of quiesce instructions executed -system.cpu.dcache.tags.replacements 10282368 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.969706 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 311548704 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 10282880 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 30.297806 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 10281150 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.969700 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 311526777 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 10281662 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 30.299263 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 3093156250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.969706 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 511.969700 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999941 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999941 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 49 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 410 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 51 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 401 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 64 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1298012717 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1298012717 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 157556193 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 157556193 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 145511723 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 145511723 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 396994 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 396994 # number of SoftPFReq hits -system.cpu.dcache.WriteInvalidateReq_hits::cpu.data 336687 # number of WriteInvalidateReq hits -system.cpu.dcache.WriteInvalidateReq_hits::total 336687 # number of WriteInvalidateReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 3698345 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 3698345 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 4003149 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 4003149 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 303067916 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 303067916 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 303464910 # number of overall hits -system.cpu.dcache.overall_hits::total 303464910 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 5344087 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 5344087 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2236666 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2236666 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 1310162 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 1310162 # number of SoftPFReq misses -system.cpu.dcache.WriteInvalidateReq_misses::cpu.data 1231947 # number of WriteInvalidateReq misses -system.cpu.dcache.WriteInvalidateReq_misses::total 1231947 # number of WriteInvalidateReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 306495 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 306495 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 4 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 4 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 7580753 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 7580753 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 8890915 # number of overall misses -system.cpu.dcache.overall_misses::total 8890915 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 83712196260 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 83712196260 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 64378240535 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 64378240535 # number of WriteReq miss cycles -system.cpu.dcache.WriteInvalidateReq_miss_latency::cpu.data 27514486506 # number of WriteInvalidateReq miss cycles -system.cpu.dcache.WriteInvalidateReq_miss_latency::total 27514486506 # number of WriteInvalidateReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 4474608500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 4474608500 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 251501 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 251501 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 148090436795 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 148090436795 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 148090436795 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 148090436795 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 162900280 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 162900280 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 147748389 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 147748389 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 1707156 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 1707156 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.WriteInvalidateReq_accesses::cpu.data 1568634 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu.dcache.WriteInvalidateReq_accesses::total 1568634 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4004840 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 4004840 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 4003153 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 4003153 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 310648669 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 310648669 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 312355825 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 312355825 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.032806 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.032806 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015138 # miss rate for WriteReq accesses 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-system.cpu.dcache.demand_miss_rate::total 0.024403 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.028464 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.028464 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15664.452368 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 15664.452368 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28783.126553 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 28783.126553 # average WriteReq miss latency -system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::cpu.data 22334.147902 # average WriteInvalidateReq miss latency -system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::total 22334.147902 # average WriteInvalidateReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14599.287101 # average LoadLockedReq miss latency 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75000 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 75000 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 19493.969413 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 19493.969413 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 16621.748543 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 16621.748543 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -596,88 +718,88 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes 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26688.386385 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 26688.386385 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 14883.018206 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 14883.018206 # average SoftPFReq mshr miss latency -system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data 20334.147893 # average WriteInvalidateReq mshr miss latency -system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 20334.147893 # average WriteInvalidateReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12313.246955 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12313.246955 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 60874.750000 # average StoreCondReq mshr miss latency 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ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 7536913001 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 5166015500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 5166015500 # number of WriteReq MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 2248902500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 10454004000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 12702906500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.011216 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.017188 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.005692 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.041978 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.017609 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu.data 0.413551 # mshr miss rate for WriteInvalidateReq accesses -system.cpu.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.413551 # mshr miss rate for WriteInvalidateReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.783332 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.783332 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 10454026001 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 12702928501 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.010861 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.016551 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.005754 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.042136 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.017717 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu.data 0.415226 # mshr miss rate for WriteInvalidateReq accesses +system.cpu.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.415226 # mshr miss rate for WriteInvalidateReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.780981 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.780981 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.246582 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.246582 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.011216 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.017188 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005692 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.091032 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.038711 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.011216 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.017188 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005692 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.091032 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.038711 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 65814.594972 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 66260.822511 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62136.636697 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63764.581031 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63475.943573 # average ReadReq mshr miss latency -system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data 21568.658213 # average WriteInvalidateReq mshr miss latency -system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 21568.658213 # average WriteInvalidateReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10005.590282 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10005.590282 # average UpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 47500.250000 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 47500.250000 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61617.263057 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61617.263057 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 65814.594972 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 66260.822511 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62136.636697 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62370.072593 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62384.840746 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 65814.594972 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 66260.822511 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62136.636697 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62370.072593 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62384.840746 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.246111 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.246111 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.010861 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.016551 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005754 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.091088 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.038840 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.010861 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.016551 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005754 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.091088 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.038840 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 65693.527160 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 66687.544358 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61986.826021 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63479.273949 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63225.991053 # average ReadReq mshr miss latency +system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data 21565.936570 # average WriteInvalidateReq mshr miss latency +system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 21565.936570 # average WriteInvalidateReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10002.708273 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10002.708273 # average UpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 60000 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 60000 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61281.495461 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61281.495461 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 65693.527160 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 66687.544358 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61986.826021 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62054.166126 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62086.457372 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 65693.527160 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 66687.544358 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61986.826021 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62054.166126 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62086.457372 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1067,58 +1189,58 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 21819690 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 21811671 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 21752331 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 21744344 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 33872 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 33872 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 7918344 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 1338611 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteInvalidateResp 1231947 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 45612 # Transaction distribution -system.cpu.toL2Bus.trans_dist::SCUpgradeReq 4 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 45616 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 2169953 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 2169953 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 27799880 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 28711563 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 624328 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1010117 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 58145888 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 887008660 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1165125804 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2042816 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 3064096 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 2057241376 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 474114 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 33215302 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5.003479 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.058876 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::Writeback 7913457 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 1339455 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteInvalidateResp 1232790 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 45725 # Transaction distribution +system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 45727 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 2171658 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 2171658 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 27670608 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 28704497 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 624113 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1013195 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 58012413 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 882871956 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1164737260 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2043192 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 3078296 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 2052730704 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 473368 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 33145716 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 5.003486 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.058938 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 33099762 99.65% 99.65% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 115540 0.35% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 33030174 99.65% 99.65% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::6 115542 0.35% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 33215302 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 25772593750 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 33145716 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 25733748000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 1282500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 1332000 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 20852498735 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 20755677476 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 14430330552 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 14427270036 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 369475750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 369197500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 627605250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 628893000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 40402 # Transaction distribution -system.iobus.trans_dist::ReadResp 40402 # Transaction distribution +system.iobus.trans_dist::ReadReq 40403 # Transaction distribution +system.iobus.trans_dist::ReadResp 40403 # Transaction distribution system.iobus.trans_dist::WriteReq 136733 # Transaction distribution system.iobus.trans_dist::WriteResp 30069 # Transaction distribution system.iobus.trans_dist::WriteInvalidateResp 106664 # Transaction distribution @@ -1138,11 +1260,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 123190 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231000 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 231000 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231002 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231002 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 354270 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 354272 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 48328 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -1159,11 +1281,11 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 156320 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334432 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7334432 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334440 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334440 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7492838 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 7492846 # Cumulative packet size per connected master and slave (bytes) system.iobus.reqLayer0.occupancy 36706000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) @@ -1192,71 +1314,71 @@ system.iobus.reqLayer25.occupancy 32658000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 1042392405 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 1042395169 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 93124000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 179042528 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 179037771 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 297000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 115480 # number of replacements -system.iocache.tags.tagsinuse 10.457351 # Cycle average of tags in use +system.iocache.tags.replacements 115482 # number of replacements +system.iocache.tags.tagsinuse 10.457347 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115496 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115498 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 13153949219000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.511147 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 6.946204 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.219447 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.434138 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 13153920852000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.510781 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 6.946566 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.219424 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.434160 # Average percentage of cache occupancy system.iocache.tags.occ_percent::total 0.653584 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1039857 # Number of tag accesses -system.iocache.tags.data_accesses 1039857 # Number of data accesses +system.iocache.tags.tag_accesses 1039866 # Number of tag accesses +system.iocache.tags.data_accesses 1039866 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8836 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8873 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8837 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8874 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteInvalidateReq_misses::realview.ide 106664 # number of WriteInvalidateReq misses system.iocache.WriteInvalidateReq_misses::total 106664 # number of WriteInvalidateReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8836 # number of demand (read+write) misses -system.iocache.demand_misses::total 8876 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8837 # number of demand (read+write) misses +system.iocache.demand_misses::total 8877 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8836 # number of overall misses -system.iocache.overall_misses::total 8876 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ethernet 5485000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1916450860 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1921935860 # number of ReadReq miss cycles +system.iocache.overall_misses::realview.ide 8837 # number of overall misses +system.iocache.overall_misses::total 8877 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ethernet 5479000 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1901914612 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1907393612 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 339000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 339000 # number of WriteReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::realview.ide 28823836017 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 28823836017 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 5824000 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 1916450860 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 1922274860 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 5824000 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 1916450860 # number of overall miss cycles -system.iocache.overall_miss_latency::total 1922274860 # number of overall miss cycles +system.iocache.WriteInvalidateReq_miss_latency::realview.ide 28843036786 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 28843036786 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 5818000 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 1901914612 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1907732612 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 5818000 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 1901914612 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1907732612 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8836 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8873 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8837 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8874 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::realview.ide 106664 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::total 106664 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8836 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8876 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8837 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8877 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8836 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8876 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8837 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8877 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -1270,55 +1392,55 @@ system.iocache.demand_miss_rate::total 1 # mi system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 148243.243243 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 216891.224536 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 216604.965626 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 148081.081081 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 215221.750820 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 214941.808880 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 113000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 113000 # average WriteReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 270230.218415 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 270230.218415 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 145600 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 216891.224536 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 216569.948175 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 145600 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 216891.224536 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 216569.948175 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 223291 # number of cycles access was blocked +system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 270410.230125 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 270410.230125 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 145450 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 215221.750820 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 214907.357441 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 145450 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 215221.750820 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 214907.357441 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 223600 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 27458 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 27526 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8.132093 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 8.123229 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 106629 # number of writebacks -system.iocache.writebacks::total 106629 # number of writebacks +system.iocache.writebacks::writebacks 106630 # number of writebacks +system.iocache.writebacks::total 106630 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8836 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8873 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8837 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8874 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 106664 # number of WriteInvalidateReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::total 106664 # number of WriteInvalidateReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 8836 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 8876 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 8837 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 8877 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 8836 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 8876 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3561000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1456881862 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1460442862 # number of ReadReq MSHR miss cycles +system.iocache.overall_mshr_misses::realview.ide 8837 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 8877 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3555000 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1442304112 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1445859112 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 183000 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 183000 # number of WriteReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 23277254071 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 23277254071 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ethernet 3744000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 1456881862 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 1460625862 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ethernet 3744000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 1456881862 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 1460625862 # number of overall MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 23296466828 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 23296466828 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ethernet 3738000 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 1442304112 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 1446042112 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ethernet 3738000 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 1442304112 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 1446042112 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -1332,71 +1454,71 @@ system.iocache.demand_mshr_miss_rate::total 1 # system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 96243.243243 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 164880.246944 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 164594.033810 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 96081.081081 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 163211.962431 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 162932.061303 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 61000 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 218229.712658 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 218229.712658 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 93600 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 164880.246944 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 164559.020054 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 93600 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 164880.246944 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 164559.020054 # average overall mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 218409.836758 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 218409.836758 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 93450 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 163211.962431 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 162897.613158 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 93450 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 163211.962431 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 162897.613158 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 462201 # Transaction distribution -system.membus.trans_dist::ReadResp 462201 # Transaction distribution +system.membus.trans_dist::ReadReq 463332 # Transaction distribution +system.membus.trans_dist::ReadResp 463332 # Transaction distribution system.membus.trans_dist::WriteReq 33872 # Transaction distribution system.membus.trans_dist::WriteResp 33872 # Transaction distribution -system.membus.trans_dist::Writeback 1241967 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 616132 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 616132 # Transaction distribution -system.membus.trans_dist::UpgradeReq 36293 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 4 # Transaction distribution -system.membus.trans_dist::UpgradeResp 36297 # Transaction distribution -system.membus.trans_dist::ReadExReq 534513 # Transaction distribution -system.membus.trans_dist::ReadExResp 534513 # Transaction distribution +system.membus.trans_dist::Writeback 1244337 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 618545 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 618545 # Transaction distribution +system.membus.trans_dist::UpgradeReq 36281 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution +system.membus.trans_dist::UpgradeResp 36283 # Transaction distribution +system.membus.trans_dist::ReadExReq 533903 # Transaction distribution +system.membus.trans_dist::ReadExResp 533903 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 123190 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6942 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4139437 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4269627 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 335126 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 335126 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4604753 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4147646 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4277836 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 334832 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 334832 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4612668 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 156320 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13884 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 163718240 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 163888576 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14053504 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 14053504 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 177942080 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 3244 # Total snoops (count) -system.membus.snoop_fanout::samples 2814199 # Request fanout histogram +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 164057632 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 164227968 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14034624 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 14034624 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 178262592 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 3539 # Total snoops (count) +system.membus.snoop_fanout::samples 2819489 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 2814199 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 2819489 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 2814199 # Request fanout histogram -system.membus.reqLayer0.occupancy 106092500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 2819489 # Request fanout histogram +system.membus.reqLayer0.occupancy 106085000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 31000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 5680000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 5679999 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 17856822743 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 17900056737 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 9254301682 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 9260714451 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 186599472 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 186597229 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/stats.txt index 72bc2e01a..5213927ce 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 51.111151 # Nu sim_ticks 51111150553500 # Number of ticks simulated final_tick 51111150553500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1088550 # Simulator instruction rate (inst/s) -host_op_rate 1279225 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 56496360239 # Simulator tick rate (ticks/s) -host_mem_usage 672572 # Number of bytes of host memory used -host_seconds 904.68 # Real time elapsed on the host +host_inst_rate 1151312 # Simulator instruction rate (inst/s) +host_op_rate 1352981 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 59753764865 # Simulator tick rate (ticks/s) +host_mem_usage 728116 # Number of bytes of host memory used +host_seconds 855.36 # Real time elapsed on the host sim_insts 984789519 # Number of instructions simulated sim_ops 1157289961 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -92,6 +92,14 @@ system.cf0.dma_write_full_pages 1666 # Nu system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1669 # Number of DMA write transactions. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -113,6 +121,24 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu0.dtb.walker.walks 144982 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 144982 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walkWaitTime::samples 144982 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 144982 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 144982 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walksPending::samples 22846000 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 22846000 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 22846000 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 108340 85.69% 85.69% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 18088 14.31% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 126428 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 144982 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 144982 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 126428 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 126428 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 271410 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses system.cpu0.dtb.read_hits 91965302 # DTB read hits @@ -134,6 +160,14 @@ system.cpu0.dtb.inst_accesses 0 # IT system.cpu0.dtb.hits 176331252 # DTB hits system.cpu0.dtb.misses 144982 # DTB misses system.cpu0.dtb.accesses 176476234 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -155,6 +189,24 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu0.itb.walker.walks 70785 # Table walker walks requested +system.cpu0.itb.walker.walksLong 70785 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walkWaitTime::samples 70785 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 70785 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 70785 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walksPending::samples 22844500 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 22844500 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 22844500 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 62159 96.07% 96.07% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 2545 3.93% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 64704 # Table walker page sizes translated +system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 70785 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 70785 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 64704 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 64704 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 135489 # Table walker requests started/completed, data/inst system.cpu0.itb.inst_hits 493804573 # ITB inst hits system.cpu0.itb.inst_misses 70785 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits @@ -424,6 +476,14 @@ system.cpu0.icache.avg_blocked_cycles::no_targets nan system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -445,6 +505,24 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu1.dtb.walker.walks 143312 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 143312 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walkWaitTime::samples 143312 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 143312 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 143312 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walksPending::samples 1000001000 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 1000001000 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 1000001000 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 106567 85.62% 85.62% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 17903 14.38% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 124470 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 143312 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 143312 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 124470 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 124470 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 267782 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses system.cpu1.dtb.read_hits 92072581 # DTB read hits @@ -466,6 +544,14 @@ system.cpu1.dtb.inst_accesses 0 # IT system.cpu1.dtb.hits 175979862 # DTB hits system.cpu1.dtb.misses 143312 # DTB misses system.cpu1.dtb.accesses 176123174 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -487,6 +573,24 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu1.itb.walker.walks 69790 # Table walker walks requested +system.cpu1.itb.walker.walksLong 69790 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walkWaitTime::samples 69790 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 69790 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 69790 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walksPending::samples 1000000500 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 1000000500 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 1000000500 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 61179 95.99% 95.99% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 2554 4.01% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 63733 # Table walker page sizes translated +system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 69790 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 69790 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 63733 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 63733 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 133523 # Table walker requests started/completed, data/inst system.cpu1.itb.inst_hits 491448225 # ITB inst hits system.cpu1.itb.inst_misses 69790 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt index e0cd774db..806ccbd13 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt @@ -1,120 +1,120 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.196466 # Number of seconds simulated -sim_ticks 5196466347000 # Number of ticks simulated -final_tick 5196466347000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.192453 # Number of seconds simulated +sim_ticks 5192452884000 # Number of ticks simulated +final_tick 5192452884000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 596082 # Simulator instruction rate (inst/s) -host_op_rate 1149061 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 24120553188 # Simulator tick rate (ticks/s) -host_mem_usage 596696 # Number of bytes of host memory used -host_seconds 215.44 # Real time elapsed on the host -sim_insts 128418244 # Number of instructions simulated -sim_ops 247550593 # Number of ops (including micro ops) simulated +host_inst_rate 836744 # Simulator instruction rate (inst/s) +host_op_rate 1613002 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 33830425760 # Simulator tick rate (ticks/s) +host_mem_usage 654168 # Number of bytes of host memory used +host_seconds 153.48 # Real time elapsed on the host +sim_insts 128427413 # Number of instructions simulated +sim_ops 247571076 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.dtb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 128 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 828416 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9035072 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 827456 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9039104 # Number of bytes read from this memory system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory -system.physmem.bytes_read::total 9892224 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 828416 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 828416 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8113920 # Number of bytes written to this memory -system.physmem.bytes_written::total 8113920 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 1 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 9895360 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 827456 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 827456 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8137984 # Number of bytes written to this memory +system.physmem.bytes_written::total 8137984 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 2 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 12944 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 141173 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 12929 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 141236 # Number of read requests responded to by this memory system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory -system.physmem.num_reads::total 154566 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 126780 # Number of write requests responded to by this memory -system.physmem.num_writes::total 126780 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 12 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::total 154615 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 127156 # Number of write requests responded to by this memory +system.physmem.num_writes::total 127156 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 25 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 159419 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1738695 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::pc.south_bridge.ide 5456 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1903644 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 159419 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 159419 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1561430 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1561430 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1561430 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 12 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 159357 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1740816 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::pc.south_bridge.ide 5460 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1905720 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 159357 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 159357 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1567272 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1567272 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1567272 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 25 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 159419 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1738695 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 5456 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3465075 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 154566 # Number of read requests accepted -system.physmem.writeReqs 173500 # Number of write requests accepted -system.physmem.readBursts 154566 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 173500 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 9886080 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 6144 # Total number of bytes read from write queue -system.physmem.bytesWritten 10951744 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 9892224 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 11104000 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 96 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2352 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 1595 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 9833 # Per bank write bursts -system.physmem.perBankRdBursts::1 9504 # Per bank write bursts -system.physmem.perBankRdBursts::2 9844 # Per bank write bursts -system.physmem.perBankRdBursts::3 9497 # Per bank write bursts -system.physmem.perBankRdBursts::4 9570 # Per bank write bursts -system.physmem.perBankRdBursts::5 9679 # Per bank write bursts -system.physmem.perBankRdBursts::6 9540 # Per bank write bursts -system.physmem.perBankRdBursts::7 9680 # Per bank write bursts -system.physmem.perBankRdBursts::8 9214 # Per bank write bursts -system.physmem.perBankRdBursts::9 9453 # Per bank write bursts -system.physmem.perBankRdBursts::10 9241 # Per bank write bursts -system.physmem.perBankRdBursts::11 9575 # Per bank write bursts -system.physmem.perBankRdBursts::12 9600 # Per bank write bursts -system.physmem.perBankRdBursts::13 10182 # Per bank write bursts -system.physmem.perBankRdBursts::14 10246 # Per bank write bursts -system.physmem.perBankRdBursts::15 9812 # Per bank write bursts -system.physmem.perBankWrBursts::0 10679 # Per bank write bursts -system.physmem.perBankWrBursts::1 10594 # Per bank write bursts -system.physmem.perBankWrBursts::2 10884 # Per bank write bursts -system.physmem.perBankWrBursts::3 10241 # Per bank write bursts -system.physmem.perBankWrBursts::4 10237 # Per bank write bursts -system.physmem.perBankWrBursts::5 10759 # Per bank write bursts -system.physmem.perBankWrBursts::6 10579 # Per bank write bursts -system.physmem.perBankWrBursts::7 10814 # Per bank write bursts -system.physmem.perBankWrBursts::8 10762 # Per bank write bursts -system.physmem.perBankWrBursts::9 11220 # Per bank write bursts -system.physmem.perBankWrBursts::10 10499 # Per bank write bursts -system.physmem.perBankWrBursts::11 10145 # Per bank write bursts -system.physmem.perBankWrBursts::12 11054 # Per bank write bursts -system.physmem.perBankWrBursts::13 11426 # Per bank write bursts -system.physmem.perBankWrBursts::14 10852 # Per bank write bursts -system.physmem.perBankWrBursts::15 10376 # Per bank write bursts +system.physmem.bw_total::cpu.inst 159357 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1740816 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 5460 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3472991 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 154615 # Number of read requests accepted +system.physmem.writeReqs 173876 # Number of write requests accepted +system.physmem.readBursts 154615 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 173876 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 9886592 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 8768 # Total number of bytes read from write queue +system.physmem.bytesWritten 10962560 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 9895360 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 11128064 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 137 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 2557 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 1589 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 10281 # Per bank write bursts +system.physmem.perBankRdBursts::1 9591 # Per bank write bursts +system.physmem.perBankRdBursts::2 10028 # Per bank write bursts +system.physmem.perBankRdBursts::3 9674 # Per bank write bursts +system.physmem.perBankRdBursts::4 9945 # Per bank write bursts +system.physmem.perBankRdBursts::5 9558 # Per bank write bursts +system.physmem.perBankRdBursts::6 9523 # Per bank write bursts +system.physmem.perBankRdBursts::7 9498 # Per bank write bursts +system.physmem.perBankRdBursts::8 9124 # Per bank write bursts +system.physmem.perBankRdBursts::9 8990 # Per bank write bursts +system.physmem.perBankRdBursts::10 9390 # Per bank write bursts +system.physmem.perBankRdBursts::11 9205 # Per bank write bursts +system.physmem.perBankRdBursts::12 9557 # Per bank write bursts +system.physmem.perBankRdBursts::13 10069 # Per bank write bursts +system.physmem.perBankRdBursts::14 10020 # Per bank write bursts +system.physmem.perBankRdBursts::15 10025 # Per bank write bursts +system.physmem.perBankWrBursts::0 10769 # Per bank write bursts +system.physmem.perBankWrBursts::1 10634 # Per bank write bursts +system.physmem.perBankWrBursts::2 10541 # Per bank write bursts +system.physmem.perBankWrBursts::3 10043 # Per bank write bursts +system.physmem.perBankWrBursts::4 11026 # Per bank write bursts +system.physmem.perBankWrBursts::5 9713 # Per bank write bursts +system.physmem.perBankWrBursts::6 10229 # Per bank write bursts +system.physmem.perBankWrBursts::7 10822 # Per bank write bursts +system.physmem.perBankWrBursts::8 11151 # Per bank write bursts +system.physmem.perBankWrBursts::9 11218 # Per bank write bursts +system.physmem.perBankWrBursts::10 10861 # Per bank write bursts +system.physmem.perBankWrBursts::11 10308 # Per bank write bursts +system.physmem.perBankWrBursts::12 10862 # Per bank write bursts +system.physmem.perBankWrBursts::13 11716 # Per bank write bursts +system.physmem.perBankWrBursts::14 11104 # Per bank write bursts +system.physmem.perBankWrBursts::15 10293 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 5196466283500 # Total gap between requests +system.physmem.totGap 5192452820500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 154566 # Read request sizes (log2) +system.physmem.readPktSize::6 154615 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 173500 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 151257 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 2780 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 62 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 55 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 35 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 38 # What read queue length does an incoming req see +system.physmem.writePktSize::6 173876 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 151192 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 2858 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 61 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 51 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 34 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 39 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 35 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 32 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 28 # What read queue length does an incoming req see @@ -156,377 +156,360 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2693 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 5142 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 8647 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 9871 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 10255 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 11236 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 11623 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 12575 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 12144 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 12750 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 11495 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 10962 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 9581 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8954 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7428 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7073 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7063 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6898 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 506 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 442 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 395 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 348 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 314 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 281 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 261 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 267 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 241 # What write queue length does an incoming req see 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incoming req see -system.physmem.wrQLenPdf::54 38 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 18 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 13 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2714 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 5087 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 8567 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 9777 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 10086 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 11162 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 11557 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 12608 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 12143 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 12879 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 11627 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 11021 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 9719 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8989 # What write queue length does an incoming req see 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does an incoming req see +system.physmem.wrQLenPdf::41 243 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 245 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 231 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 197 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 185 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 176 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 158 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 146 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 142 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 121 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 119 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 90 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 72 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 48 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 58532 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 356.006287 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 207.370190 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 358.892439 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 19432 33.20% 33.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 13728 23.45% 56.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5812 9.93% 66.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3460 5.91% 72.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2276 3.89% 76.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1654 2.83% 79.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1160 1.98% 81.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1010 1.73% 82.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 10000 17.08% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 58532 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6314 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 24.461831 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 602.615488 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 6313 99.98% 99.98% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 60024 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 347.345862 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 200.231116 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 357.371422 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 21054 35.08% 35.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 13721 22.86% 57.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5818 9.69% 67.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3428 5.71% 73.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2258 3.76% 77.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1594 2.66% 79.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1149 1.91% 81.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 996 1.66% 83.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 10006 16.67% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 60024 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6317 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 24.452430 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 602.471336 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6316 99.98% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::47104-49151 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6314 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6314 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 27.101837 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 21.618222 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 26.504313 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 4900 77.61% 77.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 45 0.71% 78.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 20 0.32% 78.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 269 4.26% 82.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 162 2.57% 85.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 59 0.93% 86.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 31 0.49% 86.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 30 0.48% 87.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 184 2.91% 90.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 10 0.16% 90.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 13 0.21% 90.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 9 0.14% 90.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 33 0.52% 91.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 21 0.33% 91.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 17 0.27% 91.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 41 0.65% 92.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 96 1.52% 94.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 7 0.11% 94.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 8 0.13% 94.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 18 0.29% 94.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 170 2.69% 97.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 5 0.08% 97.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 12 0.19% 97.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 4 0.06% 97.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 20 0.32% 97.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 4 0.06% 98.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 7 0.11% 98.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 6 0.10% 98.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 38 0.60% 98.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 9 0.14% 98.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 3 0.05% 99.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 7 0.11% 99.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 12 0.19% 99.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 3 0.05% 99.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 2 0.03% 99.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 3 0.05% 99.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 7 0.11% 99.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 3 0.05% 99.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-171 1 0.02% 99.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 2 0.03% 99.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 3 0.05% 99.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 4 0.06% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-187 2 0.03% 99.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 1 0.02% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-195 4 0.06% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-203 3 0.05% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::204-207 1 0.02% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-219 1 0.02% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::220-223 1 0.02% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::228-231 2 0.03% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::248-251 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6314 # Writes before turning the bus around for reads -system.physmem.totQLat 1460181000 # Total ticks spent queuing -system.physmem.totMemAccLat 4356493500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 772350000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9452.85 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 6317 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6317 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 27.115719 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 21.572083 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 27.245873 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 4954 78.42% 78.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 303 4.80% 83.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 227 3.59% 86.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 68 1.08% 87.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-55 174 2.75% 90.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-63 37 0.59% 91.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-71 45 0.71% 91.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-79 56 0.89% 92.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-87 90 1.42% 94.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-95 19 0.30% 94.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-103 157 2.49% 97.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-111 22 0.35% 97.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-119 27 0.43% 97.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-127 21 0.33% 98.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-135 36 0.57% 98.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-143 11 0.17% 98.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-151 22 0.35% 99.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-159 8 0.13% 99.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-167 14 0.22% 99.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-183 6 0.09% 99.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-191 5 0.08% 99.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-207 1 0.02% 99.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-215 1 0.02% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::216-223 4 0.06% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-231 3 0.05% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::232-239 1 0.02% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-247 1 0.02% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::248-255 3 0.05% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-263 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6317 # Writes before turning the bus around for reads +system.physmem.totQLat 1525176500 # Total ticks spent queuing +system.physmem.totMemAccLat 4421639000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 772390000 # Total ticks spent in databus transfers +system.physmem.avgQLat 9873.10 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28202.85 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 28623.10 # Average memory access latency per DRAM burst system.physmem.avgRdBW 1.90 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 2.11 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.90 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.91 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 2.14 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 21.87 # Average write queue length when enqueuing -system.physmem.readRowHits 127064 # Number of row buffer hits during reads -system.physmem.writeRowHits 139994 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.26 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 81.80 # Row buffer hit rate for writes -system.physmem.avgGap 15839697.75 # Average gap between requests -system.physmem.pageHitRate 82.02 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 4974958806500 # Time in different power states -system.physmem.memoryStateTime::REF 173521400000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 47986025500 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 218272320 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 224229600 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 119097000 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 122347500 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 601746600 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 603111600 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 549419760 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 559444320 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 339407858400 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 339407858400 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 134224004700 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 134453555955 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 3000139025250 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 2999937664500 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 3475259424030 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 3475308211875 # Total energy per rank (pJ) -system.physmem.averagePower::0 668.773676 # Core power per rank (mW) -system.physmem.averagePower::1 668.783065 # Core power per rank (mW) +system.physmem.avgWrQLen 25.96 # Average write queue length when enqueuing +system.physmem.readRowHits 125716 # Number of row buffer hits during reads +system.physmem.writeRowHits 140027 # Number of row buffer hits during writes +system.physmem.readRowHitRate 81.38 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 81.73 # Row buffer hit rate for writes +system.physmem.avgGap 15806986.56 # Average gap between requests +system.physmem.pageHitRate 81.57 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 224879760 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 122702250 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 609164400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 542874960 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 339145441440 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 134202799845 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 2997747003000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 3472594865655 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.777986 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 4986908920500 # Time in different power states +system.physmem_0.memoryStateTime::REF 173387240000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 32151782000 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 228901680 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 124896750 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 595756200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 567084240 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 339145441440 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 134282501235 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 2997677089500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 3472621671045 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.783148 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 4986802992250 # Time in different power states +system.physmem_1.memoryStateTime::REF 173387240000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 32262536750 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu.numCycles 10392932694 # number of cpu cycles simulated +system.cpu.numCycles 10384905768 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 128418244 # Number of instructions committed -system.cpu.committedOps 247550593 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 232131886 # Number of integer alu accesses +system.cpu.committedInsts 128427413 # Number of instructions committed +system.cpu.committedOps 247571076 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 232151918 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu.num_func_calls 2300917 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 23183149 # number of instructions that are conditional controls -system.cpu.num_int_insts 232131886 # number of integer instructions +system.cpu.num_func_calls 2302537 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 23180236 # number of instructions that are conditional controls +system.cpu.num_int_insts 232151918 # number of integer instructions system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 434791523 # number of times the integer registers were read -system.cpu.num_int_register_writes 197987761 # number of times the integer registers were written +system.cpu.num_int_register_reads 434861886 # number of times the integer registers were read +system.cpu.num_int_register_writes 198003963 # number of times the integer registers were written system.cpu.num_fp_register_reads 0 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_cc_register_reads 132892118 # number of times the CC registers were read -system.cpu.num_cc_register_writes 95599960 # number of times the CC registers were written -system.cpu.num_mem_refs 22255642 # number of memory refs -system.cpu.num_load_insts 13887148 # Number of load instructions -system.cpu.num_store_insts 8368494 # Number of store instructions -system.cpu.num_idle_cycles 9795963958.998116 # Number of idle cycles -system.cpu.num_busy_cycles 596968735.001885 # Number of busy cycles -system.cpu.not_idle_fraction 0.057440 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.942560 # Percentage of idle cycles -system.cpu.Branches 26322824 # Number of branches fetched -system.cpu.op_class::No_OpClass 174818 0.07% 0.07% # Class of executed instruction -system.cpu.op_class::IntAlu 224858584 90.83% 90.90% # Class of executed instruction -system.cpu.op_class::IntMult 140018 0.06% 90.96% # Class of executed instruction -system.cpu.op_class::IntDiv 123105 0.05% 91.01% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 91.01% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 91.01% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 91.01% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 91.01% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 91.01% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 91.01% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 91.01% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 91.01% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 91.01% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 91.01% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 91.01% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 91.01% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 91.01% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 91.01% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 91.01% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 91.01% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 91.01% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 91.01% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 91.01% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 91.01% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 91.01% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 91.01% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 91.01% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 91.01% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 91.01% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 91.01% # Class of executed instruction -system.cpu.op_class::MemRead 13887148 5.61% 96.62% # Class of executed instruction -system.cpu.op_class::MemWrite 8368494 3.38% 100.00% # Class of executed instruction +system.cpu.num_cc_register_reads 132886732 # number of times the CC registers were read +system.cpu.num_cc_register_writes 95589498 # number of times the CC registers were written +system.cpu.num_mem_refs 22270580 # number of memory refs +system.cpu.num_load_insts 13896035 # Number of load instructions +system.cpu.num_store_insts 8374545 # Number of store instructions +system.cpu.num_idle_cycles 9787798534.998116 # Number of idle cycles +system.cpu.num_busy_cycles 597107233.001885 # Number of busy cycles +system.cpu.not_idle_fraction 0.057498 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.942502 # Percentage of idle cycles +system.cpu.Branches 26321851 # Number of branches fetched +system.cpu.op_class::No_OpClass 175044 0.07% 0.07% # Class of executed instruction +system.cpu.op_class::IntAlu 224863247 90.83% 90.90% # Class of executed instruction +system.cpu.op_class::IntMult 140296 0.06% 90.95% # Class of executed instruction +system.cpu.op_class::IntDiv 123429 0.05% 91.00% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 91.00% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 91.00% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 91.00% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 91.00% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 91.00% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 91.00% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 91.00% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 91.00% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 91.00% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 91.00% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 91.00% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 91.00% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 91.00% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 91.00% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 91.00% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 91.00% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 91.00% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 91.00% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 91.00% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 91.00% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 91.00% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 91.00% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 91.00% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 91.00% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 91.00% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 91.00% # Class of executed instruction +system.cpu.op_class::MemRead 13896035 5.61% 96.62% # Class of executed instruction +system.cpu.op_class::MemWrite 8374545 3.38% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 247552167 # Class of executed instruction +system.cpu.op_class::total 247572596 # Class of executed instruction system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu.dcache.tags.replacements 1622836 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.996904 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 20034858 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1623348 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 12.341690 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 1622236 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.996968 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 20050453 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1622748 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 12.355864 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 51171250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.996904 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 511.996968 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 111 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 323 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 77 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 102 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 320 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 89 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 88294796 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 88294796 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 11940626 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 11940626 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 8032822 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8032822 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 59222 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 59222 # number of SoftPFReq hits -system.cpu.dcache.demand_hits::cpu.data 19973448 # number of demand (read+write) hits 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1635178 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 12738871000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 12738871000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 11339051069 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 11339051069 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 24077922069 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 24077922069 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 24077922069 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 24077922069 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 12848128 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 12848128 # number of ReadReq accesses(hits+misses) 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34862.892107 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 19531.893410 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 19531.893410 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 14724.954757 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 14724.954757 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 6197 # number of cycles access was blocked +system.cpu.dcache.tags.tag_accesses 88354150 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 88354150 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 11949885 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 11949885 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 8039029 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 8039029 # number of WriteReq hits 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26518808638 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 26518808638 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 94240373000 # number of ReadReq MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 94240373000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2561805000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2561805000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 96802178000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 96802178000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.070610 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.070610 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037806 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.037806 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.871639 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.871639 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.057681 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.057681 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.075023 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.075023 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12033.510672 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12033.510672 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32292.830357 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32292.830357 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13264.542375 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13264.542375 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17267.084202 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 17267.084202 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16276.309879 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 16276.309879 # average overall mshr miss latency +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2561567000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2561567000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 96801940000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 96801940000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.070525 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.070525 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037759 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.037759 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.871392 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.871392 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.057610 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.057610 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074943 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.074943 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12032.198047 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12032.198047 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32437.608291 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32437.608291 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13330.165225 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13330.165225 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17303.509041 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 17303.509041 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16319.517924 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 16319.517924 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -534,58 +517,58 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.tags.replacements 7764 # number of replacements -system.cpu.dtb_walker_cache.tags.tagsinuse 5.069200 # Cycle average of tags in use -system.cpu.dtb_walker_cache.tags.total_refs 13087 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.tags.sampled_refs 7779 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.tags.avg_refs 1.682350 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.tags.warmup_cycle 5159703878000 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.069200 # Average occupied blocks per requestor -system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.316825 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.tags.occ_percent::total 0.316825 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.tags.replacements 7361 # number of replacements +system.cpu.dtb_walker_cache.tags.tagsinuse 5.061574 # Cycle average of tags in use +system.cpu.dtb_walker_cache.tags.total_refs 13446 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.sampled_refs 7376 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.tags.avg_refs 1.822939 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.warmup_cycle 5159721667000 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.061574 # Average occupied blocks per requestor +system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.316348 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.tags.occ_percent::total 0.316348 # Average percentage of cache occupancy system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 15 # Occupied blocks per task id system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 6 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 5 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 7 # Occupied blocks per task id system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 0.937500 # Percentage of cache occupancy per task id -system.cpu.dtb_walker_cache.tags.tag_accesses 53125 # Number of tag accesses -system.cpu.dtb_walker_cache.tags.data_accesses 53125 # Number of data accesses -system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 13088 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 13088 # number of ReadReq hits -system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 13088 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 13088 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 13088 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 13088 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8983 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 8983 # number of ReadReq misses -system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8983 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 8983 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8983 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 8983 # number of overall misses -system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 95259000 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 95259000 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 95259000 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::total 95259000 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 95259000 # number of overall miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::total 95259000 # number of overall miss cycles -system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 22071 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 22071 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 22071 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 22071 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 22071 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 22071 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.407005 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.407005 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.407005 # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::total 0.407005 # miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.407005 # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::total 0.407005 # miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 10604.363798 # average ReadReq miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 10604.363798 # average ReadReq miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 10604.363798 # average overall miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 10604.363798 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10604.363798 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10604.363798 # average overall miss latency +system.cpu.dtb_walker_cache.tags.tag_accesses 52616 # Number of tag accesses +system.cpu.dtb_walker_cache.tags.data_accesses 52616 # Number of data accesses +system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 13447 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 13447 # number of ReadReq hits +system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 13447 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 13447 # number of demand (read+write) hits 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number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::total 90024000 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 90024000 # number of overall miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::total 90024000 # number of overall miss cycles +system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 22021 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 22021 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 22021 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 22021 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 22021 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 22021 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.389356 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.389356 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.389356 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total 0.389356 # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.389356 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total 0.389356 # miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 10499.650105 # average ReadReq miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 10499.650105 # average ReadReq miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 10499.650105 # average overall miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 10499.650105 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10499.650105 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10499.650105 # average overall miss latency system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -594,86 +577,86 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks::writebacks 3015 # number of writebacks -system.cpu.dtb_walker_cache.writebacks::total 3015 # number of writebacks -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 8983 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 8983 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 8983 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::total 8983 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 8983 # number of overall MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::total 8983 # number of overall MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 77292500 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 77292500 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 77292500 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 77292500 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 77292500 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 77292500 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.407005 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.407005 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.407005 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.407005 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.407005 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.407005 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 8604.308138 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8604.308138 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 8604.308138 # average overall mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 8604.308138 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 8604.308138 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 8604.308138 # average overall mshr miss latency +system.cpu.dtb_walker_cache.writebacks::writebacks 2787 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::total 2787 # number of writebacks +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 8574 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 8574 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 8574 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::total 8574 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 8574 # number of overall MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::total 8574 # number of overall MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 72875500 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 72875500 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 72875500 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 72875500 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 72875500 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 72875500 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.389356 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.389356 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.389356 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.389356 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.389356 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.389356 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 8499.591789 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8499.591789 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 8499.591789 # average overall mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 8499.591789 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 8499.591789 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 8499.591789 # average overall mshr miss latency system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 791291 # number of replacements -system.cpu.icache.tags.tagsinuse 510.349956 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 144673577 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 791803 # Sample count of references to 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Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 146257197 # Number of tag accesses -system.cpu.icache.tags.data_accesses 146257197 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 144673577 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 144673577 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 144673577 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 144673577 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 144673577 # number of overall hits -system.cpu.icache.overall_hits::total 144673577 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 791810 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 791810 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 791810 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 791810 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 791810 # number of overall misses -system.cpu.icache.overall_misses::total 791810 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 11120002617 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 11120002617 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 11120002617 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 11120002617 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 11120002617 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 11120002617 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 145465387 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 145465387 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 145465387 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 145465387 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 145465387 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 145465387 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.005443 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.005443 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.005443 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.005443 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.005443 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.005443 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14043.776432 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 14043.776432 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14043.776432 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 14043.776432 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14043.776432 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 14043.776432 # average overall miss latency +system.cpu.icache.tags.tag_accesses 146267168 # Number of tag accesses +system.cpu.icache.tags.data_accesses 146267168 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 144679610 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 144679610 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 144679610 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 144679610 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 144679610 # number of overall hits +system.cpu.icache.overall_hits::total 144679610 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 793779 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 793779 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 793779 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 793779 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 793779 # number of overall misses +system.cpu.icache.overall_misses::total 793779 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 11142507120 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 11142507120 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 11142507120 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 11142507120 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 11142507120 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 11142507120 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 145473389 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 145473389 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 145473389 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 145473389 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 145473389 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 145473389 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.005457 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.005457 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.005457 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.005457 # miss rate for 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was blocked @@ -682,88 +665,88 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 791810 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 791810 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 791810 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 791810 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 791810 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 791810 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9531495383 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 9531495383 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9531495383 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 9531495383 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9531495383 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 9531495383 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.005443 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.005443 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.005443 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.005443 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.005443 # mshr miss rate for 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(read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 793779 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 793779 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 793779 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9550046380 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 9550046380 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9550046380 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 9550046380 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9550046380 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 9550046380 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.005457 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.005457 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.005457 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.005457 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.005457 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.005457 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12031.114932 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12031.114932 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12031.114932 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 12031.114932 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12031.114932 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 12031.114932 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.itb_walker_cache.tags.replacements 3671 # number of replacements -system.cpu.itb_walker_cache.tags.tagsinuse 3.091001 # Cycle average of tags in use -system.cpu.itb_walker_cache.tags.total_refs 7743 # Total number of references to valid blocks. -system.cpu.itb_walker_cache.tags.sampled_refs 3683 # Sample count of references to valid blocks. -system.cpu.itb_walker_cache.tags.avg_refs 2.102362 # Average number of references to valid blocks. -system.cpu.itb_walker_cache.tags.warmup_cycle 5161228729000 # Cycle when the warmup percentage was hit. -system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.091001 # Average occupied blocks per requestor -system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.193188 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.tags.occ_percent::total 0.193188 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 12 # Occupied blocks per task id +system.cpu.itb_walker_cache.tags.replacements 3392 # number of replacements +system.cpu.itb_walker_cache.tags.tagsinuse 3.080377 # Cycle average of tags in use +system.cpu.itb_walker_cache.tags.total_refs 8023 # Total number of references to valid blocks. +system.cpu.itb_walker_cache.tags.sampled_refs 3405 # Sample count of references to valid blocks. +system.cpu.itb_walker_cache.tags.avg_refs 2.356241 # Average number of references to valid blocks. +system.cpu.itb_walker_cache.tags.warmup_cycle 5161936228000 # Cycle when the warmup percentage was hit. +system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.080377 # Average occupied blocks per requestor +system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.192524 # Average percentage of cache occupancy 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hits +system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 4 # Occupied blocks per task id +system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id +system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id +system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.812500 # Percentage of cache occupancy per task id +system.cpu.itb_walker_cache.tags.tag_accesses 28882 # Number of tag accesses +system.cpu.itb_walker_cache.tags.data_accesses 28882 # Number of data accesses +system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 8043 # number of ReadReq hits +system.cpu.itb_walker_cache.ReadReq_hits::total 8043 # number of ReadReq hits system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits -system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7745 # number of demand (read+write) hits -system.cpu.itb_walker_cache.demand_hits::total 7745 # number of demand (read+write) hits -system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7745 # number of overall hits -system.cpu.itb_walker_cache.overall_hits::total 7745 # number of overall hits -system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4535 # number of ReadReq misses -system.cpu.itb_walker_cache.ReadReq_misses::total 4535 # number of ReadReq misses -system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4535 # number of demand (read+write) misses -system.cpu.itb_walker_cache.demand_misses::total 4535 # number of demand (read+write) misses -system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4535 # number of overall misses -system.cpu.itb_walker_cache.overall_misses::total 4535 # number of overall misses -system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 45208750 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.ReadReq_miss_latency::total 45208750 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 45208750 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::total 45208750 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 45208750 # number of overall miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::total 45208750 # number of overall miss cycles -system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12278 # number of ReadReq accesses(hits+misses) -system.cpu.itb_walker_cache.ReadReq_accesses::total 12278 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 8045 # number of demand (read+write) hits +system.cpu.itb_walker_cache.demand_hits::total 8045 # number of demand (read+write) hits +system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 8045 # number of overall hits +system.cpu.itb_walker_cache.overall_hits::total 8045 # number of overall hits +system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4264 # number of ReadReq misses +system.cpu.itb_walker_cache.ReadReq_misses::total 4264 # number of ReadReq misses +system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4264 # number of demand (read+write) misses +system.cpu.itb_walker_cache.demand_misses::total 4264 # number of demand (read+write) misses +system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4264 # number of overall misses +system.cpu.itb_walker_cache.overall_misses::total 4264 # number of overall misses +system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 41583500 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.ReadReq_miss_latency::total 41583500 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 41583500 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::total 41583500 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 41583500 # number of overall miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::total 41583500 # number of overall miss cycles +system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12307 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.ReadReq_accesses::total 12307 # number of ReadReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) -system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12280 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.demand_accesses::total 12280 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12280 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::total 12280 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.369360 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.369360 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.369300 # miss rate for demand accesses -system.cpu.itb_walker_cache.demand_miss_rate::total 0.369300 # miss rate for demand accesses -system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.369300 # miss rate for overall accesses -system.cpu.itb_walker_cache.overall_miss_rate::total 0.369300 # miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 9968.853363 # average ReadReq miss latency -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 9968.853363 # average ReadReq miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 9968.853363 # average overall miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::total 9968.853363 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 9968.853363 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::total 9968.853363 # average overall miss latency +system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12309 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_accesses::total 12309 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12309 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::total 12309 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.346469 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.346469 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.346413 # miss rate for demand accesses +system.cpu.itb_walker_cache.demand_miss_rate::total 0.346413 # miss rate for demand accesses +system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.346413 # miss rate for overall accesses +system.cpu.itb_walker_cache.overall_miss_rate::total 0.346413 # miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 9752.227955 # average ReadReq miss latency +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 9752.227955 # average ReadReq miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 9752.227955 # average overall miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::total 9752.227955 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 9752.227955 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::total 9752.227955 # average overall miss latency system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -772,177 +755,177 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.itb_walker_cache.writebacks::writebacks 782 # number of writebacks -system.cpu.itb_walker_cache.writebacks::total 782 # number of writebacks -system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 4535 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 4535 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 4535 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::total 4535 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 4535 # number of overall MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::total 4535 # number of overall MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 36137250 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 36137250 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 36137250 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 36137250 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 36137250 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 36137250 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.369360 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.369360 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.369300 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.369300 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.369300 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.369300 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 7968.522602 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 7968.522602 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 7968.522602 # average overall mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 7968.522602 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 7968.522602 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 7968.522602 # average overall mshr miss latency +system.cpu.itb_walker_cache.writebacks::writebacks 713 # number of writebacks +system.cpu.itb_walker_cache.writebacks::total 713 # number of writebacks +system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 4264 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 4264 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 4264 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::total 4264 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 4264 # number of overall MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::total 4264 # number of overall MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 33053500 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 33053500 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 33053500 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 33053500 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 33053500 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 33053500 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.346469 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.346469 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.346413 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.346413 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.346413 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.346413 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 7751.758912 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 7751.758912 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 7751.758912 # average overall mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 7751.758912 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 7751.758912 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 7751.758912 # average overall mshr miss latency system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 87090 # number of replacements -system.cpu.l2cache.tags.tagsinuse 64747.295038 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3489215 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 151848 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 22.978340 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 87367 # number of replacements +system.cpu.l2cache.tags.tagsinuse 64711.001958 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 3492751 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 152091 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 22.964876 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 50370.250728 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 0.007923 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.141558 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 3248.489299 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 11128.405530 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.768589 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 50199.140845 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 0.014318 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.141821 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 3238.410068 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 11273.294906 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.765978 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000000 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.049568 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.169806 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.987965 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 64758 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 28 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 86 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2868 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4655 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 57121 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.988129 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 32220029 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 32220029 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6582 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2969 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 778852 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 1280153 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 2068556 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 1543232 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 1543232 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 331 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 331 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 200337 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 200337 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 6582 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 2969 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 778852 # number of demand (read+write) hits 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id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 77 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 119 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2777 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4943 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 56808 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.987610 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 32220272 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 32220272 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6177 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2685 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 780836 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 1279767 # number of ReadReq hits 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ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 113458 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.dtb.walker 1 # number of demand (read+write) misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 12930 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 28590 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 41527 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 1330 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 1330 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 113574 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 113574 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.dtb.walker 2 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 12945 # number of demand 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+system.cpu.l2cache.demand_mshr_miss_latency::total 9067229777 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 111250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 301500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 785787500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8281029527 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 9067229777 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 86680074500 # number of ReadReq MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 86680074500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2395003500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2395003500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 89075078000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 89075078000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000152 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001681 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016349 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.021886 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.019712 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.800962 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.800962 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.361567 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.361567 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000152 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.001681 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016349 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.087578 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.063968 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000152 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.001681 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016349 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.087578 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.063968 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 76250 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 57550 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60940.073387 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62274.585442 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61859.042937 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10662.023273 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10662.023273 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56679.443318 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56679.443318 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 76250 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 57550 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60940.073387 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57807.307235 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58068.963264 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 76250 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 57550 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60940.073387 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57807.307235 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58068.963264 # average overall mshr miss latency +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2394785000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2394785000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 89074859500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 89074859500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000324 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001859 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016289 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.021852 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.019672 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.809495 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.809495 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.362122 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.362122 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000324 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.001859 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016289 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.087648 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.063969 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000324 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.001859 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016289 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.087648 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.063969 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 55625 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 60300 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60772.428461 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63250.760756 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62478.375515 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10692.715789 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10692.715789 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56990.951072 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56990.951072 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 55625 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 60300 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60772.428461 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 58249.834888 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58460.163229 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 55625 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 60300 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60772.428461 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 58249.834888 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58460.163229 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1042,59 +1025,59 @@ system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 2697337 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2696818 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 13890 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 13890 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 1543232 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 2698168 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2697644 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 13888 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 13888 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 1542614 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2201 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2201 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 313800 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 313800 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1583607 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5980523 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 8291 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 18581 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7591002 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50675008 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 204057491 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 240384 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 614272 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 255587155 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 53212 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 4021729 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 3.011827 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.108106 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::UpgradeReq 2194 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2194 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 313640 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 313640 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1587545 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5978947 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 7667 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 17540 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7591699 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50801024 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 203997643 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 217792 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 573824 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 255590283 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 53203 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 4021775 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3.011825 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.108096 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 3974165 98.82% 98.82% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 47564 1.18% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 3974219 98.82% 98.82% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 47556 1.18% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 4021729 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 3834985000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 4021775 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 3834392000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 487500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 468000 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1190158617 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1193119870 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3054984845 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3054097839 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 6803250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 6397000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 13474750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 12861250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 230264 # Transaction distribution -system.iobus.trans_dist::ReadResp 230264 # Transaction distribution +system.iobus.trans_dist::ReadReq 230256 # Transaction distribution +system.iobus.trans_dist::ReadResp 230256 # Transaction distribution system.iobus.trans_dist::WriteReq 57694 # Transaction distribution system.iobus.trans_dist::WriteResp 10974 # Transaction distribution system.iobus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution -system.iobus.trans_dist::MessageReq 1655 # Transaction distribution -system.iobus.trans_dist::MessageResp 1655 # Transaction distribution +system.iobus.trans_dist::MessageReq 1654 # Transaction distribution +system.iobus.trans_dist::MessageResp 1654 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11088 # Packet count per connected master and slave (bytes) @@ -1114,11 +1097,11 @@ system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 480788 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95128 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95128 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3310 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3310 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 579226 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95112 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95112 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3308 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3308 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 579208 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6686 # Cumulative packet size per connected master and slave (bytes) @@ -1138,12 +1121,12 @@ system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 246674 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027296 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027296 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6620 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6620 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 3280590 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 3947664 # Layer occupancy (ticks) +system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027232 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027232 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6616 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6616 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 3280522 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 3944816 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -1179,54 +1162,54 @@ system.iobus.reqLayer17.occupancy 9000 # La system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer18.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer19.occupancy 448397612 # Layer occupancy (ticks) +system.iobus.reqLayer19.occupancy 448430581 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer20.occupancy 1064000 # Layer occupancy (ticks) system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 469814000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 52228501 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 52212002 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer2.occupancy 1655000 # Layer occupancy (ticks) +system.iobus.respLayer2.occupancy 1654000 # Layer occupancy (ticks) system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 47510 # number of replacements -system.iocache.tags.tagsinuse 0.132770 # Cycle average of tags in use +system.iocache.tags.replacements 47501 # number of replacements +system.iocache.tags.tagsinuse 0.119711 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 47526 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 47517 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 5045851378000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.132770 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::pc.south_bridge.ide 0.008298 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.008298 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 5045856556000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.119711 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::pc.south_bridge.ide 0.007482 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.007482 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 428076 # Number of tag accesses -system.iocache.tags.data_accesses 428076 # Number of data accesses -system.iocache.ReadReq_misses::pc.south_bridge.ide 844 # number of ReadReq misses -system.iocache.ReadReq_misses::total 844 # number of ReadReq misses +system.iocache.tags.tag_accesses 428004 # Number of tag accesses +system.iocache.tags.data_accesses 428004 # Number of data accesses +system.iocache.ReadReq_misses::pc.south_bridge.ide 836 # number of ReadReq misses +system.iocache.ReadReq_misses::total 836 # number of ReadReq misses system.iocache.WriteInvalidateReq_misses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq misses system.iocache.WriteInvalidateReq_misses::total 46720 # number of WriteInvalidateReq misses -system.iocache.demand_misses::pc.south_bridge.ide 844 # number of demand (read+write) misses -system.iocache.demand_misses::total 844 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 844 # number of overall misses -system.iocache.overall_misses::total 844 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 143496186 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 143496186 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::pc.south_bridge.ide 12353940925 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 12353940925 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 143496186 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 143496186 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 143496186 # number of overall miss cycles -system.iocache.overall_miss_latency::total 143496186 # number of overall miss cycles -system.iocache.ReadReq_accesses::pc.south_bridge.ide 844 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 844 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::pc.south_bridge.ide 836 # number of demand (read+write) misses +system.iocache.demand_misses::total 836 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 836 # number of overall misses +system.iocache.overall_misses::total 836 # number of overall misses +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 143698686 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 143698686 # number of ReadReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::pc.south_bridge.ide 12361223893 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 12361223893 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 143698686 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 143698686 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 143698686 # number of overall miss cycles +system.iocache.overall_miss_latency::total 143698686 # number of overall miss cycles +system.iocache.ReadReq_accesses::pc.south_bridge.ide 836 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 836 # number of ReadReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::total 46720 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 844 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 844 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 844 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 844 # number of overall (read+write) accesses +system.iocache.demand_accesses::pc.south_bridge.ide 836 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 836 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 836 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 836 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteInvalidateReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteInvalidateReq accesses @@ -1235,40 +1218,40 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 170019.177725 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 170019.177725 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::pc.south_bridge.ide 264425.105415 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 264425.105415 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 170019.177725 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 170019.177725 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 170019.177725 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 170019.177725 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 70456 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 171888.380383 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 171888.380383 # average ReadReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::pc.south_bridge.ide 264580.990860 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 264580.990860 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 171888.380383 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 171888.380383 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 171888.380383 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 171888.380383 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 70511 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 9155 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 9153 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 7.695904 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 7.703594 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 46668 # number of writebacks -system.iocache.writebacks::total 46668 # number of writebacks -system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 844 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 844 # number of ReadReq MSHR misses +system.iocache.writebacks::writebacks 46667 # number of writebacks +system.iocache.writebacks::total 46667 # number of writebacks +system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 836 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 836 # number of ReadReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::total 46720 # number of WriteInvalidateReq MSHR misses -system.iocache.demand_mshr_misses::pc.south_bridge.ide 844 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 844 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::pc.south_bridge.ide 844 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 844 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 99583186 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 99583186 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 9924498927 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 9924498927 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 99583186 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 99583186 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 99583186 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 99583186 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::pc.south_bridge.ide 836 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 836 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 836 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 836 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 100200686 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 100200686 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 9931779897 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 9931779897 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 100200686 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 100200686 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 100200686 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 100200686 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteInvalidateReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteInvalidateReq accesses @@ -1277,71 +1260,71 @@ system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 117989.556872 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 117989.556872 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 212425.062650 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 212425.062650 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 117989.556872 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 117989.556872 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 117989.556872 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 117989.556872 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 119857.279904 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 119857.279904 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 212580.905330 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 212580.905330 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 119857.279904 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 119857.279904 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 119857.279904 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 119857.279904 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 624001 # Transaction distribution -system.membus.trans_dist::ReadResp 624001 # Transaction distribution -system.membus.trans_dist::WriteReq 13890 # Transaction distribution -system.membus.trans_dist::WriteResp 13890 # Transaction distribution -system.membus.trans_dist::Writeback 126780 # Transaction distribution +system.membus.trans_dist::ReadReq 623924 # Transaction distribution +system.membus.trans_dist::ReadResp 623924 # Transaction distribution +system.membus.trans_dist::WriteReq 13888 # Transaction distribution +system.membus.trans_dist::WriteResp 13888 # Transaction distribution +system.membus.trans_dist::Writeback 127156 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution -system.membus.trans_dist::UpgradeReq 2150 # Transaction distribution -system.membus.trans_dist::UpgradeResp 1612 # Transaction distribution -system.membus.trans_dist::ReadExReq 113178 # Transaction distribution -system.membus.trans_dist::ReadExResp 113178 # Transaction distribution -system.membus.trans_dist::MessageReq 1655 # Transaction distribution -system.membus.trans_dist::MessageResp 1655 # Transaction distribution -system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3310 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.apicbridge.master::total 3310 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::UpgradeReq 2158 # Transaction distribution +system.membus.trans_dist::UpgradeResp 1607 # Transaction distribution +system.membus.trans_dist::ReadExReq 113297 # Transaction distribution +system.membus.trans_dist::ReadExResp 113297 # Transaction distribution +system.membus.trans_dist::MessageReq 1654 # Transaction distribution +system.membus.trans_dist::MessageResp 1654 # Transaction distribution +system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3308 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.apicbridge.master::total 3308 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 480788 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 710114 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 392754 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1583656 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141395 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 141395 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1728361 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6620 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.apicbridge.master::total 6620 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 710110 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 393232 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1584130 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141386 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 141386 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1728824 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6616 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.apicbridge.master::total 6616 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 246674 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1420225 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 14991040 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16657939 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 6005184 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 6005184 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 22669743 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 1607 # Total snoops (count) -system.membus.snoop_fanout::samples 331268 # Request fanout histogram +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1420217 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15018304 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16685195 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 6005120 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 6005120 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 22696931 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 1614 # Total snoops (count) +system.membus.snoop_fanout::samples 331694 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 331268 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 331694 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 331268 # Request fanout histogram -system.membus.reqLayer0.occupancy 257196000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 331694 # Request fanout histogram +system.membus.reqLayer0.occupancy 257197500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 358100000 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 358100500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3310000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3308000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer3.occupancy 1728081500 # Layer occupancy (ticks) +system.membus.reqLayer3.occupancy 1731913000 # Layer occupancy (ticks) system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.membus.respLayer0.occupancy 1655000 # Layer occupancy (ticks) +system.membus.respLayer0.occupancy 1654000 # Layer occupancy (ticks) system.membus.respLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 2618580655 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 2619410411 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.1 # Layer utilization (%) -system.membus.respLayer4.occupancy 54329499 # Layer occupancy (ticks) +system.membus.respLayer4.occupancy 54258998 # Layer occupancy (ticks) system.membus.respLayer4.utilization 0.0 # Layer utilization (%) system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). diff --git a/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt index c9524dba5..954061e30 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000035 # Number of seconds simulated -sim_ticks 35022500 # Number of ticks simulated -final_tick 35022500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 34993500 # Number of ticks simulated +final_tick 34993500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 71946 # Simulator instruction rate (inst/s) -host_op_rate 71929 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 393524726 # Simulator tick rate (ticks/s) -host_mem_usage 237176 # Number of bytes of host memory used -host_seconds 0.09 # Real time elapsed on the host +host_inst_rate 162128 # Simulator instruction rate (inst/s) +host_op_rate 162075 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 885888965 # Simulator tick rate (ticks/s) +host_mem_usage 292456 # Number of bytes of host memory used +host_seconds 0.04 # Real time elapsed on the host sim_insts 6400 # Number of instructions simulated sim_ops 6400 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -19,12 +19,12 @@ system.physmem.bytes_inst_read::cpu.inst 23296 # Nu system.physmem.bytes_inst_read::total 23296 # Number of instructions bytes read from this memory system.physmem.num_reads::cpu.inst 533 # Number of read requests responded to by this memory system.physmem.num_reads::total 533 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 974002427 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 974002427 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 665172389 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 665172389 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 974002427 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 974002427 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 974809607 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 974809607 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 665723634 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 665723634 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 974809607 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 974809607 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 533 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 533 # Number of DRAM read bursts, including those serviced by the write queue @@ -71,7 +71,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 34924000 # Total gap between requests +system.physmem.totGap 34895000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -196,19 +196,19 @@ system.physmem.bytesPerActivate::768-895 1 1.11% 84.44% # By system.physmem.bytesPerActivate::896-1023 4 4.44% 88.89% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 10 11.11% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 90 # Bytes accessed per row activation -system.physmem.totQLat 3887500 # Total ticks spent queuing -system.physmem.totMemAccLat 13881250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 3849750 # Total ticks spent queuing +system.physmem.totMemAccLat 13843500 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2665000 # Total ticks spent in databus transfers -system.physmem.avgQLat 7293.62 # Average queueing delay per DRAM burst +system.physmem.avgQLat 7222.80 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26043.62 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 974.00 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 25972.80 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 974.81 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 974.00 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 974.81 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 7.61 # Data bus utilization in percentage -system.physmem.busUtilRead 7.61 # Data bus utilization in percentage for reads +system.physmem.busUtil 7.62 # Data bus utilization in percentage +system.physmem.busUtilRead 7.62 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.21 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing @@ -216,31 +216,36 @@ system.physmem.readRowHits 435 # Nu system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 81.61 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 65523.45 # Average gap between requests +system.physmem.avgGap 65469.04 # Average gap between requests system.physmem.pageHitRate 81.61 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 15500 # Time in different power states -system.physmem.memoryStateTime::REF 1040000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 30393500 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 257040 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 385560 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 140250 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 210375 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 2082600 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 1677000 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 2034240 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 2034240 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 21425445 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 20164320 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 67500 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 1173750 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 26007075 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 25645245 # Total energy per rank (pJ) -system.physmem.averagePower::0 827.295718 # Core power per rank (mW) -system.physmem.averagePower::1 815.785757 # Core power per rank (mW) +system.physmem_0.actEnergy 257040 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 140250 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 2082600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 2034240 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 21404070 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 67500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 25985700 # Total energy per rank (pJ) +system.physmem_0.averagePower 827.438306 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 15500 # Time in different power states +system.physmem_0.memoryStateTime::REF 1040000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 30363250 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 385560 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 210375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1677000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 2034240 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 20164320 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1173750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 25645245 # Total energy per rank (pJ) +system.physmem_1.averagePower 815.785757 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2149750 # Time in different power states +system.physmem_1.memoryStateTime::REF 1040000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 28549750 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.branchPred.lookups 1972 # Number of BP lookups system.cpu.branchPred.condPredicted 1208 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 368 # Number of conditional branches incorrect @@ -284,26 +289,26 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 70045 # number of cpu cycles simulated +system.cpu.numCycles 69987 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 6400 # Number of instructions committed system.cpu.committedOps 6400 # Number of ops (including micro ops) committed system.cpu.discardedOps 1109 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 10.944531 # CPI: cycles per instruction -system.cpu.ipc 0.091370 # IPC: instructions per cycle -system.cpu.tickCycles 12615 # Number of cycles that the object actually ticked -system.cpu.idleCycles 57430 # Total number of cycles that the object has spent stopped +system.cpu.cpi 10.935469 # CPI: cycles per instruction +system.cpu.ipc 0.091446 # IPC: instructions per cycle +system.cpu.tickCycles 12616 # Number of cycles that the object actually ticked +system.cpu.idleCycles 57371 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 104.047628 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 104.036694 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1973 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 169 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 11.674556 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.inst 104.047628 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.inst 0.025402 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.025402 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.inst 104.036694 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.inst 0.025400 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.025400 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 169 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 25 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 144 # Occupied blocks per task id @@ -328,12 +333,12 @@ system.cpu.dcache.overall_misses::cpu.inst 227 # system.cpu.dcache.overall_misses::total 227 # number of overall misses system.cpu.dcache.ReadReq_miss_latency::cpu.inst 7703250 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 7703250 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 8679250 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 8679250 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.inst 16382500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 16382500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.inst 16382500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 16382500 # number of overall miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.inst 8670250 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 8670250 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.inst 16373500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 16373500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.inst 16373500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 16373500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.inst 1335 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1335 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.inst 865 # number of WriteReq accesses(hits+misses) @@ -352,12 +357,12 @@ system.cpu.dcache.overall_miss_rate::cpu.inst 0.103182 system.cpu.dcache.overall_miss_rate::total 0.103182 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 75522.058824 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 75522.058824 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 69434 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 69434 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 72169.603524 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 72169.603524 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 72169.603524 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 72169.603524 # average overall miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 69362 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 69362 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 72129.955947 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 72129.955947 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 72129.955947 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 72129.955947 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -384,12 +389,12 @@ system.cpu.dcache.overall_mshr_misses::cpu.inst 169 system.cpu.dcache.overall_mshr_misses::total 169 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 7131000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 7131000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 5128000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5128000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 12259000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 12259000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 12259000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 12259000 # number of overall MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 5119000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5119000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 12250000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 12250000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 12250000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 12250000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.071910 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.071910 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.084393 # mshr miss rate for WriteReq accesses @@ -400,25 +405,25 @@ system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.076818 system.cpu.dcache.overall_mshr_miss_rate::total 0.076818 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 74281.250000 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 74281.250000 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 70246.575342 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 70246.575342 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 72538.461538 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 72538.461538 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 72538.461538 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 72538.461538 # average overall mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 70123.287671 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 70123.287671 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 72485.207101 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 72485.207101 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 72485.207101 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 72485.207101 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 176.126032 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 176.047314 # Cycle average of tags in use system.cpu.icache.tags.total_refs 2277 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 365 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 6.238356 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 176.126032 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.085999 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.085999 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 176.047314 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.085961 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.085961 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 365 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 117 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 248 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 118 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 247 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.178223 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 5649 # Number of tag accesses system.cpu.icache.tags.data_accesses 5649 # Number of data accesses @@ -434,12 +439,12 @@ system.cpu.icache.demand_misses::cpu.inst 365 # n system.cpu.icache.demand_misses::total 365 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 365 # number of overall misses system.cpu.icache.overall_misses::total 365 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 25915750 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 25915750 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 25915750 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 25915750 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 25915750 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 25915750 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 25886500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 25886500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 25886500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 25886500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 25886500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 25886500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 2642 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 2642 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 2642 # number of demand (read+write) accesses @@ -452,12 +457,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.138153 system.cpu.icache.demand_miss_rate::total 0.138153 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.138153 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.138153 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 71002.054795 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 71002.054795 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 71002.054795 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 71002.054795 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 71002.054795 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 71002.054795 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70921.917808 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 70921.917808 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 70921.917808 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 70921.917808 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 70921.917808 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 70921.917808 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -472,37 +477,37 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 365 system.cpu.icache.demand_mshr_misses::total 365 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 365 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 365 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 25028250 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 25028250 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 25028250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 25028250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 25028250 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 25028250 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24998500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 24998500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24998500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 24998500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24998500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 24998500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.138153 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.138153 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.138153 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.138153 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.138153 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.138153 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68570.547945 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68570.547945 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68570.547945 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 68570.547945 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68570.547945 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 68570.547945 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68489.041096 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68489.041096 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68489.041096 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 68489.041096 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68489.041096 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 68489.041096 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 233.857006 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 233.762820 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 460 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.002174 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 233.857006 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.007137 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.007137 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 233.762820 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.007134 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.007134 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 460 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 134 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 326 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 135 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 325 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.014038 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 4805 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 4805 # Number of data accesses @@ -520,14 +525,14 @@ system.cpu.l2cache.demand_misses::cpu.inst 533 # system.cpu.l2cache.demand_misses::total 533 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 533 # number of overall misses system.cpu.l2cache.overall_misses::total 533 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 31686750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 31686750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 5053000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 5053000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 36739750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 36739750 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 36739750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 36739750 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 31657000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 31657000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 5044000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 5044000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 36701000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 36701000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 36701000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 36701000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 461 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 461 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.inst 73 # number of ReadExReq accesses(hits+misses) @@ -544,14 +549,14 @@ system.cpu.l2cache.demand_miss_rate::cpu.inst 0.998127 system.cpu.l2cache.demand_miss_rate::total 0.998127 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.998127 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.998127 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68884.239130 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 68884.239130 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 69219.178082 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69219.178082 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68930.112570 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 68930.112570 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68930.112570 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 68930.112570 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68819.565217 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 68819.565217 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 69095.890411 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69095.890411 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68857.410882 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 68857.410882 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68857.410882 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 68857.410882 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -568,14 +573,14 @@ system.cpu.l2cache.demand_mshr_misses::cpu.inst 533 system.cpu.l2cache.demand_mshr_misses::total 533 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 533 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 533 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 25921750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25921750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 4147500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4147500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 30069250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 30069250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 30069250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 30069250 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 25891500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25891500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 4138000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4138000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 30029500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 30029500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 30029500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 30029500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.997831 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997831 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadExReq accesses @@ -584,14 +589,14 @@ system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.998127 system.cpu.l2cache.demand_mshr_miss_rate::total 0.998127 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.998127 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.998127 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56351.630435 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56351.630435 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 56815.068493 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56815.068493 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56415.103189 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56415.103189 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56415.103189 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56415.103189 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56285.869565 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56285.869565 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 56684.931507 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56684.931507 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56340.525328 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56340.525328 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56340.525328 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56340.525328 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 461 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 461 # Transaction distribution @@ -617,7 +622,7 @@ system.cpu.toL2Bus.snoop_fanout::max_value 1 # system.cpu.toL2Bus.snoop_fanout::total 534 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 267000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 626250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 626500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 1.8 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 279000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) @@ -642,7 +647,7 @@ system.membus.snoop_fanout::max_value 0 # Re system.membus.snoop_fanout::total 533 # Request fanout histogram system.membus.reqLayer0.occupancy 606000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 4967250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4968000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 14.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt index c9776266f..7064bc28f 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000021 # Nu sim_ticks 20537500 # Number of ticks simulated final_tick 20537500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 69014 # Simulator instruction rate (inst/s) -host_op_rate 69006 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 222388397 # Simulator tick rate (ticks/s) -host_mem_usage 237256 # Number of bytes of host memory used -host_seconds 0.09 # Real time elapsed on the host +host_inst_rate 92569 # Simulator instruction rate (inst/s) +host_op_rate 92553 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 298254404 # Simulator tick rate (ticks/s) +host_mem_usage 293992 # Number of bytes of host memory used +host_seconds 0.07 # Real time elapsed on the host sim_insts 6372 # Number of instructions simulated sim_ops 6372 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -222,53 +222,34 @@ system.physmem.readRowHitRate 80.08 # Ro system.physmem.writeRowHitRate nan # Row buffer hit rate for writes system.physmem.avgGap 41913.76 # Average gap between requests system.physmem.pageHitRate 80.08 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 22000 # Time in different power states -system.physmem.memoryStateTime::REF 520000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 15339250 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 234360 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 332640 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 127875 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 181500 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 1755000 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 1365000 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 1017120 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 1017120 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 10809765 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 10569510 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 38250 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 249000 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 13982370 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 13714770 # Total energy per rank (pJ) -system.physmem.averagePower::0 881.195525 # Core power per rank (mW) -system.physmem.averagePower::1 864.330865 # Core power per rank (mW) -system.membus.trans_dist::ReadReq 415 # Transaction distribution -system.membus.trans_dist::ReadResp 415 # Transaction distribution -system.membus.trans_dist::ReadExReq 72 # Transaction distribution -system.membus.trans_dist::ReadExResp 72 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 974 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 974 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 31168 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 31168 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 487 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 487 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 487 # Request fanout histogram -system.membus.reqLayer0.occupancy 610000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 3.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 4554500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 22.2 # Layer utilization (%) -system.cpu_clk_domain.clock 500 # Clock period in ticks +system.physmem_0.actEnergy 234360 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 127875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1755000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 10809765 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 38250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 13982370 # Total energy per rank (pJ) +system.physmem_0.averagePower 881.195525 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 22000 # Time in different power states +system.physmem_0.memoryStateTime::REF 520000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 15339250 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 332640 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 181500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1365000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 10541295 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 252750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 13690305 # Total energy per rank (pJ) +system.physmem_1.averagePower 864.696352 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 637250 # Time in different power states +system.physmem_1.memoryStateTime::REF 520000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 14974750 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.branchPred.lookups 2806 # Number of BP lookups system.cpu.branchPred.condPredicted 1662 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 479 # Number of conditional branches incorrect @@ -278,6 +259,7 @@ system.cpu.branchPred.BTBCorrect 0 # Nu system.cpu.branchPred.BTBHitPct 32.481061 # BTB Hit Percentage system.cpu.branchPred.usedRAS 395 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 30 # Number of incorrect RAS predictions. +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -605,34 +587,118 @@ system.cpu.fp_regfile_reads 8 # nu system.cpu.fp_regfile_writes 2 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.trans_dist::ReadReq 416 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 416 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 72 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 72 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 628 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 348 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 976 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20096 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 11136 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 31232 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 488 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 488 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 488 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 244000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 528500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.6 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 276000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 107.148001 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 2314 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 174 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 13.298851 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 107.148001 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.026159 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.026159 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 174 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 119 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.042480 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 5846 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 5846 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 1808 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1808 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 506 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 506 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 2314 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2314 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2314 # number of overall hits +system.cpu.dcache.overall_hits::total 2314 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 163 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 163 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 359 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 359 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 522 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 522 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 522 # number of overall misses +system.cpu.dcache.overall_misses::total 522 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11503750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11503750 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 22566471 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 22566471 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 34070221 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 34070221 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 34070221 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 34070221 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1971 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1971 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 2836 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2836 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2836 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2836 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.082699 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.082699 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.415029 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.415029 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.184062 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.184062 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.184062 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.184062 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 70575.153374 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 70575.153374 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62859.250696 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 62859.250696 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 65268.622605 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 65268.622605 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 65268.622605 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 65268.622605 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 1879 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 42 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 44.738095 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 61 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 61 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 287 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 287 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 348 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 348 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 348 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 348 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 102 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 102 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 72 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 72 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 174 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 174 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 174 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 174 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8025750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 8025750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5483750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5483750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13509500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 13509500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13509500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 13509500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.051750 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.051750 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.083237 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.083237 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.061354 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.061354 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.061354 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.061354 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78683.823529 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78683.823529 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76163.194444 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76163.194444 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77640.804598 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 77640.804598 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77640.804598 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 77640.804598 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements system.cpu.icache.tags.tagsinuse 158.374396 # Cycle average of tags in use system.cpu.icache.tags.total_refs 1718 # Total number of references to valid blocks. @@ -854,117 +920,56 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57645.367412 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64275.862069 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60014.373717 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 107.148001 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 2314 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 174 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 13.298851 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 107.148001 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.026159 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.026159 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 174 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 119 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.042480 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 5846 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 5846 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 1808 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1808 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 506 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 506 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2314 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2314 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2314 # number of overall hits -system.cpu.dcache.overall_hits::total 2314 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 163 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 163 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 359 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 359 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 522 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 522 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 522 # number of overall misses -system.cpu.dcache.overall_misses::total 522 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11503750 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11503750 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 22566471 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 22566471 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 34070221 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 34070221 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 34070221 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 34070221 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1971 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1971 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2836 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2836 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2836 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2836 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.082699 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.082699 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.415029 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.415029 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.184062 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.184062 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.184062 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.184062 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 70575.153374 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 70575.153374 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62859.250696 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 62859.250696 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 65268.622605 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 65268.622605 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 65268.622605 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 65268.622605 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 1879 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 42 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 44.738095 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 61 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 61 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 287 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 287 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 348 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 348 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 348 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 348 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 102 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 102 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 72 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 72 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 174 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 174 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 174 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 174 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8025750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 8025750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5483750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5483750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13509500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 13509500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13509500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 13509500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.051750 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.051750 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.083237 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.083237 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.061354 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.061354 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.061354 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.061354 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78683.823529 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78683.823529 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76163.194444 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76163.194444 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77640.804598 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 77640.804598 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77640.804598 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 77640.804598 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.trans_dist::ReadReq 416 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 416 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 72 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 72 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 628 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 348 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 976 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20096 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 11136 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 31232 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 488 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 488 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 488 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 244000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 528500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 2.6 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 276000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) +system.membus.trans_dist::ReadReq 415 # Transaction distribution +system.membus.trans_dist::ReadResp 415 # Transaction distribution +system.membus.trans_dist::ReadExReq 72 # Transaction distribution +system.membus.trans_dist::ReadExResp 72 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 974 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 974 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 31168 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 31168 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 487 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 487 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 487 # Request fanout histogram +system.membus.reqLayer0.occupancy 610000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 3.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 4554500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 22.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/stats.txt index 95f3db4f2..aeda1c330 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000139 # Nu sim_ticks 138637 # Number of ticks simulated final_tick 138637 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 12523 # Simulator instruction rate (inst/s) -host_op_rate 12523 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 271684 # Simulator tick rate (ticks/s) -host_mem_usage 436940 # Number of bytes of host memory used -host_seconds 0.51 # Real time elapsed on the host +host_inst_rate 45640 # Simulator instruction rate (inst/s) +host_op_rate 45635 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 990010 # Simulator tick rate (ticks/s) +host_mem_usage 451208 # Number of bytes of host memory used +host_seconds 0.14 # Real time elapsed on the host sim_insts 6390 # Number of instructions simulated sim_ops 6390 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -237,29 +237,126 @@ system.mem_ctrls.readRowHitRate 81.03 # Ro system.mem_ctrls.writeRowHitRate 75.41 # Row buffer hit rate for writes system.mem_ctrls.avgGap 79.75 # Average gap between requests system.mem_ctrls.pageHitRate 80.50 # Row buffer hit rate, read and write combined -system.mem_ctrls.memoryStateTime::IDLE 211 # Time in different power states -system.mem_ctrls.memoryStateTime::REF 4420 # Time in different power states -system.mem_ctrls.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls.memoryStateTime::ACT 128005 # Time in different power states -system.mem_ctrls.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrls.actEnergy::0 559440 # Energy for activate commands per rank (pJ) -system.mem_ctrls.actEnergy::1 1103760 # Energy for activate commands per rank (pJ) -system.mem_ctrls.preEnergy::0 310800 # Energy for precharge commands per rank (pJ) -system.mem_ctrls.preEnergy::1 613200 # Energy for precharge commands per rank (pJ) -system.mem_ctrls.readEnergy::0 5828160 # Energy for read commands per rank (pJ) -system.mem_ctrls.readEnergy::1 8112000 # Energy for read commands per rank (pJ) -system.mem_ctrls.writeEnergy::0 362880 # Energy for write commands per rank (pJ) -system.mem_ctrls.writeEnergy::1 673920 # Energy for write commands per rank (pJ) -system.mem_ctrls.refreshEnergy::0 8645520 # Energy for refresh commands per rank (pJ) -system.mem_ctrls.refreshEnergy::1 8645520 # Energy for refresh commands per rank (pJ) -system.mem_ctrls.actBackEnergy::0 75333024 # Energy for active background per rank (pJ) -system.mem_ctrls.actBackEnergy::1 89081424 # Energy for active background per rank (pJ) -system.mem_ctrls.preBackEnergy::0 13491600 # Energy for precharge background per rank (pJ) -system.mem_ctrls.preBackEnergy::1 1431600 # Energy for precharge background per rank (pJ) -system.mem_ctrls.totalEnergy::0 104531424 # Total energy per rank (pJ) -system.mem_ctrls.totalEnergy::1 109661424 # Total energy per rank (pJ) -system.mem_ctrls.averagePower::0 788.190677 # Core power per rank (mW) -system.mem_ctrls.averagePower::1 826.872042 # Core power per rank (mW) +system.mem_ctrls_0.actEnergy 559440 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 310800 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 5828160 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 362880 # Energy for write commands per rank (pJ) +system.mem_ctrls_0.refreshEnergy 8645520 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_0.actBackEnergy 75338496 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 13486800 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.totalEnergy 104532096 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 788.195744 # Core power per rank (mW) +system.mem_ctrls_0.memoryStateTime::IDLE 25869 # Time in different power states +system.mem_ctrls_0.memoryStateTime::REF 4420 # Time in different power states +system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 106214 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls_1.actEnergy 1103760 # Energy for activate commands per rank (pJ) +system.mem_ctrls_1.preEnergy 613200 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_1.readEnergy 8112000 # Energy for read commands per rank (pJ) +system.mem_ctrls_1.writeEnergy 673920 # Energy for write commands per rank (pJ) +system.mem_ctrls_1.refreshEnergy 8645520 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_1.actBackEnergy 89081424 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 1431600 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.totalEnergy 109661424 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 826.872042 # Core power per rank (mW) +system.mem_ctrls_1.memoryStateTime::IDLE 1728 # Time in different power states +system.mem_ctrls_1.memoryStateTime::REF 4420 # Time in different power states +system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 126488 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.clk_domain.clock 1 # Clock period in ticks +system.cpu.dtb.fetch_hits 0 # ITB hits +system.cpu.dtb.fetch_misses 0 # ITB misses +system.cpu.dtb.fetch_acv 0 # ITB acv +system.cpu.dtb.fetch_accesses 0 # ITB accesses +system.cpu.dtb.read_hits 1183 # DTB read hits +system.cpu.dtb.read_misses 7 # DTB read misses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_accesses 1190 # DTB read accesses +system.cpu.dtb.write_hits 865 # DTB write hits +system.cpu.dtb.write_misses 3 # DTB write misses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_accesses 868 # DTB write accesses +system.cpu.dtb.data_hits 2048 # DTB hits +system.cpu.dtb.data_misses 10 # DTB misses +system.cpu.dtb.data_acv 0 # DTB access violations +system.cpu.dtb.data_accesses 2058 # DTB accesses +system.cpu.itb.fetch_hits 6401 # ITB hits +system.cpu.itb.fetch_misses 17 # ITB misses +system.cpu.itb.fetch_acv 0 # ITB acv +system.cpu.itb.fetch_accesses 6418 # ITB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_acv 0 # DTB read access violations +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_acv 0 # DTB write access violations +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.data_hits 0 # DTB hits +system.cpu.itb.data_misses 0 # DTB misses +system.cpu.itb.data_acv 0 # DTB access violations +system.cpu.itb.data_accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 17 # Number of system calls +system.cpu.numCycles 138637 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 6390 # Number of instructions committed +system.cpu.committedOps 6390 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 6317 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses +system.cpu.num_func_calls 251 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 749 # number of instructions that are conditional controls +system.cpu.num_int_insts 6317 # number of integer instructions +system.cpu.num_fp_insts 10 # number of float instructions +system.cpu.num_int_register_reads 8285 # number of times the integer registers were read +system.cpu.num_int_register_writes 4568 # number of times the integer registers were written +system.cpu.num_fp_register_reads 8 # number of times the floating registers were read +system.cpu.num_fp_register_writes 2 # number of times the floating registers were written +system.cpu.num_mem_refs 2058 # number of memory refs +system.cpu.num_load_insts 1190 # Number of load instructions +system.cpu.num_store_insts 868 # Number of store instructions +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 138637 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.Branches 1050 # Number of branches fetched +system.cpu.op_class::No_OpClass 19 0.30% 0.30% # Class of executed instruction +system.cpu.op_class::IntAlu 4320 67.50% 67.80% # Class of executed instruction +system.cpu.op_class::IntMult 1 0.02% 67.81% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 67.81% # Class of executed instruction +system.cpu.op_class::FloatAdd 2 0.03% 67.84% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::MemRead 1190 18.59% 86.44% # Class of executed instruction +system.cpu.op_class::MemWrite 868 13.56% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 6400 # Class of executed instruction system.ruby.clk_domain.clock 1 # Clock period in ticks system.ruby.delayHist::bucket_size 1 # delay histogram for all message system.ruby.delayHist::max_bucket 9 # delay histogram for all message @@ -279,8 +376,8 @@ system.ruby.latency_hist::bucket_size 64 system.ruby.latency_hist::max_bucket 639 system.ruby.latency_hist::samples 8448 system.ruby.latency_hist::mean 15.410630 -system.ruby.latency_hist::gmean 5.220511 -system.ruby.latency_hist::stdev 29.550250 +system.ruby.latency_hist::gmean 5.220490 +system.ruby.latency_hist::stdev 29.556532 system.ruby.latency_hist | 7278 86.15% 86.15% | 1151 13.62% 99.78% | 3 0.04% 99.81% | 2 0.02% 99.83% | 6 0.07% 99.91% | 8 0.09% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.latency_hist::total 8448 system.ruby.hit_latency_hist::bucket_size 1 @@ -294,8 +391,8 @@ system.ruby.miss_latency_hist::bucket_size 64 system.ruby.miss_latency_hist::max_bucket 639 system.ruby.miss_latency_hist::samples 1490 system.ruby.miss_latency_hist::mean 73.365772 -system.ruby.miss_latency_hist::gmean 69.379008 -system.ruby.miss_latency_hist::stdev 29.545012 +system.ruby.miss_latency_hist::gmean 69.377440 +system.ruby.miss_latency_hist::stdev 29.580633 system.ruby.miss_latency_hist | 320 21.48% 21.48% | 1151 77.25% 98.72% | 3 0.20% 98.93% | 2 0.13% 99.06% | 6 0.40% 99.46% | 8 0.54% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.miss_latency_hist::total 1490 system.ruby.l1_cntrl0.L1Dcache.demand_hits 1249 # Number of cache demand hits @@ -304,7 +401,6 @@ system.ruby.l1_cntrl0.L1Dcache.demand_accesses 2048 system.ruby.l1_cntrl0.L1Icache.demand_hits 5709 # Number of cache demand hits system.ruby.l1_cntrl0.L1Icache.demand_misses 691 # Number of cache demand misses system.ruby.l1_cntrl0.L1Icache.demand_accesses 6400 # Number of cache demand accesses -system.cpu.clk_domain.clock 1 # Clock period in ticks system.ruby.l1_cntrl0.prefetcher.miss_observed 0 # number of misses observed system.ruby.l1_cntrl0.prefetcher.allocated_streams 0 # number of streams allocated for prefetching system.ruby.l1_cntrl0.prefetcher.prefetches_requested 0 # number of prefetch requests made @@ -314,6 +410,10 @@ system.ruby.l1_cntrl0.prefetcher.hits 0 # nu system.ruby.l1_cntrl0.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched system.ruby.l1_cntrl0.prefetcher.pages_crossed 0 # number of prefetches across pages system.ruby.l1_cntrl0.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed +system.ruby.l2_cntrl0.L2cache.demand_hits 30 # Number of cache demand hits +system.ruby.l2_cntrl0.L2cache.demand_misses 1460 # Number of cache demand misses +system.ruby.l2_cntrl0.L2cache.demand_accesses 1490 # Number of cache demand accesses +system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks system.ruby.network.routers0.percent_links_utilized 3.776229 system.ruby.network.routers0.msg_count.Control::0 1490 system.ruby.network.routers0.msg_count.Request_Control::2 1041 @@ -331,9 +431,6 @@ system.ruby.network.routers0.msg_bytes.Response_Control::2 6392 system.ruby.network.routers0.msg_bytes.Writeback_Data::0 10440 system.ruby.network.routers0.msg_bytes.Writeback_Data::1 10152 system.ruby.network.routers0.msg_bytes.Writeback_Control::0 2328 -system.ruby.l2_cntrl0.L2cache.demand_hits 30 # Number of cache demand hits -system.ruby.l2_cntrl0.L2cache.demand_misses 1460 # Number of cache demand misses -system.ruby.l2_cntrl0.L2cache.demand_accesses 1490 # Number of cache demand accesses system.ruby.network.routers1.percent_links_utilized 7.332278 system.ruby.network.routers1.msg_count.Control::0 2950 system.ruby.network.routers1.msg_count.Request_Control::2 1041 @@ -387,98 +484,6 @@ system.ruby.network.msg_byte.Response_Data 697032 system.ruby.network.msg_byte.Response_Control 114288 system.ruby.network.msg_byte.Writeback_Data 61776 system.ruby.network.msg_byte.Writeback_Control 6984 -system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 1183 # DTB read hits -system.cpu.dtb.read_misses 7 # DTB read misses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 1190 # DTB read accesses -system.cpu.dtb.write_hits 865 # DTB write hits -system.cpu.dtb.write_misses 3 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 868 # DTB write accesses -system.cpu.dtb.data_hits 2048 # DTB hits -system.cpu.dtb.data_misses 10 # DTB misses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 2058 # DTB accesses -system.cpu.itb.fetch_hits 6401 # ITB hits -system.cpu.itb.fetch_misses 17 # ITB misses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 6418 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 138637 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 6390 # Number of instructions committed -system.cpu.committedOps 6390 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 6317 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses -system.cpu.num_func_calls 251 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 749 # number of instructions that are conditional controls -system.cpu.num_int_insts 6317 # number of integer instructions -system.cpu.num_fp_insts 10 # number of float instructions -system.cpu.num_int_register_reads 8285 # number of times the integer registers were read -system.cpu.num_int_register_writes 4568 # number of times the integer registers were written -system.cpu.num_fp_register_reads 8 # number of times the floating registers were read -system.cpu.num_fp_register_writes 2 # number of times the floating registers were written -system.cpu.num_mem_refs 2058 # number of memory refs -system.cpu.num_load_insts 1190 # Number of load instructions -system.cpu.num_store_insts 868 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 138637 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.Branches 1050 # Number of branches fetched -system.cpu.op_class::No_OpClass 19 0.30% 0.30% # Class of executed instruction -system.cpu.op_class::IntAlu 4320 67.50% 67.80% # Class of executed instruction -system.cpu.op_class::IntMult 1 0.02% 67.81% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 67.81% # Class of executed instruction -system.cpu.op_class::FloatAdd 2 0.03% 67.84% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::MemRead 1190 18.59% 86.44% # Class of executed instruction -system.cpu.op_class::MemWrite 868 13.56% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 6400 # Class of executed instruction system.ruby.network.routers0.throttle0.link_utilization 5.369057 system.ruby.network.routers0.throttle0.msg_count.Request_Control::2 1041 system.ruby.network.routers0.throttle0.msg_count.Response_Data::1 1490 @@ -609,9 +614,9 @@ system.ruby.LD.miss_latency_hist::total 583 system.ruby.ST.latency_hist::bucket_size 64 system.ruby.ST.latency_hist::max_bucket 639 system.ruby.ST.latency_hist::samples 865 -system.ruby.ST.latency_hist::mean 17.899422 -system.ruby.ST.latency_hist::gmean 6.261931 -system.ruby.ST.latency_hist::stdev 30.808929 +system.ruby.ST.latency_hist::mean 17.890173 +system.ruby.ST.latency_hist::gmean 6.261514 +system.ruby.ST.latency_hist::stdev 30.772511 system.ruby.ST.latency_hist | 767 88.67% 88.67% | 95 10.98% 99.65% | 1 0.12% 99.77% | 0 0.00% 99.77% | 0 0.00% 99.77% | 2 0.23% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.ST.latency_hist::total 865 system.ruby.ST.hit_latency_hist::bucket_size 1 @@ -624,17 +629,17 @@ system.ruby.ST.hit_latency_hist::total 649 system.ruby.ST.miss_latency_hist::bucket_size 64 system.ruby.ST.miss_latency_hist::max_bucket 639 system.ruby.ST.miss_latency_hist::samples 216 -system.ruby.ST.miss_latency_hist::mean 62.666667 -system.ruby.ST.miss_latency_hist::gmean 57.141141 -system.ruby.ST.miss_latency_hist::stdev 33.628615 +system.ruby.ST.miss_latency_hist::mean 62.629630 +system.ruby.ST.miss_latency_hist::gmean 57.125913 +system.ruby.ST.miss_latency_hist::stdev 33.544027 system.ruby.ST.miss_latency_hist | 118 54.63% 54.63% | 95 43.98% 98.61% | 1 0.46% 99.07% | 0 0.00% 99.07% | 0 0.00% 99.07% | 2 0.93% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.ST.miss_latency_hist::total 216 system.ruby.IFETCH.latency_hist::bucket_size 64 system.ruby.IFETCH.latency_hist::max_bucket 639 system.ruby.IFETCH.latency_hist::samples 6400 -system.ruby.IFETCH.latency_hist::mean 11.389844 -system.ruby.IFETCH.latency_hist::gmean 4.264766 -system.ruby.IFETCH.latency_hist::stdev 26.115167 +system.ruby.IFETCH.latency_hist::mean 11.391094 +system.ruby.IFETCH.latency_hist::gmean 4.264782 +system.ruby.IFETCH.latency_hist::stdev 26.130654 system.ruby.IFETCH.latency_hist | 5714 89.28% 89.28% | 673 10.52% 99.80% | 1 0.02% 99.81% | 2 0.03% 99.84% | 5 0.08% 99.92% | 5 0.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.latency_hist::total 6400 system.ruby.IFETCH.hit_latency_hist::bucket_size 1 @@ -647,11 +652,21 @@ system.ruby.IFETCH.hit_latency_hist::total 5709 system.ruby.IFETCH.miss_latency_hist::bucket_size 64 system.ruby.IFETCH.miss_latency_hist::max_bucket 639 system.ruby.IFETCH.miss_latency_hist::samples 691 -system.ruby.IFETCH.miss_latency_hist::mean 80.706223 -system.ruby.IFETCH.miss_latency_hist::gmean 78.001693 -system.ruby.IFETCH.miss_latency_hist::stdev 30.507480 +system.ruby.IFETCH.miss_latency_hist::mean 80.717800 +system.ruby.IFETCH.miss_latency_hist::gmean 78.004389 +system.ruby.IFETCH.miss_latency_hist::stdev 30.603968 system.ruby.IFETCH.miss_latency_hist | 5 0.72% 0.72% | 673 97.40% 98.12% | 1 0.14% 98.26% | 2 0.29% 98.55% | 5 0.72% 99.28% | 5 0.72% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.miss_latency_hist::total 691 +system.ruby.Directory_Controller.Fetch 1460 0.00% 0.00% +system.ruby.Directory_Controller.Data 277 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Data 1460 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Ack 277 0.00% 0.00% +system.ruby.Directory_Controller.CleanReplacement 1175 0.00% 0.00% +system.ruby.Directory_Controller.I.Fetch 1460 0.00% 0.00% +system.ruby.Directory_Controller.M.Data 277 0.00% 0.00% +system.ruby.Directory_Controller.M.CleanReplacement 1175 0.00% 0.00% +system.ruby.Directory_Controller.IM.Memory_Data 1460 0.00% 0.00% +system.ruby.Directory_Controller.MI.Memory_Ack 277 0.00% 0.00% system.ruby.L1Cache_Controller.Load 1183 0.00% 0.00% system.ruby.L1Cache_Controller.Ifetch 6400 0.00% 0.00% system.ruby.L1Cache_Controller.Store 865 0.00% 0.00% @@ -716,15 +731,5 @@ system.ruby.L2Cache_Controller.ISS.Mem_Data 570 0.00% 0.00% system.ruby.L2Cache_Controller.IS.Mem_Data 686 0.00% 0.00% system.ruby.L2Cache_Controller.IM.Mem_Data 204 0.00% 0.00% system.ruby.L2Cache_Controller.MT_MB.Exclusive_Unblock 799 0.00% 0.00% -system.ruby.Directory_Controller.Fetch 1460 0.00% 0.00% -system.ruby.Directory_Controller.Data 277 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Data 1460 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Ack 277 0.00% 0.00% -system.ruby.Directory_Controller.CleanReplacement 1175 0.00% 0.00% -system.ruby.Directory_Controller.I.Fetch 1460 0.00% 0.00% -system.ruby.Directory_Controller.M.Data 277 0.00% 0.00% -system.ruby.Directory_Controller.M.CleanReplacement 1175 0.00% 0.00% -system.ruby.Directory_Controller.IM.Memory_Data 1460 0.00% 0.00% -system.ruby.Directory_Controller.MI.Memory_Ack 277 0.00% 0.00% ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt index a7cf38c09..d5c587675 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000126 # Nu sim_ticks 126195 # Number of ticks simulated final_tick 126195 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 17040 # Simulator instruction rate (inst/s) -host_op_rate 17039 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 336486 # Simulator tick rate (ticks/s) -host_mem_usage 440076 # Number of bytes of host memory used -host_seconds 0.38 # Real time elapsed on the host +host_inst_rate 43805 # Simulator instruction rate (inst/s) +host_op_rate 43801 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 864948 # Simulator tick rate (ticks/s) +host_mem_usage 454088 # Number of bytes of host memory used +host_seconds 0.15 # Real time elapsed on the host sim_insts 6390 # Number of instructions simulated sim_ops 6390 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -230,36 +230,133 @@ system.mem_ctrls.busUtil 4.32 # Da system.mem_ctrls.busUtilRead 4.00 # Data bus utilization in percentage for reads system.mem_ctrls.busUtilWrite 0.32 # Data bus utilization in percentage for writes system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing -system.mem_ctrls.avgWrQLen 22.41 # Average write queue length when enqueuing +system.mem_ctrls.avgWrQLen 22.42 # Average write queue length when enqueuing system.mem_ctrls.readRowHits 799 # Number of row buffer hits during reads system.mem_ctrls.writeRowHits 76 # Number of row buffer hits during writes system.mem_ctrls.readRowHitRate 79.19 # Row buffer hit rate for reads system.mem_ctrls.writeRowHitRate 68.47 # Row buffer hit rate for writes system.mem_ctrls.avgGap 91.66 # Average gap between requests system.mem_ctrls.pageHitRate 78.12 # Row buffer hit rate, read and write combined -system.mem_ctrls.memoryStateTime::IDLE 232 # Time in different power states -system.mem_ctrls.memoryStateTime::REF 4160 # Time in different power states -system.mem_ctrls.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls.memoryStateTime::ACT 120458 # Time in different power states -system.mem_ctrls.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrls.actEnergy::0 551880 # Energy for activate commands per rank (pJ) -system.mem_ctrls.actEnergy::1 1035720 # Energy for activate commands per rank (pJ) -system.mem_ctrls.preEnergy::0 306600 # Energy for precharge commands per rank (pJ) -system.mem_ctrls.preEnergy::1 575400 # Energy for precharge commands per rank (pJ) -system.mem_ctrls.readEnergy::0 4992000 # Energy for read commands per rank (pJ) -system.mem_ctrls.readEnergy::1 7450560 # Energy for read commands per rank (pJ) -system.mem_ctrls.writeEnergy::0 186624 # Energy for write commands per rank (pJ) -system.mem_ctrls.writeEnergy::1 663552 # Energy for write commands per rank (pJ) -system.mem_ctrls.refreshEnergy::0 8136960 # Energy for refresh commands per rank (pJ) -system.mem_ctrls.refreshEnergy::1 8136960 # Energy for refresh commands per rank (pJ) -system.mem_ctrls.actBackEnergy::0 64157832 # Energy for active background per rank (pJ) -system.mem_ctrls.actBackEnergy::1 84064968 # Energy for active background per rank (pJ) -system.mem_ctrls.preBackEnergy::0 18622800 # Energy for precharge background per rank (pJ) -system.mem_ctrls.preBackEnergy::1 1160400 # Energy for precharge background per rank (pJ) -system.mem_ctrls.totalEnergy::0 96954696 # Total energy per rank (pJ) -system.mem_ctrls.totalEnergy::1 103087560 # Total energy per rank (pJ) -system.mem_ctrls.averagePower::0 776.656541 # Core power per rank (mW) -system.mem_ctrls.averagePower::1 825.783908 # Core power per rank (mW) +system.mem_ctrls_0.actEnergy 551880 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 306600 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 4992000 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 186624 # Energy for write commands per rank (pJ) +system.mem_ctrls_0.refreshEnergy 8136960 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_0.actBackEnergy 64142784 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 18636000 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.totalEnergy 96952848 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 776.641738 # Core power per rank (mW) +system.mem_ctrls_0.memoryStateTime::IDLE 31414 # Time in different power states +system.mem_ctrls_0.memoryStateTime::REF 4160 # Time in different power states +system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 90106 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls_1.actEnergy 1035720 # Energy for activate commands per rank (pJ) +system.mem_ctrls_1.preEnergy 575400 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_1.readEnergy 7450560 # Energy for read commands per rank (pJ) +system.mem_ctrls_1.writeEnergy 663552 # Energy for write commands per rank (pJ) +system.mem_ctrls_1.refreshEnergy 8136960 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_1.actBackEnergy 84064968 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 1160400 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.totalEnergy 103087560 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 825.783908 # Core power per rank (mW) +system.mem_ctrls_1.memoryStateTime::IDLE 1262 # Time in different power states +system.mem_ctrls_1.memoryStateTime::REF 4160 # Time in different power states +system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 119428 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.clk_domain.clock 1 # Clock period in ticks +system.cpu.dtb.fetch_hits 0 # ITB hits +system.cpu.dtb.fetch_misses 0 # ITB misses +system.cpu.dtb.fetch_acv 0 # ITB acv +system.cpu.dtb.fetch_accesses 0 # ITB accesses +system.cpu.dtb.read_hits 1183 # DTB read hits +system.cpu.dtb.read_misses 7 # DTB read misses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_accesses 1190 # DTB read accesses +system.cpu.dtb.write_hits 865 # DTB write hits +system.cpu.dtb.write_misses 3 # DTB write misses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_accesses 868 # DTB write accesses +system.cpu.dtb.data_hits 2048 # DTB hits +system.cpu.dtb.data_misses 10 # DTB misses +system.cpu.dtb.data_acv 0 # DTB access violations +system.cpu.dtb.data_accesses 2058 # DTB accesses +system.cpu.itb.fetch_hits 6401 # ITB hits +system.cpu.itb.fetch_misses 17 # ITB misses +system.cpu.itb.fetch_acv 0 # ITB acv +system.cpu.itb.fetch_accesses 6418 # ITB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_acv 0 # DTB read access violations +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_acv 0 # DTB write access violations +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.data_hits 0 # DTB hits +system.cpu.itb.data_misses 0 # DTB misses +system.cpu.itb.data_acv 0 # DTB access violations +system.cpu.itb.data_accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 17 # Number of system calls +system.cpu.numCycles 126195 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 6390 # Number of instructions committed +system.cpu.committedOps 6390 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 6317 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses +system.cpu.num_func_calls 251 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 749 # number of instructions that are conditional controls +system.cpu.num_int_insts 6317 # number of integer instructions +system.cpu.num_fp_insts 10 # number of float instructions +system.cpu.num_int_register_reads 8285 # number of times the integer registers were read +system.cpu.num_int_register_writes 4568 # number of times the integer registers were written +system.cpu.num_fp_register_reads 8 # number of times the floating registers were read +system.cpu.num_fp_register_writes 2 # number of times the floating registers were written +system.cpu.num_mem_refs 2058 # number of memory refs +system.cpu.num_load_insts 1190 # Number of load instructions +system.cpu.num_store_insts 868 # Number of store instructions +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 126195 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.Branches 1050 # Number of branches fetched +system.cpu.op_class::No_OpClass 19 0.30% 0.30% # Class of executed instruction +system.cpu.op_class::IntAlu 4320 67.50% 67.80% # Class of executed instruction +system.cpu.op_class::IntMult 1 0.02% 67.81% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 67.81% # Class of executed instruction +system.cpu.op_class::FloatAdd 2 0.03% 67.84% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::MemRead 1190 18.59% 86.44% # Class of executed instruction +system.cpu.op_class::MemWrite 868 13.56% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 6400 # Class of executed instruction system.ruby.clk_domain.clock 1 # Clock period in ticks system.ruby.outstanding_req_hist::bucket_size 1 system.ruby.outstanding_req_hist::max_bucket 9 @@ -272,8 +369,8 @@ system.ruby.latency_hist::bucket_size 64 system.ruby.latency_hist::max_bucket 639 system.ruby.latency_hist::samples 8448 system.ruby.latency_hist::mean 13.937855 -system.ruby.latency_hist::gmean 4.957822 -system.ruby.latency_hist::stdev 28.418252 +system.ruby.latency_hist::gmean 4.957827 +system.ruby.latency_hist::stdev 28.413153 system.ruby.latency_hist | 7438 88.04% 88.04% | 992 11.74% 99.79% | 2 0.02% 99.81% | 1 0.01% 99.82% | 11 0.13% 99.95% | 3 0.04% 99.99% | 1 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.latency_hist::total 8448 system.ruby.hit_latency_hist::bucket_size 1 @@ -287,8 +384,8 @@ system.ruby.miss_latency_hist::bucket_size 64 system.ruby.miss_latency_hist::max_bucket 639 system.ruby.miss_latency_hist::samples 1421 system.ruby.miss_latency_hist::mean 68.026742 -system.ruby.miss_latency_hist::gmean 59.451623 -system.ruby.miss_latency_hist::stdev 35.838026 +system.ruby.miss_latency_hist::gmean 59.451968 +system.ruby.miss_latency_hist::stdev 35.813966 system.ruby.miss_latency_hist | 411 28.92% 28.92% | 992 69.81% 98.73% | 2 0.14% 98.87% | 1 0.07% 98.94% | 11 0.77% 99.72% | 3 0.21% 99.93% | 1 0.07% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.miss_latency_hist::total 1421 system.ruby.l1_cntrl0.L1Dcache.demand_hits 1273 # Number of cache demand hits @@ -297,7 +394,10 @@ system.ruby.l1_cntrl0.L1Dcache.demand_accesses 2048 system.ruby.l1_cntrl0.L1Icache.demand_hits 5754 # Number of cache demand hits system.ruby.l1_cntrl0.L1Icache.demand_misses 646 # Number of cache demand misses system.ruby.l1_cntrl0.L1Icache.demand_accesses 6400 # Number of cache demand accesses -system.cpu.clk_domain.clock 1 # Clock period in ticks +system.ruby.l2_cntrl0.L2cache.demand_hits 239 # Number of cache demand hits +system.ruby.l2_cntrl0.L2cache.demand_misses 1182 # Number of cache demand misses +system.ruby.l2_cntrl0.L2cache.demand_accesses 1421 # Number of cache demand accesses +system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks system.ruby.network.routers0.percent_links_utilized 5.974286 system.ruby.network.routers0.msg_count.Request_Control::0 1421 system.ruby.network.routers0.msg_count.Response_Data::2 1182 @@ -311,9 +411,6 @@ system.ruby.network.routers0.msg_bytes.ResponseL2hit_Data::2 17208 system.ruby.network.routers0.msg_bytes.Writeback_Data::2 94176 system.ruby.network.routers0.msg_bytes.Writeback_Control::0 21664 system.ruby.network.routers0.msg_bytes.Unblock_Control::2 11736 -system.ruby.l2_cntrl0.L2cache.demand_hits 239 # Number of cache demand hits -system.ruby.l2_cntrl0.L2cache.demand_misses 1182 # Number of cache demand misses -system.ruby.l2_cntrl0.L2cache.demand_accesses 1421 # Number of cache demand accesses system.ruby.network.routers1.percent_links_utilized 8.972820 system.ruby.network.routers1.msg_count.Request_Control::0 1421 system.ruby.network.routers1.msg_count.Request_Control::1 1182 @@ -371,98 +468,6 @@ system.ruby.network.msg_byte.ResponseL2hit_Data 51624 system.ruby.network.msg_byte.Writeback_Data 324432 system.ruby.network.msg_byte.Writeback_Control 74304 system.ruby.network.msg_byte.Unblock_Control 63576 -system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 1183 # DTB read hits -system.cpu.dtb.read_misses 7 # DTB read misses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 1190 # DTB read accesses -system.cpu.dtb.write_hits 865 # DTB write hits -system.cpu.dtb.write_misses 3 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 868 # DTB write accesses -system.cpu.dtb.data_hits 2048 # DTB hits -system.cpu.dtb.data_misses 10 # DTB misses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 2058 # DTB accesses -system.cpu.itb.fetch_hits 6401 # ITB hits -system.cpu.itb.fetch_misses 17 # ITB misses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 6418 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 126195 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 6390 # Number of instructions committed -system.cpu.committedOps 6390 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 6317 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses -system.cpu.num_func_calls 251 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 749 # number of instructions that are conditional controls -system.cpu.num_int_insts 6317 # number of integer instructions -system.cpu.num_fp_insts 10 # number of float instructions -system.cpu.num_int_register_reads 8285 # number of times the integer registers were read -system.cpu.num_int_register_writes 4568 # number of times the integer registers were written -system.cpu.num_fp_register_reads 8 # number of times the floating registers were read -system.cpu.num_fp_register_writes 2 # number of times the floating registers were written -system.cpu.num_mem_refs 2058 # number of memory refs -system.cpu.num_load_insts 1190 # Number of load instructions -system.cpu.num_store_insts 868 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 126195 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.Branches 1050 # Number of branches fetched -system.cpu.op_class::No_OpClass 19 0.30% 0.30% # Class of executed instruction -system.cpu.op_class::IntAlu 4320 67.50% 67.80% # Class of executed instruction -system.cpu.op_class::IntMult 1 0.02% 67.81% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 67.81% # Class of executed instruction -system.cpu.op_class::FloatAdd 2 0.03% 67.84% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::MemRead 1190 18.59% 86.44% # Class of executed instruction -system.cpu.op_class::MemWrite 868 13.56% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 6400 # Class of executed instruction system.ruby.network.routers0.throttle0.link_utilization 5.603629 system.ruby.network.routers0.throttle0.msg_count.Response_Data::2 1182 system.ruby.network.routers0.throttle0.msg_count.ResponseL2hit_Data::2 239 @@ -553,9 +558,9 @@ system.ruby.network.routers3.throttle2.msg_bytes.Unblock_Control::2 9456 system.ruby.LD.latency_hist::bucket_size 64 system.ruby.LD.latency_hist::max_bucket 639 system.ruby.LD.latency_hist::samples 1183 -system.ruby.LD.latency_hist::mean 29.355030 -system.ruby.LD.latency_hist::gmean 10.774857 -system.ruby.LD.latency_hist::stdev 36.604149 +system.ruby.LD.latency_hist::mean 29.370245 +system.ruby.LD.latency_hist::gmean 10.775321 +system.ruby.LD.latency_hist::stdev 36.738545 system.ruby.LD.latency_hist | 860 72.70% 72.70% | 320 27.05% 99.75% | 0 0.00% 99.75% | 0 0.00% 99.75% | 2 0.17% 99.92% | 1 0.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.latency_hist::total 1183 system.ruby.LD.hit_latency_hist::bucket_size 1 @@ -568,9 +573,9 @@ system.ruby.LD.hit_latency_hist::total 658 system.ruby.LD.miss_latency_hist::bucket_size 64 system.ruby.LD.miss_latency_hist::max_bucket 639 system.ruby.LD.miss_latency_hist::samples 525 -system.ruby.LD.miss_latency_hist::mean 62.386667 -system.ruby.LD.miss_latency_hist::gmean 53.502649 -system.ruby.LD.miss_latency_hist::stdev 32.511258 +system.ruby.LD.miss_latency_hist::mean 62.420952 +system.ruby.LD.miss_latency_hist::gmean 53.507846 +system.ruby.LD.miss_latency_hist::stdev 32.816863 system.ruby.LD.miss_latency_hist | 202 38.48% 38.48% | 320 60.95% 99.43% | 0 0.00% 99.43% | 0 0.00% 99.43% | 2 0.38% 99.81% | 1 0.19% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.miss_latency_hist::total 525 system.ruby.ST.latency_hist::bucket_size 64 @@ -599,9 +604,9 @@ system.ruby.ST.miss_latency_hist::total 250 system.ruby.IFETCH.latency_hist::bucket_size 64 system.ruby.IFETCH.latency_hist::max_bucket 639 system.ruby.IFETCH.latency_hist::samples 6400 -system.ruby.IFETCH.latency_hist::mean 10.378594 -system.ruby.IFETCH.latency_hist::gmean 4.114908 -system.ruby.IFETCH.latency_hist::stdev 25.040800 +system.ruby.IFETCH.latency_hist::mean 10.375781 +system.ruby.IFETCH.latency_hist::gmean 4.114880 +system.ruby.IFETCH.latency_hist::stdev 24.994631 system.ruby.IFETCH.latency_hist | 5825 91.02% 91.02% | 564 8.81% 99.83% | 0 0.00% 99.83% | 1 0.02% 99.84% | 8 0.12% 99.97% | 1 0.02% 99.98% | 1 0.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.latency_hist::total 6400 system.ruby.IFETCH.hit_latency_hist::bucket_size 1 @@ -614,11 +619,33 @@ system.ruby.IFETCH.hit_latency_hist::total 5754 system.ruby.IFETCH.miss_latency_hist::bucket_size 64 system.ruby.IFETCH.miss_latency_hist::max_bucket 639 system.ruby.IFETCH.miss_latency_hist::samples 646 -system.ruby.IFETCH.miss_latency_hist::mean 76.100619 -system.ruby.IFETCH.miss_latency_hist::gmean 68.669414 -system.ruby.IFETCH.miss_latency_hist::stdev 37.537546 +system.ruby.IFETCH.miss_latency_hist::mean 76.072755 +system.ruby.IFETCH.miss_latency_hist::gmean 68.664868 +system.ruby.IFETCH.miss_latency_hist::stdev 37.280241 system.ruby.IFETCH.miss_latency_hist | 71 10.99% 10.99% | 564 87.31% 98.30% | 0 0.00% 98.30% | 1 0.15% 98.45% | 8 1.24% 99.69% | 1 0.15% 99.85% | 1 0.15% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.miss_latency_hist::total 646 +system.ruby.Directory_Controller.GETX 198 0.00% 0.00% +system.ruby.Directory_Controller.GETS 984 0.00% 0.00% +system.ruby.Directory_Controller.PUTX 194 0.00% 0.00% +system.ruby.Directory_Controller.Unblock 466 0.00% 0.00% +system.ruby.Directory_Controller.Last_Unblock 518 0.00% 0.00% +system.ruby.Directory_Controller.Exclusive_Unblock 198 0.00% 0.00% +system.ruby.Directory_Controller.Dirty_Writeback 194 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Data 1182 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Ack 194 0.00% 0.00% +system.ruby.Directory_Controller.I.GETX 111 0.00% 0.00% +system.ruby.Directory_Controller.I.GETS 466 0.00% 0.00% +system.ruby.Directory_Controller.I.Memory_Ack 194 0.00% 0.00% +system.ruby.Directory_Controller.S.GETX 87 0.00% 0.00% +system.ruby.Directory_Controller.S.GETS 518 0.00% 0.00% +system.ruby.Directory_Controller.M.PUTX 194 0.00% 0.00% +system.ruby.Directory_Controller.IS.Unblock 466 0.00% 0.00% +system.ruby.Directory_Controller.IS.Memory_Data 466 0.00% 0.00% +system.ruby.Directory_Controller.SS.Last_Unblock 518 0.00% 0.00% +system.ruby.Directory_Controller.SS.Memory_Data 518 0.00% 0.00% +system.ruby.Directory_Controller.MM.Exclusive_Unblock 198 0.00% 0.00% +system.ruby.Directory_Controller.MM.Memory_Data 198 0.00% 0.00% +system.ruby.Directory_Controller.MI.Dirty_Writeback 194 0.00% 0.00% system.ruby.L1Cache_Controller.Load 1183 0.00% 0.00% system.ruby.L1Cache_Controller.Ifetch 6400 0.00% 0.00% system.ruby.L1Cache_Controller.Store 865 0.00% 0.00% @@ -696,27 +723,5 @@ system.ruby.L2Cache_Controller.MM.Exclusive_Unblock 52 0.00% system.ruby.L2Cache_Controller.SS.Unblock 141 0.00% 0.00% system.ruby.L2Cache_Controller.OO.Exclusive_Unblock 46 0.00% 0.00% system.ruby.L2Cache_Controller.MI.Writeback_Ack 194 0.00% 0.00% -system.ruby.Directory_Controller.GETX 198 0.00% 0.00% -system.ruby.Directory_Controller.GETS 984 0.00% 0.00% -system.ruby.Directory_Controller.PUTX 194 0.00% 0.00% -system.ruby.Directory_Controller.Unblock 466 0.00% 0.00% -system.ruby.Directory_Controller.Last_Unblock 518 0.00% 0.00% -system.ruby.Directory_Controller.Exclusive_Unblock 198 0.00% 0.00% -system.ruby.Directory_Controller.Dirty_Writeback 194 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Data 1182 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Ack 194 0.00% 0.00% -system.ruby.Directory_Controller.I.GETX 111 0.00% 0.00% -system.ruby.Directory_Controller.I.GETS 466 0.00% 0.00% -system.ruby.Directory_Controller.I.Memory_Ack 194 0.00% 0.00% -system.ruby.Directory_Controller.S.GETX 87 0.00% 0.00% -system.ruby.Directory_Controller.S.GETS 518 0.00% 0.00% -system.ruby.Directory_Controller.M.PUTX 194 0.00% 0.00% -system.ruby.Directory_Controller.IS.Unblock 466 0.00% 0.00% -system.ruby.Directory_Controller.IS.Memory_Data 466 0.00% 0.00% -system.ruby.Directory_Controller.SS.Last_Unblock 518 0.00% 0.00% -system.ruby.Directory_Controller.SS.Memory_Data 518 0.00% 0.00% -system.ruby.Directory_Controller.MM.Exclusive_Unblock 198 0.00% 0.00% -system.ruby.Directory_Controller.MM.Memory_Data 198 0.00% 0.00% -system.ruby.Directory_Controller.MI.Dirty_Writeback 194 0.00% 0.00% ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt index abe542f63..23f7e060f 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000117 # Nu sim_ticks 116770 # Number of ticks simulated final_tick 116770 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 333 # Simulator instruction rate (inst/s) -host_op_rate 333 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 6085 # Simulator tick rate (ticks/s) -host_mem_usage 436992 # Number of bytes of host memory used -host_seconds 19.19 # Real time elapsed on the host +host_inst_rate 63656 # Simulator instruction rate (inst/s) +host_op_rate 63646 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1162909 # Simulator tick rate (ticks/s) +host_mem_usage 451252 # Number of bytes of host memory used +host_seconds 0.10 # Real time elapsed on the host sim_insts 6390 # Number of instructions simulated sim_ops 6390 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -236,29 +236,126 @@ system.mem_ctrls.readRowHitRate 79.80 # Ro system.mem_ctrls.writeRowHitRate 77.31 # Row buffer hit rate for writes system.mem_ctrls.avgGap 83.10 # Average gap between requests system.mem_ctrls.pageHitRate 79.54 # Row buffer hit rate, read and write combined -system.mem_ctrls.memoryStateTime::IDLE 22 # Time in different power states -system.mem_ctrls.memoryStateTime::REF 3640 # Time in different power states -system.mem_ctrls.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls.memoryStateTime::ACT 105625 # Time in different power states -system.mem_ctrls.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrls.actEnergy::0 514080 # Energy for activate commands per rank (pJ) -system.mem_ctrls.actEnergy::1 937440 # Energy for activate commands per rank (pJ) -system.mem_ctrls.preEnergy::0 285600 # Energy for precharge commands per rank (pJ) -system.mem_ctrls.preEnergy::1 520800 # Energy for precharge commands per rank (pJ) -system.mem_ctrls.readEnergy::0 5041920 # Energy for read commands per rank (pJ) -system.mem_ctrls.readEnergy::1 6764160 # Energy for read commands per rank (pJ) -system.mem_ctrls.writeEnergy::0 269568 # Energy for write commands per rank (pJ) -system.mem_ctrls.writeEnergy::1 725760 # Energy for write commands per rank (pJ) -system.mem_ctrls.refreshEnergy::0 7119840 # Energy for refresh commands per rank (pJ) -system.mem_ctrls.refreshEnergy::1 7119840 # Energy for refresh commands per rank (pJ) -system.mem_ctrls.actBackEnergy::0 60929352 # Energy for active background per rank (pJ) -system.mem_ctrls.actBackEnergy::1 72381564 # Energy for active background per rank (pJ) -system.mem_ctrls.preBackEnergy::0 12117000 # Energy for precharge background per rank (pJ) -system.mem_ctrls.preBackEnergy::1 2071200 # Energy for precharge background per rank (pJ) -system.mem_ctrls.totalEnergy::0 86277360 # Total energy per rank (pJ) -system.mem_ctrls.totalEnergy::1 90520764 # Total energy per rank (pJ) -system.mem_ctrls.averagePower::0 789.557896 # Core power per rank (mW) -system.mem_ctrls.averagePower::1 828.390947 # Core power per rank (mW) +system.mem_ctrls_0.actEnergy 514080 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 285600 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 5041920 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 269568 # Energy for write commands per rank (pJ) +system.mem_ctrls_0.refreshEnergy 7119840 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_0.actBackEnergy 60923196 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 12117000 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.totalEnergy 86271204 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 789.566591 # Core power per rank (mW) +system.mem_ctrls_0.memoryStateTime::IDLE 22175 # Time in different power states +system.mem_ctrls_0.memoryStateTime::REF 3640 # Time in different power states +system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 85821 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls_1.actEnergy 937440 # Energy for activate commands per rank (pJ) +system.mem_ctrls_1.preEnergy 520800 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_1.readEnergy 6764160 # Energy for read commands per rank (pJ) +system.mem_ctrls_1.writeEnergy 725760 # Energy for write commands per rank (pJ) +system.mem_ctrls_1.refreshEnergy 7119840 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_1.actBackEnergy 72391140 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 2062800 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.totalEnergy 90521940 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 828.401709 # Core power per rank (mW) +system.mem_ctrls_1.memoryStateTime::IDLE 2878 # Time in different power states +system.mem_ctrls_1.memoryStateTime::REF 3640 # Time in different power states +system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 102769 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.clk_domain.clock 1 # Clock period in ticks +system.cpu.dtb.fetch_hits 0 # ITB hits +system.cpu.dtb.fetch_misses 0 # ITB misses +system.cpu.dtb.fetch_acv 0 # ITB acv +system.cpu.dtb.fetch_accesses 0 # ITB accesses +system.cpu.dtb.read_hits 1183 # DTB read hits +system.cpu.dtb.read_misses 7 # DTB read misses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_accesses 1190 # DTB read accesses +system.cpu.dtb.write_hits 865 # DTB write hits +system.cpu.dtb.write_misses 3 # DTB write misses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_accesses 868 # DTB write accesses +system.cpu.dtb.data_hits 2048 # DTB hits +system.cpu.dtb.data_misses 10 # DTB misses +system.cpu.dtb.data_acv 0 # DTB access violations +system.cpu.dtb.data_accesses 2058 # DTB accesses +system.cpu.itb.fetch_hits 6401 # ITB hits +system.cpu.itb.fetch_misses 17 # ITB misses +system.cpu.itb.fetch_acv 0 # ITB acv +system.cpu.itb.fetch_accesses 6418 # ITB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_acv 0 # DTB read access violations +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_acv 0 # DTB write access violations +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.data_hits 0 # DTB hits +system.cpu.itb.data_misses 0 # DTB misses +system.cpu.itb.data_acv 0 # DTB access violations +system.cpu.itb.data_accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 17 # Number of system calls +system.cpu.numCycles 116770 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 6390 # Number of instructions committed +system.cpu.committedOps 6390 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 6317 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses +system.cpu.num_func_calls 251 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 749 # number of instructions that are conditional controls +system.cpu.num_int_insts 6317 # number of integer instructions +system.cpu.num_fp_insts 10 # number of float instructions +system.cpu.num_int_register_reads 8285 # number of times the integer registers were read +system.cpu.num_int_register_writes 4568 # number of times the integer registers were written +system.cpu.num_fp_register_reads 8 # number of times the floating registers were read +system.cpu.num_fp_register_writes 2 # number of times the floating registers were written +system.cpu.num_mem_refs 2058 # number of memory refs +system.cpu.num_load_insts 1190 # Number of load instructions +system.cpu.num_store_insts 868 # Number of store instructions +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 116770 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.Branches 1050 # Number of branches fetched +system.cpu.op_class::No_OpClass 19 0.30% 0.30% # Class of executed instruction +system.cpu.op_class::IntAlu 4320 67.50% 67.80% # Class of executed instruction +system.cpu.op_class::IntMult 1 0.02% 67.81% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 67.81% # Class of executed instruction +system.cpu.op_class::FloatAdd 2 0.03% 67.84% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.84% # Class of executed instruction +system.cpu.op_class::MemRead 1190 18.59% 86.44% # Class of executed instruction +system.cpu.op_class::MemWrite 868 13.56% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 6400 # Class of executed instruction system.ruby.clk_domain.clock 1 # Clock period in ticks system.ruby.outstanding_req_hist::bucket_size 1 system.ruby.outstanding_req_hist::max_bucket 9 @@ -271,8 +368,8 @@ system.ruby.latency_hist::bucket_size 64 system.ruby.latency_hist::max_bucket 639 system.ruby.latency_hist::samples 8448 system.ruby.latency_hist::mean 12.822206 -system.ruby.latency_hist::gmean 3.506831 -system.ruby.latency_hist::stdev 27.804874 +system.ruby.latency_hist::gmean 3.506830 +system.ruby.latency_hist::stdev 27.805292 system.ruby.latency_hist | 7433 87.99% 87.99% | 995 11.78% 99.76% | 6 0.07% 99.83% | 2 0.02% 99.86% | 8 0.09% 99.95% | 4 0.05% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.latency_hist::total 8448 system.ruby.hit_latency_hist::bucket_size 4 @@ -287,8 +384,8 @@ system.ruby.miss_latency_hist::bucket_size 64 system.ruby.miss_latency_hist::max_bucket 639 system.ruby.miss_latency_hist::samples 1176 system.ruby.miss_latency_hist::mean 75.774660 -system.ruby.miss_latency_hist::gmean 72.686076 -system.ruby.miss_latency_hist::stdev 29.372665 +system.ruby.miss_latency_hist::gmean 72.686009 +system.ruby.miss_latency_hist::stdev 29.375504 system.ruby.miss_latency_hist | 161 13.69% 13.69% | 995 84.61% 98.30% | 6 0.51% 98.81% | 2 0.17% 98.98% | 8 0.68% 99.66% | 4 0.34% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.miss_latency_hist::total 1176 system.ruby.Directory.incomplete_times 1175 @@ -298,7 +395,10 @@ system.ruby.l1_cntrl0.L1Dcache.demand_accesses 2048 system.ruby.l1_cntrl0.L1Icache.demand_hits 5754 # Number of cache demand hits system.ruby.l1_cntrl0.L1Icache.demand_misses 646 # Number of cache demand misses system.ruby.l1_cntrl0.L1Icache.demand_accesses 6400 # Number of cache demand accesses -system.cpu.clk_domain.clock 1 # Clock period in ticks +system.ruby.l2_cntrl0.L2cache.demand_hits 189 # Number of cache demand hits +system.ruby.l2_cntrl0.L2cache.demand_misses 1194 # Number of cache demand misses +system.ruby.l2_cntrl0.L2cache.demand_accesses 1383 # Number of cache demand accesses +system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks system.ruby.network.routers0.percent_links_utilized 5.578702 system.ruby.network.routers0.msg_count.Request_Control::1 1383 system.ruby.network.routers0.msg_count.Response_Data::4 1176 @@ -312,9 +412,6 @@ system.ruby.network.routers0.msg_bytes.ResponseL2hit_Data::4 14904 system.ruby.network.routers0.msg_bytes.Response_Control::4 8 system.ruby.network.routers0.msg_bytes.Writeback_Data::4 97488 system.ruby.network.routers0.msg_bytes.Persistent_Control::3 320 -system.ruby.l2_cntrl0.L2cache.demand_hits 189 # Number of cache demand hits -system.ruby.l2_cntrl0.L2cache.demand_misses 1194 # Number of cache demand misses -system.ruby.l2_cntrl0.L2cache.demand_accesses 1383 # Number of cache demand accesses system.ruby.network.routers1.percent_links_utilized 4.210200 system.ruby.network.routers1.msg_count.Request_Control::1 1383 system.ruby.network.routers1.msg_count.Request_Control::2 1194 @@ -372,98 +469,6 @@ system.ruby.network.msg_byte.Response_Control 24 system.ruby.network.msg_byte.Writeback_Data 341712 system.ruby.network.msg_byte.Writeback_Control 23184 system.ruby.network.msg_byte.Persistent_Control 960 -system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 1183 # DTB read hits -system.cpu.dtb.read_misses 7 # DTB read misses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 1190 # DTB read accesses -system.cpu.dtb.write_hits 865 # DTB write hits -system.cpu.dtb.write_misses 3 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 868 # DTB write accesses -system.cpu.dtb.data_hits 2048 # DTB hits -system.cpu.dtb.data_misses 10 # DTB misses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 2058 # DTB accesses -system.cpu.itb.fetch_hits 6401 # ITB hits -system.cpu.itb.fetch_misses 17 # ITB misses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 6418 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 116770 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 6390 # Number of instructions committed -system.cpu.committedOps 6390 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 6317 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses -system.cpu.num_func_calls 251 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 749 # number of instructions that are conditional controls -system.cpu.num_int_insts 6317 # number of integer instructions -system.cpu.num_fp_insts 10 # number of float instructions -system.cpu.num_int_register_reads 8285 # number of times the integer registers were read -system.cpu.num_int_register_writes 4568 # number of times the integer registers were written -system.cpu.num_fp_register_reads 8 # number of times the floating registers were read -system.cpu.num_fp_register_writes 2 # number of times the floating registers were written -system.cpu.num_mem_refs 2058 # number of memory refs -system.cpu.num_load_insts 1190 # Number of load instructions -system.cpu.num_store_insts 868 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 116770 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.Branches 1050 # Number of branches fetched -system.cpu.op_class::No_OpClass 19 0.30% 0.30% # Class of executed instruction -system.cpu.op_class::IntAlu 4320 67.50% 67.80% # Class of executed instruction -system.cpu.op_class::IntMult 1 0.02% 67.81% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 67.81% # Class of executed instruction -system.cpu.op_class::FloatAdd 2 0.03% 67.84% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::MemRead 1190 18.59% 86.44% # Class of executed instruction -system.cpu.op_class::MemWrite 868 13.56% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 6400 # Class of executed instruction system.ruby.network.routers0.throttle0.link_utilization 5.338700 system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1176 system.ruby.network.routers0.throttle0.msg_count.ResponseL2hit_Data::4 207 @@ -585,8 +590,8 @@ system.ruby.IFETCH.latency_hist::bucket_size 64 system.ruby.IFETCH.latency_hist::max_bucket 639 system.ruby.IFETCH.latency_hist::samples 6400 system.ruby.IFETCH.latency_hist::mean 9.334062 -system.ruby.IFETCH.latency_hist::gmean 2.862492 -system.ruby.IFETCH.latency_hist::stdev 24.015420 +system.ruby.IFETCH.latency_hist::gmean 2.862491 +system.ruby.IFETCH.latency_hist::stdev 24.016058 system.ruby.IFETCH.latency_hist | 5815 90.86% 90.86% | 573 8.95% 99.81% | 4 0.06% 99.87% | 0 0.00% 99.87% | 7 0.11% 99.98% | 1 0.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.latency_hist::total 6400 system.ruby.IFETCH.hit_latency_hist::bucket_size 4 @@ -601,8 +606,8 @@ system.ruby.IFETCH.miss_latency_hist::bucket_size 64 system.ruby.IFETCH.miss_latency_hist::max_bucket 639 system.ruby.IFETCH.miss_latency_hist::samples 585 system.ruby.IFETCH.miss_latency_hist::mean 79.849573 -system.ruby.IFETCH.miss_latency_hist::gmean 77.699187 -system.ruby.IFETCH.miss_latency_hist::stdev 27.986383 +system.ruby.IFETCH.miss_latency_hist::gmean 77.699044 +system.ruby.IFETCH.miss_latency_hist::stdev 27.992378 system.ruby.IFETCH.miss_latency_hist | 0 0.00% 0.00% | 573 97.95% 97.95% | 4 0.68% 98.63% | 0 0.00% 98.63% | 7 1.20% 99.83% | 1 0.17% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.miss_latency_hist::total 585 system.ruby.L1Cache.hit_mach_latency_hist::bucket_size 1 @@ -624,8 +629,8 @@ system.ruby.Directory.miss_mach_latency_hist::bucket_size 64 system.ruby.Directory.miss_mach_latency_hist::max_bucket 639 system.ruby.Directory.miss_mach_latency_hist::samples 1176 system.ruby.Directory.miss_mach_latency_hist::mean 75.774660 -system.ruby.Directory.miss_mach_latency_hist::gmean 72.686076 -system.ruby.Directory.miss_mach_latency_hist::stdev 29.372665 +system.ruby.Directory.miss_mach_latency_hist::gmean 72.686009 +system.ruby.Directory.miss_mach_latency_hist::stdev 29.375504 system.ruby.Directory.miss_mach_latency_hist | 161 13.69% 13.69% | 995 84.61% 98.30% | 6 0.51% 98.81% | 2 0.17% 98.98% | 8 0.68% 99.66% | 4 0.34% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.Directory.miss_mach_latency_hist::total 1176 system.ruby.Directory.miss_latency_hist.issue_to_initial_request::bucket_size 1 @@ -719,10 +724,37 @@ system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::bucket_size system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::max_bucket 639 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::samples 585 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean 79.849573 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 77.699187 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 27.986383 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 77.699044 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 27.992378 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 573 97.95% 97.95% | 4 0.68% 98.63% | 0 0.00% 98.63% | 7 1.20% 99.83% | 1 0.17% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total 585 +system.ruby.Directory_Controller.GETX 209 0.00% 0.00% +system.ruby.Directory_Controller.GETS 1013 0.00% 0.00% +system.ruby.Directory_Controller.Lockdown 10 0.00% 0.00% +system.ruby.Directory_Controller.Unlockdown 10 0.00% 0.00% +system.ruby.Directory_Controller.Data_Owner 9 0.00% 0.00% +system.ruby.Directory_Controller.Data_All_Tokens 219 0.00% 0.00% +system.ruby.Directory_Controller.Ack_Owner 29 0.00% 0.00% +system.ruby.Directory_Controller.Ack_Owner_All_Tokens 903 0.00% 0.00% +system.ruby.Directory_Controller.Ack_All_Tokens 34 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Data 1176 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Ack 228 0.00% 0.00% +system.ruby.Directory_Controller.O.GETX 168 0.00% 0.00% +system.ruby.Directory_Controller.O.GETS 1008 0.00% 0.00% +system.ruby.Directory_Controller.O.Ack_All_Tokens 34 0.00% 0.00% +system.ruby.Directory_Controller.NO.GETX 18 0.00% 0.00% +system.ruby.Directory_Controller.NO.Lockdown 1 0.00% 0.00% +system.ruby.Directory_Controller.NO.Data_Owner 9 0.00% 0.00% +system.ruby.Directory_Controller.NO.Data_All_Tokens 219 0.00% 0.00% +system.ruby.Directory_Controller.NO.Ack_Owner 29 0.00% 0.00% +system.ruby.Directory_Controller.NO.Ack_Owner_All_Tokens 903 0.00% 0.00% +system.ruby.Directory_Controller.L.Unlockdown 10 0.00% 0.00% +system.ruby.Directory_Controller.O_W.GETX 23 0.00% 0.00% +system.ruby.Directory_Controller.O_W.GETS 5 0.00% 0.00% +system.ruby.Directory_Controller.O_W.Memory_Ack 228 0.00% 0.00% +system.ruby.Directory_Controller.L_NO_W.Memory_Data 9 0.00% 0.00% +system.ruby.Directory_Controller.NO_W.Lockdown 9 0.00% 0.00% +system.ruby.Directory_Controller.NO_W.Memory_Data 1167 0.00% 0.00% system.ruby.L1Cache_Controller.Load 1183 0.00% 0.00% system.ruby.L1Cache_Controller.Ifetch 6400 0.00% 0.00% system.ruby.L1Cache_Controller.Store 865 0.00% 0.00% @@ -796,32 +828,5 @@ system.ruby.L2Cache_Controller.M.L1_GETX 26 0.00% 0.00% system.ruby.L2Cache_Controller.M.L2_Replacement 1122 0.00% 0.00% system.ruby.L2Cache_Controller.I_L.Persistent_GETX 1 0.00% 0.00% system.ruby.L2Cache_Controller.I_L.Persistent_GETS 9 0.00% 0.00% -system.ruby.Directory_Controller.GETX 209 0.00% 0.00% -system.ruby.Directory_Controller.GETS 1013 0.00% 0.00% -system.ruby.Directory_Controller.Lockdown 10 0.00% 0.00% -system.ruby.Directory_Controller.Unlockdown 10 0.00% 0.00% -system.ruby.Directory_Controller.Data_Owner 9 0.00% 0.00% -system.ruby.Directory_Controller.Data_All_Tokens 219 0.00% 0.00% -system.ruby.Directory_Controller.Ack_Owner 29 0.00% 0.00% -system.ruby.Directory_Controller.Ack_Owner_All_Tokens 903 0.00% 0.00% -system.ruby.Directory_Controller.Ack_All_Tokens 34 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Data 1176 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Ack 228 0.00% 0.00% -system.ruby.Directory_Controller.O.GETX 168 0.00% 0.00% -system.ruby.Directory_Controller.O.GETS 1008 0.00% 0.00% -system.ruby.Directory_Controller.O.Ack_All_Tokens 34 0.00% 0.00% -system.ruby.Directory_Controller.NO.GETX 18 0.00% 0.00% -system.ruby.Directory_Controller.NO.Lockdown 1 0.00% 0.00% -system.ruby.Directory_Controller.NO.Data_Owner 9 0.00% 0.00% -system.ruby.Directory_Controller.NO.Data_All_Tokens 219 0.00% 0.00% -system.ruby.Directory_Controller.NO.Ack_Owner 29 0.00% 0.00% -system.ruby.Directory_Controller.NO.Ack_Owner_All_Tokens 903 0.00% 0.00% -system.ruby.Directory_Controller.L.Unlockdown 10 0.00% 0.00% -system.ruby.Directory_Controller.O_W.GETX 23 0.00% 0.00% -system.ruby.Directory_Controller.O_W.GETS 5 0.00% 0.00% -system.ruby.Directory_Controller.O_W.Memory_Ack 228 0.00% 0.00% -system.ruby.Directory_Controller.L_NO_W.Memory_Data 9 0.00% 0.00% -system.ruby.Directory_Controller.NO_W.Lockdown 9 0.00% 0.00% -system.ruby.Directory_Controller.NO_W.Memory_Data 1167 0.00% 0.00% ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt index 72fcefa3c..4d5f2d93a 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000096 # Nu sim_ticks 96381 # Number of ticks simulated final_tick 96381 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 32379 # Simulator instruction rate (inst/s) -host_op_rate 32376 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 488288 # Simulator tick rate (ticks/s) -host_mem_usage 436896 # Number of bytes of host memory used -host_seconds 0.20 # Real time elapsed on the host +host_inst_rate 66831 # Simulator instruction rate (inst/s) +host_op_rate 66821 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1007748 # Simulator tick rate (ticks/s) +host_mem_usage 449612 # Number of bytes of host memory used +host_seconds 0.10 # Real time elapsed on the host sim_insts 6390 # Number of instructions simulated sim_ops 6390 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -186,12 +186,12 @@ system.mem_ctrls.wrQLenPdf::62 0 # Wh system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see system.mem_ctrls.bytesPerActivate::samples 194 # Bytes accessed per row activation system.mem_ctrls.bytesPerActivate::mean 352.659794 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::gmean 218.108055 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::stdev 333.620332 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::0-127 54 27.84% 27.84% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::128-255 51 26.29% 54.12% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::256-383 19 9.79% 63.92% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::384-511 16 8.25% 72.16% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 217.534506 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 333.874690 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 55 28.35% 28.35% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 50 25.77% 54.12% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 18 9.28% 63.40% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 17 8.76% 72.16% # Bytes accessed per row activation system.mem_ctrls.bytesPerActivate::512-639 12 6.19% 78.35% # Bytes accessed per row activation system.mem_ctrls.bytesPerActivate::640-767 7 3.61% 81.96% # Bytes accessed per row activation system.mem_ctrls.bytesPerActivate::768-895 7 3.61% 85.57% # Bytes accessed per row activation @@ -231,138 +231,42 @@ system.mem_ctrls.busUtil 5.65 # Da system.mem_ctrls.busUtilRead 5.20 # Data bus utilization in percentage for reads system.mem_ctrls.busUtilWrite 0.45 # Data bus utilization in percentage for writes system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing -system.mem_ctrls.avgWrQLen 21.25 # Average write queue length when enqueuing +system.mem_ctrls.avgWrQLen 21.24 # Average write queue length when enqueuing system.mem_ctrls.readRowHits 808 # Number of row buffer hits during reads system.mem_ctrls.writeRowHits 82 # Number of row buffer hits during writes system.mem_ctrls.readRowHitRate 80.56 # Row buffer hit rate for reads system.mem_ctrls.writeRowHitRate 70.69 # Row buffer hit rate for writes system.mem_ctrls.avgGap 69.83 # Average gap between requests system.mem_ctrls.pageHitRate 79.54 # Row buffer hit rate, read and write combined -system.mem_ctrls.memoryStateTime::IDLE 11 # Time in different power states -system.mem_ctrls.memoryStateTime::REF 3120 # Time in different power states -system.mem_ctrls.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls.memoryStateTime::ACT 90575 # Time in different power states -system.mem_ctrls.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrls.actEnergy::0 476280 # Energy for activate commands per rank (pJ) -system.mem_ctrls.actEnergy::1 975240 # Energy for activate commands per rank (pJ) -system.mem_ctrls.preEnergy::0 264600 # Energy for precharge commands per rank (pJ) -system.mem_ctrls.preEnergy::1 541800 # Energy for precharge commands per rank (pJ) -system.mem_ctrls.readEnergy::0 5104320 # Energy for read commands per rank (pJ) -system.mem_ctrls.readEnergy::1 7063680 # Energy for read commands per rank (pJ) -system.mem_ctrls.writeEnergy::0 238464 # Energy for write commands per rank (pJ) -system.mem_ctrls.writeEnergy::1 663552 # Energy for write commands per rank (pJ) -system.mem_ctrls.refreshEnergy::0 6102720 # Energy for refresh commands per rank (pJ) -system.mem_ctrls.refreshEnergy::1 6102720 # Energy for refresh commands per rank (pJ) -system.mem_ctrls.actBackEnergy::0 54836964 # Energy for active background per rank (pJ) -system.mem_ctrls.actBackEnergy::1 61829496 # Energy for active background per rank (pJ) -system.mem_ctrls.preBackEnergy::0 8112600 # Energy for precharge background per rank (pJ) -system.mem_ctrls.preBackEnergy::1 1978800 # Energy for precharge background per rank (pJ) -system.mem_ctrls.totalEnergy::0 75135948 # Total energy per rank (pJ) -system.mem_ctrls.totalEnergy::1 79155288 # Total energy per rank (pJ) -system.mem_ctrls.averagePower::0 801.946249 # Core power per rank (mW) -system.mem_ctrls.averagePower::1 844.845750 # Core power per rank (mW) -system.ruby.clk_domain.clock 1 # Clock period in ticks -system.ruby.outstanding_req_hist::bucket_size 1 -system.ruby.outstanding_req_hist::max_bucket 9 -system.ruby.outstanding_req_hist::samples 8449 -system.ruby.outstanding_req_hist::mean 1 -system.ruby.outstanding_req_hist::gmean 1 -system.ruby.outstanding_req_hist | 0 0.00% 0.00% | 8449 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.outstanding_req_hist::total 8449 -system.ruby.latency_hist::bucket_size 64 -system.ruby.latency_hist::max_bucket 639 -system.ruby.latency_hist::samples 8448 -system.ruby.latency_hist::mean 10.408736 -system.ruby.latency_hist::gmean 3.320045 -system.ruby.latency_hist::stdev 22.997500 -system.ruby.latency_hist | 8209 97.17% 97.17% | 227 2.69% 99.86% | 0 0.00% 99.86% | 1 0.01% 99.87% | 6 0.07% 99.94% | 5 0.06% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.latency_hist::total 8448 -system.ruby.hit_latency_hist::bucket_size 2 -system.ruby.hit_latency_hist::max_bucket 19 -system.ruby.hit_latency_hist::samples 7289 -system.ruby.hit_latency_hist::mean 2.306352 -system.ruby.hit_latency_hist::gmean 2.107025 -system.ruby.hit_latency_hist::stdev 1.810102 -system.ruby.hit_latency_hist | 0 0.00% 0.00% | 7086 97.21% 97.21% | 0 0.00% 97.21% | 0 0.00% 97.21% | 0 0.00% 97.21% | 0 0.00% 97.21% | 203 2.79% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.hit_latency_hist::total 7289 -system.ruby.miss_latency_hist::bucket_size 64 -system.ruby.miss_latency_hist::max_bucket 639 -system.ruby.miss_latency_hist::samples 1159 -system.ruby.miss_latency_hist::mean 61.364970 -system.ruby.miss_latency_hist::gmean 57.951867 -system.ruby.miss_latency_hist::stdev 28.728264 -system.ruby.miss_latency_hist | 920 79.38% 79.38% | 227 19.59% 98.96% | 0 0.00% 98.96% | 1 0.09% 99.05% | 6 0.52% 99.57% | 5 0.43% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.miss_latency_hist::total 1159 -system.ruby.Directory.incomplete_times 1158 -system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.ruby.l1_cntrl0.L1Dcache.demand_hits 1332 # Number of cache demand hits -system.ruby.l1_cntrl0.L1Dcache.demand_misses 716 # Number of cache demand misses -system.ruby.l1_cntrl0.L1Dcache.demand_accesses 2048 # Number of cache demand accesses -system.ruby.l1_cntrl0.L1Icache.demand_hits 5754 # Number of cache demand hits -system.ruby.l1_cntrl0.L1Icache.demand_misses 646 # Number of cache demand misses -system.ruby.l1_cntrl0.L1Icache.demand_accesses 6400 # Number of cache demand accesses -system.ruby.l1_cntrl0.L2cache.demand_hits 203 # Number of cache demand hits -system.ruby.l1_cntrl0.L2cache.demand_misses 1159 # Number of cache demand misses -system.ruby.l1_cntrl0.L2cache.demand_accesses 1362 # Number of cache demand accesses +system.mem_ctrls_0.actEnergy 476280 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 264600 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 5104320 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 238464 # Energy for write commands per rank (pJ) +system.mem_ctrls_0.refreshEnergy 6102720 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_0.actBackEnergy 54887580 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 8068200 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.totalEnergy 75142164 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 802.012594 # Core power per rank (mW) +system.mem_ctrls_0.memoryStateTime::IDLE 14237 # Time in different power states +system.mem_ctrls_0.memoryStateTime::REF 3120 # Time in different power states +system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 77447 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls_1.actEnergy 975240 # Energy for activate commands per rank (pJ) +system.mem_ctrls_1.preEnergy 541800 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_1.readEnergy 7063680 # Energy for read commands per rank (pJ) +system.mem_ctrls_1.writeEnergy 663552 # Energy for write commands per rank (pJ) +system.mem_ctrls_1.refreshEnergy 6102720 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_1.actBackEnergy 61908840 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 1909200 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.totalEnergy 79165032 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 844.949750 # Core power per rank (mW) +system.mem_ctrls_1.memoryStateTime::IDLE 2762 # Time in different power states +system.mem_ctrls_1.memoryStateTime::REF 3120 # Time in different power states +system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 87824 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.clk_domain.clock 1 # Clock period in ticks -system.ruby.network.routers0.percent_links_utilized 4.652888 -system.ruby.network.routers0.msg_count.Request_Control::2 1159 -system.ruby.network.routers0.msg_count.Response_Data::4 1159 -system.ruby.network.routers0.msg_count.Writeback_Data::5 220 -system.ruby.network.routers0.msg_count.Writeback_Control::2 1143 -system.ruby.network.routers0.msg_count.Writeback_Control::3 1143 -system.ruby.network.routers0.msg_count.Writeback_Control::5 923 -system.ruby.network.routers0.msg_count.Unblock_Control::5 1159 -system.ruby.network.routers0.msg_bytes.Request_Control::2 9272 -system.ruby.network.routers0.msg_bytes.Response_Data::4 83448 -system.ruby.network.routers0.msg_bytes.Writeback_Data::5 15840 -system.ruby.network.routers0.msg_bytes.Writeback_Control::2 9144 -system.ruby.network.routers0.msg_bytes.Writeback_Control::3 9144 -system.ruby.network.routers0.msg_bytes.Writeback_Control::5 7384 -system.ruby.network.routers0.msg_bytes.Unblock_Control::5 9272 -system.ruby.dir_cntrl0.probeFilter.demand_hits 0 # Number of cache demand hits -system.ruby.dir_cntrl0.probeFilter.demand_misses 0 # Number of cache demand misses -system.ruby.dir_cntrl0.probeFilter.demand_accesses 0 # Number of cache demand accesses -system.ruby.network.routers1.percent_links_utilized 4.652888 -system.ruby.network.routers1.msg_count.Request_Control::2 1159 -system.ruby.network.routers1.msg_count.Response_Data::4 1159 -system.ruby.network.routers1.msg_count.Writeback_Data::5 220 -system.ruby.network.routers1.msg_count.Writeback_Control::2 1143 -system.ruby.network.routers1.msg_count.Writeback_Control::3 1143 -system.ruby.network.routers1.msg_count.Writeback_Control::5 923 -system.ruby.network.routers1.msg_count.Unblock_Control::5 1159 -system.ruby.network.routers1.msg_bytes.Request_Control::2 9272 -system.ruby.network.routers1.msg_bytes.Response_Data::4 83448 -system.ruby.network.routers1.msg_bytes.Writeback_Data::5 15840 -system.ruby.network.routers1.msg_bytes.Writeback_Control::2 9144 -system.ruby.network.routers1.msg_bytes.Writeback_Control::3 9144 -system.ruby.network.routers1.msg_bytes.Writeback_Control::5 7384 -system.ruby.network.routers1.msg_bytes.Unblock_Control::5 9272 -system.ruby.network.routers2.percent_links_utilized 4.652888 -system.ruby.network.routers2.msg_count.Request_Control::2 1159 -system.ruby.network.routers2.msg_count.Response_Data::4 1159 -system.ruby.network.routers2.msg_count.Writeback_Data::5 220 -system.ruby.network.routers2.msg_count.Writeback_Control::2 1143 -system.ruby.network.routers2.msg_count.Writeback_Control::3 1143 -system.ruby.network.routers2.msg_count.Writeback_Control::5 923 -system.ruby.network.routers2.msg_count.Unblock_Control::5 1159 -system.ruby.network.routers2.msg_bytes.Request_Control::2 9272 -system.ruby.network.routers2.msg_bytes.Response_Data::4 83448 -system.ruby.network.routers2.msg_bytes.Writeback_Data::5 15840 -system.ruby.network.routers2.msg_bytes.Writeback_Control::2 9144 -system.ruby.network.routers2.msg_bytes.Writeback_Control::3 9144 -system.ruby.network.routers2.msg_bytes.Writeback_Control::5 7384 -system.ruby.network.routers2.msg_bytes.Unblock_Control::5 9272 -system.ruby.network.msg_count.Request_Control 3477 -system.ruby.network.msg_count.Response_Data 3477 -system.ruby.network.msg_count.Writeback_Data 660 -system.ruby.network.msg_count.Writeback_Control 9627 -system.ruby.network.msg_count.Unblock_Control 3477 -system.ruby.network.msg_byte.Request_Control 27816 -system.ruby.network.msg_byte.Response_Data 250344 -system.ruby.network.msg_byte.Writeback_Data 47520 -system.ruby.network.msg_byte.Writeback_Control 77016 -system.ruby.network.msg_byte.Unblock_Control 27816 system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -454,6 +358,107 @@ system.cpu.op_class::MemWrite 868 13.56% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 6400 # Class of executed instruction +system.ruby.clk_domain.clock 1 # Clock period in ticks +system.ruby.outstanding_req_hist::bucket_size 1 +system.ruby.outstanding_req_hist::max_bucket 9 +system.ruby.outstanding_req_hist::samples 8449 +system.ruby.outstanding_req_hist::mean 1 +system.ruby.outstanding_req_hist::gmean 1 +system.ruby.outstanding_req_hist | 0 0.00% 0.00% | 8449 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.outstanding_req_hist::total 8449 +system.ruby.latency_hist::bucket_size 64 +system.ruby.latency_hist::max_bucket 639 +system.ruby.latency_hist::samples 8448 +system.ruby.latency_hist::mean 10.408736 +system.ruby.latency_hist::gmean 3.320047 +system.ruby.latency_hist::stdev 22.995606 +system.ruby.latency_hist | 8209 97.17% 97.17% | 227 2.69% 99.86% | 0 0.00% 99.86% | 0 0.00% 99.86% | 7 0.08% 99.94% | 5 0.06% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.latency_hist::total 8448 +system.ruby.hit_latency_hist::bucket_size 2 +system.ruby.hit_latency_hist::max_bucket 19 +system.ruby.hit_latency_hist::samples 7289 +system.ruby.hit_latency_hist::mean 2.306352 +system.ruby.hit_latency_hist::gmean 2.107025 +system.ruby.hit_latency_hist::stdev 1.810102 +system.ruby.hit_latency_hist | 0 0.00% 0.00% | 7086 97.21% 97.21% | 0 0.00% 97.21% | 0 0.00% 97.21% | 0 0.00% 97.21% | 0 0.00% 97.21% | 203 2.79% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.hit_latency_hist::total 7289 +system.ruby.miss_latency_hist::bucket_size 64 +system.ruby.miss_latency_hist::max_bucket 639 +system.ruby.miss_latency_hist::samples 1159 +system.ruby.miss_latency_hist::mean 61.364970 +system.ruby.miss_latency_hist::gmean 57.952099 +system.ruby.miss_latency_hist::stdev 28.717200 +system.ruby.miss_latency_hist | 920 79.38% 79.38% | 227 19.59% 98.96% | 0 0.00% 98.96% | 0 0.00% 98.96% | 7 0.60% 99.57% | 5 0.43% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.miss_latency_hist::total 1159 +system.ruby.Directory.incomplete_times 1158 +system.ruby.dir_cntrl0.probeFilter.demand_hits 0 # Number of cache demand hits +system.ruby.dir_cntrl0.probeFilter.demand_misses 0 # Number of cache demand misses +system.ruby.dir_cntrl0.probeFilter.demand_accesses 0 # Number of cache demand accesses +system.ruby.l1_cntrl0.L1Dcache.demand_hits 1332 # Number of cache demand hits +system.ruby.l1_cntrl0.L1Dcache.demand_misses 716 # Number of cache demand misses +system.ruby.l1_cntrl0.L1Dcache.demand_accesses 2048 # Number of cache demand accesses +system.ruby.l1_cntrl0.L1Icache.demand_hits 5754 # Number of cache demand hits +system.ruby.l1_cntrl0.L1Icache.demand_misses 646 # Number of cache demand misses +system.ruby.l1_cntrl0.L1Icache.demand_accesses 6400 # Number of cache demand accesses +system.ruby.l1_cntrl0.L2cache.demand_hits 203 # Number of cache demand hits +system.ruby.l1_cntrl0.L2cache.demand_misses 1159 # Number of cache demand misses +system.ruby.l1_cntrl0.L2cache.demand_accesses 1362 # Number of cache demand accesses +system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks +system.ruby.network.routers0.percent_links_utilized 4.652888 +system.ruby.network.routers0.msg_count.Request_Control::2 1159 +system.ruby.network.routers0.msg_count.Response_Data::4 1159 +system.ruby.network.routers0.msg_count.Writeback_Data::5 220 +system.ruby.network.routers0.msg_count.Writeback_Control::2 1143 +system.ruby.network.routers0.msg_count.Writeback_Control::3 1143 +system.ruby.network.routers0.msg_count.Writeback_Control::5 923 +system.ruby.network.routers0.msg_count.Unblock_Control::5 1159 +system.ruby.network.routers0.msg_bytes.Request_Control::2 9272 +system.ruby.network.routers0.msg_bytes.Response_Data::4 83448 +system.ruby.network.routers0.msg_bytes.Writeback_Data::5 15840 +system.ruby.network.routers0.msg_bytes.Writeback_Control::2 9144 +system.ruby.network.routers0.msg_bytes.Writeback_Control::3 9144 +system.ruby.network.routers0.msg_bytes.Writeback_Control::5 7384 +system.ruby.network.routers0.msg_bytes.Unblock_Control::5 9272 +system.ruby.network.routers1.percent_links_utilized 4.652888 +system.ruby.network.routers1.msg_count.Request_Control::2 1159 +system.ruby.network.routers1.msg_count.Response_Data::4 1159 +system.ruby.network.routers1.msg_count.Writeback_Data::5 220 +system.ruby.network.routers1.msg_count.Writeback_Control::2 1143 +system.ruby.network.routers1.msg_count.Writeback_Control::3 1143 +system.ruby.network.routers1.msg_count.Writeback_Control::5 923 +system.ruby.network.routers1.msg_count.Unblock_Control::5 1159 +system.ruby.network.routers1.msg_bytes.Request_Control::2 9272 +system.ruby.network.routers1.msg_bytes.Response_Data::4 83448 +system.ruby.network.routers1.msg_bytes.Writeback_Data::5 15840 +system.ruby.network.routers1.msg_bytes.Writeback_Control::2 9144 +system.ruby.network.routers1.msg_bytes.Writeback_Control::3 9144 +system.ruby.network.routers1.msg_bytes.Writeback_Control::5 7384 +system.ruby.network.routers1.msg_bytes.Unblock_Control::5 9272 +system.ruby.network.routers2.percent_links_utilized 4.652888 +system.ruby.network.routers2.msg_count.Request_Control::2 1159 +system.ruby.network.routers2.msg_count.Response_Data::4 1159 +system.ruby.network.routers2.msg_count.Writeback_Data::5 220 +system.ruby.network.routers2.msg_count.Writeback_Control::2 1143 +system.ruby.network.routers2.msg_count.Writeback_Control::3 1143 +system.ruby.network.routers2.msg_count.Writeback_Control::5 923 +system.ruby.network.routers2.msg_count.Unblock_Control::5 1159 +system.ruby.network.routers2.msg_bytes.Request_Control::2 9272 +system.ruby.network.routers2.msg_bytes.Response_Data::4 83448 +system.ruby.network.routers2.msg_bytes.Writeback_Data::5 15840 +system.ruby.network.routers2.msg_bytes.Writeback_Control::2 9144 +system.ruby.network.routers2.msg_bytes.Writeback_Control::3 9144 +system.ruby.network.routers2.msg_bytes.Writeback_Control::5 7384 +system.ruby.network.routers2.msg_bytes.Unblock_Control::5 9272 +system.ruby.network.msg_count.Request_Control 3477 +system.ruby.network.msg_count.Response_Data 3477 +system.ruby.network.msg_count.Writeback_Data 660 +system.ruby.network.msg_count.Writeback_Control 9627 +system.ruby.network.msg_count.Unblock_Control 3477 +system.ruby.network.msg_byte.Request_Control 27816 +system.ruby.network.msg_byte.Response_Data 250344 +system.ruby.network.msg_byte.Writeback_Data 47520 +system.ruby.network.msg_byte.Writeback_Control 77016 +system.ruby.network.msg_byte.Unblock_Control 27816 system.ruby.network.routers0.throttle0.link_utilization 6.004295 system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1159 system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 1143 @@ -554,9 +559,9 @@ system.ruby.IFETCH.latency_hist::bucket_size 64 system.ruby.IFETCH.latency_hist::max_bucket 639 system.ruby.IFETCH.latency_hist::samples 6400 system.ruby.IFETCH.latency_hist::mean 7.937812 -system.ruby.IFETCH.latency_hist::gmean 2.788276 -system.ruby.IFETCH.latency_hist::stdev 21.096217 -system.ruby.IFETCH.latency_hist | 6291 98.30% 98.30% | 99 1.55% 99.84% | 0 0.00% 99.84% | 1 0.02% 99.86% | 4 0.06% 99.92% | 5 0.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.latency_hist::gmean 2.788278 +system.ruby.IFETCH.latency_hist::stdev 21.093490 +system.ruby.IFETCH.latency_hist | 6291 98.30% 98.30% | 99 1.55% 99.84% | 0 0.00% 99.84% | 0 0.00% 99.84% | 5 0.08% 99.92% | 5 0.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.latency_hist::total 6400 system.ruby.IFETCH.hit_latency_hist::bucket_size 2 system.ruby.IFETCH.hit_latency_hist::max_bucket 19 @@ -570,9 +575,9 @@ system.ruby.IFETCH.miss_latency_hist::bucket_size 64 system.ruby.IFETCH.miss_latency_hist::max_bucket 639 system.ruby.IFETCH.miss_latency_hist::samples 581 system.ruby.IFETCH.miss_latency_hist::mean 66.177281 -system.ruby.IFETCH.miss_latency_hist::gmean 63.049831 -system.ruby.IFETCH.miss_latency_hist::stdev 34.055805 -system.ruby.IFETCH.miss_latency_hist | 472 81.24% 81.24% | 99 17.04% 98.28% | 0 0.00% 98.28% | 1 0.17% 98.45% | 4 0.69% 99.14% | 5 0.86% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.miss_latency_hist::gmean 63.050334 +system.ruby.IFETCH.miss_latency_hist::stdev 34.037169 +system.ruby.IFETCH.miss_latency_hist | 472 81.24% 81.24% | 99 17.04% 98.28% | 0 0.00% 98.28% | 0 0.00% 98.28% | 5 0.86% 99.14% | 5 0.86% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.miss_latency_hist::total 581 system.ruby.L1Cache.hit_mach_latency_hist::bucket_size 1 system.ruby.L1Cache.hit_mach_latency_hist::max_bucket 9 @@ -592,9 +597,9 @@ system.ruby.Directory.miss_mach_latency_hist::bucket_size 64 system.ruby.Directory.miss_mach_latency_hist::max_bucket 639 system.ruby.Directory.miss_mach_latency_hist::samples 1159 system.ruby.Directory.miss_mach_latency_hist::mean 61.364970 -system.ruby.Directory.miss_mach_latency_hist::gmean 57.951867 -system.ruby.Directory.miss_mach_latency_hist::stdev 28.728264 -system.ruby.Directory.miss_mach_latency_hist | 920 79.38% 79.38% | 227 19.59% 98.96% | 0 0.00% 98.96% | 1 0.09% 99.05% | 6 0.52% 99.57% | 5 0.43% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_mach_latency_hist::gmean 57.952099 +system.ruby.Directory.miss_mach_latency_hist::stdev 28.717200 +system.ruby.Directory.miss_mach_latency_hist | 920 79.38% 79.38% | 227 19.59% 98.96% | 0 0.00% 98.96% | 0 0.00% 98.96% | 7 0.60% 99.57% | 5 0.43% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.Directory.miss_mach_latency_hist::total 1159 system.ruby.Directory.miss_latency_hist.issue_to_initial_request::bucket_size 1 system.ruby.Directory.miss_latency_hist.issue_to_initial_request::max_bucket 9 @@ -684,10 +689,28 @@ system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::bucket_size system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::max_bucket 639 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::samples 581 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean 66.177281 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 63.049831 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 34.055805 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 472 81.24% 81.24% | 99 17.04% 98.28% | 0 0.00% 98.28% | 1 0.17% 98.45% | 4 0.69% 99.14% | 5 0.86% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 63.050334 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 34.037169 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 472 81.24% 81.24% | 99 17.04% 98.28% | 0 0.00% 98.28% | 0 0.00% 98.28% | 5 0.86% 99.14% | 5 0.86% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total 581 +system.ruby.Directory_Controller.GETX 185 0.00% 0.00% +system.ruby.Directory_Controller.GETS 1020 0.00% 0.00% +system.ruby.Directory_Controller.PUT 1143 0.00% 0.00% +system.ruby.Directory_Controller.UnblockM 1159 0.00% 0.00% +system.ruby.Directory_Controller.Writeback_Exclusive_Clean 923 0.00% 0.00% +system.ruby.Directory_Controller.Writeback_Exclusive_Dirty 220 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Data 1159 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Ack 220 0.00% 0.00% +system.ruby.Directory_Controller.NO.PUT 1143 0.00% 0.00% +system.ruby.Directory_Controller.E.GETX 158 0.00% 0.00% +system.ruby.Directory_Controller.E.GETS 1001 0.00% 0.00% +system.ruby.Directory_Controller.NO_B.UnblockM 1159 0.00% 0.00% +system.ruby.Directory_Controller.NO_B_W.Memory_Data 1159 0.00% 0.00% +system.ruby.Directory_Controller.WB.GETX 27 0.00% 0.00% +system.ruby.Directory_Controller.WB.GETS 19 0.00% 0.00% +system.ruby.Directory_Controller.WB.Writeback_Exclusive_Clean 923 0.00% 0.00% +system.ruby.Directory_Controller.WB.Writeback_Exclusive_Dirty 220 0.00% 0.00% +system.ruby.Directory_Controller.WB_E_W.Memory_Ack 220 0.00% 0.00% system.ruby.L1Cache_Controller.Load 1191 0.00% 0.00% system.ruby.L1Cache_Controller.Ifetch 6411 0.00% 0.00% system.ruby.L1Cache_Controller.Store 892 0.00% 0.00% @@ -729,23 +752,5 @@ system.ruby.L1Cache_Controller.MI.Store 27 0.00% 0.00% system.ruby.L1Cache_Controller.MI.Writeback_Ack 1143 0.00% 0.00% system.ruby.L1Cache_Controller.MT.Complete_L2_to_L1 133 0.00% 0.00% system.ruby.L1Cache_Controller.MMT.Complete_L2_to_L1 70 0.00% 0.00% -system.ruby.Directory_Controller.GETX 185 0.00% 0.00% -system.ruby.Directory_Controller.GETS 1020 0.00% 0.00% -system.ruby.Directory_Controller.PUT 1143 0.00% 0.00% -system.ruby.Directory_Controller.UnblockM 1159 0.00% 0.00% -system.ruby.Directory_Controller.Writeback_Exclusive_Clean 923 0.00% 0.00% -system.ruby.Directory_Controller.Writeback_Exclusive_Dirty 220 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Data 1159 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Ack 220 0.00% 0.00% -system.ruby.Directory_Controller.NO.PUT 1143 0.00% 0.00% -system.ruby.Directory_Controller.E.GETX 158 0.00% 0.00% -system.ruby.Directory_Controller.E.GETS 1001 0.00% 0.00% -system.ruby.Directory_Controller.NO_B.UnblockM 1159 0.00% 0.00% -system.ruby.Directory_Controller.NO_B_W.Memory_Data 1159 0.00% 0.00% -system.ruby.Directory_Controller.WB.GETX 27 0.00% 0.00% -system.ruby.Directory_Controller.WB.GETS 19 0.00% 0.00% -system.ruby.Directory_Controller.WB.Writeback_Exclusive_Clean 923 0.00% 0.00% -system.ruby.Directory_Controller.WB.Writeback_Exclusive_Dirty 220 0.00% 0.00% -system.ruby.Directory_Controller.WB_E_W.Memory_Ack 220 0.00% 0.00% ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt index 01d67d280..e18c35fff 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000124 # Nu sim_ticks 123564 # Number of ticks simulated final_tick 123564 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 34581 # Simulator instruction rate (inst/s) -host_op_rate 34578 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 668563 # Simulator tick rate (ticks/s) -host_mem_usage 436724 # Number of bytes of host memory used -host_seconds 0.19 # Real time elapsed on the host +host_inst_rate 69668 # Simulator instruction rate (inst/s) +host_op_rate 69633 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1346306 # Simulator tick rate (ticks/s) +host_mem_usage 450680 # Number of bytes of host memory used +host_seconds 0.09 # Real time elapsed on the host sim_insts 6390 # Number of instructions simulated sim_ops 6390 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -238,106 +238,35 @@ system.mem_ctrls.readRowHitRate 75.06 # Ro system.mem_ctrls.writeRowHitRate 92.52 # Row buffer hit rate for writes system.mem_ctrls.avgGap 35.73 # Average gap between requests system.mem_ctrls.pageHitRate 83.97 # Row buffer hit rate, read and write combined -system.mem_ctrls.memoryStateTime::IDLE 11701 # Time in different power states -system.mem_ctrls.memoryStateTime::REF 3900 # Time in different power states -system.mem_ctrls.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls.memoryStateTime::ACT 101465 # Time in different power states -system.mem_ctrls.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrls.actEnergy::0 771120 # Energy for activate commands per rank (pJ) -system.mem_ctrls.actEnergy::1 1081080 # Energy for activate commands per rank (pJ) -system.mem_ctrls.preEnergy::0 428400 # Energy for precharge commands per rank (pJ) -system.mem_ctrls.preEnergy::1 600600 # Energy for precharge commands per rank (pJ) -system.mem_ctrls.readEnergy::0 4879680 # Energy for read commands per rank (pJ) -system.mem_ctrls.readEnergy::1 5466240 # Energy for read commands per rank (pJ) -system.mem_ctrls.writeEnergy::0 4281984 # Energy for write commands per rank (pJ) -system.mem_ctrls.writeEnergy::1 4323456 # Energy for write commands per rank (pJ) -system.mem_ctrls.refreshEnergy::0 7628400 # Energy for refresh commands per rank (pJ) -system.mem_ctrls.refreshEnergy::1 7628400 # Energy for refresh commands per rank (pJ) -system.mem_ctrls.actBackEnergy::0 69482088 # Energy for active background per rank (pJ) -system.mem_ctrls.actBackEnergy::1 69027912 # Energy for active background per rank (pJ) -system.mem_ctrls.preBackEnergy::0 9282000 # Energy for precharge background per rank (pJ) -system.mem_ctrls.preBackEnergy::1 9680400 # Energy for precharge background per rank (pJ) -system.mem_ctrls.totalEnergy::0 96753672 # Total energy per rank (pJ) -system.mem_ctrls.totalEnergy::1 97808088 # Total energy per rank (pJ) -system.mem_ctrls.averagePower::0 826.587089 # Core power per rank (mW) -system.mem_ctrls.averagePower::1 835.595188 # Core power per rank (mW) -system.ruby.clk_domain.clock 1 # Clock period in ticks -system.ruby.delayHist::bucket_size 1 # delay histogram for all message -system.ruby.delayHist::max_bucket 9 # delay histogram for all message -system.ruby.delayHist::samples 3456 # delay histogram for all message -system.ruby.delayHist | 3456 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message -system.ruby.delayHist::total 3456 # delay histogram for all message -system.ruby.outstanding_req_hist::bucket_size 1 -system.ruby.outstanding_req_hist::max_bucket 9 -system.ruby.outstanding_req_hist::samples 8449 -system.ruby.outstanding_req_hist::mean 1 -system.ruby.outstanding_req_hist::gmean 1 -system.ruby.outstanding_req_hist | 0 0.00% 0.00% | 8449 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.outstanding_req_hist::total 8449 -system.ruby.latency_hist::bucket_size 64 -system.ruby.latency_hist::max_bucket 639 -system.ruby.latency_hist::samples 8448 -system.ruby.latency_hist::mean 13.626420 -system.ruby.latency_hist::gmean 5.329740 -system.ruby.latency_hist::stdev 25.242996 -system.ruby.latency_hist | 8195 97.01% 97.01% | 199 2.36% 99.36% | 43 0.51% 99.87% | 2 0.02% 99.89% | 5 0.06% 99.95% | 4 0.05% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.latency_hist::total 8448 -system.ruby.hit_latency_hist::bucket_size 1 -system.ruby.hit_latency_hist::max_bucket 9 -system.ruby.hit_latency_hist::samples 6718 -system.ruby.hit_latency_hist::mean 3 -system.ruby.hit_latency_hist::gmean 3.000000 -system.ruby.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 6718 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.hit_latency_hist::total 6718 -system.ruby.miss_latency_hist::bucket_size 64 -system.ruby.miss_latency_hist::max_bucket 639 -system.ruby.miss_latency_hist::samples 1730 -system.ruby.miss_latency_hist::mean 54.891329 -system.ruby.miss_latency_hist::gmean 49.648144 -system.ruby.miss_latency_hist::stdev 31.153546 -system.ruby.miss_latency_hist | 1477 85.38% 85.38% | 199 11.50% 96.88% | 43 2.49% 99.36% | 2 0.12% 99.48% | 5 0.29% 99.77% | 4 0.23% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.miss_latency_hist::total 1730 -system.ruby.Directory.incomplete_times 1729 -system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.ruby.l1_cntrl0.cacheMemory.demand_hits 6718 # Number of cache demand hits -system.ruby.l1_cntrl0.cacheMemory.demand_misses 1730 # Number of cache demand misses -system.ruby.l1_cntrl0.cacheMemory.demand_accesses 8448 # Number of cache demand accesses +system.mem_ctrls_0.actEnergy 771120 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 428400 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 4879680 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 4281984 # Energy for write commands per rank (pJ) +system.mem_ctrls_0.refreshEnergy 7628400 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_0.actBackEnergy 69480720 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 9282000 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.totalEnergy 96752304 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 826.589526 # Core power per rank (mW) +system.mem_ctrls_0.memoryStateTime::IDLE 15125 # Time in different power states +system.mem_ctrls_0.memoryStateTime::REF 3900 # Time in different power states +system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 98100 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls_1.actEnergy 1081080 # Energy for activate commands per rank (pJ) +system.mem_ctrls_1.preEnergy 600600 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_1.readEnergy 5466240 # Energy for read commands per rank (pJ) +system.mem_ctrls_1.writeEnergy 4323456 # Energy for write commands per rank (pJ) +system.mem_ctrls_1.refreshEnergy 7628400 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_1.actBackEnergy 69027912 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 9680400 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.totalEnergy 97808088 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 835.595188 # Core power per rank (mW) +system.mem_ctrls_1.memoryStateTime::IDLE 15368 # Time in different power states +system.mem_ctrls_1.memoryStateTime::REF 3900 # Time in different power states +system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 97798 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.clk_domain.clock 1 # Clock period in ticks -system.ruby.network.routers0.percent_links_utilized 6.992328 -system.ruby.network.routers0.msg_count.Control::2 1730 -system.ruby.network.routers0.msg_count.Data::2 1726 -system.ruby.network.routers0.msg_count.Response_Data::4 1730 -system.ruby.network.routers0.msg_count.Writeback_Control::3 1726 -system.ruby.network.routers0.msg_bytes.Control::2 13840 -system.ruby.network.routers0.msg_bytes.Data::2 124272 -system.ruby.network.routers0.msg_bytes.Response_Data::4 124560 -system.ruby.network.routers0.msg_bytes.Writeback_Control::3 13808 -system.ruby.network.routers1.percent_links_utilized 6.992328 -system.ruby.network.routers1.msg_count.Control::2 1730 -system.ruby.network.routers1.msg_count.Data::2 1726 -system.ruby.network.routers1.msg_count.Response_Data::4 1730 -system.ruby.network.routers1.msg_count.Writeback_Control::3 1726 -system.ruby.network.routers1.msg_bytes.Control::2 13840 -system.ruby.network.routers1.msg_bytes.Data::2 124272 -system.ruby.network.routers1.msg_bytes.Response_Data::4 124560 -system.ruby.network.routers1.msg_bytes.Writeback_Control::3 13808 -system.ruby.network.routers2.percent_links_utilized 6.992328 -system.ruby.network.routers2.msg_count.Control::2 1730 -system.ruby.network.routers2.msg_count.Data::2 1726 -system.ruby.network.routers2.msg_count.Response_Data::4 1730 -system.ruby.network.routers2.msg_count.Writeback_Control::3 1726 -system.ruby.network.routers2.msg_bytes.Control::2 13840 -system.ruby.network.routers2.msg_bytes.Data::2 124272 -system.ruby.network.routers2.msg_bytes.Response_Data::4 124560 -system.ruby.network.routers2.msg_bytes.Writeback_Control::3 13808 -system.ruby.network.msg_count.Control 5190 -system.ruby.network.msg_count.Data 5178 -system.ruby.network.msg_count.Response_Data 5190 -system.ruby.network.msg_count.Writeback_Control 5178 -system.ruby.network.msg_byte.Control 41520 -system.ruby.network.msg_byte.Data 372816 -system.ruby.network.msg_byte.Response_Data 373680 -system.ruby.network.msg_byte.Writeback_Control 41424 system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -429,6 +358,82 @@ system.cpu.op_class::MemWrite 868 13.56% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 6400 # Class of executed instruction +system.ruby.clk_domain.clock 1 # Clock period in ticks +system.ruby.delayHist::bucket_size 1 # delay histogram for all message +system.ruby.delayHist::max_bucket 9 # delay histogram for all message +system.ruby.delayHist::samples 3456 # delay histogram for all message +system.ruby.delayHist | 3456 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message +system.ruby.delayHist::total 3456 # delay histogram for all message +system.ruby.outstanding_req_hist::bucket_size 1 +system.ruby.outstanding_req_hist::max_bucket 9 +system.ruby.outstanding_req_hist::samples 8449 +system.ruby.outstanding_req_hist::mean 1 +system.ruby.outstanding_req_hist::gmean 1 +system.ruby.outstanding_req_hist | 0 0.00% 0.00% | 8449 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.outstanding_req_hist::total 8449 +system.ruby.latency_hist::bucket_size 64 +system.ruby.latency_hist::max_bucket 639 +system.ruby.latency_hist::samples 8448 +system.ruby.latency_hist::mean 13.626420 +system.ruby.latency_hist::gmean 5.329740 +system.ruby.latency_hist::stdev 25.242996 +system.ruby.latency_hist | 8195 97.01% 97.01% | 199 2.36% 99.36% | 43 0.51% 99.87% | 2 0.02% 99.89% | 5 0.06% 99.95% | 4 0.05% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.latency_hist::total 8448 +system.ruby.hit_latency_hist::bucket_size 1 +system.ruby.hit_latency_hist::max_bucket 9 +system.ruby.hit_latency_hist::samples 6718 +system.ruby.hit_latency_hist::mean 3 +system.ruby.hit_latency_hist::gmean 3.000000 +system.ruby.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 6718 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.hit_latency_hist::total 6718 +system.ruby.miss_latency_hist::bucket_size 64 +system.ruby.miss_latency_hist::max_bucket 639 +system.ruby.miss_latency_hist::samples 1730 +system.ruby.miss_latency_hist::mean 54.891329 +system.ruby.miss_latency_hist::gmean 49.648144 +system.ruby.miss_latency_hist::stdev 31.153546 +system.ruby.miss_latency_hist | 1477 85.38% 85.38% | 199 11.50% 96.88% | 43 2.49% 99.36% | 2 0.12% 99.48% | 5 0.29% 99.77% | 4 0.23% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.miss_latency_hist::total 1730 +system.ruby.Directory.incomplete_times 1729 +system.ruby.l1_cntrl0.cacheMemory.demand_hits 6718 # Number of cache demand hits +system.ruby.l1_cntrl0.cacheMemory.demand_misses 1730 # Number of cache demand misses +system.ruby.l1_cntrl0.cacheMemory.demand_accesses 8448 # Number of cache demand accesses +system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks +system.ruby.network.routers0.percent_links_utilized 6.992328 +system.ruby.network.routers0.msg_count.Control::2 1730 +system.ruby.network.routers0.msg_count.Data::2 1726 +system.ruby.network.routers0.msg_count.Response_Data::4 1730 +system.ruby.network.routers0.msg_count.Writeback_Control::3 1726 +system.ruby.network.routers0.msg_bytes.Control::2 13840 +system.ruby.network.routers0.msg_bytes.Data::2 124272 +system.ruby.network.routers0.msg_bytes.Response_Data::4 124560 +system.ruby.network.routers0.msg_bytes.Writeback_Control::3 13808 +system.ruby.network.routers1.percent_links_utilized 6.992328 +system.ruby.network.routers1.msg_count.Control::2 1730 +system.ruby.network.routers1.msg_count.Data::2 1726 +system.ruby.network.routers1.msg_count.Response_Data::4 1730 +system.ruby.network.routers1.msg_count.Writeback_Control::3 1726 +system.ruby.network.routers1.msg_bytes.Control::2 13840 +system.ruby.network.routers1.msg_bytes.Data::2 124272 +system.ruby.network.routers1.msg_bytes.Response_Data::4 124560 +system.ruby.network.routers1.msg_bytes.Writeback_Control::3 13808 +system.ruby.network.routers2.percent_links_utilized 6.992328 +system.ruby.network.routers2.msg_count.Control::2 1730 +system.ruby.network.routers2.msg_count.Data::2 1726 +system.ruby.network.routers2.msg_count.Response_Data::4 1730 +system.ruby.network.routers2.msg_count.Writeback_Control::3 1726 +system.ruby.network.routers2.msg_bytes.Control::2 13840 +system.ruby.network.routers2.msg_bytes.Data::2 124272 +system.ruby.network.routers2.msg_bytes.Response_Data::4 124560 +system.ruby.network.routers2.msg_bytes.Writeback_Control::3 13808 +system.ruby.network.msg_count.Control 5190 +system.ruby.network.msg_count.Data 5178 +system.ruby.network.msg_count.Response_Data 5190 +system.ruby.network.msg_count.Writeback_Control 5178 +system.ruby.network.msg_byte.Control 41520 +system.ruby.network.msg_byte.Data 372816 +system.ruby.network.msg_byte.Response_Data 373680 +system.ruby.network.msg_byte.Writeback_Control 41424 system.ruby.network.routers0.throttle0.link_utilization 6.998802 system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1730 system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 1726 @@ -596,6 +601,14 @@ system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 52.414605 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 32.138819 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 614 84.11% 84.11% | 92 12.60% 96.71% | 19 2.60% 99.32% | 0 0.00% 99.32% | 3 0.41% 99.73% | 2 0.27% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total 730 +system.ruby.Directory_Controller.GETX 1730 0.00% 0.00% +system.ruby.Directory_Controller.PUTX 1726 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Data 1730 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Ack 1726 0.00% 0.00% +system.ruby.Directory_Controller.I.GETX 1730 0.00% 0.00% +system.ruby.Directory_Controller.M.PUTX 1726 0.00% 0.00% +system.ruby.Directory_Controller.IM.Memory_Data 1730 0.00% 0.00% +system.ruby.Directory_Controller.MI.Memory_Ack 1726 0.00% 0.00% system.ruby.L1Cache_Controller.Load 1183 0.00% 0.00% system.ruby.L1Cache_Controller.Ifetch 6400 0.00% 0.00% system.ruby.L1Cache_Controller.Store 865 0.00% 0.00% @@ -612,13 +625,5 @@ system.ruby.L1Cache_Controller.M.Replacement 1726 0.00% 0.00% system.ruby.L1Cache_Controller.MI.Writeback_Ack 1726 0.00% 0.00% system.ruby.L1Cache_Controller.IS.Data 1457 0.00% 0.00% system.ruby.L1Cache_Controller.IM.Data 273 0.00% 0.00% -system.ruby.Directory_Controller.GETX 1730 0.00% 0.00% -system.ruby.Directory_Controller.PUTX 1726 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Data 1730 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Ack 1726 0.00% 0.00% -system.ruby.Directory_Controller.I.GETX 1730 0.00% 0.00% -system.ruby.Directory_Controller.M.PUTX 1726 0.00% 0.00% -system.ruby.Directory_Controller.IM.Memory_Data 1730 0.00% 0.00% -system.ruby.Directory_Controller.MI.Memory_Ack 1726 0.00% 0.00% ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt index 0513960dd..8eeabeb60 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000019 # Nu sim_ticks 18733500 # Number of ticks simulated final_tick 18733500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 41421 # Simulator instruction rate (inst/s) -host_op_rate 41407 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 299977624 # Simulator tick rate (ticks/s) -host_mem_usage 235900 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host +host_inst_rate 81438 # Simulator instruction rate (inst/s) +host_op_rate 81405 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 589715743 # Simulator tick rate (ticks/s) +host_mem_usage 292180 # Number of bytes of host memory used +host_seconds 0.03 # Real time elapsed on the host sim_insts 2585 # Number of instructions simulated sim_ops 2585 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -196,12 +196,12 @@ system.physmem.bytesPerActivate::768-895 4 9.30% 88.37% # By system.physmem.bytesPerActivate::896-1023 2 4.65% 93.02% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 3 6.98% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 43 # Bytes accessed per row activation -system.physmem.totQLat 1958750 # Total ticks spent queuing -system.physmem.totMemAccLat 7733750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 1952250 # Total ticks spent queuing +system.physmem.totMemAccLat 7727250 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 1540000 # Total ticks spent in databus transfers -system.physmem.avgQLat 6359.58 # Average queueing delay per DRAM burst +system.physmem.avgQLat 6338.47 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25109.58 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 25088.47 # Average memory access latency per DRAM burst system.physmem.avgRdBW 1052.23 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 1052.23 # Average system read bandwidth in MiByte/s @@ -218,29 +218,34 @@ system.physmem.readRowHitRate 83.44 # Ro system.physmem.writeRowHitRate nan # Row buffer hit rate for writes system.physmem.avgGap 60556.82 # Average gap between requests system.physmem.pageHitRate 83.44 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 15500 # Time in different power states -system.physmem.memoryStateTime::REF 520000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 15310750 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 83160 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 219240 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 45375 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 119625 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 795600 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 1294800 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 1017120 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 1017120 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 10790100 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 10507095 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 34500 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 282750 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 12765855 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 13440630 # Total energy per rank (pJ) -system.physmem.averagePower::0 806.306964 # Core power per rank (mW) -system.physmem.averagePower::1 848.926575 # Core power per rank (mW) +system.physmem_0.actEnergy 83160 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 45375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 795600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 10790100 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 34500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 12765855 # Total energy per rank (pJ) +system.physmem_0.averagePower 806.306964 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 894750 # Time in different power states +system.physmem_0.memoryStateTime::REF 520000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 15310750 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 219240 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 119625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1294800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 10507095 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 282750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 13440630 # Total energy per rank (pJ) +system.physmem_1.averagePower 848.926575 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 429000 # Time in different power states +system.physmem_1.memoryStateTime::REF 520000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 14897250 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.branchPred.lookups 793 # Number of BP lookups system.cpu.branchPred.condPredicted 397 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 168 # Number of conditional branches incorrect @@ -296,14 +301,14 @@ system.cpu.ipc 0.068994 # IP system.cpu.tickCycles 5412 # Number of cycles that the object actually ticked system.cpu.idleCycles 32055 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 48.468521 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 48.478730 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 692 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 85 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 8.141176 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.inst 48.468521 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.inst 0.011833 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.011833 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.inst 48.478730 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.inst 0.011836 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.011836 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 85 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 35 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 50 # Occupied blocks per task id @@ -326,14 +331,14 @@ system.cpu.dcache.demand_misses::cpu.inst 104 # n system.cpu.dcache.demand_misses::total 104 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.inst 104 # number of overall misses system.cpu.dcache.overall_misses::total 104 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 4636500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 4636500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 3517500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 3517500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.inst 8154000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 8154000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.inst 8154000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 8154000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.inst 4644500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4644500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.inst 3502000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 3502000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.inst 8146500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 8146500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.inst 8146500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 8146500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.inst 502 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 502 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.inst 294 # number of WriteReq accesses(hits+misses) @@ -350,14 +355,14 @@ system.cpu.dcache.demand_miss_rate::cpu.inst 0.130653 system.cpu.dcache.demand_miss_rate::total 0.130653 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.inst 0.130653 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.130653 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 76008.196721 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 76008.196721 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 81802.325581 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 81802.325581 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 78403.846154 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 78403.846154 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 78403.846154 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 78403.846154 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 76139.344262 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 76139.344262 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 81441.860465 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 81441.860465 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 78331.730769 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 78331.730769 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 78331.730769 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 78331.730769 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -382,14 +387,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.inst 85 system.cpu.dcache.demand_mshr_misses::total 85 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.inst 85 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 85 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 4302500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4302500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 2086500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2086500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 6389000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6389000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 6389000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6389000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 4310500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4310500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 2079250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2079250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 6389750 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6389750 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 6389750 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6389750 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.115538 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.115538 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.091837 # mshr miss rate for WriteReq accesses @@ -398,24 +403,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.106784 system.cpu.dcache.demand_mshr_miss_rate::total 0.106784 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.106784 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.106784 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 74181.034483 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 74181.034483 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 77277.777778 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77277.777778 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 75164.705882 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 75164.705882 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 75164.705882 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 75164.705882 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 74318.965517 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 74318.965517 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 77009.259259 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77009.259259 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 75173.529412 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 75173.529412 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 75173.529412 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 75173.529412 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 118.426247 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 118.465909 # Cycle average of tags in use system.cpu.icache.tags.total_refs 751 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 223 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 3.367713 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 118.426247 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.057825 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.057825 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 118.465909 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.057845 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.057845 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 223 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 109 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 114 # Occupied blocks per task id @@ -434,12 +439,12 @@ system.cpu.icache.demand_misses::cpu.inst 223 # n system.cpu.icache.demand_misses::total 223 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 223 # number of overall misses system.cpu.icache.overall_misses::total 223 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 15431500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 15431500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 15431500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 15431500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 15431500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 15431500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 15423500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 15423500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 15423500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 15423500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 15423500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 15423500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 974 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 974 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 974 # number of demand (read+write) accesses @@ -452,12 +457,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.228953 system.cpu.icache.demand_miss_rate::total 0.228953 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.228953 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.228953 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69199.551570 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 69199.551570 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 69199.551570 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 69199.551570 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 69199.551570 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 69199.551570 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69163.677130 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 69163.677130 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 69163.677130 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 69163.677130 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 69163.677130 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 69163.677130 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -472,34 +477,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 223 system.cpu.icache.demand_mshr_misses::total 223 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 223 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 223 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14892500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 14892500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14892500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 14892500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14892500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 14892500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14884500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 14884500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14884500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 14884500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14884500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 14884500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.228953 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.228953 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.228953 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.228953 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.228953 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.228953 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66782.511211 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66782.511211 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66782.511211 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 66782.511211 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66782.511211 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 66782.511211 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66746.636771 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66746.636771 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66746.636771 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 66746.636771 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66746.636771 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 66746.636771 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 146.486275 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 146.534478 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 281 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 146.486275 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004470 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.004470 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 146.534478 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004472 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.004472 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 281 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 142 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 139 # Occupied blocks per task id @@ -516,12 +521,12 @@ system.cpu.l2cache.overall_misses::cpu.inst 308 # system.cpu.l2cache.overall_misses::total 308 # number of overall misses system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 18913000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::total 18913000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 2059500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 2059500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 20972500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 20972500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 20972500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 20972500 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 2052250 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 2052250 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 20965250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 20965250 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 20965250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 20965250 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 281 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 281 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.inst 27 # number of ReadExReq accesses(hits+misses) @@ -540,12 +545,12 @@ system.cpu.l2cache.overall_miss_rate::cpu.inst 1 system.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67306.049822 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::total 67306.049822 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 76277.777778 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76277.777778 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68092.532468 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 68092.532468 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68092.532468 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 68092.532468 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 76009.259259 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76009.259259 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68068.993506 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 68068.993506 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68068.993506 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 68068.993506 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -564,12 +569,12 @@ system.cpu.l2cache.overall_mshr_misses::cpu.inst 308 system.cpu.l2cache.overall_mshr_misses::total 308 # number of overall MSHR misses system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 15398500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15398500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 1725500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1725500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 17124000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 17124000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17124000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 17124000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 1718250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1718250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 17116750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 17116750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17116750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 17116750 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadExReq accesses @@ -580,12 +585,12 @@ system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54798.932384 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 54798.932384 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 63907.407407 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63907.407407 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55597.402597 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55597.402597 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55597.402597 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55597.402597 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 63638.888889 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63638.888889 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55573.863636 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55573.863636 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55573.863636 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55573.863636 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 281 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 281 # Transaction distribution @@ -613,7 +618,7 @@ system.cpu.toL2Bus.reqLayer0.occupancy 154000 # La system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 381000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 2.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 137000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 136750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) system.membus.trans_dist::ReadReq 281 # Transaction distribution system.membus.trans_dist::ReadResp 281 # Transaction distribution @@ -636,7 +641,7 @@ system.membus.snoop_fanout::max_value 0 # Re system.membus.snoop_fanout::total 308 # Request fanout histogram system.membus.reqLayer0.occupancy 363000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.9 # Layer utilization (%) -system.membus.respLayer1.occupancy 2868500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2868750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 15.3 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt index dd62dc740..49b58755c 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000012 # Nu sim_ticks 11765500 # Number of ticks simulated final_tick 11765500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 35174 # Simulator instruction rate (inst/s) -host_op_rate 35164 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 173275234 # Simulator tick rate (ticks/s) -host_mem_usage 235920 # Number of bytes of host memory used -host_seconds 0.07 # Real time elapsed on the host +host_inst_rate 73154 # Simulator instruction rate (inst/s) +host_op_rate 73124 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 360297045 # Simulator tick rate (ticks/s) +host_mem_usage 293708 # Number of bytes of host memory used +host_seconds 0.03 # Real time elapsed on the host sim_insts 2387 # Number of instructions simulated sim_ops 2387 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -222,53 +222,34 @@ system.physmem.readRowHitRate 81.99 # Ro system.physmem.writeRowHitRate nan # Row buffer hit rate for writes system.physmem.avgGap 42926.47 # Average gap between requests system.physmem.pageHitRate 81.99 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 22000 # Time in different power states -system.physmem.memoryStateTime::REF 260000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 7778000 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 68040 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 158760 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 37125 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 86625 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 631800 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 850200 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 508560 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 508560 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 5478840 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 5222340 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 21750 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 246750 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 6746115 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 7073235 # Total energy per rank (pJ) -system.physmem.averagePower::0 838.417275 # Core power per rank (mW) -system.physmem.averagePower::1 879.072239 # Core power per rank (mW) -system.membus.trans_dist::ReadReq 248 # Transaction distribution -system.membus.trans_dist::ReadResp 248 # Transaction distribution -system.membus.trans_dist::ReadExReq 24 # Transaction distribution -system.membus.trans_dist::ReadExResp 24 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 544 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 544 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17408 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 17408 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 272 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 272 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 272 # Request fanout histogram -system.membus.reqLayer0.occupancy 339500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.9 # Layer utilization (%) -system.membus.respLayer1.occupancy 2545000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 21.6 # Layer utilization (%) -system.cpu_clk_domain.clock 500 # Clock period in ticks +system.physmem_0.actEnergy 68040 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 37125 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 631800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 508560 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 5478840 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 21750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 6746115 # Total energy per rank (pJ) +system.physmem_0.averagePower 838.417275 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 206000 # Time in different power states +system.physmem_0.memoryStateTime::REF 260000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 7778000 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 158760 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 86625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 850200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 508560 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 5222340 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 246750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 7073235 # Total energy per rank (pJ) +system.physmem_1.averagePower 879.072239 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 397500 # Time in different power states +system.physmem_1.memoryStateTime::REF 260000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 7402500 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.branchPred.lookups 1090 # Number of BP lookups system.cpu.branchPred.condPredicted 548 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 231 # Number of conditional branches incorrect @@ -278,6 +259,7 @@ system.cpu.branchPred.BTBCorrect 0 # Nu system.cpu.branchPred.BTBHitPct 27.520436 # BTB Hit Percentage system.cpu.branchPred.usedRAS 199 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 9 # Number of incorrect RAS predictions. +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -603,34 +585,118 @@ system.cpu.int_regfile_writes 2774 # nu system.cpu.fp_regfile_reads 6 # number of floating regfile reads system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.trans_dist::ReadReq 248 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 248 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 24 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 24 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 374 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 170 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 544 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 11968 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5440 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 17408 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 272 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 272 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 272 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 136000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 314250 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.7 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 133250 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%) +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 46.118209 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 729 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 85 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 8.576471 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 46.118209 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.011259 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.011259 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 85 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 69 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 16 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.020752 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 1939 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1939 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 516 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 516 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 213 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 213 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 729 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 729 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 729 # number of overall hits +system.cpu.dcache.overall_hits::total 729 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 117 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 117 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 81 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 81 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 198 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 198 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 198 # number of overall misses +system.cpu.dcache.overall_misses::total 198 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 7447000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 7447000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 5312000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 5312000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 12759000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 12759000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 12759000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 12759000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 633 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 633 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 294 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 294 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 927 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 927 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 927 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 927 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.184834 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.184834 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.275510 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.275510 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.213592 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.213592 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.213592 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.213592 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63649.572650 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 63649.572650 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65580.246914 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 65580.246914 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 64439.393939 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 64439.393939 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 64439.393939 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 64439.393939 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 131 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 65.500000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 56 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 56 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 57 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 57 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 113 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 113 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 113 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 113 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 61 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 61 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 24 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 24 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 85 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 85 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 85 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4512500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4512500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1719750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1719750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6232250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6232250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6232250 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6232250 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.096367 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.096367 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.081633 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.081633 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091694 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.091694 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091694 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.091694 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 73975.409836 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 73975.409836 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71656.250000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71656.250000 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73320.588235 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 73320.588235 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73320.588235 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 73320.588235 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements system.cpu.icache.tags.tagsinuse 92.065177 # Cycle average of tags in use system.cpu.icache.tags.total_refs 685 # Total number of references to valid blocks. @@ -846,117 +912,56 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55340.909091 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60032.352941 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56806.985294 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 46.118209 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 729 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 85 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 8.576471 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 46.118209 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.011259 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.011259 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 85 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 69 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 16 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.020752 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1939 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1939 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 516 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 516 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 213 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 213 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 729 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 729 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 729 # number of overall hits -system.cpu.dcache.overall_hits::total 729 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 117 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 117 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 81 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 81 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 198 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 198 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 198 # number of overall misses -system.cpu.dcache.overall_misses::total 198 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 7447000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 7447000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 5312000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 5312000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 12759000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 12759000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 12759000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 12759000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 633 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 633 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 294 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 294 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 927 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 927 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 927 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 927 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.184834 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.184834 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.275510 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.275510 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.213592 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.213592 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.213592 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.213592 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63649.572650 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 63649.572650 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65580.246914 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 65580.246914 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 64439.393939 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 64439.393939 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 64439.393939 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 64439.393939 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 131 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 65.500000 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 56 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 56 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 57 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 57 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 113 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 113 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 113 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 113 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 61 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 61 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 24 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 24 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 85 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 85 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 85 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4512500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4512500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1719750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1719750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6232250 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6232250 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6232250 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6232250 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.096367 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.096367 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.081633 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.081633 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091694 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.091694 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091694 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.091694 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 73975.409836 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 73975.409836 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71656.250000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71656.250000 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73320.588235 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 73320.588235 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73320.588235 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 73320.588235 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.trans_dist::ReadReq 248 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 248 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 24 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 24 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 374 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 170 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 544 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 11968 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5440 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 17408 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 272 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 272 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 272 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 136000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 314250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 2.7 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 133250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%) +system.membus.trans_dist::ReadReq 248 # Transaction distribution +system.membus.trans_dist::ReadResp 248 # Transaction distribution +system.membus.trans_dist::ReadExReq 24 # Transaction distribution +system.membus.trans_dist::ReadExResp 24 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 544 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 544 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17408 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 17408 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 272 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 272 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 272 # Request fanout histogram +system.membus.reqLayer0.occupancy 339500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.9 # Layer utilization (%) +system.membus.respLayer1.occupancy 2545000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 21.6 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/stats.txt index d47845159..84bb9ed03 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000052 # Nu sim_ticks 52301 # Number of ticks simulated final_tick 52301 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 11256 # Simulator instruction rate (inst/s) -host_op_rate 11255 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 228406 # Simulator tick rate (ticks/s) -host_mem_usage 435628 # Number of bytes of host memory used -host_seconds 0.23 # Real time elapsed on the host +host_inst_rate 42059 # Simulator instruction rate (inst/s) +host_op_rate 42050 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 853239 # Simulator tick rate (ticks/s) +host_mem_usage 450140 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -232,29 +232,126 @@ system.mem_ctrls.readRowHitRate 79.91 # Ro system.mem_ctrls.writeRowHitRate 30.43 # Row buffer hit rate for writes system.mem_ctrls.avgGap 80.33 # Average gap between requests system.mem_ctrls.pageHitRate 75.21 # Row buffer hit rate, read and write combined -system.mem_ctrls.memoryStateTime::IDLE 20 # Time in different power states -system.mem_ctrls.memoryStateTime::REF 1560 # Time in different power states -system.mem_ctrls.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls.memoryStateTime::ACT 45410 # Time in different power states -system.mem_ctrls.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrls.actEnergy::0 173880 # Energy for activate commands per rank (pJ) -system.mem_ctrls.actEnergy::1 393120 # Energy for activate commands per rank (pJ) -system.mem_ctrls.preEnergy::0 96600 # Energy for precharge commands per rank (pJ) -system.mem_ctrls.preEnergy::1 218400 # Energy for precharge commands per rank (pJ) -system.mem_ctrls.readEnergy::0 1971840 # Energy for read commands per rank (pJ) -system.mem_ctrls.readEnergy::1 2907840 # Energy for read commands per rank (pJ) -system.mem_ctrls.writeEnergy::0 0 # Energy for write commands per rank (pJ) -system.mem_ctrls.writeEnergy::1 165888 # Energy for write commands per rank (pJ) -system.mem_ctrls.refreshEnergy::0 3051360 # Energy for refresh commands per rank (pJ) -system.mem_ctrls.refreshEnergy::1 3051360 # Energy for refresh commands per rank (pJ) -system.mem_ctrls.actBackEnergy::0 31347036 # Energy for active background per rank (pJ) -system.mem_ctrls.actBackEnergy::1 31310100 # Energy for active background per rank (pJ) -system.mem_ctrls.preBackEnergy::0 688200 # Energy for precharge background per rank (pJ) -system.mem_ctrls.preBackEnergy::1 720600 # Energy for precharge background per rank (pJ) -system.mem_ctrls.totalEnergy::0 37328916 # Total energy per rank (pJ) -system.mem_ctrls.totalEnergy::1 38767308 # Total energy per rank (pJ) -system.mem_ctrls.averagePower::0 794.638028 # Core power per rank (mW) -system.mem_ctrls.averagePower::1 825.257749 # Core power per rank (mW) +system.mem_ctrls_0.actEnergy 173880 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 96600 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 1971840 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls_0.refreshEnergy 3051360 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_0.actBackEnergy 31347036 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 688200 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.totalEnergy 37328916 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 794.638028 # Core power per rank (mW) +system.mem_ctrls_0.memoryStateTime::IDLE 1179 # Time in different power states +system.mem_ctrls_0.memoryStateTime::REF 1560 # Time in different power states +system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 44437 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls_1.actEnergy 393120 # Energy for activate commands per rank (pJ) +system.mem_ctrls_1.preEnergy 218400 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_1.readEnergy 2907840 # Energy for read commands per rank (pJ) +system.mem_ctrls_1.writeEnergy 165888 # Energy for write commands per rank (pJ) +system.mem_ctrls_1.refreshEnergy 3051360 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_1.actBackEnergy 31309416 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 721200 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.totalEnergy 38767224 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 825.255960 # Core power per rank (mW) +system.mem_ctrls_1.memoryStateTime::IDLE 1048 # Time in different power states +system.mem_ctrls_1.memoryStateTime::REF 1560 # Time in different power states +system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 44382 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.clk_domain.clock 1 # Clock period in ticks +system.cpu.dtb.fetch_hits 0 # ITB hits +system.cpu.dtb.fetch_misses 0 # ITB misses +system.cpu.dtb.fetch_acv 0 # ITB acv +system.cpu.dtb.fetch_accesses 0 # ITB accesses +system.cpu.dtb.read_hits 415 # DTB read hits +system.cpu.dtb.read_misses 4 # DTB read misses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_accesses 419 # DTB read accesses +system.cpu.dtb.write_hits 294 # DTB write hits +system.cpu.dtb.write_misses 4 # DTB write misses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_accesses 298 # DTB write accesses +system.cpu.dtb.data_hits 709 # DTB hits +system.cpu.dtb.data_misses 8 # DTB misses +system.cpu.dtb.data_acv 0 # DTB access violations +system.cpu.dtb.data_accesses 717 # DTB accesses +system.cpu.itb.fetch_hits 2586 # ITB hits +system.cpu.itb.fetch_misses 11 # ITB misses +system.cpu.itb.fetch_acv 0 # ITB acv +system.cpu.itb.fetch_accesses 2597 # ITB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_acv 0 # DTB read access violations +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_acv 0 # DTB write access violations +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.data_hits 0 # DTB hits +system.cpu.itb.data_misses 0 # DTB misses +system.cpu.itb.data_acv 0 # DTB access violations +system.cpu.itb.data_accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 4 # Number of system calls +system.cpu.numCycles 52301 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 2577 # Number of instructions committed +system.cpu.committedOps 2577 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 2375 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 6 # Number of float alu accesses +system.cpu.num_func_calls 140 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 238 # number of instructions that are conditional controls +system.cpu.num_int_insts 2375 # number of integer instructions +system.cpu.num_fp_insts 6 # number of float instructions +system.cpu.num_int_register_reads 2998 # number of times the integer registers were read +system.cpu.num_int_register_writes 1768 # number of times the integer registers were written +system.cpu.num_fp_register_reads 6 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_mem_refs 717 # number of memory refs +system.cpu.num_load_insts 419 # Number of load instructions +system.cpu.num_store_insts 298 # Number of store instructions +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 52301 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.Branches 396 # Number of branches fetched +system.cpu.op_class::No_OpClass 189 7.31% 7.31% # Class of executed instruction +system.cpu.op_class::IntAlu 1678 64.91% 72.22% # Class of executed instruction +system.cpu.op_class::IntMult 1 0.04% 72.26% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::MemRead 419 16.21% 88.47% # Class of executed instruction +system.cpu.op_class::MemWrite 298 11.53% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 2585 # Class of executed instruction system.ruby.clk_domain.clock 1 # Clock period in ticks system.ruby.delayHist::bucket_size 1 # delay histogram for all message system.ruby.delayHist::max_bucket 9 # delay histogram for all message @@ -299,7 +396,6 @@ system.ruby.l1_cntrl0.L1Dcache.demand_accesses 709 system.ruby.l1_cntrl0.L1Icache.demand_hits 2285 # Number of cache demand hits system.ruby.l1_cntrl0.L1Icache.demand_misses 300 # Number of cache demand misses system.ruby.l1_cntrl0.L1Icache.demand_accesses 2585 # Number of cache demand accesses -system.cpu.clk_domain.clock 1 # Clock period in ticks system.ruby.l1_cntrl0.prefetcher.miss_observed 0 # number of misses observed system.ruby.l1_cntrl0.prefetcher.allocated_streams 0 # number of streams allocated for prefetching system.ruby.l1_cntrl0.prefetcher.prefetches_requested 0 # number of prefetch requests made @@ -309,6 +405,10 @@ system.ruby.l1_cntrl0.prefetcher.hits 0 # nu system.ruby.l1_cntrl0.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched system.ruby.l1_cntrl0.prefetcher.pages_crossed 0 # number of prefetches across pages system.ruby.l1_cntrl0.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed +system.ruby.l2_cntrl0.L2cache.demand_hits 25 # Number of cache demand hits +system.ruby.l2_cntrl0.L2cache.demand_misses 547 # Number of cache demand misses +system.ruby.l2_cntrl0.L2cache.demand_accesses 572 # Number of cache demand accesses +system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks system.ruby.network.routers0.percent_links_utilized 3.803943 system.ruby.network.routers0.msg_count.Control::0 572 system.ruby.network.routers0.msg_count.Request_Control::2 431 @@ -326,9 +426,6 @@ system.ruby.network.routers0.msg_bytes.Response_Control::2 2176 system.ruby.network.routers0.msg_bytes.Writeback_Data::0 3240 system.ruby.network.routers0.msg_bytes.Writeback_Data::1 4464 system.ruby.network.routers0.msg_bytes.Writeback_Control::0 632 -system.ruby.l2_cntrl0.L2cache.demand_hits 25 # Number of cache demand hits -system.ruby.l2_cntrl0.L2cache.demand_misses 547 # Number of cache demand misses -system.ruby.l2_cntrl0.L2cache.demand_accesses 572 # Number of cache demand accesses system.ruby.network.routers1.percent_links_utilized 7.327776 system.ruby.network.routers1.msg_count.Control::0 1119 system.ruby.network.routers1.msg_count.Request_Control::2 431 @@ -382,98 +479,6 @@ system.ruby.network.msg_byte.Response_Data 263952 system.ruby.network.msg_byte.Response_Control 41760 system.ruby.network.msg_byte.Writeback_Data 23112 system.ruby.network.msg_byte.Writeback_Control 1896 -system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 415 # DTB read hits -system.cpu.dtb.read_misses 4 # DTB read misses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 419 # DTB read accesses -system.cpu.dtb.write_hits 294 # DTB write hits -system.cpu.dtb.write_misses 4 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 298 # DTB write accesses -system.cpu.dtb.data_hits 709 # DTB hits -system.cpu.dtb.data_misses 8 # DTB misses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 717 # DTB accesses -system.cpu.itb.fetch_hits 2586 # ITB hits -system.cpu.itb.fetch_misses 11 # ITB misses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 2597 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 4 # Number of system calls -system.cpu.numCycles 52301 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 2577 # Number of instructions committed -system.cpu.committedOps 2577 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 2375 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 6 # Number of float alu accesses -system.cpu.num_func_calls 140 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 238 # number of instructions that are conditional controls -system.cpu.num_int_insts 2375 # number of integer instructions -system.cpu.num_fp_insts 6 # number of float instructions -system.cpu.num_int_register_reads 2998 # number of times the integer registers were read -system.cpu.num_int_register_writes 1768 # number of times the integer registers were written -system.cpu.num_fp_register_reads 6 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 717 # number of memory refs -system.cpu.num_load_insts 419 # Number of load instructions -system.cpu.num_store_insts 298 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 52301 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.Branches 396 # Number of branches fetched -system.cpu.op_class::No_OpClass 189 7.31% 7.31% # Class of executed instruction -system.cpu.op_class::IntAlu 1678 64.91% 72.22% # Class of executed instruction -system.cpu.op_class::IntMult 1 0.04% 72.26% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::MemRead 419 16.21% 88.47% # Class of executed instruction -system.cpu.op_class::MemWrite 298 11.53% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 2585 # Class of executed instruction system.ruby.network.routers0.throttle0.link_utilization 5.452095 system.ruby.network.routers0.throttle0.msg_count.Request_Control::2 431 system.ruby.network.routers0.throttle0.msg_count.Response_Data::1 572 @@ -647,6 +652,16 @@ system.ruby.IFETCH.miss_latency_hist::gmean 75.006009 system.ruby.IFETCH.miss_latency_hist::stdev 25.337433 system.ruby.IFETCH.miss_latency_hist | 9 3.00% 3.00% | 0 0.00% 3.00% | 276 92.00% 95.00% | 10 3.33% 98.33% | 1 0.33% 98.67% | 0 0.00% 98.67% | 1 0.33% 99.00% | 1 0.33% 99.33% | 1 0.33% 99.67% | 1 0.33% 100.00% system.ruby.IFETCH.miss_latency_hist::total 300 +system.ruby.Directory_Controller.Fetch 547 0.00% 0.00% +system.ruby.Directory_Controller.Data 103 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Data 547 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Ack 103 0.00% 0.00% +system.ruby.Directory_Controller.CleanReplacement 436 0.00% 0.00% +system.ruby.Directory_Controller.I.Fetch 547 0.00% 0.00% +system.ruby.Directory_Controller.M.Data 103 0.00% 0.00% +system.ruby.Directory_Controller.M.CleanReplacement 436 0.00% 0.00% +system.ruby.Directory_Controller.IM.Memory_Data 547 0.00% 0.00% +system.ruby.Directory_Controller.MI.Memory_Ack 103 0.00% 0.00% system.ruby.L1Cache_Controller.Load 415 0.00% 0.00% system.ruby.L1Cache_Controller.Ifetch 2585 0.00% 0.00% system.ruby.L1Cache_Controller.Store 294 0.00% 0.00% @@ -711,15 +726,5 @@ system.ruby.L2Cache_Controller.ISS.Mem_Data 192 0.00% 0.00% system.ruby.L2Cache_Controller.IS.Mem_Data 291 0.00% 0.00% system.ruby.L2Cache_Controller.IM.Mem_Data 64 0.00% 0.00% system.ruby.L2Cache_Controller.MT_MB.Exclusive_Unblock 272 0.00% 0.00% -system.ruby.Directory_Controller.Fetch 547 0.00% 0.00% -system.ruby.Directory_Controller.Data 103 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Data 547 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Ack 103 0.00% 0.00% -system.ruby.Directory_Controller.CleanReplacement 436 0.00% 0.00% -system.ruby.Directory_Controller.I.Fetch 547 0.00% 0.00% -system.ruby.Directory_Controller.M.Data 103 0.00% 0.00% -system.ruby.Directory_Controller.M.CleanReplacement 436 0.00% 0.00% -system.ruby.Directory_Controller.IM.Memory_Data 547 0.00% 0.00% -system.ruby.Directory_Controller.MI.Memory_Ack 103 0.00% 0.00% ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt index 2e81c65b5..b603fabdb 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000048 # Nu sim_ticks 48283 # Number of ticks simulated final_tick 48283 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 12943 # Simulator instruction rate (inst/s) -host_op_rate 12941 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 242448 # Simulator tick rate (ticks/s) -host_mem_usage 437744 # Number of bytes of host memory used -host_seconds 0.20 # Real time elapsed on the host +host_inst_rate 45603 # Simulator instruction rate (inst/s) +host_op_rate 45593 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 854052 # Simulator tick rate (ticks/s) +host_mem_usage 451760 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -232,29 +232,126 @@ system.mem_ctrls.readRowHitRate 77.66 # Ro system.mem_ctrls.writeRowHitRate 32.61 # Row buffer hit rate for writes system.mem_ctrls.avgGap 88.76 # Average gap between requests system.mem_ctrls.pageHitRate 72.85 # Row buffer hit rate, read and write combined -system.mem_ctrls.memoryStateTime::IDLE 76 # Time in different power states -system.mem_ctrls.memoryStateTime::REF 1560 # Time in different power states -system.mem_ctrls.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls.memoryStateTime::ACT 45412 # Time in different power states -system.mem_ctrls.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrls.actEnergy::0 173880 # Energy for activate commands per rank (pJ) -system.mem_ctrls.actEnergy::1 446040 # Energy for activate commands per rank (pJ) -system.mem_ctrls.preEnergy::0 96600 # Energy for precharge commands per rank (pJ) -system.mem_ctrls.preEnergy::1 247800 # Energy for precharge commands per rank (pJ) -system.mem_ctrls.readEnergy::0 1884480 # Energy for read commands per rank (pJ) -system.mem_ctrls.readEnergy::1 2808000 # Energy for read commands per rank (pJ) -system.mem_ctrls.writeEnergy::0 0 # Energy for write commands per rank (pJ) -system.mem_ctrls.writeEnergy::1 165888 # Energy for write commands per rank (pJ) -system.mem_ctrls.refreshEnergy::0 3051360 # Energy for refresh commands per rank (pJ) -system.mem_ctrls.refreshEnergy::1 3051360 # Energy for refresh commands per rank (pJ) -system.mem_ctrls.actBackEnergy::0 31539240 # Energy for active background per rank (pJ) -system.mem_ctrls.actBackEnergy::1 30693132 # Energy for active background per rank (pJ) -system.mem_ctrls.preBackEnergy::0 520800 # Energy for precharge background per rank (pJ) -system.mem_ctrls.preBackEnergy::1 1263000 # Energy for precharge background per rank (pJ) -system.mem_ctrls.totalEnergy::0 37266360 # Total energy per rank (pJ) -system.mem_ctrls.totalEnergy::1 38675220 # Total energy per rank (pJ) -system.mem_ctrls.averagePower::0 793.272596 # Core power per rank (mW) -system.mem_ctrls.averagePower::1 823.262378 # Core power per rank (mW) +system.mem_ctrls_0.actEnergy 173880 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 96600 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 1884480 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls_0.refreshEnergy 3051360 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_0.actBackEnergy 31537872 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 520800 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.totalEnergy 37264992 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 793.277248 # Core power per rank (mW) +system.mem_ctrls_0.memoryStateTime::IDLE 968 # Time in different power states +system.mem_ctrls_0.memoryStateTime::REF 1560 # Time in different power states +system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 44716 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls_1.actEnergy 446040 # Energy for activate commands per rank (pJ) +system.mem_ctrls_1.preEnergy 247800 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_1.readEnergy 2808000 # Energy for read commands per rank (pJ) +system.mem_ctrls_1.writeEnergy 165888 # Energy for write commands per rank (pJ) +system.mem_ctrls_1.refreshEnergy 3051360 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_1.actBackEnergy 30693132 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 1263000 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.totalEnergy 38675220 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 823.262378 # Core power per rank (mW) +system.mem_ctrls_1.memoryStateTime::IDLE 2007 # Time in different power states +system.mem_ctrls_1.memoryStateTime::REF 1560 # Time in different power states +system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 43481 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.clk_domain.clock 1 # Clock period in ticks +system.cpu.dtb.fetch_hits 0 # ITB hits +system.cpu.dtb.fetch_misses 0 # ITB misses +system.cpu.dtb.fetch_acv 0 # ITB acv +system.cpu.dtb.fetch_accesses 0 # ITB accesses +system.cpu.dtb.read_hits 415 # DTB read hits +system.cpu.dtb.read_misses 4 # DTB read misses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_accesses 419 # DTB read accesses +system.cpu.dtb.write_hits 294 # DTB write hits +system.cpu.dtb.write_misses 4 # DTB write misses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_accesses 298 # DTB write accesses +system.cpu.dtb.data_hits 709 # DTB hits +system.cpu.dtb.data_misses 8 # DTB misses +system.cpu.dtb.data_acv 0 # DTB access violations +system.cpu.dtb.data_accesses 717 # DTB accesses +system.cpu.itb.fetch_hits 2586 # ITB hits +system.cpu.itb.fetch_misses 11 # ITB misses +system.cpu.itb.fetch_acv 0 # ITB acv +system.cpu.itb.fetch_accesses 2597 # ITB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_acv 0 # DTB read access violations +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_acv 0 # DTB write access violations +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.data_hits 0 # DTB hits +system.cpu.itb.data_misses 0 # DTB misses +system.cpu.itb.data_acv 0 # DTB access violations +system.cpu.itb.data_accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 4 # Number of system calls +system.cpu.numCycles 48283 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 2577 # Number of instructions committed +system.cpu.committedOps 2577 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 2375 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 6 # Number of float alu accesses +system.cpu.num_func_calls 140 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 238 # number of instructions that are conditional controls +system.cpu.num_int_insts 2375 # number of integer instructions +system.cpu.num_fp_insts 6 # number of float instructions +system.cpu.num_int_register_reads 2998 # number of times the integer registers were read +system.cpu.num_int_register_writes 1768 # number of times the integer registers were written +system.cpu.num_fp_register_reads 6 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_mem_refs 717 # number of memory refs +system.cpu.num_load_insts 419 # Number of load instructions +system.cpu.num_store_insts 298 # Number of store instructions +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 48283 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.Branches 396 # Number of branches fetched +system.cpu.op_class::No_OpClass 189 7.31% 7.31% # Class of executed instruction +system.cpu.op_class::IntAlu 1678 64.91% 72.22% # Class of executed instruction +system.cpu.op_class::IntMult 1 0.04% 72.26% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::MemRead 419 16.21% 88.47% # Class of executed instruction +system.cpu.op_class::MemWrite 298 11.53% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 2585 # Class of executed instruction system.ruby.clk_domain.clock 1 # Clock period in ticks system.ruby.outstanding_req_hist::bucket_size 1 system.ruby.outstanding_req_hist::max_bucket 9 @@ -292,7 +389,10 @@ system.ruby.l1_cntrl0.L1Dcache.demand_accesses 709 system.ruby.l1_cntrl0.L1Icache.demand_hits 2315 # Number of cache demand hits system.ruby.l1_cntrl0.L1Icache.demand_misses 270 # Number of cache demand misses system.ruby.l1_cntrl0.L1Icache.demand_accesses 2585 # Number of cache demand accesses -system.cpu.clk_domain.clock 1 # Clock period in ticks +system.ruby.l2_cntrl0.L2cache.demand_hits 79 # Number of cache demand hits +system.ruby.l2_cntrl0.L2cache.demand_misses 465 # Number of cache demand misses +system.ruby.l2_cntrl0.L2cache.demand_accesses 544 # Number of cache demand accesses +system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks system.ruby.network.routers0.percent_links_utilized 5.874739 system.ruby.network.routers0.msg_count.Request_Control::0 544 system.ruby.network.routers0.msg_count.Response_Data::2 465 @@ -306,9 +406,6 @@ system.ruby.network.routers0.msg_bytes.ResponseL2hit_Data::2 5688 system.ruby.network.routers0.msg_bytes.Writeback_Data::2 34704 system.ruby.network.routers0.msg_bytes.Writeback_Control::0 8032 system.ruby.network.routers0.msg_bytes.Unblock_Control::2 4512 -system.ruby.l2_cntrl0.L2cache.demand_hits 79 # Number of cache demand hits -system.ruby.l2_cntrl0.L2cache.demand_misses 465 # Number of cache demand misses -system.ruby.l2_cntrl0.L2cache.demand_accesses 544 # Number of cache demand accesses system.ruby.network.routers1.percent_links_utilized 8.967442 system.ruby.network.routers1.msg_count.Request_Control::0 544 system.ruby.network.routers1.msg_count.Request_Control::1 465 @@ -366,98 +463,6 @@ system.ruby.network.msg_byte.ResponseL2hit_Data 17064 system.ruby.network.msg_byte.Writeback_Data 120960 system.ruby.network.msg_byte.Writeback_Control 27840 system.ruby.network.msg_byte.Unblock_Control 24688 -system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 415 # DTB read hits -system.cpu.dtb.read_misses 4 # DTB read misses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 419 # DTB read accesses -system.cpu.dtb.write_hits 294 # DTB write hits -system.cpu.dtb.write_misses 4 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 298 # DTB write accesses -system.cpu.dtb.data_hits 709 # DTB hits -system.cpu.dtb.data_misses 8 # DTB misses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 717 # DTB accesses -system.cpu.itb.fetch_hits 2586 # ITB hits -system.cpu.itb.fetch_misses 11 # ITB misses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 2597 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 4 # Number of system calls -system.cpu.numCycles 48283 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 2577 # Number of instructions committed -system.cpu.committedOps 2577 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 2375 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 6 # Number of float alu accesses -system.cpu.num_func_calls 140 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 238 # number of instructions that are conditional controls -system.cpu.num_int_insts 2375 # number of integer instructions -system.cpu.num_fp_insts 6 # number of float instructions -system.cpu.num_int_register_reads 2998 # number of times the integer registers were read -system.cpu.num_int_register_writes 1768 # number of times the integer registers were written -system.cpu.num_fp_register_reads 6 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 717 # number of memory refs -system.cpu.num_load_insts 419 # Number of load instructions -system.cpu.num_store_insts 298 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 48283 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.Branches 396 # Number of branches fetched -system.cpu.op_class::No_OpClass 189 7.31% 7.31% # Class of executed instruction -system.cpu.op_class::IntAlu 1678 64.91% 72.22% # Class of executed instruction -system.cpu.op_class::IntMult 1 0.04% 72.26% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::MemRead 419 16.21% 88.47% # Class of executed instruction -system.cpu.op_class::MemWrite 298 11.53% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 2585 # Class of executed instruction system.ruby.network.routers0.throttle0.link_utilization 5.589959 system.ruby.network.routers0.throttle0.msg_count.Response_Data::2 465 system.ruby.network.routers0.throttle0.msg_count.ResponseL2hit_Data::2 79 @@ -614,6 +619,29 @@ system.ruby.IFETCH.miss_latency_hist::gmean 69.413198 system.ruby.IFETCH.miss_latency_hist::stdev 30.681798 system.ruby.IFETCH.miss_latency_hist | 26 9.63% 9.63% | 239 88.52% 98.15% | 2 0.74% 98.89% | 0 0.00% 98.89% | 2 0.74% 99.63% | 1 0.37% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.miss_latency_hist::total 270 +system.ruby.Directory_Controller.GETX 80 0.00% 0.00% +system.ruby.Directory_Controller.GETS 385 0.00% 0.00% +system.ruby.Directory_Controller.PUTX 78 0.00% 0.00% +system.ruby.Directory_Controller.Unblock 262 0.00% 0.00% +system.ruby.Directory_Controller.Last_Unblock 122 0.00% 0.00% +system.ruby.Directory_Controller.Exclusive_Unblock 80 0.00% 0.00% +system.ruby.Directory_Controller.Dirty_Writeback 78 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Data 465 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Ack 78 0.00% 0.00% +system.ruby.Directory_Controller.I.GETX 40 0.00% 0.00% +system.ruby.Directory_Controller.I.GETS 262 0.00% 0.00% +system.ruby.Directory_Controller.I.Memory_Ack 77 0.00% 0.00% +system.ruby.Directory_Controller.S.GETX 40 0.00% 0.00% +system.ruby.Directory_Controller.S.GETS 123 0.00% 0.00% +system.ruby.Directory_Controller.M.PUTX 78 0.00% 0.00% +system.ruby.Directory_Controller.IS.Unblock 262 0.00% 0.00% +system.ruby.Directory_Controller.IS.Memory_Data 262 0.00% 0.00% +system.ruby.Directory_Controller.SS.Last_Unblock 122 0.00% 0.00% +system.ruby.Directory_Controller.SS.Memory_Data 123 0.00% 0.00% +system.ruby.Directory_Controller.MM.Exclusive_Unblock 80 0.00% 0.00% +system.ruby.Directory_Controller.MM.Memory_Data 80 0.00% 0.00% +system.ruby.Directory_Controller.MM.Memory_Ack 1 0.00% 0.00% +system.ruby.Directory_Controller.MI.Dirty_Writeback 78 0.00% 0.00% system.ruby.L1Cache_Controller.Load 415 0.00% 0.00% system.ruby.L1Cache_Controller.Ifetch 2585 0.00% 0.00% system.ruby.L1Cache_Controller.Store 294 0.00% 0.00% @@ -691,28 +719,5 @@ system.ruby.L2Cache_Controller.MM.Exclusive_Unblock 12 0.00% system.ruby.L2Cache_Controller.SS.Unblock 51 0.00% 0.00% system.ruby.L2Cache_Controller.OO.Exclusive_Unblock 16 0.00% 0.00% system.ruby.L2Cache_Controller.MI.Writeback_Ack 78 0.00% 0.00% -system.ruby.Directory_Controller.GETX 80 0.00% 0.00% -system.ruby.Directory_Controller.GETS 385 0.00% 0.00% -system.ruby.Directory_Controller.PUTX 78 0.00% 0.00% -system.ruby.Directory_Controller.Unblock 262 0.00% 0.00% -system.ruby.Directory_Controller.Last_Unblock 122 0.00% 0.00% -system.ruby.Directory_Controller.Exclusive_Unblock 80 0.00% 0.00% -system.ruby.Directory_Controller.Dirty_Writeback 78 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Data 465 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Ack 78 0.00% 0.00% -system.ruby.Directory_Controller.I.GETX 40 0.00% 0.00% -system.ruby.Directory_Controller.I.GETS 262 0.00% 0.00% -system.ruby.Directory_Controller.I.Memory_Ack 77 0.00% 0.00% -system.ruby.Directory_Controller.S.GETX 40 0.00% 0.00% -system.ruby.Directory_Controller.S.GETS 123 0.00% 0.00% -system.ruby.Directory_Controller.M.PUTX 78 0.00% 0.00% -system.ruby.Directory_Controller.IS.Unblock 262 0.00% 0.00% -system.ruby.Directory_Controller.IS.Memory_Data 262 0.00% 0.00% -system.ruby.Directory_Controller.SS.Last_Unblock 122 0.00% 0.00% -system.ruby.Directory_Controller.SS.Memory_Data 123 0.00% 0.00% -system.ruby.Directory_Controller.MM.Exclusive_Unblock 80 0.00% 0.00% -system.ruby.Directory_Controller.MM.Memory_Data 80 0.00% 0.00% -system.ruby.Directory_Controller.MM.Memory_Ack 1 0.00% 0.00% -system.ruby.Directory_Controller.MI.Dirty_Writeback 78 0.00% 0.00% ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt index 69664e25a..166a3264e 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000044 # Nu sim_ticks 43869 # Number of ticks simulated final_tick 43869 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 107 # Simulator instruction rate (inst/s) -host_op_rate 107 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1826 # Simulator tick rate (ticks/s) -host_mem_usage 435688 # Number of bytes of host memory used -host_seconds 24.02 # Real time elapsed on the host +host_inst_rate 63661 # Simulator instruction rate (inst/s) +host_op_rate 63637 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1082971 # Simulator tick rate (ticks/s) +host_mem_usage 449944 # Number of bytes of host memory used +host_seconds 0.04 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -232,29 +232,126 @@ system.mem_ctrls.readRowHitRate 78.40 # Ro system.mem_ctrls.writeRowHitRate 32.61 # Row buffer hit rate for writes system.mem_ctrls.avgGap 82.31 # Average gap between requests system.mem_ctrls.pageHitRate 73.40 # Row buffer hit rate, read and write combined -system.mem_ctrls.memoryStateTime::IDLE 22 # Time in different power states -system.mem_ctrls.memoryStateTime::REF 1300 # Time in different power states -system.mem_ctrls.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls.memoryStateTime::ACT 37882 # Time in different power states -system.mem_ctrls.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrls.actEnergy::0 158760 # Energy for activate commands per rank (pJ) -system.mem_ctrls.actEnergy::1 355320 # Energy for activate commands per rank (pJ) -system.mem_ctrls.preEnergy::0 88200 # Energy for precharge commands per rank (pJ) -system.mem_ctrls.preEnergy::1 197400 # Energy for precharge commands per rank (pJ) -system.mem_ctrls.readEnergy::0 1697280 # Energy for read commands per rank (pJ) -system.mem_ctrls.readEnergy::1 2483520 # Energy for read commands per rank (pJ) -system.mem_ctrls.writeEnergy::0 0 # Energy for write commands per rank (pJ) -system.mem_ctrls.writeEnergy::1 165888 # Energy for write commands per rank (pJ) -system.mem_ctrls.refreshEnergy::0 2542800 # Energy for refresh commands per rank (pJ) -system.mem_ctrls.refreshEnergy::1 2542800 # Energy for refresh commands per rank (pJ) -system.mem_ctrls.actBackEnergy::0 25360668 # Energy for active background per rank (pJ) -system.mem_ctrls.actBackEnergy::1 26385300 # Energy for active background per rank (pJ) -system.mem_ctrls.preBackEnergy::0 1267800 # Energy for precharge background per rank (pJ) -system.mem_ctrls.preBackEnergy::1 369000 # Energy for precharge background per rank (pJ) -system.mem_ctrls.totalEnergy::0 31115508 # Total energy per rank (pJ) -system.mem_ctrls.totalEnergy::1 32499228 # Total energy per rank (pJ) -system.mem_ctrls.averagePower::0 793.965501 # Core power per rank (mW) -system.mem_ctrls.averagePower::1 829.273488 # Core power per rank (mW) +system.mem_ctrls_0.actEnergy 158760 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 88200 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 1697280 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls_0.refreshEnergy 2542800 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_0.actBackEnergy 25360668 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 1267800 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.totalEnergy 31115508 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 793.965501 # Core power per rank (mW) +system.mem_ctrls_0.memoryStateTime::IDLE 1987 # Time in different power states +system.mem_ctrls_0.memoryStateTime::REF 1300 # Time in different power states +system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 35917 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls_1.actEnergy 355320 # Energy for activate commands per rank (pJ) +system.mem_ctrls_1.preEnergy 197400 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_1.readEnergy 2483520 # Energy for read commands per rank (pJ) +system.mem_ctrls_1.writeEnergy 165888 # Energy for write commands per rank (pJ) +system.mem_ctrls_1.refreshEnergy 2542800 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_1.actBackEnergy 26385300 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 369000 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.totalEnergy 32499228 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 829.273488 # Core power per rank (mW) +system.mem_ctrls_1.memoryStateTime::IDLE 583 # Time in different power states +system.mem_ctrls_1.memoryStateTime::REF 1300 # Time in different power states +system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 37415 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.clk_domain.clock 1 # Clock period in ticks +system.cpu.dtb.fetch_hits 0 # ITB hits +system.cpu.dtb.fetch_misses 0 # ITB misses +system.cpu.dtb.fetch_acv 0 # ITB acv +system.cpu.dtb.fetch_accesses 0 # ITB accesses +system.cpu.dtb.read_hits 415 # DTB read hits +system.cpu.dtb.read_misses 4 # DTB read misses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_accesses 419 # DTB read accesses +system.cpu.dtb.write_hits 294 # DTB write hits +system.cpu.dtb.write_misses 4 # DTB write misses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_accesses 298 # DTB write accesses +system.cpu.dtb.data_hits 709 # DTB hits +system.cpu.dtb.data_misses 8 # DTB misses +system.cpu.dtb.data_acv 0 # DTB access violations +system.cpu.dtb.data_accesses 717 # DTB accesses +system.cpu.itb.fetch_hits 2586 # ITB hits +system.cpu.itb.fetch_misses 11 # ITB misses +system.cpu.itb.fetch_acv 0 # ITB acv +system.cpu.itb.fetch_accesses 2597 # ITB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_acv 0 # DTB read access violations +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_acv 0 # DTB write access violations +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.data_hits 0 # DTB hits +system.cpu.itb.data_misses 0 # DTB misses +system.cpu.itb.data_acv 0 # DTB access violations +system.cpu.itb.data_accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 4 # Number of system calls +system.cpu.numCycles 43869 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 2577 # Number of instructions committed +system.cpu.committedOps 2577 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 2375 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 6 # Number of float alu accesses +system.cpu.num_func_calls 140 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 238 # number of instructions that are conditional controls +system.cpu.num_int_insts 2375 # number of integer instructions +system.cpu.num_fp_insts 6 # number of float instructions +system.cpu.num_int_register_reads 2998 # number of times the integer registers were read +system.cpu.num_int_register_writes 1768 # number of times the integer registers were written +system.cpu.num_fp_register_reads 6 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_mem_refs 717 # number of memory refs +system.cpu.num_load_insts 419 # Number of load instructions +system.cpu.num_store_insts 298 # Number of store instructions +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 43869 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.Branches 396 # Number of branches fetched +system.cpu.op_class::No_OpClass 189 7.31% 7.31% # Class of executed instruction +system.cpu.op_class::IntAlu 1678 64.91% 72.22% # Class of executed instruction +system.cpu.op_class::IntMult 1 0.04% 72.26% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::MemRead 419 16.21% 88.47% # Class of executed instruction +system.cpu.op_class::MemWrite 298 11.53% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 2585 # Class of executed instruction system.ruby.clk_domain.clock 1 # Clock period in ticks system.ruby.outstanding_req_hist::bucket_size 1 system.ruby.outstanding_req_hist::max_bucket 9 @@ -294,7 +391,10 @@ system.ruby.l1_cntrl0.L1Dcache.demand_accesses 709 system.ruby.l1_cntrl0.L1Icache.demand_hits 2315 # Number of cache demand hits system.ruby.l1_cntrl0.L1Icache.demand_misses 270 # Number of cache demand misses system.ruby.l1_cntrl0.L1Icache.demand_accesses 2585 # Number of cache demand accesses -system.cpu.clk_domain.clock 1 # Clock period in ticks +system.ruby.l2_cntrl0.L2cache.demand_hits 64 # Number of cache demand hits +system.ruby.l2_cntrl0.L2cache.demand_misses 454 # Number of cache demand misses +system.ruby.l2_cntrl0.L2cache.demand_accesses 518 # Number of cache demand accesses +system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks system.ruby.network.routers0.percent_links_utilized 5.531811 system.ruby.network.routers0.msg_count.Request_Control::1 518 system.ruby.network.routers0.msg_count.Response_Data::4 448 @@ -308,9 +408,6 @@ system.ruby.network.routers0.msg_bytes.ResponseL2hit_Data::4 5040 system.ruby.network.routers0.msg_bytes.Response_Control::4 8 system.ruby.network.routers0.msg_bytes.Writeback_Data::4 36144 system.ruby.network.routers0.msg_bytes.Persistent_Control::3 64 -system.ruby.l2_cntrl0.L2cache.demand_hits 64 # Number of cache demand hits -system.ruby.l2_cntrl0.L2cache.demand_misses 454 # Number of cache demand misses -system.ruby.l2_cntrl0.L2cache.demand_accesses 518 # Number of cache demand accesses system.ruby.network.routers1.percent_links_utilized 4.129340 system.ruby.network.routers1.msg_count.Request_Control::1 518 system.ruby.network.routers1.msg_count.Request_Control::2 454 @@ -368,98 +465,6 @@ system.ruby.network.msg_byte.Response_Control 24 system.ruby.network.msg_byte.Writeback_Data 126576 system.ruby.network.msg_byte.Writeback_Control 8760 system.ruby.network.msg_byte.Persistent_Control 192 -system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 415 # DTB read hits -system.cpu.dtb.read_misses 4 # DTB read misses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 419 # DTB read accesses -system.cpu.dtb.write_hits 294 # DTB write hits -system.cpu.dtb.write_misses 4 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 298 # DTB write accesses -system.cpu.dtb.data_hits 709 # DTB hits -system.cpu.dtb.data_misses 8 # DTB misses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 717 # DTB accesses -system.cpu.itb.fetch_hits 2586 # ITB hits -system.cpu.itb.fetch_misses 11 # ITB misses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 2597 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 4 # Number of system calls -system.cpu.numCycles 43869 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 2577 # Number of instructions committed -system.cpu.committedOps 2577 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 2375 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 6 # Number of float alu accesses -system.cpu.num_func_calls 140 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 238 # number of instructions that are conditional controls -system.cpu.num_int_insts 2375 # number of integer instructions -system.cpu.num_fp_insts 6 # number of float instructions -system.cpu.num_int_register_reads 2998 # number of times the integer registers were read -system.cpu.num_int_register_writes 1768 # number of times the integer registers were written -system.cpu.num_fp_register_reads 6 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 717 # number of memory refs -system.cpu.num_load_insts 419 # Number of load instructions -system.cpu.num_store_insts 298 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 43869 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.Branches 396 # Number of branches fetched -system.cpu.op_class::No_OpClass 189 7.31% 7.31% # Class of executed instruction -system.cpu.op_class::IntAlu 1678 64.91% 72.22% # Class of executed instruction -system.cpu.op_class::IntMult 1 0.04% 72.26% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::MemRead 419 16.21% 88.47% # Class of executed instruction -system.cpu.op_class::MemWrite 298 11.53% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 2585 # Class of executed instruction system.ruby.network.routers0.throttle0.link_utilization 5.319246 system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 448 system.ruby.network.routers0.throttle0.msg_count.ResponseL2hit_Data::4 70 @@ -718,6 +723,32 @@ system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 77.741160 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 34.366891 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 242 97.98% 97.98% | 0 0.00% 97.98% | 1 0.40% 98.38% | 1 0.40% 98.79% | 3 1.21% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total 247 +system.ruby.Directory_Controller.GETX 61 0.00% 0.00% +system.ruby.Directory_Controller.GETS 398 0.00% 0.00% +system.ruby.Directory_Controller.Lockdown 2 0.00% 0.00% +system.ruby.Directory_Controller.Unlockdown 2 0.00% 0.00% +system.ruby.Directory_Controller.Data_Owner 3 0.00% 0.00% +system.ruby.Directory_Controller.Data_All_Tokens 81 0.00% 0.00% +system.ruby.Directory_Controller.Ack_Owner 16 0.00% 0.00% +system.ruby.Directory_Controller.Ack_Owner_All_Tokens 334 0.00% 0.00% +system.ruby.Directory_Controller.Ack_All_Tokens 15 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Data 448 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Ack 84 0.00% 0.00% +system.ruby.Directory_Controller.O.GETX 52 0.00% 0.00% +system.ruby.Directory_Controller.O.GETS 396 0.00% 0.00% +system.ruby.Directory_Controller.O.Ack_All_Tokens 15 0.00% 0.00% +system.ruby.Directory_Controller.NO.GETX 6 0.00% 0.00% +system.ruby.Directory_Controller.NO.Data_Owner 3 0.00% 0.00% +system.ruby.Directory_Controller.NO.Data_All_Tokens 81 0.00% 0.00% +system.ruby.Directory_Controller.NO.Ack_Owner 16 0.00% 0.00% +system.ruby.Directory_Controller.NO.Ack_Owner_All_Tokens 334 0.00% 0.00% +system.ruby.Directory_Controller.L.Unlockdown 2 0.00% 0.00% +system.ruby.Directory_Controller.O_W.GETX 3 0.00% 0.00% +system.ruby.Directory_Controller.O_W.GETS 2 0.00% 0.00% +system.ruby.Directory_Controller.O_W.Memory_Ack 84 0.00% 0.00% +system.ruby.Directory_Controller.L_NO_W.Memory_Data 2 0.00% 0.00% +system.ruby.Directory_Controller.NO_W.Lockdown 2 0.00% 0.00% +system.ruby.Directory_Controller.NO_W.Memory_Data 446 0.00% 0.00% system.ruby.L1Cache_Controller.Load 415 0.00% 0.00% system.ruby.L1Cache_Controller.Ifetch 2585 0.00% 0.00% system.ruby.L1Cache_Controller.Store 294 0.00% 0.00% @@ -786,31 +817,5 @@ system.ruby.L2Cache_Controller.M.L1_GETS 52 0.00% 0.00% system.ruby.L2Cache_Controller.M.L1_GETX 8 0.00% 0.00% system.ruby.L2Cache_Controller.M.L2_Replacement 415 0.00% 0.00% system.ruby.L2Cache_Controller.I_L.Persistent_GETS 2 0.00% 0.00% -system.ruby.Directory_Controller.GETX 61 0.00% 0.00% -system.ruby.Directory_Controller.GETS 398 0.00% 0.00% -system.ruby.Directory_Controller.Lockdown 2 0.00% 0.00% -system.ruby.Directory_Controller.Unlockdown 2 0.00% 0.00% -system.ruby.Directory_Controller.Data_Owner 3 0.00% 0.00% -system.ruby.Directory_Controller.Data_All_Tokens 81 0.00% 0.00% -system.ruby.Directory_Controller.Ack_Owner 16 0.00% 0.00% -system.ruby.Directory_Controller.Ack_Owner_All_Tokens 334 0.00% 0.00% -system.ruby.Directory_Controller.Ack_All_Tokens 15 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Data 448 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Ack 84 0.00% 0.00% -system.ruby.Directory_Controller.O.GETX 52 0.00% 0.00% -system.ruby.Directory_Controller.O.GETS 396 0.00% 0.00% -system.ruby.Directory_Controller.O.Ack_All_Tokens 15 0.00% 0.00% -system.ruby.Directory_Controller.NO.GETX 6 0.00% 0.00% -system.ruby.Directory_Controller.NO.Data_Owner 3 0.00% 0.00% -system.ruby.Directory_Controller.NO.Data_All_Tokens 81 0.00% 0.00% -system.ruby.Directory_Controller.NO.Ack_Owner 16 0.00% 0.00% -system.ruby.Directory_Controller.NO.Ack_Owner_All_Tokens 334 0.00% 0.00% -system.ruby.Directory_Controller.L.Unlockdown 2 0.00% 0.00% -system.ruby.Directory_Controller.O_W.GETX 3 0.00% 0.00% -system.ruby.Directory_Controller.O_W.GETS 2 0.00% 0.00% -system.ruby.Directory_Controller.O_W.Memory_Ack 84 0.00% 0.00% -system.ruby.Directory_Controller.L_NO_W.Memory_Data 2 0.00% 0.00% -system.ruby.Directory_Controller.NO_W.Lockdown 2 0.00% 0.00% -system.ruby.Directory_Controller.NO_W.Memory_Data 446 0.00% 0.00% ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt index 391ee4c59..2c1a5d0e0 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000036 # Nu sim_ticks 36255 # Number of ticks simulated final_tick 36255 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 16369 # Simulator instruction rate (inst/s) -host_op_rate 16367 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 230240 # Simulator tick rate (ticks/s) -host_mem_usage 435584 # Number of bytes of host memory used -host_seconds 0.16 # Real time elapsed on the host +host_inst_rate 60442 # Simulator instruction rate (inst/s) +host_op_rate 60421 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 849780 # Simulator tick rate (ticks/s) +host_mem_usage 449324 # Number of bytes of host memory used +host_seconds 0.04 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -232,29 +232,126 @@ system.mem_ctrls.readRowHitRate 80.27 # Ro system.mem_ctrls.writeRowHitRate 32.61 # Row buffer hit rate for writes system.mem_ctrls.avgGap 69.32 # Average gap between requests system.mem_ctrls.pageHitRate 75.06 # Row buffer hit rate, read and write combined -system.mem_ctrls.memoryStateTime::IDLE 11 # Time in different power states -system.mem_ctrls.memoryStateTime::REF 1040 # Time in different power states -system.mem_ctrls.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls.memoryStateTime::ACT 30367 # Time in different power states -system.mem_ctrls.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrls.actEnergy::0 143640 # Energy for activate commands per rank (pJ) -system.mem_ctrls.actEnergy::1 309960 # Energy for activate commands per rank (pJ) -system.mem_ctrls.preEnergy::0 79800 # Energy for precharge commands per rank (pJ) -system.mem_ctrls.preEnergy::1 172200 # Energy for precharge commands per rank (pJ) -system.mem_ctrls.readEnergy::0 1634880 # Energy for read commands per rank (pJ) -system.mem_ctrls.readEnergy::1 2446080 # Energy for read commands per rank (pJ) -system.mem_ctrls.writeEnergy::0 0 # Energy for write commands per rank (pJ) -system.mem_ctrls.writeEnergy::1 165888 # Energy for write commands per rank (pJ) -system.mem_ctrls.refreshEnergy::0 2034240 # Energy for refresh commands per rank (pJ) -system.mem_ctrls.refreshEnergy::1 2034240 # Energy for refresh commands per rank (pJ) -system.mem_ctrls.actBackEnergy::0 20833956 # Energy for active background per rank (pJ) -system.mem_ctrls.actBackEnergy::1 21069936 # Energy for active background per rank (pJ) -system.mem_ctrls.preBackEnergy::0 567000 # Energy for precharge background per rank (pJ) -system.mem_ctrls.preBackEnergy::1 360000 # Energy for precharge background per rank (pJ) -system.mem_ctrls.totalEnergy::0 25293516 # Total energy per rank (pJ) -system.mem_ctrls.totalEnergy::1 26558304 # Total energy per rank (pJ) -system.mem_ctrls.averagePower::0 805.423386 # Core power per rank (mW) -system.mem_ctrls.averagePower::1 845.698128 # Core power per rank (mW) +system.mem_ctrls_0.actEnergy 143640 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 79800 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 1634880 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls_0.refreshEnergy 2034240 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_0.actBackEnergy 20833956 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 567000 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.totalEnergy 25293516 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 805.423386 # Core power per rank (mW) +system.mem_ctrls_0.memoryStateTime::IDLE 847 # Time in different power states +system.mem_ctrls_0.memoryStateTime::REF 1040 # Time in different power states +system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 29531 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls_1.actEnergy 309960 # Energy for activate commands per rank (pJ) +system.mem_ctrls_1.preEnergy 172200 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_1.readEnergy 2446080 # Energy for read commands per rank (pJ) +system.mem_ctrls_1.writeEnergy 165888 # Energy for write commands per rank (pJ) +system.mem_ctrls_1.refreshEnergy 2034240 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_1.actBackEnergy 21069936 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 360000 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.totalEnergy 26558304 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 845.698128 # Core power per rank (mW) +system.mem_ctrls_1.memoryStateTime::IDLE 1450 # Time in different power states +system.mem_ctrls_1.memoryStateTime::REF 1040 # Time in different power states +system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 29876 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.clk_domain.clock 1 # Clock period in ticks +system.cpu.dtb.fetch_hits 0 # ITB hits +system.cpu.dtb.fetch_misses 0 # ITB misses +system.cpu.dtb.fetch_acv 0 # ITB acv +system.cpu.dtb.fetch_accesses 0 # ITB accesses +system.cpu.dtb.read_hits 415 # DTB read hits +system.cpu.dtb.read_misses 4 # DTB read misses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_accesses 419 # DTB read accesses +system.cpu.dtb.write_hits 294 # DTB write hits +system.cpu.dtb.write_misses 4 # DTB write misses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_accesses 298 # DTB write accesses +system.cpu.dtb.data_hits 709 # DTB hits +system.cpu.dtb.data_misses 8 # DTB misses +system.cpu.dtb.data_acv 0 # DTB access violations +system.cpu.dtb.data_accesses 717 # DTB accesses +system.cpu.itb.fetch_hits 2586 # ITB hits +system.cpu.itb.fetch_misses 11 # ITB misses +system.cpu.itb.fetch_acv 0 # ITB acv +system.cpu.itb.fetch_accesses 2597 # ITB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_acv 0 # DTB read access violations +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_acv 0 # DTB write access violations +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.data_hits 0 # DTB hits +system.cpu.itb.data_misses 0 # DTB misses +system.cpu.itb.data_acv 0 # DTB access violations +system.cpu.itb.data_accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 4 # Number of system calls +system.cpu.numCycles 36255 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 2577 # Number of instructions committed +system.cpu.committedOps 2577 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 2375 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 6 # Number of float alu accesses +system.cpu.num_func_calls 140 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 238 # number of instructions that are conditional controls +system.cpu.num_int_insts 2375 # number of integer instructions +system.cpu.num_fp_insts 6 # number of float instructions +system.cpu.num_int_register_reads 2998 # number of times the integer registers were read +system.cpu.num_int_register_writes 1768 # number of times the integer registers were written +system.cpu.num_fp_register_reads 6 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_mem_refs 717 # number of memory refs +system.cpu.num_load_insts 419 # Number of load instructions +system.cpu.num_store_insts 298 # Number of store instructions +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 36255 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.Branches 396 # Number of branches fetched +system.cpu.op_class::No_OpClass 189 7.31% 7.31% # Class of executed instruction +system.cpu.op_class::IntAlu 1678 64.91% 72.22% # Class of executed instruction +system.cpu.op_class::IntMult 1 0.04% 72.26% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 72.26% # Class of executed instruction +system.cpu.op_class::MemRead 419 16.21% 88.47% # Class of executed instruction +system.cpu.op_class::MemWrite 298 11.53% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 2585 # Class of executed instruction system.ruby.clk_domain.clock 1 # Clock period in ticks system.ruby.outstanding_req_hist::bucket_size 1 system.ruby.outstanding_req_hist::max_bucket 9 @@ -288,7 +385,9 @@ system.ruby.miss_latency_hist::stdev 26.697338 system.ruby.miss_latency_hist | 59 13.38% 13.38% | 290 65.76% 79.14% | 87 19.73% 98.87% | 1 0.23% 99.09% | 0 0.00% 99.09% | 0 0.00% 99.09% | 0 0.00% 99.09% | 0 0.00% 99.09% | 1 0.23% 99.32% | 3 0.68% 100.00% system.ruby.miss_latency_hist::total 441 system.ruby.Directory.incomplete_times 440 -system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks +system.ruby.dir_cntrl0.probeFilter.demand_hits 0 # Number of cache demand hits +system.ruby.dir_cntrl0.probeFilter.demand_misses 0 # Number of cache demand misses +system.ruby.dir_cntrl0.probeFilter.demand_accesses 0 # Number of cache demand accesses system.ruby.l1_cntrl0.L1Dcache.demand_hits 469 # Number of cache demand hits system.ruby.l1_cntrl0.L1Dcache.demand_misses 240 # Number of cache demand misses system.ruby.l1_cntrl0.L1Dcache.demand_accesses 709 # Number of cache demand accesses @@ -298,7 +397,7 @@ system.ruby.l1_cntrl0.L1Icache.demand_accesses 2585 system.ruby.l1_cntrl0.L2cache.demand_hits 69 # Number of cache demand hits system.ruby.l1_cntrl0.L2cache.demand_misses 441 # Number of cache demand misses system.ruby.l1_cntrl0.L2cache.demand_accesses 510 # Number of cache demand accesses -system.cpu.clk_domain.clock 1 # Clock period in ticks +system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks system.ruby.network.routers0.percent_links_utilized 4.670390 system.ruby.network.routers0.msg_count.Request_Control::2 441 system.ruby.network.routers0.msg_count.Response_Data::4 441 @@ -314,9 +413,6 @@ system.ruby.network.routers0.msg_bytes.Writeback_Control::2 3400 system.ruby.network.routers0.msg_bytes.Writeback_Control::3 3400 system.ruby.network.routers0.msg_bytes.Writeback_Control::5 2752 system.ruby.network.routers0.msg_bytes.Unblock_Control::5 3520 -system.ruby.dir_cntrl0.probeFilter.demand_hits 0 # Number of cache demand hits -system.ruby.dir_cntrl0.probeFilter.demand_misses 0 # Number of cache demand misses -system.ruby.dir_cntrl0.probeFilter.demand_accesses 0 # Number of cache demand accesses system.ruby.network.routers1.percent_links_utilized 4.670390 system.ruby.network.routers1.msg_count.Request_Control::2 441 system.ruby.network.routers1.msg_count.Response_Data::4 441 @@ -357,97 +453,6 @@ system.ruby.network.msg_byte.Response_Data 95256 system.ruby.network.msg_byte.Writeback_Data 17496 system.ruby.network.msg_byte.Writeback_Control 28656 system.ruby.network.msg_byte.Unblock_Control 10560 -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 415 # DTB read hits -system.cpu.dtb.read_misses 4 # DTB read misses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 419 # DTB read accesses -system.cpu.dtb.write_hits 294 # DTB write hits -system.cpu.dtb.write_misses 4 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 298 # DTB write accesses -system.cpu.dtb.data_hits 709 # DTB hits -system.cpu.dtb.data_misses 8 # DTB misses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 717 # DTB accesses -system.cpu.itb.fetch_hits 2586 # ITB hits -system.cpu.itb.fetch_misses 11 # ITB misses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 2597 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 4 # Number of system calls -system.cpu.numCycles 36255 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 2577 # Number of instructions committed -system.cpu.committedOps 2577 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 2375 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 6 # Number of float alu accesses -system.cpu.num_func_calls 140 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 238 # number of instructions that are conditional controls -system.cpu.num_int_insts 2375 # number of integer instructions -system.cpu.num_fp_insts 6 # number of float instructions -system.cpu.num_int_register_reads 2998 # number of times the integer registers were read -system.cpu.num_int_register_writes 1768 # number of times the integer registers were written -system.cpu.num_fp_register_reads 6 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 717 # number of memory refs -system.cpu.num_load_insts 419 # Number of load instructions -system.cpu.num_store_insts 298 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 36255 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.Branches 396 # Number of branches fetched -system.cpu.op_class::No_OpClass 189 7.31% 7.31% # Class of executed instruction -system.cpu.op_class::IntAlu 1678 64.91% 72.22% # Class of executed instruction -system.cpu.op_class::IntMult 1 0.04% 72.26% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::MemRead 419 16.21% 88.47% # Class of executed instruction -system.cpu.op_class::MemWrite 298 11.53% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 2585 # Class of executed instruction system.ruby.network.routers0.throttle0.link_utilization 6.059854 system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 441 system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 425 @@ -682,6 +687,25 @@ system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 62.229629 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 23.299188 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 199 80.24% 80.24% | 46 18.55% 98.79% | 1 0.40% 99.19% | 0 0.00% 99.19% | 0 0.00% 99.19% | 0 0.00% 99.19% | 0 0.00% 99.19% | 0 0.00% 99.19% | 2 0.81% 100.00% system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total 248 +system.ruby.Directory_Controller.GETX 51 0.00% 0.00% +system.ruby.Directory_Controller.GETS 409 0.00% 0.00% +system.ruby.Directory_Controller.PUT 425 0.00% 0.00% +system.ruby.Directory_Controller.UnblockM 440 0.00% 0.00% +system.ruby.Directory_Controller.Writeback_Exclusive_Clean 344 0.00% 0.00% +system.ruby.Directory_Controller.Writeback_Exclusive_Dirty 81 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Data 441 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Ack 81 0.00% 0.00% +system.ruby.Directory_Controller.NO.PUT 425 0.00% 0.00% +system.ruby.Directory_Controller.E.GETX 47 0.00% 0.00% +system.ruby.Directory_Controller.E.GETS 394 0.00% 0.00% +system.ruby.Directory_Controller.NO_B.UnblockM 440 0.00% 0.00% +system.ruby.Directory_Controller.NO_B_W.Memory_Data 441 0.00% 0.00% +system.ruby.Directory_Controller.WB.GETX 4 0.00% 0.00% +system.ruby.Directory_Controller.WB.GETS 14 0.00% 0.00% +system.ruby.Directory_Controller.WB.Writeback_Exclusive_Clean 344 0.00% 0.00% +system.ruby.Directory_Controller.WB.Writeback_Exclusive_Dirty 81 0.00% 0.00% +system.ruby.Directory_Controller.WB_E_W.GETS 1 0.00% 0.00% +system.ruby.Directory_Controller.WB_E_W.Memory_Ack 81 0.00% 0.00% system.ruby.L1Cache_Controller.Load 422 0.00% 0.00% system.ruby.L1Cache_Controller.Ifetch 2591 0.00% 0.00% system.ruby.L1Cache_Controller.Store 298 0.00% 0.00% @@ -723,24 +747,5 @@ system.ruby.L1Cache_Controller.MI.Store 4 0.00% 0.00% system.ruby.L1Cache_Controller.MI.Writeback_Ack 425 0.00% 0.00% system.ruby.L1Cache_Controller.MT.Complete_L2_to_L1 45 0.00% 0.00% system.ruby.L1Cache_Controller.MMT.Complete_L2_to_L1 24 0.00% 0.00% -system.ruby.Directory_Controller.GETX 51 0.00% 0.00% -system.ruby.Directory_Controller.GETS 409 0.00% 0.00% -system.ruby.Directory_Controller.PUT 425 0.00% 0.00% -system.ruby.Directory_Controller.UnblockM 440 0.00% 0.00% -system.ruby.Directory_Controller.Writeback_Exclusive_Clean 344 0.00% 0.00% -system.ruby.Directory_Controller.Writeback_Exclusive_Dirty 81 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Data 441 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Ack 81 0.00% 0.00% -system.ruby.Directory_Controller.NO.PUT 425 0.00% 0.00% -system.ruby.Directory_Controller.E.GETX 47 0.00% 0.00% -system.ruby.Directory_Controller.E.GETS 394 0.00% 0.00% -system.ruby.Directory_Controller.NO_B.UnblockM 440 0.00% 0.00% -system.ruby.Directory_Controller.NO_B_W.Memory_Data 441 0.00% 0.00% -system.ruby.Directory_Controller.WB.GETX 4 0.00% 0.00% -system.ruby.Directory_Controller.WB.GETS 14 0.00% 0.00% -system.ruby.Directory_Controller.WB.Writeback_Exclusive_Clean 344 0.00% 0.00% -system.ruby.Directory_Controller.WB.Writeback_Exclusive_Dirty 81 0.00% 0.00% -system.ruby.Directory_Controller.WB_E_W.GETS 1 0.00% 0.00% -system.ruby.Directory_Controller.WB_E_W.Memory_Ack 81 0.00% 0.00% ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt index 58855671d..19e3fb417 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000048 # Nu sim_ticks 47840 # Number of ticks simulated final_tick 47840 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 31483 # Simulator instruction rate (inst/s) -host_op_rate 31473 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 584131 # Simulator tick rate (ticks/s) -host_mem_usage 435420 # Number of bytes of host memory used -host_seconds 0.08 # Real time elapsed on the host +host_inst_rate 35814 # Simulator instruction rate (inst/s) +host_op_rate 35808 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 664620 # Simulator tick rate (ticks/s) +host_mem_usage 449364 # Number of bytes of host memory used +host_seconds 0.07 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -238,106 +238,35 @@ system.mem_ctrls.readRowHitRate 74.87 # Ro system.mem_ctrls.writeRowHitRate 87.91 # Row buffer hit rate for writes system.mem_ctrls.avgGap 38.30 # Average gap between requests system.mem_ctrls.pageHitRate 81.48 # Row buffer hit rate, read and write combined -system.mem_ctrls.memoryStateTime::IDLE 140 # Time in different power states -system.mem_ctrls.memoryStateTime::REF 1560 # Time in different power states -system.mem_ctrls.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls.memoryStateTime::ACT 45290 # Time in different power states -system.mem_ctrls.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrls.actEnergy::0 249480 # Energy for activate commands per rank (pJ) -system.mem_ctrls.actEnergy::1 574560 # Energy for activate commands per rank (pJ) -system.mem_ctrls.preEnergy::0 138600 # Energy for precharge commands per rank (pJ) -system.mem_ctrls.preEnergy::1 319200 # Energy for precharge commands per rank (pJ) -system.mem_ctrls.readEnergy::0 2009280 # Energy for read commands per rank (pJ) -system.mem_ctrls.readEnergy::1 2758080 # Energy for read commands per rank (pJ) -system.mem_ctrls.writeEnergy::0 1575936 # Energy for write commands per rank (pJ) -system.mem_ctrls.writeEnergy::1 2208384 # Energy for write commands per rank (pJ) -system.mem_ctrls.refreshEnergy::0 3051360 # Energy for refresh commands per rank (pJ) -system.mem_ctrls.refreshEnergy::1 3051360 # Energy for refresh commands per rank (pJ) -system.mem_ctrls.actBackEnergy::0 30369600 # Energy for active background per rank (pJ) -system.mem_ctrls.actBackEnergy::1 31087116 # Energy for active background per rank (pJ) -system.mem_ctrls.preBackEnergy::0 1545600 # Energy for precharge background per rank (pJ) -system.mem_ctrls.preBackEnergy::1 916200 # Energy for precharge background per rank (pJ) -system.mem_ctrls.totalEnergy::0 38939856 # Total energy per rank (pJ) -system.mem_ctrls.totalEnergy::1 40914900 # Total energy per rank (pJ) -system.mem_ctrls.averagePower::0 828.930858 # Core power per rank (mW) -system.mem_ctrls.averagePower::1 870.974540 # Core power per rank (mW) -system.ruby.clk_domain.clock 1 # Clock period in ticks -system.ruby.delayHist::bucket_size 1 # delay histogram for all message -system.ruby.delayHist::max_bucket 9 # delay histogram for all message -system.ruby.delayHist::samples 1248 # delay histogram for all message -system.ruby.delayHist | 1248 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message -system.ruby.delayHist::total 1248 # delay histogram for all message -system.ruby.outstanding_req_hist::bucket_size 1 -system.ruby.outstanding_req_hist::max_bucket 9 -system.ruby.outstanding_req_hist::samples 3295 -system.ruby.outstanding_req_hist::mean 1 -system.ruby.outstanding_req_hist::gmean 1 -system.ruby.outstanding_req_hist | 0 0.00% 0.00% | 3295 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.outstanding_req_hist::total 3295 -system.ruby.latency_hist::bucket_size 64 -system.ruby.latency_hist::max_bucket 639 -system.ruby.latency_hist::samples 3294 -system.ruby.latency_hist::mean 13.523376 -system.ruby.latency_hist::gmean 5.183572 -system.ruby.latency_hist::stdev 25.409311 -system.ruby.latency_hist | 3181 96.57% 96.57% | 93 2.82% 99.39% | 16 0.49% 99.88% | 1 0.03% 99.91% | 2 0.06% 99.97% | 1 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.latency_hist::total 3294 -system.ruby.hit_latency_hist::bucket_size 1 -system.ruby.hit_latency_hist::max_bucket 9 -system.ruby.hit_latency_hist::samples 2668 -system.ruby.hit_latency_hist::mean 3 -system.ruby.hit_latency_hist::gmean 3.000000 -system.ruby.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 2668 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.hit_latency_hist::total 2668 -system.ruby.miss_latency_hist::bucket_size 64 -system.ruby.miss_latency_hist::max_bucket 639 -system.ruby.miss_latency_hist::samples 626 -system.ruby.miss_latency_hist::mean 58.373802 -system.ruby.miss_latency_hist::gmean 53.319163 -system.ruby.miss_latency_hist::stdev 30.235728 -system.ruby.miss_latency_hist | 513 81.95% 81.95% | 93 14.86% 96.81% | 16 2.56% 99.36% | 1 0.16% 99.52% | 2 0.32% 99.84% | 1 0.16% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.miss_latency_hist::total 626 -system.ruby.Directory.incomplete_times 625 -system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.ruby.l1_cntrl0.cacheMemory.demand_hits 2668 # Number of cache demand hits -system.ruby.l1_cntrl0.cacheMemory.demand_misses 626 # Number of cache demand misses -system.ruby.l1_cntrl0.cacheMemory.demand_accesses 3294 # Number of cache demand accesses +system.mem_ctrls_0.actEnergy 249480 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 138600 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 2009280 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 1575936 # Energy for write commands per rank (pJ) +system.mem_ctrls_0.refreshEnergy 3051360 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_0.actBackEnergy 30369600 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 1545600 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.totalEnergy 38939856 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 828.930858 # Core power per rank (mW) +system.mem_ctrls_0.memoryStateTime::IDLE 2928 # Time in different power states +system.mem_ctrls_0.memoryStateTime::REF 1560 # Time in different power states +system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 43008 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls_1.actEnergy 574560 # Energy for activate commands per rank (pJ) +system.mem_ctrls_1.preEnergy 319200 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_1.readEnergy 2758080 # Energy for read commands per rank (pJ) +system.mem_ctrls_1.writeEnergy 2208384 # Energy for write commands per rank (pJ) +system.mem_ctrls_1.refreshEnergy 3051360 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_1.actBackEnergy 31087116 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 916200 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.totalEnergy 40914900 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 870.974540 # Core power per rank (mW) +system.mem_ctrls_1.memoryStateTime::IDLE 1359 # Time in different power states +system.mem_ctrls_1.memoryStateTime::REF 1560 # Time in different power states +system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 44071 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.clk_domain.clock 1 # Clock period in ticks -system.ruby.network.routers0.percent_links_utilized 6.521739 -system.ruby.network.routers0.msg_count.Control::2 626 -system.ruby.network.routers0.msg_count.Data::2 622 -system.ruby.network.routers0.msg_count.Response_Data::4 626 -system.ruby.network.routers0.msg_count.Writeback_Control::3 622 -system.ruby.network.routers0.msg_bytes.Control::2 5008 -system.ruby.network.routers0.msg_bytes.Data::2 44784 -system.ruby.network.routers0.msg_bytes.Response_Data::4 45072 -system.ruby.network.routers0.msg_bytes.Writeback_Control::3 4976 -system.ruby.network.routers1.percent_links_utilized 6.521739 -system.ruby.network.routers1.msg_count.Control::2 626 -system.ruby.network.routers1.msg_count.Data::2 622 -system.ruby.network.routers1.msg_count.Response_Data::4 626 -system.ruby.network.routers1.msg_count.Writeback_Control::3 622 -system.ruby.network.routers1.msg_bytes.Control::2 5008 -system.ruby.network.routers1.msg_bytes.Data::2 44784 -system.ruby.network.routers1.msg_bytes.Response_Data::4 45072 -system.ruby.network.routers1.msg_bytes.Writeback_Control::3 4976 -system.ruby.network.routers2.percent_links_utilized 6.521739 -system.ruby.network.routers2.msg_count.Control::2 626 -system.ruby.network.routers2.msg_count.Data::2 622 -system.ruby.network.routers2.msg_count.Response_Data::4 626 -system.ruby.network.routers2.msg_count.Writeback_Control::3 622 -system.ruby.network.routers2.msg_bytes.Control::2 5008 -system.ruby.network.routers2.msg_bytes.Data::2 44784 -system.ruby.network.routers2.msg_bytes.Response_Data::4 45072 -system.ruby.network.routers2.msg_bytes.Writeback_Control::3 4976 -system.ruby.network.msg_count.Control 1878 -system.ruby.network.msg_count.Data 1866 -system.ruby.network.msg_count.Response_Data 1878 -system.ruby.network.msg_count.Writeback_Control 1866 -system.ruby.network.msg_byte.Control 15024 -system.ruby.network.msg_byte.Data 134352 -system.ruby.network.msg_byte.Response_Data 135216 -system.ruby.network.msg_byte.Writeback_Control 14928 system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -429,6 +358,82 @@ system.cpu.op_class::MemWrite 298 11.53% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 2585 # Class of executed instruction +system.ruby.clk_domain.clock 1 # Clock period in ticks +system.ruby.delayHist::bucket_size 1 # delay histogram for all message +system.ruby.delayHist::max_bucket 9 # delay histogram for all message +system.ruby.delayHist::samples 1248 # delay histogram for all message +system.ruby.delayHist | 1248 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message +system.ruby.delayHist::total 1248 # delay histogram for all message +system.ruby.outstanding_req_hist::bucket_size 1 +system.ruby.outstanding_req_hist::max_bucket 9 +system.ruby.outstanding_req_hist::samples 3295 +system.ruby.outstanding_req_hist::mean 1 +system.ruby.outstanding_req_hist::gmean 1 +system.ruby.outstanding_req_hist | 0 0.00% 0.00% | 3295 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.outstanding_req_hist::total 3295 +system.ruby.latency_hist::bucket_size 64 +system.ruby.latency_hist::max_bucket 639 +system.ruby.latency_hist::samples 3294 +system.ruby.latency_hist::mean 13.523376 +system.ruby.latency_hist::gmean 5.183572 +system.ruby.latency_hist::stdev 25.409311 +system.ruby.latency_hist | 3181 96.57% 96.57% | 93 2.82% 99.39% | 16 0.49% 99.88% | 1 0.03% 99.91% | 2 0.06% 99.97% | 1 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.latency_hist::total 3294 +system.ruby.hit_latency_hist::bucket_size 1 +system.ruby.hit_latency_hist::max_bucket 9 +system.ruby.hit_latency_hist::samples 2668 +system.ruby.hit_latency_hist::mean 3 +system.ruby.hit_latency_hist::gmean 3.000000 +system.ruby.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 2668 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.hit_latency_hist::total 2668 +system.ruby.miss_latency_hist::bucket_size 64 +system.ruby.miss_latency_hist::max_bucket 639 +system.ruby.miss_latency_hist::samples 626 +system.ruby.miss_latency_hist::mean 58.373802 +system.ruby.miss_latency_hist::gmean 53.319163 +system.ruby.miss_latency_hist::stdev 30.235728 +system.ruby.miss_latency_hist | 513 81.95% 81.95% | 93 14.86% 96.81% | 16 2.56% 99.36% | 1 0.16% 99.52% | 2 0.32% 99.84% | 1 0.16% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.miss_latency_hist::total 626 +system.ruby.Directory.incomplete_times 625 +system.ruby.l1_cntrl0.cacheMemory.demand_hits 2668 # Number of cache demand hits +system.ruby.l1_cntrl0.cacheMemory.demand_misses 626 # Number of cache demand misses +system.ruby.l1_cntrl0.cacheMemory.demand_accesses 3294 # Number of cache demand accesses +system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks +system.ruby.network.routers0.percent_links_utilized 6.521739 +system.ruby.network.routers0.msg_count.Control::2 626 +system.ruby.network.routers0.msg_count.Data::2 622 +system.ruby.network.routers0.msg_count.Response_Data::4 626 +system.ruby.network.routers0.msg_count.Writeback_Control::3 622 +system.ruby.network.routers0.msg_bytes.Control::2 5008 +system.ruby.network.routers0.msg_bytes.Data::2 44784 +system.ruby.network.routers0.msg_bytes.Response_Data::4 45072 +system.ruby.network.routers0.msg_bytes.Writeback_Control::3 4976 +system.ruby.network.routers1.percent_links_utilized 6.521739 +system.ruby.network.routers1.msg_count.Control::2 626 +system.ruby.network.routers1.msg_count.Data::2 622 +system.ruby.network.routers1.msg_count.Response_Data::4 626 +system.ruby.network.routers1.msg_count.Writeback_Control::3 622 +system.ruby.network.routers1.msg_bytes.Control::2 5008 +system.ruby.network.routers1.msg_bytes.Data::2 44784 +system.ruby.network.routers1.msg_bytes.Response_Data::4 45072 +system.ruby.network.routers1.msg_bytes.Writeback_Control::3 4976 +system.ruby.network.routers2.percent_links_utilized 6.521739 +system.ruby.network.routers2.msg_count.Control::2 626 +system.ruby.network.routers2.msg_count.Data::2 622 +system.ruby.network.routers2.msg_count.Response_Data::4 626 +system.ruby.network.routers2.msg_count.Writeback_Control::3 622 +system.ruby.network.routers2.msg_bytes.Control::2 5008 +system.ruby.network.routers2.msg_bytes.Data::2 44784 +system.ruby.network.routers2.msg_bytes.Response_Data::4 45072 +system.ruby.network.routers2.msg_bytes.Writeback_Control::3 4976 +system.ruby.network.msg_count.Control 1878 +system.ruby.network.msg_count.Data 1866 +system.ruby.network.msg_count.Response_Data 1878 +system.ruby.network.msg_count.Writeback_Control 1866 +system.ruby.network.msg_byte.Control 15024 +system.ruby.network.msg_byte.Data 134352 +system.ruby.network.msg_byte.Response_Data 135216 +system.ruby.network.msg_byte.Writeback_Control 14928 system.ruby.network.routers0.throttle0.link_utilization 6.538462 system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 626 system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 622 @@ -596,6 +601,14 @@ system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 58.999958 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 28.587258 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 234 78.79% 78.79% | 49 16.50% 95.29% | 3 1.01% 96.30% | 2 0.67% 96.97% | 7 2.36% 99.33% | 1 0.34% 99.66% | 0 0.00% 99.66% | 0 0.00% 99.66% | 1 0.34% 100.00% system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total 297 +system.ruby.Directory_Controller.GETX 626 0.00% 0.00% +system.ruby.Directory_Controller.PUTX 622 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Data 626 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Ack 622 0.00% 0.00% +system.ruby.Directory_Controller.I.GETX 626 0.00% 0.00% +system.ruby.Directory_Controller.M.PUTX 622 0.00% 0.00% +system.ruby.Directory_Controller.IM.Memory_Data 626 0.00% 0.00% +system.ruby.Directory_Controller.MI.Memory_Ack 622 0.00% 0.00% system.ruby.L1Cache_Controller.Load 415 0.00% 0.00% system.ruby.L1Cache_Controller.Ifetch 2585 0.00% 0.00% system.ruby.L1Cache_Controller.Store 294 0.00% 0.00% @@ -612,13 +625,5 @@ system.ruby.L1Cache_Controller.M.Replacement 622 0.00% 0.00% system.ruby.L1Cache_Controller.MI.Writeback_Ack 622 0.00% 0.00% system.ruby.L1Cache_Controller.IS.Data 542 0.00% 0.00% system.ruby.L1Cache_Controller.IM.Data 84 0.00% 0.00% -system.ruby.Directory_Controller.GETX 626 0.00% 0.00% -system.ruby.Directory_Controller.PUTX 622 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Data 626 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Ack 622 0.00% 0.00% -system.ruby.Directory_Controller.I.GETX 626 0.00% 0.00% -system.ruby.Directory_Controller.M.PUTX 622 0.00% 0.00% -system.ruby.Directory_Controller.IM.Memory_Data 626 0.00% 0.00% -system.ruby.Directory_Controller.MI.Memory_Ack 622 0.00% 0.00% ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt index 1f9a90b5a..58622e09f 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000028 # Nu sim_ticks 27981000 # Number of ticks simulated final_tick 27981000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 65720 # Simulator instruction rate (inst/s) -host_op_rate 76928 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 399296424 # Simulator tick rate (ticks/s) -host_mem_usage 250660 # Number of bytes of host memory used -host_seconds 0.07 # Real time elapsed on the host +host_inst_rate 95550 # Simulator instruction rate (inst/s) +host_op_rate 111835 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 580422337 # Simulator tick rate (ticks/s) +host_mem_usage 309164 # Number of bytes of host memory used +host_seconds 0.05 # Real time elapsed on the host sim_insts 4604 # Number of instructions simulated sim_ops 5390 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -217,29 +217,34 @@ system.physmem.readRowHitRate 83.14 # Ro system.physmem.writeRowHitRate nan # Row buffer hit rate for writes system.physmem.avgGap 66260.10 # Average gap between requests system.physmem.pageHitRate 83.14 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 12000 # Time in different power states -system.physmem.memoryStateTime::REF 780000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 22840500 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 294840 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 136080 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 160875 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 74250 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 2090400 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 702000 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 1525680 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 1525680 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 16099650 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 15972255 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 48750 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 160500 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 20220195 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 18570765 # Total energy per rank (pJ) -system.physmem.averagePower::0 856.107753 # Core power per rank (mW) -system.physmem.averagePower::1 786.272135 # Core power per rank (mW) +system.physmem_0.actEnergy 294840 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 160875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 2090400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 16099650 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 48750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 20220195 # Total energy per rank (pJ) +system.physmem_0.averagePower 856.107753 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 12000 # Time in different power states +system.physmem_0.memoryStateTime::REF 780000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 22840500 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 136080 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 74250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 702000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 15972255 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 160500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 18570765 # Total energy per rank (pJ) +system.physmem_1.averagePower 786.272135 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1588250 # Time in different power states +system.physmem_1.memoryStateTime::REF 780000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 22654750 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.branchPred.lookups 1926 # Number of BP lookups system.cpu.branchPred.condPredicted 1154 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 341 # Number of conditional branches incorrect @@ -250,6 +255,14 @@ system.cpu.branchPred.BTBHitPct 20.426065 # BT system.cpu.branchPred.usedRAS 222 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 16 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -271,6 +284,14 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -292,6 +313,14 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -313,6 +342,14 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt index 62f6dcd2b..bac015830 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000016 # Nu sim_ticks 16223000 # Number of ticks simulated final_tick 16223000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 26356 # Simulator instruction rate (inst/s) -host_op_rate 30865 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 93111675 # Simulator tick rate (ticks/s) -host_mem_usage 251576 # Number of bytes of host memory used -host_seconds 0.17 # Real time elapsed on the host +host_inst_rate 54860 # Simulator instruction rate (inst/s) +host_op_rate 64243 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 193800024 # Simulator tick rate (ticks/s) +host_mem_usage 308908 # Number of bytes of host memory used +host_seconds 0.08 # Real time elapsed on the host sim_insts 4591 # Number of instructions simulated sim_ops 5377 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -221,53 +221,34 @@ system.physmem.readRowHitRate 83.38 # Ro system.physmem.writeRowHitRate nan # Row buffer hit rate for writes system.physmem.avgGap 40695.21 # Average gap between requests system.physmem.pageHitRate 83.38 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 11000 # Time in different power states -system.physmem.memoryStateTime::REF 520000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 15315250 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 317520 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 151200 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 173250 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 82500 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 2238600 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 795600 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 1017120 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 1017120 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 10793520 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 10477170 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 31500 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 309000 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 14571510 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 12832590 # Total energy per rank (pJ) -system.physmem.averagePower::0 920.354334 # Core power per rank (mW) -system.physmem.averagePower::1 810.522027 # Core power per rank (mW) -system.membus.trans_dist::ReadReq 355 # Transaction distribution -system.membus.trans_dist::ReadResp 355 # Transaction distribution -system.membus.trans_dist::ReadExReq 42 # Transaction distribution -system.membus.trans_dist::ReadExResp 42 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 794 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 794 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 25408 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 25408 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 397 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 397 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 397 # Request fanout histogram -system.membus.reqLayer0.occupancy 494500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 3.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 3699500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 22.8 # Layer utilization (%) -system.cpu_clk_domain.clock 500 # Clock period in ticks +system.physmem_0.actEnergy 317520 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 173250 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 2238600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 10793520 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 31500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 14571510 # Total energy per rank (pJ) +system.physmem_0.averagePower 920.354334 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 11000 # Time in different power states +system.physmem_0.memoryStateTime::REF 520000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 15315250 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 151200 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 82500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 795600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 10477170 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 309000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 12832590 # Total energy per rank (pJ) +system.physmem_1.averagePower 810.522027 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 784250 # Time in different power states +system.physmem_1.memoryStateTime::REF 520000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 14853250 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.branchPred.lookups 2638 # Number of BP lookups system.cpu.branchPred.condPredicted 1635 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 480 # Number of conditional branches incorrect @@ -277,6 +258,15 @@ system.cpu.branchPred.BTBCorrect 0 # Nu system.cpu.branchPred.BTBHitPct 37.267968 # BTB Hit Percentage system.cpu.branchPred.usedRAS 354 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 68 # Number of incorrect RAS predictions. +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.checker.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.checker.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.checker.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -298,6 +288,14 @@ system.cpu.checker.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.checker.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.checker.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.checker.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.checker.dtb.walker.walks 0 # Table walker walks requested +system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.checker.dtb.inst_hits 0 # ITB inst hits system.cpu.checker.dtb.inst_misses 0 # ITB inst misses system.cpu.checker.dtb.read_hits 0 # DTB read hits @@ -319,6 +317,14 @@ system.cpu.checker.dtb.inst_accesses 0 # IT system.cpu.checker.dtb.hits 0 # DTB hits system.cpu.checker.dtb.misses 0 # DTB misses system.cpu.checker.dtb.accesses 0 # DTB accesses +system.cpu.checker.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.checker.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.checker.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.checker.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -340,6 +346,14 @@ system.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.checker.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.checker.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.checker.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.checker.itb.walker.walks 0 # Table walker walks requested +system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.checker.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.checker.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.checker.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.checker.itb.inst_hits 0 # ITB inst hits system.cpu.checker.itb.inst_misses 0 # ITB inst misses system.cpu.checker.itb.read_hits 0 # DTB read hits @@ -365,6 +379,14 @@ system.cpu.workload.num_syscalls 13 # Nu system.cpu.checker.numCycles 5390 # number of cpu cycles simulated system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -386,6 +408,14 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -407,6 +437,14 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -428,6 +466,14 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -744,42 +790,136 @@ system.cpu.cc_regfile_reads 28734 # nu system.cpu.cc_regfile_writes 3302 # number of cc regfile writes system.cpu.misc_regfile_reads 3189 # number of misc regfile reads system.cpu.misc_regfile_writes 24 # number of misc regfile writes -system.cpu.toL2Bus.trans_dist::ReadReq 399 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 398 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 42 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 42 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 588 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 293 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 881 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18816 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 28160 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 441 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 9 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::7 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::8 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::9 441 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::10 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 9 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 9 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 441 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 220500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.4 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 488250 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 3.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 228495 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%) +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 87.114563 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 2168 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 14.849315 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 87.114563 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.021268 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.021268 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 67 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 79 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.035645 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 5528 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 5528 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 1551 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1551 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 595 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 595 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 2146 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2146 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2146 # number of overall hits +system.cpu.dcache.overall_hits::total 2146 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 203 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 203 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 318 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 318 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 521 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 521 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 521 # number of overall misses +system.cpu.dcache.overall_misses::total 521 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11353493 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11353493 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 20745500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 20745500 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 130500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 130500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 32098993 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 32098993 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 32098993 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 32098993 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1754 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1754 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 13 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 13 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 2667 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2667 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2667 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2667 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.115735 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.115735 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.348302 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.348302 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.153846 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.153846 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.195351 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.195351 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.195351 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.195351 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55928.536946 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 55928.536946 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65237.421384 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 65237.421384 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 65250 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 65250 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 61610.351248 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 61610.351248 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 61610.351248 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 61610.351248 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 105 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 4 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 26.250000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 98 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 98 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 276 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 276 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 374 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 374 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 374 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 374 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 105 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 105 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 42 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 42 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 147 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6247255 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6247255 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3144750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3144750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9392005 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9392005 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9392005 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 9392005 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.059863 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.059863 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046002 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046002 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.055118 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.055118 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.055118 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.055118 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 59497.666667 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 59497.666667 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74875 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74875 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 63891.190476 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 63891.190476 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 63891.190476 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 63891.190476 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 1 # number of replacements system.cpu.icache.tags.tagsinuse 150.722255 # Cycle average of tags in use system.cpu.icache.tags.total_refs 1666 # Total number of references to valid blocks. @@ -1010,135 +1150,64 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57439.090909 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60059.426230 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58244.332494 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 87.114563 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 2168 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 14.849315 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 87.114563 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.021268 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.021268 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 67 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 79 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.035645 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 5528 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 5528 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 1551 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1551 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 595 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 595 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 2146 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2146 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2146 # number of overall hits -system.cpu.dcache.overall_hits::total 2146 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 203 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 203 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 318 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 318 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 521 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 521 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 521 # number of overall misses -system.cpu.dcache.overall_misses::total 521 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11353493 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11353493 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 20745500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 20745500 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 130500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 130500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 32098993 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 32098993 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 32098993 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 32098993 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1754 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1754 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 13 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 13 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2667 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2667 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2667 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2667 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.115735 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.115735 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.348302 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.348302 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.153846 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.153846 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.195351 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.195351 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.195351 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.195351 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55928.536946 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 55928.536946 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65237.421384 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 65237.421384 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 65250 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 65250 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 61610.351248 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 61610.351248 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 61610.351248 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 61610.351248 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 105 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 4 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 26.250000 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 98 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 98 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 276 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 276 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 374 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 374 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 374 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 374 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 105 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 105 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 42 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 42 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 147 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6247255 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6247255 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3144750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3144750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9392005 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 9392005 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9392005 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 9392005 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.059863 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.059863 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046002 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046002 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.055118 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.055118 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.055118 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.055118 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 59497.666667 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 59497.666667 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74875 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74875 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 63891.190476 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 63891.190476 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 63891.190476 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 63891.190476 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.trans_dist::ReadReq 399 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 398 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 42 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 42 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 588 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 293 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 881 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18816 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 28160 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 441 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 9 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::7 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::8 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::9 441 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::10 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 9 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 9 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 441 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 220500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 1.4 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 488250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 3.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 228495 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%) +system.membus.trans_dist::ReadReq 355 # Transaction distribution +system.membus.trans_dist::ReadResp 355 # Transaction distribution +system.membus.trans_dist::ReadExReq 42 # Transaction distribution +system.membus.trans_dist::ReadExResp 42 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 794 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 794 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 25408 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 25408 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 397 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 397 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 397 # Request fanout histogram +system.membus.reqLayer0.occupancy 494500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 3.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 3699500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 22.8 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt index 6fc5d6de3..9157ec7b3 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt @@ -1,66 +1,66 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000012 # Number of seconds simulated -sim_ticks 11859500 # Number of ticks simulated -final_tick 11859500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000016 # Number of seconds simulated +sim_ticks 16487000 # Number of ticks simulated +final_tick 16487000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 34923 # Simulator instruction rate (inst/s) -host_op_rate 40896 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 90188816 # Simulator tick rate (ticks/s) -host_mem_usage 248256 # Number of bytes of host memory used -host_seconds 0.13 # Real time elapsed on the host +host_inst_rate 33036 # Simulator instruction rate (inst/s) +host_op_rate 38686 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 118603969 # Simulator tick rate (ticks/s) +host_mem_usage 248576 # Number of bytes of host memory used +host_seconds 0.14 # Real time elapsed on the host sim_insts 4591 # Number of instructions simulated sim_ops 5377 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 3776 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 5888 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 37184 # Number of bytes read from this memory -system.physmem.bytes_read::total 46848 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 3776 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 3776 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 59 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 92 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 581 # Number of read requests responded to by this memory -system.physmem.num_reads::total 732 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 318394536 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 496479615 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 3135376702 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3950250854 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 318394536 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 318394536 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 318394536 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 496479615 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 3135376702 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3950250854 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 733 # Number of read requests accepted +system.physmem.bytes_read::cpu.inst 17408 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 6912 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 1728 # Number of bytes read from this memory +system.physmem.bytes_read::total 26048 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 17408 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 17408 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 272 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 108 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 27 # Number of read requests responded to by this memory +system.physmem.num_reads::total 407 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1055862194 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 419239401 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 104809850 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1579911445 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1055862194 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1055862194 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1055862194 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 419239401 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 104809850 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1579911445 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 408 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 733 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 408 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 46912 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 26112 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 46912 # Total read bytes from the system interface side +system.physmem.bytesReadSys 26112 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 143 # Per bank write bursts -system.physmem.perBankRdBursts::1 90 # Per bank write bursts -system.physmem.perBankRdBursts::2 40 # Per bank write bursts -system.physmem.perBankRdBursts::3 73 # Per bank write bursts -system.physmem.perBankRdBursts::4 58 # Per bank write bursts -system.physmem.perBankRdBursts::5 88 # Per bank write bursts -system.physmem.perBankRdBursts::6 52 # Per bank write bursts -system.physmem.perBankRdBursts::7 18 # Per bank write bursts -system.physmem.perBankRdBursts::8 12 # Per bank write bursts -system.physmem.perBankRdBursts::9 28 # Per bank write bursts -system.physmem.perBankRdBursts::10 34 # Per bank write bursts +system.physmem.perBankRdBursts::0 88 # Per bank write bursts +system.physmem.perBankRdBursts::1 45 # Per bank write bursts +system.physmem.perBankRdBursts::2 19 # Per bank write bursts +system.physmem.perBankRdBursts::3 45 # Per bank write bursts +system.physmem.perBankRdBursts::4 18 # Per bank write bursts +system.physmem.perBankRdBursts::5 32 # Per bank write bursts +system.physmem.perBankRdBursts::6 37 # Per bank write bursts +system.physmem.perBankRdBursts::7 10 # Per bank write bursts +system.physmem.perBankRdBursts::8 4 # Per bank write bursts +system.physmem.perBankRdBursts::9 7 # Per bank write bursts +system.physmem.perBankRdBursts::10 26 # Per bank write bursts system.physmem.perBankRdBursts::11 47 # Per bank write bursts system.physmem.perBankRdBursts::12 17 # Per bank write bursts -system.physmem.perBankRdBursts::13 19 # Per bank write bursts +system.physmem.perBankRdBursts::13 7 # Per bank write bursts system.physmem.perBankRdBursts::14 0 # Per bank write bursts -system.physmem.perBankRdBursts::15 14 # Per bank write bursts +system.physmem.perBankRdBursts::15 6 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts system.physmem.perBankWrBursts::2 0 # Per bank write bursts @@ -79,14 +79,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 11846500 # Total gap between requests +system.physmem.totGap 16473500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 733 # Read request sizes (log2) +system.physmem.readPktSize::6 408 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -94,22 +94,22 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 96 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 114 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 83 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 79 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 68 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 60 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 51 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 53 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 48 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 26 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 17 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 18 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 6 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 8 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 226 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 123 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 30 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see @@ -190,98 +190,88 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 60 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 712.533333 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 570.872295 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 336.283550 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 4 6.67% 6.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 5 8.33% 15.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4 6.67% 21.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 1 1.67% 23.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 4 6.67% 30.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 10 16.67% 46.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 4 6.67% 53.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 5 8.33% 61.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 23 38.33% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 60 # Bytes accessed per row activation -system.physmem.totQLat 17284989 # Total ticks spent queuing -system.physmem.totMemAccLat 31028739 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 3665000 # Total ticks spent in databus transfers -system.physmem.avgQLat 23581.16 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 63 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 406.349206 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 267.472109 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 352.639181 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 10 15.87% 15.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 20 31.75% 47.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 9 14.29% 61.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 4 6.35% 68.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2 3.17% 71.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 3 4.76% 76.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 3 4.76% 80.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2 3.17% 84.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 10 15.87% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 63 # Bytes accessed per row activation +system.physmem.totQLat 3192729 # Total ticks spent queuing +system.physmem.totMemAccLat 10842729 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2040000 # Total ticks spent in databus transfers +system.physmem.avgQLat 7825.32 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 42331.16 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 3955.65 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 26575.32 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1583.79 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 3955.65 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1583.79 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 30.90 # Data bus utilization in percentage -system.physmem.busUtilRead 30.90 # Data bus utilization in percentage for reads +system.physmem.busUtil 12.37 # Data bus utilization in percentage +system.physmem.busUtilRead 12.37 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 5.25 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.77 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 662 # Number of row buffer hits during reads +system.physmem.readRowHits 342 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 90.31 # Row buffer hit rate for reads +system.physmem.readRowHitRate 83.82 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 16161.66 # Average gap between requests -system.physmem.pageHitRate 90.31 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 6500 # Time in different power states -system.physmem.memoryStateTime::REF 260000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 7800750 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 249480 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 90720 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 136125 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 49500 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 3088800 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 1037400 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 508560 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 508560 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 5483970 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 5436945 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 21750 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 63000 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 9488685 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 7186125 # Total energy per rank (pJ) -system.physmem.averagePower::0 1178.169797 # Core power per rank (mW) -system.physmem.averagePower::1 892.270681 # Core power per rank (mW) -system.membus.trans_dist::ReadReq 704 # Transaction distribution -system.membus.trans_dist::ReadResp 702 # Transaction distribution -system.membus.trans_dist::ReadExReq 29 # Transaction distribution -system.membus.trans_dist::ReadExResp 29 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1464 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1464 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 46784 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 46784 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 733 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 733 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 733 # Request fanout histogram -system.membus.reqLayer0.occupancy 803724 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 6.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 6629985 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 55.9 # Layer utilization (%) -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 2560 # Number of BP lookups -system.cpu.branchPred.condPredicted 1531 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 510 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 939 # Number of BTB lookups -system.cpu.branchPred.BTBHits 497 # Number of BTB hits +system.physmem.avgGap 40376.23 # Average gap between requests +system.physmem.pageHitRate 83.82 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 317520 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 173250 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 2207400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 10796085 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 29250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 14540625 # Total energy per rank (pJ) +system.physmem_0.averagePower 918.403600 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 6500 # Time in different power states +system.physmem_0.memoryStateTime::REF 520000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 15319750 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 151200 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 82500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 881400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 10626795 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 177750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 12936765 # Total energy per rank (pJ) +system.physmem_1.averagePower 817.101847 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 860250 # Time in different power states +system.physmem_1.memoryStateTime::REF 520000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 15071750 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.branchPred.lookups 2361 # Number of BP lookups +system.cpu.branchPred.condPredicted 1411 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 506 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 871 # Number of BTB lookups +system.cpu.branchPred.BTBHits 473 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 52.928647 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 297 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 54.305396 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 287 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 56 # Number of incorrect RAS predictions. +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -303,6 +293,14 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -324,6 +322,14 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -345,6 +351,14 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -367,84 +381,84 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls -system.cpu.numCycles 23720 # number of cpu cycles simulated +system.cpu.numCycles 32975 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 4394 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 12370 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2560 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 794 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 11397 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1063 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 19 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 322 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 84 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 4117 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 139 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 16747 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.858243 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.204203 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 6157 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 11322 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2361 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 760 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 7387 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1055 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 111 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 277 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 339 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 3848 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 178 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 14798 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.892688 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.216053 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 9977 59.57% 59.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2687 16.04% 75.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 563 3.36% 78.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 3520 21.02% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 8580 57.98% 57.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2466 16.66% 74.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 512 3.46% 78.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 3240 21.89% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 16747 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.107926 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.521501 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 4535 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 6577 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 5106 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 160 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 369 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 338 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 165 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 10143 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 1684 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 369 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 5681 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 3207 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 2422 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 4105 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 963 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 9048 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 426 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 49 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 5 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 101 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 748 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 9432 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 41033 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 9977 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 14798 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.071600 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.343351 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 5946 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 3315 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 5035 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 135 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 367 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 329 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 163 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 9887 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 1624 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 367 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 7027 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 950 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 1833 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 4080 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 541 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 8892 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 410 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 16 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 16 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 453 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 9276 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 40303 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 9770 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 18 # Number of floating rename lookups system.cpu.rename.CommittedMaps 5494 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 3938 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 3782 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 31 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 29 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 472 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 1824 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1295 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.tempSerializingInsts 28 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 320 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 1789 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1266 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 8517 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 40 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 7242 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 203 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 2981 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 8241 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 3 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 16747 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.432436 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 0.833231 # Number of insts issued each cycle +system.cpu.iq.iqInstsAdded 8351 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 39 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 7157 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 186 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 2800 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 7772 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 14798 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.483646 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 0.864768 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 12501 74.65% 74.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1960 11.70% 86.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 1628 9.72% 96.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 606 3.62% 99.69% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 52 0.31% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 10589 71.56% 71.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1954 13.20% 84.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 1606 10.85% 95.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 605 4.09% 99.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 44 0.30% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle @@ -452,149 +466,149 @@ system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Nu system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 4 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 16747 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 14798 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 437 29.61% 29.61% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 29.61% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 29.61% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 29.61% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 29.61% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 29.61% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 29.61% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 29.61% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 29.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 29.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 29.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 29.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 29.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 29.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 29.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 29.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 29.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 29.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 29.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 29.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 29.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 29.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 29.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 29.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 29.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 29.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 29.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 29.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 29.61% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 482 32.66% 62.26% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 557 37.74% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 414 28.91% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 28.91% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 469 32.75% 61.66% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 549 38.34% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 4533 62.59% 62.59% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 6 0.08% 62.68% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.68% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.68% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.68% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.68% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.68% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.68% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 62.72% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.72% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.72% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.72% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 1613 22.27% 84.99% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1087 15.01% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 4493 62.78% 62.78% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 5 0.07% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 62.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.89% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 1580 22.08% 84.97% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1076 15.03% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 7242 # Type of FU issued -system.cpu.iq.rate 0.305312 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1476 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.203811 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 32865 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 11527 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 6638 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 45 # Number of floating instruction queue reads +system.cpu.iq.FU_type_0::total 7157 # Type of FU issued +system.cpu.iq.rate 0.217043 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1432 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.200084 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 30686 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 11179 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 6571 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 44 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 18 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 8689 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 29 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 15 # Number of loads that had data forwarded from stores +system.cpu.iq.int_alu_accesses 8561 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 28 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 10 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 797 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.squashedLoads 762 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 7 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 357 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 328 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 7 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 23 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 6 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 21 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 369 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 705 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 159 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 8571 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 367 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 446 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 24 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 8404 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 1824 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1295 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 28 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 6 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 151 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewDispLoadInsts 1789 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1266 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 27 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 19 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 7 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 68 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 294 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 362 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 6828 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 1428 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 414 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 69 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 290 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 359 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 6761 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 1400 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 396 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 14 # number of nop insts executed -system.cpu.iew.exec_refs 2449 # number of memory reference insts executed -system.cpu.iew.exec_branches 1283 # Number of branches executed -system.cpu.iew.exec_stores 1021 # Number of stores executed -system.cpu.iew.exec_rate 0.287858 # Inst execution rate -system.cpu.iew.wb_sent 6699 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 6654 # cumulative count of insts written-back -system.cpu.iew.wb_producers 3045 # num instructions producing a value -system.cpu.iew.wb_consumers 5519 # num instructions consuming a value +system.cpu.iew.exec_refs 2417 # number of memory reference insts executed +system.cpu.iew.exec_branches 1277 # Number of branches executed +system.cpu.iew.exec_stores 1017 # Number of stores executed +system.cpu.iew.exec_rate 0.205034 # Inst execution rate +system.cpu.iew.wb_sent 6630 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 6587 # cumulative count of insts written-back +system.cpu.iew.wb_producers 2990 # num instructions producing a value +system.cpu.iew.wb_consumers 5391 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.280523 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.551730 # average fanout of values written-back +system.cpu.iew.wb_rate 0.199757 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.554628 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 2714 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 2570 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 348 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 16184 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.332242 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 0.986798 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 346 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 14256 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.377175 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.026651 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 13581 83.92% 83.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1345 8.31% 92.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 599 3.70% 95.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 281 1.74% 97.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 168 1.04% 98.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 78 0.48% 99.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 47 0.29% 99.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 33 0.20% 99.68% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 52 0.32% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 11607 81.42% 81.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1384 9.71% 91.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 607 4.26% 95.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 292 2.05% 97.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 168 1.18% 98.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 76 0.53% 99.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 46 0.32% 99.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 33 0.23% 99.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 43 0.30% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 16184 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 14256 # Number of insts commited each cycle system.cpu.commit.committedInsts 4591 # Number of instructions committed system.cpu.commit.committedOps 5377 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -640,449 +654,469 @@ system.cpu.commit.op_class_0::MemWrite 938 17.44% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 5377 # Class of committed instruction -system.cpu.commit.bw_lim_events 52 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 43 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 24066 # The number of ROB reads -system.cpu.rob.rob_writes 16750 # The number of ROB writes -system.cpu.timesIdled 138 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 6973 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 22003 # The number of ROB reads +system.cpu.rob.rob_writes 16441 # The number of ROB writes +system.cpu.timesIdled 222 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 18177 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 4591 # Number of Instructions Simulated system.cpu.committedOps 5377 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 5.166630 # CPI: Cycles Per Instruction -system.cpu.cpi_total 5.166630 # CPI: Total CPI of All Threads -system.cpu.ipc 0.193550 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.193550 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 6787 # number of integer regfile reads -system.cpu.int_regfile_writes 3839 # number of integer regfile writes +system.cpu.cpi 7.182531 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.182531 # CPI: Total CPI of All Threads +system.cpu.ipc 0.139227 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.139227 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 6737 # number of integer regfile reads +system.cpu.int_regfile_writes 3765 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.cc_regfile_reads 24301 # number of cc regfile reads -system.cpu.cc_regfile_writes 2919 # number of cc regfile writes -system.cpu.misc_regfile_reads 2642 # number of misc regfile reads +system.cpu.cc_regfile_reads 24010 # number of cc regfile reads +system.cpu.cc_regfile_writes 2910 # number of cc regfile writes +system.cpu.misc_regfile_reads 2599 # number of misc regfile reads system.cpu.misc_regfile_writes 24 # number of misc regfile writes -system.cpu.toL2Bus.trans_dist::ReadReq 408 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 407 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 1026 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 40 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 40 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 608 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 287 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 895 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 19456 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9152 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 28608 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 1026 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 1474 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5.696065 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.460111 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 448 30.39% 30.39% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 1026 69.61% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 1474 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 224000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 461250 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 3.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 223747 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 1.9 # Layer utilization (%) -system.cpu.icache.tags.replacements 47 # number of replacements -system.cpu.icache.tags.tagsinuse 138.950029 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 3784 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 304 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 12.447368 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 1 # number of replacements +system.cpu.dcache.tags.tagsinuse 84.720980 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 1896 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 142 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 13.352113 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 84.720980 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.165471 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.165471 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 141 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 67 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 74 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.275391 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 4676 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 4676 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 1154 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1154 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 722 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 722 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 9 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 9 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits 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(read+write) misses +system.cpu.dcache.overall_misses::cpu.data 369 # number of overall misses +system.cpu.dcache.overall_misses::total 369 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 8985992 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 8985992 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 6715000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 6715000 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 112000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 112000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 15700992 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 15700992 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 15700992 # number of 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number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 92 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 151 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 59 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 92 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 603 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 754 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 3978500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4478500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 8457000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 49457864 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 49457864 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2337500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2337500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 3978500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6816000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 10794500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 3978500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6816000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 49457864 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 60252364 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.194079 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.605769 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.299020 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 5 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 6 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 5 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 6 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits 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+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.919192 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.764706 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.879699 # mshr miss rate for ReadReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.725000 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.725000 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.194079 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.638889 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.337054 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.194079 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.638889 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.731707 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.731707 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.919192 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.755245 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.865909 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.919192 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.755245 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 1.683036 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67432.203390 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 71087.301587 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 69319.672131 # average ReadReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 82019.674959 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 82019.674959 # average HardPFReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80603.448276 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 80603.448276 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67432.203390 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 74086.956522 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71486.754967 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67432.203390 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 74086.956522 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 82019.674959 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 79910.297082 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.975000 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 52055.860806 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 53663.461538 # average ReadReq mshr miss latency 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-system.cpu.dcache.tags.occ_percent::cpu.data 0.160760 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.160760 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 142 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 112 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 30 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.277344 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 4719 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 4719 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 1158 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1158 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 715 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 715 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 10 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 10 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 1873 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 1873 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 1873 # number of overall hits -system.cpu.dcache.overall_hits::total 1873 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 194 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 194 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 198 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 198 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 392 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 392 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 392 # number of overall misses -system.cpu.dcache.overall_misses::total 392 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 10805495 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 10805495 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 8861750 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 8861750 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 152500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 152500 # number of LoadLockedReq miss cycles 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LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.166667 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.173068 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.173068 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.173068 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.173068 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55698.427835 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 55698.427835 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44756.313131 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 44756.313131 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 76250 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 76250 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 50171.543367 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 50171.543367 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 50171.543367 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 50171.543367 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 10 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 617 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 18 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 10 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 34.277778 # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 90 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 90 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 158 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 158 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 248 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 248 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 248 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 248 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 104 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 104 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 40 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 40 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 144 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 144 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 144 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 144 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5492753 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5492753 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2689000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2689000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8181753 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 8181753 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8181753 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 8181753 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076923 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076923 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.043812 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.043812 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.063576 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.063576 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.063576 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.063576 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 52814.932692 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 52814.932692 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 67225 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67225 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 56817.729167 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 56817.729167 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 56817.729167 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 56817.729167 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.trans_dist::ReadReq 399 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 397 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 67 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 41 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 41 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 593 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 285 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 878 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18944 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9088 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 28032 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 67 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 507 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 5.132150 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.338988 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 440 86.79% 86.79% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::6 67 13.21% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 507 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 220000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 493249 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 3.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 222745 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%) +system.membus.trans_dist::ReadReq 378 # Transaction distribution +system.membus.trans_dist::ReadResp 376 # Transaction distribution +system.membus.trans_dist::ReadExReq 30 # Transaction distribution +system.membus.trans_dist::ReadExResp 30 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 814 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 814 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 25984 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 25984 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 408 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 408 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 408 # Request fanout histogram +system.membus.reqLayer0.occupancy 506687 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 3.1 # Layer utilization (%) +system.membus.respLayer1.occupancy 3785965 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 23.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt index 398374723..72322cbec 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt @@ -4,10 +4,10 @@ sim_seconds 0.000003 # Nu sim_ticks 2694500 # Number of ticks simulated final_tick 2694500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 582910 # Simulator instruction rate (inst/s) -host_op_rate 681582 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 341032781 # Simulator tick rate (ticks/s) -host_mem_usage 293692 # Number of bytes of host memory used +host_inst_rate 396323 # Simulator instruction rate (inst/s) +host_op_rate 463654 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 232084410 # Simulator tick rate (ticks/s) +host_mem_usage 298640 # Number of bytes of host memory used host_seconds 0.01 # Real time elapsed on the host sim_insts 4591 # Number of instructions simulated sim_ops 5377 # Number of ops (including micro ops) simulated @@ -35,35 +35,15 @@ system.physmem.bw_write::total 1353868992 # Wr system.physmem.bw_total::cpu.inst 6834663203 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 3020597513 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 9855260716 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 5596 # Transaction distribution -system.membus.trans_dist::ReadResp 5607 # Transaction distribution -system.membus.trans_dist::WriteReq 913 # Transaction distribution -system.membus.trans_dist::WriteResp 913 # Transaction distribution -system.membus.trans_dist::LoadLockedReq 11 # Transaction distribution -system.membus.trans_dist::StoreCondReq 11 # Transaction distribution -system.membus.trans_dist::StoreCondResp 11 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 9208 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 3854 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 13062 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 18416 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 8139 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 26555 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 6531 # Request fanout histogram -system.membus.snoop_fanout::mean 4.704946 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.456102 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::4 1927 29.51% 29.51% # Request fanout histogram -system.membus.snoop_fanout::5 4604 70.49% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 4 # Request fanout histogram -system.membus.snoop_fanout::max_value 5 # Request fanout histogram -system.membus.snoop_fanout::total 6531 # Request fanout histogram system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.checker.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.checker.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.checker.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -85,6 +65,14 @@ system.cpu.checker.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.checker.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.checker.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.checker.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.checker.dtb.walker.walks 0 # Table walker walks requested +system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.checker.dtb.inst_hits 0 # ITB inst hits system.cpu.checker.dtb.inst_misses 0 # ITB inst misses system.cpu.checker.dtb.read_hits 0 # DTB read hits @@ -106,6 +94,14 @@ system.cpu.checker.dtb.inst_accesses 0 # IT system.cpu.checker.dtb.hits 0 # DTB hits system.cpu.checker.dtb.misses 0 # DTB misses system.cpu.checker.dtb.accesses 0 # DTB accesses +system.cpu.checker.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.checker.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.checker.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.checker.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -127,6 +123,14 @@ system.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.checker.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.checker.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.checker.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.checker.itb.walker.walks 0 # Table walker walks requested +system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.checker.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.checker.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.checker.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.checker.itb.inst_hits 0 # ITB inst hits system.cpu.checker.itb.inst_misses 0 # ITB inst misses system.cpu.checker.itb.read_hits 0 # DTB read hits @@ -152,6 +156,14 @@ system.cpu.workload.num_syscalls 13 # Nu system.cpu.checker.numCycles 0 # number of cpu cycles simulated system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -173,6 +185,14 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -194,6 +214,14 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -215,6 +243,14 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -296,5 +332,33 @@ system.cpu.op_class::MemWrite 938 17.40% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 5390 # Class of executed instruction +system.membus.trans_dist::ReadReq 5596 # Transaction distribution +system.membus.trans_dist::ReadResp 5607 # Transaction distribution +system.membus.trans_dist::WriteReq 913 # Transaction distribution +system.membus.trans_dist::WriteResp 913 # Transaction distribution +system.membus.trans_dist::LoadLockedReq 11 # Transaction distribution +system.membus.trans_dist::StoreCondReq 11 # Transaction distribution +system.membus.trans_dist::StoreCondResp 11 # Transaction distribution +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 9208 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 3854 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 13062 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 18416 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 8139 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 26555 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 6531 # Request fanout histogram +system.membus.snoop_fanout::mean 4.704946 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.456102 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::4 1927 29.51% 29.51% # Request fanout histogram +system.membus.snoop_fanout::5 4604 70.49% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 4 # Request fanout histogram +system.membus.snoop_fanout::max_value 5 # Request fanout histogram +system.membus.snoop_fanout::total 6531 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt index d2d36b722..b8c713e42 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt @@ -4,10 +4,10 @@ sim_seconds 0.000003 # Nu sim_ticks 2694500 # Number of ticks simulated final_tick 2694500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 685428 # Simulator instruction rate (inst/s) -host_op_rate 801222 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 400788339 # Simulator tick rate (ticks/s) -host_mem_usage 292412 # Number of bytes of host memory used +host_inst_rate 370272 # Simulator instruction rate (inst/s) +host_op_rate 433210 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 216878622 # Simulator tick rate (ticks/s) +host_mem_usage 297624 # Number of bytes of host memory used host_seconds 0.01 # Real time elapsed on the host sim_insts 4591 # Number of instructions simulated sim_ops 5377 # Number of ops (including micro ops) simulated @@ -35,35 +35,15 @@ system.physmem.bw_write::total 1353868992 # Wr system.physmem.bw_total::cpu.inst 6834663203 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 3020597513 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 9855260716 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 5596 # Transaction distribution -system.membus.trans_dist::ReadResp 5607 # Transaction distribution -system.membus.trans_dist::WriteReq 913 # Transaction distribution -system.membus.trans_dist::WriteResp 913 # Transaction distribution -system.membus.trans_dist::LoadLockedReq 11 # Transaction distribution -system.membus.trans_dist::StoreCondReq 11 # Transaction distribution -system.membus.trans_dist::StoreCondResp 11 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 9208 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 3854 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 13062 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 18416 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 8139 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 26555 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 6531 # Request fanout histogram -system.membus.snoop_fanout::mean 4.704946 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.456102 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::4 1927 29.51% 29.51% # Request fanout histogram -system.membus.snoop_fanout::5 4604 70.49% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 4 # Request fanout histogram -system.membus.snoop_fanout::max_value 5 # Request fanout histogram -system.membus.snoop_fanout::total 6531 # Request fanout histogram system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -85,6 +65,14 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -106,6 +94,14 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -127,6 +123,14 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -209,5 +213,33 @@ system.cpu.op_class::MemWrite 938 17.40% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 5390 # Class of executed instruction +system.membus.trans_dist::ReadReq 5596 # Transaction distribution +system.membus.trans_dist::ReadResp 5607 # Transaction distribution +system.membus.trans_dist::WriteReq 913 # Transaction distribution +system.membus.trans_dist::WriteResp 913 # Transaction distribution +system.membus.trans_dist::LoadLockedReq 11 # Transaction distribution +system.membus.trans_dist::StoreCondReq 11 # Transaction distribution +system.membus.trans_dist::StoreCondResp 11 # Transaction distribution +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 9208 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 3854 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 13062 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 18416 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 8139 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 26555 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 6531 # Request fanout histogram +system.membus.snoop_fanout::mean 4.704946 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.456102 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::4 1927 29.51% 29.51% # Request fanout histogram +system.membus.snoop_fanout::5 4604 70.49% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 4 # Request fanout histogram +system.membus.snoop_fanout::max_value 5 # Request fanout histogram +system.membus.snoop_fanout::total 6531 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt index 83a7fcb5f..872a056d2 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt @@ -4,10 +4,10 @@ sim_seconds 0.000026 # Nu sim_ticks 25815000 # Number of ticks simulated final_tick 25815000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 367819 # Simulator instruction rate (inst/s) -host_op_rate 428893 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2075494452 # Simulator tick rate (ticks/s) -host_mem_usage 302164 # Number of bytes of host memory used +host_inst_rate 376930 # Simulator instruction rate (inst/s) +host_op_rate 439541 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2127142386 # Simulator tick rate (ticks/s) +host_mem_usage 307352 # Number of bytes of host memory used host_seconds 0.01 # Real time elapsed on the host sim_insts 4565 # Number of instructions simulated sim_ops 5329 # Number of ops (including micro ops) simulated @@ -29,30 +29,15 @@ system.physmem.bw_inst_read::total 557815224 # In system.physmem.bw_total::cpu.inst 557815224 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 309897347 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 867712570 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 307 # Transaction distribution -system.membus.trans_dist::ReadResp 307 # Transaction distribution -system.membus.trans_dist::ReadExReq 43 # Transaction distribution -system.membus.trans_dist::ReadExResp 43 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 700 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 700 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22400 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 22400 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 350 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 350 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 350 # Request fanout histogram -system.membus.reqLayer0.occupancy 355000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 1.4 # Layer utilization (%) -system.membus.respLayer1.occupancy 3155000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 12.2 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -74,6 +59,14 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -95,6 +88,14 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -116,6 +117,14 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -198,6 +207,118 @@ system.cpu.op_class::MemWrite 938 17.40% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 5390 # Class of executed instruction +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 82.900177 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 1786 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 141 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 12.666667 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 82.900177 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.020239 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.020239 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 141 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 100 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.034424 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 3995 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 3995 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 894 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 894 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 870 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 870 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 1764 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 1764 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 1764 # number of overall hits +system.cpu.dcache.overall_hits::total 1764 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 98 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 98 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 43 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 43 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 141 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 141 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 141 # number of overall misses +system.cpu.dcache.overall_misses::total 141 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 4718000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4718000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 2365000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 2365000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 7083000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 7083000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 7083000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 7083000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 992 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 992 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 1905 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 1905 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 1905 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 1905 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098790 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.098790 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.047097 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.047097 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.074016 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.074016 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.074016 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.074016 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 48142.857143 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 48142.857143 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 50234.042553 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 50234.042553 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 50234.042553 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 50234.042553 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 98 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 98 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 43 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 141 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 141 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 141 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4522000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4522000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2279000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2279000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6801000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6801000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6801000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6801000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.098790 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.098790 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047097 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047097 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.074016 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.074016 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074016 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.074016 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46142.857143 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46142.857143 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 48234.042553 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 48234.042553 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 48234.042553 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 48234.042553 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 1 # number of replacements system.cpu.icache.tags.tagsinuse 114.428477 # Cycle average of tags in use system.cpu.icache.tags.total_refs 4364 # Total number of references to valid blocks. @@ -416,118 +537,6 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 82.900177 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 1786 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 141 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 12.666667 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 82.900177 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.020239 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.020239 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 141 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 100 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.034424 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 3995 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 3995 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 894 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 894 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 870 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 870 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 1764 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 1764 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 1764 # number of overall hits -system.cpu.dcache.overall_hits::total 1764 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 98 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 98 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 43 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 43 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 141 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 141 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 141 # number of overall misses -system.cpu.dcache.overall_misses::total 141 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 4718000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 4718000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 2365000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 2365000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 7083000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 7083000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 7083000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 7083000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 992 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 992 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 1905 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 1905 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 1905 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 1905 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098790 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.098790 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.047097 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.047097 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.074016 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.074016 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.074016 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.074016 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 48142.857143 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 48142.857143 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 50234.042553 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 50234.042553 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 50234.042553 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 50234.042553 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 98 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 98 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 43 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 141 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 141 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 141 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4522000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4522000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2279000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2279000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6801000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6801000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6801000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6801000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.098790 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.098790 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047097 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047097 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.074016 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.074016 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074016 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.074016 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46142.857143 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46142.857143 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 48234.042553 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 48234.042553 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 48234.042553 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 48234.042553 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 339 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 339 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 43 # Transaction distribution @@ -560,5 +569,28 @@ system.cpu.toL2Bus.respLayer0.occupancy 361500 # La system.cpu.toL2Bus.respLayer0.utilization 1.4 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 211500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) +system.membus.trans_dist::ReadReq 307 # Transaction distribution +system.membus.trans_dist::ReadResp 307 # Transaction distribution +system.membus.trans_dist::ReadExReq 43 # Transaction distribution +system.membus.trans_dist::ReadExResp 43 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 700 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 700 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22400 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 22400 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 350 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 350 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 350 # Request fanout histogram +system.membus.reqLayer0.occupancy 355000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.4 # Layer utilization (%) +system.membus.respLayer1.occupancy 3155000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 12.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt index 1593f969f..a18a67ef2 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000024 # Number of seconds simulated -sim_ticks 24417000 # Number of ticks simulated -final_tick 24417000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 24407000 # Number of ticks simulated +final_tick 24407000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 26948 # Simulator instruction rate (inst/s) -host_op_rate 26945 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 116974890 # Simulator tick rate (ticks/s) -host_mem_usage 277212 # Number of bytes of host memory used -host_seconds 0.21 # Real time elapsed on the host +host_inst_rate 92117 # Simulator instruction rate (inst/s) +host_op_rate 92097 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 399597243 # Simulator tick rate (ticks/s) +host_mem_usage 289532 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host sim_insts 5624 # Number of instructions simulated sim_ops 5624 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 20032 # Nu system.physmem.num_reads::cpu.inst 313 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 137 # Number of read requests responded to by this memory system.physmem.num_reads::total 450 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 820412008 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 359094074 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1179506082 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 820412008 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 820412008 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 820412008 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 359094074 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1179506082 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 820748146 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 359241201 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1179989347 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 820748146 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 820748146 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 820748146 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 359241201 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1179989347 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 450 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 450 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 24336000 # Total gap between requests +system.physmem.totGap 24326000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -200,19 +200,19 @@ system.physmem.bytesPerActivate::768-895 3 2.91% 94.17% # By system.physmem.bytesPerActivate::896-1023 1 0.97% 95.15% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 5 4.85% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 103 # Bytes accessed per row activation -system.physmem.totQLat 4914500 # Total ticks spent queuing -system.physmem.totMemAccLat 13352000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 4895500 # Total ticks spent queuing +system.physmem.totMemAccLat 13333000 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2250000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10921.11 # Average queueing delay per DRAM burst +system.physmem.avgQLat 10878.89 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29671.11 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1179.51 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 29628.89 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1179.99 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1179.51 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1179.99 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 9.21 # Data bus utilization in percentage -system.physmem.busUtilRead 9.21 # Data bus utilization in percentage for reads +system.physmem.busUtil 9.22 # Data bus utilization in percentage +system.physmem.busUtilRead 9.22 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.52 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing @@ -220,55 +220,36 @@ system.physmem.readRowHits 344 # Nu system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 76.44 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 54080.00 # Average gap between requests +system.physmem.avgGap 54057.78 # Average gap between requests system.physmem.pageHitRate 76.44 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 11000 # Time in different power states -system.physmem.memoryStateTime::REF 780000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 22851000 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 181440 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 582120 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 99000 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 317625 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 772200 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 2652000 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 1525680 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 1525680 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 14753880 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 16048350 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 1235250 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 99750 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 18567450 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 21225525 # Total energy per rank (pJ) -system.physmem.averagePower::0 785.799080 # Core power per rank (mW) -system.physmem.averagePower::1 898.292335 # Core power per rank (mW) -system.membus.trans_dist::ReadReq 400 # Transaction distribution -system.membus.trans_dist::ReadResp 400 # Transaction distribution -system.membus.trans_dist::ReadExReq 50 # Transaction distribution -system.membus.trans_dist::ReadExResp 50 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 900 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 900 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 28800 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 28800 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 450 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 450 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 450 # Request fanout histogram -system.membus.reqLayer0.occupancy 545500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 4210750 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 17.2 # Layer utilization (%) -system.cpu_clk_domain.clock 500 # Clock period in ticks +system.physmem_0.actEnergy 181440 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 99000 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 772200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 14753880 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1232250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 18564450 # Total energy per rank (pJ) +system.physmem_0.averagePower 785.838404 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1971000 # Time in different power states +system.physmem_0.memoryStateTime::REF 780000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 20886000 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 582120 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 317625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 2652000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 16041510 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 99750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 21218685 # Total energy per rank (pJ) +system.physmem_1.averagePower 898.383064 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 96500 # Time in different power states +system.physmem_1.memoryStateTime::REF 780000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 22756000 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.branchPred.lookups 1124 # Number of BP lookups system.cpu.branchPred.condPredicted 833 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 586 # Number of conditional branches incorrect @@ -278,6 +259,7 @@ system.cpu.branchPred.BTBCorrect 0 # Nu system.cpu.branchPred.BTBHitPct 38.705882 # BTB Hit Percentage system.cpu.branchPred.usedRAS 84 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 31 # Number of incorrect RAS predictions. +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses system.cpu.dtb.read_accesses 0 # DTB read accesses @@ -297,7 +279,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 7 # Number of system calls -system.cpu.numCycles 48835 # number of cpu cycles simulated +system.cpu.numCycles 48815 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.branch_predictor.predictedTaken 421 # Number of Branches Predicted As Taken (True). @@ -322,9 +304,9 @@ system.cpu.contextSwitches 1 # Nu system.cpu.threadCycles 9295 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode system.cpu.timesIdled 454 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 43587 # Number of cycles cpu's stages were not processed +system.cpu.idleCycles 43567 # Number of cycles cpu's stages were not processed system.cpu.runCycles 5248 # Number of cycles cpu stages are processed. -system.cpu.activity 10.746391 # Percentage of cycles cpu is active +system.cpu.activity 10.750794 # Percentage of cycles cpu is active system.cpu.comLoads 1132 # Number of Load instructions committed system.cpu.comStores 901 # Number of Store instructions committed system.cpu.comBranches 883 # Number of Branches instructions committed @@ -336,36 +318,148 @@ system.cpu.committedInsts 5624 # Nu system.cpu.committedOps 5624 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 5624 # Number of Instructions committed (Total) -system.cpu.cpi 8.683321 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 8.679765 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 8.683321 # CPI: Total CPI of All Threads -system.cpu.ipc 0.115163 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 8.679765 # CPI: Total CPI of All Threads +system.cpu.ipc 0.115210 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 0.115163 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 45291 # Number of cycles 0 instructions are processed. +system.cpu.ipc_total 0.115210 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 45271 # Number of cycles 0 instructions are processed. system.cpu.stage0.runCycles 3544 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 7.257090 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 46099 # Number of cycles 0 instructions are processed. +system.cpu.stage0.utilization 7.260064 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 46079 # Number of cycles 0 instructions are processed. system.cpu.stage1.runCycles 2736 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 5.602539 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 46145 # Number of cycles 0 instructions are processed. +system.cpu.stage1.utilization 5.604835 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 46125 # Number of cycles 0 instructions are processed. system.cpu.stage2.runCycles 2690 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 5.508344 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 47641 # Number of cycles 0 instructions are processed. +system.cpu.stage2.utilization 5.510601 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 47621 # Number of cycles 0 instructions are processed. system.cpu.stage3.runCycles 1194 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 2.444968 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 46041 # Number of cycles 0 instructions are processed. +system.cpu.stage3.utilization 2.445969 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 46021 # Number of cycles 0 instructions are processed. system.cpu.stage4.runCycles 2794 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 5.721306 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.utilization 5.723651 # Percentage of cycles stage was utilized (processing insts). +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 89.114959 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 1596 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 137 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 11.649635 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 89.114959 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.021757 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.021757 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 137 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 107 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.033447 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 4203 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 4203 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 1035 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1035 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 561 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 561 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 1596 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 1596 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 1596 # number of overall hits +system.cpu.dcache.overall_hits::total 1596 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 97 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 97 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 340 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 340 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 437 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 437 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 437 # number of overall misses +system.cpu.dcache.overall_misses::total 437 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 7368000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 7368000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 20579000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 20579000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 27947000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 27947000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 27947000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 27947000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1132 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1132 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 901 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 901 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 2033 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2033 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2033 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2033 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.085689 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.085689 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.377358 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.377358 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.214953 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.214953 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.214953 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.214953 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 75958.762887 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 75958.762887 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60526.470588 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 60526.470588 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 63951.945080 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 63951.945080 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 63951.945080 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 63951.945080 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 265 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 13 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 20.384615 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 10 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 10 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 290 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 290 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 300 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 300 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 300 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 300 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 87 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 87 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 50 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 50 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 137 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 137 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 137 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 137 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6703250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6703250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3771500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3771500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10474750 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10474750 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10474750 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10474750 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076855 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076855 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055494 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055494 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.067388 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.067388 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.067388 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.067388 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 77048.850575 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 77048.850575 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75430 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75430 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76458.029197 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 76458.029197 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76458.029197 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 76458.029197 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 13 # number of replacements -system.cpu.icache.tags.tagsinuse 147.900639 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 147.861470 # Cycle average of tags in use system.cpu.icache.tags.total_refs 418 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 315 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 1.326984 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 147.900639 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.072217 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.072217 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 147.861470 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.072198 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.072198 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 302 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 132 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 170 # Occupied blocks per task id @@ -384,12 +478,12 @@ system.cpu.icache.demand_misses::cpu.inst 344 # n system.cpu.icache.demand_misses::total 344 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 344 # number of overall misses system.cpu.icache.overall_misses::total 344 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 25151000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 25151000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 25151000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 25151000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 25151000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 25151000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 25136000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 25136000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 25136000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 25136000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 25136000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 25136000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 762 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 762 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 762 # number of demand (read+write) accesses @@ -402,12 +496,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.451444 system.cpu.icache.demand_miss_rate::total 0.451444 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.451444 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.451444 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 73113.372093 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 73113.372093 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 73113.372093 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 73113.372093 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 73113.372093 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 73113.372093 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 73069.767442 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 73069.767442 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 73069.767442 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 73069.767442 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 73069.767442 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 73069.767442 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -428,64 +522,36 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 315 system.cpu.icache.demand_mshr_misses::total 315 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 315 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 315 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22975000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 22975000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22975000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 22975000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22975000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 22975000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22960000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 22960000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22960000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 22960000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22960000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 22960000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.413386 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.413386 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.413386 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.413386 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.413386 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.413386 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72936.507937 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72936.507937 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72936.507937 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 72936.507937 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72936.507937 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 72936.507937 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72888.888889 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72888.888889 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72888.888889 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 72888.888889 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72888.888889 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 72888.888889 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 402 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 402 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 50 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 50 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 630 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 274 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 904 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20160 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8768 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 28928 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 452 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 452 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 452 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 226000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 532000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 224750 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 204.797884 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 204.748410 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 400 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.005000 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 149.365797 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 55.432088 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004558 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.001692 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.006250 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 149.325774 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 55.422636 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004557 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.001691 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.006248 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 400 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 161 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 239 # Occupied blocks per task id @@ -509,17 +575,17 @@ system.cpu.l2cache.demand_misses::total 450 # nu system.cpu.l2cache.overall_misses::cpu.inst 313 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 137 # number of overall misses system.cpu.l2cache.overall_misses::total 450 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 22634000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 22619000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6609750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 29243750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3723500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 3723500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 22634000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 10333250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 32967250 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 22634000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 10333250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 32967250 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 29228750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3718500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 3718500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 22619000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 10328250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 32947250 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 22619000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 10328250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 32947250 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 315 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 87 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 402 # number of ReadReq accesses(hits+misses) @@ -542,17 +608,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.995575 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993651 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.995575 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72313.099042 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72265.175719 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75974.137931 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 73109.375000 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74470 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74470 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72313.099042 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75425.182482 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 73260.555556 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72313.099042 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75425.182482 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 73260.555556 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 73071.875000 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74370 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74370 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72265.175719 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75388.686131 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 73216.111111 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72265.175719 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75388.686131 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 73216.111111 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -572,17 +638,17 @@ system.cpu.l2cache.demand_mshr_misses::total 450 system.cpu.l2cache.overall_mshr_misses::cpu.inst 313 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 137 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 450 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 18704000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 18689500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5530750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 24234750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3093000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3093000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18704000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8623750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 27327750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 18704000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8623750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 27327750 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 24220250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3088000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3088000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18689500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8618750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 27308250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 18689500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8618750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 27308250 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993651 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.995025 # mshr miss rate for ReadReq accesses @@ -594,129 +660,68 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.995575 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993651 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.995575 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59757.188498 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59710.862620 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63571.839080 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60586.875000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61860 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61860 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59757.188498 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62947.080292 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60728.333333 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59757.188498 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62947.080292 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60728.333333 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60550.625000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61760 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61760 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59710.862620 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62910.583942 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60685 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59710.862620 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62910.583942 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60685 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 89.129655 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 1596 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 137 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 11.649635 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 89.129655 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.021760 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.021760 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 137 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 107 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.033447 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 4203 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 4203 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 1035 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1035 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 561 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 561 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 1596 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 1596 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 1596 # number of overall hits -system.cpu.dcache.overall_hits::total 1596 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 97 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 97 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 340 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 340 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 437 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 437 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 437 # number of overall misses -system.cpu.dcache.overall_misses::total 437 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 7368000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 7368000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 20584000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 20584000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 27952000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 27952000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 27952000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 27952000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1132 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1132 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2033 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2033 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2033 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2033 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.085689 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.085689 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.377358 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.377358 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.214953 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.214953 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.214953 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.214953 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 75958.762887 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 75958.762887 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60541.176471 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 60541.176471 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 63963.386728 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 63963.386728 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 63963.386728 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 63963.386728 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 265 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 13 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 20.384615 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 10 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 10 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 290 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 290 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 300 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 300 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 300 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 300 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 87 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 87 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 50 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 50 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 137 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 137 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 137 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 137 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6703250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6703250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3776500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3776500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10479750 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10479750 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10479750 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10479750 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076855 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076855 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055494 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055494 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.067388 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.067388 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.067388 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.067388 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 77048.850575 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 77048.850575 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75530 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75530 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76494.525547 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 76494.525547 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76494.525547 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 76494.525547 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.trans_dist::ReadReq 402 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 402 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 50 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 50 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 630 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 274 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 904 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20160 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8768 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 28928 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 452 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 452 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 452 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 226000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 532000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 2.2 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 224750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) +system.membus.trans_dist::ReadReq 400 # Transaction distribution +system.membus.trans_dist::ReadResp 400 # Transaction distribution +system.membus.trans_dist::ReadExReq 50 # Transaction distribution +system.membus.trans_dist::ReadExResp 50 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 900 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 900 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 28800 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 28800 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 450 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 450 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 450 # Request fanout histogram +system.membus.reqLayer0.occupancy 545500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.2 # Layer utilization (%) +system.membus.respLayer1.occupancy 4210250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 17.3 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt index 61d4efb5a..ca0260a61 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000021 # Nu sim_ticks 21163500 # Number of ticks simulated final_tick 21163500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 24711 # Simulator instruction rate (inst/s) -host_op_rate 24708 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 104867636 # Simulator tick rate (ticks/s) -host_mem_usage 278232 # Number of bytes of host memory used -host_seconds 0.20 # Real time elapsed on the host +host_inst_rate 81533 # Simulator instruction rate (inst/s) +host_op_rate 81515 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 345921870 # Simulator tick rate (ticks/s) +host_mem_usage 292088 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host sim_insts 4986 # Number of instructions simulated sim_ops 4986 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -222,53 +222,34 @@ system.physmem.readRowHitRate 75.58 # Ro system.physmem.writeRowHitRate nan # Row buffer hit rate for writes system.physmem.avgGap 44762.21 # Average gap between requests system.physmem.pageHitRate 75.58 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 11000 # Time in different power states -system.physmem.memoryStateTime::REF 520000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 15315250 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 136080 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 536760 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 74250 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 292875 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 569400 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 2285400 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 1017120 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 1017120 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 9955620 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 10734525 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 766500 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 83250 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 12518970 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 14949930 # Total energy per rank (pJ) -system.physmem.averagePower::0 790.713406 # Core power per rank (mW) -system.physmem.averagePower::1 944.255803 # Core power per rank (mW) -system.membus.trans_dist::ReadReq 421 # Transaction distribution -system.membus.trans_dist::ReadResp 421 # Transaction distribution -system.membus.trans_dist::ReadExReq 50 # Transaction distribution -system.membus.trans_dist::ReadExResp 50 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 942 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 942 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30144 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 30144 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 471 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 471 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 471 # Request fanout histogram -system.membus.reqLayer0.occupancy 594000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 4415500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 20.9 # Layer utilization (%) -system.cpu_clk_domain.clock 500 # Clock period in ticks +system.physmem_0.actEnergy 136080 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 74250 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 569400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 9948780 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 772500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 12518130 # Total energy per rank (pJ) +system.physmem_0.averagePower 790.660351 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2505250 # Time in different power states +system.physmem_0.memoryStateTime::REF 520000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 14081250 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 536760 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 292875 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 2285400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 10734525 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 83250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 14949930 # Total energy per rank (pJ) +system.physmem_1.averagePower 944.255803 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 97000 # Time in different power states +system.physmem_1.memoryStateTime::REF 520000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 15229250 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.branchPred.lookups 2146 # Number of BP lookups system.cpu.branchPred.condPredicted 1406 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 427 # Number of conditional branches incorrect @@ -278,6 +259,7 @@ system.cpu.branchPred.BTBCorrect 0 # Nu system.cpu.branchPred.BTBHitPct 32.273839 # BTB Hit Percentage system.cpu.branchPred.usedRAS 284 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 68 # Number of incorrect RAS predictions. +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses system.cpu.dtb.read_accesses 0 # DTB read accesses @@ -589,34 +571,118 @@ system.cpu.int_regfile_writes 5247 # nu system.cpu.fp_regfile_reads 3 # number of floating regfile reads system.cpu.fp_regfile_writes 1 # number of floating regfile writes system.cpu.misc_regfile_reads 164 # number of misc regfile reads -system.cpu.toL2Bus.trans_dist::ReadReq 424 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 424 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 50 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 50 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 666 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 282 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 948 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 21312 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9024 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 30336 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 474 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 474 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 474 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 237000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 562000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.7 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 227000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%) +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 91.168146 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 2445 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 141 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 17.340426 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 91.168146 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.022258 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.022258 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 141 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 102 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.034424 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 6061 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 6061 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 1893 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1893 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 552 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 552 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 2445 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2445 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2445 # number of overall hits +system.cpu.dcache.overall_hits::total 2445 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 166 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 166 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 349 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 349 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 515 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 515 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 515 # number of overall misses +system.cpu.dcache.overall_misses::total 515 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11320500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11320500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 22383749 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 22383749 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 33704249 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 33704249 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 33704249 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 33704249 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 2059 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 2059 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 901 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 901 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 2960 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2960 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2960 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2960 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.080622 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.080622 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.387347 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.387347 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.173986 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.173986 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.173986 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.173986 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 68195.783133 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 68195.783133 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64136.816619 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 64136.816619 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 65445.143689 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 65445.143689 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 65445.143689 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 65445.143689 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 573 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 11 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 52.090909 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 75 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 75 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 299 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 299 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 374 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 374 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 374 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 374 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 91 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 91 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 50 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 50 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 141 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 141 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 141 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7311000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 7311000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4032499 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4032499 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11343499 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 11343499 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11343499 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 11343499 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.044196 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.044196 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055494 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055494 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.047635 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.047635 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.047635 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.047635 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 80340.659341 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 80340.659341 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80649.980000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80649.980000 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 80450.347518 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 80450.347518 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 80450.347518 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 80450.347518 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 17 # number of replacements system.cpu.icache.tags.tagsinuse 158.344728 # Cycle average of tags in use system.cpu.icache.tags.total_refs 1593 # Total number of references to valid blocks. @@ -838,117 +904,56 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59142.424242 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67056.737589 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61511.677282 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 91.168146 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 2445 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 141 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 17.340426 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 91.168146 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.022258 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.022258 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 141 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 102 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.034424 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 6061 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 6061 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 1893 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1893 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 552 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 552 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2445 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2445 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2445 # number of overall hits -system.cpu.dcache.overall_hits::total 2445 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 166 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 166 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 349 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 349 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 515 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 515 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 515 # number of overall misses -system.cpu.dcache.overall_misses::total 515 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11320500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11320500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 22383749 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 22383749 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 33704249 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 33704249 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 33704249 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 33704249 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 2059 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 2059 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2960 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2960 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2960 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2960 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.080622 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.080622 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.387347 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.387347 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.173986 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.173986 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.173986 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.173986 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 68195.783133 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 68195.783133 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64136.816619 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 64136.816619 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 65445.143689 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 65445.143689 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 65445.143689 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 65445.143689 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 573 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 11 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 52.090909 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 75 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 75 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 299 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 299 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 374 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 374 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 374 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 374 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 91 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 91 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 50 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 50 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 141 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 141 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 141 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7311000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 7311000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4032499 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4032499 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11343499 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 11343499 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11343499 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 11343499 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.044196 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.044196 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055494 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055494 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.047635 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.047635 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.047635 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.047635 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 80340.659341 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 80340.659341 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80649.980000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80649.980000 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 80450.347518 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 80450.347518 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 80450.347518 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 80450.347518 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.trans_dist::ReadReq 424 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 424 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 50 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 50 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 666 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 282 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 948 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 21312 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9024 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 30336 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 474 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 474 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 474 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 237000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 562000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 2.7 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 227000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%) +system.membus.trans_dist::ReadReq 421 # Transaction distribution +system.membus.trans_dist::ReadResp 421 # Transaction distribution +system.membus.trans_dist::ReadExReq 50 # Transaction distribution +system.membus.trans_dist::ReadExResp 50 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 942 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 942 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30144 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 30144 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 471 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 471 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 471 # Request fanout histogram +system.membus.reqLayer0.occupancy 594000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.8 # Layer utilization (%) +system.membus.respLayer1.occupancy 4415500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 20.9 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt index 3a696e5a2..8476aa73a 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000116 # Number of seconds simulated -sim_ticks 115508 # Number of ticks simulated -final_tick 115508 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000115 # Number of seconds simulated +sim_ticks 115467 # Number of ticks simulated +final_tick 115467 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 2198 # Simulator instruction rate (inst/s) -host_op_rate 2198 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 45146 # Simulator tick rate (ticks/s) -host_mem_usage 435400 # Number of bytes of host memory used -host_seconds 2.56 # Real time elapsed on the host +host_inst_rate 66709 # Simulator instruction rate (inst/s) +host_op_rate 66698 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1369179 # Simulator tick rate (ticks/s) +host_mem_usage 449556 # Number of bytes of host memory used +host_seconds 0.08 # Real time elapsed on the host sim_insts 5624 # Number of instructions simulated sim_ops 5624 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,41 +21,41 @@ system.mem_ctrls.num_reads::ruby.dir_cntrl0 1470 # system.mem_ctrls.num_reads::total 1470 # Number of read requests responded to by this memory system.mem_ctrls.num_writes::ruby.dir_cntrl0 1466 # Number of write requests responded to by this memory system.mem_ctrls.num_writes::total 1466 # Number of write requests responded to by this memory -system.mem_ctrls.bw_read::ruby.dir_cntrl0 814489040 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_read::total 814489040 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::ruby.dir_cntrl0 812272743 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::total 812272743 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_total::ruby.dir_cntrl0 1626761783 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.bw_total::total 1626761783 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_read::ruby.dir_cntrl0 814778248 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 814778248 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::ruby.dir_cntrl0 812561165 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::total 812561165 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::ruby.dir_cntrl0 1627339413 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 1627339413 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrls.readReqs 1470 # Number of read requests accepted system.mem_ctrls.writeReqs 1466 # Number of write requests accepted system.mem_ctrls.readBursts 1470 # Number of DRAM read bursts, including those serviced by the write queue system.mem_ctrls.writeBursts 1466 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrls.bytesReadDRAM 59264 # Total number of bytes read from DRAM -system.mem_ctrls.bytesReadWrQ 34816 # Total number of bytes read from write queue -system.mem_ctrls.bytesWritten 60672 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadDRAM 59456 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 34624 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 60800 # Total number of bytes written to DRAM system.mem_ctrls.bytesReadSys 94080 # Total read bytes from the system interface side system.mem_ctrls.bytesWrittenSys 93824 # Total written bytes from the system interface side -system.mem_ctrls.servicedByWrQ 544 # Number of DRAM read bursts serviced by the write queue -system.mem_ctrls.mergedWrBursts 493 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.servicedByWrQ 541 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 491 # Number of DRAM write bursts merged with an existing one system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.mem_ctrls.perBankRdBursts::0 33 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::0 34 # Per bank write bursts system.mem_ctrls.perBankRdBursts::1 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::2 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::3 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::4 7 # Per bank write bursts system.mem_ctrls.perBankRdBursts::5 3 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::6 12 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::7 86 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::8 65 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::9 244 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::10 102 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::11 43 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::12 100 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::6 13 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 88 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::8 66 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::9 248 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::10 103 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::11 46 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::12 103 # Per bank write bursts system.mem_ctrls.perBankRdBursts::13 45 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::14 173 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::15 13 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::0 35 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::14 158 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::15 15 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 36 # Per bank write bursts system.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::3 0 # Per bank write bursts @@ -64,16 +64,16 @@ system.mem_ctrls.perBankWrBursts::5 3 # Pe system.mem_ctrls.perBankWrBursts::6 13 # Per bank write bursts system.mem_ctrls.perBankWrBursts::7 76 # Per bank write bursts system.mem_ctrls.perBankWrBursts::8 60 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::9 244 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::9 249 # Per bank write bursts system.mem_ctrls.perBankWrBursts::10 103 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::11 45 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::12 110 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::13 43 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::14 194 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::15 15 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::11 47 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::12 114 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::13 44 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::14 182 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::15 16 # Per bank write bursts system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrls.totGap 115437 # Total gap between requests +system.mem_ctrls.totGap 115396 # Total gap between requests system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) @@ -88,7 +88,7 @@ system.mem_ctrls.writePktSize::3 0 # Wr system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::6 1466 # Write request sizes (log2) -system.mem_ctrls.rdQLenPdf::0 926 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::0 929 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see @@ -135,12 +135,12 @@ system.mem_ctrls.wrQLenPdf::11 1 # Wh system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::15 12 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::16 16 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::15 13 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::16 17 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::17 56 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::18 60 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::19 59 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::20 64 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::18 62 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::19 60 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::20 61 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::21 59 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::22 58 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::23 58 # What write queue length does an incoming req see @@ -184,162 +184,91 @@ system.mem_ctrls.wrQLenPdf::60 0 # Wh system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrls.bytesPerActivate::samples 349 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::mean 341.455587 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::gmean 225.575393 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::stdev 311.156448 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::0-127 80 22.92% 22.92% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::128-255 99 28.37% 51.29% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::256-383 59 16.91% 68.19% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::384-511 25 7.16% 75.36% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::512-639 22 6.30% 81.66% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::640-767 9 2.58% 84.24% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::768-895 12 3.44% 87.68% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::896-1023 6 1.72% 89.40% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::1024-1151 37 10.60% 100.00% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::total 349 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::samples 362 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 330.077348 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 218.964738 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 303.831296 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 84 23.20% 23.20% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 104 28.73% 51.93% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 58 16.02% 67.96% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 36 9.94% 77.90% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 19 5.25% 83.15% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 10 2.76% 85.91% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 9 2.49% 88.40% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 5 1.38% 89.78% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 37 10.22% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 362 # Bytes accessed per row activation system.mem_ctrls.rdPerTurnAround::samples 57 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::mean 16.070175 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::gmean 15.908868 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::stdev 2.750712 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::12-13 2 3.51% 3.51% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::14-15 24 42.11% 45.61% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::mean 16.105263 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::gmean 15.953786 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::stdev 2.697116 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::12-13 1 1.75% 1.75% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::14-15 25 43.86% 45.61% # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::16-17 25 43.86% 89.47% # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::18-19 5 8.77% 98.25% # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::34-35 1 1.75% 100.00% # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::total 57 # Reads before turning the bus around for writes system.mem_ctrls.wrPerTurnAround::samples 57 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::mean 16.631579 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::gmean 16.601010 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::stdev 1.045937 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::16 39 68.42% 68.42% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::17 5 8.77% 77.19% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::18 9 15.79% 92.98% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::19 3 5.26% 98.25% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::mean 16.666667 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::gmean 16.637263 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::stdev 1.023533 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::16 37 64.91% 64.91% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::17 6 10.53% 75.44% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::18 11 19.30% 94.74% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::19 2 3.51% 98.25% # Writes before turning the bus around for reads system.mem_ctrls.wrPerTurnAround::20 1 1.75% 100.00% # Writes before turning the bus around for reads system.mem_ctrls.wrPerTurnAround::total 57 # Writes before turning the bus around for reads -system.mem_ctrls.totQLat 12468 # Total ticks spent queuing -system.mem_ctrls.totMemAccLat 30062 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrls.totBusLat 4630 # Total ticks spent in databus transfers -system.mem_ctrls.avgQLat 13.46 # Average queueing delay per DRAM burst +system.mem_ctrls.totQLat 12340 # Total ticks spent queuing +system.mem_ctrls.totMemAccLat 29991 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.totBusLat 4645 # Total ticks spent in databus transfers +system.mem_ctrls.avgQLat 13.28 # Average queueing delay per DRAM burst system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst -system.mem_ctrls.avgMemAccLat 32.46 # Average memory access latency per DRAM burst -system.mem_ctrls.avgRdBW 513.07 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrls.avgWrBW 525.26 # Average achieved write bandwidth in MiByte/s -system.mem_ctrls.avgRdBWSys 814.49 # Average system read bandwidth in MiByte/s -system.mem_ctrls.avgWrBWSys 812.27 # Average system write bandwidth in MiByte/s +system.mem_ctrls.avgMemAccLat 32.28 # Average memory access latency per DRAM burst +system.mem_ctrls.avgRdBW 514.92 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 526.56 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 814.78 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 812.56 # Average system write bandwidth in MiByte/s system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrls.busUtil 8.11 # Data bus utilization in percentage -system.mem_ctrls.busUtilRead 4.01 # Data bus utilization in percentage for reads -system.mem_ctrls.busUtilWrite 4.10 # Data bus utilization in percentage for writes +system.mem_ctrls.busUtil 8.14 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 4.02 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 4.11 # Data bus utilization in percentage for writes system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing -system.mem_ctrls.avgWrQLen 25.51 # Average write queue length when enqueuing -system.mem_ctrls.readRowHits 626 # Number of row buffer hits during reads -system.mem_ctrls.writeRowHits 891 # Number of row buffer hits during writes -system.mem_ctrls.readRowHitRate 67.60 # Row buffer hit rate for reads -system.mem_ctrls.writeRowHitRate 91.57 # Row buffer hit rate for writes -system.mem_ctrls.avgGap 39.32 # Average gap between requests -system.mem_ctrls.pageHitRate 79.88 # Row buffer hit rate, read and write combined -system.mem_ctrls.memoryStateTime::IDLE 12 # Time in different power states -system.mem_ctrls.memoryStateTime::REF 3640 # Time in different power states -system.mem_ctrls.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls.memoryStateTime::ACT 105626 # Time in different power states -system.mem_ctrls.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrls.actEnergy::0 453600 # Energy for activate commands per rank (pJ) -system.mem_ctrls.actEnergy::1 2033640 # Energy for activate commands per rank (pJ) -system.mem_ctrls.preEnergy::0 252000 # Energy for precharge commands per rank (pJ) -system.mem_ctrls.preEnergy::1 1129800 # Energy for precharge commands per rank (pJ) -system.mem_ctrls.readEnergy::0 1547520 # Energy for read commands per rank (pJ) -system.mem_ctrls.readEnergy::1 9409920 # Energy for read commands per rank (pJ) -system.mem_ctrls.writeEnergy::0 1213056 # Energy for write commands per rank (pJ) -system.mem_ctrls.writeEnergy::1 8107776 # Energy for write commands per rank (pJ) -system.mem_ctrls.refreshEnergy::0 7119840 # Energy for refresh commands per rank (pJ) -system.mem_ctrls.refreshEnergy::1 7119840 # Energy for refresh commands per rank (pJ) -system.mem_ctrls.actBackEnergy::0 51518196 # Energy for active background per rank (pJ) -system.mem_ctrls.actBackEnergy::1 74359692 # Energy for active background per rank (pJ) -system.mem_ctrls.preBackEnergy::0 20367000 # Energy for precharge background per rank (pJ) -system.mem_ctrls.preBackEnergy::1 330600 # Energy for precharge background per rank (pJ) -system.mem_ctrls.totalEnergy::0 82471212 # Total energy per rank (pJ) -system.mem_ctrls.totalEnergy::1 102491268 # Total energy per rank (pJ) -system.mem_ctrls.averagePower::0 754.788512 # Core power per rank (mW) -system.mem_ctrls.averagePower::1 938.014973 # Core power per rank (mW) -system.ruby.clk_domain.clock 1 # Clock period in ticks -system.ruby.delayHist::bucket_size 1 # delay histogram for all message -system.ruby.delayHist::max_bucket 9 # delay histogram for all message -system.ruby.delayHist::samples 2936 # delay histogram for all message -system.ruby.delayHist | 2936 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message -system.ruby.delayHist::total 2936 # delay histogram for all message -system.ruby.outstanding_req_hist::bucket_size 1 -system.ruby.outstanding_req_hist::max_bucket 9 -system.ruby.outstanding_req_hist::samples 7659 -system.ruby.outstanding_req_hist::mean 1 -system.ruby.outstanding_req_hist::gmean 1 -system.ruby.outstanding_req_hist | 0 0.00% 0.00% | 7659 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.outstanding_req_hist::total 7659 -system.ruby.latency_hist::bucket_size 64 -system.ruby.latency_hist::max_bucket 639 -system.ruby.latency_hist::samples 7658 -system.ruby.latency_hist::mean 14.083312 -system.ruby.latency_hist::gmean 5.240199 -system.ruby.latency_hist::stdev 27.247033 -system.ruby.latency_hist | 7337 95.81% 95.81% | 269 3.51% 99.32% | 34 0.44% 99.76% | 10 0.13% 99.90% | 4 0.05% 99.95% | 3 0.04% 99.99% | 0 0.00% 99.99% | 1 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.latency_hist::total 7658 -system.ruby.hit_latency_hist::bucket_size 1 -system.ruby.hit_latency_hist::max_bucket 9 -system.ruby.hit_latency_hist::samples 6188 -system.ruby.hit_latency_hist::mean 3 -system.ruby.hit_latency_hist::gmean 3.000000 -system.ruby.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 6188 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.hit_latency_hist::total 6188 -system.ruby.miss_latency_hist::bucket_size 64 -system.ruby.miss_latency_hist::max_bucket 639 -system.ruby.miss_latency_hist::samples 1470 -system.ruby.miss_latency_hist::mean 60.738776 -system.ruby.miss_latency_hist::gmean 54.828482 -system.ruby.miss_latency_hist::stdev 34.263958 -system.ruby.miss_latency_hist | 1149 78.16% 78.16% | 269 18.30% 96.46% | 34 2.31% 98.78% | 10 0.68% 99.46% | 4 0.27% 99.73% | 3 0.20% 99.93% | 0 0.00% 99.93% | 1 0.07% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.miss_latency_hist::total 1470 -system.ruby.Directory.incomplete_times 1469 -system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.ruby.l1_cntrl0.cacheMemory.demand_hits 6188 # Number of cache demand hits -system.ruby.l1_cntrl0.cacheMemory.demand_misses 1470 # Number of cache demand misses -system.ruby.l1_cntrl0.cacheMemory.demand_accesses 7658 # Number of cache demand accesses +system.mem_ctrls.avgWrQLen 25.24 # Average write queue length when enqueuing +system.mem_ctrls.readRowHits 618 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 892 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 66.52 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate 91.49 # Row buffer hit rate for writes +system.mem_ctrls.avgGap 39.30 # Average gap between requests +system.mem_ctrls.pageHitRate 79.31 # Row buffer hit rate, read and write combined +system.mem_ctrls_0.actEnergy 559440 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 310800 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 1684800 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 1327104 # Energy for write commands per rank (pJ) +system.mem_ctrls_0.refreshEnergy 7119840 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_0.actBackEnergy 54116712 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 18087600 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.totalEnergy 83206296 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 761.516108 # Core power per rank (mW) +system.mem_ctrls_0.memoryStateTime::IDLE 29701 # Time in different power states +system.mem_ctrls_0.memoryStateTime::REF 3640 # Time in different power states +system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 76066 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls_1.actEnergy 2079000 # Energy for activate commands per rank (pJ) +system.mem_ctrls_1.preEnergy 1155000 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_1.readEnergy 9372480 # Energy for read commands per rank (pJ) +system.mem_ctrls_1.writeEnergy 7993728 # Energy for write commands per rank (pJ) +system.mem_ctrls_1.refreshEnergy 7119840 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_1.actBackEnergy 74259144 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 418800 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.totalEnergy 102397992 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 937.161297 # Core power per rank (mW) +system.mem_ctrls_1.memoryStateTime::IDLE 278 # Time in different power states +system.mem_ctrls_1.memoryStateTime::REF 3640 # Time in different power states +system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 105360 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.clk_domain.clock 1 # Clock period in ticks -system.ruby.network.routers0.percent_links_utilized 6.354538 -system.ruby.network.routers0.msg_count.Control::2 1470 -system.ruby.network.routers0.msg_count.Data::2 1466 -system.ruby.network.routers0.msg_count.Response_Data::4 1470 -system.ruby.network.routers0.msg_count.Writeback_Control::3 1466 -system.ruby.network.routers0.msg_bytes.Control::2 11760 -system.ruby.network.routers0.msg_bytes.Data::2 105552 -system.ruby.network.routers0.msg_bytes.Response_Data::4 105840 -system.ruby.network.routers0.msg_bytes.Writeback_Control::3 11728 -system.ruby.network.routers1.percent_links_utilized 6.354538 -system.ruby.network.routers1.msg_count.Control::2 1470 -system.ruby.network.routers1.msg_count.Data::2 1466 -system.ruby.network.routers1.msg_count.Response_Data::4 1470 -system.ruby.network.routers1.msg_count.Writeback_Control::3 1466 -system.ruby.network.routers1.msg_bytes.Control::2 11760 -system.ruby.network.routers1.msg_bytes.Data::2 105552 -system.ruby.network.routers1.msg_bytes.Response_Data::4 105840 -system.ruby.network.routers1.msg_bytes.Writeback_Control::3 11728 -system.ruby.network.routers2.percent_links_utilized 6.354538 -system.ruby.network.routers2.msg_count.Control::2 1470 -system.ruby.network.routers2.msg_count.Data::2 1466 -system.ruby.network.routers2.msg_count.Response_Data::4 1470 -system.ruby.network.routers2.msg_count.Writeback_Control::3 1466 -system.ruby.network.routers2.msg_bytes.Control::2 11760 -system.ruby.network.routers2.msg_bytes.Data::2 105552 -system.ruby.network.routers2.msg_bytes.Response_Data::4 105840 -system.ruby.network.routers2.msg_bytes.Writeback_Control::3 11728 -system.ruby.network.msg_count.Control 4410 -system.ruby.network.msg_count.Data 4398 -system.ruby.network.msg_count.Response_Data 4410 -system.ruby.network.msg_count.Writeback_Control 4398 -system.ruby.network.msg_byte.Control 35280 -system.ruby.network.msg_byte.Data 316656 -system.ruby.network.msg_byte.Response_Data 317520 -system.ruby.network.msg_byte.Writeback_Control 35184 system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses system.cpu.dtb.read_accesses 0 # DTB read accesses @@ -359,7 +288,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 7 # Number of system calls -system.cpu.numCycles 115508 # number of cpu cycles simulated +system.cpu.numCycles 115467 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 5624 # Number of instructions committed @@ -378,7 +307,7 @@ system.cpu.num_mem_refs 2034 # nu system.cpu.num_load_insts 1132 # Number of load instructions system.cpu.num_store_insts 902 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 115508 # Number of busy cycles +system.cpu.num_busy_cycles 115467 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 883 # Number of branches fetched @@ -417,32 +346,108 @@ system.cpu.op_class::MemWrite 902 16.04% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 5625 # Class of executed instruction -system.ruby.network.routers0.throttle0.link_utilization 6.361464 +system.ruby.clk_domain.clock 1 # Clock period in ticks +system.ruby.delayHist::bucket_size 1 # delay histogram for all message +system.ruby.delayHist::max_bucket 9 # delay histogram for all message +system.ruby.delayHist::samples 2936 # delay histogram for all message +system.ruby.delayHist | 2936 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message +system.ruby.delayHist::total 2936 # delay histogram for all message +system.ruby.outstanding_req_hist::bucket_size 1 +system.ruby.outstanding_req_hist::max_bucket 9 +system.ruby.outstanding_req_hist::samples 7659 +system.ruby.outstanding_req_hist::mean 1 +system.ruby.outstanding_req_hist::gmean 1 +system.ruby.outstanding_req_hist | 0 0.00% 0.00% | 7659 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.outstanding_req_hist::total 7659 +system.ruby.latency_hist::bucket_size 64 +system.ruby.latency_hist::max_bucket 639 +system.ruby.latency_hist::samples 7658 +system.ruby.latency_hist::mean 14.077958 +system.ruby.latency_hist::gmean 5.242569 +system.ruby.latency_hist::stdev 26.858459 +system.ruby.latency_hist | 7322 95.61% 95.61% | 283 3.70% 99.31% | 37 0.48% 99.79% | 6 0.08% 99.87% | 9 0.12% 99.99% | 1 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.latency_hist::total 7658 +system.ruby.hit_latency_hist::bucket_size 1 +system.ruby.hit_latency_hist::max_bucket 9 +system.ruby.hit_latency_hist::samples 6188 +system.ruby.hit_latency_hist::mean 3 +system.ruby.hit_latency_hist::gmean 3.000000 +system.ruby.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 6188 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.hit_latency_hist::total 6188 +system.ruby.miss_latency_hist::bucket_size 64 +system.ruby.miss_latency_hist::max_bucket 639 +system.ruby.miss_latency_hist::samples 1470 +system.ruby.miss_latency_hist::mean 60.710884 +system.ruby.miss_latency_hist::gmean 54.957755 +system.ruby.miss_latency_hist::stdev 32.665540 +system.ruby.miss_latency_hist | 1134 77.14% 77.14% | 283 19.25% 96.39% | 37 2.52% 98.91% | 6 0.41% 99.32% | 9 0.61% 99.93% | 1 0.07% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.miss_latency_hist::total 1470 +system.ruby.Directory.incomplete_times 1469 +system.ruby.l1_cntrl0.cacheMemory.demand_hits 6188 # Number of cache demand hits +system.ruby.l1_cntrl0.cacheMemory.demand_misses 1470 # Number of cache demand misses +system.ruby.l1_cntrl0.cacheMemory.demand_accesses 7658 # Number of cache demand accesses +system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks +system.ruby.network.routers0.percent_links_utilized 6.356795 +system.ruby.network.routers0.msg_count.Control::2 1470 +system.ruby.network.routers0.msg_count.Data::2 1466 +system.ruby.network.routers0.msg_count.Response_Data::4 1470 +system.ruby.network.routers0.msg_count.Writeback_Control::3 1466 +system.ruby.network.routers0.msg_bytes.Control::2 11760 +system.ruby.network.routers0.msg_bytes.Data::2 105552 +system.ruby.network.routers0.msg_bytes.Response_Data::4 105840 +system.ruby.network.routers0.msg_bytes.Writeback_Control::3 11728 +system.ruby.network.routers1.percent_links_utilized 6.356795 +system.ruby.network.routers1.msg_count.Control::2 1470 +system.ruby.network.routers1.msg_count.Data::2 1466 +system.ruby.network.routers1.msg_count.Response_Data::4 1470 +system.ruby.network.routers1.msg_count.Writeback_Control::3 1466 +system.ruby.network.routers1.msg_bytes.Control::2 11760 +system.ruby.network.routers1.msg_bytes.Data::2 105552 +system.ruby.network.routers1.msg_bytes.Response_Data::4 105840 +system.ruby.network.routers1.msg_bytes.Writeback_Control::3 11728 +system.ruby.network.routers2.percent_links_utilized 6.356795 +system.ruby.network.routers2.msg_count.Control::2 1470 +system.ruby.network.routers2.msg_count.Data::2 1466 +system.ruby.network.routers2.msg_count.Response_Data::4 1470 +system.ruby.network.routers2.msg_count.Writeback_Control::3 1466 +system.ruby.network.routers2.msg_bytes.Control::2 11760 +system.ruby.network.routers2.msg_bytes.Data::2 105552 +system.ruby.network.routers2.msg_bytes.Response_Data::4 105840 +system.ruby.network.routers2.msg_bytes.Writeback_Control::3 11728 +system.ruby.network.msg_count.Control 4410 +system.ruby.network.msg_count.Data 4398 +system.ruby.network.msg_count.Response_Data 4410 +system.ruby.network.msg_count.Writeback_Control 4398 +system.ruby.network.msg_byte.Control 35280 +system.ruby.network.msg_byte.Data 316656 +system.ruby.network.msg_byte.Response_Data 317520 +system.ruby.network.msg_byte.Writeback_Control 35184 +system.ruby.network.routers0.throttle0.link_utilization 6.363723 system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1470 system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 1466 system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 105840 system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 11728 -system.ruby.network.routers0.throttle1.link_utilization 6.347612 +system.ruby.network.routers0.throttle1.link_utilization 6.349866 system.ruby.network.routers0.throttle1.msg_count.Control::2 1470 system.ruby.network.routers0.throttle1.msg_count.Data::2 1466 system.ruby.network.routers0.throttle1.msg_bytes.Control::2 11760 system.ruby.network.routers0.throttle1.msg_bytes.Data::2 105552 -system.ruby.network.routers1.throttle0.link_utilization 6.347612 +system.ruby.network.routers1.throttle0.link_utilization 6.349866 system.ruby.network.routers1.throttle0.msg_count.Control::2 1470 system.ruby.network.routers1.throttle0.msg_count.Data::2 1466 system.ruby.network.routers1.throttle0.msg_bytes.Control::2 11760 system.ruby.network.routers1.throttle0.msg_bytes.Data::2 105552 -system.ruby.network.routers1.throttle1.link_utilization 6.361464 +system.ruby.network.routers1.throttle1.link_utilization 6.363723 system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 1470 system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 1466 system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 105840 system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 11728 -system.ruby.network.routers2.throttle0.link_utilization 6.361464 +system.ruby.network.routers2.throttle0.link_utilization 6.363723 system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 1470 system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 1466 system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 105840 system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 11728 -system.ruby.network.routers2.throttle1.link_utilization 6.347612 +system.ruby.network.routers2.throttle1.link_utilization 6.349866 system.ruby.network.routers2.throttle1.msg_count.Control::2 1470 system.ruby.network.routers2.throttle1.msg_count.Data::2 1466 system.ruby.network.routers2.throttle1.msg_bytes.Control::2 11760 @@ -457,13 +462,13 @@ system.ruby.delayVCHist.vnet_2::max_bucket 9 # system.ruby.delayVCHist.vnet_2::samples 1466 # delay histogram for vnet_2 system.ruby.delayVCHist.vnet_2 | 1466 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2 system.ruby.delayVCHist.vnet_2::total 1466 # delay histogram for vnet_2 -system.ruby.LD.latency_hist::bucket_size 64 -system.ruby.LD.latency_hist::max_bucket 639 +system.ruby.LD.latency_hist::bucket_size 32 +system.ruby.LD.latency_hist::max_bucket 319 system.ruby.LD.latency_hist::samples 1132 -system.ruby.LD.latency_hist::mean 35.522968 -system.ruby.LD.latency_hist::gmean 16.130611 -system.ruby.LD.latency_hist::stdev 37.257775 -system.ruby.LD.latency_hist | 989 87.37% 87.37% | 116 10.25% 97.61% | 20 1.77% 99.38% | 4 0.35% 99.73% | 2 0.18% 99.91% | 1 0.09% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.latency_hist::mean 35.492049 +system.ruby.LD.latency_hist::gmean 16.147834 +system.ruby.LD.latency_hist::stdev 37.303839 +system.ruby.LD.latency_hist | 465 41.08% 41.08% | 518 45.76% 86.84% | 124 10.95% 97.79% | 3 0.27% 98.06% | 3 0.27% 98.32% | 12 1.06% 99.38% | 2 0.18% 99.56% | 0 0.00% 99.56% | 3 0.27% 99.82% | 2 0.18% 100.00% system.ruby.LD.latency_hist::total 1132 system.ruby.LD.hit_latency_hist::bucket_size 1 system.ruby.LD.hit_latency_hist::max_bucket 9 @@ -472,21 +477,21 @@ system.ruby.LD.hit_latency_hist::mean 3 system.ruby.LD.hit_latency_hist::gmean 3.000000 system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 465 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.hit_latency_hist::total 465 -system.ruby.LD.miss_latency_hist::bucket_size 64 -system.ruby.LD.miss_latency_hist::max_bucket 639 +system.ruby.LD.miss_latency_hist::bucket_size 32 +system.ruby.LD.miss_latency_hist::max_bucket 319 system.ruby.LD.miss_latency_hist::samples 667 -system.ruby.LD.miss_latency_hist::mean 58.196402 -system.ruby.LD.miss_latency_hist::gmean 52.112336 -system.ruby.LD.miss_latency_hist::stdev 33.226027 -system.ruby.LD.miss_latency_hist | 524 78.56% 78.56% | 116 17.39% 95.95% | 20 3.00% 98.95% | 4 0.60% 99.55% | 2 0.30% 99.85% | 1 0.15% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.miss_latency_hist::mean 58.143928 +system.ruby.LD.miss_latency_hist::gmean 52.206801 +system.ruby.LD.miss_latency_hist::stdev 33.349415 +system.ruby.LD.miss_latency_hist | 0 0.00% 0.00% | 518 77.66% 77.66% | 124 18.59% 96.25% | 3 0.45% 96.70% | 3 0.45% 97.15% | 12 1.80% 98.95% | 2 0.30% 99.25% | 0 0.00% 99.25% | 3 0.45% 99.70% | 2 0.30% 100.00% system.ruby.LD.miss_latency_hist::total 667 -system.ruby.ST.latency_hist::bucket_size 64 -system.ruby.ST.latency_hist::max_bucket 639 +system.ruby.ST.latency_hist::bucket_size 32 +system.ruby.ST.latency_hist::max_bucket 319 system.ruby.ST.latency_hist::samples 901 -system.ruby.ST.latency_hist::mean 15.558269 -system.ruby.ST.latency_hist::gmean 5.883337 -system.ruby.ST.latency_hist::stdev 27.738104 -system.ruby.ST.latency_hist | 860 95.45% 95.45% | 33 3.66% 99.11% | 6 0.67% 99.78% | 1 0.11% 99.89% | 0 0.00% 99.89% | 1 0.11% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.latency_hist::mean 14.748058 +system.ruby.ST.latency_hist::gmean 5.824702 +system.ruby.ST.latency_hist::stdev 24.783906 +system.ruby.ST.latency_hist | 684 75.92% 75.92% | 183 20.31% 96.23% | 29 3.22% 99.45% | 0 0.00% 99.45% | 2 0.22% 99.67% | 2 0.22% 99.89% | 0 0.00% 99.89% | 0 0.00% 99.89% | 1 0.11% 100.00% | 0 0.00% 100.00% system.ruby.ST.latency_hist::total 901 system.ruby.ST.hit_latency_hist::bucket_size 1 system.ruby.ST.hit_latency_hist::max_bucket 9 @@ -495,21 +500,21 @@ system.ruby.ST.hit_latency_hist::mean 3 system.ruby.ST.hit_latency_hist::gmean 3.000000 system.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 684 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.ST.hit_latency_hist::total 684 -system.ruby.ST.miss_latency_hist::bucket_size 64 -system.ruby.ST.miss_latency_hist::max_bucket 639 +system.ruby.ST.miss_latency_hist::bucket_size 32 +system.ruby.ST.miss_latency_hist::max_bucket 319 system.ruby.ST.miss_latency_hist::samples 217 -system.ruby.ST.miss_latency_hist::mean 55.142857 -system.ruby.ST.miss_latency_hist::gmean 49.160125 -system.ruby.ST.miss_latency_hist::stdev 33.648687 -system.ruby.ST.miss_latency_hist | 176 81.11% 81.11% | 33 15.21% 96.31% | 6 2.76% 99.08% | 1 0.46% 99.54% | 0 0.00% 99.54% | 1 0.46% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.miss_latency_hist::mean 51.778802 +system.ruby.ST.miss_latency_hist::gmean 47.157588 +system.ruby.ST.miss_latency_hist::stdev 27.288529 +system.ruby.ST.miss_latency_hist | 0 0.00% 0.00% | 183 84.33% 84.33% | 29 13.36% 97.70% | 0 0.00% 97.70% | 2 0.92% 98.62% | 2 0.92% 99.54% | 0 0.00% 99.54% | 0 0.00% 99.54% | 1 0.46% 100.00% | 0 0.00% 100.00% system.ruby.ST.miss_latency_hist::total 217 system.ruby.IFETCH.latency_hist::bucket_size 64 system.ruby.IFETCH.latency_hist::max_bucket 639 system.ruby.IFETCH.latency_hist::samples 5625 -system.ruby.IFETCH.latency_hist::mean 9.532444 -system.ruby.IFETCH.latency_hist::gmean 4.102291 -system.ruby.IFETCH.latency_hist::stdev 22.246367 -system.ruby.IFETCH.latency_hist | 5488 97.56% 97.56% | 120 2.13% 99.70% | 8 0.14% 99.84% | 5 0.09% 99.93% | 2 0.04% 99.96% | 1 0.02% 99.98% | 0 0.00% 99.98% | 1 0.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.latency_hist::mean 9.661156 +system.ruby.IFETCH.latency_hist::gmean 4.110524 +system.ruby.IFETCH.latency_hist::stdev 22.183687 +system.ruby.IFETCH.latency_hist | 5472 97.28% 97.28% | 127 2.26% 99.54% | 18 0.32% 99.86% | 4 0.07% 99.93% | 3 0.05% 99.98% | 1 0.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.latency_hist::total 5625 system.ruby.IFETCH.hit_latency_hist::bucket_size 1 system.ruby.IFETCH.hit_latency_hist::max_bucket 9 @@ -521,18 +526,18 @@ system.ruby.IFETCH.hit_latency_hist::total 5039 system.ruby.IFETCH.miss_latency_hist::bucket_size 64 system.ruby.IFETCH.miss_latency_hist::max_bucket 639 system.ruby.IFETCH.miss_latency_hist::samples 586 -system.ruby.IFETCH.miss_latency_hist::mean 65.704778 -system.ruby.IFETCH.miss_latency_hist::gmean 60.488386 -system.ruby.IFETCH.miss_latency_hist::stdev 35.064530 -system.ruby.IFETCH.miss_latency_hist | 449 76.62% 76.62% | 120 20.48% 97.10% | 8 1.37% 98.46% | 5 0.85% 99.32% | 2 0.34% 99.66% | 1 0.17% 99.83% | 0 0.00% 99.83% | 1 0.17% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.miss_latency_hist::mean 66.940273 +system.ruby.IFETCH.miss_latency_hist::gmean 61.663848 +system.ruby.IFETCH.miss_latency_hist::stdev 32.593558 +system.ruby.IFETCH.miss_latency_hist | 433 73.89% 73.89% | 127 21.67% 95.56% | 18 3.07% 98.63% | 4 0.68% 99.32% | 3 0.51% 99.83% | 1 0.17% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.miss_latency_hist::total 586 system.ruby.Directory.miss_mach_latency_hist::bucket_size 64 system.ruby.Directory.miss_mach_latency_hist::max_bucket 639 system.ruby.Directory.miss_mach_latency_hist::samples 1470 -system.ruby.Directory.miss_mach_latency_hist::mean 60.738776 -system.ruby.Directory.miss_mach_latency_hist::gmean 54.828482 -system.ruby.Directory.miss_mach_latency_hist::stdev 34.263958 -system.ruby.Directory.miss_mach_latency_hist | 1149 78.16% 78.16% | 269 18.30% 96.46% | 34 2.31% 98.78% | 10 0.68% 99.46% | 4 0.27% 99.73% | 3 0.20% 99.93% | 0 0.00% 99.93% | 1 0.07% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_mach_latency_hist::mean 60.710884 +system.ruby.Directory.miss_mach_latency_hist::gmean 54.957755 +system.ruby.Directory.miss_mach_latency_hist::stdev 32.665540 +system.ruby.Directory.miss_mach_latency_hist | 1134 77.14% 77.14% | 283 19.25% 96.39% | 37 2.52% 98.91% | 6 0.41% 99.32% | 9 0.61% 99.93% | 1 0.07% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.Directory.miss_mach_latency_hist::total 1470 system.ruby.Directory.miss_latency_hist.issue_to_initial_request::bucket_size 1 system.ruby.Directory.miss_latency_hist.issue_to_initial_request::max_bucket 9 @@ -560,30 +565,38 @@ system.ruby.Directory.miss_latency_hist.first_response_to_completion::gmean 7 system.ruby.Directory.miss_latency_hist.first_response_to_completion::stdev nan system.ruby.Directory.miss_latency_hist.first_response_to_completion | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% system.ruby.Directory.miss_latency_hist.first_response_to_completion::total 1 -system.ruby.LD.Directory.miss_type_mach_latency_hist::bucket_size 64 -system.ruby.LD.Directory.miss_type_mach_latency_hist::max_bucket 639 +system.ruby.LD.Directory.miss_type_mach_latency_hist::bucket_size 32 +system.ruby.LD.Directory.miss_type_mach_latency_hist::max_bucket 319 system.ruby.LD.Directory.miss_type_mach_latency_hist::samples 667 -system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 58.196402 -system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 52.112336 -system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 33.226027 -system.ruby.LD.Directory.miss_type_mach_latency_hist | 524 78.56% 78.56% | 116 17.39% 95.95% | 20 3.00% 98.95% | 4 0.60% 99.55% | 2 0.30% 99.85% | 1 0.15% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 58.143928 +system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 52.206801 +system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 33.349415 +system.ruby.LD.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 518 77.66% 77.66% | 124 18.59% 96.25% | 3 0.45% 96.70% | 3 0.45% 97.15% | 12 1.80% 98.95% | 2 0.30% 99.25% | 0 0.00% 99.25% | 3 0.45% 99.70% | 2 0.30% 100.00% system.ruby.LD.Directory.miss_type_mach_latency_hist::total 667 -system.ruby.ST.Directory.miss_type_mach_latency_hist::bucket_size 64 -system.ruby.ST.Directory.miss_type_mach_latency_hist::max_bucket 639 +system.ruby.ST.Directory.miss_type_mach_latency_hist::bucket_size 32 +system.ruby.ST.Directory.miss_type_mach_latency_hist::max_bucket 319 system.ruby.ST.Directory.miss_type_mach_latency_hist::samples 217 -system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 55.142857 -system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 49.160125 -system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 33.648687 -system.ruby.ST.Directory.miss_type_mach_latency_hist | 176 81.11% 81.11% | 33 15.21% 96.31% | 6 2.76% 99.08% | 1 0.46% 99.54% | 0 0.00% 99.54% | 1 0.46% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 51.778802 +system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 47.157588 +system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 27.288529 +system.ruby.ST.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 183 84.33% 84.33% | 29 13.36% 97.70% | 0 0.00% 97.70% | 2 0.92% 98.62% | 2 0.92% 99.54% | 0 0.00% 99.54% | 0 0.00% 99.54% | 1 0.46% 100.00% | 0 0.00% 100.00% system.ruby.ST.Directory.miss_type_mach_latency_hist::total 217 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::bucket_size 64 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::max_bucket 639 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::samples 586 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean 65.704778 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 60.488386 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 35.064530 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 449 76.62% 76.62% | 120 20.48% 97.10% | 8 1.37% 98.46% | 5 0.85% 99.32% | 2 0.34% 99.66% | 1 0.17% 99.83% | 0 0.00% 99.83% | 1 0.17% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean 66.940273 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 61.663848 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 32.593558 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 433 73.89% 73.89% | 127 21.67% 95.56% | 18 3.07% 98.63% | 4 0.68% 99.32% | 3 0.51% 99.83% | 1 0.17% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total 586 +system.ruby.Directory_Controller.GETX 1470 0.00% 0.00% +system.ruby.Directory_Controller.PUTX 1466 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Data 1470 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Ack 1466 0.00% 0.00% +system.ruby.Directory_Controller.I.GETX 1470 0.00% 0.00% +system.ruby.Directory_Controller.M.PUTX 1466 0.00% 0.00% +system.ruby.Directory_Controller.IM.Memory_Data 1470 0.00% 0.00% +system.ruby.Directory_Controller.MI.Memory_Ack 1466 0.00% 0.00% system.ruby.L1Cache_Controller.Load 1132 0.00% 0.00% system.ruby.L1Cache_Controller.Ifetch 5625 0.00% 0.00% system.ruby.L1Cache_Controller.Store 901 0.00% 0.00% @@ -600,13 +613,5 @@ system.ruby.L1Cache_Controller.M.Replacement 1466 0.00% 0.00% system.ruby.L1Cache_Controller.MI.Writeback_Ack 1466 0.00% 0.00% system.ruby.L1Cache_Controller.IS.Data 1253 0.00% 0.00% system.ruby.L1Cache_Controller.IM.Data 217 0.00% 0.00% -system.ruby.Directory_Controller.GETX 1470 0.00% 0.00% -system.ruby.Directory_Controller.PUTX 1466 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Data 1470 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Ack 1466 0.00% 0.00% -system.ruby.Directory_Controller.I.GETX 1470 0.00% 0.00% -system.ruby.Directory_Controller.M.PUTX 1466 0.00% 0.00% -system.ruby.Directory_Controller.IM.Memory_Data 1470 0.00% 0.00% -system.ruby.Directory_Controller.MI.Memory_Ack 1466 0.00% 0.00% ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt index b652069ee..e81ca8aaa 100644 --- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000019 # Nu sim_ticks 18857500 # Number of ticks simulated final_tick 18857500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 71546 # Simulator instruction rate (inst/s) -host_op_rate 71536 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 232873039 # Simulator tick rate (ticks/s) -host_mem_usage 233800 # Number of bytes of host memory used -host_seconds 0.08 # Real time elapsed on the host +host_inst_rate 101158 # Simulator instruction rate (inst/s) +host_op_rate 101133 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 329193143 # Simulator tick rate (ticks/s) +host_mem_usage 288984 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host sim_insts 5792 # Number of instructions simulated sim_ops 5792 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -222,53 +222,34 @@ system.physmem.readRowHitRate 80.18 # Ro system.physmem.writeRowHitRate nan # Row buffer hit rate for writes system.physmem.avgGap 42171.17 # Average gap between requests system.physmem.pageHitRate 80.18 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 11000 # Time in different power states -system.physmem.memoryStateTime::REF 520000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 15315250 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 476280 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 68040 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 259875 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 37125 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 2644200 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 288600 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 1017120 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 1017120 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 10793520 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 8055810 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 31500 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 2433000 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 15222495 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 11899695 # Total energy per rank (pJ) -system.physmem.averagePower::0 961.471341 # Core power per rank (mW) -system.physmem.averagePower::1 751.599242 # Core power per rank (mW) -system.membus.trans_dist::ReadReq 397 # Transaction distribution -system.membus.trans_dist::ReadResp 397 # Transaction distribution -system.membus.trans_dist::ReadExReq 47 # Transaction distribution -system.membus.trans_dist::ReadExResp 47 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 888 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 888 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 28416 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 28416 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 444 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 444 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 444 # Request fanout histogram -system.membus.reqLayer0.occupancy 555500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.9 # Layer utilization (%) -system.membus.respLayer1.occupancy 4160750 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 22.1 # Layer utilization (%) -system.cpu_clk_domain.clock 500 # Clock period in ticks +system.physmem_0.actEnergy 476280 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 259875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 2644200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 10793520 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 31500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 15222495 # Total energy per rank (pJ) +system.physmem_0.averagePower 961.471341 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 11000 # Time in different power states +system.physmem_0.memoryStateTime::REF 520000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 15315250 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 68040 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 37125 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 288600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 8055810 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 2433000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 11899695 # Total energy per rank (pJ) +system.physmem_1.averagePower 751.599242 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 4725250 # Time in different power states +system.physmem_1.memoryStateTime::REF 520000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 11341250 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.branchPred.lookups 2332 # Number of BP lookups system.cpu.branchPred.condPredicted 1883 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 415 # Number of conditional branches incorrect @@ -278,6 +259,7 @@ system.cpu.branchPred.BTBCorrect 0 # Nu system.cpu.branchPred.BTBHitPct 34.230968 # BTB Hit Percentage system.cpu.branchPred.usedRAS 219 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 31 # Number of incorrect RAS predictions. +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses system.cpu.dtb.read_accesses 0 # DTB read accesses @@ -589,34 +571,118 @@ system.cpu.int_regfile_reads 13744 # nu system.cpu.int_regfile_writes 7176 # number of integer regfile writes system.cpu.fp_regfile_reads 25 # number of floating regfile reads system.cpu.fp_regfile_writes 2 # number of floating regfile writes -system.cpu.toL2Bus.trans_dist::ReadReq 405 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 404 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 47 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 47 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 699 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 204 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 903 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 22336 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6528 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 28864 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 452 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 452 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 452 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 226000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 584250 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 3.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 162500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 64.061622 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 2261 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 102 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 22.166667 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 64.061622 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.015640 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.015640 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 102 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 64 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.024902 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 5528 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 5528 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 1554 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1554 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 707 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 707 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 2261 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2261 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2261 # number of overall hits +system.cpu.dcache.overall_hits::total 2261 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 113 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 113 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 339 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 339 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 452 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 452 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 452 # number of overall misses +system.cpu.dcache.overall_misses::total 452 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 8122250 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 8122250 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 22327496 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 22327496 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 30449746 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 30449746 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 30449746 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 30449746 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1667 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1667 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 1046 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 1046 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 2713 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2713 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2713 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2713 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.067786 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.067786 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.324092 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.324092 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.166605 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.166605 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.166605 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.166605 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 71878.318584 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 71878.318584 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65862.820059 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 65862.820059 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 67366.694690 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 67366.694690 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 67366.694690 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 67366.694690 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 597 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 6 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 99.500000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 58 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 58 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 292 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 292 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 350 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 350 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 350 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 350 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 55 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 47 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 47 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 102 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 102 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 102 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 102 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4203250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4203250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3795248 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3795248 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7998498 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 7998498 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7998498 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7998498 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032993 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032993 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044933 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044933 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.037597 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.037597 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.037597 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.037597 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 76422.727273 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 76422.727273 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80749.957447 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80749.957447 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78416.647059 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 78416.647059 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78416.647059 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 78416.647059 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements system.cpu.icache.tags.tagsinuse 170.472010 # Cycle average of tags in use system.cpu.icache.tags.total_refs 1391 # Total number of references to valid blocks. @@ -841,117 +907,56 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56178.052326 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65782.178218 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58357.865169 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 64.061622 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 2261 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 102 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 22.166667 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 64.061622 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.015640 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.015640 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 102 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 64 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.024902 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 5528 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 5528 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 1554 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1554 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 707 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 707 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2261 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2261 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2261 # number of overall hits -system.cpu.dcache.overall_hits::total 2261 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 113 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 113 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 339 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 339 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 452 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 452 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 452 # number of overall misses -system.cpu.dcache.overall_misses::total 452 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 8122250 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 8122250 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 22327496 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 22327496 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 30449746 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 30449746 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 30449746 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 30449746 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1667 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1667 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 1046 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 1046 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2713 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2713 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2713 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2713 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.067786 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.067786 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.324092 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.324092 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.166605 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.166605 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.166605 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.166605 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 71878.318584 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 71878.318584 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65862.820059 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 65862.820059 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 67366.694690 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 67366.694690 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 67366.694690 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 67366.694690 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 597 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 6 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 99.500000 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 58 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 58 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 292 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 292 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 350 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 350 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 350 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 350 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 55 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 47 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 47 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 102 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 102 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 102 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 102 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4203250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4203250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3795248 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3795248 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7998498 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7998498 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7998498 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7998498 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032993 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032993 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044933 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044933 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.037597 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.037597 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.037597 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.037597 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 76422.727273 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 76422.727273 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80749.957447 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80749.957447 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78416.647059 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 78416.647059 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78416.647059 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 78416.647059 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.trans_dist::ReadReq 405 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 404 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 47 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 47 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 699 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 204 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 903 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 22336 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6528 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 28864 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 452 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 452 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 452 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 226000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 584250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 3.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 162500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) +system.membus.trans_dist::ReadReq 397 # Transaction distribution +system.membus.trans_dist::ReadResp 397 # Transaction distribution +system.membus.trans_dist::ReadExReq 47 # Transaction distribution +system.membus.trans_dist::ReadExResp 47 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 888 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 888 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 28416 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 28416 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 444 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 444 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 444 # Request fanout histogram +system.membus.reqLayer0.occupancy 555500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.9 # Layer utilization (%) +system.membus.respLayer1.occupancy 4160750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 22.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt index 951c5abaa..33e0e9c43 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000021 # Nu sim_ticks 20927500 # Number of ticks simulated final_tick 20927500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 61359 # Simulator instruction rate (inst/s) -host_op_rate 61351 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 240990471 # Simulator tick rate (ticks/s) -host_mem_usage 234980 # Number of bytes of host memory used -host_seconds 0.09 # Real time elapsed on the host +host_inst_rate 82286 # Simulator instruction rate (inst/s) +host_op_rate 82268 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 323129777 # Simulator tick rate (ticks/s) +host_mem_usage 289972 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host sim_insts 5327 # Number of instructions simulated sim_ops 5327 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -220,53 +220,34 @@ system.physmem.readRowHitRate 80.14 # Ro system.physmem.writeRowHitRate nan # Row buffer hit rate for writes system.physmem.avgGap 49309.69 # Average gap between requests system.physmem.pageHitRate 80.14 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 13500 # Time in different power states -system.physmem.memoryStateTime::REF 520000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 15312750 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 294840 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 196560 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 160875 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 107250 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 1497600 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 1107600 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 1017120 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 1017120 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 10702035 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 10576350 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 111750 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 222000 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 13784220 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 13226880 # Total energy per rank (pJ) -system.physmem.averagePower::0 870.628138 # Core power per rank (mW) -system.physmem.averagePower::1 835.425865 # Core power per rank (mW) -system.membus.trans_dist::ReadReq 342 # Transaction distribution -system.membus.trans_dist::ReadResp 342 # Transaction distribution -system.membus.trans_dist::ReadExReq 81 # Transaction distribution -system.membus.trans_dist::ReadExResp 81 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 846 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 846 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 27072 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 27072 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 423 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 423 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 423 # Request fanout histogram -system.membus.reqLayer0.occupancy 501500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.4 # Layer utilization (%) -system.membus.respLayer1.occupancy 3931250 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 18.8 # Layer utilization (%) -system.cpu_clk_domain.clock 500 # Clock period in ticks +system.physmem_0.actEnergy 294840 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 160875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1497600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 10702035 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 111750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 13784220 # Total energy per rank (pJ) +system.physmem_0.averagePower 870.628138 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 116500 # Time in different power states +system.physmem_0.memoryStateTime::REF 520000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 15209750 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 196560 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 107250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1107600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 10576350 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 222000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 13226880 # Total energy per rank (pJ) +system.physmem_1.averagePower 835.425865 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 328000 # Time in different power states +system.physmem_1.memoryStateTime::REF 520000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 14998250 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.branchPred.lookups 1636 # Number of BP lookups system.cpu.branchPred.condPredicted 1090 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 897 # Number of conditional branches incorrect @@ -276,6 +257,7 @@ system.cpu.branchPred.BTBCorrect 0 # Nu system.cpu.branchPred.BTBHitPct 43.484736 # BTB Hit Percentage system.cpu.branchPred.usedRAS 67 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 4 # Number of incorrect RAS predictions. +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.workload.num_syscalls 11 # Number of system calls system.cpu.numCycles 41856 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started @@ -337,6 +319,118 @@ system.cpu.stage3.utilization 2.329415 # Pe system.cpu.stage4.idleCycles 38699 # Number of cycles 0 instructions are processed. system.cpu.stage4.runCycles 3157 # Number of cycles 1+ instructions are processed. system.cpu.stage4.utilization 7.542527 # Percentage of cycles stage was utilized (processing insts). +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 85.369863 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 914 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 135 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 6.770370 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 85.369863 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.020842 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.020842 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 135 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 97 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.032959 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 2911 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 2911 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 654 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 654 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 260 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 260 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 914 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 914 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 914 # number of overall hits +system.cpu.dcache.overall_hits::total 914 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 61 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 61 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 413 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 413 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 474 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 474 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 474 # number of overall misses +system.cpu.dcache.overall_misses::total 474 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 4588750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4588750 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 28972250 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 28972250 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 33561000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 33561000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 33561000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 33561000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 715 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 715 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 673 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 673 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 1388 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 1388 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 1388 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 1388 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.085315 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.085315 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.613670 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.613670 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.341499 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.341499 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.341499 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.341499 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 75225.409836 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 75225.409836 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 70150.726392 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 70150.726392 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 70803.797468 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 70803.797468 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 70803.797468 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 70803.797468 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 818 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 31 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 26.387097 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 7 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 7 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 332 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 332 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 339 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 339 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 339 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 339 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 54 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 54 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 81 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 81 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 135 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 135 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 135 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 135 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4091500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4091500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6091750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 6091750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10183250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10183250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10183250 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10183250 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075524 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075524 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.120357 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.120357 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.097262 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.097262 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.097262 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.097262 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 75768.518519 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 75768.518519 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75206.790123 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75206.790123 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75431.481481 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 75431.481481 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75431.481481 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 75431.481481 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements system.cpu.icache.tags.tagsinuse 142.708262 # Cycle average of tags in use system.cpu.icache.tags.total_refs 892 # Total number of references to valid blocks. @@ -427,34 +521,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 70926.116838 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 70926.116838 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 70926.116838 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 345 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 345 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 81 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 81 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 582 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 270 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 852 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18624 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8640 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 27264 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 426 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 426 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 426 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 213000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 486500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 216750 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) system.cpu.l2cache.tags.replacements 0 # number of replacements system.cpu.l2cache.tags.tagsinuse 169.161112 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 3 # Total number of references to valid blocks. @@ -589,117 +655,56 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57807.958478 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62561.567164 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59313.829787 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 85.369863 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 914 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 135 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 6.770370 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 85.369863 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.020842 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.020842 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 135 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 97 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.032959 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 2911 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 2911 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 654 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 654 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 260 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 260 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 914 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 914 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 914 # number of overall hits -system.cpu.dcache.overall_hits::total 914 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 61 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 61 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 413 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 413 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 474 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 474 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 474 # number of overall misses -system.cpu.dcache.overall_misses::total 474 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 4588750 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 4588750 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 28972250 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 28972250 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 33561000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 33561000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 33561000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 33561000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 715 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 715 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 673 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 673 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 1388 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 1388 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 1388 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 1388 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.085315 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.085315 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.613670 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.613670 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.341499 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.341499 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.341499 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.341499 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 75225.409836 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 75225.409836 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 70150.726392 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 70150.726392 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 70803.797468 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 70803.797468 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 70803.797468 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 70803.797468 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 818 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 31 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 26.387097 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 7 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 7 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 332 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 332 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 339 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 339 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 339 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 339 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 54 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 54 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 81 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 81 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 135 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 135 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 135 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 135 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4091500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4091500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6091750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 6091750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10183250 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10183250 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10183250 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10183250 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075524 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075524 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.120357 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.120357 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.097262 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.097262 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.097262 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.097262 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 75768.518519 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 75768.518519 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75206.790123 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75206.790123 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75431.481481 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 75431.481481 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75431.481481 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 75431.481481 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.trans_dist::ReadReq 345 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 345 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 81 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 81 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 582 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 270 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 852 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18624 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8640 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 27264 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 426 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 426 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 426 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 213000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 486500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 2.3 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 216750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) +system.membus.trans_dist::ReadReq 342 # Transaction distribution +system.membus.trans_dist::ReadResp 342 # Transaction distribution +system.membus.trans_dist::ReadExReq 81 # Transaction distribution +system.membus.trans_dist::ReadExResp 81 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 846 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 846 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 27072 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 27072 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 423 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 423 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 423 # Request fanout histogram +system.membus.reqLayer0.occupancy 501500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.4 # Layer utilization (%) +system.membus.respLayer1.occupancy 3931250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 18.8 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt index 0a40cf084..51b100b5f 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000096 # Number of seconds simulated -sim_ticks 95992 # Number of ticks simulated -final_tick 95992 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 95989 # Number of ticks simulated +final_tick 95989 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 28429 # Simulator instruction rate (inst/s) -host_op_rate 28426 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 512186 # Simulator tick rate (ticks/s) -host_mem_usage 435856 # Number of bytes of host memory used -host_seconds 0.19 # Real time elapsed on the host +host_inst_rate 73101 # Simulator instruction rate (inst/s) +host_op_rate 73087 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1316740 # Simulator tick rate (ticks/s) +host_mem_usage 448980 # Number of bytes of host memory used +host_seconds 0.07 # Real time elapsed on the host sim_insts 5327 # Number of instructions simulated sim_ops 5327 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,12 +21,12 @@ system.mem_ctrls.num_reads::ruby.dir_cntrl0 1289 # system.mem_ctrls.num_reads::total 1289 # Number of read requests responded to by this memory system.mem_ctrls.num_writes::ruby.dir_cntrl0 1285 # Number of write requests responded to by this memory system.mem_ctrls.num_writes::total 1285 # Number of write requests responded to by this memory -system.mem_ctrls.bw_read::ruby.dir_cntrl0 859404950 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_read::total 859404950 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::ruby.dir_cntrl0 856738062 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::total 856738062 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_total::ruby.dir_cntrl0 1716143012 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.bw_total::total 1716143012 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_read::ruby.dir_cntrl0 859431810 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 859431810 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::ruby.dir_cntrl0 856764838 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::total 856764838 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::ruby.dir_cntrl0 1716196648 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 1716196648 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrls.readReqs 1289 # Number of read requests accepted system.mem_ctrls.writeReqs 1285 # Number of write requests accepted system.mem_ctrls.readBursts 1289 # Number of DRAM read bursts, including those serviced by the write queue @@ -73,7 +73,7 @@ system.mem_ctrls.perBankWrBursts::14 18 # Pe system.mem_ctrls.perBankWrBursts::15 8 # Per bank write bursts system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrls.totGap 95928 # Total gap between requests +system.mem_ctrls.totGap 95925 # Total gap between requests system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) @@ -217,16 +217,16 @@ system.mem_ctrls.wrPerTurnAround::17 1 2.33% 83.72% # Wr system.mem_ctrls.wrPerTurnAround::18 2 4.65% 88.37% # Writes before turning the bus around for reads system.mem_ctrls.wrPerTurnAround::19 5 11.63% 100.00% # Writes before turning the bus around for reads system.mem_ctrls.wrPerTurnAround::total 43 # Writes before turning the bus around for reads -system.mem_ctrls.totQLat 8746 # Total ticks spent queuing -system.mem_ctrls.totMemAccLat 22027 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.totQLat 8743 # Total ticks spent queuing +system.mem_ctrls.totMemAccLat 22024 # Total ticks spent from burst creation until serviced by the DRAM system.mem_ctrls.totBusLat 3495 # Total ticks spent in databus transfers system.mem_ctrls.avgQLat 12.51 # Average queueing delay per DRAM burst system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst system.mem_ctrls.avgMemAccLat 31.51 # Average memory access latency per DRAM burst -system.mem_ctrls.avgRdBW 466.04 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrls.avgWrBW 472.04 # Average achieved write bandwidth in MiByte/s -system.mem_ctrls.avgRdBWSys 859.40 # Average system read bandwidth in MiByte/s -system.mem_ctrls.avgWrBWSys 856.74 # Average system write bandwidth in MiByte/s +system.mem_ctrls.avgRdBW 466.05 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 472.05 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 859.43 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 856.76 # Average system write bandwidth in MiByte/s system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.mem_ctrls.busUtil 7.33 # Data bus utilization in percentage system.mem_ctrls.busUtilRead 3.64 # Data bus utilization in percentage for reads @@ -239,29 +239,94 @@ system.mem_ctrls.readRowHitRate 70.96 # Ro system.mem_ctrls.writeRowHitRate 92.86 # Row buffer hit rate for writes system.mem_ctrls.avgGap 37.27 # Average gap between requests system.mem_ctrls.pageHitRate 82.13 # Row buffer hit rate, read and write combined -system.mem_ctrls.memoryStateTime::IDLE 3037 # Time in different power states -system.mem_ctrls.memoryStateTime::REF 3120 # Time in different power states -system.mem_ctrls.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls.memoryStateTime::ACT 87552 # Time in different power states -system.mem_ctrls.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrls.actEnergy::0 1035720 # Energy for activate commands per rank (pJ) -system.mem_ctrls.actEnergy::1 672840 # Energy for activate commands per rank (pJ) -system.mem_ctrls.preEnergy::0 575400 # Energy for precharge commands per rank (pJ) -system.mem_ctrls.preEnergy::1 373800 # Energy for precharge commands per rank (pJ) -system.mem_ctrls.readEnergy::0 5229120 # Energy for read commands per rank (pJ) -system.mem_ctrls.readEnergy::1 3257280 # Energy for read commands per rank (pJ) -system.mem_ctrls.writeEnergy::0 4271616 # Energy for write commands per rank (pJ) -system.mem_ctrls.writeEnergy::1 2716416 # Energy for write commands per rank (pJ) -system.mem_ctrls.refreshEnergy::0 6102720 # Energy for refresh commands per rank (pJ) -system.mem_ctrls.refreshEnergy::1 6102720 # Energy for refresh commands per rank (pJ) -system.mem_ctrls.actBackEnergy::0 59194044 # Energy for active background per rank (pJ) -system.mem_ctrls.actBackEnergy::1 56254896 # Energy for active background per rank (pJ) -system.mem_ctrls.preBackEnergy::0 4292400 # Energy for precharge background per rank (pJ) -system.mem_ctrls.preBackEnergy::1 6870600 # Energy for precharge background per rank (pJ) -system.mem_ctrls.totalEnergy::0 80701020 # Total energy per rank (pJ) -system.mem_ctrls.totalEnergy::1 76248552 # Total energy per rank (pJ) -system.mem_ctrls.averagePower::0 861.316185 # Core power per rank (mW) -system.mem_ctrls.averagePower::1 813.795315 # Core power per rank (mW) +system.mem_ctrls_0.actEnergy 1035720 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 575400 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 5229120 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 4271616 # Energy for write commands per rank (pJ) +system.mem_ctrls_0.refreshEnergy 6102720 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_0.actBackEnergy 59194044 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 4292400 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.totalEnergy 80701020 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 861.316185 # Core power per rank (mW) +system.mem_ctrls_0.memoryStateTime::IDLE 6799 # Time in different power states +system.mem_ctrls_0.memoryStateTime::REF 3120 # Time in different power states +system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 83841 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls_1.actEnergy 672840 # Energy for activate commands per rank (pJ) +system.mem_ctrls_1.preEnergy 373800 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_1.readEnergy 3257280 # Energy for read commands per rank (pJ) +system.mem_ctrls_1.writeEnergy 2716416 # Energy for write commands per rank (pJ) +system.mem_ctrls_1.refreshEnergy 6102720 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_1.actBackEnergy 56250108 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 6873000 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.totalEnergy 76246164 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 813.795884 # Core power per rank (mW) +system.mem_ctrls_1.memoryStateTime::IDLE 11133 # Time in different power states +system.mem_ctrls_1.memoryStateTime::REF 3120 # Time in different power states +system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 79453 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.clk_domain.clock 1 # Clock period in ticks +system.cpu.workload.num_syscalls 11 # Number of system calls +system.cpu.numCycles 95989 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 5327 # Number of instructions committed +system.cpu.committedOps 5327 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 4505 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses +system.cpu.num_func_calls 146 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 773 # number of instructions that are conditional controls +system.cpu.num_int_insts 4505 # number of integer instructions +system.cpu.num_fp_insts 0 # number of float instructions +system.cpu.num_int_register_reads 10598 # number of times the integer registers were read +system.cpu.num_int_register_writes 4845 # number of times the integer registers were written +system.cpu.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_mem_refs 1401 # number of memory refs +system.cpu.num_load_insts 723 # Number of load instructions +system.cpu.num_store_insts 678 # Number of store instructions +system.cpu.num_idle_cycles 0.999990 # Number of idle cycles +system.cpu.num_busy_cycles 95988.000010 # Number of busy cycles +system.cpu.not_idle_fraction 0.999990 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.000010 # Percentage of idle cycles +system.cpu.Branches 1121 # Number of branches fetched +system.cpu.op_class::No_OpClass 173 3.22% 3.22% # Class of executed instruction +system.cpu.op_class::IntAlu 3796 70.69% 73.91% # Class of executed instruction +system.cpu.op_class::IntMult 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 73.91% # Class of executed instruction +system.cpu.op_class::MemRead 723 13.46% 87.37% # Class of executed instruction +system.cpu.op_class::MemWrite 678 12.63% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 5370 # Class of executed instruction system.ruby.clk_domain.clock 1 # Clock period in ticks system.ruby.delayHist::bucket_size 1 # delay histogram for all message system.ruby.delayHist::max_bucket 9 # delay histogram for all message @@ -278,9 +343,9 @@ system.ruby.outstanding_req_hist::total 6759 system.ruby.latency_hist::bucket_size 64 system.ruby.latency_hist::max_bucket 639 system.ruby.latency_hist::samples 6758 -system.ruby.latency_hist::mean 13.204202 -system.ruby.latency_hist::gmean 5.149414 -system.ruby.latency_hist::stdev 25.350800 +system.ruby.latency_hist::mean 13.203759 +system.ruby.latency_hist::gmean 5.149407 +system.ruby.latency_hist::stdev 25.345890 system.ruby.latency_hist | 6535 96.70% 96.70% | 182 2.69% 99.39% | 30 0.44% 99.84% | 2 0.03% 99.87% | 8 0.12% 99.99% | 1 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.latency_hist::total 6758 system.ruby.hit_latency_hist::bucket_size 1 @@ -293,18 +358,17 @@ system.ruby.hit_latency_hist::total 5469 system.ruby.miss_latency_hist::bucket_size 64 system.ruby.miss_latency_hist::max_bucket 639 system.ruby.miss_latency_hist::samples 1289 -system.ruby.miss_latency_hist::mean 56.498836 -system.ruby.miss_latency_hist::gmean 50.965885 -system.ruby.miss_latency_hist::stdev 32.457285 +system.ruby.miss_latency_hist::mean 56.496509 +system.ruby.miss_latency_hist::gmean 50.965481 +system.ruby.miss_latency_hist::stdev 32.440273 system.ruby.miss_latency_hist | 1066 82.70% 82.70% | 182 14.12% 96.82% | 30 2.33% 99.15% | 2 0.16% 99.30% | 8 0.62% 99.92% | 1 0.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.miss_latency_hist::total 1289 system.ruby.Directory.incomplete_times 1288 -system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks system.ruby.l1_cntrl0.cacheMemory.demand_hits 5469 # Number of cache demand hits system.ruby.l1_cntrl0.cacheMemory.demand_misses 1289 # Number of cache demand misses system.ruby.l1_cntrl0.cacheMemory.demand_accesses 6758 # Number of cache demand accesses -system.cpu.clk_domain.clock 1 # Clock period in ticks -system.ruby.network.routers0.percent_links_utilized 6.703684 +system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks +system.ruby.network.routers0.percent_links_utilized 6.703893 system.ruby.network.routers0.msg_count.Control::2 1289 system.ruby.network.routers0.msg_count.Data::2 1285 system.ruby.network.routers0.msg_count.Response_Data::4 1289 @@ -313,7 +377,7 @@ system.ruby.network.routers0.msg_bytes.Control::2 10312 system.ruby.network.routers0.msg_bytes.Data::2 92520 system.ruby.network.routers0.msg_bytes.Response_Data::4 92808 system.ruby.network.routers0.msg_bytes.Writeback_Control::3 10280 -system.ruby.network.routers1.percent_links_utilized 6.703684 +system.ruby.network.routers1.percent_links_utilized 6.703893 system.ruby.network.routers1.msg_count.Control::2 1289 system.ruby.network.routers1.msg_count.Data::2 1285 system.ruby.network.routers1.msg_count.Response_Data::4 1289 @@ -322,7 +386,7 @@ system.ruby.network.routers1.msg_bytes.Control::2 10312 system.ruby.network.routers1.msg_bytes.Data::2 92520 system.ruby.network.routers1.msg_bytes.Response_Data::4 92808 system.ruby.network.routers1.msg_bytes.Writeback_Control::3 10280 -system.ruby.network.routers2.percent_links_utilized 6.703684 +system.ruby.network.routers2.percent_links_utilized 6.703893 system.ruby.network.routers2.msg_count.Control::2 1289 system.ruby.network.routers2.msg_count.Data::2 1285 system.ruby.network.routers2.msg_count.Response_Data::4 1289 @@ -339,91 +403,32 @@ system.ruby.network.msg_byte.Control 30936 system.ruby.network.msg_byte.Data 277560 system.ruby.network.msg_byte.Response_Data 278424 system.ruby.network.msg_byte.Writeback_Control 30840 -system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.numCycles 95992 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 5327 # Number of instructions committed -system.cpu.committedOps 5327 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 4505 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu.num_func_calls 146 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 773 # number of instructions that are conditional controls -system.cpu.num_int_insts 4505 # number of integer instructions -system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 10598 # number of times the integer registers were read -system.cpu.num_int_register_writes 4845 # number of times the integer registers were written -system.cpu.num_fp_register_reads 0 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 1401 # number of memory refs -system.cpu.num_load_insts 723 # Number of load instructions -system.cpu.num_store_insts 678 # Number of store instructions -system.cpu.num_idle_cycles 0.999990 # Number of idle cycles -system.cpu.num_busy_cycles 95991.000010 # Number of busy cycles -system.cpu.not_idle_fraction 0.999990 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000010 # Percentage of idle cycles -system.cpu.Branches 1121 # Number of branches fetched -system.cpu.op_class::No_OpClass 173 3.22% 3.22% # Class of executed instruction -system.cpu.op_class::IntAlu 3796 70.69% 73.91% # Class of executed instruction -system.cpu.op_class::IntMult 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::MemRead 723 13.46% 87.37% # Class of executed instruction -system.cpu.op_class::MemWrite 678 12.63% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 5370 # Class of executed instruction -system.ruby.network.routers0.throttle0.link_utilization 6.712018 +system.ruby.network.routers0.throttle0.link_utilization 6.712227 system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1289 system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 1285 system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 92808 system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 10280 -system.ruby.network.routers0.throttle1.link_utilization 6.695350 +system.ruby.network.routers0.throttle1.link_utilization 6.695559 system.ruby.network.routers0.throttle1.msg_count.Control::2 1289 system.ruby.network.routers0.throttle1.msg_count.Data::2 1285 system.ruby.network.routers0.throttle1.msg_bytes.Control::2 10312 system.ruby.network.routers0.throttle1.msg_bytes.Data::2 92520 -system.ruby.network.routers1.throttle0.link_utilization 6.695350 +system.ruby.network.routers1.throttle0.link_utilization 6.695559 system.ruby.network.routers1.throttle0.msg_count.Control::2 1289 system.ruby.network.routers1.throttle0.msg_count.Data::2 1285 system.ruby.network.routers1.throttle0.msg_bytes.Control::2 10312 system.ruby.network.routers1.throttle0.msg_bytes.Data::2 92520 -system.ruby.network.routers1.throttle1.link_utilization 6.712018 +system.ruby.network.routers1.throttle1.link_utilization 6.712227 system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 1289 system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 1285 system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 92808 system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 10280 -system.ruby.network.routers2.throttle0.link_utilization 6.712018 +system.ruby.network.routers2.throttle0.link_utilization 6.712227 system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 1289 system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 1285 system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 92808 system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 10280 -system.ruby.network.routers2.throttle1.link_utilization 6.695350 +system.ruby.network.routers2.throttle1.link_utilization 6.695559 system.ruby.network.routers2.throttle1.msg_count.Control::2 1289 system.ruby.network.routers2.throttle1.msg_count.Data::2 1285 system.ruby.network.routers2.throttle1.msg_bytes.Control::2 10312 @@ -441,9 +446,9 @@ system.ruby.delayVCHist.vnet_2::total 1285 # de system.ruby.LD.latency_hist::bucket_size 32 system.ruby.LD.latency_hist::max_bucket 319 system.ruby.LD.latency_hist::samples 715 -system.ruby.LD.latency_hist::mean 30.928671 -system.ruby.LD.latency_hist::gmean 13.876476 -system.ruby.LD.latency_hist::stdev 34.808507 +system.ruby.LD.latency_hist::mean 30.924476 +system.ruby.LD.latency_hist::gmean 13.876278 +system.ruby.LD.latency_hist::stdev 34.776798 system.ruby.LD.latency_hist | 320 44.76% 44.76% | 330 46.15% 90.91% | 50 6.99% 97.90% | 2 0.28% 98.18% | 3 0.42% 98.60% | 6 0.84% 99.44% | 1 0.14% 99.58% | 0 0.00% 99.58% | 2 0.28% 99.86% | 1 0.14% 100.00% system.ruby.LD.latency_hist::total 715 system.ruby.LD.hit_latency_hist::bucket_size 1 @@ -456,9 +461,9 @@ system.ruby.LD.hit_latency_hist::total 320 system.ruby.LD.miss_latency_hist::bucket_size 32 system.ruby.LD.miss_latency_hist::max_bucket 319 system.ruby.LD.miss_latency_hist::samples 395 -system.ruby.LD.miss_latency_hist::mean 53.554430 -system.ruby.LD.miss_latency_hist::gmean 47.988958 -system.ruby.LD.miss_latency_hist::stdev 32.387704 +system.ruby.LD.miss_latency_hist::mean 53.546835 +system.ruby.LD.miss_latency_hist::gmean 47.987716 +system.ruby.LD.miss_latency_hist::stdev 32.331244 system.ruby.LD.miss_latency_hist | 0 0.00% 0.00% | 330 83.54% 83.54% | 50 12.66% 96.20% | 2 0.51% 96.71% | 3 0.76% 97.47% | 6 1.52% 98.99% | 1 0.25% 99.24% | 0 0.00% 99.24% | 2 0.51% 99.75% | 1 0.25% 100.00% system.ruby.LD.miss_latency_hist::total 395 system.ruby.ST.latency_hist::bucket_size 32 @@ -510,9 +515,9 @@ system.ruby.IFETCH.miss_latency_hist::total 715 system.ruby.Directory.miss_mach_latency_hist::bucket_size 64 system.ruby.Directory.miss_mach_latency_hist::max_bucket 639 system.ruby.Directory.miss_mach_latency_hist::samples 1289 -system.ruby.Directory.miss_mach_latency_hist::mean 56.498836 -system.ruby.Directory.miss_mach_latency_hist::gmean 50.965885 -system.ruby.Directory.miss_mach_latency_hist::stdev 32.457285 +system.ruby.Directory.miss_mach_latency_hist::mean 56.496509 +system.ruby.Directory.miss_mach_latency_hist::gmean 50.965481 +system.ruby.Directory.miss_mach_latency_hist::stdev 32.440273 system.ruby.Directory.miss_mach_latency_hist | 1066 82.70% 82.70% | 182 14.12% 96.82% | 30 2.33% 99.15% | 2 0.16% 99.30% | 8 0.62% 99.92% | 1 0.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.Directory.miss_mach_latency_hist::total 1289 system.ruby.Directory.miss_latency_hist.issue_to_initial_request::bucket_size 1 @@ -544,9 +549,9 @@ system.ruby.Directory.miss_latency_hist.first_response_to_completion::total system.ruby.LD.Directory.miss_type_mach_latency_hist::bucket_size 32 system.ruby.LD.Directory.miss_type_mach_latency_hist::max_bucket 319 system.ruby.LD.Directory.miss_type_mach_latency_hist::samples 395 -system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 53.554430 -system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 47.988958 -system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 32.387704 +system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 53.546835 +system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 47.987716 +system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 32.331244 system.ruby.LD.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 330 83.54% 83.54% | 50 12.66% 96.20% | 2 0.51% 96.71% | 3 0.76% 97.47% | 6 1.52% 98.99% | 1 0.25% 99.24% | 0 0.00% 99.24% | 2 0.51% 99.75% | 1 0.25% 100.00% system.ruby.LD.Directory.miss_type_mach_latency_hist::total 395 system.ruby.ST.Directory.miss_type_mach_latency_hist::bucket_size 32 @@ -565,6 +570,14 @@ system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 51.762329 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 34.218674 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 591 82.66% 82.66% | 101 14.13% 96.78% | 16 2.24% 99.02% | 1 0.14% 99.16% | 5 0.70% 99.86% | 1 0.14% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total 715 +system.ruby.Directory_Controller.GETX 1289 0.00% 0.00% +system.ruby.Directory_Controller.PUTX 1285 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Data 1289 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Ack 1285 0.00% 0.00% +system.ruby.Directory_Controller.I.GETX 1289 0.00% 0.00% +system.ruby.Directory_Controller.M.PUTX 1285 0.00% 0.00% +system.ruby.Directory_Controller.IM.Memory_Data 1289 0.00% 0.00% +system.ruby.Directory_Controller.MI.Memory_Ack 1285 0.00% 0.00% system.ruby.L1Cache_Controller.Load 715 0.00% 0.00% system.ruby.L1Cache_Controller.Ifetch 5370 0.00% 0.00% system.ruby.L1Cache_Controller.Store 673 0.00% 0.00% @@ -581,13 +594,5 @@ system.ruby.L1Cache_Controller.M.Replacement 1285 0.00% 0.00% system.ruby.L1Cache_Controller.MI.Writeback_Ack 1285 0.00% 0.00% system.ruby.L1Cache_Controller.IS.Data 1110 0.00% 0.00% system.ruby.L1Cache_Controller.IM.Data 179 0.00% 0.00% -system.ruby.Directory_Controller.GETX 1289 0.00% 0.00% -system.ruby.Directory_Controller.PUTX 1285 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Data 1289 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Ack 1285 0.00% 0.00% -system.ruby.Directory_Controller.I.GETX 1289 0.00% 0.00% -system.ruby.Directory_Controller.M.PUTX 1285 0.00% 0.00% -system.ruby.Directory_Controller.IM.Memory_Data 1289 0.00% 0.00% -system.ruby.Directory_Controller.MI.Memory_Ack 1285 0.00% 0.00% ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt index 83799ecfd..3b4d7b677 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000020 # Nu sim_ticks 19678000 # Number of ticks simulated final_tick 19678000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 30596 # Simulator instruction rate (inst/s) -host_op_rate 55428 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 111894824 # Simulator tick rate (ticks/s) -host_mem_usage 253080 # Number of bytes of host memory used -host_seconds 0.18 # Real time elapsed on the host +host_inst_rate 46918 # Simulator instruction rate (inst/s) +host_op_rate 84992 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 171550123 # Simulator tick rate (ticks/s) +host_mem_usage 309548 # Number of bytes of host memory used +host_seconds 0.11 # Real time elapsed on the host sim_insts 5380 # Number of instructions simulated sim_ops 9747 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -220,55 +220,34 @@ system.physmem.readRowHitRate 74.10 # Ro system.physmem.writeRowHitRate nan # Row buffer hit rate for writes system.physmem.avgGap 47073.14 # Average gap between requests system.physmem.pageHitRate 74.10 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 11000 # Time in different power states -system.physmem.memoryStateTime::REF 520000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 15318250 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 219240 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 446040 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 119625 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 243375 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 1084200 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 1567800 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 1017120 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 1017120 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 10796085 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 10703745 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 31500 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 112500 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 13267770 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 14090580 # Total energy per rank (pJ) -system.physmem.averagePower::0 837.810088 # Core power per rank (mW) -system.physmem.averagePower::1 889.767464 # Core power per rank (mW) -system.membus.trans_dist::ReadReq 339 # Transaction distribution -system.membus.trans_dist::ReadResp 338 # Transaction distribution -system.membus.trans_dist::ReadExReq 78 # Transaction distribution -system.membus.trans_dist::ReadExResp 78 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 833 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 833 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 833 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26624 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 26624 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 26624 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 417 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 417 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 417 # Request fanout histogram -system.membus.reqLayer0.occupancy 505000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.6 # Layer utilization (%) -system.membus.respLayer1.occupancy 3897000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 19.8 # Layer utilization (%) -system.cpu_clk_domain.clock 500 # Clock period in ticks +system.physmem_0.actEnergy 219240 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 119625 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1084200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 10796085 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 31500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 13267770 # Total energy per rank (pJ) +system.physmem_0.averagePower 837.810088 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 11000 # Time in different power states +system.physmem_0.memoryStateTime::REF 520000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 15318250 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 446040 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 243375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1567800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 10701180 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 112500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 14088015 # Total energy per rank (pJ) +system.physmem_1.averagePower 889.816201 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 882750 # Time in different power states +system.physmem_1.memoryStateTime::REF 520000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 15230750 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.branchPred.lookups 3423 # Number of BP lookups system.cpu.branchPred.condPredicted 3423 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 535 # Number of conditional branches incorrect @@ -278,6 +257,7 @@ system.cpu.branchPred.BTBCorrect 0 # Nu system.cpu.branchPred.BTBHitPct 33.962264 # BTB Hit Percentage system.cpu.branchPred.usedRAS 247 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 76 # Number of incorrect RAS predictions. +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 11 # Number of system calls system.cpu.numCycles 39357 # number of cpu cycles simulated @@ -572,36 +552,116 @@ system.cpu.cc_regfile_reads 8069 # nu system.cpu.cc_regfile_writes 5036 # number of cc regfile writes system.cpu.misc_regfile_reads 7491 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.trans_dist::ReadReq 340 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 339 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 78 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 78 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 552 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 283 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 835 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17664 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9024 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 26688 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 418 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 418 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 418 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 209000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 462500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.4 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 234500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%) +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 82.331185 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 2400 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 141 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 17.021277 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 82.331185 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.020100 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.020100 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 141 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 87 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.034424 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 5369 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 5369 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 1543 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1543 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 857 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 857 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 2400 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2400 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2400 # number of overall hits +system.cpu.dcache.overall_hits::total 2400 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 136 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 136 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 78 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 78 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 214 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 214 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 214 # number of overall misses +system.cpu.dcache.overall_misses::total 214 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 9815500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 9815500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 5771000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 5771000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 15586500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 15586500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 15586500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 15586500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1679 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1679 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 935 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 935 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 2614 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2614 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2614 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2614 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.081001 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.081001 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.083422 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.083422 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.081867 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.081867 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.081867 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.081867 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 72172.794118 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 72172.794118 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73987.179487 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 73987.179487 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 72834.112150 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 72834.112150 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 72834.112150 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 72834.112150 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 201 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 40.200000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 72 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 72 # number of ReadReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 72 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 72 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 72 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 72 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 64 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 64 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 78 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 78 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 142 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 142 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 142 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5009500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5009500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5588000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5588000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10597500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10597500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10597500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10597500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.038118 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.038118 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.083422 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.083422 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.054323 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.054323 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.054323 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.054323 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78273.437500 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78273.437500 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71641.025641 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71641.025641 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74630.281690 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 74630.281690 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74630.281690 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 74630.281690 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements system.cpu.icache.tags.tagsinuse 131.539722 # Cycle average of tags in use system.cpu.icache.tags.total_refs 1800 # Total number of references to valid blocks. @@ -823,115 +883,60 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59334.545455 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61235.915493 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59982.014388 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 82.331185 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 2400 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 141 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 17.021277 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 82.331185 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.020100 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.020100 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 141 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 87 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.034424 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 5369 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 5369 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 1543 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1543 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 857 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 857 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2400 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2400 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2400 # number of overall hits -system.cpu.dcache.overall_hits::total 2400 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 136 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 136 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 78 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 78 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 214 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 214 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 214 # number of overall misses -system.cpu.dcache.overall_misses::total 214 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 9815500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 9815500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 5771000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 5771000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 15586500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 15586500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 15586500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 15586500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1679 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1679 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 935 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 935 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2614 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2614 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2614 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2614 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.081001 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.081001 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.083422 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.083422 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.081867 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.081867 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.081867 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.081867 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 72172.794118 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 72172.794118 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73987.179487 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 73987.179487 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 72834.112150 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 72834.112150 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 72834.112150 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 72834.112150 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 201 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 40.200000 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 72 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 72 # number of ReadReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 72 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 72 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 72 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 72 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 64 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 64 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 78 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 78 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 142 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 142 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 142 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5009500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5009500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5588000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5588000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10597500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10597500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10597500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10597500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.038118 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.038118 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.083422 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.083422 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.054323 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.054323 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.054323 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.054323 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78273.437500 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78273.437500 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71641.025641 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71641.025641 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74630.281690 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 74630.281690 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74630.281690 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 74630.281690 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.trans_dist::ReadReq 340 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 339 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 78 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 78 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 552 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 283 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 835 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17664 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9024 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 26688 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 418 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 418 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 418 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 209000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 462500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 2.4 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 234500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%) +system.membus.trans_dist::ReadReq 339 # Transaction distribution +system.membus.trans_dist::ReadResp 338 # Transaction distribution +system.membus.trans_dist::ReadExReq 78 # Transaction distribution +system.membus.trans_dist::ReadExResp 78 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 833 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 833 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 833 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26624 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 26624 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 26624 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 417 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 417 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 417 # Request fanout histogram +system.membus.reqLayer0.occupancy 505000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.6 # Layer utilization (%) +system.membus.respLayer1.occupancy 3897000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 19.8 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt index f27f9e229..6ad7b9146 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000107 # Nu sim_ticks 107237 # Number of ticks simulated final_tick 107237 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 14917 # Simulator instruction rate (inst/s) -host_op_rate 27022 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 297251 # Simulator tick rate (ticks/s) -host_mem_usage 452416 # Number of bytes of host memory used -host_seconds 0.36 # Real time elapsed on the host +host_inst_rate 59170 # Simulator instruction rate (inst/s) +host_op_rate 107175 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1178869 # Simulator tick rate (ticks/s) +host_mem_usage 466480 # Number of bytes of host memory used +host_seconds 0.09 # Real time elapsed on the host sim_insts 5381 # Number of instructions simulated sim_ops 9748 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -238,29 +238,97 @@ system.mem_ctrls.readRowHitRate 64.11 # Ro system.mem_ctrls.writeRowHitRate 90.98 # Row buffer hit rate for writes system.mem_ctrls.avgGap 38.96 # Average gap between requests system.mem_ctrls.pageHitRate 77.75 # Row buffer hit rate, read and write combined -system.mem_ctrls.memoryStateTime::IDLE 6647 # Time in different power states -system.mem_ctrls.memoryStateTime::REF 3380 # Time in different power states -system.mem_ctrls.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls.memoryStateTime::ACT 91465 # Time in different power states -system.mem_ctrls.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrls.actEnergy::0 695520 # Energy for activate commands per rank (pJ) -system.mem_ctrls.actEnergy::1 1270080 # Energy for activate commands per rank (pJ) -system.mem_ctrls.preEnergy::0 386400 # Energy for precharge commands per rank (pJ) -system.mem_ctrls.preEnergy::1 705600 # Energy for precharge commands per rank (pJ) -system.mem_ctrls.readEnergy::0 3219840 # Energy for read commands per rank (pJ) -system.mem_ctrls.readEnergy::1 4605120 # Energy for read commands per rank (pJ) -system.mem_ctrls.writeEnergy::0 2623104 # Energy for write commands per rank (pJ) -system.mem_ctrls.writeEnergy::1 3784320 # Energy for write commands per rank (pJ) -system.mem_ctrls.refreshEnergy::0 6611280 # Energy for refresh commands per rank (pJ) -system.mem_ctrls.refreshEnergy::1 6611280 # Energy for refresh commands per rank (pJ) -system.mem_ctrls.actBackEnergy::0 57894444 # Energy for active background per rank (pJ) -system.mem_ctrls.actBackEnergy::1 62913636 # Energy for active background per rank (pJ) -system.mem_ctrls.preBackEnergy::0 10102200 # Energy for precharge background per rank (pJ) -system.mem_ctrls.preBackEnergy::1 5699400 # Energy for precharge background per rank (pJ) -system.mem_ctrls.totalEnergy::0 81532788 # Total energy per rank (pJ) -system.mem_ctrls.totalEnergy::1 85589436 # Total energy per rank (pJ) -system.mem_ctrls.averagePower::0 803.452847 # Core power per rank (mW) -system.mem_ctrls.averagePower::1 843.428487 # Core power per rank (mW) +system.mem_ctrls_0.actEnergy 695520 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 386400 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 3219840 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 2623104 # Energy for write commands per rank (pJ) +system.mem_ctrls_0.refreshEnergy 6611280 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_0.actBackEnergy 57895812 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 10101000 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.totalEnergy 81532956 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 803.454502 # Core power per rank (mW) +system.mem_ctrls_0.memoryStateTime::IDLE 16443 # Time in different power states +system.mem_ctrls_0.memoryStateTime::REF 3380 # Time in different power states +system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 81669 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls_1.actEnergy 1270080 # Energy for activate commands per rank (pJ) +system.mem_ctrls_1.preEnergy 705600 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_1.readEnergy 4605120 # Energy for read commands per rank (pJ) +system.mem_ctrls_1.writeEnergy 3784320 # Energy for write commands per rank (pJ) +system.mem_ctrls_1.refreshEnergy 6611280 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_1.actBackEnergy 62916372 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 5697000 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.totalEnergy 85589772 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 843.431798 # Core power per rank (mW) +system.mem_ctrls_1.memoryStateTime::IDLE 9164 # Time in different power states +system.mem_ctrls_1.memoryStateTime::REF 3380 # Time in different power states +system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 89065 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.clk_domain.clock 1 # Clock period in ticks +system.cpu.apic_clk_domain.clock 16 # Clock period in ticks +system.cpu.workload.num_syscalls 11 # Number of system calls +system.cpu.numCycles 107237 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 5381 # Number of instructions committed +system.cpu.committedOps 9748 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 9654 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses +system.cpu.num_func_calls 209 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 899 # number of instructions that are conditional controls +system.cpu.num_int_insts 9654 # number of integer instructions +system.cpu.num_fp_insts 0 # number of float instructions +system.cpu.num_int_register_reads 18335 # number of times the integer registers were read +system.cpu.num_int_register_writes 7527 # number of times the integer registers were written +system.cpu.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_cc_register_reads 6487 # number of times the CC registers were read +system.cpu.num_cc_register_writes 3536 # number of times the CC registers were written +system.cpu.num_mem_refs 1988 # number of memory refs +system.cpu.num_load_insts 1053 # Number of load instructions +system.cpu.num_store_insts 935 # Number of store instructions +system.cpu.num_idle_cycles 0.999991 # Number of idle cycles +system.cpu.num_busy_cycles 107236.000009 # Number of busy cycles +system.cpu.not_idle_fraction 0.999991 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.000009 # Percentage of idle cycles +system.cpu.Branches 1208 # Number of branches fetched +system.cpu.op_class::No_OpClass 1 0.01% 0.01% # Class of executed instruction +system.cpu.op_class::IntAlu 7749 79.49% 79.50% # Class of executed instruction +system.cpu.op_class::IntMult 3 0.03% 79.53% # Class of executed instruction +system.cpu.op_class::IntDiv 7 0.07% 79.61% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::MemRead 1053 10.80% 90.41% # Class of executed instruction +system.cpu.op_class::MemWrite 935 9.59% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 9748 # Class of executed instruction system.ruby.clk_domain.clock 1 # Clock period in ticks system.ruby.delayHist::bucket_size 1 # delay histogram for all message system.ruby.delayHist::max_bucket 9 # delay histogram for all message @@ -278,8 +346,8 @@ system.ruby.latency_hist::bucket_size 64 system.ruby.latency_hist::max_bucket 639 system.ruby.latency_hist::samples 8852 system.ruby.latency_hist::mean 11.114437 -system.ruby.latency_hist::gmean 4.638311 -system.ruby.latency_hist::stdev 22.978637 +system.ruby.latency_hist::gmean 4.638310 +system.ruby.latency_hist::stdev 22.979355 system.ruby.latency_hist | 8594 97.09% 97.09% | 215 2.43% 99.51% | 29 0.33% 99.84% | 6 0.07% 99.91% | 6 0.07% 99.98% | 2 0.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.latency_hist::total 8852 system.ruby.hit_latency_hist::bucket_size 1 @@ -293,16 +361,15 @@ system.ruby.miss_latency_hist::bucket_size 64 system.ruby.miss_latency_hist::max_bucket 639 system.ruby.miss_latency_hist::samples 1377 system.ruby.miss_latency_hist::mean 55.163399 -system.ruby.miss_latency_hist::gmean 49.389613 -system.ruby.miss_latency_hist::stdev 33.121212 +system.ruby.miss_latency_hist::gmean 49.389540 +system.ruby.miss_latency_hist::stdev 33.124416 system.ruby.miss_latency_hist | 1119 81.26% 81.26% | 215 15.61% 96.88% | 29 2.11% 98.98% | 6 0.44% 99.42% | 6 0.44% 99.85% | 2 0.15% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.miss_latency_hist::total 1377 system.ruby.Directory.incomplete_times 1376 -system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks system.ruby.l1_cntrl0.cacheMemory.demand_hits 7475 # Number of cache demand hits system.ruby.l1_cntrl0.cacheMemory.demand_misses 1377 # Number of cache demand misses system.ruby.l1_cntrl0.cacheMemory.demand_accesses 8852 # Number of cache demand accesses -system.cpu.clk_domain.clock 1 # Clock period in ticks +system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks system.ruby.network.routers0.percent_links_utilized 6.411034 system.ruby.network.routers0.msg_count.Control::2 1377 system.ruby.network.routers0.msg_count.Data::2 1373 @@ -338,68 +405,6 @@ system.ruby.network.msg_byte.Control 33048 system.ruby.network.msg_byte.Data 296568 system.ruby.network.msg_byte.Response_Data 297432 system.ruby.network.msg_byte.Writeback_Control 32952 -system.cpu.apic_clk_domain.clock 16 # Clock period in ticks -system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.numCycles 107237 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 5381 # Number of instructions committed -system.cpu.committedOps 9748 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 9654 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu.num_func_calls 209 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 899 # number of instructions that are conditional controls -system.cpu.num_int_insts 9654 # number of integer instructions -system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 18335 # number of times the integer registers were read -system.cpu.num_int_register_writes 7527 # number of times the integer registers were written -system.cpu.num_fp_register_reads 0 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_cc_register_reads 6487 # number of times the CC registers were read -system.cpu.num_cc_register_writes 3536 # number of times the CC registers were written -system.cpu.num_mem_refs 1988 # number of memory refs -system.cpu.num_load_insts 1053 # Number of load instructions -system.cpu.num_store_insts 935 # Number of store instructions -system.cpu.num_idle_cycles 0.999991 # Number of idle cycles -system.cpu.num_busy_cycles 107236.000009 # Number of busy cycles -system.cpu.not_idle_fraction 0.999991 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000009 # Percentage of idle cycles -system.cpu.Branches 1208 # Number of branches fetched -system.cpu.op_class::No_OpClass 1 0.01% 0.01% # Class of executed instruction -system.cpu.op_class::IntAlu 7749 79.49% 79.50% # Class of executed instruction -system.cpu.op_class::IntMult 3 0.03% 79.53% # Class of executed instruction -system.cpu.op_class::IntDiv 7 0.07% 79.61% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::MemRead 1053 10.80% 90.41% # Class of executed instruction -system.cpu.op_class::MemWrite 935 9.59% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 9748 # Class of executed instruction system.ruby.network.routers0.throttle0.link_utilization 6.418494 system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1377 system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 1373 @@ -490,8 +495,8 @@ system.ruby.IFETCH.latency_hist::bucket_size 64 system.ruby.IFETCH.latency_hist::max_bucket 639 system.ruby.IFETCH.latency_hist::samples 6864 system.ruby.IFETCH.latency_hist::mean 8.263112 -system.ruby.IFETCH.latency_hist::gmean 3.900454 -system.ruby.IFETCH.latency_hist::stdev 20.208626 +system.ruby.IFETCH.latency_hist::gmean 3.900453 +system.ruby.IFETCH.latency_hist::stdev 20.209679 system.ruby.IFETCH.latency_hist | 6731 98.06% 98.06% | 102 1.49% 99.55% | 22 0.32% 99.87% | 3 0.04% 99.91% | 5 0.07% 99.99% | 1 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.latency_hist::total 6864 system.ruby.IFETCH.hit_latency_hist::bucket_size 1 @@ -505,8 +510,8 @@ system.ruby.IFETCH.miss_latency_hist::bucket_size 64 system.ruby.IFETCH.miss_latency_hist::max_bucket 639 system.ruby.IFETCH.miss_latency_hist::samples 623 system.ruby.IFETCH.miss_latency_hist::mean 60.987159 -system.ruby.IFETCH.miss_latency_hist::gmean 54.083768 -system.ruby.IFETCH.miss_latency_hist::stdev 37.997755 +system.ruby.IFETCH.miss_latency_hist::gmean 54.083593 +system.ruby.IFETCH.miss_latency_hist::stdev 38.003932 system.ruby.IFETCH.miss_latency_hist | 490 78.65% 78.65% | 102 16.37% 95.02% | 22 3.53% 98.56% | 3 0.48% 99.04% | 5 0.80% 99.84% | 1 0.16% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.miss_latency_hist::total 623 system.ruby.RMW_Read.latency_hist::bucket_size 4 @@ -536,8 +541,8 @@ system.ruby.Directory.miss_mach_latency_hist::bucket_size 64 system.ruby.Directory.miss_mach_latency_hist::max_bucket 639 system.ruby.Directory.miss_mach_latency_hist::samples 1377 system.ruby.Directory.miss_mach_latency_hist::mean 55.163399 -system.ruby.Directory.miss_mach_latency_hist::gmean 49.389613 -system.ruby.Directory.miss_mach_latency_hist::stdev 33.121212 +system.ruby.Directory.miss_mach_latency_hist::gmean 49.389540 +system.ruby.Directory.miss_mach_latency_hist::stdev 33.124416 system.ruby.Directory.miss_mach_latency_hist | 1119 81.26% 81.26% | 215 15.61% 96.88% | 29 2.11% 98.98% | 6 0.44% 99.42% | 6 0.44% 99.85% | 2 0.15% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.Directory.miss_mach_latency_hist::total 1377 system.ruby.Directory.miss_latency_hist.issue_to_initial_request::bucket_size 1 @@ -586,8 +591,8 @@ system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::bucket_size system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::max_bucket 639 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::samples 623 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean 60.987159 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 54.083768 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 37.997755 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 54.083593 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 38.003932 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 490 78.65% 78.65% | 102 16.37% 95.02% | 22 3.53% 98.56% | 3 0.48% 99.04% | 5 0.80% 99.84% | 1 0.16% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total 623 system.ruby.RMW_Read.Directory.miss_type_mach_latency_hist::bucket_size 4 @@ -598,6 +603,14 @@ system.ruby.RMW_Read.Directory.miss_type_mach_latency_hist::gmean 34.000000 system.ruby.RMW_Read.Directory.miss_type_mach_latency_hist::stdev nan system.ruby.RMW_Read.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% system.ruby.RMW_Read.Directory.miss_type_mach_latency_hist::total 1 +system.ruby.Directory_Controller.GETX 1377 0.00% 0.00% +system.ruby.Directory_Controller.PUTX 1373 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Data 1377 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Ack 1373 0.00% 0.00% +system.ruby.Directory_Controller.I.GETX 1377 0.00% 0.00% +system.ruby.Directory_Controller.M.PUTX 1373 0.00% 0.00% +system.ruby.Directory_Controller.IM.Memory_Data 1377 0.00% 0.00% +system.ruby.Directory_Controller.MI.Memory_Ack 1373 0.00% 0.00% system.ruby.L1Cache_Controller.Load 1045 0.00% 0.00% system.ruby.L1Cache_Controller.Ifetch 6864 0.00% 0.00% system.ruby.L1Cache_Controller.Store 943 0.00% 0.00% @@ -614,13 +627,5 @@ system.ruby.L1Cache_Controller.M.Replacement 1373 0.00% 0.00% system.ruby.L1Cache_Controller.MI.Writeback_Ack 1373 0.00% 0.00% system.ruby.L1Cache_Controller.IS.Data 1122 0.00% 0.00% system.ruby.L1Cache_Controller.IM.Data 255 0.00% 0.00% -system.ruby.Directory_Controller.GETX 1377 0.00% 0.00% -system.ruby.Directory_Controller.PUTX 1373 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Data 1377 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Ack 1373 0.00% 0.00% -system.ruby.Directory_Controller.I.GETX 1377 0.00% 0.00% -system.ruby.Directory_Controller.M.PUTX 1373 0.00% 0.00% -system.ruby.Directory_Controller.IM.Memory_Data 1377 0.00% 0.00% -system.ruby.Directory_Controller.MI.Memory_Ack 1373 0.00% 0.00% ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt index 390228fe9..752a25834 100644 --- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt @@ -1,61 +1,61 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000023 # Number of seconds simulated -sim_ticks 23061500 # Number of ticks simulated -final_tick 23061500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000024 # Number of seconds simulated +sim_ticks 23754500 # Number of ticks simulated +final_tick 23754500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 45645 # Simulator instruction rate (inst/s) -host_op_rate 45641 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 82586308 # Simulator tick rate (ticks/s) -host_mem_usage 237816 # Number of bytes of host memory used -host_seconds 0.28 # Real time elapsed on the host +host_inst_rate 70868 # Simulator instruction rate (inst/s) +host_op_rate 70863 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 132078042 # Simulator tick rate (ticks/s) +host_mem_usage 294344 # Number of bytes of host memory used +host_seconds 0.18 # Real time elapsed on the host sim_insts 12744 # Number of instructions simulated sim_ops 12744 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 40576 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 22080 # Number of bytes read from this memory -system.physmem.bytes_read::total 62656 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 40576 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 40576 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 634 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 345 # Number of read requests responded to by this memory -system.physmem.num_reads::total 979 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1759469245 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 957439889 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2716909134 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1759469245 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1759469245 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1759469245 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 957439889 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2716909134 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 979 # Number of read requests accepted +system.physmem.bytes_read::cpu.inst 40064 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 22336 # Number of bytes read from this memory +system.physmem.bytes_read::total 62400 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 40064 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 40064 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 626 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 349 # Number of read requests responded to by this memory +system.physmem.num_reads::total 975 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1686585700 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 940284999 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2626870698 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1686585700 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1686585700 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1686585700 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 940284999 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2626870698 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 975 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 979 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 975 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 62656 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 62400 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 62656 # Total read bytes from the system interface side +system.physmem.bytesReadSys 62400 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 84 # Per bank write bursts +system.physmem.perBankRdBursts::0 83 # Per bank write bursts system.physmem.perBankRdBursts::1 151 # Per bank write bursts system.physmem.perBankRdBursts::2 78 # Per bank write bursts system.physmem.perBankRdBursts::3 58 # Per bank write bursts -system.physmem.perBankRdBursts::4 89 # Per bank write bursts -system.physmem.perBankRdBursts::5 50 # Per bank write bursts -system.physmem.perBankRdBursts::6 33 # Per bank write bursts -system.physmem.perBankRdBursts::7 51 # Per bank write bursts -system.physmem.perBankRdBursts::8 42 # Per bank write bursts -system.physmem.perBankRdBursts::9 39 # Per bank write bursts -system.physmem.perBankRdBursts::10 29 # Per bank write bursts +system.physmem.perBankRdBursts::4 88 # Per bank write bursts +system.physmem.perBankRdBursts::5 49 # Per bank write bursts +system.physmem.perBankRdBursts::6 32 # Per bank write bursts +system.physmem.perBankRdBursts::7 49 # Per bank write bursts +system.physmem.perBankRdBursts::8 41 # Per bank write bursts +system.physmem.perBankRdBursts::9 38 # Per bank write bursts +system.physmem.perBankRdBursts::10 30 # Per bank write bursts system.physmem.perBankRdBursts::11 34 # Per bank write bursts system.physmem.perBankRdBursts::12 15 # Per bank write bursts -system.physmem.perBankRdBursts::13 120 # Per bank write bursts -system.physmem.perBankRdBursts::14 69 # Per bank write bursts +system.physmem.perBankRdBursts::13 122 # Per bank write bursts +system.physmem.perBankRdBursts::14 70 # Per bank write bursts system.physmem.perBankRdBursts::15 37 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts @@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 22909000 # Total gap between requests +system.physmem.totGap 23342000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 979 # Read request sizes (log2) +system.physmem.readPktSize::6 975 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -90,11 +90,11 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 342 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 332 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 191 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 77 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 27 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 328 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 345 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 183 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 80 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 29 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 10 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -186,118 +186,100 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 196 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 290.285714 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 185.772581 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 289.019279 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 62 31.63% 31.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 59 30.10% 61.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 22 11.22% 72.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 8 4.08% 77.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 15 7.65% 84.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 9 4.59% 89.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 4 2.04% 91.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 4 2.04% 93.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 13 6.63% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 196 # Bytes accessed per row activation -system.physmem.totQLat 11811000 # Total ticks spent queuing -system.physmem.totMemAccLat 30167250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 4895000 # Total ticks spent in databus transfers -system.physmem.avgQLat 12064.35 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 211 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 295.431280 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 188.087836 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 290.004628 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 69 32.70% 32.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 56 26.54% 59.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 25 11.85% 71.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 14 6.64% 77.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 15 7.11% 84.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 9 4.27% 89.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 4 1.90% 91.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 6 2.84% 93.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 13 6.16% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 211 # Bytes accessed per row activation +system.physmem.totQLat 12504500 # Total ticks spent queuing +system.physmem.totMemAccLat 30785750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 4875000 # Total ticks spent in databus transfers +system.physmem.avgQLat 12825.13 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30814.35 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 2716.91 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 31575.13 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2626.87 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 2716.91 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 2626.87 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 21.23 # Data bus utilization in percentage -system.physmem.busUtilRead 21.23 # Data bus utilization in percentage for reads +system.physmem.busUtil 20.52 # Data bus utilization in percentage +system.physmem.busUtilRead 20.52 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 2.42 # Average read queue length when enqueuing +system.physmem.avgRdQLen 2.40 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 767 # Number of row buffer hits during reads +system.physmem.readRowHits 763 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 78.35 # Row buffer hit rate for reads +system.physmem.readRowHitRate 78.26 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 23400.41 # Average gap between requests -system.physmem.pageHitRate 78.35 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 25750 # Time in different power states -system.physmem.memoryStateTime::REF 520000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 15300500 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 710640 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 438480 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 387750 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 239250 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 3798600 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 1747200 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 1017120 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 1017120 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 10760175 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 10602000 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 60750 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 199500 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 16735035 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 14243550 # Total energy per rank (pJ) -system.physmem.averagePower::0 1057.005211 # Core power per rank (mW) -system.physmem.averagePower::1 899.639981 # Core power per rank (mW) -system.membus.trans_dist::ReadReq 833 # Transaction distribution -system.membus.trans_dist::ReadResp 833 # Transaction distribution -system.membus.trans_dist::ReadExReq 146 # Transaction distribution -system.membus.trans_dist::ReadExResp 146 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1958 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1958 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 62656 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 62656 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 979 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 979 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 979 # Request fanout histogram -system.membus.reqLayer0.occupancy 1210000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 5.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 9085500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 39.4 # Layer utilization (%) -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 6891 # Number of BP lookups -system.cpu.branchPred.condPredicted 3900 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1379 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 5156 # Number of BTB lookups -system.cpu.branchPred.BTBHits 960 # Number of BTB hits +system.physmem.avgGap 23940.51 # Average gap between requests +system.physmem.pageHitRate 78.26 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 899640 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 490875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 4578600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 16058610 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 84750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 23638155 # Total energy per rank (pJ) +system.physmem_0.averagePower 1000.821593 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 44000 # Time in different power states +system.physmem_0.memoryStateTime::REF 780000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 22808500 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 695520 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 379500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 3018600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 15908130 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 216750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 21744180 # Total energy per rank (pJ) +system.physmem_1.averagePower 920.632125 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 278750 # Time in different power states +system.physmem_1.memoryStateTime::REF 780000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 22573750 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.branchPred.lookups 7608 # Number of BP lookups +system.cpu.branchPred.condPredicted 4258 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1618 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 5646 # Number of BTB lookups +system.cpu.branchPred.BTBHits 865 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 18.619085 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 963 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 72 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 15.320581 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1051 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 77 # Number of incorrect RAS predictions. +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 4694 # DTB read hits -system.cpu.dtb.read_misses 106 # DTB read misses +system.cpu.dtb.read_hits 5192 # DTB read hits +system.cpu.dtb.read_misses 102 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 4800 # DTB read accesses -system.cpu.dtb.write_hits 2103 # DTB write hits -system.cpu.dtb.write_misses 62 # DTB write misses +system.cpu.dtb.read_accesses 5294 # DTB read accesses +system.cpu.dtb.write_hits 2108 # DTB write hits +system.cpu.dtb.write_misses 66 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 2165 # DTB write accesses -system.cpu.dtb.data_hits 6797 # DTB hits +system.cpu.dtb.write_accesses 2174 # DTB write accesses +system.cpu.dtb.data_hits 7300 # DTB hits system.cpu.dtb.data_misses 168 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 6965 # DTB accesses -system.cpu.itb.fetch_hits 5123 # ITB hits -system.cpu.itb.fetch_misses 59 # ITB misses +system.cpu.dtb.data_accesses 7468 # DTB accesses +system.cpu.itb.fetch_hits 5663 # ITB hits +system.cpu.itb.fetch_misses 57 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 5182 # ITB accesses +system.cpu.itb.fetch_accesses 5720 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -312,318 +294,318 @@ system.cpu.itb.data_acv 0 # DT system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload0.num_syscalls 17 # Number of system calls system.cpu.workload1.num_syscalls 17 # Number of system calls -system.cpu.numCycles 46124 # number of cpu cycles simulated +system.cpu.numCycles 47510 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 1227 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 38336 # Number of instructions fetch has processed -system.cpu.fetch.Branches 6891 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 1923 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 10750 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1460 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 320 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.CacheLines 5123 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 789 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 27999 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.369192 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.769631 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 1451 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 41889 # Number of instructions fetch has processed +system.cpu.fetch.Branches 7608 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 1916 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 11137 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1697 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 556 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.CacheLines 5663 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 846 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 28570 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.466188 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.843743 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 21530 76.90% 76.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 534 1.91% 78.80% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 415 1.48% 80.29% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 507 1.81% 82.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 495 1.77% 83.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 425 1.52% 85.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 487 1.74% 87.12% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 424 1.51% 88.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 3182 11.36% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 21551 75.43% 75.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 541 1.89% 77.33% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 402 1.41% 78.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 607 2.12% 80.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 545 1.91% 82.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 439 1.54% 84.30% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 542 1.90% 86.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 448 1.57% 87.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 3495 12.23% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 27999 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.149402 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.831151 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 37351 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 11762 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 4916 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 633 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1095 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 569 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 385 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 31322 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 859 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1095 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 37970 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 4830 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 1235 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 4957 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 5670 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 29386 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 35 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 318 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 603 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 4545 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 22134 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 36672 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 36654 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 28570 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.160135 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.881688 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 37575 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 12018 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 5449 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 625 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1245 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 719 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 495 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 33794 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 947 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1245 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 38261 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 5449 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 1170 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 5378 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 5409 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 31549 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 73 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 407 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 458 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 4425 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 23766 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 39316 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 39298 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 16 # Number of floating rename lookups system.cpu.rename.CommittedMaps 9140 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 12994 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 62 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 48 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 2157 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2815 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1467 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 39 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 26 # Number of conflicting stores. -system.cpu.memDep1.insertedLoads 2781 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep1.insertedStores 1339 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep1.conflictingLoads 5 # Number of conflicting loads. +system.cpu.rename.UndoneMaps 14626 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 56 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 44 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 2199 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 3120 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1520 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 45 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 25 # Number of conflicting stores. +system.cpu.memDep1.insertedLoads 2933 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep1.insertedStores 1394 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep1.conflictingLoads 11 # Number of conflicting loads. system.cpu.memDep1.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 26455 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 53 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 22074 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 73 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 12913 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 7569 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 19 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 27999 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.788385 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.505249 # Number of insts issued each cycle +system.cpu.iq.iqInstsAdded 28021 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 51 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 23357 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 131 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 14239 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 8472 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 17 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 28570 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.817536 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.542788 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 19729 70.46% 70.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 2607 9.31% 79.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 1874 6.69% 86.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 1399 5.00% 91.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 1239 4.43% 95.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 603 2.15% 98.04% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 335 1.20% 99.24% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 163 0.58% 99.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 50 0.18% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 19963 69.87% 69.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 2657 9.30% 79.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 1959 6.86% 86.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 1384 4.84% 90.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 1325 4.64% 95.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 682 2.39% 97.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 348 1.22% 99.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 184 0.64% 99.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 68 0.24% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 27999 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 28570 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 17 5.72% 5.72% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 5.72% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 5.72% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.72% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.72% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.72% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 5.72% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.72% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 5.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 5.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.72% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 196 65.99% 71.72% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 84 28.28% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 22 6.04% 6.04% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 6.04% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 6.04% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.04% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.04% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.04% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 6.04% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.04% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 6.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 6.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.04% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 263 72.25% 78.30% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 79 21.70% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 7289 65.97% 65.99% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1 0.01% 66.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 66.02% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.02% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.02% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.02% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.02% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.02% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.02% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2595 23.49% 89.50% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1160 10.50% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 7749 65.04% 65.05% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1 0.01% 65.06% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.06% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 65.08% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 65.08% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 65.08% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 65.08% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 65.08% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.08% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.08% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.08% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.08% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.08% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.08% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.08% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.08% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.08% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.08% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.08% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.08% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.08% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.08% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.08% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.08% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.08% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.08% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.08% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.08% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.08% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2973 24.95% 90.03% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1188 9.97% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 11049 # Type of FU issued +system.cpu.iq.FU_type_0::total 11915 # Type of FU issued system.cpu.iq.FU_type_1::No_OpClass 2 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_1::IntAlu 7322 66.41% 66.43% # Type of FU issued -system.cpu.iq.FU_type_1::IntMult 1 0.01% 66.44% # Type of FU issued -system.cpu.iq.FU_type_1::IntDiv 0 0.00% 66.44% # Type of FU issued -system.cpu.iq.FU_type_1::FloatAdd 2 0.02% 66.46% # Type of FU issued -system.cpu.iq.FU_type_1::FloatCmp 0 0.00% 66.46% # Type of FU issued -system.cpu.iq.FU_type_1::FloatCvt 0 0.00% 66.46% # Type of FU issued -system.cpu.iq.FU_type_1::FloatMult 0 0.00% 66.46% # Type of FU issued -system.cpu.iq.FU_type_1::FloatDiv 0 0.00% 66.46% # Type of FU issued -system.cpu.iq.FU_type_1::FloatSqrt 0 0.00% 66.46% # Type of FU issued -system.cpu.iq.FU_type_1::SimdAdd 0 0.00% 66.46% # Type of FU issued -system.cpu.iq.FU_type_1::SimdAddAcc 0 0.00% 66.46% # Type of FU issued -system.cpu.iq.FU_type_1::SimdAlu 0 0.00% 66.46% # Type of FU issued -system.cpu.iq.FU_type_1::SimdCmp 0 0.00% 66.46% # Type of FU issued -system.cpu.iq.FU_type_1::SimdCvt 0 0.00% 66.46% # Type of FU issued -system.cpu.iq.FU_type_1::SimdMisc 0 0.00% 66.46% # Type of FU issued -system.cpu.iq.FU_type_1::SimdMult 0 0.00% 66.46% # Type of FU issued -system.cpu.iq.FU_type_1::SimdMultAcc 0 0.00% 66.46% # Type of FU issued -system.cpu.iq.FU_type_1::SimdShift 0 0.00% 66.46% # Type of FU issued -system.cpu.iq.FU_type_1::SimdShiftAcc 0 0.00% 66.46% # Type of FU issued -system.cpu.iq.FU_type_1::SimdSqrt 0 0.00% 66.46% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatAdd 0 0.00% 66.46% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatAlu 0 0.00% 66.46% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatCmp 0 0.00% 66.46% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatCvt 0 0.00% 66.46% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatDiv 0 0.00% 66.46% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatMisc 0 0.00% 66.46% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatMult 0 0.00% 66.46% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatMultAcc 0 0.00% 66.46% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatSqrt 0 0.00% 66.46% # Type of FU issued -system.cpu.iq.FU_type_1::MemRead 2566 23.27% 89.73% # Type of FU issued -system.cpu.iq.FU_type_1::MemWrite 1132 10.27% 100.00% # Type of FU issued +system.cpu.iq.FU_type_1::IntAlu 7559 66.06% 66.08% # Type of FU issued +system.cpu.iq.FU_type_1::IntMult 1 0.01% 66.09% # Type of FU issued +system.cpu.iq.FU_type_1::IntDiv 0 0.00% 66.09% # Type of FU issued +system.cpu.iq.FU_type_1::FloatAdd 2 0.02% 66.11% # Type of FU issued +system.cpu.iq.FU_type_1::FloatCmp 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_1::FloatCvt 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_1::FloatMult 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_1::FloatDiv 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_1::FloatSqrt 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_1::SimdAdd 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_1::SimdAddAcc 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_1::SimdAlu 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_1::SimdCmp 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_1::SimdCvt 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_1::SimdMisc 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_1::SimdMult 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_1::SimdMultAcc 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_1::SimdShift 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_1::SimdShiftAcc 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_1::SimdSqrt 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatAdd 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatAlu 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatCmp 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatCvt 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatDiv 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatMisc 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatMult 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatMultAcc 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatSqrt 0 0.00% 66.11% # Type of FU issued +system.cpu.iq.FU_type_1::MemRead 2735 23.90% 90.01% # Type of FU issued +system.cpu.iq.FU_type_1::MemWrite 1143 9.99% 100.00% # Type of FU issued system.cpu.iq.FU_type_1::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_1::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_1::total 11025 # Type of FU issued -system.cpu.iq.FU_type::total 22074 0.00% 0.00% # Type of FU issued -system.cpu.iq.rate 0.478579 # Inst issue rate -system.cpu.iq.fu_busy_cnt::0 149 # FU busy when requested -system.cpu.iq.fu_busy_cnt::1 148 # FU busy when requested -system.cpu.iq.fu_busy_cnt::total 297 # FU busy when requested -system.cpu.iq.fu_busy_rate::0 0.006750 # FU busy rate (busy events/executed inst) -system.cpu.iq.fu_busy_rate::1 0.006705 # FU busy rate (busy events/executed inst) -system.cpu.iq.fu_busy_rate::total 0.013455 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 72475 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 39437 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 19551 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_1::total 11442 # Type of FU issued +system.cpu.iq.FU_type::total 23357 0.00% 0.00% # Type of FU issued +system.cpu.iq.rate 0.491623 # Inst issue rate +system.cpu.iq.fu_busy_cnt::0 183 # FU busy when requested +system.cpu.iq.fu_busy_cnt::1 181 # FU busy when requested +system.cpu.iq.fu_busy_cnt::total 364 # FU busy when requested +system.cpu.iq.fu_busy_rate::0 0.007835 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_busy_rate::1 0.007749 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_busy_rate::total 0.015584 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 75737 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 42325 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 20244 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 42 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 20 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 20 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 22345 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 23695 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 22 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 67 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 87 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1632 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1937 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 18 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 602 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 655 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 311 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread1.forwLoads 78 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.cacheBlocked 426 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread1.forwLoads 65 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread1.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread1.squashedLoads 1598 # Number of loads squashed -system.cpu.iew.lsq.thread1.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread1.memOrderViolation 20 # Number of memory ordering violations -system.cpu.iew.lsq.thread1.squashedStores 474 # Number of stores squashed +system.cpu.iew.lsq.thread1.squashedLoads 1750 # Number of loads squashed +system.cpu.iew.lsq.thread1.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread1.memOrderViolation 18 # Number of memory ordering violations +system.cpu.iew.lsq.thread1.squashedStores 529 # Number of stores squashed system.cpu.iew.lsq.thread1.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread1.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread1.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread1.cacheBlocked 263 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread1.cacheBlocked 346 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1095 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 2708 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 391 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 26654 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 299 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 5596 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 2806 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 53 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 29 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 359 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 38 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 141 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1078 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1219 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 20887 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts::0 2420 # Number of load instructions executed -system.cpu.iew.iewExecLoadInsts::1 2389 # Number of load instructions executed -system.cpu.iew.iewExecLoadInsts::total 4809 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1187 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1245 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 2860 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 601 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 28216 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 318 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 6053 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 2914 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 51 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 32 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 571 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 36 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 148 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1270 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1418 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 21922 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts::0 2766 # Number of load instructions executed +system.cpu.iew.iewExecLoadInsts::1 2537 # Number of load instructions executed +system.cpu.iew.iewExecLoadInsts::total 5303 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1435 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp::0 0 # number of swp insts executed system.cpu.iew.exec_swp::1 0 # number of swp insts executed system.cpu.iew.exec_swp::total 0 # number of swp insts executed -system.cpu.iew.exec_nop::0 73 # number of nop insts executed +system.cpu.iew.exec_nop::0 71 # number of nop insts executed system.cpu.iew.exec_nop::1 73 # number of nop insts executed -system.cpu.iew.exec_nop::total 146 # number of nop insts executed -system.cpu.iew.exec_refs::0 3521 # number of memory reference insts executed -system.cpu.iew.exec_refs::1 3470 # number of memory reference insts executed -system.cpu.iew.exec_refs::total 6991 # number of memory reference insts executed -system.cpu.iew.exec_branches::0 1644 # Number of branches executed -system.cpu.iew.exec_branches::1 1667 # Number of branches executed -system.cpu.iew.exec_branches::total 3311 # Number of branches executed -system.cpu.iew.exec_stores::0 1101 # Number of stores executed -system.cpu.iew.exec_stores::1 1081 # Number of stores executed -system.cpu.iew.exec_stores::total 2182 # Number of stores executed -system.cpu.iew.exec_rate 0.452845 # Inst execution rate -system.cpu.iew.wb_sent::0 9956 # cumulative count of insts sent to commit -system.cpu.iew.wb_sent::1 9970 # cumulative count of insts sent to commit -system.cpu.iew.wb_sent::total 19926 # cumulative count of insts sent to commit -system.cpu.iew.wb_count::0 9780 # cumulative count of insts written-back -system.cpu.iew.wb_count::1 9791 # cumulative count of insts written-back -system.cpu.iew.wb_count::total 19571 # cumulative count of insts written-back -system.cpu.iew.wb_producers::0 5173 # num instructions producing a value -system.cpu.iew.wb_producers::1 5150 # num instructions producing a value -system.cpu.iew.wb_producers::total 10323 # num instructions producing a value -system.cpu.iew.wb_consumers::0 6916 # num instructions consuming a value -system.cpu.iew.wb_consumers::1 6837 # num instructions consuming a value -system.cpu.iew.wb_consumers::total 13753 # num instructions consuming a value +system.cpu.iew.exec_nop::total 144 # number of nop insts executed +system.cpu.iew.exec_refs::0 3883 # number of memory reference insts executed +system.cpu.iew.exec_refs::1 3616 # number of memory reference insts executed +system.cpu.iew.exec_refs::total 7499 # number of memory reference insts executed +system.cpu.iew.exec_branches::0 1763 # Number of branches executed +system.cpu.iew.exec_branches::1 1733 # Number of branches executed +system.cpu.iew.exec_branches::total 3496 # Number of branches executed +system.cpu.iew.exec_stores::0 1117 # Number of stores executed +system.cpu.iew.exec_stores::1 1079 # Number of stores executed +system.cpu.iew.exec_stores::total 2196 # Number of stores executed +system.cpu.iew.exec_rate 0.461419 # Inst execution rate +system.cpu.iew.wb_sent::0 10477 # cumulative count of insts sent to commit +system.cpu.iew.wb_sent::1 10192 # cumulative count of insts sent to commit +system.cpu.iew.wb_sent::total 20669 # cumulative count of insts sent to commit +system.cpu.iew.wb_count::0 10260 # cumulative count of insts written-back +system.cpu.iew.wb_count::1 10004 # cumulative count of insts written-back +system.cpu.iew.wb_count::total 20264 # cumulative count of insts written-back +system.cpu.iew.wb_producers::0 5390 # num instructions producing a value +system.cpu.iew.wb_producers::1 5243 # num instructions producing a value +system.cpu.iew.wb_producers::total 10633 # num instructions producing a value +system.cpu.iew.wb_consumers::0 7128 # num instructions consuming a value +system.cpu.iew.wb_consumers::1 6992 # num instructions consuming a value +system.cpu.iew.wb_consumers::total 14120 # num instructions consuming a value system.cpu.iew.wb_penalized::0 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_penalized::1 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_penalized::total 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate::0 0.212037 # insts written-back per cycle -system.cpu.iew.wb_rate::1 0.212276 # insts written-back per cycle -system.cpu.iew.wb_rate::total 0.424313 # insts written-back per cycle -system.cpu.iew.wb_fanout::0 0.747976 # average fanout of values written-back -system.cpu.iew.wb_fanout::1 0.753254 # average fanout of values written-back -system.cpu.iew.wb_fanout::total 0.750600 # average fanout of values written-back +system.cpu.iew.wb_rate::0 0.215955 # insts written-back per cycle +system.cpu.iew.wb_rate::1 0.210566 # insts written-back per cycle +system.cpu.iew.wb_rate::total 0.426521 # insts written-back per cycle +system.cpu.iew.wb_fanout::0 0.756173 # average fanout of values written-back +system.cpu.iew.wb_fanout::1 0.749857 # average fanout of values written-back +system.cpu.iew.wb_fanout::total 0.753045 # average fanout of values written-back system.cpu.iew.wb_penalized_rate::0 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.wb_penalized_rate::1 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.wb_penalized_rate::total 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 13856 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 15441 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 34 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1015 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 27930 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.457501 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.335540 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1167 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 28457 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.449028 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.318063 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 22902 82.00% 82.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 2402 8.60% 90.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 1059 3.79% 94.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 373 1.34% 95.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 324 1.16% 96.89% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 194 0.69% 97.58% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 197 0.71% 98.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 141 0.50% 98.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 338 1.21% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 23389 82.19% 82.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 2450 8.61% 90.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 1057 3.71% 94.51% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 365 1.28% 95.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 316 1.11% 96.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 193 0.68% 97.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 226 0.79% 98.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 154 0.54% 98.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 307 1.08% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 27930 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 28457 # Number of insts commited each cycle system.cpu.commit.committedInsts::0 6389 # Number of instructions committed system.cpu.commit.committedInsts::1 6389 # Number of instructions committed system.cpu.commit.committedInsts::total 12778 # Number of instructions committed @@ -725,232 +707,318 @@ system.cpu.commit.op_class_1::IprAccess 0 0.00% 100.00% # Cl system.cpu.commit.op_class_1::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_1::total 6389 # Class of committed instruction system.cpu.commit.op_class::total 12778 0.00% 0.00% # Class of committed instruction -system.cpu.commit.bw_lim_events 338 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 307 # number cycles where commit BW limit reached system.cpu.commit.bw_limited::0 0 # number of insts not committed due to BW limits system.cpu.commit.bw_limited::1 0 # number of insts not committed due to BW limits system.cpu.commit.bw_limited::total 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 129256 # The number of ROB reads -system.cpu.rob.rob_writes 55848 # The number of ROB writes -system.cpu.timesIdled 409 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 18125 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 133653 # The number of ROB reads +system.cpu.rob.rob_writes 59305 # The number of ROB writes +system.cpu.timesIdled 412 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 18940 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts::0 6372 # Number of Instructions Simulated system.cpu.committedInsts::1 6372 # Number of Instructions Simulated system.cpu.committedInsts::total 12744 # Number of Instructions Simulated system.cpu.committedOps::0 6372 # Number of Ops (including micro ops) Simulated system.cpu.committedOps::1 6372 # Number of Ops (including micro ops) Simulated system.cpu.committedOps::total 12744 # Number of Ops (including micro ops) Simulated -system.cpu.cpi::0 7.238544 # CPI: Cycles Per Instruction -system.cpu.cpi::1 7.238544 # CPI: Cycles Per Instruction -system.cpu.cpi_total 3.619272 # CPI: Total CPI of All Threads -system.cpu.ipc::0 0.138149 # IPC: Instructions Per Cycle -system.cpu.ipc::1 0.138149 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.276299 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 26325 # number of integer regfile reads -system.cpu.int_regfile_writes 14897 # number of integer regfile writes +system.cpu.cpi::0 7.456058 # CPI: Cycles Per Instruction +system.cpu.cpi::1 7.456058 # CPI: Cycles Per Instruction +system.cpu.cpi_total 3.728029 # CPI: Total CPI of All Threads +system.cpu.ipc::0 0.134119 # IPC: Instructions Per Cycle +system.cpu.ipc::1 0.134119 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.268238 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 27427 # number of integer regfile reads +system.cpu.int_regfile_writes 15512 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads system.cpu.fp_regfile_writes 4 # number of floating regfile writes system.cpu.misc_regfile_reads 2 # number of misc regfile reads system.cpu.misc_regfile_writes 2 # number of misc regfile writes -system.cpu.toL2Bus.trans_dist::ReadReq 835 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 835 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 146 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 146 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1272 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 690 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 1962 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 40704 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22080 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 62784 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 981 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 981 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 981 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 490500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 2.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1047000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 4.5 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 547500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 2.4 # Layer utilization (%) +system.cpu.dcache.tags.replacements::0 0 # number of replacements +system.cpu.dcache.tags.replacements::1 0 # number of replacements +system.cpu.dcache.tags.replacements::total 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 215.485703 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 5082 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 349 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 14.561605 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 215.485703 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.052609 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.052609 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 349 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 96 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 253 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.085205 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 12575 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 12575 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 4060 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 4060 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 1022 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 1022 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 5082 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 5082 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 5082 # number of overall hits +system.cpu.dcache.overall_hits::total 5082 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 323 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 323 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 708 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 708 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1031 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1031 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1031 # number of overall misses +system.cpu.dcache.overall_misses::total 1031 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 22902750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 22902750 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 50997162 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 50997162 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 73899912 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 73899912 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 73899912 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 73899912 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 4383 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 4383 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 1730 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 1730 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 6113 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 6113 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 6113 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 6113 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.073694 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.073694 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.409249 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.409249 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.168657 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.168657 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.168657 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.168657 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 70906.346749 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 70906.346749 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 72029.889831 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 72029.889831 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 71677.897187 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 71677.897187 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 71677.897187 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 71677.897187 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 5816 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 146 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 39.835616 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 119 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 119 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 563 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 563 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 682 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 682 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 682 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 682 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 204 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 204 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 145 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 145 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 349 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 349 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 349 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 349 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 16652250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 16652250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11883990 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 11883990 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28536240 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 28536240 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28536240 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 28536240 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.046543 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.046543 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.083815 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.083815 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.057091 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.057091 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.057091 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.057091 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 81628.676471 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 81628.676471 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 81958.551724 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 81958.551724 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 81765.730659 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 81765.730659 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 81765.730659 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 81765.730659 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements::0 7 # number of replacements system.cpu.icache.tags.replacements::1 0 # number of replacements system.cpu.icache.tags.replacements::total 7 # number of replacements -system.cpu.icache.tags.tagsinuse 316.469432 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 4175 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 636 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 6.564465 # Average number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 320.653868 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 4726 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 628 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 7.525478 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 316.469432 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.154526 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.154526 # Average percentage of cache occupancy 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ReadReq misses -system.cpu.icache.ReadReq_misses::total 942 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 942 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 942 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 942 # number of overall misses -system.cpu.icache.overall_misses::total 942 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 64530491 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 64530491 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 64530491 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 64530491 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 64530491 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 64530491 # number of overall miss cycles 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Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 621 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 261 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 360 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.303223 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 11936 # Number of tag accesses +system.cpu.icache.tags.data_accesses 11936 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 4726 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 4726 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 4726 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 4726 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 4726 # number of overall hits +system.cpu.icache.overall_hits::total 4726 # number of overall hits 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of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 5654 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 5654 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 5654 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 5654 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 5654 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 5654 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.164132 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.164132 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.164132 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.164132 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.164132 # miss rate for overall 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306 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 636 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 636 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 636 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 636 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 636 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 636 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 46571744 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 46571744 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 46571744 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 46571744 # number of demand (read+write) MSHR miss cycles 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MSHR hits -system.cpu.dcache.demand_mshr_hits::total 681 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 681 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 681 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 199 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 199 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 146 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 146 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 345 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 345 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 345 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 345 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 16277750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 16277750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12037990 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 12037990 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28315740 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 28315740 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28315740 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 28315740 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.048858 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.048858 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.059452 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.059452 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.059452 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.059452 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 81797.738693 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 81797.738693 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 82451.986301 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 82451.986301 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 82074.608696 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 82074.608696 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 82074.608696 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 82074.608696 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.trans_dist::ReadReq 832 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 832 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 145 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 145 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1256 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 698 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 1954 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 40192 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22336 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 62528 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 977 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 977 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 977 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 488500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 2.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1032000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 4.3 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 556000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 2.3 # Layer utilization (%) +system.membus.trans_dist::ReadReq 830 # Transaction distribution +system.membus.trans_dist::ReadResp 830 # Transaction distribution +system.membus.trans_dist::ReadExReq 145 # Transaction distribution +system.membus.trans_dist::ReadExResp 145 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1950 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1950 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 62400 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 62400 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 975 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 975 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 975 # Request fanout histogram +system.membus.reqLayer0.occupancy 1213500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 5.1 # Layer utilization (%) +system.membus.respLayer1.occupancy 9051500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 38.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt index 2e75d917e..766e4c6e5 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000028 # Nu sim_ticks 27671000 # Number of ticks simulated final_tick 27671000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 16681 # Simulator instruction rate (inst/s) -host_op_rate 16680 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 30441710 # Simulator tick rate (ticks/s) -host_mem_usage 234904 # Number of bytes of host memory used -host_seconds 0.91 # Real time elapsed on the host +host_inst_rate 95145 # Simulator instruction rate (inst/s) +host_op_rate 95137 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 173614335 # Simulator tick rate (ticks/s) +host_mem_usage 289900 # Number of bytes of host memory used +host_seconds 0.16 # Real time elapsed on the host sim_insts 15162 # Number of instructions simulated sim_ops 15162 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -221,53 +221,34 @@ system.physmem.readRowHitRate 83.03 # Ro system.physmem.writeRowHitRate nan # Row buffer hit rate for writes system.physmem.avgGap 63388.76 # Average gap between requests system.physmem.pageHitRate 83.03 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 1258750 # Time in different power states -system.physmem.memoryStateTime::REF 780000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 21626500 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 287280 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 204120 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 156750 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 111375 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 1786200 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 1232400 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 1525680 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 1525680 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 15269445 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 14648715 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 797250 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 1341750 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 19822605 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 19064040 # Total energy per rank (pJ) -system.physmem.averagePower::0 838.076525 # Core power per rank (mW) -system.physmem.averagePower::1 806.005285 # Core power per rank (mW) -system.membus.trans_dist::ReadReq 351 # Transaction distribution -system.membus.trans_dist::ReadResp 350 # Transaction distribution -system.membus.trans_dist::ReadExReq 85 # Transaction distribution -system.membus.trans_dist::ReadExResp 85 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 871 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 871 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 27840 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 27840 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 436 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 436 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 436 # Request fanout histogram -system.membus.reqLayer0.occupancy 519500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 1.9 # Layer utilization (%) -system.membus.respLayer1.occupancy 4048500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 14.6 # Layer utilization (%) -system.cpu_clk_domain.clock 500 # Clock period in ticks +system.physmem_0.actEnergy 287280 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 156750 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1786200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 15269445 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 797250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 19822605 # Total energy per rank (pJ) +system.physmem_0.averagePower 838.076525 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1258750 # Time in different power states +system.physmem_0.memoryStateTime::REF 780000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 21626500 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 204120 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 111375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1232400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 14625630 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1341750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 19040955 # Total energy per rank (pJ) +system.physmem_1.averagePower 806.179624 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 4247250 # Time in different power states +system.physmem_1.memoryStateTime::REF 780000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 20686250 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.branchPred.lookups 5146 # Number of BP lookups system.cpu.branchPred.condPredicted 3529 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 2366 # Number of conditional branches incorrect @@ -277,6 +258,7 @@ system.cpu.branchPred.BTBCorrect 0 # Nu system.cpu.branchPred.BTBHitPct 66.317073 # BTB Hit Percentage system.cpu.branchPred.usedRAS 174 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 5 # Number of incorrect RAS predictions. +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.workload.num_syscalls 18 # Number of system calls system.cpu.numCycles 55343 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started @@ -338,6 +320,122 @@ system.cpu.stage3.utilization 5.200296 # Pe system.cpu.stage4.idleCycles 46034 # Number of cycles 0 instructions are processed. system.cpu.stage4.runCycles 9309 # Number of cycles 1+ instructions are processed. system.cpu.stage4.utilization 16.820555 # Percentage of cycles stage was utilized (processing insts). +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 98.529834 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 3193 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 138 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 23.137681 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 98.529834 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.024055 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.024055 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 138 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 122 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.033691 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 7484 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 7484 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 2167 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 2167 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 1020 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 1020 # number of WriteReq hits +system.cpu.dcache.SwapReq_hits::cpu.data 6 # number of SwapReq hits +system.cpu.dcache.SwapReq_hits::total 6 # number of SwapReq hits +system.cpu.dcache.demand_hits::cpu.data 3187 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 3187 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 3187 # number of overall hits +system.cpu.dcache.overall_hits::total 3187 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 58 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 58 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 422 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 422 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 480 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 480 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 480 # number of overall misses +system.cpu.dcache.overall_misses::total 480 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 4268250 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4268250 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 25898250 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 25898250 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 30166500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 30166500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 30166500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 30166500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 2225 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 2225 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 1442 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SwapReq_accesses::cpu.data 6 # number of SwapReq accesses(hits+misses) +system.cpu.dcache.SwapReq_accesses::total 6 # number of SwapReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 3667 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 3667 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 3667 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 3667 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.026067 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.026067 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.292649 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.292649 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.130897 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.130897 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.130897 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.130897 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 73590.517241 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 73590.517241 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61370.260664 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 61370.260664 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 62846.875000 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 62846.875000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 62846.875000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 62846.875000 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 1102 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 33 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 33.393939 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 5 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 5 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 337 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 337 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 342 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 342 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 342 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 342 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 53 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 53 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 85 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 85 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 138 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3749750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3749750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6087750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 6087750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9837500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9837500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9837500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 9837500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.023820 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.023820 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.058946 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.058946 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.037633 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.037633 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.037633 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.037633 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 70750 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 70750 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71620.588235 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71620.588235 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 71286.231884 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 71286.231884 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 71286.231884 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 71286.231884 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements system.cpu.icache.tags.tagsinuse 168.877638 # Cycle average of tags in use system.cpu.icache.tags.total_refs 3004 # Total number of references to valid blocks. @@ -428,34 +526,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 67971.760797 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 67971.760797 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 67971.760797 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 354 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 352 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 85 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 85 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 600 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 276 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 876 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 19136 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8832 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 27968 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 439 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 439 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 439 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 219500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 500000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 1.8 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 222000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) system.cpu.l2cache.tags.replacements 0 # number of replacements system.cpu.l2cache.tags.tagsinuse 199.907137 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. @@ -587,121 +657,56 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54914.715719 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57909.420290 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55860.411899 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 98.529834 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 3193 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 138 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 23.137681 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 98.529834 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.024055 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.024055 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 138 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 122 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.033691 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 7484 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 7484 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 2167 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 2167 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 1020 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 1020 # number of WriteReq hits -system.cpu.dcache.SwapReq_hits::cpu.data 6 # number of SwapReq hits -system.cpu.dcache.SwapReq_hits::total 6 # number of SwapReq hits -system.cpu.dcache.demand_hits::cpu.data 3187 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 3187 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 3187 # number of overall hits -system.cpu.dcache.overall_hits::total 3187 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 58 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 58 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 422 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 422 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 480 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 480 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 480 # number of overall misses -system.cpu.dcache.overall_misses::total 480 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 4268250 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 4268250 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 25898250 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 25898250 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 30166500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 30166500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 30166500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 30166500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 2225 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 2225 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 1442 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SwapReq_accesses::cpu.data 6 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.SwapReq_accesses::total 6 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 3667 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 3667 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 3667 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 3667 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.026067 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.026067 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.292649 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.292649 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.130897 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.130897 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.130897 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.130897 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 73590.517241 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 73590.517241 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61370.260664 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 61370.260664 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 62846.875000 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 62846.875000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 62846.875000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 62846.875000 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 1102 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 33 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 33.393939 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 5 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 5 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 337 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 337 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 342 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 342 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 342 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 342 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 53 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 53 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 85 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 85 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 138 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3749750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3749750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6087750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 6087750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9837500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 9837500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9837500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 9837500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.023820 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.023820 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.058946 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.058946 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.037633 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.037633 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.037633 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.037633 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 70750 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 70750 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71620.588235 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71620.588235 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 71286.231884 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 71286.231884 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 71286.231884 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 71286.231884 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.trans_dist::ReadReq 354 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 352 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 85 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 85 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 600 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 276 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 876 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 19136 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8832 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 27968 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 439 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 439 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 439 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 219500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 500000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 1.8 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 222000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) +system.membus.trans_dist::ReadReq 351 # Transaction distribution +system.membus.trans_dist::ReadResp 350 # Transaction distribution +system.membus.trans_dist::ReadExReq 85 # Transaction distribution +system.membus.trans_dist::ReadExResp 85 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 871 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 871 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 27840 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 27840 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 436 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 436 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 436 # Request fanout histogram +system.membus.reqLayer0.occupancy 519500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.9 # Layer utilization (%) +system.membus.respLayer1.occupancy 4048500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 14.6 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt index 9c69b7311..b851aeb29 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000026 # Nu sim_ticks 25944000 # Number of ticks simulated final_tick 25944000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 15615 # Simulator instruction rate (inst/s) -host_op_rate 15615 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 28062245 # Simulator tick rate (ticks/s) -host_mem_usage 236980 # Number of bytes of host memory used -host_seconds 0.92 # Real time elapsed on the host +host_inst_rate 95549 # Simulator instruction rate (inst/s) +host_op_rate 95539 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 171686089 # Simulator tick rate (ticks/s) +host_mem_usage 292480 # Number of bytes of host memory used +host_seconds 0.15 # Real time elapsed on the host sim_insts 14436 # Number of instructions simulated sim_ops 14436 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -222,53 +222,34 @@ system.physmem.readRowHitRate 83.54 # Ro system.physmem.writeRowHitRate nan # Row buffer hit rate for writes system.physmem.avgGap 52627.03 # Average gap between requests system.physmem.pageHitRate 83.54 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 279250 # Time in different power states -system.physmem.memoryStateTime::REF 780000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 22761250 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 309960 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 226800 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 169125 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 123750 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 2106000 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 1318200 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 1525680 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 1525680 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 16044930 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 14873580 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 96750 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 1124250 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 20252445 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 19192260 # Total energy per rank (pJ) -system.physmem.averagePower::0 857.473194 # Core power per rank (mW) -system.physmem.averagePower::1 812.585763 # Core power per rank (mW) -system.membus.trans_dist::ReadReq 409 # Transaction distribution -system.membus.trans_dist::ReadResp 408 # Transaction distribution -system.membus.trans_dist::ReadExReq 83 # Transaction distribution -system.membus.trans_dist::ReadExResp 83 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 983 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 983 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 31424 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 31424 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 492 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 492 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 492 # Request fanout histogram -system.membus.reqLayer0.occupancy 611000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.4 # Layer utilization (%) -system.membus.respLayer1.occupancy 4586750 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 17.7 # Layer utilization (%) -system.cpu_clk_domain.clock 500 # Clock period in ticks +system.physmem_0.actEnergy 309960 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 169125 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 2106000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 16044930 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 96750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 20252445 # Total energy per rank (pJ) +system.physmem_0.averagePower 857.473194 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 279250 # Time in different power states +system.physmem_0.memoryStateTime::REF 780000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 22761250 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 226800 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 123750 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1318200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 14873580 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1124250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 19192260 # Total energy per rank (pJ) +system.physmem_1.averagePower 812.585763 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2246250 # Time in different power states +system.physmem_1.memoryStateTime::REF 780000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 21062250 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.branchPred.lookups 8578 # Number of BP lookups system.cpu.branchPred.condPredicted 5479 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 1058 # Number of conditional branches incorrect @@ -278,6 +259,7 @@ system.cpu.branchPred.BTBCorrect 0 # Nu system.cpu.branchPred.BTBHitPct 50.673765 # BTB Hit Percentage system.cpu.branchPred.usedRAS 607 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 166 # Number of incorrect RAS predictions. +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.workload.num_syscalls 18 # Number of system calls system.cpu.numCycles 51889 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started @@ -566,34 +548,122 @@ system.cpu.int_regfile_reads 33401 # nu system.cpu.int_regfile_writes 18599 # number of integer regfile writes system.cpu.misc_regfile_reads 7136 # number of misc regfile reads system.cpu.misc_regfile_writes 569 # number of misc regfile writes -system.cpu.toL2Bus.trans_dist::ReadReq 411 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 410 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 83 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 83 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 692 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 295 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 987 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 22144 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9408 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 31552 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 494 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 494 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 494 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 247000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 579250 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 233000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 98.823294 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 4124 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 147 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 28.054422 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 98.823294 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.024127 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.024127 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 147 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 22 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 125 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.035889 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 9491 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 9491 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 3085 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 3085 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 1033 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 1033 # number of WriteReq hits +system.cpu.dcache.SwapReq_hits::cpu.data 6 # number of SwapReq hits +system.cpu.dcache.SwapReq_hits::total 6 # number of SwapReq hits +system.cpu.dcache.demand_hits::cpu.data 4118 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 4118 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 4118 # number of overall hits +system.cpu.dcache.overall_hits::total 4118 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 139 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 139 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 409 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 409 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 548 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 548 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 548 # number of overall misses +system.cpu.dcache.overall_misses::total 548 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 8670750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 8670750 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 26093224 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 26093224 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 34763974 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 34763974 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 34763974 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 34763974 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 3224 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 3224 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 1442 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SwapReq_accesses::cpu.data 6 # number of SwapReq accesses(hits+misses) +system.cpu.dcache.SwapReq_accesses::total 6 # number of SwapReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 4666 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 4666 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 4666 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 4666 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.043114 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.043114 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.283634 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.283634 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.117445 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.117445 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.117445 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.117445 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62379.496403 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 62379.496403 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63797.613692 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 63797.613692 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 63437.908759 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 63437.908759 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 63437.908759 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 63437.908759 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 955 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 30 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 31.833333 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 74 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 74 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 326 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 326 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 400 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 400 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 400 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 400 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 65 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 65 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 83 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 83 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 148 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 148 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 148 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 148 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4741000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4741000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6235500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 6235500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10976500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10976500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10976500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10976500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.020161 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.020161 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.057559 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.057559 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.031719 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.031719 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.031719 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.031719 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 72938.461538 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 72938.461538 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75126.506024 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75126.506024 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74165.540541 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 74165.540541 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74165.540541 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 74165.540541 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements system.cpu.icache.tags.tagsinuse 192.510962 # Cycle average of tags in use system.cpu.icache.tags.total_refs 5925 # Total number of references to valid blocks. @@ -815,121 +885,56 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53335.029070 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60952.702703 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55626.524390 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 98.823294 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 4124 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 147 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 28.054422 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 98.823294 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.024127 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.024127 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 147 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 22 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 125 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.035889 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 9491 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 9491 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 3085 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 3085 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 1033 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 1033 # number of WriteReq hits -system.cpu.dcache.SwapReq_hits::cpu.data 6 # number of SwapReq hits -system.cpu.dcache.SwapReq_hits::total 6 # number of SwapReq hits -system.cpu.dcache.demand_hits::cpu.data 4118 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 4118 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 4118 # number of overall hits -system.cpu.dcache.overall_hits::total 4118 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 139 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 139 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 409 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 409 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 548 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 548 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 548 # number of overall misses -system.cpu.dcache.overall_misses::total 548 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 8670750 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 8670750 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 26093224 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 26093224 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 34763974 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 34763974 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 34763974 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 34763974 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 3224 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 3224 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 1442 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SwapReq_accesses::cpu.data 6 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.SwapReq_accesses::total 6 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 4666 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 4666 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 4666 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 4666 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.043114 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.043114 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.283634 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.283634 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.117445 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.117445 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.117445 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.117445 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62379.496403 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 62379.496403 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63797.613692 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 63797.613692 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 63437.908759 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 63437.908759 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 63437.908759 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 63437.908759 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 955 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 30 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 31.833333 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 74 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 74 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 326 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 326 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 400 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 400 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 400 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 400 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 65 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 65 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 83 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 83 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 148 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 148 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 148 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 148 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4741000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4741000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6235500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 6235500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10976500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10976500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10976500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10976500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.020161 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.020161 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.057559 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.057559 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.031719 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.031719 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.031719 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.031719 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 72938.461538 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 72938.461538 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75126.506024 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75126.506024 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74165.540541 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 74165.540541 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74165.540541 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 74165.540541 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.trans_dist::ReadReq 411 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 410 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 83 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 83 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 692 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 295 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 987 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 22144 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9408 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 31552 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 494 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 494 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 494 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 247000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 579250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 2.2 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 233000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) +system.membus.trans_dist::ReadReq 409 # Transaction distribution +system.membus.trans_dist::ReadResp 408 # Transaction distribution +system.membus.trans_dist::ReadExReq 83 # Transaction distribution +system.membus.trans_dist::ReadExResp 83 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 983 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 983 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 31424 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 31424 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 492 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 492 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 492 # Request fanout histogram +system.membus.reqLayer0.occupancy 611000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.4 # Layer utilization (%) +system.membus.respLayer1.occupancy 4586750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 17.7 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt index 994a2ff39..ffbae61d5 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt @@ -1,79 +1,79 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000106 # Number of seconds simulated -sim_ticks 105696000 # Number of ticks simulated -final_tick 105696000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 105542000 # Number of ticks simulated +final_tick 105542000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 145069 # Simulator instruction rate (inst/s) -host_op_rate 145069 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 15443503 # Simulator tick rate (ticks/s) -host_mem_usage 252160 # Number of bytes of host memory used -host_seconds 6.84 # Real time elapsed on the host -sim_insts 992854 # Number of instructions simulated -sim_ops 992854 # Number of ops (including micro ops) simulated +host_inst_rate 163449 # Simulator instruction rate (inst/s) +host_op_rate 163449 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 17392605 # Simulator tick rate (ticks/s) +host_mem_usage 309188 # Number of bytes of host memory used +host_seconds 6.07 # Real time elapsed on the host +sim_insts 991839 # Number of instructions simulated +sim_ops 991839 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.inst 23104 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 22976 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.data 10752 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 896 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 768 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.data 832 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 4800 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 4864 # Number of bytes read from this memory system.physmem.bytes_read::cpu2.data 1280 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.inst 256 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.inst 192 # Number of bytes read from this memory system.physmem.bytes_read::cpu3.data 832 # Number of bytes read from this memory -system.physmem.bytes_read::total 42752 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 23104 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 896 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 4800 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu3.inst 256 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 29056 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu0.inst 361 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 42496 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 22976 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 768 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 4864 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu3.inst 192 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 28800 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu0.inst 359 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.data 168 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 14 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.data 13 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 75 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 76 # Number of read requests responded to by this memory system.physmem.num_reads::cpu2.data 20 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.inst 4 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.inst 3 # Number of read requests responded to by this memory system.physmem.num_reads::cpu3.data 13 # Number of read requests responded to by this memory -system.physmem.num_reads::total 668 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu0.inst 218589161 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 101725704 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 8477142 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 7871632 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 45413261 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 12110203 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.inst 2422041 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.data 7871632 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 404480775 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 218589161 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 8477142 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 45413261 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu3.inst 2422041 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 274901605 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 218589161 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 101725704 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 8477142 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 7871632 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 45413261 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 12110203 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.inst 2422041 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.data 7871632 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 404480775 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 669 # Number of read requests accepted +system.physmem.num_reads::total 664 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu0.inst 217695325 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 101874135 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 7276724 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 7883118 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 46085918 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 12127873 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.inst 1819181 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.data 7883118 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 402645392 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 217695325 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 7276724 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 46085918 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu3.inst 1819181 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 272877148 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 217695325 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 101874135 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 7276724 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 7883118 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 46085918 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 12127873 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.inst 1819181 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.data 7883118 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 402645392 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 665 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 669 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 665 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 42816 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 42560 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 42816 # Total read bytes from the system interface side +system.physmem.bytesReadSys 42560 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 78 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 114 # Per bank write bursts system.physmem.perBankRdBursts::1 42 # Per bank write bursts -system.physmem.perBankRdBursts::2 30 # Per bank write bursts +system.physmem.perBankRdBursts::2 27 # Per bank write bursts system.physmem.perBankRdBursts::3 60 # Per bank write bursts system.physmem.perBankRdBursts::4 65 # Per bank write bursts system.physmem.perBankRdBursts::5 28 # Per bank write bursts @@ -81,7 +81,7 @@ system.physmem.perBankRdBursts::6 18 # Pe system.physmem.perBankRdBursts::7 24 # Per bank write bursts system.physmem.perBankRdBursts::8 7 # Per bank write bursts system.physmem.perBankRdBursts::9 28 # Per bank write bursts -system.physmem.perBankRdBursts::10 23 # Per bank write bursts +system.physmem.perBankRdBursts::10 22 # Per bank write bursts system.physmem.perBankRdBursts::11 13 # Per bank write bursts system.physmem.perBankRdBursts::12 65 # Per bank write bursts system.physmem.perBankRdBursts::13 38 # Per bank write bursts @@ -105,14 +105,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 105668000 # Total gap between requests +system.physmem.totGap 105514000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 669 # Read request sizes (log2) +system.physmem.readPktSize::6 665 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -120,10 +120,10 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 399 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 194 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 59 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 13 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 394 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 192 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 61 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -216,812 +216,319 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 143 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 280.167832 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 190.166692 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 257.214493 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 42 29.37% 29.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 39 27.27% 56.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 24 16.78% 73.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 13 9.09% 82.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 6 4.20% 86.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 6 4.20% 90.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 6 4.20% 95.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2 1.40% 96.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 5 3.50% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 143 # Bytes accessed per row activation -system.physmem.totQLat 6392250 # Total ticks spent queuing -system.physmem.totMemAccLat 18936000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 3345000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9554.93 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 142 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 280.338028 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 190.767584 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 256.989000 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 41 28.87% 28.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 38 26.76% 55.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 26 18.31% 73.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 12 8.45% 82.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 6 4.23% 86.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 6 4.23% 90.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 6 4.23% 95.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2 1.41% 96.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 5 3.52% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 142 # Bytes accessed per row activation +system.physmem.totQLat 6421750 # Total ticks spent queuing +system.physmem.totMemAccLat 18890500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 3325000 # Total ticks spent in databus transfers +system.physmem.avgQLat 9656.77 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28304.93 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 405.09 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 28406.77 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 403.25 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 405.09 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 403.25 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 3.16 # Data bus utilization in percentage -system.physmem.busUtilRead 3.16 # Data bus utilization in percentage for reads +system.physmem.busUtil 3.15 # Data bus utilization in percentage +system.physmem.busUtilRead 3.15 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.23 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.24 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 515 # Number of row buffer hits during reads +system.physmem.readRowHits 512 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 76.98 # Row buffer hit rate for reads +system.physmem.readRowHitRate 76.99 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 157949.18 # Average gap between requests -system.physmem.pageHitRate 76.98 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 46119750 # Time in different power states -system.physmem.memoryStateTime::REF 3380000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 52590250 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 695520 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 355320 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 379500 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 193875 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 2776800 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 2051400 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 6611280 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 6611280 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 36176760 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 31269060 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 29154750 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 33459750 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 75794610 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 73940685 # Total energy per rank (pJ) -system.physmem.averagePower::0 746.882897 # Core power per rank (mW) -system.physmem.averagePower::1 728.614251 # Core power per rank (mW) -system.membus.trans_dist::ReadReq 538 # Transaction distribution -system.membus.trans_dist::ReadResp 537 # Transaction distribution -system.membus.trans_dist::UpgradeReq 276 # Transaction distribution -system.membus.trans_dist::UpgradeResp 78 # Transaction distribution -system.membus.trans_dist::ReadExReq 177 # Transaction distribution -system.membus.trans_dist::ReadExResp 131 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1737 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1737 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 42752 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 42752 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 244 # Total snoops (count) -system.membus.snoop_fanout::samples 991 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 991 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 991 # Request fanout histogram -system.membus.reqLayer0.occupancy 940500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.9 # Layer utilization (%) -system.membus.respLayer1.occupancy 6384422 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 6.0 # Layer utilization (%) -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 0 # number of replacements -system.l2c.tags.tagsinuse 424.241443 # Cycle average of tags in use -system.l2c.tags.total_refs 1667 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 535 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 3.115888 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 0.793516 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 289.763968 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 58.233930 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 9.364536 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 0.722908 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 57.054480 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 5.356180 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.inst 2.266531 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.data 0.685395 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.000012 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.004421 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.000889 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.000143 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.000011 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.000871 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.000082 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.inst 0.000035 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.data 0.000010 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.006473 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 535 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 368 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 117 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.008163 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 20109 # Number of tag accesses -system.l2c.tags.data_accesses 20109 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.inst 250 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 480 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 11 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.inst 413 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.data 5 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu3.inst 492 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu3.data 11 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1667 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 1 # number of Writeback hits -system.l2c.Writeback_hits::total 1 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 3 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 3 # number of UpgradeReq hits -system.l2c.demand_hits::cpu0.inst 250 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 480 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 11 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.inst 413 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.data 5 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3.inst 492 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3.data 11 # number of demand (read+write) hits -system.l2c.demand_hits::total 1667 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 250 # number of overall hits -system.l2c.overall_hits::cpu0.data 5 # number of overall hits -system.l2c.overall_hits::cpu1.inst 480 # number of overall hits -system.l2c.overall_hits::cpu1.data 11 # number of overall hits -system.l2c.overall_hits::cpu2.inst 413 # number of overall hits -system.l2c.overall_hits::cpu2.data 5 # number of overall hits -system.l2c.overall_hits::cpu3.inst 492 # number of overall hits -system.l2c.overall_hits::cpu3.data 11 # number of overall hits -system.l2c.overall_hits::total 1667 # number of overall hits -system.l2c.ReadReq_misses::cpu0.inst 363 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 74 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 17 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.inst 80 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.data 7 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu3.inst 7 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu3.data 1 # number of ReadReq misses -system.l2c.ReadReq_misses::total 550 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 23 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 17 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2.data 18 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu3.data 20 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 78 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 94 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 12 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu2.data 13 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu3.data 12 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 131 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.inst 363 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 168 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 17 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 13 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.inst 80 # number of demand (read+write) misses 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cycles -system.l2c.ReadReq_miss_latency::cpu0.data 5642000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 1337250 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 75000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.inst 5652250 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.data 765250 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu3.inst 458000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu3.data 75000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 39069000 # number of ReadReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 6921000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 852750 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu2.data 1047250 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu3.data 837000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 9658000 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.inst 25064250 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 12563000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 1337250 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 927750 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.inst 5652250 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.data 1812500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu3.inst 458000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu3.data 912000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 48727000 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.inst 25064250 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 12563000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 1337250 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 927750 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.inst 5652250 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.data 1812500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu3.inst 458000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu3.data 912000 # number of overall miss cycles -system.l2c.overall_miss_latency::total 48727000 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.inst 613 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 79 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 497 # number of ReadReq accesses(hits+misses) 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demand accesses -system.l2c.demand_mshr_miss_rate::total 0.284923 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.590538 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.971098 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.028169 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.541667 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.inst 0.152130 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.data 0.800000 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu3.inst 0.008016 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu3.data 0.541667 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.284923 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 56569.751381 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 63905.405405 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 70357.142857 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 62500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 59290 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 96964.285714 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 59062.500000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 62500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 58882.899628 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10001 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 10001 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 61292.553191 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 58437.500000 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 68326.923077 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 57250 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 61358.778626 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 56569.751381 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 62443.452381 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 70357.142857 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 58750 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 59290 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 78350 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 59062.500000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.data 57653.846154 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 59367.713004 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 56569.751381 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 62443.452381 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 70357.142857 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 58750 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 59290 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 78350 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 59062.500000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.data 57653.846154 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 59367.713004 # average overall mshr miss latency -system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.toL2Bus.trans_dist::ReadReq 2766 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2765 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 1 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 279 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 279 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 406 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 406 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1225 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 583 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 994 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 366 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 986 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 353 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 998 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 375 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 5880 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 39168 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 11136 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 31808 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1536 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 31552 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 31936 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 1536 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 150272 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 1022 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 3452 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 7 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram -system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::5 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::6 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::7 3452 100.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::min_value 7 # Request fanout histogram -system.toL2Bus.snoop_fanout::max_value 7 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 3452 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 1739480 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 1.6 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 2819999 # Layer occupancy (ticks) -system.toL2Bus.respLayer0.utilization 2.7 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1460516 # Layer occupancy (ticks) -system.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 2239746 # Layer occupancy (ticks) -system.toL2Bus.respLayer2.utilization 2.1 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 1188247 # Layer occupancy (ticks) -system.toL2Bus.respLayer3.utilization 1.1 # Layer utilization (%) -system.toL2Bus.respLayer4.occupancy 2234243 # Layer occupancy (ticks) -system.toL2Bus.respLayer4.utilization 2.1 # Layer utilization (%) -system.toL2Bus.respLayer5.occupancy 1152996 # Layer occupancy (ticks) -system.toL2Bus.respLayer5.utilization 1.1 # Layer utilization (%) -system.toL2Bus.respLayer6.occupancy 2246748 # Layer occupancy (ticks) -system.toL2Bus.respLayer6.utilization 2.1 # Layer utilization (%) -system.toL2Bus.respLayer7.occupancy 1204495 # Layer occupancy (ticks) -system.toL2Bus.respLayer7.utilization 1.1 # Layer utilization (%) -system.cpu0.branchPred.lookups 81418 # Number of BP lookups -system.cpu0.branchPred.condPredicted 78534 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 1187 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 78143 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 75395 # Number of BTB hits +system.physmem.avgGap 158667.67 # Average gap between requests +system.physmem.pageHitRate 76.99 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 687960 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 375375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 2753400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 6611280 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 29877120 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 34680750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 74985885 # Total energy per rank (pJ) +system.physmem_0.averagePower 738.913691 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 57973250 # Time in different power states +system.physmem_0.memoryStateTime::REF 3380000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 40577250 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 355320 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 193875 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 2043600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 6611280 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 27463455 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 36789750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 73457280 # Total energy per rank (pJ) +system.physmem_1.averagePower 723.948851 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 62480000 # Time in different power states +system.physmem_1.memoryStateTime::REF 3380000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 37046000 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu0.branchPred.lookups 81296 # Number of BP lookups +system.cpu0.branchPred.condPredicted 78365 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 1199 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 77900 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 75117 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 96.483370 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 733 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.BTBHitPct 96.427471 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 763 # Number of times the RAS was used to get a target. system.cpu0.branchPred.RASInCorrect 128 # Number of incorrect RAS predictions. +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.workload.num_syscalls 89 # Number of system calls -system.cpu0.numCycles 211393 # number of cpu cycles simulated +system.cpu0.numCycles 211085 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 20064 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 481063 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 81418 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 76128 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 164143 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 2675 # Number of cycles fetch has spent squashing +system.cpu0.fetch.icacheStallCycles 20068 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 480268 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 81296 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 75880 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 163785 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 2699 # Number of cycles fetch has spent squashing system.cpu0.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 1880 # Number of stall cycles due to pending traps -system.cpu0.fetch.CacheLines 7123 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 658 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.rateDist::samples 187427 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 2.566669 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.225288 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.PendingTrapStallCycles 1916 # Number of stall cycles due to pending traps +system.cpu0.fetch.CacheLines 7139 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 648 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.rateDist::samples 187121 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 2.566617 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.228608 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 30149 16.09% 16.09% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 77654 41.43% 57.52% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 823 0.44% 57.96% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 1078 0.58% 58.53% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 624 0.33% 58.86% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 72980 38.94% 97.80% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 691 0.37% 98.17% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 437 0.23% 98.40% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 2991 1.60% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 30271 16.18% 16.18% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 77424 41.38% 57.55% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 764 0.41% 57.96% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 1076 0.58% 58.54% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 624 0.33% 58.87% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 72740 38.87% 97.74% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 718 0.38% 98.13% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 448 0.24% 98.37% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 3056 1.63% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 187427 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.385150 # Number of branch fetches per cycle -system.cpu0.fetch.rate 2.275681 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 15737 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 17837 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 151841 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 675 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1337 # Number of cycles decode is squashing -system.cpu0.decode.DecodedInsts 469212 # Number of instructions handled by decode -system.cpu0.rename.SquashCycles 1337 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 16355 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 2021 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 14599 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 151852 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 1263 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 465757 # Number of instructions processed by rename +system.cpu0.fetch.rateDist::total 187121 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.385134 # Number of branch fetches per cycle +system.cpu0.fetch.rate 2.275235 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 15778 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 17868 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 151448 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 678 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1349 # Number of cycles decode is squashing +system.cpu0.decode.DecodedInsts 468198 # Number of instructions handled by decode +system.cpu0.rename.SquashCycles 1349 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 16395 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 2033 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 14616 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 151464 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 1264 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 464735 # Number of instructions processed by rename system.cpu0.rename.IQFullEvents 17 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 16 # Number of times rename has blocked due to LQ full +system.cpu0.rename.LQFullEvents 19 # Number of times rename has blocked due to LQ full system.cpu0.rename.SQFullEvents 756 # Number of times rename has blocked due to SQ full -system.cpu0.rename.RenamedOperands 319012 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 928821 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 701999 # Number of integer rename lookups -system.cpu0.rename.CommittedMaps 305055 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 13957 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 896 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 905 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 4572 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 148578 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 75186 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 72446 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 72197 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 389771 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 964 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 386457 # Number of instructions issued +system.cpu0.rename.RenamedOperands 318331 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 926755 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 700443 # Number of integer rename lookups +system.cpu0.rename.CommittedMaps 304259 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 14072 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 900 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 909 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 4585 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 148203 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 75025 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 72247 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 71998 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 388891 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 968 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 385538 # Number of instructions issued system.cpu0.iq.iqSquashedInstsIssued 23 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 12213 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 11103 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 405 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 187427 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 2.061907 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.125198 # Number of insts issued each cycle +system.cpu0.iq.iqSquashedInstsExamined 12303 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 11219 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 409 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 187121 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 2.060367 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.127018 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 33106 17.66% 17.66% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 4299 2.29% 19.96% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 73629 39.28% 59.24% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 73187 39.05% 98.29% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 1656 0.88% 99.17% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 900 0.48% 99.65% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 407 0.22% 99.87% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 171 0.09% 99.96% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 72 0.04% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 33176 17.73% 17.73% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 4313 2.30% 20.03% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 73426 39.24% 59.27% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 72986 39.00% 98.28% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 1673 0.89% 99.17% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 893 0.48% 99.65% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 397 0.21% 99.86% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 180 0.10% 99.96% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 77 0.04% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 187427 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 187121 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 96 33.92% 33.92% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 0 0.00% 33.92% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 33.92% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 33.92% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 33.92% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 33.92% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 33.92% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 33.92% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 33.92% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 33.92% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 33.92% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 33.92% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 33.92% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 33.92% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 33.92% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 33.92% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 33.92% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 33.92% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 33.92% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 33.92% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 33.92% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 33.92% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 33.92% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 33.92% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 33.92% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 33.92% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 33.92% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.92% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 33.92% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 84 29.68% 63.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 103 36.40% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 102 35.29% 35.29% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 0 0.00% 35.29% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 35.29% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 35.29% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 35.29% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 35.29% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 35.29% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 35.29% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 35.29% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 35.29% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 35.29% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 35.29% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 35.29% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 35.29% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 35.29% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 35.29% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 35.29% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 35.29% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 35.29% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 35.29% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 35.29% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 35.29% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 35.29% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 35.29% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 35.29% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 35.29% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 35.29% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 35.29% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 35.29% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 84 29.07% 64.36% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 103 35.64% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 163898 42.41% 42.41% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.41% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.41% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.41% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.41% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.41% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.41% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.41% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.41% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 42.41% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 42.41% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 42.41% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 42.41% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 42.41% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 42.41% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 42.41% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 42.41% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 42.41% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 42.41% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 42.41% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.41% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.41% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.41% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.41% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.41% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.41% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.41% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.41% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.41% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 148040 38.31% 80.72% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 74519 19.28% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 163537 42.42% 42.42% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.42% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.42% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.42% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.42% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.42% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.42% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.42% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.42% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 42.42% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 42.42% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 42.42% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 42.42% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 42.42% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 42.42% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 42.42% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 42.42% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 42.42% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 42.42% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 42.42% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.42% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.42% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.42% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.42% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.42% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.42% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.42% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.42% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.42% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 147667 38.30% 80.72% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 74334 19.28% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 386457 # Type of FU issued -system.cpu0.iq.rate 1.828145 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 283 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.000732 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 960647 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 403001 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 384607 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.FU_type_0::total 385538 # Type of FU issued +system.cpu0.iq.rate 1.826459 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 289 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.000750 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 958509 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 402215 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 383670 # Number of integer instruction queue wakeup accesses system.cpu0.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu0.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu0.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 386740 # Number of integer alu accesses +system.cpu0.iq.int_alu_accesses 385827 # Number of integer alu accesses system.cpu0.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 71819 # Number of loads that had data forwarded from stores +system.cpu0.iew.lsq.thread0.forwLoads 71619 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 2461 # Number of loads squashed +system.cpu0.iew.lsq.thread0.squashedLoads 2484 # Number of loads squashed system.cpu0.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed system.cpu0.iew.lsq.thread0.memOrderViolation 54 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 1621 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedStores 1659 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu0.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu0.iew.lsq.thread0.cacheBlocked 12 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1337 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 1980 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 50 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 463607 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 160 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 148578 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 75186 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 843 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 45 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewSquashCycles 1349 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 1995 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 47 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 462536 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 162 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 148203 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 75025 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 847 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 42 # Number of times the IQ has become full, causing a stall system.cpu0.iew.iewLSQFullEvents 10 # Number of times the LSQ has become full, causing a stall system.cpu0.iew.memOrderViolationEvents 54 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 323 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 1099 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 1422 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 385445 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 147736 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 1012 # Number of squashed instructions skipped in execute +system.cpu0.iew.predictedTakenIncorrect 324 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 1113 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 1437 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 384525 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 147369 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 1013 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 72872 # number of nop insts executed -system.cpu0.iew.exec_refs 222117 # number of memory reference insts executed -system.cpu0.iew.exec_branches 76458 # Number of branches executed -system.cpu0.iew.exec_stores 74381 # Number of stores executed -system.cpu0.iew.exec_rate 1.823357 # Inst execution rate -system.cpu0.iew.wb_sent 384977 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 384607 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 228096 # num instructions producing a value -system.cpu0.iew.wb_consumers 231328 # num instructions consuming a value +system.cpu0.iew.exec_nop 72677 # number of nop insts executed +system.cpu0.iew.exec_refs 221564 # number of memory reference insts executed +system.cpu0.iew.exec_branches 76264 # Number of branches executed +system.cpu0.iew.exec_stores 74195 # Number of stores executed +system.cpu0.iew.exec_rate 1.821660 # Inst execution rate +system.cpu0.iew.wb_sent 384046 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 383670 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 227520 # num instructions producing a value +system.cpu0.iew.wb_consumers 230755 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 1.819393 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.986028 # average fanout of values written-back +system.cpu0.iew.wb_rate 1.817609 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.985981 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 13622 # The number of squashed insts skipped by commit +system.cpu0.commit.commitSquashedInsts 13745 # The number of squashed insts skipped by commit system.cpu0.commit.commitNonSpecStalls 559 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 1187 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 184803 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 2.434668 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 2.147538 # Number of insts commited each cycle +system.cpu0.commit.branchMispredicts 1199 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 184477 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 2.432498 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 2.147629 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 33298 18.02% 18.02% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 75556 40.88% 58.90% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 2014 1.09% 59.99% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 640 0.35% 60.34% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 527 0.29% 60.62% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 71511 38.70% 99.32% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 33360 18.08% 18.08% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 75359 40.85% 58.93% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 2024 1.10% 60.03% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 644 0.35% 60.38% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 522 0.28% 60.66% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 71315 38.66% 99.32% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::6 520 0.28% 99.60% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 249 0.13% 99.74% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 488 0.26% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 246 0.13% 99.74% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 487 0.26% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 184803 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 449934 # Number of instructions committed -system.cpu0.commit.committedOps 449934 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 184477 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 448740 # Number of instructions committed +system.cpu0.commit.committedOps 448740 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 219682 # Number of memory references committed -system.cpu0.commit.loads 146117 # Number of loads committed +system.cpu0.commit.refs 219085 # Number of memory references committed +system.cpu0.commit.loads 145719 # Number of loads committed system.cpu0.commit.membars 84 # Number of memory barriers committed -system.cpu0.commit.branches 75452 # Number of branches committed +system.cpu0.commit.branches 75253 # Number of branches committed system.cpu0.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 303386 # Number of committed integer instructions. +system.cpu0.commit.int_insts 302590 # Number of committed integer instructions. system.cpu0.commit.function_calls 223 # Number of function calls committed. -system.cpu0.commit.op_class_0::No_OpClass 72184 16.04% 16.04% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 157984 35.11% 51.16% # Class of committed instruction +system.cpu0.commit.op_class_0::No_OpClass 71985 16.04% 16.04% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 157586 35.12% 51.16% # Class of committed instruction system.cpu0.commit.op_class_0::IntMult 0 0.00% 51.16% # Class of committed instruction system.cpu0.commit.op_class_0::IntDiv 0 0.00% 51.16% # Class of committed instruction system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 51.16% # Class of committed instruction @@ -1050,195 +557,104 @@ system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 51.16% system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 51.16% # Class of committed instruction system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 51.16% # Class of committed instruction system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 51.16% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 146201 32.49% 83.65% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 73565 16.35% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 145803 32.49% 83.65% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 73366 16.35% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 449934 # Class of committed instruction -system.cpu0.commit.bw_lim_events 488 # number cycles where commit BW limit reached +system.cpu0.commit.op_class_0::total 448740 # Class of committed instruction +system.cpu0.commit.bw_lim_events 487 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 646710 # The number of ROB reads -system.cpu0.rob.rob_writes 929757 # The number of ROB writes +system.cpu0.rob.rob_reads 645314 # The number of ROB reads +system.cpu0.rob.rob_writes 927635 # The number of ROB writes system.cpu0.timesIdled 318 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 23966 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.committedInsts 377666 # Number of Instructions Simulated -system.cpu0.committedOps 377666 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 0.559735 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 0.559735 # CPI: Total CPI of All Threads -system.cpu0.ipc 1.786559 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 1.786559 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 689346 # number of integer regfile reads -system.cpu0.int_regfile_writes 310987 # number of integer regfile writes +system.cpu0.idleCycles 23964 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.committedInsts 376671 # Number of Instructions Simulated +system.cpu0.committedOps 376671 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 0.560396 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 0.560396 # CPI: Total CPI of All Threads +system.cpu0.ipc 1.784452 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 1.784452 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 687652 # number of integer regfile reads +system.cpu0.int_regfile_writes 310240 # number of integer regfile writes system.cpu0.fp_regfile_reads 192 # number of floating regfile reads -system.cpu0.misc_regfile_reads 224004 # number of misc regfile reads +system.cpu0.misc_regfile_reads 223454 # number of misc regfile reads system.cpu0.misc_regfile_writes 564 # number of misc regfile writes -system.cpu0.icache.tags.replacements 322 # number of replacements -system.cpu0.icache.tags.tagsinuse 240.567538 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 6326 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 612 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 10.336601 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 240.567538 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.469858 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.469858 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_task_id_blocks::1024 290 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 188 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 44 # Occupied blocks per task id -system.cpu0.icache.tags.occ_task_id_percent::1024 0.566406 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 7735 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 7735 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 6326 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 6326 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 6326 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 6326 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 6326 # number of overall hits -system.cpu0.icache.overall_hits::total 6326 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 797 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 797 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 797 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 797 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 797 # number of overall misses -system.cpu0.icache.overall_misses::total 797 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 36689746 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 36689746 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 36689746 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 36689746 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 36689746 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 36689746 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 7123 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 7123 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 7123 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 7123 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 7123 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 7123 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.111891 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.111891 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.111891 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.111891 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.111891 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.111891 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 46034.813049 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 46034.813049 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 46034.813049 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 46034.813049 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 46034.813049 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 46034.813049 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 22 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 1 # number of cycles access was blocked -system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 22 # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.fast_writes 0 # number of fast writes performed -system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 184 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 184 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 184 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 184 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 184 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 184 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 613 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 613 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 613 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 613 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 613 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 613 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 28185001 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 28185001 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 28185001 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 28185001 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 28185001 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 28185001 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.086059 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.086059 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.086059 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.086059 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.086059 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.086059 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 45978.794454 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 45978.794454 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 45978.794454 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 45978.794454 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 45978.794454 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 45978.794454 # average overall mshr miss latency -system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.dcache.tags.replacements 2 # number of replacements -system.cpu0.dcache.tags.tagsinuse 141.516453 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 148253 # Total number of references to valid blocks. +system.cpu0.dcache.tags.tagsinuse 141.523626 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 147885 # Total number of references to valid blocks. system.cpu0.dcache.tags.sampled_refs 170 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 872.076471 # Average number of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 869.911765 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 141.516453 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.276399 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.276399 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 141.523626 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.276413 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.276413 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 168 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::0 17 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 104 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 47 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 105 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 46 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 0.328125 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 597940 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 597940 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 75362 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 75362 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 72979 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 72979 # number of WriteReq hits +system.cpu0.dcache.tags.tag_accesses 596477 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 596477 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 75193 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 75193 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 72780 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 72780 # number of WriteReq hits system.cpu0.dcache.SwapReq_hits::cpu0.data 20 # number of SwapReq hits system.cpu0.dcache.SwapReq_hits::total 20 # number of SwapReq hits -system.cpu0.dcache.demand_hits::cpu0.data 148341 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 148341 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 148341 # number of overall hits -system.cpu0.dcache.overall_hits::total 148341 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 480 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 480 # number of ReadReq misses +system.cpu0.dcache.demand_hits::cpu0.data 147973 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 147973 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 147973 # number of overall hits +system.cpu0.dcache.overall_hits::total 147973 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 482 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 482 # number of ReadReq misses system.cpu0.dcache.WriteReq_misses::cpu0.data 544 # number of WriteReq misses system.cpu0.dcache.WriteReq_misses::total 544 # number of WriteReq misses system.cpu0.dcache.SwapReq_misses::cpu0.data 22 # number of SwapReq misses system.cpu0.dcache.SwapReq_misses::total 22 # number of SwapReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1024 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1024 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1024 # number of overall misses -system.cpu0.dcache.overall_misses::total 1024 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 15203420 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 15203420 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 32866263 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 32866263 # number of WriteReq miss cycles -system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 427750 # number of SwapReq miss cycles -system.cpu0.dcache.SwapReq_miss_latency::total 427750 # number of SwapReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 48069683 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 48069683 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 48069683 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 48069683 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 75842 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 75842 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 73523 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 73523 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.demand_misses::cpu0.data 1026 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1026 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1026 # number of overall misses +system.cpu0.dcache.overall_misses::total 1026 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 15529368 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 15529368 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 32868763 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 32868763 # number of WriteReq miss cycles +system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 428750 # number of SwapReq miss cycles +system.cpu0.dcache.SwapReq_miss_latency::total 428750 # number of SwapReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 48398131 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 48398131 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 48398131 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 48398131 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 75675 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 75675 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 73324 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 73324 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses) system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 149365 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 149365 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 149365 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 149365 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.006329 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.006329 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007399 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.007399 # miss rate for WriteReq accesses +system.cpu0.dcache.demand_accesses::cpu0.data 148999 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 148999 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 148999 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 148999 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.006369 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.006369 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007419 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.007419 # miss rate for WriteReq accesses system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.523810 # miss rate for SwapReq accesses system.cpu0.dcache.SwapReq_miss_rate::total 0.523810 # miss rate for SwapReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.006856 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.006856 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.006856 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.006856 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 31673.791667 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 31673.791667 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 60415.924632 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 60415.924632 # average WriteReq miss latency -system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 19443.181818 # average SwapReq miss latency -system.cpu0.dcache.SwapReq_avg_miss_latency::total 19443.181818 # average SwapReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 46943.049805 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 46943.049805 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 46943.049805 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 46943.049805 # average overall miss latency +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.006886 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.006886 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.006886 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.006886 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 32218.605809 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 32218.605809 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 60420.520221 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 60420.520221 # average WriteReq miss latency +system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 19488.636364 # average SwapReq miss latency +system.cpu0.dcache.SwapReq_avg_miss_latency::total 19488.636364 # average SwapReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 47171.667641 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 47171.667641 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 47171.667641 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 47171.667641 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 754 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 27 # number of cycles access was blocked @@ -1249,518 +665,519 @@ system.cpu0.dcache.fast_writes 0 # nu system.cpu0.dcache.cache_copies 0 # number of cache copies performed system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks system.cpu0.dcache.writebacks::total 1 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 298 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 298 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 299 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 299 # number of ReadReq MSHR hits system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 365 # number of WriteReq MSHR hits system.cpu0.dcache.WriteReq_mshr_hits::total 365 # number of WriteReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 663 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 663 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 663 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 663 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 182 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 182 # number of ReadReq MSHR misses +system.cpu0.dcache.demand_mshr_hits::cpu0.data 664 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 664 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 664 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 664 # number of overall MSHR hits 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-system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6258507 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7387727 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7387727 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 382250 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.SwapReq_mshr_miss_latency::total 382250 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 13646234 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 13646234 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 13646234 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 13646234 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002400 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002400 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002435 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002435 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 362 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 362 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 362 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 362 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 6541511 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6541511 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7390227 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7390227 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 383250 # number of SwapReq MSHR miss cycles +system.cpu0.dcache.SwapReq_mshr_miss_latency::total 383250 # number of SwapReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 13931738 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 13931738 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 13931738 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 13931738 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002418 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002418 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002441 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002441 # mshr miss rate for WriteReq accesses system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.523810 # mshr miss rate for SwapReq accesses system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.523810 # mshr miss rate for SwapReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002417 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.002417 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002417 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.002417 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 34387.401099 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 34387.401099 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 41272.217877 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 41272.217877 # average WriteReq mshr miss latency -system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 17375 # average SwapReq mshr miss latency -system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 17375 # average SwapReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 37801.202216 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 37801.202216 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 37801.202216 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 37801.202216 # average overall mshr miss latency +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002430 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.002430 # mshr miss rate for demand accesses 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+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 38485.464088 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 38485.464088 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 38485.464088 # average overall mshr miss latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 52620 # Number of BP lookups -system.cpu1.branchPred.condPredicted 49209 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 1295 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 45306 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 44357 # Number of BTB hits +system.cpu0.icache.tags.replacements 319 # number of replacements +system.cpu0.icache.tags.tagsinuse 239.733862 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 6347 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 608 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 10.439145 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 239.733862 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.468230 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.468230 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_task_id_blocks::1024 289 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 187 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 44 # Occupied blocks per task id +system.cpu0.icache.tags.occ_task_id_percent::1024 0.564453 # Percentage of cache occupancy per task id +system.cpu0.icache.tags.tag_accesses 7747 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 7747 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 6347 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 6347 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 6347 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 6347 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 6347 # number of overall hits +system.cpu0.icache.overall_hits::total 6347 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 792 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 792 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 792 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 792 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 792 # number of overall misses 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accesses +system.cpu0.icache.overall_accesses::cpu0.inst 7139 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 7139 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.110940 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.110940 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.110940 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.110940 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.110940 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.110940 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 46001.257576 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 46001.257576 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 46001.257576 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 46001.257576 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 46001.257576 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 46001.257576 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu0.icache.fast_writes 0 # number of fast writes performed +system.cpu0.icache.cache_copies 0 # number of cache copies performed +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 183 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 183 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 183 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 183 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 183 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 183 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 609 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 609 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 609 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 609 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 609 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 609 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 27995751 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 27995751 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 27995751 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 27995751 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 27995751 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 27995751 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.085306 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.085306 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.085306 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.085306 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.085306 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.085306 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 45970.034483 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 45970.034483 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 45970.034483 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 45970.034483 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 45970.034483 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 45970.034483 # average overall mshr miss latency +system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.branchPred.lookups 48230 # Number of BP lookups +system.cpu1.branchPred.condPredicted 44811 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 1266 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 41091 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 39963 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 97.905355 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 875 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.BTBHitPct 97.254873 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 868 # Number of times the RAS was used to get a target. system.cpu1.branchPred.RASInCorrect 231 # Number of incorrect RAS predictions. -system.cpu1.numCycles 161023 # number of cpu cycles simulated +system.cpu1.numCycles 160735 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 31247 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 289875 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 52620 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 45232 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 125550 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 2747 # Number of cycles fetch has spent squashing +system.cpu1.fetch.icacheStallCycles 33641 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 261327 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 48230 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 40831 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 122936 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 2691 # Number of cycles fetch has spent squashing system.cpu1.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu1.fetch.NoActiveThreadStallCycles 10 # Number of stall cycles due to no active thread to fetch from -system.cpu1.fetch.PendingTrapStallCycles 1122 # Number of stall cycles due to pending traps -system.cpu1.fetch.CacheLines 22380 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 446 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 159305 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 1.819623 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.179377 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.PendingTrapStallCycles 1065 # Number of stall cycles due to pending traps +system.cpu1.fetch.CacheLines 24854 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 432 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 159000 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 1.643566 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.124362 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 56744 35.62% 35.62% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 52063 32.68% 68.30% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 6924 4.35% 72.65% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 3540 2.22% 74.87% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 1103 0.69% 75.56% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 33079 20.76% 96.33% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 1261 0.79% 97.12% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 757 0.48% 97.59% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 3834 2.41% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 63867 40.17% 40.17% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 48973 30.80% 70.97% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 8266 5.20% 76.17% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 3472 2.18% 78.35% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 1057 0.66% 79.02% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 27547 17.33% 96.34% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 1174 0.74% 97.08% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 753 0.47% 97.55% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 3891 2.45% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 159305 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.326786 # Number of branch fetches per cycle -system.cpu1.fetch.rate 1.800209 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 17668 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 57241 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 79500 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 3513 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 1373 # Number of cycles decode is squashing -system.cpu1.decode.DecodedInsts 275603 # Number of instructions handled by decode -system.cpu1.rename.SquashCycles 1373 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 18384 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 26779 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 12577 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 80781 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 19401 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 272270 # Number of instructions processed by rename -system.cpu1.rename.IQFullEvents 17163 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 27 # Number of times rename has blocked due to LQ full +system.cpu1.fetch.rateDist::total 159000 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.300059 # Number of branch fetches per cycle +system.cpu1.fetch.rate 1.625825 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 17613 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 67674 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 68228 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 4130 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 1345 # Number of cycles decode is squashing +system.cpu1.decode.DecodedInsts 247069 # Number of instructions handled by decode +system.cpu1.rename.SquashCycles 1345 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 18292 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 33178 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 12317 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 69139 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 24719 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 243777 # Number of instructions processed by rename +system.cpu1.rename.IQFullEvents 21468 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 22 # Number of times rename has blocked due to LQ full system.cpu1.rename.FullRegisterEvents 3 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 191050 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 520032 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 405162 # Number of integer rename lookups -system.cpu1.rename.CommittedMaps 176680 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 14370 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 1196 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 1257 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 24088 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 76067 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 35939 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 36374 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 30769 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 225624 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 6666 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 227547 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 18 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 12526 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 11238 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 649 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 159305 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 1.428373 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.374842 # Number of insts issued each cycle +system.cpu1.rename.RenamedOperands 169834 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 458131 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 358650 # Number of integer rename lookups +system.cpu1.rename.CommittedMaps 155489 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 14345 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 1180 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 1243 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 29340 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 66237 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 30368 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 32190 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 25244 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 200152 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 7929 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 203048 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 39 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 12672 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 11906 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 679 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 159000 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 1.277031 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.370207 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 60375 37.90% 37.90% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 22487 14.12% 52.01% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 35297 22.16% 74.17% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 34879 21.89% 96.07% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 3406 2.14% 98.20% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1579 0.99% 99.20% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 861 0.54% 99.74% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 224 0.14% 99.88% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 197 0.12% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 67764 42.62% 42.62% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 26124 16.43% 59.05% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 29595 18.61% 77.66% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 29204 18.37% 96.03% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 3405 2.14% 98.17% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1592 1.00% 99.17% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 880 0.55% 99.73% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 226 0.14% 99.87% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 210 0.13% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 159305 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 159000 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 89 26.49% 26.49% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 26.49% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 26.49% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 26.49% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 26.49% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 26.49% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 26.49% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 26.49% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 26.49% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 26.49% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 26.49% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 26.49% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 26.49% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 26.49% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 26.49% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 26.49% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 26.49% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 26.49% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 26.49% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 26.49% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 26.49% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 26.49% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 26.49% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 26.49% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 26.49% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 26.49% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 26.49% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 26.49% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 26.49% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 38 11.31% 37.80% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 209 62.20% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 87 24.30% 24.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 24.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 24.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 24.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 24.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 24.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 24.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 24.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 24.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 24.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 24.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 24.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 24.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 24.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 24.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 24.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 24.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 24.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 24.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 24.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 24.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 24.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 24.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 24.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 24.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 24.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 24.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 24.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 24.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 62 17.32% 41.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 209 58.38% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 111688 49.08% 49.08% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 0 0.00% 49.08% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 49.08% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 49.08% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 49.08% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 49.08% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 49.08% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 49.08% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 49.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 49.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 49.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 49.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 49.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 49.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 49.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 49.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 49.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 49.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 49.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 49.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.08% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 80614 35.43% 84.51% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 35245 15.49% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 101499 49.99% 49.99% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 0 0.00% 49.99% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 49.99% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 49.99% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 49.99% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 49.99% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 49.99% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 49.99% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 49.99% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 49.99% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 49.99% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 49.99% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 49.99% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 49.99% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 49.99% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 49.99% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 49.99% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 49.99% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.99% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 49.99% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.99% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.99% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.99% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.99% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.99% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.99% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 49.99% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.99% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.99% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 71903 35.41% 85.40% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 29646 14.60% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 227547 # Type of FU issued -system.cpu1.iq.rate 1.413134 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 336 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.001477 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 614753 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 244854 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 225845 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.FU_type_0::total 203048 # Type of FU issued +system.cpu1.iq.rate 1.263247 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 358 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.001763 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 565493 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 220798 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 201375 # Number of integer instruction queue wakeup accesses system.cpu1.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu1.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu1.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 227883 # Number of integer alu accesses +system.cpu1.iq.int_alu_accesses 203406 # Number of integer alu accesses system.cpu1.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 30551 # Number of loads that had data forwarded from stores +system.cpu1.iew.lsq.thread0.forwLoads 24951 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 2638 # Number of loads squashed +system.cpu1.iew.lsq.thread0.squashedLoads 2787 # Number of loads squashed system.cpu1.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 38 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 1613 # Number of stores squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 45 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 1647 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu1.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu1.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 1373 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 7085 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 49 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 269526 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 186 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 76067 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 35939 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 1117 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 28 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewSquashCycles 1345 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 8539 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 65 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 241028 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 239 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 66237 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 30368 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 1097 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 39 # Number of times the IQ has become full, causing a stall system.cpu1.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 38 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 476 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 1037 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 1513 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 226408 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 75003 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 1139 # Number of squashed instructions skipped in execute +system.cpu1.iew.memOrderViolationEvents 45 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 465 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 1009 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 1474 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 201951 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 65061 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 1097 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 37236 # number of nop insts executed -system.cpu1.iew.exec_refs 110148 # number of memory reference insts executed -system.cpu1.iew.exec_branches 46633 # Number of branches executed -system.cpu1.iew.exec_stores 35145 # Number of stores executed -system.cpu1.iew.exec_rate 1.406060 # Inst execution rate -system.cpu1.iew.wb_sent 226126 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 225845 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 127804 # num instructions producing a value -system.cpu1.iew.wb_consumers 134338 # num instructions consuming a value +system.cpu1.iew.exec_nop 32947 # number of nop insts executed +system.cpu1.iew.exec_refs 94595 # number of memory reference insts executed +system.cpu1.iew.exec_branches 42219 # Number of branches executed +system.cpu1.iew.exec_stores 29534 # Number of stores executed +system.cpu1.iew.exec_rate 1.256422 # Inst execution rate +system.cpu1.iew.wb_sent 201670 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 201375 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 112178 # num instructions producing a value +system.cpu1.iew.wb_consumers 118722 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 1.402564 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.951361 # average fanout of values written-back +system.cpu1.iew.wb_rate 1.252839 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.944880 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 14108 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 6017 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 1295 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 156709 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 1.629549 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 2.048246 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 14315 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 7250 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 1266 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 156398 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 1.449251 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.979774 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 66028 42.13% 42.13% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 43411 27.70% 69.84% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 5268 3.36% 73.20% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 6809 4.34% 77.54% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1543 0.98% 78.53% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 30606 19.53% 98.06% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 798 0.51% 98.57% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 967 0.62% 99.18% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1279 0.82% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 74586 47.69% 47.69% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 38945 24.90% 72.59% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 5214 3.33% 75.92% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 8053 5.15% 81.07% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1537 0.98% 82.06% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 24957 15.96% 98.01% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 851 0.54% 98.56% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 951 0.61% 99.17% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1304 0.83% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 156709 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 255365 # Number of instructions committed -system.cpu1.commit.committedOps 255365 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 156398 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 226660 # Number of instructions committed +system.cpu1.commit.committedOps 226660 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 107755 # Number of memory references committed -system.cpu1.commit.loads 73429 # Number of loads committed -system.cpu1.commit.membars 5300 # Number of memory barriers committed -system.cpu1.commit.branches 45589 # Number of branches committed +system.cpu1.commit.refs 92171 # Number of memory references committed +system.cpu1.commit.loads 63450 # Number of loads committed +system.cpu1.commit.membars 6533 # Number of memory barriers committed +system.cpu1.commit.branches 41215 # Number of branches committed system.cpu1.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 175463 # Number of committed integer instructions. +system.cpu1.commit.int_insts 155506 # Number of committed integer instructions. system.cpu1.commit.function_calls 322 # Number of function calls committed. -system.cpu1.commit.op_class_0::No_OpClass 36376 14.24% 14.24% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 105934 41.48% 55.73% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 0 0.00% 55.73% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 0 0.00% 55.73% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 55.73% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 55.73% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 55.73% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 55.73% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 55.73% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 55.73% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 55.73% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 55.73% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 55.73% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 55.73% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 55.73% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 55.73% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 55.73% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 55.73% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 55.73% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 55.73% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 55.73% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 55.73% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 55.73% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 55.73% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 55.73% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 55.73% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 55.73% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 55.73% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 55.73% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 55.73% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 78729 30.83% 86.56% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 34326 13.44% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::No_OpClass 32002 14.12% 14.12% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 95954 42.33% 56.45% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 0 0.00% 56.45% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 0 0.00% 56.45% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 56.45% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 56.45% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 56.45% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 56.45% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 56.45% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 56.45% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 56.45% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 56.45% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 56.45% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 56.45% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 56.45% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 56.45% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 56.45% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 56.45% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 56.45% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 56.45% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 56.45% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 56.45% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 56.45% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 56.45% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 56.45% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 56.45% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 56.45% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 56.45% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 56.45% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 56.45% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 69983 30.88% 87.33% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 28721 12.67% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 255365 # Class of committed instruction -system.cpu1.commit.bw_lim_events 1279 # number cycles where commit BW limit reached +system.cpu1.commit.op_class_0::total 226660 # Class of committed instruction +system.cpu1.commit.bw_lim_events 1304 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 424317 # The number of ROB reads -system.cpu1.rob.rob_writes 541540 # The number of ROB writes -system.cpu1.timesIdled 208 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 1718 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 43314 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 213689 # Number of Instructions Simulated -system.cpu1.committedOps 213689 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 0.753539 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 0.753539 # CPI: Total CPI of All Threads -system.cpu1.ipc 1.327071 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 1.327071 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 390200 # number of integer regfile reads -system.cpu1.int_regfile_writes 182656 # number of integer regfile writes +system.cpu1.rob.rob_reads 395483 # The number of ROB reads +system.cpu1.rob.rob_writes 484550 # The number of ROB writes +system.cpu1.timesIdled 209 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 1735 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 43282 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 188125 # Number of Instructions Simulated +system.cpu1.committedOps 188125 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 0.854405 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 0.854405 # CPI: Total CPI of All Threads +system.cpu1.ipc 1.170405 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 1.170405 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 343348 # number of integer regfile reads +system.cpu1.int_regfile_writes 161358 # number of integer regfile writes system.cpu1.fp_regfile_writes 64 # number of floating regfile writes -system.cpu1.misc_regfile_reads 111763 # number of misc regfile reads +system.cpu1.misc_regfile_reads 96189 # number of misc regfile reads system.cpu1.misc_regfile_writes 648 # number of misc regfile writes -system.cpu1.icache.tags.replacements 388 # number of replacements -system.cpu1.icache.tags.tagsinuse 78.707719 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 21821 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 497 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 43.905433 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 78.707719 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.153726 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.153726 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_task_id_blocks::1024 109 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 98 # Occupied blocks per task id -system.cpu1.icache.tags.occ_task_id_percent::1024 0.212891 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 22877 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 22877 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 21821 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 21821 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 21821 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 21821 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 21821 # number of overall hits -system.cpu1.icache.overall_hits::total 21821 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 559 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 559 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 559 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 559 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 559 # number of overall misses -system.cpu1.icache.overall_misses::total 559 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8425746 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 8425746 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 8425746 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 8425746 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 8425746 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 8425746 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 22380 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 22380 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 22380 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 22380 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 22380 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 22380 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024978 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.024978 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024978 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.024978 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024978 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.024978 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15072.890877 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 15072.890877 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15072.890877 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 15072.890877 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15072.890877 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 15072.890877 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 2 # number of cycles access was blocked -system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 1 # number of cycles access was blocked -system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 2 # average number of cycles each access was blocked -system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.icache.fast_writes 0 # number of fast writes performed -system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 62 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 62 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 62 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 62 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 62 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 62 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 497 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 497 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 497 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 497 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 497 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 497 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 6648254 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 6648254 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 6648254 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 6648254 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 6648254 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 6648254 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.022207 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.022207 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.022207 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.022207 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.022207 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.022207 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13376.768612 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13376.768612 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13376.768612 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 13376.768612 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13376.768612 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 13376.768612 # average overall mshr miss latency -system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dcache.tags.replacements 0 # number of replacements -system.cpu1.dcache.tags.tagsinuse 24.402316 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 40362 # Total number of references to valid blocks. +system.cpu1.dcache.tags.tagsinuse 23.332143 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 34754 # Total number of references to valid blocks. system.cpu1.dcache.tags.sampled_refs 28 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 1441.500000 # Average number of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 1241.214286 # Average number of references to valid blocks. system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 24.402316 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.047661 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.047661 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_blocks::cpu1.data 23.332143 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.045571 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.045571 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_task_id_blocks::1024 28 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id system.cpu1.dcache.tags.occ_task_id_percent::1024 0.054688 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 315306 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 315306 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 43998 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 43998 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 34119 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 34119 # number of WriteReq hits -system.cpu1.dcache.SwapReq_hits::cpu1.data 13 # number of SwapReq hits -system.cpu1.dcache.SwapReq_hits::total 13 # number of SwapReq hits -system.cpu1.dcache.demand_hits::cpu1.data 78117 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 78117 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 78117 # number of overall hits -system.cpu1.dcache.overall_hits::total 78117 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 439 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 439 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 136 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 136 # number of WriteReq misses -system.cpu1.dcache.SwapReq_misses::cpu1.data 58 # number of SwapReq misses -system.cpu1.dcache.SwapReq_misses::total 58 # number of SwapReq misses -system.cpu1.dcache.demand_misses::cpu1.data 575 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 575 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 575 # number of overall misses -system.cpu1.dcache.overall_misses::total 575 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 5820038 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 5820038 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2819511 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 2819511 # number of WriteReq miss cycles -system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 502006 # number of SwapReq miss cycles -system.cpu1.dcache.SwapReq_miss_latency::total 502006 # number of SwapReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 8639549 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 8639549 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 8639549 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 8639549 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 44437 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 44437 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 34255 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 34255 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.tags.tag_accesses 275515 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 275515 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 39673 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 39673 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 28513 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 28513 # number of WriteReq hits +system.cpu1.dcache.SwapReq_hits::cpu1.data 14 # number of SwapReq hits +system.cpu1.dcache.SwapReq_hits::total 14 # number of SwapReq hits +system.cpu1.dcache.demand_hits::cpu1.data 68186 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 68186 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 68186 # number of overall hits +system.cpu1.dcache.overall_hits::total 68186 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 422 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 422 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 137 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 137 # number of WriteReq misses +system.cpu1.dcache.SwapReq_misses::cpu1.data 57 # number of SwapReq misses +system.cpu1.dcache.SwapReq_misses::total 57 # number of SwapReq misses +system.cpu1.dcache.demand_misses::cpu1.data 559 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 559 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 559 # number of overall misses +system.cpu1.dcache.overall_misses::total 559 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 5603617 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 5603617 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2812761 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 2812761 # number of WriteReq miss cycles +system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 492507 # number of SwapReq miss cycles +system.cpu1.dcache.SwapReq_miss_latency::total 492507 # number of SwapReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 8416378 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 8416378 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 8416378 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 8416378 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 40095 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 40095 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 28650 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 28650 # number of WriteReq accesses(hits+misses) system.cpu1.dcache.SwapReq_accesses::cpu1.data 71 # number of SwapReq accesses(hits+misses) system.cpu1.dcache.SwapReq_accesses::total 71 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 78692 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 78692 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 78692 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 78692 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.009879 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.009879 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.003970 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.003970 # miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.816901 # miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_miss_rate::total 0.816901 # miss rate for SwapReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.007307 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.007307 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.007307 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.007307 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13257.489749 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 13257.489749 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 20731.698529 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 20731.698529 # average WriteReq miss latency -system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 8655.275862 # average SwapReq miss latency -system.cpu1.dcache.SwapReq_avg_miss_latency::total 8655.275862 # average SwapReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15025.302609 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 15025.302609 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15025.302609 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 15025.302609 # average overall miss latency +system.cpu1.dcache.demand_accesses::cpu1.data 68745 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 68745 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 68745 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 68745 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.010525 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.010525 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.004782 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.004782 # miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.802817 # miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_miss_rate::total 0.802817 # miss rate for SwapReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.008132 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.008132 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.008132 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.008132 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13278.713270 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 13278.713270 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 20531.102190 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 20531.102190 # average WriteReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 8640.473684 # average SwapReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::total 8640.473684 # average SwapReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15056.132379 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 15056.132379 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15056.132379 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 15056.132379 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1769,520 +1186,519 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 276 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 276 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 32 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 32 # number of WriteReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 308 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 308 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 308 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 308 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 163 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 163 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 104 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 104 # number of WriteReq MSHR misses -system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 58 # number of SwapReq MSHR misses -system.cpu1.dcache.SwapReq_mshr_misses::total 58 # number of SwapReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 267 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 267 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 267 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 267 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1085520 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1085520 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1288239 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1288239 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 385994 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::total 385994 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2373759 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 2373759 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2373759 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 2373759 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003668 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003668 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.003036 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.003036 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.816901 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.816901 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.003393 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.003393 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.003393 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.003393 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 6659.631902 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 6659.631902 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 12386.913462 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 12386.913462 # average WriteReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 6655.068966 # average SwapReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 6655.068966 # average SwapReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 8890.483146 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 8890.483146 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 8890.483146 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 8890.483146 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 262 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 262 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 34 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 34 # number of WriteReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 296 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 296 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 296 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 296 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 160 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 160 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 103 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 103 # number of WriteReq MSHR misses +system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 57 # number of SwapReq MSHR misses +system.cpu1.dcache.SwapReq_mshr_misses::total 57 # number of SwapReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 263 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 263 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 263 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 263 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1125015 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1125015 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1272489 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1272489 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 378493 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::total 378493 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2397504 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 2397504 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2397504 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 2397504 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003991 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003991 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.003595 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.003595 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.802817 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.802817 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.003826 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.003826 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.003826 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.003826 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 7031.343750 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 7031.343750 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 12354.262136 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 12354.262136 # average WriteReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 6640.228070 # average SwapReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 6640.228070 # average SwapReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 9115.984791 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 9115.984791 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 9115.984791 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 9115.984791 # average overall mshr miss latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.branchPred.lookups 52660 # Number of BP lookups -system.cpu2.branchPred.condPredicted 48877 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 1286 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 45218 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 43881 # Number of BTB hits +system.cpu1.icache.tags.replacements 388 # number of replacements +system.cpu1.icache.tags.tagsinuse 76.215682 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 24292 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 498 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 48.779116 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 76.215682 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.148859 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.148859 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_task_id_blocks::1024 110 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 99 # Occupied blocks per task id +system.cpu1.icache.tags.occ_task_id_percent::1024 0.214844 # Percentage of cache occupancy per task id +system.cpu1.icache.tags.tag_accesses 25352 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 25352 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 24292 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 24292 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 24292 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 24292 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 24292 # number of overall hits +system.cpu1.icache.overall_hits::total 24292 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 562 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 562 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 562 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 562 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 562 # number of overall misses +system.cpu1.icache.overall_misses::total 562 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7960746 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 7960746 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 7960746 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 7960746 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 7960746 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 7960746 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 24854 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 24854 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 24854 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 24854 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 24854 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 24854 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.022612 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.022612 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.022612 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.022612 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.022612 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.022612 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14165.028470 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 14165.028470 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14165.028470 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 14165.028470 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14165.028470 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 14165.028470 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 2 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 1 # number of cycles access was blocked +system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 2 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu1.icache.fast_writes 0 # number of fast writes performed +system.cpu1.icache.cache_copies 0 # number of cache copies performed +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 64 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 64 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 64 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 64 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 64 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 64 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 498 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 498 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 498 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 498 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 498 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 498 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 6368004 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 6368004 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 6368004 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 6368004 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 6368004 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 6368004 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.020037 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.020037 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.020037 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.020037 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.020037 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.020037 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12787.156627 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12787.156627 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12787.156627 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 12787.156627 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12787.156627 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 12787.156627 # average overall mshr miss latency +system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu2.branchPred.lookups 55295 # Number of BP lookups +system.cpu2.branchPred.condPredicted 51520 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 1304 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 47890 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 46487 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 97.043213 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 913 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.BTBHitPct 97.070370 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 899 # Number of times the RAS was used to get a target. system.cpu2.branchPred.RASInCorrect 231 # Number of incorrect RAS predictions. -system.cpu2.numCycles 160663 # number of cpu cycles simulated +system.cpu2.numCycles 160375 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 30584 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 291962 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 52660 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 44794 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 122431 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 2729 # Number of cycles fetch has spent squashing +system.cpu2.fetch.icacheStallCycles 28879 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 309014 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 55295 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 47386 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 123906 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 2765 # Number of cycles fetch has spent squashing system.cpu2.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu2.fetch.NoActiveThreadStallCycles 10 # Number of stall cycles due to no active thread to fetch from -system.cpu2.fetch.PendingTrapStallCycles 1111 # Number of stall cycles due to pending traps +system.cpu2.fetch.PendingTrapStallCycles 1110 # Number of stall cycles due to pending traps system.cpu2.fetch.IcacheWaitRetryStallCycles 3 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 21169 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 445 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.rateDist::samples 155507 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.877485 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.219728 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.CacheLines 19451 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 461 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.rateDist::samples 155294 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.989864 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.243889 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 53998 34.72% 34.72% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 51209 32.93% 67.65% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 6210 3.99% 71.65% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 3413 2.19% 73.84% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 933 0.60% 74.44% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 33386 21.47% 95.91% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 1293 0.83% 96.74% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 846 0.54% 97.29% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 4219 2.71% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 49501 31.88% 31.88% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 52893 34.06% 65.94% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 5338 3.44% 69.37% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 3457 2.23% 71.60% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 949 0.61% 72.21% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 36899 23.76% 95.97% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 1216 0.78% 96.75% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 841 0.54% 97.30% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 4200 2.70% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 155507 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.327767 # Number of branch fetches per cycle -system.cpu2.fetch.rate 1.817232 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 17863 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 52592 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 80411 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 3267 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 1364 # Number of cycles decode is squashing -system.cpu2.decode.DecodedInsts 276853 # Number of instructions handled by decode -system.cpu2.rename.SquashCycles 1364 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 18564 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 24147 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 12636 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 81735 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 17051 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 273529 # Number of instructions processed by rename -system.cpu2.rename.IQFullEvents 15090 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LQFullEvents 25 # Number of times rename has blocked due to LQ full +system.cpu2.fetch.rateDist::total 155294 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.344786 # Number of branch fetches per cycle +system.cpu2.fetch.rate 1.926822 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 17746 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 46456 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 86830 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 2870 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 1382 # Number of cycles decode is squashing +system.cpu2.decode.DecodedInsts 293603 # Number of instructions handled by decode +system.cpu2.rename.SquashCycles 1382 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 18442 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 20397 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 12871 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 87967 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 14225 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 290431 # Number of instructions processed by rename +system.cpu2.rename.IQFullEvents 12472 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LQFullEvents 29 # Number of times rename has blocked due to LQ full system.cpu2.rename.FullRegisterEvents 6 # Number of times there has been no free registers -system.cpu2.rename.RenamedOperands 193256 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 525177 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 409210 # Number of integer rename lookups -system.cpu2.rename.CommittedMaps 178291 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 14965 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 1175 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 1247 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 21746 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 76624 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 36478 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 36325 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 31287 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 227715 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 6015 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 228842 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 34 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 13120 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 11533 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 647 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 155507 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 1.471586 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.386146 # Number of insts issued each cycle +system.cpu2.rename.RenamedOperands 205748 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 562377 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 437048 # Number of integer rename lookups +system.cpu2.rename.CommittedMaps 190737 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 15011 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 1169 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 1232 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 18731 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 82610 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 39860 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 38981 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 34721 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 242796 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 5190 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 242904 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 29 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 13134 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 12157 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 612 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 155294 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 1.564156 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.378675 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 57410 36.92% 36.92% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 20565 13.22% 50.14% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 35759 23.00% 73.14% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 35374 22.75% 95.89% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 3397 2.18% 98.07% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 1636 1.05% 99.12% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 896 0.58% 99.70% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 267 0.17% 99.87% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 203 0.13% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 52943 34.09% 34.09% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 18212 11.73% 45.82% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 39071 25.16% 70.98% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 38654 24.89% 95.87% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 3479 2.24% 98.11% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 1594 1.03% 99.14% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 891 0.57% 99.71% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 244 0.16% 99.87% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 206 0.13% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 155507 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 155294 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 89 26.57% 26.57% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 0 0.00% 26.57% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 26.57% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 26.57% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 26.57% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 26.57% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 26.57% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 26.57% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 26.57% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 26.57% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 26.57% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 26.57% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 26.57% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 26.57% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 26.57% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 26.57% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 26.57% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 26.57% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 26.57% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 26.57% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 26.57% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 26.57% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 26.57% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 26.57% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 26.57% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 26.57% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 26.57% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 26.57% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 26.57% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 37 11.04% 37.61% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 209 62.39% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 90 25.64% 25.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 0 0.00% 25.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 25.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 25.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 25.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 25.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 25.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 25.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 25.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 25.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 25.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 25.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 25.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 25.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 25.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 25.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 25.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 25.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 25.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 25.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 25.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 25.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 25.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 25.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 25.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 25.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 25.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 25.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 52 14.81% 40.46% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 209 59.54% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 112448 49.14% 49.14% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 0 0.00% 49.14% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 49.14% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 49.14% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 49.14% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 49.14% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 49.14% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 49.14% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 49.14% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 49.14% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 49.14% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 49.14% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 49.14% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 49.14% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 49.14% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 49.14% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 49.14% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 49.14% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.14% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 49.14% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.14% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.14% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.14% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.14% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.14% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.14% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 49.14% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.14% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.14% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 80571 35.21% 84.35% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 35823 15.65% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 118122 48.63% 48.63% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 0 0.00% 48.63% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 48.63% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 48.63% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 48.63% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 48.63% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 48.63% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 48.63% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 48.63% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 48.63% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 48.63% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 48.63% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 48.63% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 48.63% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 48.63% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 48.63% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 48.63% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 48.63% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.63% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 48.63% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.63% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.63% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.63% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.63% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.63% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.63% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 48.63% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.63% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.63% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 85639 35.26% 83.89% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 39143 16.11% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 228842 # Type of FU issued -system.cpu2.iq.rate 1.424360 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 335 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.001464 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 613560 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 246890 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 227101 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.FU_type_0::total 242904 # Type of FU issued +system.cpu2.iq.rate 1.514600 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 351 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.001445 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 641482 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 261162 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 241189 # Number of integer instruction queue wakeup accesses system.cpu2.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu2.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu2.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 229177 # Number of integer alu accesses +system.cpu2.iq.int_alu_accesses 243255 # Number of integer alu accesses system.cpu2.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 31107 # Number of loads that had data forwarded from stores +system.cpu2.iew.lsq.thread0.forwLoads 34438 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 2702 # Number of loads squashed +system.cpu2.iew.lsq.thread0.squashedLoads 2866 # Number of loads squashed system.cpu2.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 40 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 1596 # Number of stores squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 42 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 1666 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu2.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu2.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 1364 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 6807 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 58 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 270837 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 190 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 76624 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 36478 # Number of dispatched store instructions +system.cpu2.iew.iewSquashCycles 1382 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 6074 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 55 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 287692 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 198 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 82610 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 39860 # Number of dispatched store instructions system.cpu2.iew.iewDispNonSpecInsts 1098 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 36 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewIQFullEvents 33 # Number of times the IQ has become full, causing a stall system.cpu2.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 40 # Number of memory order violations +system.cpu2.iew.memOrderViolationEvents 42 # Number of memory order violations system.cpu2.iew.predictedTakenIncorrect 470 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 1049 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 1519 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 227700 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 75599 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 1142 # Number of squashed instructions skipped in execute +system.cpu2.iew.predictedNotTakenIncorrect 1074 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 1544 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 241779 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 81452 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 1125 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 37107 # number of nop insts executed -system.cpu2.iew.exec_refs 111310 # number of memory reference insts executed -system.cpu2.iew.exec_branches 46563 # Number of branches executed -system.cpu2.iew.exec_stores 35711 # Number of stores executed -system.cpu2.iew.exec_rate 1.417252 # Inst execution rate -system.cpu2.iew.wb_sent 227402 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 227101 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 129036 # num instructions producing a value -system.cpu2.iew.wb_consumers 135804 # num instructions consuming a value +system.cpu2.iew.exec_nop 39706 # number of nop insts executed +system.cpu2.iew.exec_refs 120488 # number of memory reference insts executed +system.cpu2.iew.exec_branches 49059 # Number of branches executed +system.cpu2.iew.exec_stores 39036 # Number of stores executed +system.cpu2.iew.exec_rate 1.507585 # Inst execution rate +system.cpu2.iew.wb_sent 241491 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 241189 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 138145 # num instructions producing a value +system.cpu2.iew.wb_consumers 144798 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 1.413524 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.950163 # average fanout of values written-back +system.cpu2.iew.wb_rate 1.503906 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.954053 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 14614 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 5368 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 1286 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 152859 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 1.675858 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 2.068536 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 14779 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 4578 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 1304 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 152612 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 1.787933 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 2.101313 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 62472 40.87% 40.87% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 43239 28.29% 69.16% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 5166 3.38% 72.54% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 6247 4.09% 76.62% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 1528 1.00% 77.62% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 31073 20.33% 97.95% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 875 0.57% 98.52% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 941 0.62% 99.14% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 1318 0.86% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 57189 37.47% 37.47% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 45780 30.00% 67.47% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 5178 3.39% 70.86% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 5403 3.54% 74.40% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 1516 0.99% 75.40% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 34396 22.54% 97.94% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 886 0.58% 98.52% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 957 0.63% 99.14% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 1307 0.86% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 152859 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 256170 # Number of instructions committed -system.cpu2.commit.committedOps 256170 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 152612 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 272860 # Number of instructions committed +system.cpu2.commit.committedOps 272860 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 108804 # Number of memory references committed -system.cpu2.commit.loads 73922 # Number of loads committed -system.cpu2.commit.membars 4659 # Number of memory barriers committed -system.cpu2.commit.branches 45502 # Number of branches committed +system.cpu2.commit.refs 117938 # Number of memory references committed +system.cpu2.commit.loads 79744 # Number of loads committed +system.cpu2.commit.membars 3865 # Number of memory barriers committed +system.cpu2.commit.branches 48024 # Number of branches committed system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 176434 # Number of committed integer instructions. +system.cpu2.commit.int_insts 188084 # Number of committed integer instructions. system.cpu2.commit.function_calls 322 # Number of function calls committed. -system.cpu2.commit.op_class_0::No_OpClass 36297 14.17% 14.17% # Class of committed instruction -system.cpu2.commit.op_class_0::IntAlu 106410 41.54% 55.71% # Class of committed instruction -system.cpu2.commit.op_class_0::IntMult 0 0.00% 55.71% # Class of committed instruction -system.cpu2.commit.op_class_0::IntDiv 0 0.00% 55.71% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 55.71% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 55.71% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 55.71% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatMult 0 0.00% 55.71% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 55.71% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 55.71% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 55.71% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 55.71% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 55.71% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 55.71% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 55.71% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 55.71% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMult 0 0.00% 55.71% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 55.71% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShift 0 0.00% 55.71% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 55.71% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 55.71% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 55.71% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 55.71% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 55.71% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 55.71% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 55.71% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 55.71% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 55.71% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 55.71% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 55.71% # Class of committed instruction -system.cpu2.commit.op_class_0::MemRead 78581 30.68% 86.38% # Class of committed instruction -system.cpu2.commit.op_class_0::MemWrite 34882 13.62% 100.00% # Class of committed instruction +system.cpu2.commit.op_class_0::No_OpClass 38815 14.23% 14.23% # Class of committed instruction +system.cpu2.commit.op_class_0::IntAlu 112242 41.14% 55.36% # Class of committed instruction +system.cpu2.commit.op_class_0::IntMult 0 0.00% 55.36% # Class of committed instruction +system.cpu2.commit.op_class_0::IntDiv 0 0.00% 55.36% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 55.36% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 55.36% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 55.36% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatMult 0 0.00% 55.36% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 55.36% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 55.36% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 55.36% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 55.36% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 55.36% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 55.36% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 55.36% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 55.36% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMult 0 0.00% 55.36% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 55.36% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShift 0 0.00% 55.36% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 55.36% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 55.36% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 55.36% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 55.36% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 55.36% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 55.36% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 55.36% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 55.36% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 55.36% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 55.36% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 55.36% # Class of committed instruction +system.cpu2.commit.op_class_0::MemRead 83609 30.64% 86.00% # Class of committed instruction +system.cpu2.commit.op_class_0::MemWrite 38194 14.00% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu2.commit.op_class_0::total 256170 # Class of committed instruction -system.cpu2.commit.bw_lim_events 1318 # number cycles where commit BW limit reached +system.cpu2.commit.op_class_0::total 272860 # Class of committed instruction +system.cpu2.commit.bw_lim_events 1307 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 421739 # The number of ROB reads -system.cpu2.rob.rob_writes 544215 # The number of ROB writes +system.cpu2.rob.rob_reads 438358 # The number of ROB reads +system.cpu2.rob.rob_writes 577962 # The number of ROB writes system.cpu2.timesIdled 214 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 5156 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 43676 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 215214 # Number of Instructions Simulated -system.cpu2.committedOps 215214 # Number of Ops (including micro ops) Simulated -system.cpu2.cpi 0.746527 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 0.746527 # CPI: Total CPI of All Threads -system.cpu2.ipc 1.339537 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 1.339537 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 394013 # number of integer regfile reads -system.cpu2.int_regfile_writes 184721 # number of integer regfile writes +system.cpu2.idleCycles 5081 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 43644 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 230180 # Number of Instructions Simulated +system.cpu2.committedOps 230180 # Number of Ops (including micro ops) Simulated +system.cpu2.cpi 0.696737 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 0.696737 # CPI: Total CPI of All Threads +system.cpu2.ipc 1.435261 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 1.435261 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 421380 # number of integer regfile reads +system.cpu2.int_regfile_writes 197053 # number of integer regfile writes system.cpu2.fp_regfile_writes 64 # number of floating regfile writes -system.cpu2.misc_regfile_reads 112958 # number of misc regfile reads +system.cpu2.misc_regfile_reads 122100 # number of misc regfile reads system.cpu2.misc_regfile_writes 648 # number of misc regfile writes -system.cpu2.icache.tags.replacements 380 # number of replacements -system.cpu2.icache.tags.tagsinuse 85.367642 # Cycle average of tags in use -system.cpu2.icache.tags.total_refs 20592 # Total number of references to valid blocks. -system.cpu2.icache.tags.sampled_refs 493 # Sample count of references to valid blocks. -system.cpu2.icache.tags.avg_refs 41.768763 # Average number of references to valid blocks. -system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.icache.tags.occ_blocks::cpu2.inst 85.367642 # Average occupied blocks per requestor -system.cpu2.icache.tags.occ_percent::cpu2.inst 0.166734 # Average percentage of cache occupancy -system.cpu2.icache.tags.occ_percent::total 0.166734 # Average percentage of cache occupancy -system.cpu2.icache.tags.occ_task_id_blocks::1024 113 # Occupied blocks per task id -system.cpu2.icache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id -system.cpu2.icache.tags.age_task_id_blocks_1024::1 102 # Occupied blocks per task id -system.cpu2.icache.tags.occ_task_id_percent::1024 0.220703 # Percentage of cache occupancy per task id -system.cpu2.icache.tags.tag_accesses 21662 # Number of tag accesses -system.cpu2.icache.tags.data_accesses 21662 # Number of data accesses -system.cpu2.icache.ReadReq_hits::cpu2.inst 20592 # number of ReadReq hits -system.cpu2.icache.ReadReq_hits::total 20592 # number of ReadReq hits -system.cpu2.icache.demand_hits::cpu2.inst 20592 # number of demand (read+write) hits -system.cpu2.icache.demand_hits::total 20592 # number of demand (read+write) hits -system.cpu2.icache.overall_hits::cpu2.inst 20592 # number of overall hits -system.cpu2.icache.overall_hits::total 20592 # number of overall hits -system.cpu2.icache.ReadReq_misses::cpu2.inst 577 # number of ReadReq misses -system.cpu2.icache.ReadReq_misses::total 577 # number of ReadReq misses -system.cpu2.icache.demand_misses::cpu2.inst 577 # number of demand (read+write) misses -system.cpu2.icache.demand_misses::total 577 # number of demand (read+write) misses -system.cpu2.icache.overall_misses::cpu2.inst 577 # number of overall misses -system.cpu2.icache.overall_misses::total 577 # number of overall misses -system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 13065992 # number of ReadReq miss cycles -system.cpu2.icache.ReadReq_miss_latency::total 13065992 # number of ReadReq miss cycles -system.cpu2.icache.demand_miss_latency::cpu2.inst 13065992 # number of demand (read+write) miss cycles -system.cpu2.icache.demand_miss_latency::total 13065992 # number of demand (read+write) miss cycles -system.cpu2.icache.overall_miss_latency::cpu2.inst 13065992 # number of overall miss cycles -system.cpu2.icache.overall_miss_latency::total 13065992 # number of overall miss cycles -system.cpu2.icache.ReadReq_accesses::cpu2.inst 21169 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.ReadReq_accesses::total 21169 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.demand_accesses::cpu2.inst 21169 # number of demand (read+write) accesses -system.cpu2.icache.demand_accesses::total 21169 # number of demand (read+write) accesses -system.cpu2.icache.overall_accesses::cpu2.inst 21169 # number of overall (read+write) accesses -system.cpu2.icache.overall_accesses::total 21169 # number of overall (read+write) accesses -system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.027257 # miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_miss_rate::total 0.027257 # miss rate for ReadReq accesses -system.cpu2.icache.demand_miss_rate::cpu2.inst 0.027257 # miss rate for demand accesses -system.cpu2.icache.demand_miss_rate::total 0.027257 # miss rate for demand accesses -system.cpu2.icache.overall_miss_rate::cpu2.inst 0.027257 # miss rate for overall accesses -system.cpu2.icache.overall_miss_rate::total 0.027257 # miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 22644.700173 # average ReadReq miss latency -system.cpu2.icache.ReadReq_avg_miss_latency::total 22644.700173 # average ReadReq miss latency -system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 22644.700173 # average overall miss latency -system.cpu2.icache.demand_avg_miss_latency::total 22644.700173 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 22644.700173 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::total 22644.700173 # average overall miss latency -system.cpu2.icache.blocked_cycles::no_mshrs 128 # number of cycles access was blocked -system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu2.icache.blocked::no_mshrs 3 # number of cycles access was blocked -system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu2.icache.avg_blocked_cycles::no_mshrs 42.666667 # average number of cycles each access was blocked -system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu2.icache.fast_writes 0 # number of fast writes performed -system.cpu2.icache.cache_copies 0 # number of cache copies performed -system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst 84 # number of ReadReq MSHR hits -system.cpu2.icache.ReadReq_mshr_hits::total 84 # number of ReadReq MSHR hits -system.cpu2.icache.demand_mshr_hits::cpu2.inst 84 # number of demand (read+write) MSHR hits -system.cpu2.icache.demand_mshr_hits::total 84 # number of demand (read+write) MSHR hits -system.cpu2.icache.overall_mshr_hits::cpu2.inst 84 # number of overall MSHR hits -system.cpu2.icache.overall_mshr_hits::total 84 # number of overall MSHR hits -system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 493 # number of ReadReq MSHR misses -system.cpu2.icache.ReadReq_mshr_misses::total 493 # number of ReadReq MSHR misses -system.cpu2.icache.demand_mshr_misses::cpu2.inst 493 # number of demand (read+write) MSHR misses -system.cpu2.icache.demand_mshr_misses::total 493 # number of demand (read+write) MSHR misses -system.cpu2.icache.overall_mshr_misses::cpu2.inst 493 # number of overall MSHR misses -system.cpu2.icache.overall_mshr_misses::total 493 # number of overall MSHR misses -system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 10294257 # number of ReadReq MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_latency::total 10294257 # number of ReadReq MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 10294257 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::total 10294257 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 10294257 # number of overall MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::total 10294257 # number of overall MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.023289 # mshr miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.023289 # mshr miss rate for ReadReq accesses -system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.023289 # mshr miss rate for demand accesses -system.cpu2.icache.demand_mshr_miss_rate::total 0.023289 # mshr miss rate for demand accesses -system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.023289 # mshr miss rate for overall accesses -system.cpu2.icache.overall_mshr_miss_rate::total 0.023289 # mshr miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 20880.845842 # average ReadReq mshr miss latency -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 20880.845842 # average ReadReq mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 20880.845842 # average overall mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::total 20880.845842 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 20880.845842 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::total 20880.845842 # average overall mshr miss latency -system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu2.dcache.tags.replacements 0 # number of replacements -system.cpu2.dcache.tags.tagsinuse 25.876504 # Cycle average of tags in use -system.cpu2.dcache.tags.total_refs 41118 # Total number of references to valid blocks. -system.cpu2.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. -system.cpu2.dcache.tags.avg_refs 1417.862069 # Average number of references to valid blocks. +system.cpu2.dcache.tags.tagsinuse 25.900864 # Cycle average of tags in use +system.cpu2.dcache.tags.total_refs 44302 # Total number of references to valid blocks. +system.cpu2.dcache.tags.sampled_refs 28 # Sample count of references to valid blocks. +system.cpu2.dcache.tags.avg_refs 1582.214286 # Average number of references to valid blocks. system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 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per task id -system.cpu2.dcache.tags.tag_accesses 317671 # Number of tag accesses -system.cpu2.dcache.tags.data_accesses 317671 # Number of data accesses -system.cpu2.dcache.ReadReq_hits::cpu2.data 44059 # number of ReadReq hits -system.cpu2.dcache.ReadReq_hits::total 44059 # number of ReadReq hits -system.cpu2.dcache.WriteReq_hits::cpu2.data 34671 # number of WriteReq hits -system.cpu2.dcache.WriteReq_hits::total 34671 # number of WriteReq hits -system.cpu2.dcache.SwapReq_hits::cpu2.data 14 # number of SwapReq hits -system.cpu2.dcache.SwapReq_hits::total 14 # number of SwapReq hits -system.cpu2.dcache.demand_hits::cpu2.data 78730 # number of demand (read+write) hits -system.cpu2.dcache.demand_hits::total 78730 # number of demand (read+write) hits -system.cpu2.dcache.overall_hits::cpu2.data 78730 # number of overall hits -system.cpu2.dcache.overall_hits::total 78730 # number of overall hits -system.cpu2.dcache.ReadReq_misses::cpu2.data 415 # number of ReadReq misses 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of WriteReq accesses(hits+misses) -system.cpu2.dcache.SwapReq_accesses::cpu2.data 63 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.SwapReq_accesses::total 63 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.demand_accesses::cpu2.data 79293 # number of demand (read+write) accesses -system.cpu2.dcache.demand_accesses::total 79293 # number of demand (read+write) accesses -system.cpu2.dcache.overall_accesses::cpu2.data 79293 # number of overall (read+write) accesses -system.cpu2.dcache.overall_accesses::total 79293 # number of overall (read+write) accesses -system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.009331 # miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_miss_rate::total 0.009331 # miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.004251 # miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_miss_rate::total 0.004251 # miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.777778 # miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_miss_rate::total 0.777778 # miss rate for SwapReq accesses -system.cpu2.dcache.demand_miss_rate::cpu2.data 0.007100 # miss rate for demand accesses -system.cpu2.dcache.demand_miss_rate::total 0.007100 # miss rate for demand accesses -system.cpu2.dcache.overall_miss_rate::cpu2.data 0.007100 # miss rate for overall accesses -system.cpu2.dcache.overall_miss_rate::total 0.007100 # miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 17931.440964 # average ReadReq miss latency -system.cpu2.dcache.ReadReq_avg_miss_latency::total 17931.440964 # average ReadReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 24753.452703 # average WriteReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency::total 24753.452703 # average WriteReq miss latency -system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 9204.204082 # average SwapReq miss latency -system.cpu2.dcache.SwapReq_avg_miss_latency::total 9204.204082 # average SwapReq miss latency -system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 19724.793961 # average overall miss latency -system.cpu2.dcache.demand_avg_miss_latency::total 19724.793961 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 19724.793961 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::total 19724.793961 # average overall miss latency +system.cpu2.dcache.tags.occ_task_id_percent::1024 0.054688 # Percentage of cache occupancy per task id +system.cpu2.dcache.tags.tag_accesses 341013 # Number of tag accesses +system.cpu2.dcache.tags.data_accesses 341013 # Number of data accesses +system.cpu2.dcache.ReadReq_hits::cpu2.data 46548 # number of ReadReq hits +system.cpu2.dcache.ReadReq_hits::total 46548 # number of ReadReq hits +system.cpu2.dcache.WriteReq_hits::cpu2.data 37978 # number of WriteReq hits +system.cpu2.dcache.WriteReq_hits::total 37978 # number of WriteReq hits +system.cpu2.dcache.SwapReq_hits::cpu2.data 12 # number of SwapReq hits +system.cpu2.dcache.SwapReq_hits::total 12 # number of SwapReq hits +system.cpu2.dcache.demand_hits::cpu2.data 84526 # number of demand (read+write) hits +system.cpu2.dcache.demand_hits::total 84526 # number of demand (read+write) hits +system.cpu2.dcache.overall_hits::cpu2.data 84526 # number of overall hits +system.cpu2.dcache.overall_hits::total 84526 # number of overall hits +system.cpu2.dcache.ReadReq_misses::cpu2.data 448 # number of ReadReq misses +system.cpu2.dcache.ReadReq_misses::total 448 # number of ReadReq misses +system.cpu2.dcache.WriteReq_misses::cpu2.data 149 # number of WriteReq misses +system.cpu2.dcache.WriteReq_misses::total 149 # number of WriteReq misses +system.cpu2.dcache.SwapReq_misses::cpu2.data 55 # number of SwapReq misses +system.cpu2.dcache.SwapReq_misses::total 55 # number of SwapReq misses +system.cpu2.dcache.demand_misses::cpu2.data 597 # number of demand (read+write) misses +system.cpu2.dcache.demand_misses::total 597 # number of demand (read+write) misses +system.cpu2.dcache.overall_misses::cpu2.data 597 # number of overall misses +system.cpu2.dcache.overall_misses::total 597 # number of overall misses +system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 7705986 # number of ReadReq miss cycles +system.cpu2.dcache.ReadReq_miss_latency::total 7705986 # number of ReadReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 3669012 # number of WriteReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::total 3669012 # number of WriteReq miss cycles +system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 505508 # number of SwapReq miss cycles +system.cpu2.dcache.SwapReq_miss_latency::total 505508 # number of SwapReq miss cycles +system.cpu2.dcache.demand_miss_latency::cpu2.data 11374998 # number of demand (read+write) miss cycles +system.cpu2.dcache.demand_miss_latency::total 11374998 # number of demand (read+write) miss cycles +system.cpu2.dcache.overall_miss_latency::cpu2.data 11374998 # number of overall miss cycles +system.cpu2.dcache.overall_miss_latency::total 11374998 # number of overall miss cycles +system.cpu2.dcache.ReadReq_accesses::cpu2.data 46996 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.ReadReq_accesses::total 46996 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses::cpu2.data 38127 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses::total 38127 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.SwapReq_accesses::cpu2.data 67 # number of SwapReq accesses(hits+misses) +system.cpu2.dcache.SwapReq_accesses::total 67 # number of SwapReq accesses(hits+misses) +system.cpu2.dcache.demand_accesses::cpu2.data 85123 # number of demand (read+write) accesses +system.cpu2.dcache.demand_accesses::total 85123 # number of demand (read+write) accesses +system.cpu2.dcache.overall_accesses::cpu2.data 85123 # number of overall (read+write) accesses +system.cpu2.dcache.overall_accesses::total 85123 # number of overall (read+write) accesses +system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.009533 # miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_miss_rate::total 0.009533 # miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.003908 # miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_miss_rate::total 0.003908 # miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.820896 # miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_miss_rate::total 0.820896 # miss rate for SwapReq accesses +system.cpu2.dcache.demand_miss_rate::cpu2.data 0.007013 # miss rate for demand accesses +system.cpu2.dcache.demand_miss_rate::total 0.007013 # miss rate for demand accesses +system.cpu2.dcache.overall_miss_rate::cpu2.data 0.007013 # miss rate for overall accesses +system.cpu2.dcache.overall_miss_rate::total 0.007013 # miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 17200.861607 # average ReadReq miss latency +system.cpu2.dcache.ReadReq_avg_miss_latency::total 17200.861607 # average ReadReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 24624.241611 # average WriteReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::total 24624.241611 # average WriteReq miss latency +system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 9191.054545 # average SwapReq miss latency +system.cpu2.dcache.SwapReq_avg_miss_latency::total 9191.054545 # average SwapReq miss latency +system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 19053.597990 # average overall miss latency +system.cpu2.dcache.demand_avg_miss_latency::total 19053.597990 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 19053.597990 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::total 19053.597990 # average overall miss latency system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -2291,518 +1707,519 @@ system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.dcache.fast_writes 0 # number of fast writes performed system.cpu2.dcache.cache_copies 0 # number of cache copies performed -system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 262 # number of ReadReq MSHR hits -system.cpu2.dcache.ReadReq_mshr_hits::total 262 # number of ReadReq MSHR hits -system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 40 # number of WriteReq MSHR hits -system.cpu2.dcache.WriteReq_mshr_hits::total 40 # number of WriteReq MSHR hits -system.cpu2.dcache.demand_mshr_hits::cpu2.data 302 # number of demand (read+write) MSHR hits -system.cpu2.dcache.demand_mshr_hits::total 302 # number of demand (read+write) MSHR hits -system.cpu2.dcache.overall_mshr_hits::cpu2.data 302 # number of overall MSHR hits -system.cpu2.dcache.overall_mshr_hits::total 302 # number of overall MSHR hits -system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 153 # number of ReadReq MSHR misses -system.cpu2.dcache.ReadReq_mshr_misses::total 153 # number of ReadReq MSHR misses +system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 289 # number of ReadReq MSHR hits +system.cpu2.dcache.ReadReq_mshr_hits::total 289 # number of ReadReq MSHR hits +system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 41 # number of WriteReq MSHR hits +system.cpu2.dcache.WriteReq_mshr_hits::total 41 # number of WriteReq MSHR hits +system.cpu2.dcache.demand_mshr_hits::cpu2.data 330 # number of demand (read+write) MSHR hits +system.cpu2.dcache.demand_mshr_hits::total 330 # number of demand (read+write) MSHR hits +system.cpu2.dcache.overall_mshr_hits::cpu2.data 330 # number of overall MSHR hits +system.cpu2.dcache.overall_mshr_hits::total 330 # number of overall MSHR hits +system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 159 # number of ReadReq MSHR misses +system.cpu2.dcache.ReadReq_mshr_misses::total 159 # number of ReadReq MSHR misses system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 108 # number of WriteReq MSHR misses system.cpu2.dcache.WriteReq_mshr_misses::total 108 # number of WriteReq MSHR misses -system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 49 # number of SwapReq MSHR misses -system.cpu2.dcache.SwapReq_mshr_misses::total 49 # number of SwapReq MSHR misses -system.cpu2.dcache.demand_mshr_misses::cpu2.data 261 # number of demand (read+write) MSHR misses -system.cpu2.dcache.demand_mshr_misses::total 261 # number of demand (read+write) MSHR misses -system.cpu2.dcache.overall_mshr_misses::cpu2.data 261 # number of overall MSHR misses -system.cpu2.dcache.overall_mshr_misses::total 261 # number of overall MSHR misses -system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1686771 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1686771 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1511239 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1511239 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 352994 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency::total 352994 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3198010 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::total 3198010 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3198010 # number of overall MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::total 3198010 # number of overall MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003440 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003440 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.003102 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.003102 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.777778 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.777778 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.003292 # mshr miss rate for demand accesses -system.cpu2.dcache.demand_mshr_miss_rate::total 0.003292 # mshr miss rate for demand accesses -system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.003292 # mshr miss rate for overall accesses -system.cpu2.dcache.overall_mshr_miss_rate::total 0.003292 # mshr miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 11024.647059 # average ReadReq mshr miss latency -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 11024.647059 # average ReadReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 13992.953704 # average WriteReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 13992.953704 # average WriteReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 7203.959184 # average SwapReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 7203.959184 # average SwapReq mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 12252.911877 # average overall mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::total 12252.911877 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 12252.911877 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::total 12252.911877 # average overall mshr miss latency +system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 55 # number of SwapReq MSHR misses +system.cpu2.dcache.SwapReq_mshr_misses::total 55 # number of SwapReq MSHR misses +system.cpu2.dcache.demand_mshr_misses::cpu2.data 267 # number of demand (read+write) MSHR misses +system.cpu2.dcache.demand_mshr_misses::total 267 # number of demand (read+write) MSHR misses +system.cpu2.dcache.overall_mshr_misses::cpu2.data 267 # number of overall MSHR misses +system.cpu2.dcache.overall_mshr_misses::total 267 # number of overall MSHR misses +system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1526276 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1526276 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1511738 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1511738 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 395492 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::total 395492 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3038014 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::total 3038014 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3038014 # number of overall MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::total 3038014 # number of overall MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003383 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003383 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.002833 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.002833 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.820896 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.820896 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.003137 # mshr miss rate for demand accesses +system.cpu2.dcache.demand_mshr_miss_rate::total 0.003137 # mshr miss rate for demand accesses +system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.003137 # mshr miss rate for overall accesses +system.cpu2.dcache.overall_mshr_miss_rate::total 0.003137 # mshr miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 9599.220126 # average ReadReq mshr miss latency +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 9599.220126 # average ReadReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 13997.574074 # average WriteReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 13997.574074 # average WriteReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 7190.763636 # average SwapReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 7190.763636 # average SwapReq mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 11378.329588 # average overall mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::total 11378.329588 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 11378.329588 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::total 11378.329588 # average overall mshr miss latency system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.branchPred.lookups 48141 # Number of BP lookups -system.cpu3.branchPred.condPredicted 44605 # Number of conditional branches predicted -system.cpu3.branchPred.condIncorrect 1305 # Number of conditional branches incorrect -system.cpu3.branchPred.BTBLookups 40897 # Number of BTB lookups -system.cpu3.branchPred.BTBHits 39710 # Number of BTB hits +system.cpu2.icache.tags.replacements 378 # number of replacements +system.cpu2.icache.tags.tagsinuse 84.872672 # Cycle average of tags in use +system.cpu2.icache.tags.total_refs 18881 # Total number of references to valid blocks. +system.cpu2.icache.tags.sampled_refs 490 # Sample count of references to valid blocks. +system.cpu2.icache.tags.avg_refs 38.532653 # Average number of references to valid blocks. +system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu2.icache.tags.occ_blocks::cpu2.inst 84.872672 # Average occupied blocks per requestor +system.cpu2.icache.tags.occ_percent::cpu2.inst 0.165767 # Average percentage of cache occupancy +system.cpu2.icache.tags.occ_percent::total 0.165767 # Average percentage of cache occupancy +system.cpu2.icache.tags.occ_task_id_blocks::1024 112 # Occupied blocks per task id +system.cpu2.icache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id +system.cpu2.icache.tags.age_task_id_blocks_1024::1 101 # Occupied blocks per task id +system.cpu2.icache.tags.occ_task_id_percent::1024 0.218750 # Percentage of cache occupancy per task id +system.cpu2.icache.tags.tag_accesses 19941 # Number of tag accesses +system.cpu2.icache.tags.data_accesses 19941 # Number of data accesses +system.cpu2.icache.ReadReq_hits::cpu2.inst 18881 # number of ReadReq hits +system.cpu2.icache.ReadReq_hits::total 18881 # number of ReadReq hits +system.cpu2.icache.demand_hits::cpu2.inst 18881 # number of demand (read+write) hits +system.cpu2.icache.demand_hits::total 18881 # number of demand (read+write) hits +system.cpu2.icache.overall_hits::cpu2.inst 18881 # number of overall hits +system.cpu2.icache.overall_hits::total 18881 # number of overall hits +system.cpu2.icache.ReadReq_misses::cpu2.inst 570 # number of ReadReq misses +system.cpu2.icache.ReadReq_misses::total 570 # number of ReadReq misses +system.cpu2.icache.demand_misses::cpu2.inst 570 # number of demand (read+write) misses +system.cpu2.icache.demand_misses::total 570 # number of demand (read+write) misses +system.cpu2.icache.overall_misses::cpu2.inst 570 # number of overall misses +system.cpu2.icache.overall_misses::total 570 # number of overall misses +system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 13340243 # number of ReadReq miss cycles +system.cpu2.icache.ReadReq_miss_latency::total 13340243 # number of ReadReq miss cycles +system.cpu2.icache.demand_miss_latency::cpu2.inst 13340243 # number of demand (read+write) miss cycles +system.cpu2.icache.demand_miss_latency::total 13340243 # number of demand (read+write) miss cycles +system.cpu2.icache.overall_miss_latency::cpu2.inst 13340243 # number of overall miss cycles +system.cpu2.icache.overall_miss_latency::total 13340243 # number of overall miss cycles +system.cpu2.icache.ReadReq_accesses::cpu2.inst 19451 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.ReadReq_accesses::total 19451 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.demand_accesses::cpu2.inst 19451 # number of demand (read+write) accesses +system.cpu2.icache.demand_accesses::total 19451 # number of demand (read+write) accesses +system.cpu2.icache.overall_accesses::cpu2.inst 19451 # number of overall (read+write) accesses +system.cpu2.icache.overall_accesses::total 19451 # number of overall (read+write) accesses +system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.029304 # miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_miss_rate::total 0.029304 # miss rate for ReadReq accesses +system.cpu2.icache.demand_miss_rate::cpu2.inst 0.029304 # miss rate for demand accesses +system.cpu2.icache.demand_miss_rate::total 0.029304 # miss rate for demand accesses +system.cpu2.icache.overall_miss_rate::cpu2.inst 0.029304 # miss rate for overall accesses +system.cpu2.icache.overall_miss_rate::total 0.029304 # miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 23403.935088 # average ReadReq miss latency +system.cpu2.icache.ReadReq_avg_miss_latency::total 23403.935088 # average ReadReq miss latency +system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 23403.935088 # average overall miss latency +system.cpu2.icache.demand_avg_miss_latency::total 23403.935088 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 23403.935088 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::total 23403.935088 # average overall miss latency +system.cpu2.icache.blocked_cycles::no_mshrs 128 # number of cycles access was blocked +system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu2.icache.blocked::no_mshrs 3 # number of cycles access was blocked +system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu2.icache.avg_blocked_cycles::no_mshrs 42.666667 # average number of cycles each access was blocked +system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu2.icache.fast_writes 0 # number of fast writes performed +system.cpu2.icache.cache_copies 0 # number of cache copies performed +system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst 80 # number of ReadReq MSHR hits +system.cpu2.icache.ReadReq_mshr_hits::total 80 # number of ReadReq MSHR hits +system.cpu2.icache.demand_mshr_hits::cpu2.inst 80 # number of demand (read+write) MSHR hits +system.cpu2.icache.demand_mshr_hits::total 80 # number of demand (read+write) MSHR hits +system.cpu2.icache.overall_mshr_hits::cpu2.inst 80 # number of overall MSHR hits +system.cpu2.icache.overall_mshr_hits::total 80 # number of overall MSHR hits +system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 490 # number of ReadReq MSHR misses +system.cpu2.icache.ReadReq_mshr_misses::total 490 # number of ReadReq MSHR misses +system.cpu2.icache.demand_mshr_misses::cpu2.inst 490 # number of demand (read+write) MSHR misses +system.cpu2.icache.demand_mshr_misses::total 490 # number of demand (read+write) MSHR misses +system.cpu2.icache.overall_mshr_misses::cpu2.inst 490 # number of overall MSHR misses +system.cpu2.icache.overall_mshr_misses::total 490 # number of overall MSHR misses +system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 10370006 # number of ReadReq MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_latency::total 10370006 # number of ReadReq MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 10370006 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::total 10370006 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 10370006 # number of overall MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::total 10370006 # number of overall MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.025192 # mshr miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.025192 # mshr miss rate for ReadReq accesses +system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.025192 # mshr miss rate for demand accesses +system.cpu2.icache.demand_mshr_miss_rate::total 0.025192 # mshr miss rate for demand accesses +system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.025192 # mshr miss rate for overall accesses +system.cpu2.icache.overall_mshr_miss_rate::total 0.025192 # mshr miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 21163.277551 # average ReadReq mshr miss latency +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 21163.277551 # average ReadReq mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 21163.277551 # average overall mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::total 21163.277551 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 21163.277551 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::total 21163.277551 # average overall mshr miss latency +system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu3.branchPred.lookups 49708 # Number of BP lookups +system.cpu3.branchPred.condPredicted 46346 # Number of conditional branches predicted +system.cpu3.branchPred.condIncorrect 1279 # Number of conditional branches incorrect +system.cpu3.branchPred.BTBLookups 42456 # Number of BTB lookups +system.cpu3.branchPred.BTBHits 41477 # Number of BTB hits system.cpu3.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu3.branchPred.BTBHitPct 97.097587 # BTB Hit Percentage -system.cpu3.branchPred.usedRAS 884 # Number of times the RAS was used to get a target. +system.cpu3.branchPred.BTBHitPct 97.694083 # BTB Hit Percentage +system.cpu3.branchPred.usedRAS 887 # Number of times the RAS was used to get a target. system.cpu3.branchPred.RASInCorrect 231 # Number of incorrect RAS predictions. -system.cpu3.numCycles 160319 # number of cpu cycles simulated +system.cpu3.numCycles 160031 # number of cpu cycles simulated system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu3.fetch.icacheStallCycles 33851 # Number of cycles fetch is stalled on an Icache miss -system.cpu3.fetch.Insts 260297 # Number of instructions fetch has processed -system.cpu3.fetch.Branches 48141 # Number of branches that fetch encountered -system.cpu3.fetch.predictedBranches 40594 # Number of branches that fetch has predicted taken -system.cpu3.fetch.Cycles 122891 # Number of cycles fetch has run and was not squashing or blocked -system.cpu3.fetch.SquashCycles 2765 # Number of cycles fetch has spent squashing +system.cpu3.fetch.icacheStallCycles 32677 # Number of cycles fetch is stalled on an Icache miss +system.cpu3.fetch.Insts 271496 # Number of instructions fetch has processed +system.cpu3.fetch.Branches 49708 # Number of branches that fetch encountered +system.cpu3.fetch.predictedBranches 42364 # Number of branches that fetch has predicted taken +system.cpu3.fetch.Cycles 123781 # Number of cycles fetch has run and was not squashing or blocked +system.cpu3.fetch.SquashCycles 2713 # Number of cycles fetch has spent squashing system.cpu3.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu3.fetch.NoActiveThreadStallCycles 10 # Number of stall cycles due to no active thread to fetch from -system.cpu3.fetch.PendingTrapStallCycles 1076 # Number of stall cycles due to pending traps -system.cpu3.fetch.CacheLines 24972 # Number of cache lines fetched -system.cpu3.fetch.IcacheSquashes 417 # Number of outstanding Icache misses that were squashed -system.cpu3.fetch.rateDist::samples 159213 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::mean 1.634898 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::stdev 2.125574 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.PendingTrapStallCycles 1129 # Number of stall cycles due to pending traps +system.cpu3.fetch.CacheLines 23830 # Number of cache lines fetched +system.cpu3.fetch.IcacheSquashes 414 # Number of outstanding Icache misses that were squashed +system.cpu3.fetch.rateDist::samples 158956 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::mean 1.707995 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::stdev 2.148637 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::0 64563 40.55% 40.55% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::1 48696 30.59% 71.14% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::2 8235 5.17% 76.31% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::3 3504 2.20% 78.51% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::4 1064 0.67% 79.18% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::5 27204 17.09% 96.26% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::6 1240 0.78% 97.04% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::7 753 0.47% 97.52% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::8 3954 2.48% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::0 61281 38.55% 38.55% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::1 50034 31.48% 70.03% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::2 7755 4.88% 74.91% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::3 3467 2.18% 77.09% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::4 1003 0.63% 77.72% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::5 29472 18.54% 96.26% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::6 1313 0.83% 97.09% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::7 747 0.47% 97.56% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::8 3884 2.44% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::total 159213 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.branchRate 0.300283 # Number of branch fetches per cycle -system.cpu3.fetch.rate 1.623619 # Number of inst fetches per cycle -system.cpu3.decode.IdleCycles 17777 # Number of cycles decode is idle -system.cpu3.decode.BlockedCycles 68157 # Number of cycles decode is blocked -system.cpu3.decode.RunCycles 67726 # Number of cycles decode is running -system.cpu3.decode.UnblockCycles 4161 # Number of cycles decode is unblocking -system.cpu3.decode.SquashCycles 1382 # Number of cycles decode is squashing -system.cpu3.decode.DecodedInsts 245360 # Number of instructions handled by decode -system.cpu3.rename.SquashCycles 1382 # Number of cycles rename is squashing -system.cpu3.rename.IdleCycles 18479 # Number of cycles rename is idle -system.cpu3.rename.BlockCycles 33142 # Number of cycles rename is blocking -system.cpu3.rename.serializeStallCycles 12841 # count of cycles rename stalled for serializing inst -system.cpu3.rename.RunCycles 69300 # Number of cycles rename is running -system.cpu3.rename.UnblockCycles 24059 # Number of cycles rename is unblocking -system.cpu3.rename.RenamedInsts 241885 # Number of instructions processed by rename -system.cpu3.rename.IQFullEvents 21460 # Number of times rename has blocked due to IQ full -system.cpu3.rename.LQFullEvents 28 # Number of times rename has blocked due to LQ full +system.cpu3.fetch.rateDist::total 158956 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.branchRate 0.310615 # Number of branch fetches per cycle +system.cpu3.fetch.rate 1.696521 # Number of inst fetches per cycle +system.cpu3.decode.IdleCycles 17592 # Number of cycles decode is idle +system.cpu3.decode.BlockedCycles 63734 # Number of cycles decode is blocked +system.cpu3.decode.RunCycles 72321 # Number of cycles decode is running +system.cpu3.decode.UnblockCycles 3943 # Number of cycles decode is unblocking +system.cpu3.decode.SquashCycles 1356 # Number of cycles decode is squashing +system.cpu3.decode.DecodedInsts 257189 # Number of instructions handled by decode +system.cpu3.rename.SquashCycles 1356 # Number of cycles rename is squashing +system.cpu3.rename.IdleCycles 18288 # Number of cycles rename is idle +system.cpu3.rename.BlockCycles 30790 # Number of cycles rename is blocking +system.cpu3.rename.serializeStallCycles 12415 # count of cycles rename stalled for serializing inst +system.cpu3.rename.RunCycles 73229 # Number of cycles rename is running +system.cpu3.rename.UnblockCycles 22868 # Number of cycles rename is unblocking +system.cpu3.rename.RenamedInsts 253914 # Number of instructions processed by rename +system.cpu3.rename.IQFullEvents 19808 # Number of times rename has blocked due to IQ full +system.cpu3.rename.LQFullEvents 26 # Number of times rename has blocked due to LQ full system.cpu3.rename.FullRegisterEvents 3 # Number of times there has been no free registers -system.cpu3.rename.RenamedOperands 168616 # Number of destination operands rename has renamed -system.cpu3.rename.RenameLookups 454082 # Number of register rename lookups that rename has made -system.cpu3.rename.int_rename_lookups 355646 # Number of integer rename lookups -system.cpu3.rename.CommittedMaps 153987 # Number of HB maps that are committed -system.cpu3.rename.UndoneMaps 14629 # Number of HB maps that are undone due to squashing -system.cpu3.rename.serializingInsts 1214 # count of serializing insts renamed -system.cpu3.rename.tempSerializingInsts 1272 # count of temporary serializing insts renamed -system.cpu3.rename.skidInsts 28919 # count of insts added to the skid buffer -system.cpu3.memDep0.insertedLoads 65522 # Number of loads inserted to the mem dependence unit. -system.cpu3.memDep0.insertedStores 29976 # Number of stores inserted to the mem dependence unit. -system.cpu3.memDep0.conflictingLoads 31799 # Number of conflicting loads. -system.cpu3.memDep0.conflictingStores 24828 # Number of conflicting stores. -system.cpu3.iq.iqInstsAdded 198526 # Number of instructions added to the IQ (excludes non-spec) -system.cpu3.iq.iqNonSpecInstsAdded 7988 # Number of non-speculative instructions added to the IQ -system.cpu3.iq.iqInstsIssued 201423 # Number of instructions issued -system.cpu3.iq.iqSquashedInstsIssued 33 # Number of squashed instructions issued -system.cpu3.iq.iqSquashedInstsExamined 12862 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu3.iq.iqSquashedOperandsExamined 11999 # Number of squashed operands that are examined and possibly removed from graph -system.cpu3.iq.iqSquashedNonSpecRemoved 692 # Number of squashed non-spec instructions that were removed -system.cpu3.iq.issued_per_cycle::samples 159213 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::mean 1.265117 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::stdev 1.367863 # Number of insts issued each cycle +system.cpu3.rename.RenamedOperands 177532 # Number of destination operands rename has renamed +system.cpu3.rename.RenameLookups 480099 # Number of register rename lookups that rename has made +system.cpu3.rename.int_rename_lookups 375267 # Number of integer rename lookups +system.cpu3.rename.CommittedMaps 162743 # Number of HB maps that are committed +system.cpu3.rename.UndoneMaps 14789 # Number of HB maps that are undone due to squashing +system.cpu3.rename.serializingInsts 1176 # count of serializing insts renamed +system.cpu3.rename.tempSerializingInsts 1243 # count of temporary serializing insts renamed +system.cpu3.rename.skidInsts 27539 # count of insts added to the skid buffer +system.cpu3.memDep0.insertedLoads 69653 # Number of loads inserted to the mem dependence unit. +system.cpu3.memDep0.insertedStores 32298 # Number of stores inserted to the mem dependence unit. +system.cpu3.memDep0.conflictingLoads 33633 # Number of conflicting loads. +system.cpu3.memDep0.conflictingStores 27116 # Number of conflicting stores. +system.cpu3.iq.iqInstsAdded 209239 # Number of instructions added to the IQ (excludes non-spec) +system.cpu3.iq.iqNonSpecInstsAdded 7471 # Number of non-speculative instructions added to the IQ +system.cpu3.iq.iqInstsIssued 211679 # Number of instructions issued +system.cpu3.iq.iqSquashedInstsIssued 49 # Number of squashed instructions issued +system.cpu3.iq.iqSquashedInstsExamined 13005 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu3.iq.iqSquashedOperandsExamined 11959 # Number of squashed operands that are examined and possibly removed from graph +system.cpu3.iq.iqSquashedNonSpecRemoved 663 # Number of squashed non-spec instructions that were removed +system.cpu3.iq.issued_per_cycle::samples 158956 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::mean 1.331683 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::stdev 1.377458 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::0 68514 43.03% 43.03% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::1 26230 16.47% 59.51% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::2 29303 18.40% 77.91% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::3 28880 18.14% 96.05% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::4 3418 2.15% 98.20% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::5 1568 0.98% 99.18% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::6 871 0.55% 99.73% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::7 223 0.14% 99.87% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::8 206 0.13% 100.00% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::0 65156 40.99% 40.99% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::1 24774 15.59% 56.58% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::2 31508 19.82% 76.40% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::3 31138 19.59% 95.99% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::4 3432 2.16% 98.15% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::5 1609 1.01% 99.16% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::6 879 0.55% 99.71% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::7 252 0.16% 99.87% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::8 208 0.13% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::total 159213 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::total 158956 # Number of insts issued each cycle system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntAlu 92 26.36% 26.36% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntMult 0 0.00% 26.36% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntDiv 0 0.00% 26.36% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatAdd 0 0.00% 26.36% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCmp 0 0.00% 26.36% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCvt 0 0.00% 26.36% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatMult 0 0.00% 26.36% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatDiv 0 0.00% 26.36% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 26.36% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAdd 0 0.00% 26.36% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 26.36% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAlu 0 0.00% 26.36% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCmp 0 0.00% 26.36% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCvt 0 0.00% 26.36% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMisc 0 0.00% 26.36% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMult 0 0.00% 26.36% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 26.36% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShift 0 0.00% 26.36% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 26.36% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 26.36% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 26.36% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 26.36% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 26.36% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 26.36% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 26.36% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 26.36% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 26.36% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 26.36% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 26.36% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemRead 48 13.75% 40.11% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemWrite 209 59.89% 100.00% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntAlu 91 25.07% 25.07% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntMult 0 0.00% 25.07% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntDiv 0 0.00% 25.07% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatAdd 0 0.00% 25.07% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCmp 0 0.00% 25.07% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCvt 0 0.00% 25.07% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatMult 0 0.00% 25.07% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatDiv 0 0.00% 25.07% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 25.07% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAdd 0 0.00% 25.07% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 25.07% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAlu 0 0.00% 25.07% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCmp 0 0.00% 25.07% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCvt 0 0.00% 25.07% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMisc 0 0.00% 25.07% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMult 0 0.00% 25.07% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 25.07% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShift 0 0.00% 25.07% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 25.07% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 25.07% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 25.07% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 25.07% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 25.07% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 25.07% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 25.07% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 25.07% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 25.07% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.07% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 25.07% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemRead 63 17.36% 42.42% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemWrite 209 57.58% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu3.iq.FU_type_0::IntAlu 100972 50.13% 50.13% # Type of FU issued -system.cpu3.iq.FU_type_0::IntMult 0 0.00% 50.13% # Type of FU issued -system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 50.13% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 50.13% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 50.13% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 50.13% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 50.13% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 50.13% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 50.13% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 50.13% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 50.13% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 50.13% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 50.13% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 50.13% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 50.13% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 50.13% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 50.13% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 50.13% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 50.13% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 50.13% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 50.13% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 50.13% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 50.13% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 50.13% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 50.13% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 50.13% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 50.13% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 50.13% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 50.13% # Type of FU issued -system.cpu3.iq.FU_type_0::MemRead 71204 35.35% 85.48% # Type of FU issued -system.cpu3.iq.FU_type_0::MemWrite 29247 14.52% 100.00% # Type of FU issued +system.cpu3.iq.FU_type_0::IntAlu 105163 49.68% 49.68% # Type of FU issued +system.cpu3.iq.FU_type_0::IntMult 0 0.00% 49.68% # Type of FU issued +system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 49.68% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 49.68% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 49.68% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 49.68% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 49.68% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 49.68% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 49.68% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 49.68% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 49.68% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 49.68% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 49.68% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 49.68% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 49.68% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 49.68% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 49.68% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 49.68% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.68% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 49.68% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.68% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.68% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.68% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.68% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.68% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.68% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 49.68% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.68% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.68% # Type of FU issued +system.cpu3.iq.FU_type_0::MemRead 74926 35.40% 85.08% # Type of FU issued +system.cpu3.iq.FU_type_0::MemWrite 31590 14.92% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu3.iq.FU_type_0::total 201423 # Type of FU issued -system.cpu3.iq.rate 1.256389 # Inst issue rate -system.cpu3.iq.fu_busy_cnt 349 # FU busy when requested -system.cpu3.iq.fu_busy_rate 0.001733 # FU busy rate (busy events/executed inst) -system.cpu3.iq.int_inst_queue_reads 562441 # Number of integer instruction queue reads -system.cpu3.iq.int_inst_queue_writes 219414 # Number of integer instruction queue writes -system.cpu3.iq.int_inst_queue_wakeup_accesses 199715 # Number of integer instruction queue wakeup accesses +system.cpu3.iq.FU_type_0::total 211679 # Type of FU issued +system.cpu3.iq.rate 1.322737 # Inst issue rate +system.cpu3.iq.fu_busy_cnt 363 # FU busy when requested +system.cpu3.iq.fu_busy_rate 0.001715 # FU busy rate (busy events/executed inst) +system.cpu3.iq.int_inst_queue_reads 582726 # Number of integer instruction queue reads +system.cpu3.iq.int_inst_queue_writes 229757 # Number of integer instruction queue writes +system.cpu3.iq.int_inst_queue_wakeup_accesses 209929 # Number of integer instruction queue wakeup accesses system.cpu3.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu3.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu3.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu3.iq.int_alu_accesses 201772 # Number of integer alu accesses +system.cpu3.iq.int_alu_accesses 212042 # Number of integer alu accesses system.cpu3.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu3.iew.lsq.thread0.forwLoads 24567 # Number of loads that had data forwarded from stores +system.cpu3.iew.lsq.thread0.forwLoads 26876 # Number of loads that had data forwarded from stores system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu3.iew.lsq.thread0.squashedLoads 2806 # Number of loads squashed +system.cpu3.iew.lsq.thread0.squashedLoads 2797 # Number of loads squashed system.cpu3.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed -system.cpu3.iew.lsq.thread0.memOrderViolation 38 # Number of memory ordering violations -system.cpu3.iew.lsq.thread0.squashedStores 1637 # Number of stores squashed +system.cpu3.iew.lsq.thread0.memOrderViolation 42 # Number of memory ordering violations +system.cpu3.iew.lsq.thread0.squashedStores 1652 # Number of stores squashed system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu3.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu3.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu3.iew.iewSquashCycles 1382 # Number of cycles IEW is squashing -system.cpu3.iew.iewBlockCycles 8523 # Number of cycles IEW is blocking -system.cpu3.iew.iewUnblockCycles 57 # Number of cycles IEW is unblocking -system.cpu3.iew.iewDispatchedInsts 239131 # Number of instructions dispatched to IQ -system.cpu3.iew.iewDispSquashedInsts 178 # Number of squashed instructions skipped by dispatch -system.cpu3.iew.iewDispLoadInsts 65522 # Number of dispatched load instructions -system.cpu3.iew.iewDispStoreInsts 29976 # Number of dispatched store instructions -system.cpu3.iew.iewDispNonSpecInsts 1120 # Number of dispatched non-speculative instructions -system.cpu3.iew.iewIQFullEvents 32 # Number of times the IQ has become full, causing a stall +system.cpu3.iew.iewSquashCycles 1356 # Number of cycles IEW is squashing +system.cpu3.iew.iewBlockCycles 8047 # Number of cycles IEW is blocking +system.cpu3.iew.iewUnblockCycles 61 # Number of cycles IEW is unblocking +system.cpu3.iew.iewDispatchedInsts 251105 # Number of instructions dispatched to IQ +system.cpu3.iew.iewDispSquashedInsts 176 # Number of squashed instructions skipped by dispatch +system.cpu3.iew.iewDispLoadInsts 69653 # Number of dispatched load instructions +system.cpu3.iew.iewDispStoreInsts 32298 # Number of dispatched store instructions +system.cpu3.iew.iewDispNonSpecInsts 1093 # Number of dispatched non-speculative instructions +system.cpu3.iew.iewIQFullEvents 37 # Number of times the IQ has become full, causing a stall system.cpu3.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu3.iew.memOrderViolationEvents 38 # Number of memory order violations -system.cpu3.iew.predictedTakenIncorrect 471 # Number of branches that were predicted taken incorrectly -system.cpu3.iew.predictedNotTakenIncorrect 1054 # Number of branches that were predicted not taken incorrectly -system.cpu3.iew.branchMispredicts 1525 # Number of branch mispredicts detected at execute -system.cpu3.iew.iewExecutedInsts 200291 # Number of executed instructions -system.cpu3.iew.iewExecLoadInsts 64311 # Number of load instructions executed -system.cpu3.iew.iewExecSquashedInsts 1132 # Number of squashed instructions skipped in execute +system.cpu3.iew.memOrderViolationEvents 42 # Number of memory order violations +system.cpu3.iew.predictedTakenIncorrect 461 # Number of branches that were predicted taken incorrectly +system.cpu3.iew.predictedNotTakenIncorrect 1042 # Number of branches that were predicted not taken incorrectly +system.cpu3.iew.branchMispredicts 1503 # Number of branch mispredicts detected at execute +system.cpu3.iew.iewExecutedInsts 210537 # Number of executed instructions +system.cpu3.iew.iewExecLoadInsts 68521 # Number of load instructions executed +system.cpu3.iew.iewExecSquashedInsts 1142 # Number of squashed instructions skipped in execute system.cpu3.iew.exec_swp 0 # number of swp insts executed -system.cpu3.iew.exec_nop 32617 # number of nop insts executed -system.cpu3.iew.exec_refs 93457 # number of memory reference insts executed -system.cpu3.iew.exec_branches 41928 # Number of branches executed -system.cpu3.iew.exec_stores 29146 # Number of stores executed -system.cpu3.iew.exec_rate 1.249328 # Inst execution rate -system.cpu3.iew.wb_sent 200012 # cumulative count of insts sent to commit -system.cpu3.iew.wb_count 199715 # cumulative count of insts written-back -system.cpu3.iew.wb_producers 111117 # num instructions producing a value -system.cpu3.iew.wb_consumers 117670 # num instructions consuming a value +system.cpu3.iew.exec_nop 34395 # number of nop insts executed +system.cpu3.iew.exec_refs 99995 # number of memory reference insts executed +system.cpu3.iew.exec_branches 43728 # Number of branches executed +system.cpu3.iew.exec_stores 31474 # Number of stores executed +system.cpu3.iew.exec_rate 1.315601 # Inst execution rate +system.cpu3.iew.wb_sent 210248 # cumulative count of insts sent to commit +system.cpu3.iew.wb_count 209929 # cumulative count of insts written-back +system.cpu3.iew.wb_producers 117676 # num instructions producing a value +system.cpu3.iew.wb_consumers 124324 # num instructions consuming a value system.cpu3.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu3.iew.wb_rate 1.245735 # insts written-back per cycle -system.cpu3.iew.wb_fanout 0.944310 # average fanout of values written-back +system.cpu3.iew.wb_rate 1.311802 # insts written-back per cycle +system.cpu3.iew.wb_fanout 0.946527 # average fanout of values written-back system.cpu3.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu3.commit.commitSquashedInsts 14558 # The number of squashed insts skipped by commit -system.cpu3.commit.commitNonSpecStalls 7296 # The number of times commit has been forced to stall to communicate backwards -system.cpu3.commit.branchMispredicts 1305 # The number of times a branch was mispredicted -system.cpu3.commit.committed_per_cycle::samples 156559 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::mean 1.434092 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::stdev 1.973064 # Number of insts commited each cycle +system.cpu3.commit.commitSquashedInsts 14613 # The number of squashed insts skipped by commit +system.cpu3.commit.commitNonSpecStalls 6808 # The number of times commit has been forced to stall to communicate backwards +system.cpu3.commit.branchMispredicts 1279 # The number of times a branch was mispredicted +system.cpu3.commit.committed_per_cycle::samples 156309 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::mean 1.512638 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::stdev 2.007092 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::0 75373 48.14% 48.14% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::1 38673 24.70% 72.85% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::2 5214 3.33% 76.18% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::3 8076 5.16% 81.33% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::4 1539 0.98% 82.32% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::5 24642 15.74% 98.06% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::6 775 0.50% 98.55% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::7 961 0.61% 99.17% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::8 1306 0.83% 100.00% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::0 71539 45.77% 45.77% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::1 40455 25.88% 71.65% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::2 5161 3.30% 74.95% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::3 7618 4.87% 79.82% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::4 1540 0.99% 80.81% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::5 26903 17.21% 98.02% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::6 829 0.53% 98.55% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::7 953 0.61% 99.16% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::8 1311 0.84% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::total 156559 # Number of insts commited each cycle -system.cpu3.commit.committedInsts 224520 # Number of instructions committed -system.cpu3.commit.committedOps 224520 # Number of ops (including micro ops) committed +system.cpu3.commit.committed_per_cycle::total 156309 # Number of insts commited each cycle +system.cpu3.commit.committedInsts 236439 # Number of instructions committed +system.cpu3.commit.committedOps 236439 # Number of ops (including micro ops) committed system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu3.commit.refs 91055 # Number of memory references committed -system.cpu3.commit.loads 62716 # Number of loads committed -system.cpu3.commit.membars 6575 # Number of memory barriers committed -system.cpu3.commit.branches 40877 # Number of branches committed +system.cpu3.commit.refs 97502 # Number of memory references committed +system.cpu3.commit.loads 66856 # Number of loads committed +system.cpu3.commit.membars 6091 # Number of memory barriers committed +system.cpu3.commit.branches 42698 # Number of branches committed system.cpu3.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu3.commit.int_insts 154046 # Number of committed integer instructions. +system.cpu3.commit.int_insts 162319 # Number of committed integer instructions. system.cpu3.commit.function_calls 322 # Number of function calls committed. -system.cpu3.commit.op_class_0::No_OpClass 31660 14.10% 14.10% # Class of committed instruction -system.cpu3.commit.op_class_0::IntAlu 95230 42.41% 56.52% # Class of committed instruction -system.cpu3.commit.op_class_0::IntMult 0 0.00% 56.52% # Class of committed instruction -system.cpu3.commit.op_class_0::IntDiv 0 0.00% 56.52% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 56.52% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 56.52% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 56.52% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatMult 0 0.00% 56.52% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 56.52% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 56.52% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 56.52% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 56.52% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdAlu 0 0.00% 56.52% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdCmp 0 0.00% 56.52% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdCvt 0 0.00% 56.52% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdMisc 0 0.00% 56.52% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdMult 0 0.00% 56.52% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 56.52% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdShift 0 0.00% 56.52% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 56.52% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 56.52% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 56.52% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 56.52% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 56.52% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 56.52% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 56.52% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatMisc 0 0.00% 56.52% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 56.52% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 56.52% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 56.52% # Class of committed instruction -system.cpu3.commit.op_class_0::MemRead 69291 30.86% 87.38% # Class of committed instruction -system.cpu3.commit.op_class_0::MemWrite 28339 12.62% 100.00% # Class of committed instruction +system.cpu3.commit.op_class_0::No_OpClass 33485 14.16% 14.16% # Class of committed instruction +system.cpu3.commit.op_class_0::IntAlu 99361 42.02% 56.19% # Class of committed instruction +system.cpu3.commit.op_class_0::IntMult 0 0.00% 56.19% # Class of committed instruction +system.cpu3.commit.op_class_0::IntDiv 0 0.00% 56.19% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 56.19% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 56.19% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 56.19% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatMult 0 0.00% 56.19% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 56.19% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 56.19% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 56.19% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 56.19% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdAlu 0 0.00% 56.19% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdCmp 0 0.00% 56.19% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdCvt 0 0.00% 56.19% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdMisc 0 0.00% 56.19% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdMult 0 0.00% 56.19% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 56.19% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdShift 0 0.00% 56.19% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 56.19% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 56.19% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 56.19% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 56.19% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 56.19% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 56.19% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 56.19% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMisc 0 0.00% 56.19% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 56.19% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 56.19% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 56.19% # Class of committed instruction +system.cpu3.commit.op_class_0::MemRead 72947 30.85% 87.04% # Class of committed instruction +system.cpu3.commit.op_class_0::MemWrite 30646 12.96% 100.00% # Class of committed instruction system.cpu3.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu3.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu3.commit.op_class_0::total 224520 # Class of committed instruction -system.cpu3.commit.bw_lim_events 1306 # number cycles where commit BW limit reached +system.cpu3.commit.op_class_0::total 236439 # Class of committed instruction +system.cpu3.commit.bw_lim_events 1311 # number cycles where commit BW limit reached system.cpu3.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu3.rob.rob_reads 393745 # The number of ROB reads -system.cpu3.rob.rob_writes 480811 # The number of ROB writes -system.cpu3.timesIdled 204 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu3.idleCycles 1106 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu3.quiesceCycles 44020 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu3.committedInsts 186285 # Number of Instructions Simulated -system.cpu3.committedOps 186285 # Number of Ops (including micro ops) Simulated -system.cpu3.cpi 0.860611 # CPI: Cycles Per Instruction -system.cpu3.cpi_total 0.860611 # CPI: Total CPI of All Threads -system.cpu3.ipc 1.161965 # IPC: Instructions Per Cycle -system.cpu3.ipc_total 1.161965 # IPC: Total IPC of All Threads -system.cpu3.int_regfile_reads 340113 # number of integer regfile reads -system.cpu3.int_regfile_writes 159981 # number of integer regfile writes +system.cpu3.rob.rob_reads 405464 # The number of ROB reads +system.cpu3.rob.rob_writes 504751 # The number of ROB writes +system.cpu3.timesIdled 203 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu3.idleCycles 1075 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu3.quiesceCycles 43988 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu3.committedInsts 196863 # Number of Instructions Simulated +system.cpu3.committedOps 196863 # Number of Ops (including micro ops) Simulated +system.cpu3.cpi 0.812905 # CPI: Cycles Per Instruction +system.cpu3.cpi_total 0.812905 # CPI: Total CPI of All Threads +system.cpu3.ipc 1.230155 # IPC: Instructions Per Cycle +system.cpu3.ipc_total 1.230155 # IPC: Total IPC of All Threads +system.cpu3.int_regfile_reads 359772 # number of integer regfile reads +system.cpu3.int_regfile_writes 168916 # number of integer regfile writes system.cpu3.fp_regfile_writes 64 # number of floating regfile writes -system.cpu3.misc_regfile_reads 95078 # number of misc regfile reads +system.cpu3.misc_regfile_reads 101608 # number of misc regfile reads system.cpu3.misc_regfile_writes 648 # number of misc regfile writes -system.cpu3.icache.tags.replacements 386 # number of replacements -system.cpu3.icache.tags.tagsinuse 77.771025 # Cycle average of tags in use -system.cpu3.icache.tags.total_refs 24411 # Total number of references to valid blocks. -system.cpu3.icache.tags.sampled_refs 499 # Sample count of references to valid blocks. -system.cpu3.icache.tags.avg_refs 48.919840 # Average number of references to valid blocks. -system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.icache.tags.occ_blocks::cpu3.inst 77.771025 # Average occupied blocks per requestor -system.cpu3.icache.tags.occ_percent::cpu3.inst 0.151897 # Average percentage of cache occupancy -system.cpu3.icache.tags.occ_percent::total 0.151897 # Average percentage of cache occupancy -system.cpu3.icache.tags.occ_task_id_blocks::1024 113 # Occupied blocks per task id -system.cpu3.icache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id -system.cpu3.icache.tags.age_task_id_blocks_1024::1 102 # Occupied blocks per task id -system.cpu3.icache.tags.occ_task_id_percent::1024 0.220703 # Percentage of cache occupancy per task id -system.cpu3.icache.tags.tag_accesses 25471 # Number of tag accesses -system.cpu3.icache.tags.data_accesses 25471 # Number of data accesses -system.cpu3.icache.ReadReq_hits::cpu3.inst 24411 # number of ReadReq hits -system.cpu3.icache.ReadReq_hits::total 24411 # number of ReadReq hits -system.cpu3.icache.demand_hits::cpu3.inst 24411 # number of demand (read+write) hits -system.cpu3.icache.demand_hits::total 24411 # number of demand (read+write) hits -system.cpu3.icache.overall_hits::cpu3.inst 24411 # number of overall hits -system.cpu3.icache.overall_hits::total 24411 # number of overall hits -system.cpu3.icache.ReadReq_misses::cpu3.inst 561 # number of ReadReq misses -system.cpu3.icache.ReadReq_misses::total 561 # number of ReadReq misses -system.cpu3.icache.demand_misses::cpu3.inst 561 # number of demand (read+write) misses -system.cpu3.icache.demand_misses::total 561 # number of demand (read+write) misses -system.cpu3.icache.overall_misses::cpu3.inst 561 # number of overall misses -system.cpu3.icache.overall_misses::total 561 # number of overall misses -system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 7400997 # number of ReadReq miss cycles -system.cpu3.icache.ReadReq_miss_latency::total 7400997 # number of ReadReq miss cycles -system.cpu3.icache.demand_miss_latency::cpu3.inst 7400997 # number of demand (read+write) miss cycles -system.cpu3.icache.demand_miss_latency::total 7400997 # number of demand (read+write) miss cycles -system.cpu3.icache.overall_miss_latency::cpu3.inst 7400997 # number of overall miss cycles -system.cpu3.icache.overall_miss_latency::total 7400997 # number of overall miss cycles -system.cpu3.icache.ReadReq_accesses::cpu3.inst 24972 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.ReadReq_accesses::total 24972 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.demand_accesses::cpu3.inst 24972 # number of demand (read+write) accesses -system.cpu3.icache.demand_accesses::total 24972 # number of demand (read+write) accesses -system.cpu3.icache.overall_accesses::cpu3.inst 24972 # number of overall (read+write) accesses -system.cpu3.icache.overall_accesses::total 24972 # number of overall (read+write) accesses -system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.022465 # miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_miss_rate::total 0.022465 # miss rate for ReadReq accesses -system.cpu3.icache.demand_miss_rate::cpu3.inst 0.022465 # miss rate for demand accesses -system.cpu3.icache.demand_miss_rate::total 0.022465 # miss rate for demand accesses -system.cpu3.icache.overall_miss_rate::cpu3.inst 0.022465 # miss rate for overall accesses -system.cpu3.icache.overall_miss_rate::total 0.022465 # miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 13192.508021 # average ReadReq miss latency -system.cpu3.icache.ReadReq_avg_miss_latency::total 13192.508021 # average ReadReq miss latency -system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 13192.508021 # average overall miss latency -system.cpu3.icache.demand_avg_miss_latency::total 13192.508021 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13192.508021 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::total 13192.508021 # average overall miss latency -system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu3.icache.fast_writes 0 # number of fast writes performed -system.cpu3.icache.cache_copies 0 # number of cache copies performed -system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst 62 # number of ReadReq MSHR hits -system.cpu3.icache.ReadReq_mshr_hits::total 62 # number of ReadReq MSHR hits -system.cpu3.icache.demand_mshr_hits::cpu3.inst 62 # number of demand (read+write) MSHR hits -system.cpu3.icache.demand_mshr_hits::total 62 # number of demand (read+write) MSHR hits -system.cpu3.icache.overall_mshr_hits::cpu3.inst 62 # number of overall MSHR hits -system.cpu3.icache.overall_mshr_hits::total 62 # number of overall MSHR hits -system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 499 # number of ReadReq MSHR misses -system.cpu3.icache.ReadReq_mshr_misses::total 499 # number of ReadReq MSHR misses -system.cpu3.icache.demand_mshr_misses::cpu3.inst 499 # number of demand (read+write) MSHR misses -system.cpu3.icache.demand_mshr_misses::total 499 # number of demand (read+write) MSHR misses -system.cpu3.icache.overall_mshr_misses::cpu3.inst 499 # number of overall MSHR misses -system.cpu3.icache.overall_mshr_misses::total 499 # number of overall MSHR misses -system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 5888752 # number of ReadReq MSHR miss cycles -system.cpu3.icache.ReadReq_mshr_miss_latency::total 5888752 # number of ReadReq MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 5888752 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_latency::total 5888752 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 5888752 # number of overall MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_latency::total 5888752 # number of overall MSHR miss cycles -system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.019982 # mshr miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.019982 # mshr miss rate for ReadReq accesses -system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.019982 # mshr miss rate for demand accesses -system.cpu3.icache.demand_mshr_miss_rate::total 0.019982 # mshr miss rate for demand accesses -system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.019982 # mshr miss rate for overall accesses -system.cpu3.icache.overall_mshr_miss_rate::total 0.019982 # mshr miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 11801.106212 # average ReadReq mshr miss latency -system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 11801.106212 # average ReadReq mshr miss latency -system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 11801.106212 # average overall mshr miss latency -system.cpu3.icache.demand_avg_mshr_miss_latency::total 11801.106212 # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 11801.106212 # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency::total 11801.106212 # average overall mshr miss latency -system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu3.dcache.tags.replacements 0 # number of replacements -system.cpu3.dcache.tags.tagsinuse 23.453129 # Cycle average of tags in use -system.cpu3.dcache.tags.total_refs 34358 # Total number of references to valid blocks. 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WriteReq hits -system.cpu3.dcache.WriteReq_hits::total 28128 # number of WriteReq hits -system.cpu3.dcache.SwapReq_hits::cpu3.data 13 # number of SwapReq hits -system.cpu3.dcache.SwapReq_hits::total 13 # number of SwapReq hits -system.cpu3.dcache.demand_hits::cpu3.data 67411 # number of demand (read+write) hits -system.cpu3.dcache.demand_hits::total 67411 # number of demand (read+write) hits -system.cpu3.dcache.overall_hits::cpu3.data 67411 # number of overall hits -system.cpu3.dcache.overall_hits::total 67411 # number of overall hits -system.cpu3.dcache.ReadReq_misses::cpu3.data 435 # number of ReadReq misses -system.cpu3.dcache.ReadReq_misses::total 435 # number of ReadReq misses -system.cpu3.dcache.WriteReq_misses::cpu3.data 136 # number of WriteReq misses -system.cpu3.dcache.WriteReq_misses::total 136 # number of WriteReq misses -system.cpu3.dcache.SwapReq_misses::cpu3.data 62 # number of SwapReq misses -system.cpu3.dcache.SwapReq_misses::total 62 # number of SwapReq misses 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-system.cpu3.dcache.demand_miss_latency::total 8525011 # number of demand (read+write) miss cycles -system.cpu3.dcache.overall_miss_latency::cpu3.data 8525011 # number of overall miss cycles -system.cpu3.dcache.overall_miss_latency::total 8525011 # number of overall miss cycles -system.cpu3.dcache.ReadReq_accesses::cpu3.data 39718 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.ReadReq_accesses::total 39718 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_accesses::cpu3.data 28264 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_accesses::total 28264 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.SwapReq_accesses::cpu3.data 75 # number of SwapReq accesses(hits+misses) -system.cpu3.dcache.SwapReq_accesses::total 75 # number of SwapReq accesses(hits+misses) -system.cpu3.dcache.demand_accesses::cpu3.data 67982 # number of demand (read+write) accesses -system.cpu3.dcache.demand_accesses::total 67982 # number of demand (read+write) accesses -system.cpu3.dcache.overall_accesses::cpu3.data 67982 # number of overall (read+write) accesses -system.cpu3.dcache.overall_accesses::total 67982 # number of overall (read+write) accesses -system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.010952 # miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_miss_rate::total 0.010952 # miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.004812 # miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_miss_rate::total 0.004812 # miss rate for WriteReq accesses -system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.826667 # miss rate for SwapReq accesses -system.cpu3.dcache.SwapReq_miss_rate::total 0.826667 # miss rate for SwapReq accesses -system.cpu3.dcache.demand_miss_rate::cpu3.data 0.008399 # miss rate for demand accesses -system.cpu3.dcache.demand_miss_rate::total 0.008399 # miss rate for demand accesses -system.cpu3.dcache.overall_miss_rate::cpu3.data 0.008399 # miss rate for overall accesses -system.cpu3.dcache.overall_miss_rate::total 0.008399 # miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 13280.457471 # average ReadReq miss latency -system.cpu3.dcache.ReadReq_avg_miss_latency::total 13280.457471 # average ReadReq miss latency -system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 20205.970588 # average WriteReq miss latency -system.cpu3.dcache.WriteReq_avg_miss_latency::total 20205.970588 # average WriteReq miss latency -system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 8782.387097 # average SwapReq miss latency -system.cpu3.dcache.SwapReq_avg_miss_latency::total 8782.387097 # average SwapReq miss latency -system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 14929.966725 # average overall miss latency -system.cpu3.dcache.demand_avg_miss_latency::total 14929.966725 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 14929.966725 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency::total 14929.966725 # average overall miss latency +system.cpu3.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id +system.cpu3.dcache.tags.tag_accesses 289352 # Number of tag accesses +system.cpu3.dcache.tags.data_accesses 289352 # Number of data accesses +system.cpu3.dcache.ReadReq_hits::cpu3.data 41209 # number of ReadReq hits +system.cpu3.dcache.ReadReq_hits::total 41209 # number of ReadReq hits +system.cpu3.dcache.WriteReq_hits::cpu3.data 30434 # number of WriteReq hits +system.cpu3.dcache.WriteReq_hits::total 30434 # number of WriteReq hits +system.cpu3.dcache.SwapReq_hits::cpu3.data 14 # number of SwapReq hits +system.cpu3.dcache.SwapReq_hits::total 14 # number of SwapReq hits +system.cpu3.dcache.demand_hits::cpu3.data 71643 # number of demand (read+write) hits +system.cpu3.dcache.demand_hits::total 71643 # number of demand (read+write) hits +system.cpu3.dcache.overall_hits::cpu3.data 71643 # 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accesses(hits+misses) +system.cpu3.dcache.WriteReq_accesses::cpu3.data 30575 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_accesses::total 30575 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.SwapReq_accesses::cpu3.data 71 # number of SwapReq accesses(hits+misses) +system.cpu3.dcache.SwapReq_accesses::total 71 # number of SwapReq accesses(hits+misses) +system.cpu3.dcache.demand_accesses::cpu3.data 72203 # number of demand (read+write) accesses +system.cpu3.dcache.demand_accesses::total 72203 # number of demand (read+write) accesses +system.cpu3.dcache.overall_accesses::cpu3.data 72203 # number of overall (read+write) accesses +system.cpu3.dcache.overall_accesses::total 72203 # number of overall (read+write) accesses +system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.010065 # miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_miss_rate::total 0.010065 # miss rate for ReadReq accesses +system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.004612 # miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_miss_rate::total 0.004612 # miss rate for WriteReq accesses +system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.802817 # miss rate for SwapReq accesses +system.cpu3.dcache.SwapReq_miss_rate::total 0.802817 # miss rate for SwapReq accesses +system.cpu3.dcache.demand_miss_rate::cpu3.data 0.007756 # miss rate for demand accesses +system.cpu3.dcache.demand_miss_rate::total 0.007756 # miss rate for demand accesses +system.cpu3.dcache.overall_miss_rate::cpu3.data 0.007756 # miss rate for overall accesses +system.cpu3.dcache.overall_miss_rate::total 0.007756 # miss rate for overall accesses +system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 12879.563246 # average ReadReq miss latency +system.cpu3.dcache.ReadReq_avg_miss_latency::total 12879.563246 # average ReadReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 19739.446809 # average WriteReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::total 19739.446809 # average WriteReq miss latency +system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 8438.684211 # average SwapReq miss latency +system.cpu3.dcache.SwapReq_avg_miss_latency::total 8438.684211 # average SwapReq miss latency +system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 14606.783929 # average overall miss latency +system.cpu3.dcache.demand_avg_miss_latency::total 14606.783929 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 14606.783929 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::total 14606.783929 # average overall miss latency system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -2811,54 +2228,642 @@ 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12263.906542 # average WriteReq mshr miss latency +system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 6438.508772 # average SwapReq mshr miss latency +system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 6438.508772 # average SwapReq mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 8954.153558 # average overall mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency::total 8954.153558 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 8954.153558 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency::total 8954.153558 # average overall mshr miss latency system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu3.icache.tags.replacements 386 # number of replacements +system.cpu3.icache.tags.tagsinuse 78.630086 # Cycle average of tags in use +system.cpu3.icache.tags.total_refs 23274 # Total number of references to valid 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ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.884615 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.962963 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.591133 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.971098 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.024096 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.541667 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.155102 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.data 0.800000 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.inst 0.006061 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.data 0.541667 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.284431 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.591133 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.971098 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.024096 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.541667 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.155102 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.800000 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.inst 0.006061 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.data 0.541667 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.284431 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 56500 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 67689.189189 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 58437.500000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 62500 # average ReadReq mshr miss latency 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+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 61292.553191 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 57250 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 68326.923077 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 58395.833333 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 61354.961832 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 56500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 64110.119048 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 58437.500000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 57653.846154 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 59723.684211 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 66225 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 130083.333333 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.data 58711.538462 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 59516.165414 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 56500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 64110.119048 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 58437.500000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 57653.846154 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 59723.684211 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 66225 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 130083.333333 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.data 58711.538462 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 59516.165414 # average overall mshr miss latency +system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate +system.membus.trans_dist::ReadReq 534 # Transaction distribution +system.membus.trans_dist::ReadResp 533 # Transaction distribution +system.membus.trans_dist::UpgradeReq 274 # Transaction distribution +system.membus.trans_dist::UpgradeResp 78 # Transaction distribution +system.membus.trans_dist::ReadExReq 179 # Transaction distribution +system.membus.trans_dist::ReadExResp 131 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1729 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1729 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 42496 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 42496 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 244 # Total snoops (count) +system.membus.snoop_fanout::samples 987 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 987 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 987 # Request fanout histogram +system.membus.reqLayer0.occupancy 933500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.9 # Layer utilization (%) +system.membus.respLayer1.occupancy 6348672 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 6.0 # Layer utilization (%) +system.toL2Bus.trans_dist::ReadReq 2754 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2753 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 1 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 277 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 277 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 411 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 411 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1217 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 584 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 996 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 362 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 980 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 367 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 990 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 365 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 5861 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 38912 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 11136 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 31872 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1536 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 31360 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 31680 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 1536 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 149632 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 1023 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 3443 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 7 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::5 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::6 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::7 3443 100.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::min_value 7 # Request fanout histogram +system.toL2Bus.snoop_fanout::max_value 7 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 3443 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 1734981 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 1.6 # Layer utilization (%) +system.toL2Bus.respLayer0.occupancy 2800749 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 2.7 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 1466512 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%) +system.toL2Bus.respLayer2.occupancy 2243496 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.utilization 2.1 # Layer utilization (%) +system.toL2Bus.respLayer3.occupancy 1172003 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.utilization 1.1 # Layer utilization (%) +system.toL2Bus.respLayer4.occupancy 2220994 # Layer occupancy (ticks) +system.toL2Bus.respLayer4.utilization 2.1 # Layer utilization (%) +system.toL2Bus.respLayer5.occupancy 1183494 # Layer occupancy (ticks) +system.toL2Bus.respLayer5.utilization 1.1 # Layer utilization (%) +system.toL2Bus.respLayer6.occupancy 2229247 # Layer occupancy (ticks) +system.toL2Bus.respLayer6.utilization 2.1 # Layer utilization (%) +system.toL2Bus.respLayer7.occupancy 1196246 # Layer occupancy (ticks) +system.toL2Bus.respLayer7.utilization 1.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/stats.txt index 427faaaab..8156a1abf 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/stats.txt +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/stats.txt @@ -1,48 +1,48 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.010189 # Number of seconds simulated -sim_ticks 10189338 # Number of ticks simulated -final_tick 10189338 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.010101 # Number of seconds simulated +sim_ticks 10100518 # Number of ticks simulated +final_tick 10100518 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 78610 # Simulator tick rate (ticks/s) -host_mem_usage 651260 # Number of bytes of host memory used -host_seconds 129.62 # Real time elapsed on the host +host_tick_rate 129349 # Simulator tick rate (ticks/s) +host_mem_usage 663928 # Number of bytes of host memory used +host_seconds 78.09 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks -system.mem_ctrls.bytes_read::ruby.dir_cntrl0 39524800 # Number of bytes read from this memory -system.mem_ctrls.bytes_read::total 39524800 # Number of bytes read from this memory -system.mem_ctrls.bytes_written::ruby.dir_cntrl0 14139200 # Number of bytes written to this memory -system.mem_ctrls.bytes_written::total 14139200 # Number of bytes written to this memory -system.mem_ctrls.num_reads::ruby.dir_cntrl0 617575 # Number of read requests responded to by this memory -system.mem_ctrls.num_reads::total 617575 # Number of read requests responded to by this memory -system.mem_ctrls.num_writes::ruby.dir_cntrl0 220925 # Number of write requests responded to by this memory -system.mem_ctrls.num_writes::total 220925 # Number of write requests responded to by this memory -system.mem_ctrls.bw_read::ruby.dir_cntrl0 3879035125 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_read::total 3879035125 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::ruby.dir_cntrl0 1387646577 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::total 1387646577 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_total::ruby.dir_cntrl0 5266681702 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.bw_total::total 5266681702 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.readReqs 617577 # Number of read requests accepted -system.mem_ctrls.writeReqs 220925 # Number of write requests accepted -system.mem_ctrls.readBursts 617577 # Number of DRAM read bursts, including those serviced by the write queue -system.mem_ctrls.writeBursts 220925 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrls.bytesReadDRAM 39138176 # Total number of bytes read from DRAM -system.mem_ctrls.bytesReadWrQ 386752 # Total number of bytes read from write queue -system.mem_ctrls.bytesWritten 14013696 # Total number of bytes written to DRAM -system.mem_ctrls.bytesReadSys 39524928 # Total read bytes from the system interface side -system.mem_ctrls.bytesWrittenSys 14139200 # Total written bytes from the system interface side -system.mem_ctrls.servicedByWrQ 6043 # Number of DRAM read bursts serviced by the write queue -system.mem_ctrls.mergedWrBursts 1932 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.bytes_read::ruby.dir_cntrl0 39550848 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 39550848 # Number of bytes read from this memory +system.mem_ctrls.bytes_written::ruby.dir_cntrl0 14145024 # Number of bytes written to this memory +system.mem_ctrls.bytes_written::total 14145024 # Number of bytes written to this memory +system.mem_ctrls.num_reads::ruby.dir_cntrl0 617982 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 617982 # Number of read requests responded to by this memory +system.mem_ctrls.num_writes::ruby.dir_cntrl0 221016 # Number of write requests responded to by this memory +system.mem_ctrls.num_writes::total 221016 # Number of write requests responded to by this memory +system.mem_ctrls.bw_read::ruby.dir_cntrl0 3915724718 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 3915724718 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::ruby.dir_cntrl0 1400425602 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::total 1400425602 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::ruby.dir_cntrl0 5316150320 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 5316150320 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.readReqs 617983 # Number of read requests accepted +system.mem_ctrls.writeReqs 221016 # Number of write requests accepted +system.mem_ctrls.readBursts 617983 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.writeBursts 221016 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrls.bytesReadDRAM 39163072 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 387840 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 14016640 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadSys 39550912 # Total read bytes from the system interface side +system.mem_ctrls.bytesWrittenSys 14145024 # Total written bytes from the system interface side +system.mem_ctrls.servicedByWrQ 6060 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 1978 # Number of DRAM write bursts merged with an existing one system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.mem_ctrls.perBankRdBursts::0 76538 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::1 76571 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::2 76714 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::3 76079 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::4 76086 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::5 76610 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::6 76532 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::7 76404 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::0 76629 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::1 76171 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::2 76824 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 76474 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 76756 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::5 76802 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::6 76225 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 76042 # Per bank write bursts system.mem_ctrls.perBankRdBursts::8 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::9 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::10 0 # Per bank write bursts @@ -51,14 +51,14 @@ system.mem_ctrls.perBankRdBursts::12 0 # Pe system.mem_ctrls.perBankRdBursts::13 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::14 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::15 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::0 27378 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::1 27423 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::2 27424 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::3 27014 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::4 27346 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::5 27635 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::6 27364 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::7 27380 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 27421 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::1 27227 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::2 27422 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 27319 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 27412 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 27477 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::6 27095 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::7 27637 # Per bank write bursts system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::10 0 # Per bank write bursts @@ -69,29 +69,29 @@ system.mem_ctrls.perBankWrBursts::14 0 # Pe system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrls.totGap 10189309 # Total gap between requests +system.mem_ctrls.totGap 10100475 # Total gap between requests system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::6 617577 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 617983 # Read request sizes (log2) system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::6 220925 # Write request sizes (log2) -system.mem_ctrls.rdQLenPdf::0 33272 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::1 65829 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::2 105799 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::3 135981 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::4 124559 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::5 85542 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::6 44255 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::7 16297 # What read queue length does an incoming req see +system.mem_ctrls.writePktSize::6 221016 # Write request sizes (log2) +system.mem_ctrls.rdQLenPdf::0 34398 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::1 67691 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::2 107083 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::3 135966 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::4 123386 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::5 83518 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::6 43655 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::7 16226 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see @@ -131,32 +131,32 @@ system.mem_ctrls.wrQLenPdf::11 1 # Wh system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::15 30 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::16 83 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::17 1662 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::18 5307 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::19 9467 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::20 12599 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::21 14395 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::22 15324 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::23 15907 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::24 16029 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::25 15907 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::26 15548 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::27 15075 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::28 14795 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::29 14747 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::30 14706 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::31 14783 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::32 15249 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::33 4255 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::34 1854 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::35 778 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::36 292 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::37 114 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::38 50 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::39 17 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::40 5 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::15 36 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::16 118 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::17 1783 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::18 5370 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::19 9528 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::20 12721 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::21 14465 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::22 15565 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::23 15821 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::24 16096 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::25 15783 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::26 15412 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::27 15030 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::28 14722 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::29 14673 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::30 14636 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::31 14779 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::32 15223 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::33 4310 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::34 1845 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::35 727 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::36 255 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::37 87 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::38 26 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::39 12 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see @@ -180,205 +180,174 @@ system.mem_ctrls.wrQLenPdf::60 0 # Wh system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrls.bytesPerActivate::samples 331991 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::mean 160.098220 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::gmean 126.076476 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::stdev 125.468332 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::0-127 134789 40.60% 40.60% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::128-255 125458 37.79% 78.39% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::256-383 44451 13.39% 91.78% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::384-511 17342 5.22% 97.00% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::512-639 6423 1.93% 98.94% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::640-767 2310 0.70% 99.63% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::768-895 840 0.25% 99.89% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::896-1023 257 0.08% 99.96% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::1024-1151 121 0.04% 100.00% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::total 331991 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::samples 332523 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 159.925611 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 125.830358 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 125.889032 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 135463 40.74% 40.74% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 125752 37.82% 78.56% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 43770 13.16% 91.72% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 17448 5.25% 96.97% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 6543 1.97% 98.93% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 2325 0.70% 99.63% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 803 0.24% 99.87% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 286 0.09% 99.96% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 133 0.04% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 332523 # Bytes accessed per row activation system.mem_ctrls.rdPerTurnAround::samples 13671 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::mean 44.729574 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::gmean 43.698245 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::stdev 9.605843 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::12-15 1 0.01% 0.01% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::16-19 10 0.07% 0.08% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::20-23 59 0.43% 0.51% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::24-27 247 1.81% 2.32% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::28-31 645 4.72% 7.04% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::32-35 1323 9.68% 16.71% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::36-39 1874 13.71% 30.42% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::40-43 2328 17.03% 47.45% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::44-47 2269 16.60% 64.05% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::48-51 1834 13.42% 77.46% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::52-55 1248 9.13% 86.59% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::56-59 853 6.24% 92.83% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::60-63 491 3.59% 96.42% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::64-67 271 1.98% 98.41% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::68-71 125 0.91% 99.32% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::72-75 48 0.35% 99.67% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::76-79 28 0.20% 99.88% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::80-83 10 0.07% 99.95% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::84-87 4 0.03% 99.98% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::88-91 2 0.01% 99.99% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::mean 44.758833 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::gmean 43.734391 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::stdev 9.598616 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::16-19 10 0.07% 0.07% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::20-23 51 0.37% 0.45% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::24-27 237 1.73% 2.18% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::28-31 592 4.33% 6.51% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::32-35 1395 10.20% 16.71% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::36-39 1956 14.31% 31.02% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::40-43 2298 16.81% 47.83% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::44-47 2196 16.06% 63.89% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::48-51 1787 13.07% 76.97% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::52-55 1319 9.65% 86.61% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::56-59 876 6.41% 93.02% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::60-63 474 3.47% 96.49% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::64-67 243 1.78% 98.27% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::68-71 135 0.99% 99.25% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::72-75 62 0.45% 99.71% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::76-79 22 0.16% 99.87% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::80-83 13 0.10% 99.96% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::84-87 3 0.02% 99.99% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::92-95 1 0.01% 99.99% # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::104-107 1 0.01% 100.00% # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::total 13671 # Reads before turning the bus around for writes system.mem_ctrls.wrPerTurnAround::samples 13671 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::mean 16.016678 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::gmean 16.015501 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::stdev 0.206017 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::16 13555 99.15% 99.15% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::17 48 0.35% 99.50% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::18 43 0.31% 99.82% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::19 9 0.07% 99.88% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::20 13 0.10% 99.98% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::21 3 0.02% 100.00% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::mean 16.020042 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::gmean 16.018590 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::stdev 0.229581 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::16 13535 99.01% 99.01% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::17 53 0.39% 99.39% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::18 50 0.37% 99.76% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::19 20 0.15% 99.90% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::20 6 0.04% 99.95% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::21 5 0.04% 99.99% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::22 2 0.01% 100.00% # Writes before turning the bus around for reads system.mem_ctrls.wrPerTurnAround::total 13671 # Writes before turning the bus around for reads -system.mem_ctrls.totQLat 29899696 # Total ticks spent queuing -system.mem_ctrls.totMemAccLat 41518842 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrls.totBusLat 3057670 # Total ticks spent in databus transfers -system.mem_ctrls.avgQLat 48.89 # Average queueing delay per DRAM burst +system.mem_ctrls.totQLat 28940521 # Total ticks spent queuing +system.mem_ctrls.totMemAccLat 40567058 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.totBusLat 3059615 # Total ticks spent in databus transfers +system.mem_ctrls.avgQLat 47.29 # Average queueing delay per DRAM burst system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst -system.mem_ctrls.avgMemAccLat 67.89 # Average memory access latency per DRAM burst -system.mem_ctrls.avgRdBW 3841.09 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrls.avgWrBW 1375.33 # Average achieved write bandwidth in MiByte/s -system.mem_ctrls.avgRdBWSys 3879.05 # Average system read bandwidth in MiByte/s -system.mem_ctrls.avgWrBWSys 1387.65 # Average system write bandwidth in MiByte/s +system.mem_ctrls.avgMemAccLat 66.29 # Average memory access latency per DRAM burst +system.mem_ctrls.avgRdBW 3877.33 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 1387.71 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 3915.73 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 1400.43 # Average system write bandwidth in MiByte/s system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrls.busUtil 40.75 # Data bus utilization in percentage -system.mem_ctrls.busUtilRead 30.01 # Data bus utilization in percentage for reads -system.mem_ctrls.busUtilWrite 10.74 # Data bus utilization in percentage for writes -system.mem_ctrls.avgRdQLen 5.53 # Average read queue length when enqueuing -system.mem_ctrls.avgWrQLen 26.44 # Average write queue length when enqueuing -system.mem_ctrls.readRowHits 285563 # Number of row buffer hits during reads -system.mem_ctrls.writeRowHits 212936 # Number of row buffer hits during writes -system.mem_ctrls.readRowHitRate 46.70 # Row buffer hit rate for reads -system.mem_ctrls.writeRowHitRate 97.23 # Row buffer hit rate for writes -system.mem_ctrls.avgGap 12.15 # Average gap between requests -system.mem_ctrls.pageHitRate 60.02 # Row buffer hit rate, read and write combined -system.mem_ctrls.memoryStateTime::IDLE 20 # Time in different power states -system.mem_ctrls.memoryStateTime::REF 340080 # Time in different power states -system.mem_ctrls.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls.memoryStateTime::ACT 9844307 # Time in different power states -system.mem_ctrls.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrls.actEnergy::0 2508483600 # Energy for activate commands per rank (pJ) -system.mem_ctrls.actEnergy::1 0 # Energy for activate commands per rank (pJ) -system.mem_ctrls.preEnergy::0 1393602000 # Energy for precharge commands per rank (pJ) -system.mem_ctrls.preEnergy::1 0 # Energy for precharge commands per rank (pJ) -system.mem_ctrls.readEnergy::0 7628000640 # Energy for read commands per rank (pJ) -system.mem_ctrls.readEnergy::1 0 # Energy for read commands per rank (pJ) -system.mem_ctrls.writeEnergy::0 2269057536 # Energy for write commands per rank (pJ) -system.mem_ctrls.writeEnergy::1 0 # Energy for write commands per rank (pJ) -system.mem_ctrls.refreshEnergy::0 665196480 # Energy for refresh commands per rank (pJ) -system.mem_ctrls.refreshEnergy::1 665196480 # Energy for refresh commands per rank (pJ) -system.mem_ctrls.actBackEnergy::0 6939209412 # Energy for active background per rank (pJ) -system.mem_ctrls.actBackEnergy::1 220089312 # Energy for active background per rank (pJ) -system.mem_ctrls.preBackEnergy::0 23610000 # Energy for precharge background per rank (pJ) -system.mem_ctrls.preBackEnergy::1 5917575000 # Energy for precharge background per rank (pJ) -system.mem_ctrls.totalEnergy::0 21427159668 # Total energy per rank (pJ) -system.mem_ctrls.totalEnergy::1 6802860792 # Total energy per rank (pJ) -system.mem_ctrls.averagePower::0 2103.921134 # Core power per rank (mW) -system.mem_ctrls.averagePower::1 667.969195 # Core power per rank (mW) +system.mem_ctrls.busUtil 41.13 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 30.29 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 10.84 # Data bus utilization in percentage for writes +system.mem_ctrls.avgRdQLen 5.49 # Average read queue length when enqueuing +system.mem_ctrls.avgWrQLen 26.46 # Average write queue length when enqueuing +system.mem_ctrls.readRowHits 285611 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 212791 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 46.67 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate 97.15 # Row buffer hit rate for writes +system.mem_ctrls.avgGap 12.04 # Average gap between requests +system.mem_ctrls.pageHitRate 59.98 # Row buffer hit rate, read and write combined +system.mem_ctrls_0.actEnergy 2513405160 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 1396336200 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 7635376320 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 2270198016 # Energy for write commands per rank (pJ) +system.mem_ctrls_0.refreshEnergy 659602320 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_0.actBackEnergy 6882629616 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 21843000 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.totalEnergy 21379390632 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 2117.037761 # Core power per rank (mW) +system.mem_ctrls_0.memoryStateTime::IDLE 20 # Time in different power states +system.mem_ctrls_0.memoryStateTime::REF 337220 # Time in different power states +system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 9761503 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls_1.actEnergy 0 # Energy for activate commands per rank (pJ) +system.mem_ctrls_1.preEnergy 0 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_1.readEnergy 0 # Energy for read commands per rank (pJ) +system.mem_ctrls_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls_1.refreshEnergy 659602320 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_1.actBackEnergy 218238408 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 5867775600 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.totalEnergy 6745616328 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 667.969575 # Core power per rank (mW) +system.mem_ctrls_1.memoryStateTime::IDLE 9761482 # Time in different power states +system.mem_ctrls_1.memoryStateTime::REF 337220 # Time in different power states +system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 0 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu_clk_domain.clock 1 # Clock period in ticks +system.cpu0.num_reads 98577 # number of read accesses completed +system.cpu0.num_writes 54699 # number of write accesses completed +system.cpu0.num_copies 0 # number of copy accesses completed +system.cpu1.num_reads 98994 # number of read accesses completed +system.cpu1.num_writes 54402 # number of write accesses completed +system.cpu1.num_copies 0 # number of copy accesses completed +system.cpu2.num_reads 99663 # number of read accesses completed +system.cpu2.num_writes 54801 # number of write accesses completed +system.cpu2.num_copies 0 # number of copy accesses completed +system.cpu3.num_reads 99192 # number of read accesses completed +system.cpu3.num_writes 55310 # number of write accesses completed +system.cpu3.num_copies 0 # number of copy accesses completed +system.cpu4.num_reads 100000 # number of read accesses completed +system.cpu4.num_writes 55358 # number of write accesses completed +system.cpu4.num_copies 0 # number of copy accesses completed +system.cpu5.num_reads 99170 # number of read accesses completed +system.cpu5.num_writes 54755 # number of write accesses completed +system.cpu5.num_copies 0 # number of copy accesses completed +system.cpu6.num_reads 99605 # number of read accesses completed +system.cpu6.num_writes 54887 # number of write accesses completed +system.cpu6.num_copies 0 # number of copy accesses completed +system.cpu7.num_reads 99434 # number of read accesses completed +system.cpu7.num_writes 55034 # number of write accesses completed +system.cpu7.num_copies 0 # number of copy accesses completed system.ruby.clk_domain.clock 1 # Clock period in ticks system.ruby.delayHist::bucket_size 2048 # delay histogram for all message system.ruby.delayHist::max_bucket 20479 # delay histogram for all message -system.ruby.delayHist::samples 4971489 # delay histogram for all message -system.ruby.delayHist::mean 205.679263 # delay histogram for all message -system.ruby.delayHist::stdev 591.280553 # delay histogram for all message -system.ruby.delayHist | 4825560 97.06% 97.06% | 138459 2.79% 99.85% | 7092 0.14% 99.99% | 343 0.01% 100.00% | 32 0.00% 100.00% | 1 0.00% 100.00% | 1 0.00% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message -system.ruby.delayHist::total 4971489 # delay histogram for all message +system.ruby.delayHist::samples 4971796 # delay histogram for all message +system.ruby.delayHist::mean 200.857627 # delay histogram for all message +system.ruby.delayHist::stdev 577.801677 # delay histogram for all message +system.ruby.delayHist | 4834086 97.23% 97.23% | 131198 2.64% 99.87% | 6246 0.13% 99.99% | 255 0.01% 100.00% | 8 0.00% 100.00% | 2 0.00% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message +system.ruby.delayHist::total 4971796 # delay histogram for all message system.ruby.outstanding_req_hist::bucket_size 2 system.ruby.outstanding_req_hist::max_bucket 19 -system.ruby.outstanding_req_hist::samples 623259 -system.ruby.outstanding_req_hist::mean 15.998457 -system.ruby.outstanding_req_hist::gmean 15.997185 -system.ruby.outstanding_req_hist::stdev 0.126163 -system.ruby.outstanding_req_hist | 8 0.00% 0.00% | 16 0.00% 0.00% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.02% | 18 0.00% 0.02% | 623137 99.98% 100.00% | 0 0.00% 100.00% -system.ruby.outstanding_req_hist::total 623259 +system.ruby.outstanding_req_hist::samples 623814 +system.ruby.outstanding_req_hist::mean 15.998459 +system.ruby.outstanding_req_hist::gmean 15.997190 +system.ruby.outstanding_req_hist::stdev 0.126101 +system.ruby.outstanding_req_hist | 8 0.00% 0.00% | 16 0.00% 0.00% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.02% | 17 0.00% 0.02% | 623693 99.98% 100.00% | 0 0.00% 100.00% +system.ruby.outstanding_req_hist::total 623814 system.ruby.latency_hist::bucket_size 1024 system.ruby.latency_hist::max_bucket 10239 -system.ruby.latency_hist::samples 623131 -system.ruby.latency_hist::mean 2092.761496 -system.ruby.latency_hist::gmean 1620.223776 -system.ruby.latency_hist::stdev 1225.208976 -system.ruby.latency_hist | 160408 25.74% 25.74% | 151701 24.34% 50.09% | 148772 23.87% 73.96% | 132419 21.25% 95.21% | 29415 4.72% 99.93% | 416 0.07% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.latency_hist::total 623131 +system.ruby.latency_hist::samples 623686 +system.ruby.latency_hist::mean 2072.612140 +system.ruby.latency_hist::gmean 1591.498940 +system.ruby.latency_hist::stdev 1226.963263 +system.ruby.latency_hist | 164804 26.42% 26.42% | 150821 24.18% 50.61% | 147979 23.73% 74.33% | 131724 21.12% 95.45% | 27974 4.49% 99.94% | 384 0.06% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.latency_hist::total 623686 system.ruby.hit_latency_hist::bucket_size 1 system.ruby.hit_latency_hist::max_bucket 9 -system.ruby.hit_latency_hist::samples 5 +system.ruby.hit_latency_hist::samples 9 system.ruby.hit_latency_hist::mean 3 system.ruby.hit_latency_hist::gmean 3.000000 -system.ruby.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 5 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.hit_latency_hist::total 5 +system.ruby.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 9 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.hit_latency_hist::total 9 system.ruby.miss_latency_hist::bucket_size 1024 system.ruby.miss_latency_hist::max_bucket 10239 -system.ruby.miss_latency_hist::samples 623126 -system.ruby.miss_latency_hist::mean 2092.778265 -system.ruby.miss_latency_hist::gmean 1620.305575 -system.ruby.miss_latency_hist::stdev 1225.199591 -system.ruby.miss_latency_hist | 160403 25.74% 25.74% | 151701 24.35% 50.09% | 148772 23.88% 73.96% | 132419 21.25% 95.21% | 29415 4.72% 99.93% | 416 0.07% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.miss_latency_hist::total 623126 -system.ruby.l1_cntrl4.L1Dcache.demand_hits 1 # Number of cache demand hits -system.ruby.l1_cntrl4.L1Dcache.demand_misses 77550 # Number of cache demand misses -system.ruby.l1_cntrl4.L1Dcache.demand_accesses 77551 # Number of cache demand accesses -system.ruby.l1_cntrl4.L1Icache.demand_hits 0 # Number of cache demand hits -system.ruby.l1_cntrl4.L1Icache.demand_misses 0 # Number of cache demand misses -system.ruby.l1_cntrl4.L1Icache.demand_accesses 0 # Number of cache demand accesses -system.cpu_clk_domain.clock 1 # Clock period in ticks -system.ruby.l1_cntrl4.prefetcher.miss_observed 0 # number of misses observed -system.ruby.l1_cntrl4.prefetcher.allocated_streams 0 # number of streams allocated for prefetching -system.ruby.l1_cntrl4.prefetcher.prefetches_requested 0 # number of prefetch requests made -system.ruby.l1_cntrl4.prefetcher.prefetches_accepted 0 # number of prefetch requests accepted -system.ruby.l1_cntrl4.prefetcher.dropped_prefetches 0 # number of prefetch requests dropped -system.ruby.l1_cntrl4.prefetcher.hits 0 # number of prefetched blocks accessed -system.ruby.l1_cntrl4.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched -system.ruby.l1_cntrl4.prefetcher.pages_crossed 0 # number of prefetches across pages -system.ruby.l1_cntrl4.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed -system.ruby.l1_cntrl5.L1Dcache.demand_hits 1 # Number of cache demand hits -system.ruby.l1_cntrl5.L1Dcache.demand_misses 77775 # Number of cache demand misses -system.ruby.l1_cntrl5.L1Dcache.demand_accesses 77776 # Number of cache demand accesses -system.ruby.l1_cntrl5.L1Icache.demand_hits 0 # Number of cache demand hits -system.ruby.l1_cntrl5.L1Icache.demand_misses 0 # Number of cache demand misses -system.ruby.l1_cntrl5.L1Icache.demand_accesses 0 # Number of cache demand accesses -system.ruby.l1_cntrl5.prefetcher.miss_observed 0 # number of misses observed -system.ruby.l1_cntrl5.prefetcher.allocated_streams 0 # number of streams allocated for prefetching -system.ruby.l1_cntrl5.prefetcher.prefetches_requested 0 # number of prefetch requests made -system.ruby.l1_cntrl5.prefetcher.prefetches_accepted 0 # number of prefetch requests accepted -system.ruby.l1_cntrl5.prefetcher.dropped_prefetches 0 # number of prefetch requests dropped -system.ruby.l1_cntrl5.prefetcher.hits 0 # number of prefetched blocks accessed -system.ruby.l1_cntrl5.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched -system.ruby.l1_cntrl5.prefetcher.pages_crossed 0 # number of prefetches across pages -system.ruby.l1_cntrl5.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed -system.ruby.l1_cntrl6.L1Dcache.demand_hits 1 # Number of cache demand hits -system.ruby.l1_cntrl6.L1Dcache.demand_misses 77691 # Number of cache demand misses -system.ruby.l1_cntrl6.L1Dcache.demand_accesses 77692 # Number of cache demand accesses -system.ruby.l1_cntrl6.L1Icache.demand_hits 0 # Number of cache demand hits -system.ruby.l1_cntrl6.L1Icache.demand_misses 0 # Number of cache demand misses -system.ruby.l1_cntrl6.L1Icache.demand_accesses 0 # Number of cache demand accesses -system.ruby.l1_cntrl6.prefetcher.miss_observed 0 # number of misses observed -system.ruby.l1_cntrl6.prefetcher.allocated_streams 0 # number of streams allocated for prefetching -system.ruby.l1_cntrl6.prefetcher.prefetches_requested 0 # number of prefetch requests made -system.ruby.l1_cntrl6.prefetcher.prefetches_accepted 0 # number of prefetch requests accepted -system.ruby.l1_cntrl6.prefetcher.dropped_prefetches 0 # number of prefetch requests dropped -system.ruby.l1_cntrl6.prefetcher.hits 0 # number of prefetched blocks accessed -system.ruby.l1_cntrl6.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched -system.ruby.l1_cntrl6.prefetcher.pages_crossed 0 # number of prefetches across pages -system.ruby.l1_cntrl6.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed -system.ruby.l1_cntrl7.L1Dcache.demand_hits 0 # Number of cache demand hits -system.ruby.l1_cntrl7.L1Dcache.demand_misses 77428 # Number of cache demand misses -system.ruby.l1_cntrl7.L1Dcache.demand_accesses 77428 # Number of cache demand accesses -system.ruby.l1_cntrl7.L1Icache.demand_hits 0 # Number of cache demand hits -system.ruby.l1_cntrl7.L1Icache.demand_misses 0 # Number of cache demand misses -system.ruby.l1_cntrl7.L1Icache.demand_accesses 0 # Number of cache demand accesses -system.ruby.l1_cntrl7.prefetcher.miss_observed 0 # number of misses observed -system.ruby.l1_cntrl7.prefetcher.allocated_streams 0 # number of streams allocated for prefetching -system.ruby.l1_cntrl7.prefetcher.prefetches_requested 0 # number of prefetch requests made -system.ruby.l1_cntrl7.prefetcher.prefetches_accepted 0 # number of prefetch requests accepted -system.ruby.l1_cntrl7.prefetcher.dropped_prefetches 0 # number of prefetch requests dropped -system.ruby.l1_cntrl7.prefetcher.hits 0 # number of prefetched blocks accessed -system.ruby.l1_cntrl7.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched -system.ruby.l1_cntrl7.prefetcher.pages_crossed 0 # number of prefetches across pages -system.ruby.l1_cntrl7.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed -system.ruby.l1_cntrl0.L1Dcache.demand_hits 1 # Number of cache demand hits -system.ruby.l1_cntrl0.L1Dcache.demand_misses 78352 # Number of cache demand misses -system.ruby.l1_cntrl0.L1Dcache.demand_accesses 78353 # Number of cache demand accesses +system.ruby.miss_latency_hist::samples 623677 +system.ruby.miss_latency_hist::mean 2072.642005 +system.ruby.miss_latency_hist::gmean 1591.643032 +system.ruby.miss_latency_hist::stdev 1226.946927 +system.ruby.miss_latency_hist | 164795 26.42% 26.42% | 150821 24.18% 50.61% | 147979 23.73% 74.33% | 131724 21.12% 95.45% | 27974 4.49% 99.94% | 384 0.06% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.miss_latency_hist::total 623677 +system.ruby.l1_cntrl0.L1Dcache.demand_hits 3 # Number of cache demand hits +system.ruby.l1_cntrl0.L1Dcache.demand_misses 77823 # Number of cache demand misses +system.ruby.l1_cntrl0.L1Dcache.demand_accesses 77826 # Number of cache demand accesses system.ruby.l1_cntrl0.L1Icache.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl0.L1Icache.demand_misses 0 # Number of cache demand misses system.ruby.l1_cntrl0.L1Icache.demand_accesses 0 # Number of cache demand accesses @@ -391,26 +360,9 @@ system.ruby.l1_cntrl0.prefetcher.hits 0 # nu system.ruby.l1_cntrl0.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched system.ruby.l1_cntrl0.prefetcher.pages_crossed 0 # number of prefetches across pages system.ruby.l1_cntrl0.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed -system.ruby.network.routers00.percent_links_utilized 4.017157 -system.ruby.network.routers00.msg_count.Control::0 78352 -system.ruby.network.routers00.msg_count.Request_Control::2 76727 -system.ruby.network.routers00.msg_count.Response_Data::1 78943 -system.ruby.network.routers00.msg_count.Response_Control::1 65296 -system.ruby.network.routers00.msg_count.Response_Control::2 77735 -system.ruby.network.routers00.msg_count.Writeback_Data::0 14723 -system.ruby.network.routers00.msg_count.Writeback_Data::1 52192 -system.ruby.network.routers00.msg_count.Writeback_Control::0 26458 -system.ruby.network.routers00.msg_bytes.Control::0 626816 -system.ruby.network.routers00.msg_bytes.Request_Control::2 613816 -system.ruby.network.routers00.msg_bytes.Response_Data::1 5683896 -system.ruby.network.routers00.msg_bytes.Response_Control::1 522368 -system.ruby.network.routers00.msg_bytes.Response_Control::2 621880 -system.ruby.network.routers00.msg_bytes.Writeback_Data::0 1060056 -system.ruby.network.routers00.msg_bytes.Writeback_Data::1 3757824 -system.ruby.network.routers00.msg_bytes.Writeback_Control::0 211664 -system.ruby.l1_cntrl1.L1Dcache.demand_hits 0 # Number of cache demand hits -system.ruby.l1_cntrl1.L1Dcache.demand_misses 78104 # Number of cache demand misses -system.ruby.l1_cntrl1.L1Dcache.demand_accesses 78104 # Number of cache demand accesses +system.ruby.l1_cntrl1.L1Dcache.demand_hits 2 # Number of cache demand hits +system.ruby.l1_cntrl1.L1Dcache.demand_misses 77422 # Number of cache demand misses +system.ruby.l1_cntrl1.L1Dcache.demand_accesses 77424 # Number of cache demand accesses system.ruby.l1_cntrl1.L1Icache.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl1.L1Icache.demand_misses 0 # Number of cache demand misses system.ruby.l1_cntrl1.L1Icache.demand_accesses 0 # Number of cache demand accesses @@ -423,26 +375,9 @@ system.ruby.l1_cntrl1.prefetcher.hits 0 # nu system.ruby.l1_cntrl1.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched system.ruby.l1_cntrl1.prefetcher.pages_crossed 0 # number of prefetches across pages system.ruby.l1_cntrl1.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed -system.ruby.network.routers01.percent_links_utilized 4.004745 -system.ruby.network.routers01.msg_count.Control::0 78104 -system.ruby.network.routers01.msg_count.Request_Control::2 76509 -system.ruby.network.routers01.msg_count.Response_Data::1 78659 -system.ruby.network.routers01.msg_count.Response_Control::1 65065 -system.ruby.network.routers01.msg_count.Response_Control::2 77454 -system.ruby.network.routers01.msg_count.Writeback_Data::0 14590 -system.ruby.network.routers01.msg_count.Writeback_Data::1 52150 -system.ruby.network.routers01.msg_count.Writeback_Control::0 26505 -system.ruby.network.routers01.msg_bytes.Control::0 624832 -system.ruby.network.routers01.msg_bytes.Request_Control::2 612072 -system.ruby.network.routers01.msg_bytes.Response_Data::1 5663448 -system.ruby.network.routers01.msg_bytes.Response_Control::1 520520 -system.ruby.network.routers01.msg_bytes.Response_Control::2 619632 -system.ruby.network.routers01.msg_bytes.Writeback_Data::0 1050480 -system.ruby.network.routers01.msg_bytes.Writeback_Data::1 3754800 -system.ruby.network.routers01.msg_bytes.Writeback_Control::0 212040 system.ruby.l1_cntrl2.L1Dcache.demand_hits 1 # Number of cache demand hits -system.ruby.l1_cntrl2.L1Dcache.demand_misses 78244 # Number of cache demand misses -system.ruby.l1_cntrl2.L1Dcache.demand_accesses 78245 # Number of cache demand accesses +system.ruby.l1_cntrl2.L1Dcache.demand_misses 77856 # Number of cache demand misses +system.ruby.l1_cntrl2.L1Dcache.demand_accesses 77857 # Number of cache demand accesses system.ruby.l1_cntrl2.L1Icache.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl2.L1Icache.demand_misses 0 # Number of cache demand misses system.ruby.l1_cntrl2.L1Icache.demand_accesses 0 # Number of cache demand accesses @@ -455,26 +390,9 @@ system.ruby.l1_cntrl2.prefetcher.hits 0 # nu system.ruby.l1_cntrl2.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched system.ruby.l1_cntrl2.prefetcher.pages_crossed 0 # number of prefetches across pages system.ruby.l1_cntrl2.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed -system.ruby.network.routers02.percent_links_utilized 4.010243 -system.ruby.network.routers02.msg_count.Control::0 78244 -system.ruby.network.routers02.msg_count.Request_Control::2 76806 -system.ruby.network.routers02.msg_count.Response_Data::1 78763 -system.ruby.network.routers02.msg_count.Response_Control::1 65157 -system.ruby.network.routers02.msg_count.Response_Control::2 77588 -system.ruby.network.routers02.msg_count.Writeback_Data::0 14535 -system.ruby.network.routers02.msg_count.Writeback_Data::1 52281 -system.ruby.network.routers02.msg_count.Writeback_Control::0 26463 -system.ruby.network.routers02.msg_bytes.Control::0 625952 -system.ruby.network.routers02.msg_bytes.Request_Control::2 614448 -system.ruby.network.routers02.msg_bytes.Response_Data::1 5670936 -system.ruby.network.routers02.msg_bytes.Response_Control::1 521256 -system.ruby.network.routers02.msg_bytes.Response_Control::2 620704 -system.ruby.network.routers02.msg_bytes.Writeback_Data::0 1046520 -system.ruby.network.routers02.msg_bytes.Writeback_Data::1 3764232 -system.ruby.network.routers02.msg_bytes.Writeback_Control::0 211704 -system.ruby.l1_cntrl3.L1Dcache.demand_hits 0 # Number of cache demand hits -system.ruby.l1_cntrl3.L1Dcache.demand_misses 78003 # Number of cache demand misses -system.ruby.l1_cntrl3.L1Dcache.demand_accesses 78003 # Number of cache demand accesses +system.ruby.l1_cntrl3.L1Dcache.demand_hits 1 # Number of cache demand hits +system.ruby.l1_cntrl3.L1Dcache.demand_misses 77999 # Number of cache demand misses +system.ruby.l1_cntrl3.L1Dcache.demand_accesses 78000 # Number of cache demand accesses system.ruby.l1_cntrl3.L1Icache.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl3.L1Icache.demand_misses 0 # Number of cache demand misses system.ruby.l1_cntrl3.L1Icache.demand_accesses 0 # Number of cache demand accesses @@ -487,729 +405,819 @@ system.ruby.l1_cntrl3.prefetcher.hits 0 # nu system.ruby.l1_cntrl3.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched system.ruby.l1_cntrl3.prefetcher.pages_crossed 0 # number of prefetches across pages system.ruby.l1_cntrl3.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed -system.ruby.network.routers03.percent_links_utilized 3.995461 -system.ruby.network.routers03.msg_count.Control::0 78003 -system.ruby.network.routers03.msg_count.Request_Control::2 76449 -system.ruby.network.routers03.msg_count.Response_Data::1 78486 -system.ruby.network.routers03.msg_count.Response_Control::1 64943 -system.ruby.network.routers03.msg_count.Response_Control::2 77331 -system.ruby.network.routers03.msg_count.Writeback_Data::0 14715 -system.ruby.network.routers03.msg_count.Writeback_Data::1 51879 -system.ruby.network.routers03.msg_count.Writeback_Control::0 25998 -system.ruby.network.routers03.msg_bytes.Control::0 624024 -system.ruby.network.routers03.msg_bytes.Request_Control::2 611592 -system.ruby.network.routers03.msg_bytes.Response_Data::1 5650992 -system.ruby.network.routers03.msg_bytes.Response_Control::1 519544 -system.ruby.network.routers03.msg_bytes.Response_Control::2 618648 -system.ruby.network.routers03.msg_bytes.Writeback_Data::0 1059480 -system.ruby.network.routers03.msg_bytes.Writeback_Data::1 3735288 -system.ruby.network.routers03.msg_bytes.Writeback_Control::0 207984 -system.ruby.network.routers04.percent_links_utilized 3.971652 -system.ruby.network.routers04.msg_count.Control::0 77550 -system.ruby.network.routers04.msg_count.Request_Control::2 76039 -system.ruby.network.routers04.msg_count.Response_Data::1 78047 -system.ruby.network.routers04.msg_count.Response_Control::1 64587 -system.ruby.network.routers04.msg_count.Response_Control::2 76934 -system.ruby.network.routers04.msg_count.Writeback_Data::0 14444 -system.ruby.network.routers04.msg_count.Writeback_Data::1 51674 -system.ruby.network.routers04.msg_count.Writeback_Control::0 26145 -system.ruby.network.routers04.msg_bytes.Control::0 620400 -system.ruby.network.routers04.msg_bytes.Request_Control::2 608312 -system.ruby.network.routers04.msg_bytes.Response_Data::1 5619384 -system.ruby.network.routers04.msg_bytes.Response_Control::1 516696 -system.ruby.network.routers04.msg_bytes.Response_Control::2 615472 -system.ruby.network.routers04.msg_bytes.Writeback_Data::0 1039968 -system.ruby.network.routers04.msg_bytes.Writeback_Data::1 3720528 -system.ruby.network.routers04.msg_bytes.Writeback_Control::0 209160 -system.ruby.network.routers05.percent_links_utilized 3.984903 -system.ruby.network.routers05.msg_count.Control::0 77775 -system.ruby.network.routers05.msg_count.Request_Control::2 76299 -system.ruby.network.routers05.msg_count.Response_Data::1 78272 -system.ruby.network.routers05.msg_count.Response_Control::1 64779 -system.ruby.network.routers05.msg_count.Response_Control::2 77121 -system.ruby.network.routers05.msg_count.Writeback_Data::0 14571 -system.ruby.network.routers05.msg_count.Writeback_Data::1 51833 -system.ruby.network.routers05.msg_count.Writeback_Control::0 26083 -system.ruby.network.routers05.msg_bytes.Control::0 622200 -system.ruby.network.routers05.msg_bytes.Request_Control::2 610392 -system.ruby.network.routers05.msg_bytes.Response_Data::1 5635584 -system.ruby.network.routers05.msg_bytes.Response_Control::1 518232 -system.ruby.network.routers05.msg_bytes.Response_Control::2 616968 -system.ruby.network.routers05.msg_bytes.Writeback_Data::0 1049112 -system.ruby.network.routers05.msg_bytes.Writeback_Data::1 3731976 -system.ruby.network.routers05.msg_bytes.Writeback_Control::0 208664 -system.ruby.network.routers06.percent_links_utilized 3.974939 -system.ruby.network.routers06.msg_count.Control::0 77691 -system.ruby.network.routers06.msg_count.Request_Control::2 76079 -system.ruby.network.routers06.msg_count.Response_Data::1 78230 -system.ruby.network.routers06.msg_count.Response_Control::1 64698 -system.ruby.network.routers06.msg_count.Response_Control::2 77044 -system.ruby.network.routers06.msg_count.Writeback_Data::0 14650 -system.ruby.network.routers06.msg_count.Writeback_Data::1 51429 -system.ruby.network.routers06.msg_count.Writeback_Control::0 25787 -system.ruby.network.routers06.msg_bytes.Control::0 621528 -system.ruby.network.routers06.msg_bytes.Request_Control::2 608632 -system.ruby.network.routers06.msg_bytes.Response_Data::1 5632560 -system.ruby.network.routers06.msg_bytes.Response_Control::1 517584 -system.ruby.network.routers06.msg_bytes.Response_Control::2 616352 -system.ruby.network.routers06.msg_bytes.Writeback_Data::0 1054800 -system.ruby.network.routers06.msg_bytes.Writeback_Data::1 3702888 -system.ruby.network.routers06.msg_bytes.Writeback_Control::0 206296 -system.ruby.network.routers07.percent_links_utilized 3.964826 -system.ruby.network.routers07.msg_count.Control::0 77428 -system.ruby.network.routers07.msg_count.Request_Control::2 75965 -system.ruby.network.routers07.msg_count.Response_Data::1 77944 -system.ruby.network.routers07.msg_count.Response_Control::1 64454 -system.ruby.network.routers07.msg_count.Response_Control::2 76853 -system.ruby.network.routers07.msg_count.Writeback_Data::0 14464 -system.ruby.network.routers07.msg_count.Writeback_Data::1 51520 -system.ruby.network.routers07.msg_count.Writeback_Control::0 25906 -system.ruby.network.routers07.msg_bytes.Control::0 619424 -system.ruby.network.routers07.msg_bytes.Request_Control::2 607720 -system.ruby.network.routers07.msg_bytes.Response_Data::1 5611968 -system.ruby.network.routers07.msg_bytes.Response_Control::1 515632 -system.ruby.network.routers07.msg_bytes.Response_Control::2 614824 -system.ruby.network.routers07.msg_bytes.Writeback_Data::0 1041408 -system.ruby.network.routers07.msg_bytes.Writeback_Data::1 3709440 -system.ruby.network.routers07.msg_bytes.Writeback_Control::0 207248 -system.ruby.l2_cntrl0.L2cache.demand_hits 31 # Number of cache demand hits -system.ruby.l2_cntrl0.L2cache.demand_misses 623101 # Number of cache demand misses -system.ruby.l2_cntrl0.L2cache.demand_accesses 623132 # Number of cache demand accesses -system.ruby.l2_cntrl0.fully_busy_cycles 1 # cycles for which number of transistions == max transitions -system.ruby.network.routers08.percent_links_utilized 54.245833 -system.ruby.network.routers08.msg_count.Control::0 1240723 -system.ruby.network.routers08.msg_count.Request_Control::2 607107 -system.ruby.network.routers08.msg_count.Response_Data::1 1457329 -system.ruby.network.routers08.msg_count.Response_Control::1 1533130 -system.ruby.network.routers08.msg_count.Response_Control::2 618060 -system.ruby.network.routers08.msg_count.Writeback_Data::0 116692 -system.ruby.network.routers08.msg_count.Writeback_Data::1 414958 -system.ruby.network.routers08.msg_count.Writeback_Control::0 209345 -system.ruby.network.routers08.msg_bytes.Control::0 9925784 -system.ruby.network.routers08.msg_bytes.Request_Control::2 4856856 -system.ruby.network.routers08.msg_bytes.Response_Data::1 104927688 -system.ruby.network.routers08.msg_bytes.Response_Control::1 12265040 -system.ruby.network.routers08.msg_bytes.Response_Control::2 4944480 -system.ruby.network.routers08.msg_bytes.Writeback_Data::0 8401824 -system.ruby.network.routers08.msg_bytes.Writeback_Data::1 29876976 -system.ruby.network.routers08.msg_bytes.Writeback_Control::0 1674760 -system.ruby.network.routers09.percent_links_utilized 22.519302 -system.ruby.network.routers09.msg_count.Control::0 617577 -system.ruby.network.routers09.msg_count.Response_Data::1 838498 -system.ruby.network.routers09.msg_count.Response_Control::1 1014212 -system.ruby.network.routers09.msg_bytes.Control::0 4940616 -system.ruby.network.routers09.msg_bytes.Response_Data::1 60371856 -system.ruby.network.routers09.msg_bytes.Response_Control::1 8113696 -system.ruby.network.routers10.percent_links_utilized 10.875421 -system.ruby.network.routers10.msg_count.Control::0 1240723 -system.ruby.network.routers10.msg_count.Request_Control::2 610873 -system.ruby.network.routers10.msg_count.Response_Data::1 1462851 -system.ruby.network.routers10.msg_count.Response_Control::1 1533161 -system.ruby.network.routers10.msg_count.Response_Control::2 618060 -system.ruby.network.routers10.msg_count.Writeback_Data::0 116692 -system.ruby.network.routers10.msg_count.Writeback_Data::1 414958 -system.ruby.network.routers10.msg_count.Writeback_Control::0 209345 -system.ruby.network.routers10.msg_bytes.Control::0 9925784 -system.ruby.network.routers10.msg_bytes.Request_Control::2 4886984 -system.ruby.network.routers10.msg_bytes.Response_Data::1 105325272 -system.ruby.network.routers10.msg_bytes.Response_Control::1 12265288 -system.ruby.network.routers10.msg_bytes.Response_Control::2 4944480 -system.ruby.network.routers10.msg_bytes.Writeback_Data::0 8401824 -system.ruby.network.routers10.msg_bytes.Writeback_Data::1 29876976 -system.ruby.network.routers10.msg_bytes.Writeback_Control::0 1674760 -system.ruby.network.msg_count.Control 3722170 -system.ruby.network.msg_count.Request_Control 1828853 -system.ruby.network.msg_count.Response_Data 4386022 -system.ruby.network.msg_count.Response_Control 6453662 -system.ruby.network.msg_count.Writeback_Data 1594950 -system.ruby.network.msg_count.Writeback_Control 628035 -system.ruby.network.msg_byte.Control 29777360 -system.ruby.network.msg_byte.Request_Control 14630824 -system.ruby.network.msg_byte.Response_Data 315793584 -system.ruby.network.msg_byte.Response_Control 51629296 -system.ruby.network.msg_byte.Writeback_Data 114836400 -system.ruby.network.msg_byte.Writeback_Control 5024280 +system.ruby.l1_cntrl4.L1Dcache.demand_hits 0 # Number of cache demand hits +system.ruby.l1_cntrl4.L1Dcache.demand_misses 78237 # Number of cache demand misses +system.ruby.l1_cntrl4.L1Dcache.demand_accesses 78237 # Number of cache demand accesses +system.ruby.l1_cntrl4.L1Icache.demand_hits 0 # Number of cache demand hits +system.ruby.l1_cntrl4.L1Icache.demand_misses 0 # Number of cache demand misses +system.ruby.l1_cntrl4.L1Icache.demand_accesses 0 # Number of cache demand accesses +system.ruby.l1_cntrl4.prefetcher.miss_observed 0 # number of misses observed +system.ruby.l1_cntrl4.prefetcher.allocated_streams 0 # number of streams allocated for prefetching +system.ruby.l1_cntrl4.prefetcher.prefetches_requested 0 # number of prefetch requests made +system.ruby.l1_cntrl4.prefetcher.prefetches_accepted 0 # number of prefetch requests accepted +system.ruby.l1_cntrl4.prefetcher.dropped_prefetches 0 # number of prefetch requests dropped +system.ruby.l1_cntrl4.prefetcher.hits 0 # number of prefetched blocks accessed +system.ruby.l1_cntrl4.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched +system.ruby.l1_cntrl4.prefetcher.pages_crossed 0 # number of prefetches across pages +system.ruby.l1_cntrl4.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed +system.ruby.l1_cntrl5.L1Dcache.demand_hits 1 # Number of cache demand hits +system.ruby.l1_cntrl5.L1Dcache.demand_misses 77909 # Number of cache demand misses +system.ruby.l1_cntrl5.L1Dcache.demand_accesses 77910 # Number of cache demand accesses +system.ruby.l1_cntrl5.L1Icache.demand_hits 0 # Number of cache demand hits +system.ruby.l1_cntrl5.L1Icache.demand_misses 0 # Number of cache demand misses +system.ruby.l1_cntrl5.L1Icache.demand_accesses 0 # Number of cache demand accesses +system.ruby.l1_cntrl5.prefetcher.miss_observed 0 # number of misses observed +system.ruby.l1_cntrl5.prefetcher.allocated_streams 0 # number of streams allocated for prefetching +system.ruby.l1_cntrl5.prefetcher.prefetches_requested 0 # number of prefetch requests made +system.ruby.l1_cntrl5.prefetcher.prefetches_accepted 0 # number of prefetch requests accepted +system.ruby.l1_cntrl5.prefetcher.dropped_prefetches 0 # number of prefetch requests dropped +system.ruby.l1_cntrl5.prefetcher.hits 0 # number of prefetched blocks accessed +system.ruby.l1_cntrl5.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched +system.ruby.l1_cntrl5.prefetcher.pages_crossed 0 # number of prefetches across pages +system.ruby.l1_cntrl5.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed +system.ruby.l1_cntrl6.L1Dcache.demand_hits 0 # Number of cache demand hits +system.ruby.l1_cntrl6.L1Dcache.demand_misses 77980 # Number of cache demand misses +system.ruby.l1_cntrl6.L1Dcache.demand_accesses 77980 # Number of cache demand accesses +system.ruby.l1_cntrl6.L1Icache.demand_hits 0 # Number of cache demand hits +system.ruby.l1_cntrl6.L1Icache.demand_misses 0 # Number of cache demand misses +system.ruby.l1_cntrl6.L1Icache.demand_accesses 0 # Number of cache demand accesses +system.ruby.l1_cntrl6.prefetcher.miss_observed 0 # number of misses observed +system.ruby.l1_cntrl6.prefetcher.allocated_streams 0 # number of streams allocated for prefetching +system.ruby.l1_cntrl6.prefetcher.prefetches_requested 0 # number of prefetch requests made +system.ruby.l1_cntrl6.prefetcher.prefetches_accepted 0 # number of prefetch requests accepted +system.ruby.l1_cntrl6.prefetcher.dropped_prefetches 0 # number of prefetch requests dropped +system.ruby.l1_cntrl6.prefetcher.hits 0 # number of prefetched blocks accessed +system.ruby.l1_cntrl6.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched +system.ruby.l1_cntrl6.prefetcher.pages_crossed 0 # number of prefetches across pages +system.ruby.l1_cntrl6.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed +system.ruby.l1_cntrl7.L1Dcache.demand_hits 1 # Number of cache demand hits +system.ruby.l1_cntrl7.L1Dcache.demand_misses 78469 # Number of cache demand misses +system.ruby.l1_cntrl7.L1Dcache.demand_accesses 78470 # Number of cache demand accesses +system.ruby.l1_cntrl7.L1Icache.demand_hits 0 # Number of cache demand hits +system.ruby.l1_cntrl7.L1Icache.demand_misses 0 # Number of cache demand misses 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+system.ruby.network.routers10.throttle5.msg_bytes.Response_Data::1 5609304 +system.ruby.network.routers10.throttle5.msg_bytes.Response_Control::1 325640 +system.ruby.network.routers10.throttle6.link_utilization 4.053525 +system.ruby.network.routers10.throttle6.msg_count.Request_Control::2 76399 +system.ruby.network.routers10.throttle6.msg_count.Response_Data::1 77977 +system.ruby.network.routers10.throttle6.msg_count.Response_Control::1 40662 +system.ruby.network.routers10.throttle6.msg_bytes.Request_Control::2 611192 +system.ruby.network.routers10.throttle6.msg_bytes.Response_Data::1 5614344 +system.ruby.network.routers10.throttle6.msg_bytes.Response_Control::1 325296 +system.ruby.network.routers10.throttle7.link_utilization 4.080023 +system.ruby.network.routers10.throttle7.msg_count.Request_Control::2 76701 +system.ruby.network.routers10.throttle7.msg_count.Response_Data::1 78467 +system.ruby.network.routers10.throttle7.msg_count.Response_Control::1 41303 +system.ruby.network.routers10.throttle7.msg_bytes.Request_Control::2 613608 +system.ruby.network.routers10.throttle7.msg_bytes.Response_Data::1 5649624 +system.ruby.network.routers10.throttle7.msg_bytes.Response_Control::1 330424 +system.ruby.network.routers10.throttle8.link_utilization 62.405225 +system.ruby.network.routers10.throttle8.msg_count.Control::0 623695 +system.ruby.network.routers10.throttle8.msg_count.Response_Data::1 619265 +system.ruby.network.routers10.throttle8.msg_count.Response_Control::1 811741 +system.ruby.network.routers10.throttle8.msg_count.Response_Control::2 618595 +system.ruby.network.routers10.throttle8.msg_count.Writeback_Data::0 116618 +system.ruby.network.routers10.throttle8.msg_count.Writeback_Data::1 413398 +system.ruby.network.routers10.throttle8.msg_count.Writeback_Control::0 208947 +system.ruby.network.routers10.throttle8.msg_bytes.Control::0 4989560 +system.ruby.network.routers10.throttle8.msg_bytes.Response_Data::1 44587080 +system.ruby.network.routers10.throttle8.msg_bytes.Response_Control::1 6493928 +system.ruby.network.routers10.throttle8.msg_bytes.Response_Control::2 4948760 +system.ruby.network.routers10.throttle8.msg_bytes.Writeback_Data::0 8396496 +system.ruby.network.routers10.throttle8.msg_bytes.Writeback_Data::1 29764656 +system.ruby.network.routers10.throttle8.msg_bytes.Writeback_Control::0 1671576 +system.ruby.network.routers10.throttle9.link_utilization 14.870950 +system.ruby.network.routers10.throttle9.msg_count.Control::0 617983 +system.ruby.network.routers10.throttle9.msg_count.Response_Data::1 221016 +system.ruby.network.routers10.throttle9.msg_count.Response_Control::1 396959 +system.ruby.network.routers10.throttle9.msg_bytes.Control::0 4943864 +system.ruby.network.routers10.throttle9.msg_bytes.Response_Data::1 15913152 +system.ruby.network.routers10.throttle9.msg_bytes.Response_Control::1 3175672 system.ruby.delayVCHist.vnet_0::bucket_size 2048 # delay histogram for vnet_0 system.ruby.delayVCHist.vnet_0::max_bucket 20479 # delay histogram for vnet_0 -system.ruby.delayVCHist.vnet_0::samples 1567216 # delay histogram for vnet_0 -system.ruby.delayVCHist.vnet_0::mean 648.458979 # delay histogram for vnet_0 -system.ruby.delayVCHist.vnet_0::stdev 907.022632 # delay histogram for vnet_0 -system.ruby.delayVCHist.vnet_0 | 1421287 90.69% 90.69% | 138459 8.83% 99.52% | 7092 0.45% 99.98% | 343 0.02% 100.00% | 32 0.00% 100.00% | 1 0.00% 100.00% | 1 0.00% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_0 -system.ruby.delayVCHist.vnet_0::total 1567216 # delay histogram for vnet_0 +system.ruby.delayVCHist.vnet_0::samples 1567834 # delay histogram for vnet_0 +system.ruby.delayVCHist.vnet_0::mean 632.927856 # delay histogram for vnet_0 +system.ruby.delayVCHist.vnet_0::stdev 886.561692 # delay histogram for vnet_0 +system.ruby.delayVCHist.vnet_0 | 1430124 91.22% 91.22% | 131198 8.37% 99.58% | 6246 0.40% 99.98% | 255 0.02% 100.00% | 8 0.00% 100.00% | 2 0.00% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_0 +system.ruby.delayVCHist.vnet_0::total 1567834 # delay histogram for vnet_0 system.ruby.delayVCHist.vnet_1::bucket_size 8 # delay histogram for vnet_1 system.ruby.delayVCHist.vnet_1::max_bucket 79 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::samples 2793400 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::mean 2.237732 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::stdev 4.228455 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1 | 2393251 85.68% 85.68% | 334671 11.98% 97.66% | 57246 2.05% 99.71% | 7631 0.27% 99.98% | 583 0.02% 100.00% | 15 0.00% 100.00% | 3 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::total 2793400 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::samples 2793654 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::mean 2.252049 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::stdev 4.236651 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1 | 2389326 85.53% 85.53% | 338163 12.10% 97.63% | 58171 2.08% 99.71% | 7435 0.27% 99.98% | 537 0.02% 100.00% | 22 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::total 2793654 # delay histogram for vnet_1 system.ruby.delayVCHist.vnet_2::bucket_size 1 # delay histogram for vnet_2 system.ruby.delayVCHist.vnet_2::max_bucket 9 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::samples 610873 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::mean 0.009868 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::stdev 0.140184 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2 | 607860 99.51% 99.51% | 0 0.00% 99.51% | 3012 0.49% 100.00% | 0 0.00% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::total 610873 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::samples 610308 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::mean 0.009651 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::stdev 0.138784 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2 | 607367 99.52% 99.52% | 0 0.00% 99.52% | 2937 0.48% 100.00% | 0 0.00% 100.00% | 4 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::total 610308 # delay histogram for vnet_2 system.ruby.LD.latency_hist::bucket_size 1024 system.ruby.LD.latency_hist::max_bucket 10239 -system.ruby.LD.latency_hist::samples 401577 -system.ruby.LD.latency_hist::mean 2092.828952 -system.ruby.LD.latency_hist::gmean 1620.627009 -system.ruby.LD.latency_hist::stdev 1225.164807 -system.ruby.LD.latency_hist | 103361 25.74% 25.74% | 97791 24.35% 50.09% | 95926 23.89% 73.98% | 85248 21.23% 95.21% | 18977 4.73% 99.93% | 274 0.07% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.latency_hist::total 401577 +system.ruby.LD.latency_hist::samples 402001 +system.ruby.LD.latency_hist::mean 2073.498317 +system.ruby.LD.latency_hist::gmean 1592.038290 +system.ruby.LD.latency_hist::stdev 1226.855968 +system.ruby.LD.latency_hist | 106152 26.41% 26.41% | 97021 24.13% 50.54% | 95622 23.79% 74.33% | 84872 21.11% 95.44% | 18097 4.50% 99.94% | 237 0.06% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.latency_hist::total 402001 system.ruby.LD.hit_latency_hist::bucket_size 1 system.ruby.LD.hit_latency_hist::max_bucket 9 -system.ruby.LD.hit_latency_hist::samples 3 +system.ruby.LD.hit_latency_hist::samples 6 system.ruby.LD.hit_latency_hist::mean 3 system.ruby.LD.hit_latency_hist::gmean 3.000000 -system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 3 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.hit_latency_hist::total 3 +system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 6 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.hit_latency_hist::total 6 system.ruby.LD.miss_latency_hist::bucket_size 1024 system.ruby.LD.miss_latency_hist::max_bucket 10239 -system.ruby.LD.miss_latency_hist::samples 401574 -system.ruby.LD.miss_latency_hist::mean 2092.844564 -system.ruby.LD.miss_latency_hist::gmean 1620.703188 -system.ruby.LD.miss_latency_hist::stdev 1225.156067 -system.ruby.LD.miss_latency_hist | 103358 25.74% 25.74% | 97791 24.35% 50.09% | 95926 23.89% 73.98% | 85248 21.23% 95.21% | 18977 4.73% 99.93% | 274 0.07% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.miss_latency_hist::total 401574 +system.ruby.LD.miss_latency_hist::samples 401995 +system.ruby.LD.miss_latency_hist::mean 2073.529221 +system.ruby.LD.miss_latency_hist::gmean 1592.187383 +system.ruby.LD.miss_latency_hist::stdev 1226.839046 +system.ruby.LD.miss_latency_hist | 106146 26.40% 26.40% | 97021 24.13% 50.54% | 95622 23.79% 74.33% | 84872 21.11% 95.44% | 18097 4.50% 99.94% | 237 0.06% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.miss_latency_hist::total 401995 system.ruby.ST.latency_hist::bucket_size 1024 system.ruby.ST.latency_hist::max_bucket 10239 -system.ruby.ST.latency_hist::samples 221554 -system.ruby.ST.latency_hist::mean 2092.639230 -system.ruby.ST.latency_hist::gmean 1619.493152 -system.ruby.ST.latency_hist::stdev 1225.291787 -system.ruby.ST.latency_hist | 57047 25.75% 25.75% | 53910 24.33% 50.08% | 52846 23.85% 73.93% | 47171 21.29% 95.22% | 10438 4.71% 99.94% | 142 0.06% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.latency_hist::total 221554 +system.ruby.ST.latency_hist::samples 221685 +system.ruby.ST.latency_hist::mean 2071.005156 +system.ruby.ST.latency_hist::gmean 1590.521356 +system.ruby.ST.latency_hist::stdev 1227.158942 +system.ruby.ST.latency_hist | 58652 26.46% 26.46% | 53800 24.27% 50.73% | 52357 23.62% 74.34% | 46852 21.13% 95.48% | 9877 4.46% 99.93% | 147 0.07% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.latency_hist::total 221685 system.ruby.ST.hit_latency_hist::bucket_size 1 system.ruby.ST.hit_latency_hist::max_bucket 9 -system.ruby.ST.hit_latency_hist::samples 2 +system.ruby.ST.hit_latency_hist::samples 3 system.ruby.ST.hit_latency_hist::mean 3 system.ruby.ST.hit_latency_hist::gmean 3.000000 -system.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 2 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.hit_latency_hist::total 2 +system.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 3 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.hit_latency_hist::total 3 system.ruby.ST.miss_latency_hist::bucket_size 1024 system.ruby.ST.miss_latency_hist::max_bucket 10239 -system.ruby.ST.miss_latency_hist::samples 221552 -system.ruby.ST.miss_latency_hist::mean 2092.658094 -system.ruby.ST.miss_latency_hist::gmean 1619.585130 -system.ruby.ST.miss_latency_hist::stdev 1225.281232 -system.ruby.ST.miss_latency_hist | 57045 25.75% 25.75% | 53910 24.33% 50.08% | 52846 23.85% 73.93% | 47171 21.29% 95.22% | 10438 4.71% 99.94% | 142 0.06% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.miss_latency_hist::total 221552 -system.ruby.L1Cache_Controller.Load | 50466 12.57% 12.57% | 50379 12.54% 25.11% | 50567 12.59% 37.70% | 50137 12.48% 50.19% | 50081 12.47% 62.66% | 50104 12.48% 75.13% | 49966 12.44% 87.58% | 49898 12.42% 100.00% -system.ruby.L1Cache_Controller.Load::total 401598 -system.ruby.L1Cache_Controller.Store | 27889 12.59% 12.59% | 27726 12.51% 25.10% | 27680 12.49% 37.59% | 27867 12.58% 50.17% | 27470 12.40% 62.57% | 27674 12.49% 75.06% | 27726 12.51% 87.57% | 27532 12.43% 100.00% -system.ruby.L1Cache_Controller.Store::total 221564 -system.ruby.L1Cache_Controller.Inv | 76306 12.55% 12.55% | 76112 12.52% 25.07% | 76439 12.57% 37.65% | 76103 12.52% 50.17% | 75674 12.45% 62.62% | 75957 12.50% 75.11% | 75688 12.45% 87.56% | 75603 12.44% 100.00% -system.ruby.L1Cache_Controller.Inv::total 607882 -system.ruby.L1Cache_Controller.L1_Replacement | 550362 12.51% 12.51% | 550377 12.51% 25.01% | 551471 12.53% 37.55% | 549961 12.50% 50.05% | 548799 12.47% 62.52% | 549479 12.49% 75.00% | 550759 12.52% 87.52% | 549170 12.48% 100.00% -system.ruby.L1Cache_Controller.L1_Replacement::total 4400378 -system.ruby.L1Cache_Controller.Fwd_GETX | 248 14.06% 14.06% | 237 13.44% 27.49% | 214 12.13% 39.63% | 206 11.68% 51.30% | 229 12.98% 64.29% | 184 10.43% 74.72% | 240 13.61% 88.32% | 206 11.68% 100.00% -system.ruby.L1Cache_Controller.Fwd_GETX::total 1764 -system.ruby.L1Cache_Controller.Fwd_GETS | 173 14.10% 14.10% | 160 13.04% 27.14% | 153 12.47% 39.61% | 140 11.41% 51.02% | 136 11.08% 62.10% | 158 12.88% 74.98% | 151 12.31% 87.29% | 156 12.71% 100.00% -system.ruby.L1Cache_Controller.Fwd_GETS::total 1227 -system.ruby.L1Cache_Controller.Data | 2 13.33% 13.33% | 5 33.33% 46.67% | 1 6.67% 53.33% | 3 20.00% 73.33% | 0 0.00% 73.33% | 1 6.67% 80.00% | 2 13.33% 93.33% | 1 6.67% 100.00% -system.ruby.L1Cache_Controller.Data::total 15 -system.ruby.L1Cache_Controller.Data_Exclusive | 49704 12.57% 12.57% | 49580 12.54% 25.12% | 49744 12.58% 37.70% | 49297 12.47% 50.17% | 49326 12.48% 62.65% | 49286 12.47% 75.12% | 49158 12.44% 87.56% | 49187 12.44% 100.00% -system.ruby.L1Cache_Controller.Data_Exclusive::total 395282 -system.ruby.L1Cache_Controller.DataS_fromL1 | 145 11.82% 11.82% | 148 12.06% 23.88% | 165 13.45% 37.33% | 168 13.69% 51.02% | 139 11.33% 62.35% | 164 13.37% 75.71% | 161 13.12% 88.83% | 137 11.17% 100.00% -system.ruby.L1Cache_Controller.DataS_fromL1::total 1227 -system.ruby.L1Cache_Controller.Data_all_Acks | 28498 12.58% 12.58% | 28369 12.52% 25.10% | 28333 12.50% 37.60% | 28532 12.59% 50.19% | 28081 12.39% 62.58% | 28321 12.50% 75.08% | 28367 12.52% 87.60% | 28101 12.40% 100.00% -system.ruby.L1Cache_Controller.Data_all_Acks::total 226602 -system.ruby.L1Cache_Controller.Ack | 2 13.33% 13.33% | 5 33.33% 46.67% | 1 6.67% 53.33% | 3 20.00% 73.33% | 0 0.00% 73.33% | 1 6.67% 80.00% | 2 13.33% 93.33% | 1 6.67% 100.00% -system.ruby.L1Cache_Controller.Ack::total 15 -system.ruby.L1Cache_Controller.Ack_all | 2 13.33% 13.33% | 5 33.33% 46.67% | 1 6.67% 53.33% | 3 20.00% 73.33% | 0 0.00% 73.33% | 1 6.67% 80.00% | 2 13.33% 93.33% | 1 6.67% 100.00% -system.ruby.L1Cache_Controller.Ack_all::total 15 -system.ruby.L1Cache_Controller.WB_Ack | 41178 12.63% 12.63% | 41093 12.60% 25.23% | 40997 12.57% 37.81% | 40713 12.49% 50.30% | 40587 12.45% 62.75% | 40653 12.47% 75.22% | 40435 12.40% 87.62% | 40369 12.38% 100.00% -system.ruby.L1Cache_Controller.WB_Ack::total 326025 -system.ruby.L1Cache_Controller.NP.Load | 50453 12.57% 12.57% | 50369 12.54% 25.11% | 50559 12.59% 37.70% | 50126 12.48% 50.19% | 50072 12.47% 62.66% | 50098 12.48% 75.13% | 49957 12.44% 87.58% | 49889 12.42% 100.00% -system.ruby.L1Cache_Controller.NP.Load::total 401523 -system.ruby.L1Cache_Controller.NP.Store | 27884 12.59% 12.59% | 27721 12.51% 25.10% | 27674 12.49% 37.59% | 27863 12.58% 50.17% | 27463 12.40% 62.57% | 27669 12.49% 75.06% | 27720 12.51% 87.57% | 27527 12.43% 100.00% -system.ruby.L1Cache_Controller.NP.Store::total 221521 -system.ruby.L1Cache_Controller.NP.Inv | 222 13.54% 13.54% | 219 13.35% 26.89% | 200 12.20% 39.09% | 205 12.50% 51.59% | 183 11.16% 62.74% | 203 12.38% 75.12% | 197 12.01% 87.13% | 211 12.87% 100.00% -system.ruby.L1Cache_Controller.NP.Inv::total 1640 -system.ruby.L1Cache_Controller.I.Load | 10 15.15% 15.15% | 9 13.64% 28.79% | 6 9.09% 37.88% | 10 15.15% 53.03% | 8 12.12% 65.15% | 6 9.09% 74.24% | 8 12.12% 86.36% | 9 13.64% 100.00% -system.ruby.L1Cache_Controller.I.Load::total 66 -system.ruby.L1Cache_Controller.I.Store | 5 13.51% 13.51% | 5 13.51% 27.03% | 5 13.51% 40.54% | 4 10.81% 51.35% | 7 18.92% 70.27% | 2 5.41% 75.68% | 6 16.22% 91.89% | 3 8.11% 100.00% -system.ruby.L1Cache_Controller.I.Store::total 37 -system.ruby.L1Cache_Controller.I.L1_Replacement | 37007 12.51% 12.51% | 36845 12.45% 24.96% | 37094 12.54% 37.50% | 37122 12.55% 50.05% | 36827 12.45% 62.49% | 36968 12.50% 74.99% | 37098 12.54% 87.53% | 36896 12.47% 100.00% -system.ruby.L1Cache_Controller.I.L1_Replacement::total 295857 -system.ruby.L1Cache_Controller.S.Inv | 636 11.81% 11.81% | 666 12.37% 24.18% | 704 13.08% 37.26% | 712 13.22% 50.48% | 645 11.98% 62.46% | 708 13.15% 75.61% | 711 13.21% 88.82% | 602 11.18% 100.00% -system.ruby.L1Cache_Controller.S.Inv::total 5384 -system.ruby.L1Cache_Controller.S.L1_Replacement | 145 12.97% 12.97% | 146 13.06% 26.03% | 137 12.25% 38.28% | 150 13.42% 51.70% | 115 10.29% 61.99% | 141 12.61% 74.60% | 138 12.34% 86.94% | 146 13.06% 100.00% -system.ruby.L1Cache_Controller.S.L1_Replacement::total 1118 -system.ruby.L1Cache_Controller.E.Load | 1 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.E.Load::total 2 -system.ruby.L1Cache_Controller.E.Store | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.E.Store::total 2 -system.ruby.L1Cache_Controller.E.Inv | 23183 12.50% 12.50% | 23006 12.41% 24.91% | 23185 12.51% 37.42% | 23247 12.54% 49.96% | 23113 12.47% 62.42% | 23151 12.49% 74.91% | 23303 12.57% 87.48% | 23217 12.52% 100.00% -system.ruby.L1Cache_Controller.E.Inv::total 185405 -system.ruby.L1Cache_Controller.E.L1_Replacement | 26458 12.64% 12.64% | 26505 12.66% 25.30% | 26463 12.64% 37.94% | 25998 12.42% 50.36% | 26145 12.49% 62.85% | 26083 12.46% 75.31% | 25787 12.32% 87.63% | 25906 12.37% 100.00% -system.ruby.L1Cache_Controller.E.L1_Replacement::total 209345 -system.ruby.L1Cache_Controller.E.Fwd_GETX | 55 11.63% 11.63% | 61 12.90% 24.52% | 82 17.34% 41.86% | 45 9.51% 51.37% | 66 13.95% 65.33% | 43 9.09% 74.42% | 62 13.11% 87.53% | 59 12.47% 100.00% +system.ruby.ST.miss_latency_hist::samples 221682 +system.ruby.ST.miss_latency_hist::mean 2071.033142 +system.ruby.ST.miss_latency_hist::gmean 1590.656389 +system.ruby.ST.miss_latency_hist::stdev 1227.143664 +system.ruby.ST.miss_latency_hist | 58649 26.46% 26.46% | 53800 24.27% 50.73% | 52357 23.62% 74.34% | 46852 21.13% 95.48% | 9877 4.46% 99.93% | 147 0.07% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.miss_latency_hist::total 221682 +system.ruby.Directory_Controller.Fetch 617983 0.00% 0.00% +system.ruby.Directory_Controller.Data 221016 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Data 617980 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Ack 221016 0.00% 0.00% +system.ruby.Directory_Controller.CleanReplacement 396959 0.00% 0.00% +system.ruby.Directory_Controller.I.Fetch 617983 0.00% 0.00% +system.ruby.Directory_Controller.M.Data 221016 0.00% 0.00% +system.ruby.Directory_Controller.M.CleanReplacement 396959 0.00% 0.00% +system.ruby.Directory_Controller.IM.Memory_Data 617980 0.00% 0.00% +system.ruby.Directory_Controller.MI.Memory_Ack 221016 0.00% 0.00% +system.ruby.L1Cache_Controller.Load | 50178 12.48% 12.48% | 50038 12.45% 24.93% | 50231 12.49% 37.42% | 50088 12.46% 49.88% | 50377 12.53% 62.41% | 50301 12.51% 74.93% | 50175 12.48% 87.41% | 50630 12.59% 100.00% +system.ruby.L1Cache_Controller.Load::total 402018 +system.ruby.L1Cache_Controller.Store | 27650 12.47% 12.47% | 27387 12.35% 24.83% | 27627 12.46% 37.29% | 27913 12.59% 49.88% | 27862 12.57% 62.45% | 27609 12.45% 74.90% | 27807 12.54% 87.44% | 27841 12.56% 100.00% +system.ruby.L1Cache_Controller.Store::total 221696 +system.ruby.L1Cache_Controller.Inv | 75709 12.47% 12.47% | 75402 12.42% 24.89% | 75814 12.49% 37.37% | 75941 12.51% 49.88% | 76137 12.54% 62.42% | 75836 12.49% 74.91% | 76014 12.52% 87.43% | 76329 12.57% 100.00% +system.ruby.L1Cache_Controller.Inv::total 607182 +system.ruby.L1Cache_Controller.L1_Replacement | 551542 12.52% 12.52% | 547463 12.43% 24.96% | 549808 12.48% 37.44% | 549863 12.49% 49.93% | 551618 12.53% 62.45% | 550552 12.50% 74.95% | 550899 12.51% 87.46% | 552114 12.54% 100.00% +system.ruby.L1Cache_Controller.L1_Replacement::total 4403859 +system.ruby.L1Cache_Controller.Fwd_GETX | 227 12.34% 12.34% | 242 13.15% 25.49% | 244 13.26% 38.75% | 236 12.83% 51.58% | 214 11.63% 63.21% | 219 11.90% 75.11% | 224 12.17% 87.28% | 234 12.72% 100.00% +system.ruby.L1Cache_Controller.Fwd_GETX::total 1840 +system.ruby.L1Cache_Controller.Fwd_GETS | 164 12.75% 12.75% | 163 12.67% 25.43% | 176 13.69% 39.11% | 169 13.14% 52.26% | 153 11.90% 64.15% | 162 12.60% 76.75% | 161 12.52% 89.27% | 138 10.73% 100.00% +system.ruby.L1Cache_Controller.Fwd_GETS::total 1286 +system.ruby.L1Cache_Controller.Data | 4 44.44% 44.44% | 1 11.11% 55.56% | 1 11.11% 66.67% | 0 0.00% 66.67% | 1 11.11% 77.78% | 1 11.11% 88.89% | 0 0.00% 88.89% | 1 11.11% 100.00% +system.ruby.L1Cache_Controller.Data::total 9 +system.ruby.L1Cache_Controller.Data_Exclusive | 49353 12.47% 12.47% | 49226 12.44% 24.92% | 49455 12.50% 37.42% | 49297 12.46% 49.88% | 49592 12.54% 62.41% | 49499 12.51% 74.92% | 49412 12.49% 87.41% | 49794 12.59% 100.00% +system.ruby.L1Cache_Controller.Data_Exclusive::total 395628 +system.ruby.L1Cache_Controller.DataS_fromL1 | 159 12.36% 12.36% | 160 12.44% 24.81% | 147 11.43% 36.24% | 160 12.44% 48.68% | 141 10.96% 59.64% | 142 11.04% 70.68% | 173 13.45% 84.14% | 204 15.86% 100.00% +system.ruby.L1Cache_Controller.DataS_fromL1::total 1286 +system.ruby.L1Cache_Controller.Data_all_Acks | 28305 12.48% 12.48% | 28033 12.36% 24.85% | 28250 12.46% 37.30% | 28541 12.59% 49.89% | 28500 12.57% 62.46% | 28265 12.47% 74.92% | 28392 12.52% 87.45% | 28468 12.55% 100.00% +system.ruby.L1Cache_Controller.Data_all_Acks::total 226754 +system.ruby.L1Cache_Controller.Ack | 4 44.44% 44.44% | 1 11.11% 55.56% | 1 11.11% 66.67% | 0 0.00% 66.67% | 1 11.11% 77.78% | 1 11.11% 88.89% | 0 0.00% 88.89% | 1 11.11% 100.00% +system.ruby.L1Cache_Controller.Ack::total 9 +system.ruby.L1Cache_Controller.Ack_all | 4 44.44% 44.44% | 1 11.11% 55.56% | 1 11.11% 66.67% | 0 0.00% 66.67% | 1 11.11% 77.78% | 1 11.11% 88.89% | 0 0.00% 88.89% | 1 11.11% 100.00% +system.ruby.L1Cache_Controller.Ack_all::total 9 +system.ruby.L1Cache_Controller.WB_Ack | 40511 12.44% 12.44% | 40148 12.33% 24.78% | 40397 12.41% 37.18% | 40704 12.50% 49.69% | 41130 12.63% 62.32% | 40703 12.50% 74.82% | 40662 12.49% 87.31% | 41301 12.69% 100.00% +system.ruby.L1Cache_Controller.WB_Ack::total 325556 +system.ruby.L1Cache_Controller.NP.Load | 50164 12.48% 12.48% | 50032 12.45% 24.93% | 50223 12.50% 37.42% | 50076 12.46% 49.88% | 50363 12.53% 62.41% | 50292 12.51% 74.93% | 50165 12.48% 87.41% | 50615 12.59% 100.00% +system.ruby.L1Cache_Controller.NP.Load::total 401930 +system.ruby.L1Cache_Controller.NP.Store | 27646 12.47% 12.47% | 27381 12.35% 24.83% | 27620 12.46% 37.29% | 27908 12.59% 49.88% | 27857 12.57% 62.45% | 27604 12.45% 74.90% | 27800 12.54% 87.44% | 27836 12.56% 100.00% +system.ruby.L1Cache_Controller.NP.Store::total 221652 +system.ruby.L1Cache_Controller.NP.Inv | 222 13.07% 13.07% | 216 12.72% 25.80% | 227 13.37% 39.16% | 217 12.78% 51.94% | 188 11.07% 63.02% | 211 12.43% 75.44% | 216 12.72% 88.16% | 201 11.84% 100.00% +system.ruby.L1Cache_Controller.NP.Inv::total 1698 +system.ruby.L1Cache_Controller.I.Load | 10 12.99% 12.99% | 5 6.49% 19.48% | 8 10.39% 29.87% | 11 14.29% 44.16% | 13 16.88% 61.04% | 8 10.39% 71.43% | 9 11.69% 83.12% | 13 16.88% 100.00% +system.ruby.L1Cache_Controller.I.Load::total 77 +system.ruby.L1Cache_Controller.I.Store | 3 8.33% 8.33% | 4 11.11% 19.44% | 5 13.89% 33.33% | 4 11.11% 44.44% | 4 11.11% 55.56% | 5 13.89% 69.44% | 6 16.67% 86.11% | 5 13.89% 100.00% +system.ruby.L1Cache_Controller.I.Store::total 36 +system.ruby.L1Cache_Controller.I.L1_Replacement | 37148 12.52% 12.52% | 37103 12.50% 25.02% | 37284 12.56% 37.58% | 37119 12.51% 50.08% | 36952 12.45% 62.53% | 37057 12.48% 75.01% | 37155 12.52% 87.53% | 37007 12.47% 100.00% +system.ruby.L1Cache_Controller.I.L1_Replacement::total 296825 +system.ruby.L1Cache_Controller.S.Inv | 700 12.82% 12.82% | 698 12.78% 25.60% | 657 12.03% 37.64% | 666 12.20% 49.84% | 683 12.51% 62.34% | 691 12.66% 75.00% | 647 11.85% 86.85% | 718 13.15% 100.00% +system.ruby.L1Cache_Controller.S.Inv::total 5460 +system.ruby.L1Cache_Controller.S.L1_Replacement | 145 12.50% 12.50% | 157 13.53% 26.03% | 157 13.53% 39.57% | 156 13.45% 53.02% | 133 11.47% 64.48% | 131 11.29% 75.78% | 143 12.33% 88.10% | 138 11.90% 100.00% +system.ruby.L1Cache_Controller.S.L1_Replacement::total 1160 +system.ruby.L1Cache_Controller.E.Load | 1 33.33% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 1 33.33% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 1 33.33% 100.00% +system.ruby.L1Cache_Controller.E.Load::total 3 +system.ruby.L1Cache_Controller.E.Store | 1 33.33% 33.33% | 1 33.33% 66.67% | 1 33.33% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.E.Store::total 3 +system.ruby.L1Cache_Controller.E.Inv | 23165 12.45% 12.45% | 23206 12.47% 24.91% | 23518 12.64% 37.55% | 23248 12.49% 50.04% | 23136 12.43% 62.47% | 23354 12.55% 75.02% | 23312 12.52% 87.54% | 23192 12.46% 100.00% +system.ruby.L1Cache_Controller.E.Inv::total 186131 +system.ruby.L1Cache_Controller.E.L1_Replacement | 26108 12.50% 12.50% | 25954 12.42% 24.92% | 25849 12.37% 37.29% | 25977 12.43% 49.72% | 26399 12.63% 62.35% | 26084 12.48% 74.84% | 26041 12.46% 87.30% | 26535 12.70% 100.00% +system.ruby.L1Cache_Controller.E.L1_Replacement::total 208947 +system.ruby.L1Cache_Controller.E.Fwd_GETX | 70 14.80% 14.80% | 54 11.42% 26.22% | 73 15.43% 41.65% | 64 13.53% 55.18% | 47 9.94% 65.12% | 52 10.99% 76.11% | 52 10.99% 87.10% | 61 12.90% 100.00% system.ruby.L1Cache_Controller.E.Fwd_GETX::total 473 -system.ruby.L1Cache_Controller.E.Fwd_GETS | 7 12.50% 12.50% | 8 14.29% 26.79% | 13 23.21% 50.00% | 7 12.50% 62.50% | 2 3.57% 66.07% | 8 14.29% 80.36% | 6 10.71% 91.07% | 5 8.93% 100.00% -system.ruby.L1Cache_Controller.E.Fwd_GETS::total 56 -system.ruby.L1Cache_Controller.M.Load | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.M.Load::total 1 -system.ruby.L1Cache_Controller.M.Inv | 13073 12.55% 12.55% | 13053 12.53% 25.08% | 13069 12.55% 37.63% | 13057 12.54% 50.17% | 12943 12.43% 62.59% | 13016 12.50% 75.09% | 12973 12.46% 87.55% | 12971 12.45% 100.00% -system.ruby.L1Cache_Controller.M.Inv::total 104155 -system.ruby.L1Cache_Controller.M.L1_Replacement | 14723 12.62% 12.62% | 14590 12.50% 25.12% | 14535 12.46% 37.58% | 14715 12.61% 50.19% | 14444 12.38% 62.56% | 14571 12.49% 75.05% | 14650 12.55% 87.60% | 14464 12.40% 100.00% -system.ruby.L1Cache_Controller.M.L1_Replacement::total 116692 -system.ruby.L1Cache_Controller.M.Fwd_GETX | 32 12.75% 12.75% | 33 13.15% 25.90% | 27 10.76% 36.65% | 34 13.55% 50.20% | 35 13.94% 64.14% | 22 8.76% 72.91% | 37 14.74% 87.65% | 31 12.35% 100.00% -system.ruby.L1Cache_Controller.M.Fwd_GETX::total 251 -system.ruby.L1Cache_Controller.M.Fwd_GETS | 59 12.97% 12.97% | 50 10.99% 23.96% | 49 10.77% 34.73% | 60 13.19% 47.91% | 47 10.33% 58.24% | 63 13.85% 72.09% | 65 14.29% 86.37% | 62 13.63% 100.00% -system.ruby.L1Cache_Controller.M.Fwd_GETS::total 455 -system.ruby.L1Cache_Controller.IS.Inv | 43 14.29% 14.29% | 42 13.95% 28.24% | 41 13.62% 41.86% | 42 13.95% 55.81% | 40 13.29% 69.10% | 37 12.29% 81.40% | 27 8.97% 90.37% | 29 9.63% 100.00% -system.ruby.L1Cache_Controller.IS.Inv::total 301 -system.ruby.L1Cache_Controller.IS.L1_Replacement | 304064 12.49% 12.49% | 304172 12.50% 24.99% | 306684 12.60% 37.59% | 302971 12.45% 50.03% | 304022 12.49% 62.52% | 303629 12.47% 74.99% | 303562 12.47% 87.47% | 305131 12.53% 100.00% -system.ruby.L1Cache_Controller.IS.L1_Replacement::total 2434235 -system.ruby.L1Cache_Controller.IS.Data_Exclusive | 49704 12.57% 12.57% | 49580 12.54% 25.12% | 49744 12.58% 37.70% | 49297 12.47% 50.17% | 49326 12.48% 62.65% | 49286 12.47% 75.12% | 49158 12.44% 87.56% | 49187 12.44% 100.00% -system.ruby.L1Cache_Controller.IS.Data_Exclusive::total 395282 -system.ruby.L1Cache_Controller.IS.DataS_fromL1 | 145 11.82% 11.82% | 148 12.06% 23.88% | 165 13.45% 37.33% | 168 13.69% 51.02% | 139 11.33% 62.35% | 164 13.37% 75.71% | 161 13.12% 88.83% | 137 11.17% 100.00% -system.ruby.L1Cache_Controller.IS.DataS_fromL1::total 1227 -system.ruby.L1Cache_Controller.IS.Data_all_Acks | 570 11.96% 11.96% | 606 12.72% 24.69% | 614 12.89% 37.57% | 627 13.16% 50.73% | 572 12.01% 62.74% | 614 12.89% 75.63% | 617 12.95% 88.58% | 544 11.42% 100.00% -system.ruby.L1Cache_Controller.IS.Data_all_Acks::total 4764 -system.ruby.L1Cache_Controller.IM.L1_Replacement | 167965 12.51% 12.51% | 168119 12.52% 25.02% | 166558 12.40% 37.42% | 169005 12.58% 50.01% | 167246 12.45% 62.46% | 168087 12.51% 74.97% | 169524 12.62% 87.59% | 166627 12.41% 100.00% -system.ruby.L1Cache_Controller.IM.L1_Replacement::total 1343131 -system.ruby.L1Cache_Controller.IM.Data | 2 13.33% 13.33% | 5 33.33% 46.67% | 1 6.67% 53.33% | 3 20.00% 73.33% | 0 0.00% 73.33% | 1 6.67% 80.00% | 2 13.33% 93.33% | 1 6.67% 100.00% -system.ruby.L1Cache_Controller.IM.Data::total 15 -system.ruby.L1Cache_Controller.IM.Data_all_Acks | 27885 12.59% 12.59% | 27721 12.51% 25.10% | 27678 12.49% 37.59% | 27863 12.58% 50.17% | 27469 12.40% 62.57% | 27670 12.49% 75.06% | 27723 12.51% 87.57% | 27528 12.43% 100.00% -system.ruby.L1Cache_Controller.IM.Data_all_Acks::total 221537 -system.ruby.L1Cache_Controller.SM.Ack | 2 13.33% 13.33% | 5 33.33% 46.67% | 1 6.67% 53.33% | 3 20.00% 73.33% | 0 0.00% 73.33% | 1 6.67% 80.00% | 2 13.33% 93.33% | 1 6.67% 100.00% -system.ruby.L1Cache_Controller.SM.Ack::total 15 -system.ruby.L1Cache_Controller.SM.Ack_all | 2 13.33% 13.33% | 5 33.33% 46.67% | 1 6.67% 53.33% | 3 20.00% 73.33% | 0 0.00% 73.33% | 1 6.67% 80.00% | 2 13.33% 93.33% | 1 6.67% 100.00% -system.ruby.L1Cache_Controller.SM.Ack_all::total 15 -system.ruby.L1Cache_Controller.IS_I.Data_all_Acks | 43 14.29% 14.29% | 42 13.95% 28.24% | 41 13.62% 41.86% | 42 13.95% 55.81% | 40 13.29% 69.10% | 37 12.29% 81.40% | 27 8.97% 90.37% | 29 9.63% 100.00% -system.ruby.L1Cache_Controller.IS_I.Data_all_Acks::total 301 -system.ruby.L1Cache_Controller.M_I.Inv | 39119 12.59% 12.59% | 39097 12.58% 25.17% | 39212 12.62% 37.78% | 38822 12.49% 50.27% | 38731 12.46% 62.73% | 38817 12.49% 75.22% | 38456 12.37% 87.60% | 38549 12.40% 100.00% -system.ruby.L1Cache_Controller.M_I.Inv::total 310803 -system.ruby.L1Cache_Controller.M_I.Fwd_GETX | 161 15.48% 15.48% | 143 13.75% 29.23% | 105 10.10% 39.33% | 127 12.21% 51.54% | 128 12.31% 63.85% | 119 11.44% 75.29% | 141 13.56% 88.85% | 116 11.15% 100.00% -system.ruby.L1Cache_Controller.M_I.Fwd_GETX::total 1040 -system.ruby.L1Cache_Controller.M_I.Fwd_GETS | 107 14.94% 14.94% | 102 14.25% 29.19% | 91 12.71% 41.90% | 73 10.20% 52.09% | 87 12.15% 64.25% | 87 12.15% 76.40% | 80 11.17% 87.57% | 89 12.43% 100.00% -system.ruby.L1Cache_Controller.M_I.Fwd_GETS::total 716 -system.ruby.L1Cache_Controller.M_I.WB_Ack | 1794 13.31% 13.31% | 1753 13.01% 26.32% | 1590 11.80% 38.11% | 1691 12.55% 50.66% | 1643 12.19% 62.85% | 1631 12.10% 74.95% | 1760 13.06% 88.01% | 1616 11.99% 100.00% -system.ruby.L1Cache_Controller.M_I.WB_Ack::total 13478 -system.ruby.L1Cache_Controller.SINK_WB_ACK.Load | 2 33.33% 33.33% | 1 16.67% 50.00% | 2 33.33% 83.33% | 1 16.67% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.SINK_WB_ACK.Load::total 6 -system.ruby.L1Cache_Controller.SINK_WB_ACK.Store | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 2 50.00% 50.00% | 0 0.00% 50.00% | 2 50.00% 100.00% -system.ruby.L1Cache_Controller.SINK_WB_ACK.Store::total 4 -system.ruby.L1Cache_Controller.SINK_WB_ACK.Inv | 30 15.46% 15.46% | 29 14.95% 30.41% | 28 14.43% 44.85% | 18 9.28% 54.12% | 19 9.79% 63.92% | 25 12.89% 76.80% | 21 10.82% 87.63% | 24 12.37% 100.00% -system.ruby.L1Cache_Controller.SINK_WB_ACK.Inv::total 194 -system.ruby.L1Cache_Controller.SINK_WB_ACK.WB_Ack | 39384 12.60% 12.60% | 39340 12.59% 25.19% | 39407 12.61% 37.80% | 39022 12.49% 50.28% | 38944 12.46% 62.74% | 39022 12.49% 75.23% | 38675 12.37% 87.60% | 38753 12.40% 100.00% -system.ruby.L1Cache_Controller.SINK_WB_ACK.WB_Ack::total 312547 -system.ruby.L2Cache_Controller.L1_GETS 403170 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_GETX 223814 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_PUTX 15467 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_PUTX_old 317914 0.00% 0.00% -system.ruby.L2Cache_Controller.L2_Replacement 6156 0.00% 0.00% -system.ruby.L2Cache_Controller.L2_Replacement_clean 4979199 0.00% 0.00% -system.ruby.L2Cache_Controller.Mem_Data 617573 0.00% 0.00% -system.ruby.L2Cache_Controller.Mem_Ack 617568 0.00% 0.00% -system.ruby.L2Cache_Controller.WB_Data 216108 0.00% 0.00% -system.ruby.L2Cache_Controller.WB_Data_clean 200077 0.00% 0.00% -system.ruby.L2Cache_Controller.Ack 3751 0.00% 0.00% -system.ruby.L2Cache_Controller.Ack_all 189142 0.00% 0.00% -system.ruby.L2Cache_Controller.Unblock 1227 0.00% 0.00% -system.ruby.L2Cache_Controller.Exclusive_Unblock 616832 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.L1_GETS 397804 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.L1_GETX 219774 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.L1_PUTX_old 308614 0.00% 0.00% -system.ruby.L2Cache_Controller.SS.L1_GETS 7 0.00% 0.00% -system.ruby.L2Cache_Controller.SS.L1_GETX 15 0.00% 0.00% -system.ruby.L2Cache_Controller.SS.L1_PUTX 527 0.00% 0.00% -system.ruby.L2Cache_Controller.SS.L1_PUTX_old 1 0.00% 0.00% -system.ruby.L2Cache_Controller.SS.L2_Replacement 1153 0.00% 0.00% -system.ruby.L2Cache_Controller.SS.L2_Replacement_clean 2585 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L1_GETS 6 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L1_GETX 3 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L2_Replacement 4818 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L2_Replacement_clean 8651 0.00% 0.00% -system.ruby.L2Cache_Controller.MT.L1_GETS 1227 0.00% 0.00% -system.ruby.L2Cache_Controller.MT.L1_GETX 1764 0.00% 0.00% -system.ruby.L2Cache_Controller.MT.L1_PUTX 13478 0.00% 0.00% -system.ruby.L2Cache_Controller.MT.L1_PUTX_old 808 0.00% 0.00% -system.ruby.L2Cache_Controller.MT.L2_Replacement 6 0.00% 0.00% -system.ruby.L2Cache_Controller.MT.L2_Replacement_clean 600357 0.00% 0.00% -system.ruby.L2Cache_Controller.M_I.L1_GETS 25 0.00% 0.00% -system.ruby.L2Cache_Controller.M_I.L1_GETX 20 0.00% 0.00% -system.ruby.L2Cache_Controller.M_I.L1_PUTX_old 2036 0.00% 0.00% -system.ruby.L2Cache_Controller.M_I.Mem_Ack 617568 0.00% 0.00% +system.ruby.L1Cache_Controller.E.Fwd_GETS | 9 12.50% 12.50% | 10 13.89% 26.39% | 14 19.44% 45.83% | 8 11.11% 56.94% | 9 12.50% 69.44% | 9 12.50% 81.94% | 7 9.72% 91.67% | 6 8.33% 100.00% +system.ruby.L1Cache_Controller.E.Fwd_GETS::total 72 +system.ruby.L1Cache_Controller.M.Load | 1 33.33% 33.33% | 1 33.33% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 1 33.33% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.M.Load::total 3 +system.ruby.L1Cache_Controller.M.Inv | 13157 12.61% 12.61% | 13076 12.54% 25.15% | 12978 12.44% 37.59% | 13085 12.55% 50.14% | 13028 12.49% 62.63% | 12904 12.37% 75.00% | 13083 12.54% 87.54% | 12992 12.46% 100.00% +system.ruby.L1Cache_Controller.M.Inv::total 104303 +system.ruby.L1Cache_Controller.M.L1_Replacement | 14405 12.35% 12.35% | 14195 12.17% 24.52% | 14549 12.48% 37.00% | 14728 12.63% 49.63% | 14732 12.63% 62.26% | 14620 12.54% 74.80% | 14622 12.54% 87.34% | 14767 12.66% 100.00% +system.ruby.L1Cache_Controller.M.L1_Replacement::total 116618 +system.ruby.L1Cache_Controller.M.Fwd_GETX | 27 9.96% 9.96% | 47 17.34% 27.31% | 32 11.81% 39.11% | 31 11.44% 50.55% | 35 12.92% 63.47% | 32 11.81% 75.28% | 37 13.65% 88.93% | 30 11.07% 100.00% +system.ruby.L1Cache_Controller.M.Fwd_GETX::total 271 +system.ruby.L1Cache_Controller.M.Fwd_GETS | 61 12.37% 12.37% | 67 13.59% 25.96% | 66 13.39% 39.35% | 67 13.59% 52.94% | 66 13.39% 66.33% | 53 10.75% 77.08% | 62 12.58% 89.66% | 51 10.34% 100.00% +system.ruby.L1Cache_Controller.M.Fwd_GETS::total 493 +system.ruby.L1Cache_Controller.IS.Inv | 44 14.10% 14.10% | 32 10.26% 24.36% | 40 12.82% 37.18% | 43 13.78% 50.96% | 40 12.82% 63.78% | 39 12.50% 76.28% | 40 12.82% 89.10% | 34 10.90% 100.00% +system.ruby.L1Cache_Controller.IS.Inv::total 312 +system.ruby.L1Cache_Controller.IS.L1_Replacement | 304930 12.52% 12.52% | 304677 12.51% 25.03% | 304555 12.50% 37.53% | 302791 12.43% 49.96% | 304661 12.51% 62.47% | 304322 12.49% 74.97% | 304505 12.50% 87.47% | 305212 12.53% 100.00% +system.ruby.L1Cache_Controller.IS.L1_Replacement::total 2435653 +system.ruby.L1Cache_Controller.IS.Data_Exclusive | 49353 12.47% 12.47% | 49226 12.44% 24.92% | 49455 12.50% 37.42% | 49297 12.46% 49.88% | 49592 12.54% 62.41% | 49499 12.51% 74.92% | 49412 12.49% 87.41% | 49794 12.59% 100.00% +system.ruby.L1Cache_Controller.IS.Data_Exclusive::total 395628 +system.ruby.L1Cache_Controller.IS.DataS_fromL1 | 159 12.36% 12.36% | 160 12.44% 24.81% | 147 11.43% 36.24% | 160 12.44% 48.68% | 141 10.96% 59.64% | 142 11.04% 70.68% | 173 13.45% 84.14% | 204 15.86% 100.00% +system.ruby.L1Cache_Controller.IS.DataS_fromL1::total 1286 +system.ruby.L1Cache_Controller.IS.Data_all_Acks | 616 12.92% 12.92% | 618 12.96% 25.88% | 587 12.31% 38.18% | 587 12.31% 50.49% | 600 12.58% 63.07% | 618 12.96% 76.03% | 548 11.49% 87.52% | 595 12.48% 100.00% +system.ruby.L1Cache_Controller.IS.Data_all_Acks::total 4769 +system.ruby.L1Cache_Controller.IM.L1_Replacement | 168806 12.55% 12.55% | 165377 12.30% 24.85% | 167414 12.45% 37.30% | 169092 12.58% 49.88% | 168741 12.55% 62.43% | 168337 12.52% 74.95% | 168433 12.53% 87.47% | 168454 12.53% 100.00% +system.ruby.L1Cache_Controller.IM.L1_Replacement::total 1344654 +system.ruby.L1Cache_Controller.IM.Data | 4 44.44% 44.44% | 1 11.11% 55.56% | 1 11.11% 66.67% | 0 0.00% 66.67% | 1 11.11% 77.78% | 1 11.11% 88.89% | 0 0.00% 88.89% | 1 11.11% 100.00% +system.ruby.L1Cache_Controller.IM.Data::total 9 +system.ruby.L1Cache_Controller.IM.Data_all_Acks | 27645 12.47% 12.47% | 27383 12.35% 24.82% | 27623 12.46% 37.29% | 27911 12.59% 49.88% | 27860 12.57% 62.44% | 27608 12.45% 74.90% | 27804 12.54% 87.44% | 27839 12.56% 100.00% +system.ruby.L1Cache_Controller.IM.Data_all_Acks::total 221673 +system.ruby.L1Cache_Controller.SM.L1_Replacement | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% +system.ruby.L1Cache_Controller.SM.L1_Replacement::total 1 +system.ruby.L1Cache_Controller.SM.Ack | 4 44.44% 44.44% | 1 11.11% 55.56% | 1 11.11% 66.67% | 0 0.00% 66.67% | 1 11.11% 77.78% | 1 11.11% 88.89% | 0 0.00% 88.89% | 1 11.11% 100.00% +system.ruby.L1Cache_Controller.SM.Ack::total 9 +system.ruby.L1Cache_Controller.SM.Ack_all | 4 44.44% 44.44% | 1 11.11% 55.56% | 1 11.11% 66.67% | 0 0.00% 66.67% | 1 11.11% 77.78% | 1 11.11% 88.89% | 0 0.00% 88.89% | 1 11.11% 100.00% +system.ruby.L1Cache_Controller.SM.Ack_all::total 9 +system.ruby.L1Cache_Controller.IS_I.L1_Replacement | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.IS_I.L1_Replacement::total 1 +system.ruby.L1Cache_Controller.IS_I.Data_all_Acks | 44 14.10% 14.10% | 32 10.26% 24.36% | 40 12.82% 37.18% | 43 13.78% 50.96% | 40 12.82% 63.78% | 39 12.50% 76.28% | 40 12.82% 89.10% | 34 10.90% 100.00% +system.ruby.L1Cache_Controller.IS_I.Data_all_Acks::total 312 +system.ruby.L1Cache_Controller.M_I.Inv | 38404 12.42% 12.42% | 38147 12.34% 24.77% | 38368 12.41% 37.18% | 38649 12.50% 49.68% | 39039 12.63% 62.31% | 38617 12.49% 74.81% | 38697 12.52% 87.33% | 39174 12.67% 100.00% +system.ruby.L1Cache_Controller.M_I.Inv::total 309095 +system.ruby.L1Cache_Controller.M_I.Fwd_GETX | 130 11.86% 11.86% | 141 12.86% 24.73% | 139 12.68% 37.41% | 141 12.86% 50.27% | 132 12.04% 62.32% | 135 12.32% 74.64% | 135 12.32% 86.95% | 143 13.05% 100.00% +system.ruby.L1Cache_Controller.M_I.Fwd_GETX::total 1096 +system.ruby.L1Cache_Controller.M_I.Fwd_GETS | 94 13.04% 13.04% | 86 11.93% 24.97% | 96 13.31% 38.28% | 94 13.04% 51.32% | 78 10.82% 62.14% | 100 13.87% 76.01% | 92 12.76% 88.77% | 81 11.23% 100.00% +system.ruby.L1Cache_Controller.M_I.Fwd_GETS::total 721 +system.ruby.L1Cache_Controller.M_I.WB_Ack | 1885 12.86% 12.86% | 1775 12.11% 24.98% | 1795 12.25% 37.23% | 1821 12.43% 49.66% | 1882 12.84% 62.50% | 1852 12.64% 75.14% | 1739 11.87% 87.01% | 1904 12.99% 100.00% +system.ruby.L1Cache_Controller.M_I.WB_Ack::total 14653 +system.ruby.L1Cache_Controller.SINK_WB_ACK.Load | 2 40.00% 40.00% | 0 0.00% 40.00% | 0 0.00% 40.00% | 0 0.00% 40.00% | 1 20.00% 60.00% | 0 0.00% 60.00% | 1 20.00% 80.00% | 1 20.00% 100.00% +system.ruby.L1Cache_Controller.SINK_WB_ACK.Load::total 5 +system.ruby.L1Cache_Controller.SINK_WB_ACK.Store | 0 0.00% 0.00% | 1 20.00% 20.00% | 1 20.00% 40.00% | 1 20.00% 60.00% | 1 20.00% 80.00% | 0 0.00% 80.00% | 1 20.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.SINK_WB_ACK.Store::total 5 +system.ruby.L1Cache_Controller.SINK_WB_ACK.Inv | 17 9.29% 9.29% | 27 14.75% 24.04% | 26 14.21% 38.25% | 33 18.03% 56.28% | 23 12.57% 68.85% | 20 10.93% 79.78% | 19 10.38% 90.16% | 18 9.84% 100.00% +system.ruby.L1Cache_Controller.SINK_WB_ACK.Inv::total 183 +system.ruby.L1Cache_Controller.SINK_WB_ACK.WB_Ack | 38626 12.42% 12.42% | 38373 12.34% 24.77% | 38602 12.42% 37.18% | 38883 12.51% 49.69% | 39248 12.62% 62.31% | 38851 12.50% 74.81% | 38923 12.52% 87.33% | 39397 12.67% 100.00% +system.ruby.L1Cache_Controller.SINK_WB_ACK.WB_Ack::total 310903 +system.ruby.L2Cache_Controller.L1_GETS 403619 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_GETX 224049 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_PUTX 16718 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_PUTX_old 316360 0.00% 0.00% +system.ruby.L2Cache_Controller.L2_Replacement 6791 0.00% 0.00% +system.ruby.L2Cache_Controller.L2_Replacement_clean 4927098 0.00% 0.00% +system.ruby.L2Cache_Controller.Mem_Data 617978 0.00% 0.00% +system.ruby.L2Cache_Controller.Mem_Ack 617975 0.00% 0.00% +system.ruby.L2Cache_Controller.WB_Data 215635 0.00% 0.00% +system.ruby.L2Cache_Controller.WB_Data_clean 199049 0.00% 0.00% +system.ruby.L2Cache_Controller.Ack 3824 0.00% 0.00% +system.ruby.L2Cache_Controller.Ack_all 189942 0.00% 0.00% +system.ruby.L2Cache_Controller.Unblock 1286 0.00% 0.00% +system.ruby.L2Cache_Controller.Exclusive_Unblock 617309 0.00% 0.00% +system.ruby.L2Cache_Controller.NP.L1_GETS 398157 0.00% 0.00% +system.ruby.L2Cache_Controller.NP.L1_GETX 219826 0.00% 0.00% +system.ruby.L2Cache_Controller.NP.L1_PUTX_old 306767 0.00% 0.00% +system.ruby.L2Cache_Controller.SS.L1_GETS 3 0.00% 0.00% +system.ruby.L2Cache_Controller.SS.L1_GETX 9 0.00% 0.00% +system.ruby.L2Cache_Controller.SS.L1_PUTX 543 0.00% 0.00% +system.ruby.L2Cache_Controller.SS.L1_PUTX_old 5 0.00% 0.00% +system.ruby.L2Cache_Controller.SS.L2_Replacement 1199 0.00% 0.00% +system.ruby.L2Cache_Controller.SS.L2_Replacement_clean 2612 0.00% 0.00% +system.ruby.L2Cache_Controller.M.L1_GETS 10 0.00% 0.00% +system.ruby.L2Cache_Controller.M.L1_GETX 8 0.00% 0.00% +system.ruby.L2Cache_Controller.M.L2_Replacement 5381 0.00% 0.00% +system.ruby.L2Cache_Controller.M.L2_Replacement_clean 9254 0.00% 0.00% +system.ruby.L2Cache_Controller.MT.L1_GETS 1286 0.00% 0.00% +system.ruby.L2Cache_Controller.MT.L1_GETX 1840 0.00% 0.00% +system.ruby.L2Cache_Controller.MT.L1_PUTX 14653 0.00% 0.00% +system.ruby.L2Cache_Controller.MT.L1_PUTX_old 832 0.00% 0.00% +system.ruby.L2Cache_Controller.MT.L2_Replacement 7 0.00% 0.00% +system.ruby.L2Cache_Controller.MT.L2_Replacement_clean 599522 0.00% 0.00% +system.ruby.L2Cache_Controller.M_I.L1_GETS 21 0.00% 0.00% +system.ruby.L2Cache_Controller.M_I.L1_GETX 13 0.00% 0.00% +system.ruby.L2Cache_Controller.M_I.L1_PUTX_old 2174 0.00% 0.00% +system.ruby.L2Cache_Controller.M_I.Mem_Ack 617975 0.00% 0.00% system.ruby.L2Cache_Controller.MT_I.WB_Data 4 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_I.Ack_all 2 0.00% 0.00% -system.ruby.L2Cache_Controller.MCT_I.L1_GETS 53 0.00% 0.00% -system.ruby.L2Cache_Controller.MCT_I.L1_GETX 65 0.00% 0.00% -system.ruby.L2Cache_Controller.MCT_I.L1_PUTX_old 5892 0.00% 0.00% -system.ruby.L2Cache_Controller.MCT_I.WB_Data 214948 0.00% 0.00% -system.ruby.L2Cache_Controller.MCT_I.WB_Data_clean 200006 0.00% 0.00% -system.ruby.L2Cache_Controller.MCT_I.Ack_all 185402 0.00% 0.00% -system.ruby.L2Cache_Controller.I_I.L1_GETX 1 0.00% 0.00% -system.ruby.L2Cache_Controller.I_I.Ack 2592 0.00% 0.00% -system.ruby.L2Cache_Controller.I_I.Ack_all 2585 0.00% 0.00% -system.ruby.L2Cache_Controller.S_I.Ack 1159 0.00% 0.00% -system.ruby.L2Cache_Controller.S_I.Ack_all 1153 0.00% 0.00% -system.ruby.L2Cache_Controller.ISS.L1_GETS 2526 0.00% 0.00% -system.ruby.L2Cache_Controller.ISS.L1_GETX 1358 0.00% 0.00% -system.ruby.L2Cache_Controller.ISS.L1_PUTX_old 290 0.00% 0.00% -system.ruby.L2Cache_Controller.ISS.L2_Replacement_clean 2188495 0.00% 0.00% -system.ruby.L2Cache_Controller.ISS.Mem_Data 395276 0.00% 0.00% -system.ruby.L2Cache_Controller.IS.L1_GETS 6 0.00% 0.00% -system.ruby.L2Cache_Controller.IS.L1_GETX 8 0.00% 0.00% -system.ruby.L2Cache_Controller.IS.L2_Replacement_clean 14199 0.00% 0.00% -system.ruby.L2Cache_Controller.IS.Mem_Data 2526 0.00% 0.00% -system.ruby.L2Cache_Controller.IM.L1_GETS 1376 0.00% 0.00% -system.ruby.L2Cache_Controller.IM.L1_GETX 726 0.00% 0.00% -system.ruby.L2Cache_Controller.IM.L1_PUTX_old 271 0.00% 0.00% -system.ruby.L2Cache_Controller.IM.L2_Replacement_clean 1222032 0.00% 0.00% -system.ruby.L2Cache_Controller.IM.Mem_Data 219771 0.00% 0.00% -system.ruby.L2Cache_Controller.SS_MB.L1_GETX 1 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_I.Ack_all 3 0.00% 0.00% +system.ruby.L2Cache_Controller.MCT_I.L1_GETS 62 0.00% 0.00% +system.ruby.L2Cache_Controller.MCT_I.L1_GETX 79 0.00% 0.00% +system.ruby.L2Cache_Controller.MCT_I.L1_PUTX_old 5995 0.00% 0.00% +system.ruby.L2Cache_Controller.MCT_I.WB_Data 214429 0.00% 0.00% +system.ruby.L2Cache_Controller.MCT_I.WB_Data_clean 198965 0.00% 0.00% +system.ruby.L2Cache_Controller.MCT_I.Ack_all 186128 0.00% 0.00% +system.ruby.L2Cache_Controller.I_I.Ack 2623 0.00% 0.00% +system.ruby.L2Cache_Controller.I_I.Ack_all 2612 0.00% 0.00% +system.ruby.L2Cache_Controller.S_I.Ack 1201 0.00% 0.00% +system.ruby.L2Cache_Controller.S_I.Ack_all 1199 0.00% 0.00% +system.ruby.L2Cache_Controller.ISS.L1_GETS 2534 0.00% 0.00% +system.ruby.L2Cache_Controller.ISS.L1_GETX 1425 0.00% 0.00% +system.ruby.L2Cache_Controller.ISS.L1_PUTX_old 281 0.00% 0.00% +system.ruby.L2Cache_Controller.ISS.L2_Replacement_clean 2159388 0.00% 0.00% +system.ruby.L2Cache_Controller.ISS.Mem_Data 395619 0.00% 0.00% +system.ruby.L2Cache_Controller.IS.L1_GETS 10 0.00% 0.00% +system.ruby.L2Cache_Controller.IS.L1_GETX 5 0.00% 0.00% +system.ruby.L2Cache_Controller.IS.L1_PUTX_old 1 0.00% 0.00% +system.ruby.L2Cache_Controller.IS.L2_Replacement_clean 14164 0.00% 0.00% +system.ruby.L2Cache_Controller.IS.Mem_Data 2534 0.00% 0.00% +system.ruby.L2Cache_Controller.IM.L1_GETS 1405 0.00% 0.00% +system.ruby.L2Cache_Controller.IM.L1_GETX 765 0.00% 0.00% +system.ruby.L2Cache_Controller.IM.L1_PUTX_old 299 0.00% 0.00% +system.ruby.L2Cache_Controller.IM.L2_Replacement_clean 1198508 0.00% 0.00% +system.ruby.L2Cache_Controller.IM.Mem_Data 219825 0.00% 0.00% system.ruby.L2Cache_Controller.SS_MB.L1_PUTX 2 0.00% 0.00% -system.ruby.L2Cache_Controller.SS_MB.L2_Replacement 20 0.00% 0.00% -system.ruby.L2Cache_Controller.SS_MB.L2_Replacement_clean 21 0.00% 0.00% -system.ruby.L2Cache_Controller.SS_MB.Exclusive_Unblock 15 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_MB.L1_GETS 135 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_MB.L1_GETX 77 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_MB.L1_PUTX 875 0.00% 0.00% +system.ruby.L2Cache_Controller.SS_MB.L2_Replacement_clean 10 0.00% 0.00% +system.ruby.L2Cache_Controller.SS_MB.Exclusive_Unblock 9 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_MB.L1_GETS 129 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_MB.L1_GETX 76 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_MB.L1_PUTX 921 0.00% 0.00% system.ruby.L2Cache_Controller.MT_MB.L1_PUTX_old 1 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_MB.L2_Replacement_clean 939983 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_MB.Exclusive_Unblock 616817 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_IIB.L1_GETS 5 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_IIB.L1_GETX 2 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_IIB.L1_PUTX 585 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_IIB.L1_PUTX_old 1 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_IIB.L2_Replacement_clean 2874 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_IIB.WB_Data 956 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_IIB.WB_Data_clean 45 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_IIB.Unblock 226 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_MB.L2_Replacement_clean 940845 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_MB.Exclusive_Unblock 617300 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_IIB.L1_GETS 2 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_IIB.L1_GETX 3 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_IIB.L1_PUTX 598 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_IIB.L1_PUTX_old 5 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_IIB.L2_Replacement_clean 2788 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_IIB.WB_Data 1020 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_IIB.WB_Data_clean 64 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_IIB.Unblock 202 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_IB.L1_PUTX 1 0.00% 0.00% system.ruby.L2Cache_Controller.MT_IB.L2_Replacement_clean 2 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_IB.WB_Data 200 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_IB.WB_Data_clean 26 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_SB.L2_Replacement 159 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_SB.Unblock 1001 0.00% 0.00% -system.ruby.Directory_Controller.Fetch 617577 0.00% 0.00% -system.ruby.Directory_Controller.Data 220925 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Data 617573 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Ack 220924 0.00% 0.00% -system.ruby.Directory_Controller.CleanReplacement 396644 0.00% 0.00% -system.ruby.Directory_Controller.I.Fetch 617577 0.00% 0.00% -system.ruby.Directory_Controller.M.Data 220925 0.00% 0.00% -system.ruby.Directory_Controller.M.CleanReplacement 396644 0.00% 0.00% -system.ruby.Directory_Controller.IM.Memory_Data 617573 0.00% 0.00% -system.ruby.Directory_Controller.MI.Memory_Ack 220924 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_IB.WB_Data 182 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_IB.WB_Data_clean 20 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_SB.L2_Replacement 204 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_SB.L2_Replacement_clean 5 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_SB.Unblock 1084 0.00% 0.00% ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt index f39ff9113..d7e27dd2b 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt @@ -1,48 +1,48 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.007458 # Number of seconds simulated -sim_ticks 7457946 # Number of ticks simulated -final_tick 7457946 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.007401 # Number of seconds simulated +sim_ticks 7400590 # Number of ticks simulated +final_tick 7400590 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 41657 # Simulator tick rate (ticks/s) -host_mem_usage 653376 # Number of bytes of host memory used -host_seconds 179.03 # Real time elapsed on the host +host_tick_rate 58553 # Simulator tick rate (ticks/s) +host_mem_usage 666564 # Number of bytes of host memory used +host_seconds 126.39 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks -system.mem_ctrls.bytes_read::ruby.dir_cntrl0 39482368 # Number of bytes read from this memory -system.mem_ctrls.bytes_read::total 39482368 # Number of bytes read from this memory -system.mem_ctrls.bytes_written::ruby.dir_cntrl0 14237568 # Number of bytes written to this memory -system.mem_ctrls.bytes_written::total 14237568 # Number of bytes written to this memory -system.mem_ctrls.num_reads::ruby.dir_cntrl0 616912 # Number of read requests responded to by this memory -system.mem_ctrls.num_reads::total 616912 # Number of read requests responded to by this memory -system.mem_ctrls.num_writes::ruby.dir_cntrl0 222462 # Number of write requests responded to by this memory -system.mem_ctrls.num_writes::total 222462 # Number of write requests responded to by this memory -system.mem_ctrls.bw_read::ruby.dir_cntrl0 5294000252 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_read::total 5294000252 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::ruby.dir_cntrl0 1909046807 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::total 1909046807 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_total::ruby.dir_cntrl0 7203047059 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.bw_total::total 7203047059 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.readReqs 616927 # Number of read requests accepted -system.mem_ctrls.writeReqs 222462 # Number of write requests accepted -system.mem_ctrls.readBursts 616927 # Number of DRAM read bursts, including those serviced by the write queue -system.mem_ctrls.writeBursts 222462 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrls.bytesReadDRAM 39007104 # Total number of bytes read from DRAM -system.mem_ctrls.bytesReadWrQ 475904 # Total number of bytes read from write queue -system.mem_ctrls.bytesWritten 14151616 # Total number of bytes written to DRAM -system.mem_ctrls.bytesReadSys 39483328 # Total read bytes from the system interface side -system.mem_ctrls.bytesWrittenSys 14237568 # Total written bytes from the system interface side -system.mem_ctrls.servicedByWrQ 7436 # Number of DRAM read bursts serviced by the write queue -system.mem_ctrls.mergedWrBursts 1325 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.bytes_read::ruby.dir_cntrl0 39203584 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 39203584 # Number of bytes read from this memory +system.mem_ctrls.bytes_written::ruby.dir_cntrl0 14074880 # Number of bytes written to this memory +system.mem_ctrls.bytes_written::total 14074880 # Number of bytes written to this memory +system.mem_ctrls.num_reads::ruby.dir_cntrl0 612556 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 612556 # Number of read requests responded to by this memory +system.mem_ctrls.num_writes::ruby.dir_cntrl0 219920 # Number of write requests responded to by this memory +system.mem_ctrls.num_writes::total 219920 # Number of write requests responded to by this memory +system.mem_ctrls.bw_read::ruby.dir_cntrl0 5297359265 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 5297359265 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::ruby.dir_cntrl0 1901859176 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::total 1901859176 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::ruby.dir_cntrl0 7199218441 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 7199218441 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.readReqs 612559 # Number of read requests accepted +system.mem_ctrls.writeReqs 219920 # Number of write requests accepted +system.mem_ctrls.readBursts 612559 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.writeBursts 219920 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrls.bytesReadDRAM 38724800 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 478976 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 13992640 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadSys 39203776 # Total read bytes from the system interface side +system.mem_ctrls.bytesWrittenSys 14074880 # Total written bytes from the system interface side +system.mem_ctrls.servicedByWrQ 7484 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 1262 # Number of DRAM write bursts merged with an existing one system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.mem_ctrls.perBankRdBursts::0 75997 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::1 76905 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::2 76170 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::3 76019 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::4 75858 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::5 76406 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::6 76286 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::7 75845 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::0 75565 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::1 75507 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::2 76076 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 75946 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 75488 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::5 75399 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::6 75818 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 75276 # Per bank write bursts system.mem_ctrls.perBankRdBursts::8 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::9 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::10 0 # Per bank write bursts @@ -51,14 +51,14 @@ system.mem_ctrls.perBankRdBursts::12 0 # Pe system.mem_ctrls.perBankRdBursts::13 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::14 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::15 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::0 27808 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::1 27927 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::2 27526 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::3 27488 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::4 27638 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::5 27575 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::6 27643 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::7 27514 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 27473 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::1 27140 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::2 27430 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 27423 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 27483 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 27208 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::6 27363 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::7 27115 # Per bank write bursts system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::10 0 # Per bank write bursts @@ -69,53 +69,53 @@ system.mem_ctrls.perBankWrBursts::14 0 # Pe system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrls.totGap 7457887 # Total gap between requests +system.mem_ctrls.totGap 7400487 # Total gap between requests system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::6 616927 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 612559 # Read request sizes (log2) system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::6 222462 # Write request sizes (log2) -system.mem_ctrls.rdQLenPdf::0 30785 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::1 21417 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::2 21169 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::3 21106 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::4 21067 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::5 21112 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::6 21130 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::7 21129 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::8 21188 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::9 21211 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::10 21220 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::11 21236 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::12 21233 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::13 21196 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::14 21132 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::15 21007 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::16 20933 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::17 20875 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::18 21426 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::19 23339 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::20 20555 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::21 20518 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::22 20705 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::23 21149 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::24 19529 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::25 18708 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::26 17249 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::27 14885 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::28 11036 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::29 6781 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::30 2902 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::31 563 # What read queue length does an incoming req see +system.mem_ctrls.writePktSize::6 219920 # Write request sizes (log2) +system.mem_ctrls.rdQLenPdf::0 30831 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::1 21254 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::2 20948 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::3 20951 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::4 20894 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::5 20888 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::6 20929 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::7 20953 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::8 20953 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::9 20973 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::10 20986 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::11 20998 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::12 20977 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::13 20956 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::14 20940 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::15 20847 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::16 20708 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::17 20691 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::18 21299 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::19 23250 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::20 20406 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::21 20378 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::22 20586 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::23 21073 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::24 19388 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::25 18654 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::26 17262 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::27 14777 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::28 11043 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::29 6825 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::30 2889 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::31 568 # What read queue length does an incoming req see system.mem_ctrls.wrQLenPdf::0 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::1 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::2 1 # What write queue length does an incoming req see @@ -131,47 +131,47 @@ system.mem_ctrls.wrQLenPdf::11 1 # Wh system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::15 1529 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::16 1663 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::17 3055 # What write queue length does an incoming req see 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510 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::41 451 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::42 388 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::43 333 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::44 278 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::45 218 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::46 164 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::47 137 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::48 108 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::49 75 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::50 51 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::51 39 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::52 31 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::53 17 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::54 10 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::55 5 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::15 1641 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::16 1745 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::17 3102 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::18 4476 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::19 5873 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::20 7246 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::21 8278 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::22 9308 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::23 10171 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::24 11061 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::25 12833 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::26 43856 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::27 22169 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::28 13787 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::29 13661 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::30 13451 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::31 13517 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::32 13521 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::33 1702 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::34 974 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::35 819 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::36 750 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::37 676 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::38 605 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::39 553 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::40 493 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::41 434 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::42 386 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::43 321 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::44 269 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::45 227 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::46 188 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::47 157 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::48 119 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::49 90 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::50 69 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::51 50 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::52 29 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::53 18 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::54 12 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::55 6 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see @@ -180,1252 +180,1253 @@ system.mem_ctrls.wrQLenPdf::60 0 # Wh system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrls.bytesPerActivate::samples 217842 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::mean 244.021557 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::gmean 202.580834 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::stdev 149.489115 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::0-127 27613 12.68% 12.68% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::128-255 89630 41.14% 53.82% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::256-383 57317 26.31% 80.13% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::384-511 26502 12.17% 92.30% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::512-639 10866 4.99% 97.29% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::640-767 3972 1.82% 99.11% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::768-895 1352 0.62% 99.73% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::896-1023 417 0.19% 99.92% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::1024-1151 173 0.08% 100.00% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::total 217842 # Bytes accessed per row activation -system.mem_ctrls.rdPerTurnAround::samples 13342 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::mean 45.679808 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::gmean 42.663864 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::stdev 16.154073 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::0-7 18 0.13% 0.13% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::8-15 31 0.23% 0.37% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::16-23 117 0.88% 1.24% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::24-31 4821 36.13% 37.38% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::32-39 1382 10.36% 47.74% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::40-47 232 1.74% 49.48% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::48-55 691 5.18% 54.65% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::56-63 5358 40.16% 94.81% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::64-71 326 2.44% 97.26% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::72-79 80 0.60% 97.86% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::80-87 158 1.18% 99.04% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::88-95 122 0.91% 99.96% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::96-103 3 0.02% 99.98% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::104-111 1 0.01% 99.99% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::120-127 1 0.01% 99.99% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::136-143 1 0.01% 100.00% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::total 13342 # Reads before turning the bus around for writes -system.mem_ctrls.wrPerTurnAround::samples 13342 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::mean 16.573152 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::gmean 16.530670 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::stdev 1.263681 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::16 10409 78.02% 78.02% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::17 467 3.50% 81.52% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::18 1126 8.44% 89.96% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::19 874 6.55% 96.51% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::20 256 1.92% 98.43% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::21 115 0.86% 99.29% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::22 50 0.37% 99.66% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::23 22 0.16% 99.83% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::24 5 0.04% 99.87% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::25 5 0.04% 99.90% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::26 3 0.02% 99.93% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::27 2 0.01% 99.94% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::28 2 0.01% 99.96% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::29 2 0.01% 99.97% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::30 1 0.01% 99.98% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::32 2 0.01% 99.99% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::36 1 0.01% 100.00% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::total 13342 # Writes before turning the bus around for reads -system.mem_ctrls.totQLat 70548774 # Total ticks spent queuing -system.mem_ctrls.totMemAccLat 82129008 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrls.totBusLat 3047430 # Total ticks spent in databus transfers -system.mem_ctrls.avgQLat 115.75 # Average queueing delay per DRAM burst +system.mem_ctrls.bytesPerActivate::samples 216410 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 243.595398 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 202.266425 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 149.425218 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 27460 12.69% 12.69% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 89166 41.20% 53.89% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 57358 26.50% 80.40% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 25806 11.92% 92.32% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 10676 4.93% 97.25% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 3981 1.84% 99.09% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 1348 0.62% 99.72% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 415 0.19% 99.91% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 200 0.09% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 216410 # Bytes accessed per row activation +system.mem_ctrls.rdPerTurnAround::samples 13179 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::mean 45.909705 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::gmean 42.812250 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::stdev 16.207292 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::0-7 27 0.20% 0.20% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::8-15 28 0.21% 0.42% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::16-23 98 0.74% 1.16% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::24-31 4703 35.69% 36.85% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::32-39 1350 10.24% 47.09% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::40-47 197 1.49% 48.58% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::48-55 669 5.08% 53.66% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::56-63 5402 40.99% 94.65% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::64-71 338 2.56% 97.22% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::72-79 90 0.68% 97.90% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::80-87 138 1.05% 98.95% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::88-95 137 1.04% 99.98% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::112-119 1 0.01% 99.99% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::168-175 1 0.01% 100.00% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::total 13179 # Reads before turning the bus around for writes +system.mem_ctrls.wrPerTurnAround::samples 13179 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::mean 16.589650 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::gmean 16.545210 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::stdev 1.294736 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::16 10247 77.75% 77.75% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::17 437 3.32% 81.07% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::18 1119 8.49% 89.56% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::19 908 6.89% 96.45% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::20 245 1.86% 98.31% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::21 119 0.90% 99.21% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::22 43 0.33% 99.54% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::23 23 0.17% 99.71% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::24 15 0.11% 99.83% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::25 8 0.06% 99.89% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::26 5 0.04% 99.92% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::27 4 0.03% 99.95% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::30 3 0.02% 99.98% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::31 1 0.01% 99.98% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::33 1 0.01% 99.99% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::34 1 0.01% 100.00% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::total 13179 # Writes before turning the bus around for reads +system.mem_ctrls.totQLat 69321327 # Total ticks spent queuing +system.mem_ctrls.totMemAccLat 80817752 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.totBusLat 3025375 # Total ticks spent in databus transfers +system.mem_ctrls.avgQLat 114.57 # Average queueing delay per DRAM burst system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst -system.mem_ctrls.avgMemAccLat 134.75 # Average memory access latency per DRAM burst -system.mem_ctrls.avgRdBW 5230.27 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrls.avgWrBW 1897.52 # Average achieved write bandwidth in MiByte/s -system.mem_ctrls.avgRdBWSys 5294.13 # Average system read bandwidth in MiByte/s -system.mem_ctrls.avgWrBWSys 1909.05 # Average system write bandwidth in MiByte/s +system.mem_ctrls.avgMemAccLat 133.57 # Average memory access latency per DRAM burst +system.mem_ctrls.avgRdBW 5232.66 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 1890.75 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 5297.39 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 1901.86 # Average system write bandwidth in MiByte/s system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrls.busUtil 55.69 # Data bus utilization in percentage -system.mem_ctrls.busUtilRead 40.86 # Data bus utilization in percentage for reads -system.mem_ctrls.busUtilWrite 14.82 # Data bus utilization in percentage for writes -system.mem_ctrls.avgRdQLen 20.86 # Average read queue length when enqueuing -system.mem_ctrls.avgWrQLen 27.80 # Average write queue length when enqueuing -system.mem_ctrls.readRowHits 398151 # Number of row buffer hits during reads -system.mem_ctrls.writeRowHits 214607 # Number of row buffer hits during writes -system.mem_ctrls.readRowHitRate 65.33 # Row buffer hit rate for reads -system.mem_ctrls.writeRowHitRate 97.05 # Row buffer hit rate for writes -system.mem_ctrls.avgGap 8.88 # Average gap between requests -system.mem_ctrls.pageHitRate 73.77 # Row buffer hit rate, read and write combined -system.mem_ctrls.memoryStateTime::IDLE 85 # Time in different power states -system.mem_ctrls.memoryStateTime::REF 248820 # Time in different power states -system.mem_ctrls.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls.memoryStateTime::ACT 7202571 # Time in different power states -system.mem_ctrls.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrls.actEnergy::0 1645418880 # Energy for activate commands per rank (pJ) -system.mem_ctrls.actEnergy::1 0 # Energy for activate commands per rank (pJ) -system.mem_ctrls.preEnergy::0 914121600 # Energy for precharge commands per rank (pJ) -system.mem_ctrls.preEnergy::1 0 # Energy for precharge commands per rank (pJ) -system.mem_ctrls.readEnergy::0 7599408960 # Energy for read commands per rank (pJ) -system.mem_ctrls.readEnergy::1 0 # Energy for read commands per rank (pJ) -system.mem_ctrls.writeEnergy::0 2290332672 # Energy for write commands per rank (pJ) -system.mem_ctrls.writeEnergy::1 0 # Energy for write commands per rank (pJ) -system.mem_ctrls.refreshEnergy::0 486691920 # Energy for refresh commands per rank (pJ) -system.mem_ctrls.refreshEnergy::1 486691920 # Energy for refresh commands per rank (pJ) -system.mem_ctrls.actBackEnergy::0 5077598076 # Energy for active background per rank (pJ) -system.mem_ctrls.actBackEnergy::1 161028648 # Energy for active background per rank (pJ) -system.mem_ctrls.preBackEnergy::0 16843800 # Energy for precharge background per rank (pJ) -system.mem_ctrls.preBackEnergy::1 4329624000 # Energy for precharge background per rank (pJ) -system.mem_ctrls.totalEnergy::0 18030415908 # Total energy per rank (pJ) -system.mem_ctrls.totalEnergy::1 4977344568 # Total energy per rank (pJ) -system.mem_ctrls.averagePower::0 2419.715206 # Core power per rank (mW) -system.mem_ctrls.averagePower::1 667.968859 # Core power per rank (mW) +system.mem_ctrls.busUtil 55.65 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 40.88 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 14.77 # Data bus utilization in percentage for writes +system.mem_ctrls.avgRdQLen 20.94 # Average read queue length when enqueuing +system.mem_ctrls.avgWrQLen 27.75 # Average write queue length when enqueuing +system.mem_ctrls.readRowHits 395351 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 211942 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 65.34 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate 96.93 # Row buffer hit rate for writes +system.mem_ctrls.avgGap 8.89 # Average gap between requests +system.mem_ctrls.pageHitRate 73.72 # Row buffer hit rate, read and write combined +system.mem_ctrls_0.actEnergy 1635250680 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 908472600 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 7547392320 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 2265584256 # Energy for write commands per rank (pJ) +system.mem_ctrls_0.refreshEnergy 483132000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_0.actBackEnergy 5041113516 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 16166400 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.totalEnergy 17897111772 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 2419.511790 # Core power per rank (mW) +system.mem_ctrls_0.memoryStateTime::IDLE 159 # Time in different power states +system.mem_ctrls_0.memoryStateTime::REF 247000 # Time in different power states +system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 7149848 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls_1.actEnergy 0 # Energy for activate commands per rank (pJ) +system.mem_ctrls_1.preEnergy 0 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_1.readEnergy 0 # Energy for read commands per rank (pJ) +system.mem_ctrls_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls_1.refreshEnergy 483132000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_1.actBackEnergy 159850800 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 4297947600 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.totalEnergy 4940930400 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 667.968970 # Core power per rank (mW) +system.mem_ctrls_1.memoryStateTime::IDLE 7149960 # Time in different power states +system.mem_ctrls_1.memoryStateTime::REF 247000 # Time in different power states +system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 0 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu_clk_domain.clock 1 # Clock period in ticks +system.cpu0.num_reads 99122 # number of read accesses completed +system.cpu0.num_writes 55082 # number of write accesses completed +system.cpu0.num_copies 0 # number of copy accesses completed +system.cpu1.num_reads 98934 # number of read accesses completed +system.cpu1.num_writes 54848 # number of write accesses completed +system.cpu1.num_copies 0 # number of copy accesses completed +system.cpu2.num_reads 98977 # number of read accesses completed +system.cpu2.num_writes 54560 # number of write accesses completed +system.cpu2.num_copies 0 # number of copy accesses completed +system.cpu3.num_reads 99417 # number of read accesses completed +system.cpu3.num_writes 55431 # number of write accesses completed +system.cpu3.num_copies 0 # number of copy accesses completed +system.cpu4.num_reads 100000 # number of read accesses completed +system.cpu4.num_writes 54903 # number of write accesses completed +system.cpu4.num_copies 0 # number of copy accesses completed +system.cpu5.num_reads 98481 # number of read accesses completed +system.cpu5.num_writes 55109 # number of write accesses completed +system.cpu5.num_copies 0 # number of copy accesses completed +system.cpu6.num_reads 98951 # number of read accesses completed +system.cpu6.num_writes 54779 # number of write accesses completed +system.cpu6.num_copies 0 # number of copy accesses completed +system.cpu7.num_reads 98318 # number of read accesses completed +system.cpu7.num_writes 55002 # number of write accesses completed +system.cpu7.num_copies 0 # number of copy accesses completed system.ruby.clk_domain.clock 1 # Clock period in ticks system.ruby.outstanding_req_hist::bucket_size 2 system.ruby.outstanding_req_hist::max_bucket 19 -system.ruby.outstanding_req_hist::samples 628341 -system.ruby.outstanding_req_hist::mean 15.998455 -system.ruby.outstanding_req_hist::gmean 15.997193 -system.ruby.outstanding_req_hist::stdev 0.125709 -system.ruby.outstanding_req_hist | 8 0.00% 0.00% | 16 0.00% 0.00% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.02% | 27 0.00% 0.02% | 628210 99.98% 100.00% | 0 0.00% 100.00% -system.ruby.outstanding_req_hist::total 628341 +system.ruby.outstanding_req_hist::samples 623953 +system.ruby.outstanding_req_hist::mean 15.998445 +system.ruby.outstanding_req_hist::gmean 15.997175 +system.ruby.outstanding_req_hist::stdev 0.126144 +system.ruby.outstanding_req_hist | 8 0.00% 0.00% | 16 0.00% 0.00% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.02% | 26 0.00% 0.02% | 623823 99.98% 100.00% | 0 0.00% 100.00% +system.ruby.outstanding_req_hist::total 623953 system.ruby.latency_hist::bucket_size 2048 system.ruby.latency_hist::max_bucket 20479 -system.ruby.latency_hist::samples 628213 -system.ruby.latency_hist::mean 1519.280787 -system.ruby.latency_hist::gmean 1022.681311 -system.ruby.latency_hist::stdev 1497.288069 -system.ruby.latency_hist | 474914 75.60% 75.60% | 109593 17.45% 93.04% | 31707 5.05% 98.09% | 9100 1.45% 99.54% | 2263 0.36% 99.90% | 512 0.08% 99.98% | 107 0.02% 100.00% | 17 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.latency_hist::total 628213 +system.ruby.latency_hist::samples 623825 +system.ruby.latency_hist::mean 1518.158580 +system.ruby.latency_hist::gmean 1023.158557 +system.ruby.latency_hist::stdev 1495.268071 +system.ruby.latency_hist | 471692 75.61% 75.61% | 109137 17.49% 93.11% | 31197 5.00% 98.11% | 8878 1.42% 99.53% | 2243 0.36% 99.89% | 516 0.08% 99.97% | 127 0.02% 99.99% | 29 0.00% 100.00% | 5 0.00% 100.00% | 1 0.00% 100.00% +system.ruby.latency_hist::total 623825 system.ruby.hit_latency_hist::bucket_size 1 system.ruby.hit_latency_hist::max_bucket 9 -system.ruby.hit_latency_hist::samples 119 +system.ruby.hit_latency_hist::samples 108 system.ruby.hit_latency_hist::mean 3 system.ruby.hit_latency_hist::gmean 3.000000 -system.ruby.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 119 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.hit_latency_hist::total 119 +system.ruby.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 108 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.hit_latency_hist::total 108 system.ruby.miss_latency_hist::bucket_size 2048 system.ruby.miss_latency_hist::max_bucket 20479 -system.ruby.miss_latency_hist::samples 628094 -system.ruby.miss_latency_hist::mean 1519.568065 -system.ruby.miss_latency_hist::gmean 1023.811857 -system.ruby.miss_latency_hist::stdev 1497.284420 -system.ruby.miss_latency_hist | 474795 75.59% 75.59% | 109593 17.45% 93.04% | 31707 5.05% 98.09% | 9100 1.45% 99.54% | 2263 0.36% 99.90% | 512 0.08% 99.98% | 107 0.02% 100.00% | 17 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.miss_latency_hist::total 628094 -system.ruby.l1_cntrl4.L1Dcache.demand_hits 14 # Number of cache demand hits -system.ruby.l1_cntrl4.L1Dcache.demand_misses 78541 # Number of cache demand misses -system.ruby.l1_cntrl4.L1Dcache.demand_accesses 78555 # Number of cache demand accesses -system.ruby.l1_cntrl4.L1Icache.demand_hits 0 # Number of cache demand hits -system.ruby.l1_cntrl4.L1Icache.demand_misses 0 # Number of cache demand misses -system.ruby.l1_cntrl4.L1Icache.demand_accesses 0 # Number of cache demand accesses -system.cpu_clk_domain.clock 1 # Clock period in ticks -system.ruby.l1_cntrl5.L1Dcache.demand_hits 10 # Number of cache demand hits -system.ruby.l1_cntrl5.L1Dcache.demand_misses 78462 # Number of cache demand misses -system.ruby.l1_cntrl5.L1Dcache.demand_accesses 78472 # Number of cache demand accesses -system.ruby.l1_cntrl5.L1Icache.demand_hits 0 # Number of cache demand hits -system.ruby.l1_cntrl5.L1Icache.demand_misses 0 # Number of cache demand misses -system.ruby.l1_cntrl5.L1Icache.demand_accesses 0 # Number of cache demand accesses -system.ruby.l1_cntrl6.L1Dcache.demand_hits 14 # Number of cache demand hits -system.ruby.l1_cntrl6.L1Dcache.demand_misses 78462 # Number of cache demand misses -system.ruby.l1_cntrl6.L1Dcache.demand_accesses 78476 # Number of cache demand accesses -system.ruby.l1_cntrl6.L1Icache.demand_hits 0 # Number of cache demand hits -system.ruby.l1_cntrl6.L1Icache.demand_misses 0 # Number of cache demand misses -system.ruby.l1_cntrl6.L1Icache.demand_accesses 0 # Number of cache demand accesses -system.ruby.l1_cntrl7.L1Dcache.demand_hits 13 # Number of cache demand hits -system.ruby.l1_cntrl7.L1Dcache.demand_misses 78239 # Number of cache demand misses -system.ruby.l1_cntrl7.L1Dcache.demand_accesses 78252 # Number of cache demand accesses -system.ruby.l1_cntrl7.L1Icache.demand_hits 0 # Number of cache demand hits -system.ruby.l1_cntrl7.L1Icache.demand_misses 0 # Number of cache demand misses -system.ruby.l1_cntrl7.L1Icache.demand_accesses 0 # Number of cache demand accesses -system.ruby.l1_cntrl0.L1Dcache.demand_hits 18 # Number of cache demand hits -system.ruby.l1_cntrl0.L1Dcache.demand_misses 78680 # Number of cache demand misses -system.ruby.l1_cntrl0.L1Dcache.demand_accesses 78698 # Number of cache demand accesses +system.ruby.miss_latency_hist::samples 623717 +system.ruby.miss_latency_hist::mean 1518.420938 +system.ruby.miss_latency_hist::gmean 1024.192315 +system.ruby.miss_latency_hist::stdev 1495.264581 +system.ruby.miss_latency_hist | 471584 75.61% 75.61% | 109137 17.50% 93.11% | 31197 5.00% 98.11% | 8878 1.42% 99.53% | 2243 0.36% 99.89% | 516 0.08% 99.97% | 127 0.02% 99.99% | 29 0.00% 100.00% | 5 0.00% 100.00% | 1 0.00% 100.00% +system.ruby.miss_latency_hist::total 623717 +system.ruby.l1_cntrl0.L1Dcache.demand_hits 12 # Number of cache demand hits +system.ruby.l1_cntrl0.L1Dcache.demand_misses 78021 # Number of cache demand misses +system.ruby.l1_cntrl0.L1Dcache.demand_accesses 78033 # Number of cache demand accesses system.ruby.l1_cntrl0.L1Icache.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl0.L1Icache.demand_misses 0 # Number of cache demand misses system.ruby.l1_cntrl0.L1Icache.demand_accesses 0 # Number of cache demand accesses -system.ruby.network.routers00.percent_links_utilized 5.803900 -system.ruby.network.routers00.msg_count.Request_Control::0 78680 -system.ruby.network.routers00.msg_count.Response_Data::2 77269 -system.ruby.network.routers00.msg_count.ResponseL2hit_Data::2 563 -system.ruby.network.routers00.msg_count.ResponseLocal_Data::2 1686 -system.ruby.network.routers00.msg_count.Response_Control::2 613 -system.ruby.network.routers00.msg_count.Writeback_Data::2 77627 -system.ruby.network.routers00.msg_count.Writeback_Control::0 157289 -system.ruby.network.routers00.msg_count.Forwarded_Control::0 842 -system.ruby.network.routers00.msg_count.Invalidate_Control::0 233 -system.ruby.network.routers00.msg_count.Unblock_Control::2 79445 -system.ruby.network.routers00.msg_bytes.Request_Control::0 629440 -system.ruby.network.routers00.msg_bytes.Response_Data::2 5563368 -system.ruby.network.routers00.msg_bytes.ResponseL2hit_Data::2 40536 -system.ruby.network.routers00.msg_bytes.ResponseLocal_Data::2 121392 -system.ruby.network.routers00.msg_bytes.Response_Control::2 4904 -system.ruby.network.routers00.msg_bytes.Writeback_Data::2 5589144 -system.ruby.network.routers00.msg_bytes.Writeback_Control::0 1258312 -system.ruby.network.routers00.msg_bytes.Forwarded_Control::0 6736 -system.ruby.network.routers00.msg_bytes.Invalidate_Control::0 1864 -system.ruby.network.routers00.msg_bytes.Unblock_Control::2 635560 -system.ruby.l1_cntrl1.L1Dcache.demand_hits 17 # Number of cache demand hits -system.ruby.l1_cntrl1.L1Dcache.demand_misses 78726 # Number of cache demand misses -system.ruby.l1_cntrl1.L1Dcache.demand_accesses 78743 # Number of cache demand accesses +system.ruby.l1_cntrl1.L1Dcache.demand_hits 11 # Number of cache demand hits +system.ruby.l1_cntrl1.L1Dcache.demand_misses 77929 # Number of cache demand misses +system.ruby.l1_cntrl1.L1Dcache.demand_accesses 77940 # Number of cache demand accesses system.ruby.l1_cntrl1.L1Icache.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl1.L1Icache.demand_misses 0 # Number of cache demand misses system.ruby.l1_cntrl1.L1Icache.demand_accesses 0 # Number of cache demand accesses -system.ruby.network.routers01.percent_links_utilized 5.806223 -system.ruby.network.routers01.msg_count.Request_Control::0 78726 -system.ruby.network.routers01.msg_count.Response_Data::2 77263 -system.ruby.network.routers01.msg_count.ResponseL2hit_Data::2 617 -system.ruby.network.routers01.msg_count.ResponseLocal_Data::2 1711 -system.ruby.network.routers01.msg_count.Response_Control::2 606 -system.ruby.network.routers01.msg_count.Writeback_Data::2 77607 -system.ruby.network.routers01.msg_count.Writeback_Control::0 157340 -system.ruby.network.routers01.msg_count.Forwarded_Control::0 868 -system.ruby.network.routers01.msg_count.Invalidate_Control::0 238 -system.ruby.network.routers01.msg_count.Unblock_Control::2 79540 -system.ruby.network.routers01.msg_bytes.Request_Control::0 629808 -system.ruby.network.routers01.msg_bytes.Response_Data::2 5562936 -system.ruby.network.routers01.msg_bytes.ResponseL2hit_Data::2 44424 -system.ruby.network.routers01.msg_bytes.ResponseLocal_Data::2 123192 -system.ruby.network.routers01.msg_bytes.Response_Control::2 4848 -system.ruby.network.routers01.msg_bytes.Writeback_Data::2 5587704 -system.ruby.network.routers01.msg_bytes.Writeback_Control::0 1258720 -system.ruby.network.routers01.msg_bytes.Forwarded_Control::0 6944 -system.ruby.network.routers01.msg_bytes.Invalidate_Control::0 1904 -system.ruby.network.routers01.msg_bytes.Unblock_Control::2 636320 -system.ruby.l1_cntrl2.L1Dcache.demand_hits 13 # Number of cache demand hits -system.ruby.l1_cntrl2.L1Dcache.demand_misses 78492 # Number of cache demand misses -system.ruby.l1_cntrl2.L1Dcache.demand_accesses 78505 # Number of cache demand accesses +system.ruby.l1_cntrl2.L1Dcache.demand_hits 11 # Number of cache demand hits +system.ruby.l1_cntrl2.L1Dcache.demand_misses 77932 # Number of cache demand misses +system.ruby.l1_cntrl2.L1Dcache.demand_accesses 77943 # Number of cache demand accesses system.ruby.l1_cntrl2.L1Icache.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl2.L1Icache.demand_misses 0 # Number of cache demand misses system.ruby.l1_cntrl2.L1Icache.demand_accesses 0 # Number of cache demand accesses -system.ruby.network.routers02.percent_links_utilized 5.789942 -system.ruby.network.routers02.msg_count.Request_Control::0 78492 -system.ruby.network.routers02.msg_count.Response_Data::2 77126 -system.ruby.network.routers02.msg_count.ResponseL2hit_Data::2 556 -system.ruby.network.routers02.msg_count.ResponseLocal_Data::2 1605 -system.ruby.network.routers02.msg_count.Response_Control::2 583 -system.ruby.network.routers02.msg_count.Writeback_Data::2 77494 -system.ruby.network.routers02.msg_count.Writeback_Control::0 156900 -system.ruby.network.routers02.msg_count.Forwarded_Control::0 799 -system.ruby.network.routers02.msg_count.Invalidate_Control::0 212 -system.ruby.network.routers02.msg_count.Unblock_Control::2 79228 -system.ruby.network.routers02.msg_bytes.Request_Control::0 627936 -system.ruby.network.routers02.msg_bytes.Response_Data::2 5553072 -system.ruby.network.routers02.msg_bytes.ResponseL2hit_Data::2 40032 -system.ruby.network.routers02.msg_bytes.ResponseLocal_Data::2 115560 -system.ruby.network.routers02.msg_bytes.Response_Control::2 4664 -system.ruby.network.routers02.msg_bytes.Writeback_Data::2 5579568 -system.ruby.network.routers02.msg_bytes.Writeback_Control::0 1255200 -system.ruby.network.routers02.msg_bytes.Forwarded_Control::0 6392 -system.ruby.network.routers02.msg_bytes.Invalidate_Control::0 1696 -system.ruby.network.routers02.msg_bytes.Unblock_Control::2 633824 -system.ruby.l1_cntrl3.L1Dcache.demand_hits 20 # Number of cache demand hits -system.ruby.l1_cntrl3.L1Dcache.demand_misses 78519 # Number of cache demand misses -system.ruby.l1_cntrl3.L1Dcache.demand_accesses 78539 # Number of cache demand accesses +system.ruby.l1_cntrl3.L1Dcache.demand_hits 14 # Number of cache demand hits +system.ruby.l1_cntrl3.L1Dcache.demand_misses 78185 # Number of cache demand misses +system.ruby.l1_cntrl3.L1Dcache.demand_accesses 78199 # Number of cache demand accesses system.ruby.l1_cntrl3.L1Icache.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl3.L1Icache.demand_misses 0 # Number of cache demand misses system.ruby.l1_cntrl3.L1Icache.demand_accesses 0 # Number of cache demand accesses -system.ruby.network.routers03.percent_links_utilized 5.790190 -system.ruby.network.routers03.msg_count.Request_Control::0 78519 -system.ruby.network.routers03.msg_count.Response_Data::2 77107 -system.ruby.network.routers03.msg_count.ResponseL2hit_Data::2 585 -system.ruby.network.routers03.msg_count.ResponseLocal_Data::2 1603 -system.ruby.network.routers03.msg_count.Response_Control::2 633 -system.ruby.network.routers03.msg_count.Writeback_Data::2 77472 -system.ruby.network.routers03.msg_count.Writeback_Control::0 156964 -system.ruby.network.routers03.msg_count.Forwarded_Control::0 780 -system.ruby.network.routers03.msg_count.Invalidate_Control::0 230 -system.ruby.network.routers03.msg_count.Unblock_Control::2 79288 -system.ruby.network.routers03.msg_bytes.Request_Control::0 628152 -system.ruby.network.routers03.msg_bytes.Response_Data::2 5551704 -system.ruby.network.routers03.msg_bytes.ResponseL2hit_Data::2 42120 -system.ruby.network.routers03.msg_bytes.ResponseLocal_Data::2 115416 -system.ruby.network.routers03.msg_bytes.Response_Control::2 5064 -system.ruby.network.routers03.msg_bytes.Writeback_Data::2 5577984 -system.ruby.network.routers03.msg_bytes.Writeback_Control::0 1255712 -system.ruby.network.routers03.msg_bytes.Forwarded_Control::0 6240 -system.ruby.network.routers03.msg_bytes.Invalidate_Control::0 1840 -system.ruby.network.routers03.msg_bytes.Unblock_Control::2 634304 -system.ruby.network.routers04.percent_links_utilized 5.794310 -system.ruby.network.routers04.msg_count.Request_Control::0 78541 -system.ruby.network.routers04.msg_count.Response_Data::2 77149 -system.ruby.network.routers04.msg_count.ResponseL2hit_Data::2 567 -system.ruby.network.routers04.msg_count.ResponseLocal_Data::2 1664 -system.ruby.network.routers04.msg_count.Response_Control::2 595 -system.ruby.network.routers04.msg_count.Writeback_Data::2 77514 -system.ruby.network.routers04.msg_count.Writeback_Control::0 157002 -system.ruby.network.routers04.msg_count.Forwarded_Control::0 842 -system.ruby.network.routers04.msg_count.Invalidate_Control::0 213 -system.ruby.network.routers04.msg_count.Unblock_Control::2 79307 -system.ruby.network.routers04.msg_bytes.Request_Control::0 628328 -system.ruby.network.routers04.msg_bytes.Response_Data::2 5554728 -system.ruby.network.routers04.msg_bytes.ResponseL2hit_Data::2 40824 -system.ruby.network.routers04.msg_bytes.ResponseLocal_Data::2 119808 -system.ruby.network.routers04.msg_bytes.Response_Control::2 4760 -system.ruby.network.routers04.msg_bytes.Writeback_Data::2 5581008 -system.ruby.network.routers04.msg_bytes.Writeback_Control::0 1256016 -system.ruby.network.routers04.msg_bytes.Forwarded_Control::0 6736 -system.ruby.network.routers04.msg_bytes.Invalidate_Control::0 1704 -system.ruby.network.routers04.msg_bytes.Unblock_Control::2 634456 -system.ruby.network.routers05.percent_links_utilized 5.786489 -system.ruby.network.routers05.msg_count.Request_Control::0 78462 -system.ruby.network.routers05.msg_count.Response_Data::2 77063 -system.ruby.network.routers05.msg_count.ResponseL2hit_Data::2 543 -system.ruby.network.routers05.msg_count.ResponseLocal_Data::2 1668 -system.ruby.network.routers05.msg_count.Response_Control::2 630 -system.ruby.network.routers05.msg_count.Writeback_Data::2 77392 -system.ruby.network.routers05.msg_count.Writeback_Control::0 156838 -system.ruby.network.routers05.msg_count.Forwarded_Control::0 816 -system.ruby.network.routers05.msg_count.Invalidate_Control::0 227 -system.ruby.network.routers05.msg_count.Unblock_Control::2 79246 -system.ruby.network.routers05.msg_bytes.Request_Control::0 627696 -system.ruby.network.routers05.msg_bytes.Response_Data::2 5548536 -system.ruby.network.routers05.msg_bytes.ResponseL2hit_Data::2 39096 -system.ruby.network.routers05.msg_bytes.ResponseLocal_Data::2 120096 -system.ruby.network.routers05.msg_bytes.Response_Control::2 5040 -system.ruby.network.routers05.msg_bytes.Writeback_Data::2 5572224 -system.ruby.network.routers05.msg_bytes.Writeback_Control::0 1254704 -system.ruby.network.routers05.msg_bytes.Forwarded_Control::0 6528 -system.ruby.network.routers05.msg_bytes.Invalidate_Control::0 1816 -system.ruby.network.routers05.msg_bytes.Unblock_Control::2 633968 -system.ruby.network.routers06.percent_links_utilized 5.788672 -system.ruby.network.routers06.msg_count.Request_Control::0 78462 -system.ruby.network.routers06.msg_count.Response_Data::2 77081 -system.ruby.network.routers06.msg_count.ResponseL2hit_Data::2 586 -system.ruby.network.routers06.msg_count.ResponseLocal_Data::2 1642 -system.ruby.network.routers06.msg_count.Response_Control::2 600 -system.ruby.network.routers06.msg_count.Writeback_Data::2 77437 -system.ruby.network.routers06.msg_count.Writeback_Control::0 156820 -system.ruby.network.routers06.msg_count.Forwarded_Control::0 849 -system.ruby.network.routers06.msg_count.Invalidate_Control::0 221 -system.ruby.network.routers06.msg_count.Unblock_Control::2 79201 -system.ruby.network.routers06.msg_bytes.Request_Control::0 627696 -system.ruby.network.routers06.msg_bytes.Response_Data::2 5549832 -system.ruby.network.routers06.msg_bytes.ResponseL2hit_Data::2 42192 -system.ruby.network.routers06.msg_bytes.ResponseLocal_Data::2 118224 -system.ruby.network.routers06.msg_bytes.Response_Control::2 4800 -system.ruby.network.routers06.msg_bytes.Writeback_Data::2 5575464 -system.ruby.network.routers06.msg_bytes.Writeback_Control::0 1254560 -system.ruby.network.routers06.msg_bytes.Forwarded_Control::0 6792 -system.ruby.network.routers06.msg_bytes.Invalidate_Control::0 1768 -system.ruby.network.routers06.msg_bytes.Unblock_Control::2 633608 -system.ruby.network.routers07.percent_links_utilized 5.769735 -system.ruby.network.routers07.msg_count.Request_Control::0 78239 -system.ruby.network.routers07.msg_count.Response_Data::2 76843 -system.ruby.network.routers07.msg_count.ResponseL2hit_Data::2 556 -system.ruby.network.routers07.msg_count.ResponseLocal_Data::2 1661 -system.ruby.network.routers07.msg_count.Response_Control::2 611 -system.ruby.network.routers07.msg_count.Writeback_Data::2 77149 -system.ruby.network.routers07.msg_count.Writeback_Control::0 156380 -system.ruby.network.routers07.msg_count.Forwarded_Control::0 824 -system.ruby.network.routers07.msg_count.Invalidate_Control::0 247 -system.ruby.network.routers07.msg_count.Unblock_Control::2 79033 -system.ruby.network.routers07.msg_bytes.Request_Control::0 625912 -system.ruby.network.routers07.msg_bytes.Response_Data::2 5532696 -system.ruby.network.routers07.msg_bytes.ResponseL2hit_Data::2 40032 -system.ruby.network.routers07.msg_bytes.ResponseLocal_Data::2 119592 -system.ruby.network.routers07.msg_bytes.Response_Control::2 4888 -system.ruby.network.routers07.msg_bytes.Writeback_Data::2 5554728 -system.ruby.network.routers07.msg_bytes.Writeback_Control::0 1251040 -system.ruby.network.routers07.msg_bytes.Forwarded_Control::0 6592 -system.ruby.network.routers07.msg_bytes.Invalidate_Control::0 1976 -system.ruby.network.routers07.msg_bytes.Unblock_Control::2 632264 -system.ruby.l2_cntrl0.L2cache.demand_hits 4573 # Number of cache demand hits -system.ruby.l2_cntrl0.L2cache.demand_misses 623547 # Number of cache demand misses -system.ruby.l2_cntrl0.L2cache.demand_accesses 628120 # Number of cache demand accesses -system.ruby.network.routers08.percent_links_utilized 76.868118 -system.ruby.network.routers08.msg_count.Request_Control::0 628120 -system.ruby.network.routers08.msg_count.Request_Control::1 616927 -system.ruby.network.routers08.msg_count.Response_Data::2 1233805 -system.ruby.network.routers08.msg_count.ResponseL2hit_Data::2 4573 -system.ruby.network.routers08.msg_count.Response_Control::2 1229 -system.ruby.network.routers08.msg_count.Writeback_Data::2 842154 -system.ruby.network.routers08.msg_count.Writeback_Control::0 1255532 -system.ruby.network.routers08.msg_count.Writeback_Control::1 444935 -system.ruby.network.routers08.msg_count.Forwarded_Control::0 6620 -system.ruby.network.routers08.msg_count.Invalidate_Control::0 1813 -system.ruby.network.routers08.msg_count.Unblock_Control::2 1251180 -system.ruby.network.routers08.msg_bytes.Request_Control::0 5024960 -system.ruby.network.routers08.msg_bytes.Request_Control::1 4935416 -system.ruby.network.routers08.msg_bytes.Response_Data::2 88833960 -system.ruby.network.routers08.msg_bytes.ResponseL2hit_Data::2 329256 -system.ruby.network.routers08.msg_bytes.Response_Control::2 9832 -system.ruby.network.routers08.msg_bytes.Writeback_Data::2 60635088 -system.ruby.network.routers08.msg_bytes.Writeback_Control::0 10044256 -system.ruby.network.routers08.msg_bytes.Writeback_Control::1 3559480 -system.ruby.network.routers08.msg_bytes.Forwarded_Control::0 52960 -system.ruby.network.routers08.msg_bytes.Invalidate_Control::0 14504 -system.ruby.network.routers08.msg_bytes.Unblock_Control::2 10009440 -system.ruby.network.routers09.percent_links_utilized 30.950516 -system.ruby.network.routers09.msg_count.Request_Control::1 616927 -system.ruby.network.routers09.msg_count.Response_Data::2 616908 -system.ruby.network.routers09.msg_count.Writeback_Data::2 222462 -system.ruby.network.routers09.msg_count.Writeback_Control::1 444945 -system.ruby.network.routers09.msg_count.Unblock_Control::2 616896 -system.ruby.network.routers09.msg_bytes.Request_Control::1 4935416 -system.ruby.network.routers09.msg_bytes.Response_Data::2 44417376 -system.ruby.network.routers09.msg_bytes.Writeback_Data::2 16017264 -system.ruby.network.routers09.msg_bytes.Writeback_Control::1 3559560 -system.ruby.network.routers09.msg_bytes.Unblock_Control::2 4935168 -system.ruby.network.routers10.percent_links_utilized 15.414795 -system.ruby.network.routers10.msg_count.Request_Control::0 628120 -system.ruby.network.routers10.msg_count.Request_Control::1 616927 -system.ruby.network.routers10.msg_count.Response_Data::2 1233804 -system.ruby.network.routers10.msg_count.ResponseL2hit_Data::2 4573 -system.ruby.network.routers10.msg_count.ResponseLocal_Data::2 6620 -system.ruby.network.routers10.msg_count.Response_Control::2 3050 -system.ruby.network.routers10.msg_count.Writeback_Data::2 842154 -system.ruby.network.routers10.msg_count.Writeback_Control::0 1255532 -system.ruby.network.routers10.msg_count.Writeback_Control::1 444935 -system.ruby.network.routers10.msg_count.Forwarded_Control::0 6620 -system.ruby.network.routers10.msg_count.Invalidate_Control::0 1821 -system.ruby.network.routers10.msg_count.Unblock_Control::2 1251180 -system.ruby.network.routers10.msg_bytes.Request_Control::0 5024960 -system.ruby.network.routers10.msg_bytes.Request_Control::1 4935416 -system.ruby.network.routers10.msg_bytes.Response_Data::2 88833888 -system.ruby.network.routers10.msg_bytes.ResponseL2hit_Data::2 329256 -system.ruby.network.routers10.msg_bytes.ResponseLocal_Data::2 476640 -system.ruby.network.routers10.msg_bytes.Response_Control::2 24400 -system.ruby.network.routers10.msg_bytes.Writeback_Data::2 60635088 -system.ruby.network.routers10.msg_bytes.Writeback_Control::0 10044256 -system.ruby.network.routers10.msg_bytes.Writeback_Control::1 3559480 -system.ruby.network.routers10.msg_bytes.Forwarded_Control::0 52960 -system.ruby.network.routers10.msg_bytes.Invalidate_Control::0 14568 -system.ruby.network.routers10.msg_bytes.Unblock_Control::2 10009440 -system.ruby.network.msg_count.Request_Control 3735142 -system.ruby.network.msg_count.Response_Data 3701418 -system.ruby.network.msg_count.ResponseL2hit_Data 13719 -system.ruby.network.msg_count.ResponseLocal_Data 19860 -system.ruby.network.msg_count.Response_Control 9150 -system.ruby.network.msg_count.Writeback_Data 2526462 -system.ruby.network.msg_count.Writeback_Control 5101412 -system.ruby.network.msg_count.Forwarded_Control 19860 -system.ruby.network.msg_count.Invalidate_Control 5455 -system.ruby.network.msg_count.Unblock_Control 3753544 -system.ruby.network.msg_byte.Request_Control 29881136 -system.ruby.network.msg_byte.Response_Data 266502096 -system.ruby.network.msg_byte.ResponseL2hit_Data 987768 -system.ruby.network.msg_byte.ResponseLocal_Data 1429920 -system.ruby.network.msg_byte.Response_Control 73200 -system.ruby.network.msg_byte.Writeback_Data 181905264 -system.ruby.network.msg_byte.Writeback_Control 40811296 -system.ruby.network.msg_byte.Forwarded_Control 158880 -system.ruby.network.msg_byte.Invalidate_Control 43640 -system.ruby.network.msg_byte.Unblock_Control 30028352 +system.ruby.l1_cntrl4.L1Dcache.demand_hits 10 # Number of cache demand hits +system.ruby.l1_cntrl4.L1Dcache.demand_misses 78368 # Number of cache demand misses +system.ruby.l1_cntrl4.L1Dcache.demand_accesses 78378 # Number of cache demand accesses +system.ruby.l1_cntrl4.L1Icache.demand_hits 0 # Number of cache demand hits +system.ruby.l1_cntrl4.L1Icache.demand_misses 0 # Number of cache demand misses +system.ruby.l1_cntrl4.L1Icache.demand_accesses 0 # Number of cache demand accesses +system.ruby.l1_cntrl5.L1Dcache.demand_hits 17 # Number of cache demand hits +system.ruby.l1_cntrl5.L1Dcache.demand_misses 77782 # Number of cache demand misses +system.ruby.l1_cntrl5.L1Dcache.demand_accesses 77799 # Number of cache demand accesses +system.ruby.l1_cntrl5.L1Icache.demand_hits 0 # Number of cache demand hits +system.ruby.l1_cntrl5.L1Icache.demand_misses 0 # Number of cache demand misses +system.ruby.l1_cntrl5.L1Icache.demand_accesses 0 # Number of cache demand accesses +system.ruby.l1_cntrl6.L1Dcache.demand_hits 10 # Number of cache demand hits +system.ruby.l1_cntrl6.L1Dcache.demand_misses 77715 # Number of cache demand misses +system.ruby.l1_cntrl6.L1Dcache.demand_accesses 77725 # Number of cache demand accesses +system.ruby.l1_cntrl6.L1Icache.demand_hits 0 # Number of cache demand hits +system.ruby.l1_cntrl6.L1Icache.demand_misses 0 # Number of cache demand misses +system.ruby.l1_cntrl6.L1Icache.demand_accesses 0 # Number of cache demand accesses +system.ruby.l1_cntrl7.L1Dcache.demand_hits 23 # Number of cache demand hits +system.ruby.l1_cntrl7.L1Dcache.demand_misses 77805 # Number of cache demand misses +system.ruby.l1_cntrl7.L1Dcache.demand_accesses 77828 # Number of cache demand accesses +system.ruby.l1_cntrl7.L1Icache.demand_hits 0 # Number of cache demand hits +system.ruby.l1_cntrl7.L1Icache.demand_misses 0 # Number of cache demand misses +system.ruby.l1_cntrl7.L1Icache.demand_accesses 0 # Number of cache demand accesses +system.ruby.l2_cntrl0.L2cache.demand_hits 4560 # Number of cache demand hits +system.ruby.l2_cntrl0.L2cache.demand_misses 619174 # Number of cache demand misses +system.ruby.l2_cntrl0.L2cache.demand_accesses 623734 # Number of cache demand accesses system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.cpu0.num_reads 99943 # number of read accesses completed -system.cpu0.num_writes 55703 # number of write accesses completed -system.cpu0.num_copies 0 # number of copy accesses completed -system.cpu1.num_reads 99615 # number of read accesses completed -system.cpu1.num_writes 55561 # number of write accesses completed -system.cpu1.num_copies 0 # number of copy accesses completed -system.cpu2.num_reads 98958 # number of read accesses completed -system.cpu2.num_writes 55524 # number of write accesses completed -system.cpu2.num_copies 0 # number of copy accesses completed -system.cpu3.num_reads 99879 # number of read accesses completed -system.cpu3.num_writes 55313 # number of write accesses completed -system.cpu3.num_copies 0 # number of copy accesses completed -system.cpu4.num_reads 99950 # number of read accesses completed -system.cpu4.num_writes 55567 # number of write accesses completed -system.cpu4.num_copies 0 # number of copy accesses completed -system.cpu5.num_reads 99292 # number of read accesses completed -system.cpu5.num_writes 55606 # number of write accesses completed -system.cpu5.num_copies 0 # number of copy accesses completed -system.cpu6.num_reads 100000 # number of read accesses completed -system.cpu6.num_writes 55665 # number of write accesses completed -system.cpu6.num_copies 0 # number of copy accesses completed -system.cpu7.num_reads 99277 # number of read accesses completed -system.cpu7.num_writes 55190 # number of write accesses completed -system.cpu7.num_copies 0 # number of copy accesses completed -system.ruby.network.routers00.throttle0.link_utilization 5.284183 -system.ruby.network.routers00.throttle0.msg_count.Response_Data::2 77269 -system.ruby.network.routers00.throttle0.msg_count.ResponseL2hit_Data::2 563 -system.ruby.network.routers00.throttle0.msg_count.ResponseLocal_Data::2 844 -system.ruby.network.routers00.throttle0.msg_count.Response_Control::2 380 -system.ruby.network.routers00.throttle0.msg_count.Writeback_Control::0 78644 -system.ruby.network.routers00.throttle0.msg_count.Forwarded_Control::0 842 -system.ruby.network.routers00.throttle0.msg_count.Invalidate_Control::0 233 -system.ruby.network.routers00.throttle0.msg_bytes.Response_Data::2 5563368 -system.ruby.network.routers00.throttle0.msg_bytes.ResponseL2hit_Data::2 40536 -system.ruby.network.routers00.throttle0.msg_bytes.ResponseLocal_Data::2 60768 -system.ruby.network.routers00.throttle0.msg_bytes.Response_Control::2 3040 -system.ruby.network.routers00.throttle0.msg_bytes.Writeback_Control::0 629152 -system.ruby.network.routers00.throttle0.msg_bytes.Forwarded_Control::0 6736 -system.ruby.network.routers00.throttle0.msg_bytes.Invalidate_Control::0 1864 -system.ruby.network.routers00.throttle1.link_utilization 6.323618 -system.ruby.network.routers00.throttle1.msg_count.Request_Control::0 78680 -system.ruby.network.routers00.throttle1.msg_count.ResponseLocal_Data::2 842 -system.ruby.network.routers00.throttle1.msg_count.Response_Control::2 233 -system.ruby.network.routers00.throttle1.msg_count.Writeback_Data::2 77627 -system.ruby.network.routers00.throttle1.msg_count.Writeback_Control::0 78645 -system.ruby.network.routers00.throttle1.msg_count.Unblock_Control::2 79445 -system.ruby.network.routers00.throttle1.msg_bytes.Request_Control::0 629440 -system.ruby.network.routers00.throttle1.msg_bytes.ResponseLocal_Data::2 60624 -system.ruby.network.routers00.throttle1.msg_bytes.Response_Control::2 1864 -system.ruby.network.routers00.throttle1.msg_bytes.Writeback_Data::2 5589144 -system.ruby.network.routers00.throttle1.msg_bytes.Writeback_Control::0 629160 -system.ruby.network.routers00.throttle1.msg_bytes.Unblock_Control::2 635560 -system.ruby.network.routers01.throttle0.link_utilization 5.287320 -system.ruby.network.routers01.throttle0.msg_count.Response_Data::2 77263 -system.ruby.network.routers01.throttle0.msg_count.ResponseL2hit_Data::2 617 -system.ruby.network.routers01.throttle0.msg_count.ResponseLocal_Data::2 843 -system.ruby.network.routers01.throttle0.msg_count.Response_Control::2 368 -system.ruby.network.routers01.throttle0.msg_count.Writeback_Control::0 78670 -system.ruby.network.routers01.throttle0.msg_count.Forwarded_Control::0 868 -system.ruby.network.routers01.throttle0.msg_count.Invalidate_Control::0 238 -system.ruby.network.routers01.throttle0.msg_bytes.Response_Data::2 5562936 -system.ruby.network.routers01.throttle0.msg_bytes.ResponseL2hit_Data::2 44424 -system.ruby.network.routers01.throttle0.msg_bytes.ResponseLocal_Data::2 60696 -system.ruby.network.routers01.throttle0.msg_bytes.Response_Control::2 2944 -system.ruby.network.routers01.throttle0.msg_bytes.Writeback_Control::0 629360 -system.ruby.network.routers01.throttle0.msg_bytes.Forwarded_Control::0 6944 -system.ruby.network.routers01.throttle0.msg_bytes.Invalidate_Control::0 1904 -system.ruby.network.routers01.throttle1.link_utilization 6.325126 -system.ruby.network.routers01.throttle1.msg_count.Request_Control::0 78726 -system.ruby.network.routers01.throttle1.msg_count.ResponseLocal_Data::2 868 -system.ruby.network.routers01.throttle1.msg_count.Response_Control::2 238 -system.ruby.network.routers01.throttle1.msg_count.Writeback_Data::2 77607 -system.ruby.network.routers01.throttle1.msg_count.Writeback_Control::0 78670 -system.ruby.network.routers01.throttle1.msg_count.Unblock_Control::2 79540 -system.ruby.network.routers01.throttle1.msg_bytes.Request_Control::0 629808 -system.ruby.network.routers01.throttle1.msg_bytes.ResponseLocal_Data::2 62496 -system.ruby.network.routers01.throttle1.msg_bytes.Response_Control::2 1904 -system.ruby.network.routers01.throttle1.msg_bytes.Writeback_Data::2 5587704 -system.ruby.network.routers01.throttle1.msg_bytes.Writeback_Control::0 629360 -system.ruby.network.routers01.throttle1.msg_bytes.Unblock_Control::2 636320 -system.ruby.network.routers02.throttle0.link_utilization 5.271049 -system.ruby.network.routers02.throttle0.msg_count.Response_Data::2 77126 -system.ruby.network.routers02.throttle0.msg_count.ResponseL2hit_Data::2 556 -system.ruby.network.routers02.throttle0.msg_count.ResponseLocal_Data::2 806 -system.ruby.network.routers02.throttle0.msg_count.Response_Control::2 371 -system.ruby.network.routers02.throttle0.msg_count.Writeback_Control::0 78450 -system.ruby.network.routers02.throttle0.msg_count.Forwarded_Control::0 799 -system.ruby.network.routers02.throttle0.msg_count.Invalidate_Control::0 212 -system.ruby.network.routers02.throttle0.msg_bytes.Response_Data::2 5553072 -system.ruby.network.routers02.throttle0.msg_bytes.ResponseL2hit_Data::2 40032 -system.ruby.network.routers02.throttle0.msg_bytes.ResponseLocal_Data::2 58032 -system.ruby.network.routers02.throttle0.msg_bytes.Response_Control::2 2968 -system.ruby.network.routers02.throttle0.msg_bytes.Writeback_Control::0 627600 -system.ruby.network.routers02.throttle0.msg_bytes.Forwarded_Control::0 6392 -system.ruby.network.routers02.throttle0.msg_bytes.Invalidate_Control::0 1696 -system.ruby.network.routers02.throttle1.link_utilization 6.308835 -system.ruby.network.routers02.throttle1.msg_count.Request_Control::0 78492 -system.ruby.network.routers02.throttle1.msg_count.ResponseLocal_Data::2 799 -system.ruby.network.routers02.throttle1.msg_count.Response_Control::2 212 -system.ruby.network.routers02.throttle1.msg_count.Writeback_Data::2 77494 -system.ruby.network.routers02.throttle1.msg_count.Writeback_Control::0 78450 -system.ruby.network.routers02.throttle1.msg_count.Unblock_Control::2 79228 -system.ruby.network.routers02.throttle1.msg_bytes.Request_Control::0 627936 -system.ruby.network.routers02.throttle1.msg_bytes.ResponseLocal_Data::2 57528 -system.ruby.network.routers02.throttle1.msg_bytes.Response_Control::2 1696 -system.ruby.network.routers02.throttle1.msg_bytes.Writeback_Data::2 5579568 -system.ruby.network.routers02.throttle1.msg_bytes.Writeback_Control::0 627600 -system.ruby.network.routers02.throttle1.msg_bytes.Unblock_Control::2 633824 -system.ruby.network.routers03.throttle0.link_utilization 5.273101 -system.ruby.network.routers03.throttle0.msg_count.Response_Data::2 77107 -system.ruby.network.routers03.throttle0.msg_count.ResponseL2hit_Data::2 585 -system.ruby.network.routers03.throttle0.msg_count.ResponseLocal_Data::2 823 -system.ruby.network.routers03.throttle0.msg_count.Response_Control::2 403 -system.ruby.network.routers03.throttle0.msg_count.Writeback_Control::0 78482 -system.ruby.network.routers03.throttle0.msg_count.Forwarded_Control::0 780 -system.ruby.network.routers03.throttle0.msg_count.Invalidate_Control::0 230 -system.ruby.network.routers03.throttle0.msg_bytes.Response_Data::2 5551704 -system.ruby.network.routers03.throttle0.msg_bytes.ResponseL2hit_Data::2 42120 -system.ruby.network.routers03.throttle0.msg_bytes.ResponseLocal_Data::2 59256 -system.ruby.network.routers03.throttle0.msg_bytes.Response_Control::2 3224 -system.ruby.network.routers03.throttle0.msg_bytes.Writeback_Control::0 627856 -system.ruby.network.routers03.throttle0.msg_bytes.Forwarded_Control::0 6240 -system.ruby.network.routers03.throttle0.msg_bytes.Invalidate_Control::0 1840 -system.ruby.network.routers03.throttle1.link_utilization 6.307280 -system.ruby.network.routers03.throttle1.msg_count.Request_Control::0 78519 -system.ruby.network.routers03.throttle1.msg_count.ResponseLocal_Data::2 780 -system.ruby.network.routers03.throttle1.msg_count.Response_Control::2 230 -system.ruby.network.routers03.throttle1.msg_count.Writeback_Data::2 77472 -system.ruby.network.routers03.throttle1.msg_count.Writeback_Control::0 78482 -system.ruby.network.routers03.throttle1.msg_count.Unblock_Control::2 79288 -system.ruby.network.routers03.throttle1.msg_bytes.Request_Control::0 628152 -system.ruby.network.routers03.throttle1.msg_bytes.ResponseLocal_Data::2 56160 -system.ruby.network.routers03.throttle1.msg_bytes.Response_Control::2 1840 -system.ruby.network.routers03.throttle1.msg_bytes.Writeback_Data::2 5577984 -system.ruby.network.routers03.throttle1.msg_bytes.Writeback_Control::0 627856 -system.ruby.network.routers03.throttle1.msg_bytes.Unblock_Control::2 634304 -system.ruby.network.routers04.throttle0.link_utilization 5.274777 -system.ruby.network.routers04.throttle0.msg_count.Response_Data::2 77149 -system.ruby.network.routers04.throttle0.msg_count.ResponseL2hit_Data::2 567 -system.ruby.network.routers04.throttle0.msg_count.ResponseLocal_Data::2 822 -system.ruby.network.routers04.throttle0.msg_count.Response_Control::2 382 -system.ruby.network.routers04.throttle0.msg_count.Writeback_Control::0 78501 -system.ruby.network.routers04.throttle0.msg_count.Forwarded_Control::0 842 -system.ruby.network.routers04.throttle0.msg_count.Invalidate_Control::0 213 -system.ruby.network.routers04.throttle0.msg_bytes.Response_Data::2 5554728 -system.ruby.network.routers04.throttle0.msg_bytes.ResponseL2hit_Data::2 40824 -system.ruby.network.routers04.throttle0.msg_bytes.ResponseLocal_Data::2 59184 -system.ruby.network.routers04.throttle0.msg_bytes.Response_Control::2 3056 -system.ruby.network.routers04.throttle0.msg_bytes.Writeback_Control::0 628008 -system.ruby.network.routers04.throttle0.msg_bytes.Forwarded_Control::0 6736 -system.ruby.network.routers04.throttle0.msg_bytes.Invalidate_Control::0 1704 -system.ruby.network.routers04.throttle1.link_utilization 6.313843 -system.ruby.network.routers04.throttle1.msg_count.Request_Control::0 78541 -system.ruby.network.routers04.throttle1.msg_count.ResponseLocal_Data::2 842 -system.ruby.network.routers04.throttle1.msg_count.Response_Control::2 213 -system.ruby.network.routers04.throttle1.msg_count.Writeback_Data::2 77514 -system.ruby.network.routers04.throttle1.msg_count.Writeback_Control::0 78501 -system.ruby.network.routers04.throttle1.msg_count.Unblock_Control::2 79307 -system.ruby.network.routers04.throttle1.msg_bytes.Request_Control::0 628328 -system.ruby.network.routers04.throttle1.msg_bytes.ResponseLocal_Data::2 60624 -system.ruby.network.routers04.throttle1.msg_bytes.Response_Control::2 1704 -system.ruby.network.routers04.throttle1.msg_bytes.Writeback_Data::2 5581008 -system.ruby.network.routers04.throttle1.msg_bytes.Writeback_Control::0 628008 -system.ruby.network.routers04.throttle1.msg_bytes.Unblock_Control::2 634456 -system.ruby.network.routers05.throttle0.link_utilization 5.269460 -system.ruby.network.routers05.throttle0.msg_count.Response_Data::2 77063 -system.ruby.network.routers05.throttle0.msg_count.ResponseL2hit_Data::2 543 -system.ruby.network.routers05.throttle0.msg_count.ResponseLocal_Data::2 852 -system.ruby.network.routers05.throttle0.msg_count.Response_Control::2 403 -system.ruby.network.routers05.throttle0.msg_count.Writeback_Control::0 78419 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+system.ruby.network.routers00.msg_bytes.Forwarded_Control::0 6296 +system.ruby.network.routers00.msg_bytes.Invalidate_Control::0 1936 +system.ruby.network.routers00.msg_bytes.Unblock_Control::2 630648 +system.ruby.network.routers01.percent_links_utilized 5.794585 +system.ruby.network.routers01.msg_count.Request_Control::0 77929 +system.ruby.network.routers01.msg_count.Response_Data::2 76537 +system.ruby.network.routers01.msg_count.ResponseL2hit_Data::2 588 +system.ruby.network.routers01.msg_count.ResponseLocal_Data::2 1665 +system.ruby.network.routers01.msg_count.Response_Control::2 602 +system.ruby.network.routers01.msg_count.Writeback_Data::2 76906 +system.ruby.network.routers01.msg_count.Writeback_Control::0 155780 +system.ruby.network.routers01.msg_count.Forwarded_Control::0 863 +system.ruby.network.routers01.msg_count.Invalidate_Control::0 233 +system.ruby.network.routers01.msg_count.Unblock_Control::2 78663 +system.ruby.network.routers01.msg_bytes.Request_Control::0 623432 +system.ruby.network.routers01.msg_bytes.Response_Data::2 5510664 +system.ruby.network.routers01.msg_bytes.ResponseL2hit_Data::2 42336 +system.ruby.network.routers01.msg_bytes.ResponseLocal_Data::2 119880 +system.ruby.network.routers01.msg_bytes.Response_Control::2 4816 +system.ruby.network.routers01.msg_bytes.Writeback_Data::2 5537232 +system.ruby.network.routers01.msg_bytes.Writeback_Control::0 1246240 +system.ruby.network.routers01.msg_bytes.Forwarded_Control::0 6904 +system.ruby.network.routers01.msg_bytes.Invalidate_Control::0 1864 +system.ruby.network.routers01.msg_bytes.Unblock_Control::2 629304 +system.ruby.network.routers02.percent_links_utilized 5.793798 +system.ruby.network.routers02.msg_count.Request_Control::0 77932 +system.ruby.network.routers02.msg_count.Response_Data::2 76549 +system.ruby.network.routers02.msg_count.ResponseL2hit_Data::2 582 +system.ruby.network.routers02.msg_count.ResponseLocal_Data::2 1633 +system.ruby.network.routers02.msg_count.Response_Control::2 588 +system.ruby.network.routers02.msg_count.Writeback_Data::2 76908 +system.ruby.network.routers02.msg_count.Writeback_Control::0 155796 +system.ruby.network.routers02.msg_count.Forwarded_Control::0 834 +system.ruby.network.routers02.msg_count.Invalidate_Control::0 235 +system.ruby.network.routers02.msg_count.Unblock_Control::2 78668 +system.ruby.network.routers02.msg_bytes.Request_Control::0 623456 +system.ruby.network.routers02.msg_bytes.Response_Data::2 5511528 +system.ruby.network.routers02.msg_bytes.ResponseL2hit_Data::2 41904 +system.ruby.network.routers02.msg_bytes.ResponseLocal_Data::2 117576 +system.ruby.network.routers02.msg_bytes.Response_Control::2 4704 +system.ruby.network.routers02.msg_bytes.Writeback_Data::2 5537376 +system.ruby.network.routers02.msg_bytes.Writeback_Control::0 1246368 +system.ruby.network.routers02.msg_bytes.Forwarded_Control::0 6672 +system.ruby.network.routers02.msg_bytes.Invalidate_Control::0 1880 +system.ruby.network.routers02.msg_bytes.Unblock_Control::2 629344 +system.ruby.network.routers03.percent_links_utilized 5.809520 +system.ruby.network.routers03.msg_count.Request_Control::0 78185 +system.ruby.network.routers03.msg_count.Response_Data::2 76731 +system.ruby.network.routers03.msg_count.ResponseL2hit_Data::2 592 +system.ruby.network.routers03.msg_count.ResponseLocal_Data::2 1621 +system.ruby.network.routers03.msg_count.Response_Control::2 593 +system.ruby.network.routers03.msg_count.Writeback_Data::2 77136 +system.ruby.network.routers03.msg_count.Writeback_Control::0 156302 +system.ruby.network.routers03.msg_count.Forwarded_Control::0 761 +system.ruby.network.routers03.msg_count.Invalidate_Control::0 199 +system.ruby.network.routers03.msg_count.Unblock_Control::2 78995 +system.ruby.network.routers03.msg_bytes.Request_Control::0 625480 +system.ruby.network.routers03.msg_bytes.Response_Data::2 5524632 +system.ruby.network.routers03.msg_bytes.ResponseL2hit_Data::2 42624 +system.ruby.network.routers03.msg_bytes.ResponseLocal_Data::2 116712 +system.ruby.network.routers03.msg_bytes.Response_Control::2 4744 +system.ruby.network.routers03.msg_bytes.Writeback_Data::2 5553792 +system.ruby.network.routers03.msg_bytes.Writeback_Control::0 1250416 +system.ruby.network.routers03.msg_bytes.Forwarded_Control::0 6088 +system.ruby.network.routers03.msg_bytes.Invalidate_Control::0 1592 +system.ruby.network.routers03.msg_bytes.Unblock_Control::2 631960 +system.ruby.network.routers04.percent_links_utilized 5.826012 +system.ruby.network.routers04.msg_count.Request_Control::0 78368 +system.ruby.network.routers04.msg_count.Response_Data::2 76977 +system.ruby.network.routers04.msg_count.ResponseL2hit_Data::2 573 +system.ruby.network.routers04.msg_count.ResponseLocal_Data::2 1669 +system.ruby.network.routers04.msg_count.Response_Control::2 623 +system.ruby.network.routers04.msg_count.Writeback_Data::2 77318 +system.ruby.network.routers04.msg_count.Writeback_Control::0 156610 +system.ruby.network.routers04.msg_count.Forwarded_Control::0 852 +system.ruby.network.routers04.msg_count.Invalidate_Control::0 237 +system.ruby.network.routers04.msg_count.Unblock_Control::2 79114 +system.ruby.network.routers04.msg_bytes.Request_Control::0 626944 +system.ruby.network.routers04.msg_bytes.Response_Data::2 5542344 +system.ruby.network.routers04.msg_bytes.ResponseL2hit_Data::2 41256 +system.ruby.network.routers04.msg_bytes.ResponseLocal_Data::2 120168 +system.ruby.network.routers04.msg_bytes.Response_Control::2 4984 +system.ruby.network.routers04.msg_bytes.Writeback_Data::2 5566896 +system.ruby.network.routers04.msg_bytes.Writeback_Control::0 1252880 +system.ruby.network.routers04.msg_bytes.Forwarded_Control::0 6816 +system.ruby.network.routers04.msg_bytes.Invalidate_Control::0 1896 +system.ruby.network.routers04.msg_bytes.Unblock_Control::2 632912 +system.ruby.network.routers05.percent_links_utilized 5.781556 +system.ruby.network.routers05.msg_count.Request_Control::0 77782 +system.ruby.network.routers05.msg_count.Response_Data::2 76446 +system.ruby.network.routers05.msg_count.ResponseL2hit_Data::2 532 +system.ruby.network.routers05.msg_count.ResponseLocal_Data::2 1636 +system.ruby.network.routers05.msg_count.Response_Control::2 633 +system.ruby.network.routers05.msg_count.Writeback_Data::2 76715 +system.ruby.network.routers05.msg_count.Writeback_Control::0 155472 +system.ruby.network.routers05.msg_count.Forwarded_Control::0 835 +system.ruby.network.routers05.msg_count.Invalidate_Control::0 244 +system.ruby.network.routers05.msg_count.Unblock_Control::2 78550 +system.ruby.network.routers05.msg_bytes.Request_Control::0 622256 +system.ruby.network.routers05.msg_bytes.Response_Data::2 5504112 +system.ruby.network.routers05.msg_bytes.ResponseL2hit_Data::2 38304 +system.ruby.network.routers05.msg_bytes.ResponseLocal_Data::2 117792 +system.ruby.network.routers05.msg_bytes.Response_Control::2 5064 +system.ruby.network.routers05.msg_bytes.Writeback_Data::2 5523480 +system.ruby.network.routers05.msg_bytes.Writeback_Control::0 1243776 +system.ruby.network.routers05.msg_bytes.Forwarded_Control::0 6680 +system.ruby.network.routers05.msg_bytes.Invalidate_Control::0 1952 +system.ruby.network.routers05.msg_bytes.Unblock_Control::2 628400 +system.ruby.network.routers06.percent_links_utilized 5.776735 +system.ruby.network.routers06.msg_count.Request_Control::0 77715 +system.ruby.network.routers06.msg_count.Response_Data::2 76360 +system.ruby.network.routers06.msg_count.ResponseL2hit_Data::2 521 +system.ruby.network.routers06.msg_count.ResponseLocal_Data::2 1655 +system.ruby.network.routers06.msg_count.Response_Control::2 576 +system.ruby.network.routers06.msg_count.Writeback_Data::2 76677 +system.ruby.network.routers06.msg_count.Writeback_Control::0 155326 +system.ruby.network.routers06.msg_count.Forwarded_Control::0 825 +system.ruby.network.routers06.msg_count.Invalidate_Control::0 205 +system.ruby.network.routers06.msg_count.Unblock_Control::2 78486 +system.ruby.network.routers06.msg_bytes.Request_Control::0 621720 +system.ruby.network.routers06.msg_bytes.Response_Data::2 5497920 +system.ruby.network.routers06.msg_bytes.ResponseL2hit_Data::2 37512 +system.ruby.network.routers06.msg_bytes.ResponseLocal_Data::2 119160 +system.ruby.network.routers06.msg_bytes.Response_Control::2 4608 +system.ruby.network.routers06.msg_bytes.Writeback_Data::2 5520744 +system.ruby.network.routers06.msg_bytes.Writeback_Control::0 1242608 +system.ruby.network.routers06.msg_bytes.Forwarded_Control::0 6600 +system.ruby.network.routers06.msg_bytes.Invalidate_Control::0 1640 +system.ruby.network.routers06.msg_bytes.Unblock_Control::2 627888 +system.ruby.network.routers07.percent_links_utilized 5.783225 +system.ruby.network.routers07.msg_count.Request_Control::0 77805 +system.ruby.network.routers07.msg_count.Response_Data::2 76400 +system.ruby.network.routers07.msg_count.ResponseL2hit_Data::2 558 +system.ruby.network.routers07.msg_count.ResponseLocal_Data::2 1702 +system.ruby.network.routers07.msg_count.Response_Control::2 661 +system.ruby.network.routers07.msg_count.Writeback_Data::2 76707 +system.ruby.network.routers07.msg_count.Writeback_Control::0 155500 +system.ruby.network.routers07.msg_count.Forwarded_Control::0 858 +system.ruby.network.routers07.msg_count.Invalidate_Control::0 244 +system.ruby.network.routers07.msg_count.Unblock_Control::2 78600 +system.ruby.network.routers07.msg_bytes.Request_Control::0 622440 +system.ruby.network.routers07.msg_bytes.Response_Data::2 5500800 +system.ruby.network.routers07.msg_bytes.ResponseL2hit_Data::2 40176 +system.ruby.network.routers07.msg_bytes.ResponseLocal_Data::2 122544 +system.ruby.network.routers07.msg_bytes.Response_Control::2 5288 +system.ruby.network.routers07.msg_bytes.Writeback_Data::2 5522904 +system.ruby.network.routers07.msg_bytes.Writeback_Control::0 1244000 +system.ruby.network.routers07.msg_bytes.Forwarded_Control::0 6864 +system.ruby.network.routers07.msg_bytes.Invalidate_Control::0 1952 +system.ruby.network.routers07.msg_bytes.Unblock_Control::2 628800 +system.ruby.network.routers08.percent_links_utilized 76.881076 +system.ruby.network.routers08.msg_count.Request_Control::0 623734 +system.ruby.network.routers08.msg_count.Request_Control::1 612559 +system.ruby.network.routers08.msg_count.Response_Data::2 1225087 +system.ruby.network.routers08.msg_count.ResponseL2hit_Data::2 4560 +system.ruby.network.routers08.msg_count.Response_Control::2 1204 +system.ruby.network.routers08.msg_count.Writeback_Data::2 835203 +system.ruby.network.routers08.msg_count.Writeback_Control::0 1246740 +system.ruby.network.routers08.msg_count.Writeback_Control::1 439847 +system.ruby.network.routers08.msg_count.Forwarded_Control::0 6615 +system.ruby.network.routers08.msg_count.Invalidate_Control::0 1830 +system.ruby.network.routers08.msg_count.Unblock_Control::2 1242434 +system.ruby.network.routers08.msg_bytes.Request_Control::0 4989872 +system.ruby.network.routers08.msg_bytes.Request_Control::1 4900472 +system.ruby.network.routers08.msg_bytes.Response_Data::2 88206264 +system.ruby.network.routers08.msg_bytes.ResponseL2hit_Data::2 328320 +system.ruby.network.routers08.msg_bytes.Response_Control::2 9632 +system.ruby.network.routers08.msg_bytes.Writeback_Data::2 60134616 +system.ruby.network.routers08.msg_bytes.Writeback_Control::0 9973920 +system.ruby.network.routers08.msg_bytes.Writeback_Control::1 3518776 +system.ruby.network.routers08.msg_bytes.Forwarded_Control::0 52920 +system.ruby.network.routers08.msg_bytes.Invalidate_Control::0 14640 +system.ruby.network.routers08.msg_bytes.Unblock_Control::2 9939472 +system.ruby.network.routers09.percent_links_utilized 30.933959 +system.ruby.network.routers09.msg_count.Request_Control::1 612559 +system.ruby.network.routers09.msg_count.Response_Data::2 612551 +system.ruby.network.routers09.msg_count.Writeback_Data::2 219920 +system.ruby.network.routers09.msg_count.Writeback_Control::1 439854 +system.ruby.network.routers09.msg_count.Unblock_Control::2 612533 +system.ruby.network.routers09.msg_bytes.Request_Control::1 4900472 +system.ruby.network.routers09.msg_bytes.Response_Data::2 44103672 +system.ruby.network.routers09.msg_bytes.Writeback_Data::2 15834240 +system.ruby.network.routers09.msg_bytes.Writeback_Control::1 3518832 +system.ruby.network.routers09.msg_bytes.Unblock_Control::2 4900264 +system.ruby.network.routers10.percent_links_utilized 15.417687 +system.ruby.network.routers10.msg_count.Request_Control::0 623734 +system.ruby.network.routers10.msg_count.Request_Control::1 612559 +system.ruby.network.routers10.msg_count.Response_Data::2 1225088 +system.ruby.network.routers10.msg_count.ResponseL2hit_Data::2 4560 +system.ruby.network.routers10.msg_count.ResponseLocal_Data::2 6615 +system.ruby.network.routers10.msg_count.Response_Control::2 3043 +system.ruby.network.routers10.msg_count.Writeback_Data::2 835203 +system.ruby.network.routers10.msg_count.Writeback_Control::0 1246740 +system.ruby.network.routers10.msg_count.Writeback_Control::1 439847 +system.ruby.network.routers10.msg_count.Forwarded_Control::0 6615 +system.ruby.network.routers10.msg_count.Invalidate_Control::0 1839 +system.ruby.network.routers10.msg_count.Unblock_Control::2 1242433 +system.ruby.network.routers10.msg_bytes.Request_Control::0 4989872 +system.ruby.network.routers10.msg_bytes.Request_Control::1 4900472 +system.ruby.network.routers10.msg_bytes.Response_Data::2 88206336 +system.ruby.network.routers10.msg_bytes.ResponseL2hit_Data::2 328320 +system.ruby.network.routers10.msg_bytes.ResponseLocal_Data::2 476280 +system.ruby.network.routers10.msg_bytes.Response_Control::2 24344 +system.ruby.network.routers10.msg_bytes.Writeback_Data::2 60134616 +system.ruby.network.routers10.msg_bytes.Writeback_Control::0 9973920 +system.ruby.network.routers10.msg_bytes.Writeback_Control::1 3518776 +system.ruby.network.routers10.msg_bytes.Forwarded_Control::0 52920 +system.ruby.network.routers10.msg_bytes.Invalidate_Control::0 14712 +system.ruby.network.routers10.msg_bytes.Unblock_Control::2 9939464 +system.ruby.network.msg_count.Request_Control 3708882 +system.ruby.network.msg_count.Response_Data 3675269 +system.ruby.network.msg_count.ResponseL2hit_Data 13680 +system.ruby.network.msg_count.ResponseLocal_Data 19845 +system.ruby.network.msg_count.Response_Control 9129 +system.ruby.network.msg_count.Writeback_Data 2505609 +system.ruby.network.msg_count.Writeback_Control 5059771 +system.ruby.network.msg_count.Forwarded_Control 19845 +system.ruby.network.msg_count.Invalidate_Control 5508 +system.ruby.network.msg_count.Unblock_Control 3727307 +system.ruby.network.msg_byte.Request_Control 29671056 +system.ruby.network.msg_byte.Response_Data 264619368 +system.ruby.network.msg_byte.ResponseL2hit_Data 984960 +system.ruby.network.msg_byte.ResponseLocal_Data 1428840 +system.ruby.network.msg_byte.Response_Control 73032 +system.ruby.network.msg_byte.Writeback_Data 180403848 +system.ruby.network.msg_byte.Writeback_Control 40478168 +system.ruby.network.msg_byte.Forwarded_Control 158760 +system.ruby.network.msg_byte.Invalidate_Control 44064 +system.ruby.network.msg_byte.Unblock_Control 29818456 +system.ruby.network.routers00.throttle0.link_utilization 5.280221 +system.ruby.network.routers00.throttle0.msg_count.Response_Data::2 76543 +system.ruby.network.routers00.throttle0.msg_count.ResponseL2hit_Data::2 614 +system.ruby.network.routers00.throttle0.msg_count.ResponseLocal_Data::2 862 +system.ruby.network.routers00.throttle0.msg_count.Response_Control::2 364 +system.ruby.network.routers00.throttle0.msg_count.Writeback_Control::0 77978 +system.ruby.network.routers00.throttle0.msg_count.Forwarded_Control::0 787 +system.ruby.network.routers00.throttle0.msg_count.Invalidate_Control::0 242 +system.ruby.network.routers00.throttle0.msg_bytes.Response_Data::2 5511096 +system.ruby.network.routers00.throttle0.msg_bytes.ResponseL2hit_Data::2 44208 +system.ruby.network.routers00.throttle0.msg_bytes.ResponseLocal_Data::2 62064 +system.ruby.network.routers00.throttle0.msg_bytes.Response_Control::2 2912 +system.ruby.network.routers00.throttle0.msg_bytes.Writeback_Control::0 623824 +system.ruby.network.routers00.throttle0.msg_bytes.Forwarded_Control::0 6296 +system.ruby.network.routers00.throttle0.msg_bytes.Invalidate_Control::0 1936 +system.ruby.network.routers00.throttle1.link_utilization 6.313010 +system.ruby.network.routers00.throttle1.msg_count.Request_Control::0 78021 +system.ruby.network.routers00.throttle1.msg_count.ResponseLocal_Data::2 787 +system.ruby.network.routers00.throttle1.msg_count.Response_Control::2 242 +system.ruby.network.routers00.throttle1.msg_count.Writeback_Data::2 76916 +system.ruby.network.routers00.throttle1.msg_count.Writeback_Control::0 77979 +system.ruby.network.routers00.throttle1.msg_count.Unblock_Control::2 78831 +system.ruby.network.routers00.throttle1.msg_bytes.Request_Control::0 624168 +system.ruby.network.routers00.throttle1.msg_bytes.ResponseLocal_Data::2 56664 +system.ruby.network.routers00.throttle1.msg_bytes.Response_Control::2 1936 +system.ruby.network.routers00.throttle1.msg_bytes.Writeback_Data::2 5537952 +system.ruby.network.routers00.throttle1.msg_bytes.Writeback_Control::0 623832 +system.ruby.network.routers00.throttle1.msg_bytes.Unblock_Control::2 630648 +system.ruby.network.routers01.throttle0.link_utilization 5.274566 +system.ruby.network.routers01.throttle0.msg_count.Response_Data::2 76537 +system.ruby.network.routers01.throttle0.msg_count.ResponseL2hit_Data::2 588 +system.ruby.network.routers01.throttle0.msg_count.ResponseLocal_Data::2 802 +system.ruby.network.routers01.throttle0.msg_count.Response_Control::2 369 +system.ruby.network.routers01.throttle0.msg_count.Writeback_Control::0 77890 +system.ruby.network.routers01.throttle0.msg_count.Forwarded_Control::0 863 +system.ruby.network.routers01.throttle0.msg_count.Invalidate_Control::0 233 +system.ruby.network.routers01.throttle0.msg_bytes.Response_Data::2 5510664 +system.ruby.network.routers01.throttle0.msg_bytes.ResponseL2hit_Data::2 42336 +system.ruby.network.routers01.throttle0.msg_bytes.ResponseLocal_Data::2 57744 +system.ruby.network.routers01.throttle0.msg_bytes.Response_Control::2 2952 +system.ruby.network.routers01.throttle0.msg_bytes.Writeback_Control::0 623120 +system.ruby.network.routers01.throttle0.msg_bytes.Forwarded_Control::0 6904 +system.ruby.network.routers01.throttle0.msg_bytes.Invalidate_Control::0 1864 +system.ruby.network.routers01.throttle1.link_utilization 6.314605 +system.ruby.network.routers01.throttle1.msg_count.Request_Control::0 77929 +system.ruby.network.routers01.throttle1.msg_count.ResponseLocal_Data::2 863 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1759416 +system.ruby.network.routers09.throttle0.msg_bytes.Unblock_Control::2 4900264 +system.ruby.network.routers09.throttle1.link_utilization 38.732608 +system.ruby.network.routers09.throttle1.msg_count.Response_Data::2 612551 +system.ruby.network.routers09.throttle1.msg_count.Writeback_Control::1 219927 +system.ruby.network.routers09.throttle1.msg_bytes.Response_Data::2 44103672 +system.ruby.network.routers09.throttle1.msg_bytes.Writeback_Control::1 1759416 +system.ruby.network.routers10.throttle0.link_utilization 5.280248 +system.ruby.network.routers10.throttle0.msg_count.Response_Data::2 76543 +system.ruby.network.routers10.throttle0.msg_count.ResponseL2hit_Data::2 614 +system.ruby.network.routers10.throttle0.msg_count.ResponseLocal_Data::2 862 +system.ruby.network.routers10.throttle0.msg_count.Response_Control::2 364 +system.ruby.network.routers10.throttle0.msg_count.Writeback_Control::0 77978 +system.ruby.network.routers10.throttle0.msg_count.Forwarded_Control::0 787 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219927 +system.ruby.network.routers10.throttle9.msg_count.Unblock_Control::2 612533 +system.ruby.network.routers10.throttle9.msg_bytes.Request_Control::1 4900472 +system.ruby.network.routers10.throttle9.msg_bytes.Writeback_Data::2 15834240 +system.ruby.network.routers10.throttle9.msg_bytes.Writeback_Control::1 1759416 +system.ruby.network.routers10.throttle9.msg_bytes.Unblock_Control::2 4900264 system.ruby.LD.latency_hist::bucket_size 2048 system.ruby.LD.latency_hist::max_bucket 20479 -system.ruby.LD.latency_hist::samples 403736 -system.ruby.LD.latency_hist::mean 1517.424765 -system.ruby.LD.latency_hist::gmean 1020.440366 -system.ruby.LD.latency_hist::stdev 1496.326206 -system.ruby.LD.latency_hist | 305362 75.63% 75.63% | 70366 17.43% 93.06% | 20348 5.04% 98.10% | 5804 1.44% 99.54% | 1436 0.36% 99.90% | 342 0.08% 99.98% | 68 0.02% 100.00% | 10 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.latency_hist::total 403736 +system.ruby.LD.latency_hist::samples 401957 +system.ruby.LD.latency_hist::mean 1517.986374 +system.ruby.LD.latency_hist::gmean 1021.285101 +system.ruby.LD.latency_hist::stdev 1496.687265 +system.ruby.LD.latency_hist | 304009 75.63% 75.63% | 70241 17.47% 93.11% | 20001 4.98% 98.08% | 5818 1.45% 99.53% | 1467 0.36% 99.90% | 321 0.08% 99.98% | 81 0.02% 100.00% | 16 0.00% 100.00% | 2 0.00% 100.00% | 1 0.00% 100.00% +system.ruby.LD.latency_hist::total 401957 system.ruby.LD.hit_latency_hist::bucket_size 1 system.ruby.LD.hit_latency_hist::max_bucket 9 -system.ruby.LD.hit_latency_hist::samples 89 +system.ruby.LD.hit_latency_hist::samples 84 system.ruby.LD.hit_latency_hist::mean 3 system.ruby.LD.hit_latency_hist::gmean 3.000000 -system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 89 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.hit_latency_hist::total 89 +system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 84 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.hit_latency_hist::total 84 system.ruby.LD.miss_latency_hist::bucket_size 2048 system.ruby.LD.miss_latency_hist::max_bucket 20479 -system.ruby.LD.miss_latency_hist::samples 403647 -system.ruby.LD.miss_latency_hist::mean 1517.758680 -system.ruby.LD.miss_latency_hist::gmean 1021.752799 -system.ruby.LD.miss_latency_hist::stdev 1496.322154 -system.ruby.LD.miss_latency_hist | 305273 75.63% 75.63% | 70366 17.43% 93.06% | 20348 5.04% 98.10% | 5804 1.44% 99.54% | 1436 0.36% 99.90% | 342 0.08% 99.98% | 68 0.02% 100.00% | 10 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.miss_latency_hist::total 403647 +system.ruby.LD.miss_latency_hist::samples 401873 +system.ruby.LD.miss_latency_hist::mean 1518.303039 +system.ruby.LD.miss_latency_hist::gmean 1022.530435 +system.ruby.LD.miss_latency_hist::stdev 1496.683383 +system.ruby.LD.miss_latency_hist | 303925 75.63% 75.63% | 70241 17.48% 93.11% | 20001 4.98% 98.08% | 5818 1.45% 99.53% | 1467 0.37% 99.90% | 321 0.08% 99.98% | 81 0.02% 100.00% | 16 0.00% 100.00% | 2 0.00% 100.00% | 1 0.00% 100.00% +system.ruby.LD.miss_latency_hist::total 401873 system.ruby.ST.latency_hist::bucket_size 2048 system.ruby.ST.latency_hist::max_bucket 20479 -system.ruby.ST.latency_hist::samples 224477 -system.ruby.ST.latency_hist::mean 1522.618959 -system.ruby.ST.latency_hist::gmean 1026.724184 -system.ruby.ST.latency_hist::stdev 1499.014037 -system.ruby.ST.latency_hist | 169552 75.53% 75.53% | 39227 17.47% 93.01% | 11359 5.06% 98.07% | 3296 1.47% 99.54% | 827 0.37% 99.90% | 170 0.08% 99.98% | 39 0.02% 100.00% | 7 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.latency_hist::total 224477 +system.ruby.ST.latency_hist::samples 221868 +system.ruby.ST.latency_hist::mean 1518.470564 +system.ruby.ST.latency_hist::gmean 1026.561445 +system.ruby.ST.latency_hist::stdev 1492.696810 +system.ruby.ST.latency_hist | 167683 75.58% 75.58% | 38896 17.53% 93.11% | 11196 5.05% 98.16% | 3060 1.38% 99.53% | 776 0.35% 99.88% | 195 0.09% 99.97% | 46 0.02% 99.99% | 13 0.01% 100.00% | 3 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.latency_hist::total 221868 system.ruby.ST.hit_latency_hist::bucket_size 1 system.ruby.ST.hit_latency_hist::max_bucket 9 -system.ruby.ST.hit_latency_hist::samples 30 +system.ruby.ST.hit_latency_hist::samples 24 system.ruby.ST.hit_latency_hist::mean 3 system.ruby.ST.hit_latency_hist::gmean 3.000000 -system.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 30 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.hit_latency_hist::total 30 +system.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 24 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.hit_latency_hist::total 24 system.ruby.ST.miss_latency_hist::bucket_size 2048 system.ruby.ST.miss_latency_hist::max_bucket 20479 -system.ruby.ST.miss_latency_hist::samples 224447 -system.ruby.ST.miss_latency_hist::mean 1522.822074 -system.ruby.ST.miss_latency_hist::gmean 1027.525327 -system.ruby.ST.miss_latency_hist::stdev 1499.011250 -system.ruby.ST.miss_latency_hist | 169522 75.53% 75.53% | 39227 17.48% 93.01% | 11359 5.06% 98.07% | 3296 1.47% 99.54% | 827 0.37% 99.90% | 170 0.08% 99.98% | 39 0.02% 100.00% | 7 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.miss_latency_hist::total 224447 -system.ruby.L1Cache_Controller.Load | 50543 12.52% 12.52% | 50614 12.53% 25.05% | 50311 12.46% 37.51% | 50685 12.55% 50.06% | 50542 12.52% 62.57% | 50424 12.49% 75.06% | 50331 12.46% 87.52% | 50386 12.48% 100.00% -system.ruby.L1Cache_Controller.Load::total 403836 -system.ruby.L1Cache_Controller.Store | 28185 12.55% 12.55% | 28135 12.53% 25.09% | 28201 12.56% 37.65% | 27871 12.41% 50.06% | 28023 12.48% 62.54% | 28050 12.49% 75.04% | 28175 12.55% 87.59% | 27873 12.41% 100.00% -system.ruby.L1Cache_Controller.Store::total 224513 -system.ruby.L1Cache_Controller.L1_Replacement | 9456290 12.50% 12.50% | 9453861 12.49% 24.99% | 9456743 12.50% 37.49% | 9458000 12.50% 49.99% | 9456358 12.50% 62.49% | 9459066 12.50% 74.99% | 9459283 12.50% 87.49% | 9464648 12.51% 100.00% -system.ruby.L1Cache_Controller.L1_Replacement::total 75664249 -system.ruby.L1Cache_Controller.Fwd_GETX | 149 10.92% 10.92% | 197 14.43% 25.35% | 173 12.67% 38.02% | 174 12.75% 50.77% | 167 12.23% 63.00% | 160 11.72% 74.73% | 162 11.87% 86.59% | 183 13.41% 100.00% -system.ruby.L1Cache_Controller.Fwd_GETX::total 1365 -system.ruby.L1Cache_Controller.Fwd_GETS | 730 13.05% 13.05% | 740 13.23% 26.27% | 652 11.65% 37.93% | 650 11.62% 49.54% | 717 12.82% 62.36% | 700 12.51% 74.87% | 725 12.96% 87.83% | 681 12.17% 100.00% -system.ruby.L1Cache_Controller.Fwd_GETS::total 5595 -system.ruby.L1Cache_Controller.Inv | 233 12.80% 12.80% | 238 13.07% 25.86% | 212 11.64% 37.51% | 230 12.63% 50.14% | 213 11.70% 61.83% | 227 12.47% 74.30% | 221 12.14% 86.44% | 247 13.56% 100.00% -system.ruby.L1Cache_Controller.Inv::total 1821 -system.ruby.L1Cache_Controller.Ack | 380 12.46% 12.46% | 368 12.07% 24.52% | 371 12.16% 36.69% | 403 13.21% 49.90% | 382 12.52% 62.43% | 403 13.21% 75.64% | 379 12.43% 88.07% | 364 11.93% 100.00% -system.ruby.L1Cache_Controller.Ack::total 3050 -system.ruby.L1Cache_Controller.Data | 50306 12.51% 12.51% | 50385 12.53% 25.04% | 50094 12.46% 37.50% | 50490 12.56% 50.05% | 50329 12.52% 62.57% | 50235 12.49% 75.06% | 50131 12.47% 87.52% | 50173 12.48% 100.00% -system.ruby.L1Cache_Controller.Data::total 402143 -system.ruby.L1Cache_Controller.Exclusive_Data | 28370 12.56% 12.56% | 28338 12.54% 25.10% | 28394 12.57% 37.66% | 28025 12.40% 50.07% | 28209 12.48% 62.55% | 28223 12.49% 75.04% | 28329 12.54% 87.58% | 28063 12.42% 100.00% -system.ruby.L1Cache_Controller.Exclusive_Data::total 225951 -system.ruby.L1Cache_Controller.Writeback_Ack | 646 12.65% 12.65% | 679 13.29% 25.94% | 600 11.75% 37.69% | 633 12.39% 50.08% | 633 12.39% 62.47% | 657 12.86% 75.33% | 612 11.98% 87.31% | 648 12.69% 100.00% +system.ruby.ST.miss_latency_hist::samples 221844 +system.ruby.ST.miss_latency_hist::mean 1518.634513 +system.ruby.ST.miss_latency_hist::gmean 1027.209710 +system.ruby.ST.miss_latency_hist::stdev 1492.694318 +system.ruby.ST.miss_latency_hist | 167659 75.58% 75.58% | 38896 17.53% 93.11% | 11196 5.05% 98.16% | 3060 1.38% 99.53% | 776 0.35% 99.88% | 195 0.09% 99.97% | 46 0.02% 99.99% | 13 0.01% 100.00% | 3 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.miss_latency_hist::total 221844 +system.ruby.Directory_Controller.GETX 219948 0.00% 0.00% +system.ruby.Directory_Controller.GETS 392622 0.00% 0.00% +system.ruby.Directory_Controller.PUTX 219827 0.00% 0.00% +system.ruby.Directory_Controller.PUTO_SHARERS 100 0.00% 0.00% +system.ruby.Directory_Controller.Unblock 142754 0.00% 0.00% +system.ruby.Directory_Controller.Last_Unblock 249849 0.00% 0.00% +system.ruby.Directory_Controller.Exclusive_Unblock 219930 0.00% 0.00% +system.ruby.Directory_Controller.Dirty_Writeback 219920 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Data 612551 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Ack 219920 0.00% 0.00% +system.ruby.Directory_Controller.I.GETX 78370 0.00% 0.00% +system.ruby.Directory_Controller.I.GETS 142761 0.00% 0.00% +system.ruby.Directory_Controller.I.Memory_Ack 219658 0.00% 0.00% +system.ruby.Directory_Controller.S.GETX 141568 0.00% 0.00% +system.ruby.Directory_Controller.S.GETS 249860 0.00% 0.00% +system.ruby.Directory_Controller.S.Memory_Ack 100 0.00% 0.00% +system.ruby.Directory_Controller.M.PUTX 219827 0.00% 0.00% +system.ruby.Directory_Controller.M.PUTO_SHARERS 100 0.00% 0.00% +system.ruby.Directory_Controller.IS.GETX 1 0.00% 0.00% +system.ruby.Directory_Controller.IS.Unblock 142754 0.00% 0.00% +system.ruby.Directory_Controller.IS.Memory_Data 142760 0.00% 0.00% +system.ruby.Directory_Controller.IS.Memory_Ack 108 0.00% 0.00% +system.ruby.Directory_Controller.SS.GETX 9 0.00% 0.00% +system.ruby.Directory_Controller.SS.Last_Unblock 249849 0.00% 0.00% +system.ruby.Directory_Controller.SS.Memory_Data 249856 0.00% 0.00% +system.ruby.Directory_Controller.MM.Exclusive_Unblock 219930 0.00% 0.00% +system.ruby.Directory_Controller.MM.Memory_Data 219935 0.00% 0.00% +system.ruby.Directory_Controller.MM.Memory_Ack 54 0.00% 0.00% +system.ruby.Directory_Controller.MI.GETS 1 0.00% 0.00% +system.ruby.Directory_Controller.MI.Dirty_Writeback 219820 0.00% 0.00% +system.ruby.Directory_Controller.MIS.Dirty_Writeback 100 0.00% 0.00% +system.ruby.L1Cache_Controller.Load | 50198 12.49% 12.49% | 50329 12.52% 25.01% | 50260 12.50% 37.51% | 50323 12.52% 50.03% | 50663 12.60% 62.63% | 49920 12.42% 75.04% | 50235 12.50% 87.54% | 50089 12.46% 100.00% +system.ruby.L1Cache_Controller.Load::total 402017 +system.ruby.L1Cache_Controller.Store | 27854 12.55% 12.55% | 27614 12.45% 25.00% | 27687 12.48% 37.48% | 27880 12.57% 50.04% | 27728 12.50% 62.54% | 27882 12.57% 75.10% | 27494 12.39% 87.49% | 27747 12.51% 100.00% +system.ruby.L1Cache_Controller.Store::total 221886 +system.ruby.L1Cache_Controller.L1_Replacement | 9386167 12.50% 12.50% | 9387429 12.50% 25.00% | 9388272 12.50% 37.51% | 9379351 12.49% 50.00% | 9374313 12.49% 62.48% | 9387856 12.50% 74.99% | 9392579 12.51% 87.50% | 9387972 12.50% 100.00% +system.ruby.L1Cache_Controller.L1_Replacement::total 75083939 +system.ruby.L1Cache_Controller.Fwd_GETX | 167 12.69% 12.69% | 158 12.01% 24.70% | 171 12.99% 37.69% | 153 11.63% 49.32% | 166 12.61% 61.93% | 175 13.30% 75.23% | 168 12.77% 87.99% | 158 12.01% 100.00% +system.ruby.L1Cache_Controller.Fwd_GETX::total 1316 +system.ruby.L1Cache_Controller.Fwd_GETS | 655 11.67% 11.67% | 742 13.22% 24.90% | 703 12.53% 37.43% | 638 11.37% 48.80% | 733 13.06% 61.86% | 704 12.55% 74.41% | 700 12.48% 86.88% | 736 13.12% 100.00% +system.ruby.L1Cache_Controller.Fwd_GETS::total 5611 +system.ruby.L1Cache_Controller.Inv | 242 13.16% 13.16% | 233 12.67% 25.83% | 235 12.78% 38.61% | 199 10.82% 49.43% | 237 12.89% 62.32% | 244 13.27% 75.58% | 205 11.15% 86.73% | 244 13.27% 100.00% +system.ruby.L1Cache_Controller.Inv::total 1839 +system.ruby.L1Cache_Controller.Ack | 364 11.96% 11.96% | 369 12.13% 24.09% | 353 11.60% 35.69% | 394 12.95% 48.64% | 386 12.68% 61.32% | 389 12.78% 74.10% | 371 12.19% 86.30% | 417 13.70% 100.00% +system.ruby.L1Cache_Controller.Ack::total 3043 +system.ruby.L1Cache_Controller.Data | 49948 12.48% 12.48% | 50137 12.52% 25.00% | 50041 12.50% 37.50% | 50122 12.52% 50.02% | 50438 12.60% 62.62% | 49723 12.42% 75.04% | 50036 12.50% 87.54% | 49872 12.46% 100.00% +system.ruby.L1Cache_Controller.Data::total 400317 +system.ruby.L1Cache_Controller.Exclusive_Data | 28070 12.56% 12.56% | 27790 12.44% 25.00% | 27889 12.48% 37.49% | 28061 12.56% 50.05% | 27929 12.50% 62.55% | 28056 12.56% 75.11% | 27675 12.39% 87.50% | 27930 12.50% 100.00% +system.ruby.L1Cache_Controller.Exclusive_Data::total 223400 +system.ruby.L1Cache_Controller.Writeback_Ack | 678 13.27% 13.27% | 610 11.94% 25.22% | 601 11.77% 36.98% | 683 13.37% 50.35% | 619 12.12% 62.47% | 623 12.20% 74.67% | 633 12.39% 87.06% | 661 12.94% 100.00% system.ruby.L1Cache_Controller.Writeback_Ack::total 5108 -system.ruby.L1Cache_Controller.Writeback_Ack_Data | 77750 12.52% 12.52% | 77745 12.52% 25.05% | 77634 12.51% 37.55% | 77612 12.50% 50.06% | 77650 12.51% 62.57% | 77523 12.49% 75.05% | 77567 12.50% 87.55% | 77298 12.45% 100.00% -system.ruby.L1Cache_Controller.Writeback_Ack_Data::total 620779 -system.ruby.L1Cache_Controller.Writeback_Nack | 248 13.20% 13.20% | 246 13.09% 26.29% | 216 11.50% 37.79% | 237 12.61% 50.40% | 218 11.60% 62.00% | 239 12.72% 74.72% | 231 12.29% 87.01% | 244 12.99% 100.00% -system.ruby.L1Cache_Controller.Writeback_Nack::total 1879 -system.ruby.L1Cache_Controller.All_acks | 28178 12.55% 12.55% | 28128 12.53% 25.09% | 28199 12.56% 37.65% | 27860 12.41% 50.06% | 28012 12.48% 62.54% | 28046 12.50% 75.04% | 28156 12.54% 87.58% | 27868 12.42% 100.00% -system.ruby.L1Cache_Controller.All_acks::total 224447 -system.ruby.L1Cache_Controller.Use_Timeout | 28370 12.56% 12.56% | 28338 12.54% 25.10% | 28394 12.57% 37.66% | 28025 12.40% 50.07% | 28209 12.48% 62.55% | 28223 12.49% 75.04% | 28329 12.54% 87.58% | 28063 12.42% 100.00% -system.ruby.L1Cache_Controller.Use_Timeout::total 225951 -system.ruby.L1Cache_Controller.I.Load | 50501 12.51% 12.51% | 50597 12.53% 25.04% | 50292 12.46% 37.50% | 50659 12.55% 50.05% | 50527 12.52% 62.57% | 50416 12.49% 75.06% | 50305 12.46% 87.52% | 50369 12.48% 100.00% -system.ruby.L1Cache_Controller.I.Load::total 403666 -system.ruby.L1Cache_Controller.I.Store | 28175 12.55% 12.55% | 28122 12.53% 25.08% | 28197 12.56% 37.65% | 27859 12.41% 50.06% | 28010 12.48% 62.54% | 28043 12.50% 75.04% | 28155 12.55% 87.58% | 27869 12.42% 100.00% -system.ruby.L1Cache_Controller.I.Store::total 224430 -system.ruby.L1Cache_Controller.I.L1_Replacement | 51 12.35% 12.35% | 56 13.56% 25.91% | 48 11.62% 37.53% | 47 11.38% 48.91% | 45 10.90% 59.81% | 52 12.59% 72.40% | 62 15.01% 87.41% | 52 12.59% 100.00% -system.ruby.L1Cache_Controller.I.L1_Replacement::total 413 -system.ruby.L1Cache_Controller.S.Load | 6 12.50% 12.50% | 7 14.58% 27.08% | 7 14.58% 41.67% | 9 18.75% 60.42% | 4 8.33% 68.75% | 4 8.33% 77.08% | 5 10.42% 87.50% | 6 12.50% 100.00% -system.ruby.L1Cache_Controller.S.Load::total 48 -system.ruby.L1Cache_Controller.S.Store | 4 16.00% 16.00% | 7 28.00% 44.00% | 3 12.00% 56.00% | 1 4.00% 60.00% | 4 16.00% 76.00% | 3 12.00% 88.00% | 2 8.00% 96.00% | 1 4.00% 100.00% -system.ruby.L1Cache_Controller.S.Store::total 25 -system.ruby.L1Cache_Controller.S.L1_Replacement | 50293 12.51% 12.51% | 50374 12.53% 25.04% | 50080 12.46% 37.49% | 50482 12.56% 50.05% | 50317 12.51% 62.57% | 50228 12.49% 75.06% | 50120 12.47% 87.52% | 50160 12.48% 100.00% -system.ruby.L1Cache_Controller.S.L1_Replacement::total 402054 -system.ruby.L1Cache_Controller.S.Fwd_GETS | 41 11.26% 11.26% | 43 11.81% 23.08% | 48 13.19% 36.26% | 56 15.38% 51.65% | 46 12.64% 64.29% | 46 12.64% 76.92% | 45 12.36% 89.29% | 39 10.71% 100.00% -system.ruby.L1Cache_Controller.S.Fwd_GETS::total 364 -system.ruby.L1Cache_Controller.S.Inv | 9 15.25% 15.25% | 3 5.08% 20.34% | 11 18.64% 38.98% | 7 11.86% 50.85% | 7 11.86% 62.71% | 4 6.78% 69.49% | 7 11.86% 81.36% | 11 18.64% 100.00% -system.ruby.L1Cache_Controller.S.Inv::total 59 -system.ruby.L1Cache_Controller.O.L1_Replacement | 1 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.O.L1_Replacement::total 2 -system.ruby.L1Cache_Controller.M.Store | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.Writeback_Ack_Data | 77051 12.50% 12.50% | 77032 12.50% 25.00% | 77045 12.50% 37.50% | 77265 12.54% 50.03% | 77446 12.56% 62.60% | 76863 12.47% 75.07% | 76819 12.46% 87.53% | 76844 12.47% 100.00% +system.ruby.L1Cache_Controller.Writeback_Ack_Data::total 616365 +system.ruby.L1Cache_Controller.Writeback_Nack | 249 13.13% 13.13% | 248 13.07% 26.20% | 252 13.28% 39.48% | 203 10.70% 50.18% | 240 12.65% 62.84% | 250 13.18% 76.01% | 210 11.07% 87.08% | 245 12.92% 100.00% +system.ruby.L1Cache_Controller.Writeback_Nack::total 1897 +system.ruby.L1Cache_Controller.All_acks | 27848 12.55% 12.55% | 27610 12.45% 25.00% | 27682 12.48% 37.48% | 27874 12.56% 50.04% | 27725 12.50% 62.54% | 27875 12.57% 75.10% | 27491 12.39% 87.50% | 27739 12.50% 100.00% +system.ruby.L1Cache_Controller.All_acks::total 221844 +system.ruby.L1Cache_Controller.Use_Timeout | 28069 12.56% 12.56% | 27790 12.44% 25.00% | 27888 12.48% 37.49% | 28061 12.56% 50.05% | 27928 12.50% 62.55% | 28056 12.56% 75.11% | 27675 12.39% 87.50% | 27930 12.50% 100.00% +system.ruby.L1Cache_Controller.Use_Timeout::total 223397 +system.ruby.L1Cache_Controller.I.Load | 50172 12.48% 12.48% | 50319 12.52% 25.00% | 50249 12.50% 37.51% | 50309 12.52% 50.03% | 50643 12.60% 62.63% | 49905 12.42% 75.05% | 50224 12.50% 87.54% | 50066 12.46% 100.00% +system.ruby.L1Cache_Controller.I.Load::total 401887 +system.ruby.L1Cache_Controller.I.Store | 27846 12.55% 12.55% | 27607 12.45% 25.00% | 27681 12.48% 37.48% | 27875 12.57% 50.04% | 27723 12.50% 62.54% | 27875 12.57% 75.11% | 27487 12.39% 87.50% | 27734 12.50% 100.00% +system.ruby.L1Cache_Controller.I.Store::total 221828 +system.ruby.L1Cache_Controller.I.L1_Replacement | 49 11.45% 11.45% | 54 12.62% 24.07% | 52 12.15% 36.21% | 38 8.88% 45.09% | 71 16.59% 61.68% | 55 12.85% 74.53% | 53 12.38% 86.92% | 56 13.08% 100.00% +system.ruby.L1Cache_Controller.I.L1_Replacement::total 428 +system.ruby.L1Cache_Controller.S.Load | 4 13.33% 13.33% | 4 13.33% 26.67% | 4 13.33% 40.00% | 2 6.67% 46.67% | 1 3.33% 50.00% | 7 23.33% 73.33% | 1 3.33% 76.67% | 7 23.33% 100.00% +system.ruby.L1Cache_Controller.S.Load::total 30 +system.ruby.L1Cache_Controller.S.Store | 3 13.64% 13.64% | 3 13.64% 27.27% | 2 9.09% 36.36% | 1 4.55% 40.91% | 2 9.09% 50.00% | 2 9.09% 59.09% | 4 18.18% 77.27% | 5 22.73% 100.00% +system.ruby.L1Cache_Controller.S.Store::total 22 +system.ruby.L1Cache_Controller.S.L1_Replacement | 49939 12.48% 12.48% | 50125 12.52% 25.00% | 50030 12.50% 37.50% | 50115 12.52% 50.02% | 50424 12.60% 62.62% | 49714 12.42% 75.04% | 50028 12.50% 87.54% | 49858 12.46% 100.00% +system.ruby.L1Cache_Controller.S.L1_Replacement::total 400233 +system.ruby.L1Cache_Controller.S.Fwd_GETS | 43 12.72% 12.72% | 41 12.13% 24.85% | 42 12.43% 37.28% | 41 12.13% 49.41% | 37 10.95% 60.36% | 43 12.72% 73.08% | 48 14.20% 87.28% | 43 12.72% 100.00% +system.ruby.L1Cache_Controller.S.Fwd_GETS::total 338 +system.ruby.L1Cache_Controller.S.Inv | 6 11.11% 11.11% | 7 12.96% 24.07% | 8 14.81% 38.89% | 5 9.26% 48.15% | 10 18.52% 66.67% | 6 11.11% 77.78% | 4 7.41% 85.19% | 8 14.81% 100.00% +system.ruby.L1Cache_Controller.S.Inv::total 54 +system.ruby.L1Cache_Controller.O.L1_Replacement | 1 20.00% 20.00% | 1 20.00% 40.00% | 2 40.00% 80.00% | 0 0.00% 80.00% | 0 0.00% 80.00% | 0 0.00% 80.00% | 1 20.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.O.L1_Replacement::total 5 +system.ruby.L1Cache_Controller.M.Store | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% system.ruby.L1Cache_Controller.M.Store::total 1 -system.ruby.L1Cache_Controller.M.L1_Replacement | 191 12.77% 12.77% | 210 14.04% 26.80% | 195 13.03% 39.84% | 163 10.90% 50.74% | 196 13.10% 63.84% | 177 11.83% 75.67% | 169 11.30% 86.97% | 195 13.03% 100.00% -system.ruby.L1Cache_Controller.M.L1_Replacement::total 1496 -system.ruby.L1Cache_Controller.M.Fwd_GETX | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 20.00% 20.00% | 0 0.00% 20.00% | 0 0.00% 20.00% | 4 80.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.M.Fwd_GETX::total 5 -system.ruby.L1Cache_Controller.M.Fwd_GETS | 1 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.M.Fwd_GETS::total 2 -system.ruby.L1Cache_Controller.M_W.L1_Replacement | 395 10.57% 10.57% | 427 11.43% 22.00% | 786 21.03% 43.03% | 434 11.61% 54.64% | 301 8.05% 62.70% | 536 14.34% 77.04% | 484 12.95% 89.99% | 374 10.01% 100.00% -system.ruby.L1Cache_Controller.M_W.L1_Replacement::total 3737 -system.ruby.L1Cache_Controller.M_W.Fwd_GETX | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 2 22.22% 22.22% | 0 0.00% 22.22% | 0 0.00% 22.22% | 7 77.78% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.M_W.Fwd_GETX::total 9 -system.ruby.L1Cache_Controller.M_W.Use_Timeout | 192 12.77% 12.77% | 210 13.96% 26.73% | 195 12.97% 39.69% | 165 10.97% 50.66% | 197 13.10% 63.76% | 177 11.77% 75.53% | 173 11.50% 87.03% | 195 12.97% 100.00% -system.ruby.L1Cache_Controller.M_W.Use_Timeout::total 1504 -system.ruby.L1Cache_Controller.MM.Load | 1 7.69% 7.69% | 3 23.08% 30.77% | 2 15.38% 46.15% | 1 7.69% 53.85% | 0 0.00% 53.85% | 0 0.00% 53.85% | 3 23.08% 76.92% | 3 23.08% 100.00% -system.ruby.L1Cache_Controller.MM.Load::total 13 -system.ruby.L1Cache_Controller.MM.Store | 2 25.00% 25.00% | 1 12.50% 37.50% | 1 12.50% 50.00% | 1 12.50% 62.50% | 0 0.00% 62.50% | 1 12.50% 75.00% | 1 12.50% 87.50% | 1 12.50% 100.00% -system.ruby.L1Cache_Controller.MM.Store::total 8 -system.ruby.L1Cache_Controller.MM.L1_Replacement | 28136 12.56% 12.56% | 28075 12.53% 25.08% | 28162 12.57% 37.65% | 27822 12.42% 50.06% | 27974 12.48% 62.55% | 27998 12.49% 75.04% | 28105 12.54% 87.58% | 27827 12.42% 100.00% -system.ruby.L1Cache_Controller.MM.L1_Replacement::total 224099 -system.ruby.L1Cache_Controller.MM.Fwd_GETX | 13 9.85% 9.85% | 25 18.94% 28.79% | 20 15.15% 43.94% | 16 12.12% 56.06% | 15 11.36% 67.42% | 12 9.09% 76.52% | 16 12.12% 88.64% | 15 11.36% 100.00% -system.ruby.L1Cache_Controller.MM.Fwd_GETX::total 132 -system.ruby.L1Cache_Controller.MM.Fwd_GETS | 29 13.36% 13.36% | 28 12.90% 26.27% | 17 7.83% 34.10% | 23 10.60% 44.70% | 23 10.60% 55.30% | 36 16.59% 71.89% | 35 16.13% 88.02% | 26 11.98% 100.00% -system.ruby.L1Cache_Controller.MM.Fwd_GETS::total 217 -system.ruby.L1Cache_Controller.MM_W.Load | 6 21.43% 21.43% | 4 14.29% 35.71% | 3 10.71% 46.43% | 3 10.71% 57.14% | 6 21.43% 78.57% | 3 10.71% 89.29% | 1 3.57% 92.86% | 2 7.14% 100.00% -system.ruby.L1Cache_Controller.MM_W.Load::total 28 -system.ruby.L1Cache_Controller.MM_W.Store | 3 14.29% 14.29% | 2 9.52% 23.81% | 0 0.00% 23.81% | 5 23.81% 47.62% | 4 19.05% 66.67% | 2 9.52% 76.19% | 4 19.05% 95.24% | 1 4.76% 100.00% -system.ruby.L1Cache_Controller.MM_W.Store::total 21 -system.ruby.L1Cache_Controller.MM_W.L1_Replacement | 621119 12.62% 12.62% | 613463 12.47% 25.09% | 615369 12.51% 37.60% | 613454 12.47% 50.06% | 615301 12.50% 62.57% | 615852 12.52% 75.08% | 613919 12.48% 87.56% | 612169 12.44% 100.00% -system.ruby.L1Cache_Controller.MM_W.L1_Replacement::total 4920646 -system.ruby.L1Cache_Controller.MM_W.Fwd_GETX | 12 9.45% 9.45% | 34 26.77% 36.22% | 11 8.66% 44.88% | 15 11.81% 56.69% | 15 11.81% 68.50% | 17 13.39% 81.89% | 4 3.15% 85.04% | 19 14.96% 100.00% -system.ruby.L1Cache_Controller.MM_W.Fwd_GETX::total 127 -system.ruby.L1Cache_Controller.MM_W.Fwd_GETS | 25 12.25% 12.25% | 35 17.16% 29.41% | 15 7.35% 36.76% | 27 13.24% 50.00% | 27 13.24% 63.24% | 27 13.24% 76.47% | 27 13.24% 89.71% | 21 10.29% 100.00% -system.ruby.L1Cache_Controller.MM_W.Fwd_GETS::total 204 -system.ruby.L1Cache_Controller.MM_W.Use_Timeout | 28178 12.55% 12.55% | 28128 12.53% 25.09% | 28199 12.56% 37.65% | 27860 12.41% 50.06% | 28012 12.48% 62.54% | 28046 12.50% 75.04% | 28156 12.54% 87.58% | 27868 12.42% 100.00% -system.ruby.L1Cache_Controller.MM_W.Use_Timeout::total 224447 -system.ruby.L1Cache_Controller.IM.L1_Replacement | 3178623 12.60% 12.60% | 3133531 12.42% 25.02% | 3166168 12.55% 37.57% | 3128956 12.40% 49.97% | 3171906 12.57% 62.54% | 3132218 12.41% 74.96% | 3164131 12.54% 87.50% | 3154429 12.50% 100.00% -system.ruby.L1Cache_Controller.IM.L1_Replacement::total 25229962 -system.ruby.L1Cache_Controller.IM.Ack | 163 13.27% 13.27% | 155 12.62% 25.90% | 149 12.13% 38.03% | 163 13.27% 51.30% | 150 12.21% 63.52% | 156 12.70% 76.22% | 152 12.38% 88.60% | 140 11.40% 100.00% -system.ruby.L1Cache_Controller.IM.Ack::total 1228 -system.ruby.L1Cache_Controller.IM.Exclusive_Data | 28174 12.55% 12.55% | 28121 12.53% 25.08% | 28196 12.56% 37.65% | 27859 12.41% 50.06% | 28009 12.48% 62.54% | 28043 12.50% 75.04% | 28154 12.55% 87.58% | 27867 12.42% 100.00% -system.ruby.L1Cache_Controller.IM.Exclusive_Data::total 224423 -system.ruby.L1Cache_Controller.SM.L1_Replacement | 1133 22.51% 22.51% | 986 19.59% 42.09% | 762 15.14% 57.23% | 192 3.81% 61.04% | 902 17.92% 78.96% | 385 7.65% 86.61% | 473 9.40% 96.01% | 201 3.99% 100.00% -system.ruby.L1Cache_Controller.SM.L1_Replacement::total 5034 -system.ruby.L1Cache_Controller.SM.Inv | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.SM.Inv::total 1 -system.ruby.L1Cache_Controller.SM.Exclusive_Data | 4 16.67% 16.67% | 7 29.17% 45.83% | 3 12.50% 58.33% | 1 4.17% 62.50% | 3 12.50% 75.00% | 3 12.50% 87.50% | 2 8.33% 95.83% | 1 4.17% 100.00% -system.ruby.L1Cache_Controller.SM.Exclusive_Data::total 24 -system.ruby.L1Cache_Controller.OM.L1_Replacement | 21441 12.36% 12.36% | 21531 12.41% 24.77% | 22013 12.69% 37.46% | 22555 13.00% 50.46% | 22104 12.74% 63.20% | 20567 11.85% 75.05% | 21301 12.28% 87.33% | 21980 12.67% 100.00% -system.ruby.L1Cache_Controller.OM.L1_Replacement::total 173492 -system.ruby.L1Cache_Controller.OM.Ack | 217 11.91% 11.91% | 213 11.69% 23.60% | 222 12.18% 35.78% | 240 13.17% 48.96% | 232 12.73% 61.69% | 247 13.56% 75.25% | 227 12.46% 87.71% | 224 12.29% 100.00% -system.ruby.L1Cache_Controller.OM.Ack::total 1822 -system.ruby.L1Cache_Controller.OM.All_acks | 28178 12.55% 12.55% | 28128 12.53% 25.09% | 28199 12.56% 37.65% | 27860 12.41% 50.06% | 28012 12.48% 62.54% | 28046 12.50% 75.04% | 28156 12.54% 87.58% | 27868 12.42% 100.00% -system.ruby.L1Cache_Controller.OM.All_acks::total 224447 -system.ruby.L1Cache_Controller.IS.L1_Replacement | 5554907 12.43% 12.43% | 5605208 12.54% 24.96% | 5573160 12.47% 37.43% | 5613895 12.56% 49.99% | 5567311 12.45% 62.44% | 5611053 12.55% 75.00% | 5580519 12.48% 87.48% | 5597261 12.52% 100.00% -system.ruby.L1Cache_Controller.IS.L1_Replacement::total 44703314 -system.ruby.L1Cache_Controller.IS.Data | 50306 12.51% 12.51% | 50385 12.53% 25.04% | 50094 12.46% 37.50% | 50490 12.56% 50.05% | 50329 12.52% 62.57% | 50235 12.49% 75.06% | 50131 12.47% 87.52% | 50173 12.48% 100.00% -system.ruby.L1Cache_Controller.IS.Data::total 402143 -system.ruby.L1Cache_Controller.IS.Exclusive_Data | 192 12.77% 12.77% | 210 13.96% 26.73% | 195 12.97% 39.69% | 165 10.97% 50.66% | 197 13.10% 63.76% | 177 11.77% 75.53% | 173 11.50% 87.03% | 195 12.97% 100.00% -system.ruby.L1Cache_Controller.IS.Exclusive_Data::total 1504 -system.ruby.L1Cache_Controller.SI.Load | 14 21.54% 21.54% | 2 3.08% 24.62% | 7 10.77% 35.38% | 13 20.00% 55.38% | 5 7.69% 63.08% | 1 1.54% 64.62% | 17 26.15% 90.77% | 6 9.23% 100.00% -system.ruby.L1Cache_Controller.SI.Load::total 65 -system.ruby.L1Cache_Controller.SI.Store | 1 3.57% 3.57% | 3 10.71% 14.29% | 0 0.00% 14.29% | 4 14.29% 28.57% | 5 17.86% 46.43% | 1 3.57% 50.00% | 13 46.43% 96.43% | 1 3.57% 100.00% -system.ruby.L1Cache_Controller.SI.Store::total 28 -system.ruby.L1Cache_Controller.SI.Fwd_GETS | 374 12.94% 12.94% | 385 13.32% 26.26% | 338 11.70% 37.96% | 361 12.49% 50.45% | 369 12.77% 63.22% | 354 12.25% 75.47% | 375 12.98% 88.44% | 334 11.56% 100.00% -system.ruby.L1Cache_Controller.SI.Fwd_GETS::total 2890 -system.ruby.L1Cache_Controller.SI.Inv | 224 12.72% 12.72% | 235 13.34% 26.06% | 201 11.41% 37.48% | 223 12.66% 50.14% | 205 11.64% 61.78% | 223 12.66% 74.45% | 214 12.15% 86.60% | 236 13.40% 100.00% -system.ruby.L1Cache_Controller.SI.Inv::total 1761 -system.ruby.L1Cache_Controller.SI.Writeback_Ack | 645 12.63% 12.63% | 679 13.30% 25.94% | 600 11.75% 37.69% | 632 12.38% 50.07% | 632 12.38% 62.45% | 657 12.87% 75.32% | 612 11.99% 87.31% | 648 12.69% 100.00% -system.ruby.L1Cache_Controller.SI.Writeback_Ack::total 5105 -system.ruby.L1Cache_Controller.SI.Writeback_Ack_Data | 49424 12.51% 12.51% | 49460 12.52% 25.02% | 49279 12.47% 37.49% | 49627 12.56% 50.05% | 49480 12.52% 62.57% | 49348 12.49% 75.06% | 49294 12.47% 87.53% | 49276 12.47% 100.00% -system.ruby.L1Cache_Controller.SI.Writeback_Ack_Data::total 395188 -system.ruby.L1Cache_Controller.OI.Fwd_GETX | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.OI.Fwd_GETX::total 1 -system.ruby.L1Cache_Controller.OI.Fwd_GETS | 0 0.00% 0.00% | 1 11.11% 11.11% | 0 0.00% 11.11% | 1 11.11% 22.22% | 2 22.22% 44.44% | 3 33.33% 77.78% | 1 11.11% 88.89% | 1 11.11% 100.00% -system.ruby.L1Cache_Controller.OI.Fwd_GETS::total 9 -system.ruby.L1Cache_Controller.OI.Writeback_Ack_Data | 261 13.66% 13.66% | 248 12.98% 26.65% | 233 12.20% 38.85% | 182 9.53% 48.38% | 250 13.09% 61.47% | 234 12.25% 73.72% | 242 12.67% 86.39% | 260 13.61% 100.00% -system.ruby.L1Cache_Controller.OI.Writeback_Ack_Data::total 1910 -system.ruby.L1Cache_Controller.OI.Writeback_Nack | 24 20.69% 20.69% | 11 9.48% 30.17% | 13 11.21% 41.38% | 15 12.93% 54.31% | 13 11.21% 65.52% | 16 13.79% 79.31% | 16 13.79% 93.10% | 8 6.90% 100.00% -system.ruby.L1Cache_Controller.OI.Writeback_Nack::total 116 -system.ruby.L1Cache_Controller.MI.Load | 15 93.75% 93.75% | 1 6.25% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.MI.Load::total 16 -system.ruby.L1Cache_Controller.MI.Fwd_GETX | 124 11.37% 11.37% | 138 12.65% 24.01% | 141 12.92% 36.94% | 140 12.83% 49.77% | 137 12.56% 62.33% | 131 12.01% 74.34% | 131 12.01% 86.34% | 149 13.66% 100.00% -system.ruby.L1Cache_Controller.MI.Fwd_GETX::total 1091 -system.ruby.L1Cache_Controller.MI.Fwd_GETS | 260 13.62% 13.62% | 248 12.99% 26.61% | 234 12.26% 38.87% | 182 9.53% 48.40% | 249 13.04% 61.45% | 234 12.26% 73.70% | 242 12.68% 86.38% | 260 13.62% 100.00% -system.ruby.L1Cache_Controller.MI.Fwd_GETS::total 1909 -system.ruby.L1Cache_Controller.MI.Writeback_Ack_Data | 27942 12.55% 12.55% | 27899 12.53% 25.09% | 27982 12.57% 37.66% | 27663 12.43% 50.08% | 27784 12.48% 62.57% | 27810 12.49% 75.06% | 27901 12.53% 87.59% | 27613 12.41% 100.00% -system.ruby.L1Cache_Controller.MI.Writeback_Ack_Data::total 222594 -system.ruby.L1Cache_Controller.II.Writeback_Ack | 1 33.33% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 1 33.33% 66.67% | 1 33.33% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.II.Writeback_Ack::total 3 -system.ruby.L1Cache_Controller.II.Writeback_Ack_Data | 123 11.32% 11.32% | 138 12.70% 24.01% | 140 12.88% 36.89% | 140 12.88% 49.77% | 136 12.51% 62.28% | 131 12.05% 74.33% | 130 11.96% 86.29% | 149 13.71% 100.00% -system.ruby.L1Cache_Controller.II.Writeback_Ack_Data::total 1087 -system.ruby.L1Cache_Controller.II.Writeback_Nack | 224 12.71% 12.71% | 235 13.33% 26.04% | 203 11.51% 37.55% | 222 12.59% 50.14% | 205 11.63% 61.77% | 223 12.65% 74.42% | 215 12.20% 86.61% | 236 13.39% 100.00% -system.ruby.L1Cache_Controller.II.Writeback_Nack::total 1763 -system.ruby.L2Cache_Controller.L1_GETS 501706 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_GETX 280108 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_PUTO 131 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_PUTX 260500 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_PUTS_only 476451 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_PUTS 25484 0.00% 0.00% -system.ruby.L2Cache_Controller.All_Acks 222478 0.00% 0.00% -system.ruby.L2Cache_Controller.Data 616903 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_WBCLEANDATA 395188 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_WBDIRTYDATA 224504 0.00% 0.00% -system.ruby.L2Cache_Controller.Writeback_Ack 222462 0.00% 0.00% -system.ruby.L2Cache_Controller.Unblock 408333 0.00% 0.00% -system.ruby.L2Cache_Controller.Exclusive_Unblock 225951 0.00% 0.00% -system.ruby.L2Cache_Controller.L2_Replacement 690870 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.L1_GETS 394442 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.L1_GETX 219255 0.00% 0.00% -system.ruby.L2Cache_Controller.ILS.L1_GETS 3254 0.00% 0.00% -system.ruby.L2Cache_Controller.ILS.L1_GETX 1820 0.00% 0.00% -system.ruby.L2Cache_Controller.ILS.L1_PUTS_only 391949 0.00% 0.00% -system.ruby.L2Cache_Controller.ILS.L1_PUTS 3239 0.00% 0.00% -system.ruby.L2Cache_Controller.ILX.L1_GETS 2128 0.00% 0.00% -system.ruby.L2Cache_Controller.ILX.L1_GETX 1228 0.00% 0.00% -system.ruby.L2Cache_Controller.ILX.L1_PUTX 223680 0.00% 0.00% -system.ruby.L2Cache_Controller.ILX.L1_PUTS 1753 0.00% 0.00% +system.ruby.L1Cache_Controller.M.L1_Replacement | 221 14.26% 14.26% | 179 11.55% 25.81% | 205 13.23% 39.03% | 187 12.06% 51.10% | 204 13.16% 64.26% | 181 11.68% 75.94% | 182 11.74% 87.68% | 191 12.32% 100.00% +system.ruby.L1Cache_Controller.M.L1_Replacement::total 1550 +system.ruby.L1Cache_Controller.M.Fwd_GETS | 1 20.00% 20.00% | 1 20.00% 40.00% | 2 40.00% 80.00% | 0 0.00% 80.00% | 0 0.00% 80.00% | 0 0.00% 80.00% | 1 20.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.M.Fwd_GETS::total 5 +system.ruby.L1Cache_Controller.M_W.L1_Replacement | 591 14.10% 14.10% | 590 14.08% 28.18% | 722 17.23% 45.41% | 352 8.40% 53.81% | 599 14.29% 68.10% | 348 8.30% 76.40% | 686 16.37% 92.77% | 303 7.23% 100.00% +system.ruby.L1Cache_Controller.M_W.L1_Replacement::total 4191 +system.ruby.L1Cache_Controller.M_W.Fwd_GETS | 2 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.M_W.Fwd_GETS::total 2 +system.ruby.L1Cache_Controller.M_W.Use_Timeout | 222 14.27% 14.27% | 180 11.57% 25.84% | 207 13.30% 39.14% | 187 12.02% 51.16% | 204 13.11% 64.27% | 181 11.63% 75.90% | 184 11.83% 87.72% | 191 12.28% 100.00% +system.ruby.L1Cache_Controller.M_W.Use_Timeout::total 1556 +system.ruby.L1Cache_Controller.MM.Load | 2 8.70% 8.70% | 2 8.70% 17.39% | 3 13.04% 30.43% | 5 21.74% 52.17% | 3 13.04% 65.22% | 2 8.70% 73.91% | 2 8.70% 82.61% | 4 17.39% 100.00% +system.ruby.L1Cache_Controller.MM.Load::total 23 +system.ruby.L1Cache_Controller.MM.Store | 1 14.29% 14.29% | 0 0.00% 14.29% | 0 0.00% 14.29% | 2 28.57% 42.86% | 1 14.29% 57.14% | 1 14.29% 71.43% | 0 0.00% 71.43% | 2 28.57% 100.00% +system.ruby.L1Cache_Controller.MM.Store::total 7 +system.ruby.L1Cache_Controller.MM.L1_Replacement | 27804 12.55% 12.55% | 27563 12.45% 25.00% | 27637 12.48% 37.48% | 27840 12.57% 50.05% | 27663 12.49% 62.54% | 27826 12.56% 75.11% | 27443 12.39% 87.50% | 27691 12.50% 100.00% +system.ruby.L1Cache_Controller.MM.L1_Replacement::total 221467 +system.ruby.L1Cache_Controller.MM.Fwd_GETX | 17 14.41% 14.41% | 16 13.56% 27.97% | 14 11.86% 39.83% | 14 11.86% 51.69% | 20 16.95% 68.64% | 11 9.32% 77.97% | 15 12.71% 90.68% | 11 9.32% 100.00% +system.ruby.L1Cache_Controller.MM.Fwd_GETX::total 118 +system.ruby.L1Cache_Controller.MM.Fwd_GETS | 26 10.16% 10.16% | 31 12.11% 22.27% | 30 11.72% 33.98% | 19 7.42% 41.41% | 41 16.02% 57.42% | 38 14.84% 72.27% | 34 13.28% 85.55% | 37 14.45% 100.00% +system.ruby.L1Cache_Controller.MM.Fwd_GETS::total 256 +system.ruby.L1Cache_Controller.MM_W.Load | 3 9.68% 9.68% | 4 12.90% 22.58% | 2 6.45% 29.03% | 4 12.90% 41.94% | 5 16.13% 58.06% | 3 9.68% 67.74% | 4 12.90% 80.65% | 6 19.35% 100.00% +system.ruby.L1Cache_Controller.MM_W.Load::total 31 +system.ruby.L1Cache_Controller.MM_W.Store | 2 12.50% 12.50% | 1 6.25% 18.75% | 2 12.50% 31.25% | 1 6.25% 37.50% | 0 0.00% 37.50% | 4 25.00% 62.50% | 2 12.50% 75.00% | 4 25.00% 100.00% +system.ruby.L1Cache_Controller.MM_W.Store::total 16 +system.ruby.L1Cache_Controller.MM_W.L1_Replacement | 611213 12.52% 12.52% | 604769 12.39% 24.91% | 614347 12.59% 37.50% | 608910 12.48% 49.98% | 611746 12.53% 62.51% | 610049 12.50% 75.01% | 610144 12.50% 87.51% | 609423 12.49% 100.00% +system.ruby.L1Cache_Controller.MM_W.L1_Replacement::total 4880601 +system.ruby.L1Cache_Controller.MM_W.Fwd_GETX | 13 11.61% 11.61% | 15 13.39% 25.00% | 19 16.96% 41.96% | 10 8.93% 50.89% | 18 16.07% 66.96% | 16 14.29% 81.25% | 11 9.82% 91.07% | 10 8.93% 100.00% +system.ruby.L1Cache_Controller.MM_W.Fwd_GETX::total 112 +system.ruby.L1Cache_Controller.MM_W.Fwd_GETS | 20 10.10% 10.10% | 22 11.11% 21.21% | 21 10.61% 31.82% | 20 10.10% 41.92% | 29 14.65% 56.57% | 28 14.14% 70.71% | 32 16.16% 86.87% | 26 13.13% 100.00% +system.ruby.L1Cache_Controller.MM_W.Fwd_GETS::total 198 +system.ruby.L1Cache_Controller.MM_W.Use_Timeout | 27847 12.55% 12.55% | 27610 12.45% 25.00% | 27681 12.48% 37.48% | 27874 12.56% 50.04% | 27724 12.50% 62.54% | 27875 12.57% 75.10% | 27491 12.39% 87.50% | 27739 12.50% 100.00% +system.ruby.L1Cache_Controller.MM_W.Use_Timeout::total 221841 +system.ruby.L1Cache_Controller.IM.L1_Replacement | 3117685 12.52% 12.52% | 3071171 12.34% 24.86% | 3120650 12.54% 37.40% | 3140383 12.62% 50.02% | 3099421 12.45% 62.47% | 3146089 12.64% 75.11% | 3088522 12.41% 87.51% | 3108221 12.49% 100.00% +system.ruby.L1Cache_Controller.IM.L1_Replacement::total 24892142 +system.ruby.L1Cache_Controller.IM.Ack | 144 12.04% 12.04% | 147 12.29% 24.33% | 138 11.54% 35.87% | 150 12.54% 48.41% | 150 12.54% 60.95% | 142 11.87% 72.83% | 153 12.79% 85.62% | 172 14.38% 100.00% +system.ruby.L1Cache_Controller.IM.Ack::total 1196 +system.ruby.L1Cache_Controller.IM.Exclusive_Data | 27845 12.55% 12.55% | 27607 12.45% 25.00% | 27680 12.48% 37.48% | 27873 12.57% 50.04% | 27723 12.50% 62.54% | 27873 12.57% 75.11% | 27487 12.39% 87.50% | 27734 12.50% 100.00% +system.ruby.L1Cache_Controller.IM.Exclusive_Data::total 221822 +system.ruby.L1Cache_Controller.SM.L1_Replacement | 733 19.03% 19.03% | 966 25.08% 44.11% | 395 10.25% 54.36% | 251 6.52% 60.88% | 202 5.24% 66.12% | 281 7.29% 73.42% | 679 17.63% 91.04% | 345 8.96% 100.00% +system.ruby.L1Cache_Controller.SM.L1_Replacement::total 3852 +system.ruby.L1Cache_Controller.SM.Exclusive_Data | 3 13.64% 13.64% | 3 13.64% 27.27% | 2 9.09% 36.36% | 1 4.55% 40.91% | 2 9.09% 50.00% | 2 9.09% 59.09% | 4 18.18% 77.27% | 5 22.73% 100.00% +system.ruby.L1Cache_Controller.SM.Exclusive_Data::total 22 +system.ruby.L1Cache_Controller.OM.L1_Replacement | 22520 12.98% 12.98% | 21779 12.56% 25.54% | 21024 12.12% 37.66% | 21826 12.58% 50.25% | 21159 12.20% 62.45% | 22530 12.99% 75.44% | 21258 12.26% 87.70% | 21336 12.30% 100.00% +system.ruby.L1Cache_Controller.OM.L1_Replacement::total 173432 +system.ruby.L1Cache_Controller.OM.Ack | 220 11.91% 11.91% | 222 12.02% 23.93% | 215 11.64% 35.57% | 244 13.21% 48.78% | 236 12.78% 61.56% | 247 13.37% 74.93% | 218 11.80% 86.74% | 245 13.26% 100.00% +system.ruby.L1Cache_Controller.OM.Ack::total 1847 +system.ruby.L1Cache_Controller.OM.All_acks | 27848 12.55% 12.55% | 27610 12.45% 25.00% | 27682 12.48% 37.48% | 27874 12.56% 50.04% | 27725 12.50% 62.54% | 27875 12.57% 75.10% | 27491 12.39% 87.50% | 27739 12.50% 100.00% +system.ruby.L1Cache_Controller.OM.All_acks::total 221844 +system.ruby.L1Cache_Controller.IS.L1_Replacement | 5555411 12.48% 12.48% | 5610232 12.61% 25.09% | 5553208 12.48% 37.57% | 5529449 12.42% 49.99% | 5562824 12.50% 62.49% | 5530783 12.43% 74.92% | 5593583 12.57% 87.48% | 5570548 12.52% 100.00% +system.ruby.L1Cache_Controller.IS.L1_Replacement::total 44506038 +system.ruby.L1Cache_Controller.IS.Data | 49948 12.48% 12.48% | 50137 12.52% 25.00% | 50041 12.50% 37.50% | 50122 12.52% 50.02% | 50438 12.60% 62.62% | 49723 12.42% 75.04% | 50036 12.50% 87.54% | 49872 12.46% 100.00% +system.ruby.L1Cache_Controller.IS.Data::total 400317 +system.ruby.L1Cache_Controller.IS.Exclusive_Data | 222 14.27% 14.27% | 180 11.57% 25.84% | 207 13.30% 39.14% | 187 12.02% 51.16% | 204 13.11% 64.27% | 181 11.63% 75.90% | 184 11.83% 87.72% | 191 12.28% 100.00% +system.ruby.L1Cache_Controller.IS.Exclusive_Data::total 1556 +system.ruby.L1Cache_Controller.SI.Load | 12 37.50% 37.50% | 0 0.00% 37.50% | 2 6.25% 43.75% | 0 0.00% 43.75% | 11 34.38% 78.12% | 3 9.38% 87.50% | 3 9.38% 96.88% | 1 3.12% 100.00% +system.ruby.L1Cache_Controller.SI.Load::total 32 +system.ruby.L1Cache_Controller.SI.Store | 0 0.00% 0.00% | 3 42.86% 42.86% | 1 14.29% 57.14% | 0 0.00% 57.14% | 1 14.29% 71.43% | 0 0.00% 71.43% | 0 0.00% 71.43% | 2 28.57% 100.00% +system.ruby.L1Cache_Controller.SI.Store::total 7 +system.ruby.L1Cache_Controller.SI.Fwd_GETS | 329 11.65% 11.65% | 363 12.85% 24.50% | 347 12.29% 36.79% | 329 11.65% 48.44% | 389 13.77% 62.22% | 358 12.68% 74.89% | 337 11.93% 86.83% | 372 13.17% 100.00% +system.ruby.L1Cache_Controller.SI.Fwd_GETS::total 2824 +system.ruby.L1Cache_Controller.SI.Inv | 236 13.22% 13.22% | 226 12.66% 25.88% | 227 12.72% 38.60% | 194 10.87% 49.47% | 227 12.72% 62.18% | 238 13.33% 75.52% | 201 11.26% 86.78% | 236 13.22% 100.00% +system.ruby.L1Cache_Controller.SI.Inv::total 1785 +system.ruby.L1Cache_Controller.SI.Writeback_Ack | 675 13.24% 13.24% | 609 11.95% 25.19% | 601 11.79% 36.98% | 683 13.40% 50.37% | 618 12.12% 62.50% | 620 12.16% 74.66% | 632 12.40% 87.05% | 660 12.95% 100.00% +system.ruby.L1Cache_Controller.SI.Writeback_Ack::total 5098 +system.ruby.L1Cache_Controller.SI.Writeback_Ack_Data | 49027 12.46% 12.46% | 49290 12.53% 24.99% | 49202 12.51% 37.50% | 49238 12.52% 50.02% | 49579 12.60% 62.63% | 48856 12.42% 75.05% | 49193 12.51% 87.55% | 48962 12.45% 100.00% +system.ruby.L1Cache_Controller.SI.Writeback_Ack_Data::total 393347 +system.ruby.L1Cache_Controller.OI.Fwd_GETX | 1 16.67% 16.67% | 0 0.00% 16.67% | 0 0.00% 16.67% | 1 16.67% 33.33% | 0 0.00% 33.33% | 1 16.67% 50.00% | 1 16.67% 66.67% | 2 33.33% 100.00% +system.ruby.L1Cache_Controller.OI.Fwd_GETX::total 6 +system.ruby.L1Cache_Controller.OI.Fwd_GETS | 1 16.67% 16.67% | 0 0.00% 16.67% | 0 0.00% 16.67% | 1 16.67% 33.33% | 1 16.67% 50.00% | 2 33.33% 83.33% | 1 16.67% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.OI.Fwd_GETS::total 6 +system.ruby.L1Cache_Controller.OI.Writeback_Ack_Data | 233 11.76% 11.76% | 285 14.39% 26.15% | 263 13.28% 39.42% | 227 11.46% 50.88% | 236 11.91% 62.80% | 234 11.81% 74.61% | 247 12.47% 87.08% | 256 12.92% 100.00% +system.ruby.L1Cache_Controller.OI.Writeback_Ack_Data::total 1981 +system.ruby.L1Cache_Controller.OI.Writeback_Nack | 14 11.86% 11.86% | 22 18.64% 30.51% | 24 20.34% 50.85% | 9 7.63% 58.47% | 14 11.86% 70.34% | 15 12.71% 83.05% | 10 8.47% 91.53% | 10 8.47% 100.00% +system.ruby.L1Cache_Controller.OI.Writeback_Nack::total 118 +system.ruby.L1Cache_Controller.MI.Load | 5 35.71% 35.71% | 0 0.00% 35.71% | 0 0.00% 35.71% | 3 21.43% 57.14% | 0 0.00% 57.14% | 0 0.00% 57.14% | 1 7.14% 64.29% | 5 35.71% 100.00% +system.ruby.L1Cache_Controller.MI.Load::total 14 +system.ruby.L1Cache_Controller.MI.Store | 2 50.00% 50.00% | 0 0.00% 50.00% | 1 25.00% 75.00% | 1 25.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.MI.Store::total 4 +system.ruby.L1Cache_Controller.MI.Fwd_GETX | 136 12.59% 12.59% | 127 11.76% 24.35% | 138 12.78% 37.13% | 128 11.85% 48.98% | 128 11.85% 60.83% | 147 13.61% 74.44% | 141 13.06% 87.50% | 135 12.50% 100.00% +system.ruby.L1Cache_Controller.MI.Fwd_GETX::total 1080 +system.ruby.L1Cache_Controller.MI.Fwd_GETS | 233 11.76% 11.76% | 284 14.33% 26.08% | 261 13.17% 39.25% | 228 11.50% 50.76% | 236 11.91% 62.66% | 235 11.86% 74.52% | 247 12.46% 86.98% | 258 13.02% 100.00% +system.ruby.L1Cache_Controller.MI.Fwd_GETS::total 1982 +system.ruby.L1Cache_Controller.MI.Writeback_Ack_Data | 27656 12.57% 12.57% | 27331 12.43% 25.00% | 27443 12.48% 37.48% | 27671 12.58% 50.06% | 27503 12.50% 62.56% | 27625 12.56% 75.12% | 27237 12.38% 87.50% | 27489 12.50% 100.00% +system.ruby.L1Cache_Controller.MI.Writeback_Ack_Data::total 219955 +system.ruby.L1Cache_Controller.II.Store | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.II.Store::total 1 +system.ruby.L1Cache_Controller.II.Writeback_Ack | 3 30.00% 30.00% | 1 10.00% 40.00% | 0 0.00% 40.00% | 0 0.00% 40.00% | 1 10.00% 50.00% | 3 30.00% 80.00% | 1 10.00% 90.00% | 1 10.00% 100.00% +system.ruby.L1Cache_Controller.II.Writeback_Ack::total 10 +system.ruby.L1Cache_Controller.II.Writeback_Ack_Data | 135 12.48% 12.48% | 126 11.65% 24.12% | 137 12.66% 36.78% | 129 11.92% 48.71% | 128 11.83% 60.54% | 148 13.68% 74.21% | 142 13.12% 87.34% | 137 12.66% 100.00% +system.ruby.L1Cache_Controller.II.Writeback_Ack_Data::total 1082 +system.ruby.L1Cache_Controller.II.Writeback_Nack | 235 13.21% 13.21% | 226 12.70% 25.91% | 228 12.82% 38.73% | 194 10.91% 49.63% | 226 12.70% 62.34% | 235 13.21% 75.55% | 200 11.24% 86.79% | 235 13.21% 100.00% +system.ruby.L1Cache_Controller.II.Writeback_Nack::total 1779 +system.ruby.L2Cache_Controller.L1_GETS 499463 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_GETX 277459 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_PUTO 132 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_PUTX 259037 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_PUTS_only 475631 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_PUTS 24927 0.00% 0.00% +system.ruby.L2Cache_Controller.All_Acks 219934 0.00% 0.00% +system.ruby.L2Cache_Controller.Data 612544 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_WBCLEANDATA 393347 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_WBDIRTYDATA 221936 0.00% 0.00% +system.ruby.L2Cache_Controller.Writeback_Ack 219920 0.00% 0.00% +system.ruby.L2Cache_Controller.Unblock 406502 0.00% 0.00% +system.ruby.L2Cache_Controller.Exclusive_Unblock 223397 0.00% 0.00% +system.ruby.L2Cache_Controller.L2_Replacement 683777 0.00% 0.00% +system.ruby.L2Cache_Controller.NP.L1_GETS 392621 0.00% 0.00% +system.ruby.L2Cache_Controller.NP.L1_GETX 216702 0.00% 0.00% +system.ruby.L2Cache_Controller.ILS.L1_GETS 3162 0.00% 0.00% +system.ruby.L2Cache_Controller.ILS.L1_GETX 1833 0.00% 0.00% +system.ruby.L2Cache_Controller.ILS.L1_PUTS_only 390198 0.00% 0.00% +system.ruby.L2Cache_Controller.ILS.L1_PUTS 3149 0.00% 0.00% +system.ruby.L2Cache_Controller.ILX.L1_GETS 2243 0.00% 0.00% +system.ruby.L2Cache_Controller.ILX.L1_GETX 1198 0.00% 0.00% +system.ruby.L2Cache_Controller.ILX.L1_PUTX 221036 0.00% 0.00% +system.ruby.L2Cache_Controller.ILX.L1_PUTS 1768 0.00% 0.00% system.ruby.L2Cache_Controller.ILOX.L1_GETS 1 0.00% 0.00% -system.ruby.L2Cache_Controller.ILOX.L1_PUTO 117 0.00% 0.00% -system.ruby.L2Cache_Controller.ILOX.L1_PUTX 116 0.00% 0.00% -system.ruby.L2Cache_Controller.ILOSX.L1_GETS 8 0.00% 0.00% -system.ruby.L2Cache_Controller.ILOSX.L1_GETX 1 0.00% 0.00% -system.ruby.L2Cache_Controller.ILOSX.L1_PUTO 1 0.00% 0.00% -system.ruby.L2Cache_Controller.ILOSX.L1_PUTX 1793 0.00% 0.00% -system.ruby.L2Cache_Controller.ILOSX.L1_PUTS_only 118 0.00% 0.00% -system.ruby.L2Cache_Controller.ILOSX.L1_PUTS 5 0.00% 0.00% -system.ruby.L2Cache_Controller.S.L1_GETS 2517 0.00% 0.00% -system.ruby.L2Cache_Controller.S.L1_GETX 1396 0.00% 0.00% -system.ruby.L2Cache_Controller.S.L2_Replacement 391275 0.00% 0.00% -system.ruby.L2Cache_Controller.OLSX.L1_GETS 10 0.00% 0.00% -system.ruby.L2Cache_Controller.OLSX.L1_GETX 2 0.00% 0.00% -system.ruby.L2Cache_Controller.OLSX.L1_PUTX 2 0.00% 0.00% -system.ruby.L2Cache_Controller.OLSX.L1_PUTS_only 1700 0.00% 0.00% -system.ruby.L2Cache_Controller.OLSX.L1_PUTS 15 0.00% 0.00% -system.ruby.L2Cache_Controller.OLSX.L2_Replacement 91 0.00% 0.00% +system.ruby.L2Cache_Controller.ILOX.L1_GETX 2 0.00% 0.00% +system.ruby.L2Cache_Controller.ILOX.L1_PUTO 119 0.00% 0.00% +system.ruby.L2Cache_Controller.ILOX.L1_PUTX 118 0.00% 0.00% +system.ruby.L2Cache_Controller.ILOX.L1_PUTS 1 0.00% 0.00% +system.ruby.L2Cache_Controller.ILOSX.L1_GETS 5 0.00% 0.00% +system.ruby.L2Cache_Controller.ILOSX.L1_GETX 4 0.00% 0.00% +system.ruby.L2Cache_Controller.ILOSX.L1_PUTO 4 0.00% 0.00% +system.ruby.L2Cache_Controller.ILOSX.L1_PUTX 1859 0.00% 0.00% +system.ruby.L2Cache_Controller.ILOSX.L1_PUTS_only 122 0.00% 0.00% +system.ruby.L2Cache_Controller.ILOSX.L1_PUTS 12 0.00% 0.00% +system.ruby.L2Cache_Controller.S.L1_GETS 2531 0.00% 0.00% +system.ruby.L2Cache_Controller.S.L1_GETX 1394 0.00% 0.00% +system.ruby.L2Cache_Controller.S.L2_Replacement 389456 0.00% 0.00% +system.ruby.L2Cache_Controller.OLSX.L1_GETS 4 0.00% 0.00% +system.ruby.L2Cache_Controller.OLSX.L1_GETX 6 0.00% 0.00% +system.ruby.L2Cache_Controller.OLSX.L1_PUTX 1 0.00% 0.00% +system.ruby.L2Cache_Controller.OLSX.L1_PUTS_only 1756 0.00% 0.00% +system.ruby.L2Cache_Controller.OLSX.L1_PUTS 7 0.00% 0.00% +system.ruby.L2Cache_Controller.OLSX.L2_Replacement 100 0.00% 0.00% system.ruby.L2Cache_Controller.SLS.L1_GETS 18 0.00% 0.00% -system.ruby.L2Cache_Controller.SLS.L1_GETX 14 0.00% 0.00% -system.ruby.L2Cache_Controller.SLS.L1_PUTS_only 3244 0.00% 0.00% -system.ruby.L2Cache_Controller.SLS.L1_PUTS 26 0.00% 0.00% -system.ruby.L2Cache_Controller.SLS.L2_Replacement 2498 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L1_GETS 1287 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L1_GETX 739 0.00% 0.00% +system.ruby.L2Cache_Controller.SLS.L1_GETX 9 0.00% 0.00% +system.ruby.L2Cache_Controller.SLS.L1_PUTS_only 3189 0.00% 0.00% +system.ruby.L2Cache_Controller.SLS.L1_PUTS 22 0.00% 0.00% +system.ruby.L2Cache_Controller.SLS.L2_Replacement 2482 0.00% 0.00% +system.ruby.L2Cache_Controller.M.L1_GETS 1300 0.00% 0.00% +system.ruby.L2Cache_Controller.M.L1_GETX 701 0.00% 0.00% system.ruby.L2Cache_Controller.M.L1_PUTX 3 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L1_PUTS 5 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L2_Replacement 222382 0.00% 0.00% -system.ruby.L2Cache_Controller.ILOXW.L1_GETS 6 0.00% 0.00% -system.ruby.L2Cache_Controller.ILOXW.L1_PUTO 11 0.00% 0.00% -system.ruby.L2Cache_Controller.ILOXW.L1_PUTX 1580 0.00% 0.00% -system.ruby.L2Cache_Controller.ILOXW.L1_WBDIRTYDATA 117 0.00% 0.00% -system.ruby.L2Cache_Controller.ILOXW.Unblock 118 0.00% 0.00% -system.ruby.L2Cache_Controller.ILOSXW.L1_GETS 82 0.00% 0.00% -system.ruby.L2Cache_Controller.ILOSXW.L1_GETX 11 0.00% 0.00% -system.ruby.L2Cache_Controller.ILOSXW.L1_PUTX 60 0.00% 0.00% -system.ruby.L2Cache_Controller.ILOSXW.L1_PUTS_only 4226 0.00% 0.00% -system.ruby.L2Cache_Controller.ILOSXW.L1_PUTS 49 0.00% 0.00% -system.ruby.L2Cache_Controller.ILOSXW.L1_WBDIRTYDATA 1793 0.00% 0.00% -system.ruby.L2Cache_Controller.ILOSXW.Unblock 6 0.00% 0.00% -system.ruby.L2Cache_Controller.SLSW.L1_PUTS 119 0.00% 0.00% -system.ruby.L2Cache_Controller.SLSW.Unblock 26 0.00% 0.00% -system.ruby.L2Cache_Controller.SLSW.L2_Replacement 177 0.00% 0.00% -system.ruby.L2Cache_Controller.ILSW.L1_GETS 108 0.00% 0.00% -system.ruby.L2Cache_Controller.ILSW.L1_GETX 105 0.00% 0.00% -system.ruby.L2Cache_Controller.ILSW.L1_PUTS 11967 0.00% 0.00% -system.ruby.L2Cache_Controller.ILSW.L1_WBCLEANDATA 3239 0.00% 0.00% -system.ruby.L2Cache_Controller.IW.L1_GETS 16149 0.00% 0.00% -system.ruby.L2Cache_Controller.IW.L1_GETX 9267 0.00% 0.00% -system.ruby.L2Cache_Controller.IW.L1_WBCLEANDATA 391949 0.00% 0.00% -system.ruby.L2Cache_Controller.SW.L1_GETS 61 0.00% 0.00% -system.ruby.L2Cache_Controller.SW.L1_GETX 40 0.00% 0.00% -system.ruby.L2Cache_Controller.SW.Unblock 3244 0.00% 0.00% -system.ruby.L2Cache_Controller.SW.L2_Replacement 22454 0.00% 0.00% -system.ruby.L2Cache_Controller.OXW.L1_GETS 68 0.00% 0.00% -system.ruby.L2Cache_Controller.OXW.L1_GETX 42 0.00% 0.00% -system.ruby.L2Cache_Controller.OXW.Unblock 1700 0.00% 0.00% -system.ruby.L2Cache_Controller.OXW.L2_Replacement 9730 0.00% 0.00% -system.ruby.L2Cache_Controller.OLSXW.L1_PUTS_only 2 0.00% 0.00% -system.ruby.L2Cache_Controller.OLSXW.L1_PUTS 56 0.00% 0.00% -system.ruby.L2Cache_Controller.OLSXW.Unblock 15 0.00% 0.00% -system.ruby.L2Cache_Controller.OLSXW.L2_Replacement 148 0.00% 0.00% -system.ruby.L2Cache_Controller.ILXW.L1_GETS 5812 0.00% 0.00% -system.ruby.L2Cache_Controller.ILXW.L1_GETX 3784 0.00% 0.00% -system.ruby.L2Cache_Controller.ILXW.L1_PUTX 1588 0.00% 0.00% -system.ruby.L2Cache_Controller.ILXW.L1_PUTS 58 0.00% 0.00% -system.ruby.L2Cache_Controller.ILXW.L1_WBDIRTYDATA 222594 0.00% 0.00% -system.ruby.L2Cache_Controller.ILXW.Unblock 1086 0.00% 0.00% -system.ruby.L2Cache_Controller.IFLS.L1_GETS 256 0.00% 0.00% -system.ruby.L2Cache_Controller.IFLS.L1_GETX 135 0.00% 0.00% -system.ruby.L2Cache_Controller.IFLS.L1_PUTS_only 28230 0.00% 0.00% -system.ruby.L2Cache_Controller.IFLS.L1_PUTS 202 0.00% 0.00% -system.ruby.L2Cache_Controller.IFLS.Unblock 3254 0.00% 0.00% -system.ruby.L2Cache_Controller.IFLOX.L1_PUTO 2 0.00% 0.00% -system.ruby.L2Cache_Controller.IFLOX.L1_PUTS_only 7 0.00% 0.00% +system.ruby.L2Cache_Controller.M.L1_PUTS 6 0.00% 0.00% +system.ruby.L2Cache_Controller.M.L2_Replacement 219827 0.00% 0.00% +system.ruby.L2Cache_Controller.ILOXW.L1_GETS 17 0.00% 0.00% +system.ruby.L2Cache_Controller.ILOXW.L1_GETX 29 0.00% 0.00% +system.ruby.L2Cache_Controller.ILOXW.L1_PUTO 9 0.00% 0.00% +system.ruby.L2Cache_Controller.ILOXW.L1_PUTX 1686 0.00% 0.00% +system.ruby.L2Cache_Controller.ILOXW.L1_PUTS 13 0.00% 0.00% +system.ruby.L2Cache_Controller.ILOXW.L1_WBDIRTYDATA 119 0.00% 0.00% +system.ruby.L2Cache_Controller.ILOXW.Unblock 122 0.00% 0.00% +system.ruby.L2Cache_Controller.ILOSXW.L1_GETS 50 0.00% 0.00% +system.ruby.L2Cache_Controller.ILOSXW.L1_GETX 26 0.00% 0.00% +system.ruby.L2Cache_Controller.ILOSXW.L1_PUTX 86 0.00% 0.00% +system.ruby.L2Cache_Controller.ILOSXW.L1_PUTS_only 4049 0.00% 0.00% +system.ruby.L2Cache_Controller.ILOSXW.L1_PUTS 30 0.00% 0.00% +system.ruby.L2Cache_Controller.ILOSXW.L1_WBDIRTYDATA 1862 0.00% 0.00% +system.ruby.L2Cache_Controller.ILOSXW.Unblock 13 0.00% 0.00% +system.ruby.L2Cache_Controller.SLSW.L1_PUTS 112 0.00% 0.00% +system.ruby.L2Cache_Controller.SLSW.Unblock 22 0.00% 0.00% +system.ruby.L2Cache_Controller.SLSW.L2_Replacement 161 0.00% 0.00% +system.ruby.L2Cache_Controller.ILSW.L1_GETS 182 0.00% 0.00% +system.ruby.L2Cache_Controller.ILSW.L1_GETX 82 0.00% 0.00% +system.ruby.L2Cache_Controller.ILSW.L1_PUTS 11381 0.00% 0.00% +system.ruby.L2Cache_Controller.ILSW.L1_WBCLEANDATA 3149 0.00% 0.00% +system.ruby.L2Cache_Controller.IW.L1_GETS 16447 0.00% 0.00% +system.ruby.L2Cache_Controller.IW.L1_GETX 9062 0.00% 0.00% +system.ruby.L2Cache_Controller.IW.L1_WBCLEANDATA 390198 0.00% 0.00% +system.ruby.L2Cache_Controller.SW.L1_GETS 110 0.00% 0.00% +system.ruby.L2Cache_Controller.SW.L1_GETX 77 0.00% 0.00% +system.ruby.L2Cache_Controller.SW.Unblock 3189 0.00% 0.00% +system.ruby.L2Cache_Controller.SW.L2_Replacement 21395 0.00% 0.00% +system.ruby.L2Cache_Controller.OXW.L1_GETS 57 0.00% 0.00% +system.ruby.L2Cache_Controller.OXW.L1_GETX 14 0.00% 0.00% +system.ruby.L2Cache_Controller.OXW.L1_PUTS 9 0.00% 0.00% +system.ruby.L2Cache_Controller.OXW.Unblock 1756 0.00% 0.00% +system.ruby.L2Cache_Controller.OXW.L2_Replacement 8852 0.00% 0.00% +system.ruby.L2Cache_Controller.OLSXW.L1_PUTS 4 0.00% 0.00% +system.ruby.L2Cache_Controller.OLSXW.Unblock 7 0.00% 0.00% +system.ruby.L2Cache_Controller.OLSXW.L2_Replacement 25 0.00% 0.00% +system.ruby.L2Cache_Controller.ILXW.L1_GETS 6054 0.00% 0.00% +system.ruby.L2Cache_Controller.ILXW.L1_GETX 3511 0.00% 0.00% +system.ruby.L2Cache_Controller.ILXW.L1_PUTX 1623 0.00% 0.00% +system.ruby.L2Cache_Controller.ILXW.L1_PUTS 74 0.00% 0.00% +system.ruby.L2Cache_Controller.ILXW.L1_WBDIRTYDATA 219955 0.00% 0.00% +system.ruby.L2Cache_Controller.ILXW.Unblock 1081 0.00% 0.00% +system.ruby.L2Cache_Controller.IFLS.L1_GETS 208 0.00% 0.00% +system.ruby.L2Cache_Controller.IFLS.L1_GETX 115 0.00% 0.00% +system.ruby.L2Cache_Controller.IFLS.L1_PUTS_only 28820 0.00% 0.00% +system.ruby.L2Cache_Controller.IFLS.L1_PUTS 125 0.00% 0.00% +system.ruby.L2Cache_Controller.IFLS.Unblock 3162 0.00% 0.00% +system.ruby.L2Cache_Controller.IFLOX.L1_PUTX 10 0.00% 0.00% +system.ruby.L2Cache_Controller.IFLOX.L1_PUTS_only 58 0.00% 0.00% system.ruby.L2Cache_Controller.IFLOX.Unblock 1 0.00% 0.00% -system.ruby.L2Cache_Controller.IFLOX.Exclusive_Unblock 2 0.00% 0.00% -system.ruby.L2Cache_Controller.IFLOXX.L1_GETS 214 0.00% 0.00% -system.ruby.L2Cache_Controller.IFLOXX.L1_GETX 37 0.00% 0.00% -system.ruby.L2Cache_Controller.IFLOXX.L1_PUTX 31465 0.00% 0.00% -system.ruby.L2Cache_Controller.IFLOXX.L1_PUTS 104 0.00% 0.00% -system.ruby.L2Cache_Controller.IFLOXX.Unblock 1911 0.00% 0.00% -system.ruby.L2Cache_Controller.IFLOXX.Exclusive_Unblock 1445 0.00% 0.00% -system.ruby.L2Cache_Controller.IFLOSX.L1_PUTX 109 0.00% 0.00% -system.ruby.L2Cache_Controller.IFLOSX.L1_PUTS_only 80 0.00% 0.00% -system.ruby.L2Cache_Controller.IFLOSX.L1_PUTS 5 0.00% 0.00% -system.ruby.L2Cache_Controller.IFLOSX.Unblock 8 0.00% 0.00% -system.ruby.L2Cache_Controller.IFLXO.L1_PUTX 2 0.00% 0.00% -system.ruby.L2Cache_Controller.IFLXO.Exclusive_Unblock 1 0.00% 0.00% -system.ruby.L2Cache_Controller.IGS.L1_GETS 48255 0.00% 0.00% -system.ruby.L2Cache_Controller.IGS.L1_GETX 26567 0.00% 0.00% -system.ruby.L2Cache_Controller.IGS.L1_PUTS 7485 0.00% 0.00% -system.ruby.L2Cache_Controller.IGS.Data 394425 0.00% 0.00% -system.ruby.L2Cache_Controller.IGS.Unblock 394419 0.00% 0.00% -system.ruby.L2Cache_Controller.IGM.L1_GETS 20782 0.00% 0.00% -system.ruby.L2Cache_Controller.IGM.L1_GETX 12166 0.00% 0.00% -system.ruby.L2Cache_Controller.IGM.Data 220644 0.00% 0.00% -system.ruby.L2Cache_Controller.IGMLS.L1_GETS 103 0.00% 0.00% -system.ruby.L2Cache_Controller.IGMLS.L1_GETX 166 0.00% 0.00% -system.ruby.L2Cache_Controller.IGMLS.L1_PUTS_only 29804 0.00% 0.00% -system.ruby.L2Cache_Controller.IGMLS.L1_PUTS 248 0.00% 0.00% -system.ruby.L2Cache_Controller.IGMLS.Data 1834 0.00% 0.00% -system.ruby.L2Cache_Controller.IGMO.L1_GETS 5289 0.00% 0.00% -system.ruby.L2Cache_Controller.IGMO.L1_GETX 2899 0.00% 0.00% -system.ruby.L2Cache_Controller.IGMO.L1_PUTX 94 0.00% 0.00% -system.ruby.L2Cache_Controller.IGMO.L1_PUTS_only 16694 0.00% 0.00% -system.ruby.L2Cache_Controller.IGMO.L1_PUTS 119 0.00% 0.00% -system.ruby.L2Cache_Controller.IGMO.All_Acks 222478 0.00% 0.00% -system.ruby.L2Cache_Controller.IGMO.Exclusive_Unblock 222477 0.00% 0.00% +system.ruby.L2Cache_Controller.IFLOX.Exclusive_Unblock 6 0.00% 0.00% +system.ruby.L2Cache_Controller.IFLOXX.L1_GETS 110 0.00% 0.00% +system.ruby.L2Cache_Controller.IFLOXX.L1_GETX 197 0.00% 0.00% +system.ruby.L2Cache_Controller.IFLOXX.L1_PUTX 32397 0.00% 0.00% +system.ruby.L2Cache_Controller.IFLOXX.L1_PUTS 242 0.00% 0.00% +system.ruby.L2Cache_Controller.IFLOXX.Unblock 1987 0.00% 0.00% +system.ruby.L2Cache_Controller.IFLOXX.Exclusive_Unblock 1456 0.00% 0.00% +system.ruby.L2Cache_Controller.IFLOSX.L1_PUTX 63 0.00% 0.00% +system.ruby.L2Cache_Controller.IFLOSX.L1_PUTS_only 56 0.00% 0.00% +system.ruby.L2Cache_Controller.IFLOSX.Unblock 5 0.00% 0.00% +system.ruby.L2Cache_Controller.IFLXO.L1_PUTX 34 0.00% 0.00% +system.ruby.L2Cache_Controller.IFLXO.Exclusive_Unblock 4 0.00% 0.00% +system.ruby.L2Cache_Controller.IGS.L1_GETS 46072 0.00% 0.00% +system.ruby.L2Cache_Controller.IGS.L1_GETX 26880 0.00% 0.00% +system.ruby.L2Cache_Controller.IGS.L1_PUTS 7566 0.00% 0.00% +system.ruby.L2Cache_Controller.IGS.Data 392610 0.00% 0.00% +system.ruby.L2Cache_Controller.IGS.Unblock 392604 0.00% 0.00% +system.ruby.L2Cache_Controller.IGM.L1_GETS 21372 0.00% 0.00% +system.ruby.L2Cache_Controller.IGM.L1_GETX 11875 0.00% 0.00% +system.ruby.L2Cache_Controller.IGM.Data 218092 0.00% 0.00% +system.ruby.L2Cache_Controller.IGMLS.L1_GETS 349 0.00% 0.00% +system.ruby.L2Cache_Controller.IGMLS.L1_GETX 222 0.00% 0.00% +system.ruby.L2Cache_Controller.IGMLS.L1_PUTS_only 30376 0.00% 0.00% +system.ruby.L2Cache_Controller.IGMLS.L1_PUTS 232 0.00% 0.00% +system.ruby.L2Cache_Controller.IGMLS.Data 1842 0.00% 0.00% +system.ruby.L2Cache_Controller.IGMO.L1_GETS 5603 0.00% 0.00% +system.ruby.L2Cache_Controller.IGMO.L1_GETX 3146 0.00% 0.00% +system.ruby.L2Cache_Controller.IGMO.L1_PUTX 121 0.00% 0.00% +system.ruby.L2Cache_Controller.IGMO.L1_PUTS_only 16651 0.00% 0.00% +system.ruby.L2Cache_Controller.IGMO.L1_PUTS 147 0.00% 0.00% +system.ruby.L2Cache_Controller.IGMO.All_Acks 219934 0.00% 0.00% +system.ruby.L2Cache_Controller.IGMO.Exclusive_Unblock 219930 0.00% 0.00% system.ruby.L2Cache_Controller.MM.L1_GETS 4 0.00% 0.00% -system.ruby.L2Cache_Controller.MM.L1_GETX 31 0.00% 0.00% -system.ruby.L2Cache_Controller.MM.L1_PUTX 1 0.00% 0.00% -system.ruby.L2Cache_Controller.MM.Exclusive_Unblock 739 0.00% 0.00% -system.ruby.L2Cache_Controller.SS.L1_GETS 40 0.00% 0.00% -system.ruby.L2Cache_Controller.SS.L1_GETX 20 0.00% 0.00% -system.ruby.L2Cache_Controller.SS.L1_PUTS 14 0.00% 0.00% -system.ruby.L2Cache_Controller.SS.Unblock 2517 0.00% 0.00% -system.ruby.L2Cache_Controller.SS.L2_Replacement 29818 0.00% 0.00% -system.ruby.L2Cache_Controller.OO.L1_GETS 14 0.00% 0.00% -system.ruby.L2Cache_Controller.OO.L1_GETX 19 0.00% 0.00% -system.ruby.L2Cache_Controller.OO.L1_PUTX 7 0.00% 0.00% -system.ruby.L2Cache_Controller.OO.Exclusive_Unblock 1287 0.00% 0.00% -system.ruby.L2Cache_Controller.OO.L2_Replacement 12281 0.00% 0.00% -system.ruby.L2Cache_Controller.OLSXS.L1_PUTS_only 46 0.00% 0.00% -system.ruby.L2Cache_Controller.OLSXS.Unblock 10 0.00% 0.00% -system.ruby.L2Cache_Controller.OLSXS.L2_Replacement 9 0.00% 0.00% -system.ruby.L2Cache_Controller.SLSS.L1_PUTS_only 36 0.00% 0.00% +system.ruby.L2Cache_Controller.MM.L1_GETX 4 0.00% 0.00% +system.ruby.L2Cache_Controller.MM.Exclusive_Unblock 701 0.00% 0.00% +system.ruby.L2Cache_Controller.SS.L1_GETS 52 0.00% 0.00% +system.ruby.L2Cache_Controller.SS.L1_GETX 25 0.00% 0.00% +system.ruby.L2Cache_Controller.SS.L1_PUTS 27 0.00% 0.00% +system.ruby.L2Cache_Controller.SS.Unblock 2531 0.00% 0.00% +system.ruby.L2Cache_Controller.SS.L2_Replacement 30081 0.00% 0.00% +system.ruby.L2Cache_Controller.OO.L1_GETS 46 0.00% 0.00% +system.ruby.L2Cache_Controller.OO.Exclusive_Unblock 1300 0.00% 0.00% +system.ruby.L2Cache_Controller.OO.L2_Replacement 11341 0.00% 0.00% +system.ruby.L2Cache_Controller.OLSXS.L1_PUTS_only 14 0.00% 0.00% +system.ruby.L2Cache_Controller.OLSXS.Unblock 4 0.00% 0.00% +system.ruby.L2Cache_Controller.SLSS.L1_PUTS_only 74 0.00% 0.00% system.ruby.L2Cache_Controller.SLSS.Unblock 18 0.00% 0.00% -system.ruby.L2Cache_Controller.SLSS.L2_Replacement 7 0.00% 0.00% -system.ruby.L2Cache_Controller.MI.L1_GETS 798 0.00% 0.00% -system.ruby.L2Cache_Controller.MI.L1_GETX 364 0.00% 0.00% -system.ruby.L2Cache_Controller.MI.Writeback_Ack 222371 0.00% 0.00% -system.ruby.L2Cache_Controller.OLSI.L1_PUTS_only 315 0.00% 0.00% -system.ruby.L2Cache_Controller.OLSI.L1_PUTS 15 0.00% 0.00% -system.ruby.L2Cache_Controller.OLSI.Writeback_Ack 91 0.00% 0.00% -system.ruby.Directory_Controller.GETX 222490 0.00% 0.00% -system.ruby.Directory_Controller.GETS 394442 0.00% 0.00% -system.ruby.Directory_Controller.PUTX 222382 0.00% 0.00% -system.ruby.Directory_Controller.PUTO_SHARERS 91 0.00% 0.00% -system.ruby.Directory_Controller.Unblock 143648 0.00% 0.00% -system.ruby.Directory_Controller.Last_Unblock 250771 0.00% 0.00% -system.ruby.Directory_Controller.Exclusive_Unblock 222477 0.00% 0.00% -system.ruby.Directory_Controller.Dirty_Writeback 222462 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Data 616908 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Ack 222462 0.00% 0.00% -system.ruby.Directory_Controller.I.GETX 80054 0.00% 0.00% -system.ruby.Directory_Controller.I.GETS 143652 0.00% 0.00% -system.ruby.Directory_Controller.I.Memory_Ack 222199 0.00% 0.00% -system.ruby.Directory_Controller.S.GETX 142431 0.00% 0.00% -system.ruby.Directory_Controller.S.GETS 250790 0.00% 0.00% -system.ruby.Directory_Controller.S.Memory_Ack 91 0.00% 0.00% -system.ruby.Directory_Controller.M.PUTX 222382 0.00% 0.00% -system.ruby.Directory_Controller.M.PUTO_SHARERS 91 0.00% 0.00% -system.ruby.Directory_Controller.IS.GETX 3 0.00% 0.00% -system.ruby.Directory_Controller.IS.Unblock 143648 0.00% 0.00% -system.ruby.Directory_Controller.IS.Memory_Data 143651 0.00% 0.00% -system.ruby.Directory_Controller.IS.Memory_Ack 105 0.00% 0.00% -system.ruby.Directory_Controller.SS.GETX 2 0.00% 0.00% -system.ruby.Directory_Controller.SS.Last_Unblock 250771 0.00% 0.00% -system.ruby.Directory_Controller.SS.Memory_Data 250778 0.00% 0.00% -system.ruby.Directory_Controller.MM.Exclusive_Unblock 222477 0.00% 0.00% -system.ruby.Directory_Controller.MM.Memory_Data 222479 0.00% 0.00% -system.ruby.Directory_Controller.MM.Memory_Ack 67 0.00% 0.00% -system.ruby.Directory_Controller.MI.Dirty_Writeback 222371 0.00% 0.00% -system.ruby.Directory_Controller.MIS.Dirty_Writeback 91 0.00% 0.00% +system.ruby.L2Cache_Controller.SLSS.L2_Replacement 57 0.00% 0.00% +system.ruby.L2Cache_Controller.MI.L1_GETS 845 0.00% 0.00% +system.ruby.L2Cache_Controller.MI.L1_GETX 345 0.00% 0.00% +system.ruby.L2Cache_Controller.MI.Writeback_Ack 219820 0.00% 0.00% +system.ruby.L2Cache_Controller.OLSI.L1_PUTS_only 268 0.00% 0.00% +system.ruby.L2Cache_Controller.OLSI.Writeback_Ack 100 0.00% 0.00% ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt index 02ba8cb28..cdc9c6487 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt @@ -1,48 +1,48 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.005903 # Number of seconds simulated -sim_ticks 5903349 # Number of ticks simulated -final_tick 5903349 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.005881 # Number of seconds simulated +sim_ticks 5881067 # Number of ticks simulated +final_tick 5881067 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 47205 # Simulator tick rate (ticks/s) -host_mem_usage 653496 # Number of bytes of host memory used -host_seconds 125.06 # Real time elapsed on the host +host_tick_rate 67797 # Simulator tick rate (ticks/s) +host_mem_usage 666544 # Number of bytes of host memory used +host_seconds 86.75 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks -system.mem_ctrls.bytes_read::ruby.dir_cntrl0 39803968 # Number of bytes read from this memory -system.mem_ctrls.bytes_read::total 39803968 # Number of bytes read from this memory -system.mem_ctrls.bytes_written::ruby.dir_cntrl0 15577920 # Number of bytes written to this memory -system.mem_ctrls.bytes_written::total 15577920 # Number of bytes written to this memory -system.mem_ctrls.num_reads::ruby.dir_cntrl0 621937 # Number of read requests responded to by this memory -system.mem_ctrls.num_reads::total 621937 # Number of read requests responded to by this memory -system.mem_ctrls.num_writes::ruby.dir_cntrl0 243405 # Number of write requests responded to by this memory -system.mem_ctrls.num_writes::total 243405 # Number of write requests responded to by this memory -system.mem_ctrls.bw_read::ruby.dir_cntrl0 6742607967 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_read::total 6742607967 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::ruby.dir_cntrl0 2638827554 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::total 2638827554 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_total::ruby.dir_cntrl0 9381435521 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.bw_total::total 9381435521 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.readReqs 621943 # Number of read requests accepted -system.mem_ctrls.writeReqs 243405 # Number of write requests accepted -system.mem_ctrls.readBursts 621943 # Number of DRAM read bursts, including those serviced by the write queue -system.mem_ctrls.writeBursts 243405 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrls.bytesReadDRAM 39194112 # Total number of bytes read from DRAM -system.mem_ctrls.bytesReadWrQ 610176 # Total number of bytes read from write queue -system.mem_ctrls.bytesWritten 15379392 # Total number of bytes written to DRAM -system.mem_ctrls.bytesReadSys 39804352 # Total read bytes from the system interface side -system.mem_ctrls.bytesWrittenSys 15577920 # Total written bytes from the system interface side -system.mem_ctrls.servicedByWrQ 9534 # Number of DRAM read bursts serviced by the write queue -system.mem_ctrls.mergedWrBursts 3050 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.bytes_read::ruby.dir_cntrl0 39867264 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 39867264 # Number of bytes read from this memory +system.mem_ctrls.bytes_written::ruby.dir_cntrl0 15562240 # Number of bytes written to this memory +system.mem_ctrls.bytes_written::total 15562240 # Number of bytes written to this memory +system.mem_ctrls.num_reads::ruby.dir_cntrl0 622926 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 622926 # Number of read requests responded to by this memory +system.mem_ctrls.num_writes::ruby.dir_cntrl0 243160 # Number of write requests responded to by this memory +system.mem_ctrls.num_writes::total 243160 # Number of write requests responded to by this memory +system.mem_ctrls.bw_read::ruby.dir_cntrl0 6778916819 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 6778916819 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::ruby.dir_cntrl0 2646159277 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::total 2646159277 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::ruby.dir_cntrl0 9425076096 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 9425076096 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.readReqs 622939 # Number of read requests accepted +system.mem_ctrls.writeReqs 243160 # Number of write requests accepted +system.mem_ctrls.readBursts 622939 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.writeBursts 243160 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrls.bytesReadDRAM 39257856 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 609920 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 15368000 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadSys 39868096 # Total read bytes from the system interface side +system.mem_ctrls.bytesWrittenSys 15562240 # Total written bytes from the system interface side +system.mem_ctrls.servicedByWrQ 9530 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 2992 # Number of DRAM write bursts merged with an existing one system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.mem_ctrls.perBankRdBursts::0 76347 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::1 76777 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::2 76688 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::3 76481 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::4 76573 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::5 76421 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::6 76863 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::7 76258 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::0 76660 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::1 76752 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::2 77051 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 76487 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 76654 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::5 76224 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::6 76502 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 77074 # Per bank write bursts system.mem_ctrls.perBankRdBursts::8 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::9 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::10 0 # Per bank write bursts @@ -51,14 +51,14 @@ system.mem_ctrls.perBankRdBursts::12 0 # Pe system.mem_ctrls.perBankRdBursts::13 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::14 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::15 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::0 29810 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::1 29890 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::2 29935 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::3 30014 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::4 30230 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::5 29983 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::6 30326 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::7 30115 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 30175 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::1 29930 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::2 29913 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 29922 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 30021 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 29908 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::6 29847 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::7 30409 # Per bank write bursts system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::10 0 # Per bank write bursts @@ -68,54 +68,54 @@ system.mem_ctrls.perBankWrBursts::13 0 # Pe system.mem_ctrls.perBankWrBursts::14 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry -system.mem_ctrls.numWrRetry 1 # Number of times write queue was full causing retry -system.mem_ctrls.totGap 5903324 # Total gap between requests +system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry +system.mem_ctrls.totGap 5881040 # Total gap between requests system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::6 621943 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 622939 # Read request sizes (log2) system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::6 243405 # Write request sizes (log2) -system.mem_ctrls.rdQLenPdf::0 8798 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::1 12225 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::2 15673 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::3 18982 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::4 23894 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::5 29950 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::6 36090 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::7 39516 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::8 38914 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::9 35099 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::10 30974 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::11 28275 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::12 27328 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::13 26531 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::14 25465 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::15 24154 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::16 22659 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::17 21094 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::18 19924 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::19 19151 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::20 18313 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::21 17650 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::22 16767 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::23 15495 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::24 13609 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::25 10848 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::26 7634 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::27 4446 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::28 2074 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::29 710 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::30 152 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::31 15 # What read queue length does an incoming req see +system.mem_ctrls.writePktSize::6 243160 # Write request sizes (log2) +system.mem_ctrls.rdQLenPdf::0 9491 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::1 13045 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::2 16471 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::3 19836 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::4 24397 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::5 30683 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::6 37010 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::7 40313 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::8 38781 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::9 34536 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::10 30013 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::11 27811 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::12 26580 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::13 25824 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::14 24841 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::15 23671 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::16 22442 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::17 21076 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::18 19903 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::19 19289 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::20 18444 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::21 17751 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::22 16931 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::23 15536 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::24 13465 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::25 10656 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::26 7404 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::27 4341 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::28 2023 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::29 670 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::30 154 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::31 21 # What read queue length does an incoming req see system.mem_ctrls.wrQLenPdf::0 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::1 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::2 1 # What write queue length does an incoming req see @@ -131,992 +131,1025 @@ system.mem_ctrls.wrQLenPdf::11 1 # Wh system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::15 54 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::16 129 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::17 509 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::18 1379 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::19 2637 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::20 4325 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::21 6267 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::22 8313 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::23 10420 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::24 12108 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::25 14158 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::26 15771 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::27 14672 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::28 15436 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::29 15890 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::30 16068 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::31 16476 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::32 16926 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::33 9332 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::34 7861 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::35 6772 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::36 5940 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::37 5146 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::38 4440 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::39 3847 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::40 3410 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::41 2960 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::42 2737 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::43 2369 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::44 2177 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::45 1926 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::46 1729 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::47 1554 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::48 1310 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::49 1089 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::50 996 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::51 831 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::52 739 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::53 600 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::54 548 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::55 304 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::56 115 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::57 37 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::58 16 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::59 6 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::60 5 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::61 3 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::62 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::63 2 # What write queue length does an incoming req see -system.mem_ctrls.bytesPerActivate::samples 248467 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::mean 219.637505 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::gmean 176.904831 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::stdev 149.844178 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::0-127 48636 19.57% 19.57% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::128-255 105540 42.48% 62.05% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::256-383 54258 21.84% 83.89% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::384-511 23672 9.53% 93.42% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::512-639 10163 4.09% 97.51% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::640-767 3955 1.59% 99.10% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::768-895 1444 0.58% 99.68% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::896-1023 531 0.21% 99.89% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::1024-1151 268 0.11% 100.00% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::total 248467 # Bytes accessed per row activation -system.mem_ctrls.rdPerTurnAround::samples 14728 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::mean 41.574756 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::gmean 37.550094 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::stdev 18.264182 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::0-7 348 2.36% 2.36% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::8-15 39 0.26% 2.63% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::16-23 43 0.29% 2.92% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::24-31 3310 22.47% 25.39% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::32-39 6215 42.20% 67.59% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::40-47 1541 10.46% 78.06% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::48-55 179 1.22% 79.27% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::56-63 857 5.82% 85.09% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::64-71 1087 7.38% 92.47% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::72-79 557 3.78% 96.25% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::80-87 134 0.91% 97.16% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::88-95 122 0.83% 97.99% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::96-103 118 0.80% 98.79% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::104-111 93 0.63% 99.42% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::112-119 42 0.29% 99.71% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::120-127 26 0.18% 99.88% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::128-135 7 0.05% 99.93% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::136-143 8 0.05% 99.99% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::144-151 2 0.01% 100.00% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::total 14728 # Reads before turning the bus around for writes -system.mem_ctrls.wrPerTurnAround::samples 14728 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::mean 16.316065 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::gmean 16.277150 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::stdev 1.251161 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::16 13454 91.35% 91.35% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::17 270 1.83% 93.18% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::18 233 1.58% 94.77% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::19 212 1.44% 96.20% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::20 167 1.13% 97.34% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::21 127 0.86% 98.20% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::22 100 0.68% 98.88% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::23 65 0.44% 99.32% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::24 45 0.31% 99.63% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::25 22 0.15% 99.78% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::26 11 0.07% 99.85% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::27 12 0.08% 99.93% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::28 7 0.05% 99.98% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::29 1 0.01% 99.99% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::30 2 0.01% 100.00% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::total 14728 # Writes before turning the bus around for reads -system.mem_ctrls.totQLat 63789979 # Total ticks spent queuing -system.mem_ctrls.totMemAccLat 75425731 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrls.totBusLat 3062040 # Total ticks spent in databus transfers -system.mem_ctrls.avgQLat 104.16 # Average queueing delay per DRAM burst +system.mem_ctrls.wrQLenPdf::15 69 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::16 156 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::17 556 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::18 1531 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::19 2889 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::20 4720 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::21 6835 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::22 9004 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::23 11039 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::24 13141 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::25 14827 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::26 16745 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::27 15642 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::28 15986 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::29 16671 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::30 16977 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::31 17135 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::32 17397 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::33 9213 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::34 7556 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::35 6269 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::36 5389 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::37 4612 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::38 3842 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::39 3246 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::40 2810 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::41 2318 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::42 2106 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::43 1851 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::44 1567 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::45 1379 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::46 1186 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::47 1027 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::48 894 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::49 732 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::50 636 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::51 584 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::52 504 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::53 429 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::54 350 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::55 182 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::56 79 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::57 34 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::58 22 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::59 10 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::60 4 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::61 2 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.mem_ctrls.bytesPerActivate::samples 251857 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 216.889807 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 174.913465 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 147.987384 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 50106 19.89% 19.89% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 108175 42.95% 62.85% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 54326 21.57% 84.42% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 23433 9.30% 93.72% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 9848 3.91% 97.63% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 3794 1.51% 99.14% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 1414 0.56% 99.70% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 496 0.20% 99.89% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 265 0.11% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 251857 # Bytes accessed per row activation +system.mem_ctrls.rdPerTurnAround::samples 14692 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::mean 41.747345 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::gmean 38.046520 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::stdev 17.572329 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::0-7 293 1.99% 1.99% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::8-15 32 0.22% 2.21% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::16-23 40 0.27% 2.48% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::24-31 3171 21.58% 24.07% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::32-39 6167 41.98% 66.04% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::40-47 1682 11.45% 77.49% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::48-55 182 1.24% 78.73% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::56-63 909 6.19% 84.92% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::64-71 1233 8.39% 93.31% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::72-79 536 3.65% 96.96% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::80-87 119 0.81% 97.77% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::88-95 74 0.50% 98.27% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::96-103 108 0.74% 99.01% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::104-111 74 0.50% 99.51% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::112-119 42 0.29% 99.80% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::120-127 16 0.11% 99.90% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::128-135 8 0.05% 99.96% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::136-143 4 0.03% 99.99% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::144-151 1 0.01% 99.99% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::152-159 1 0.01% 100.00% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::total 14692 # Reads before turning the bus around for writes +system.mem_ctrls.wrPerTurnAround::samples 14692 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::mean 16.343929 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::gmean 16.300692 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::stdev 1.322873 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::16 13317 90.64% 90.64% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::17 342 2.33% 92.97% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::18 211 1.44% 94.41% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::19 210 1.43% 95.83% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::20 177 1.20% 97.04% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::21 136 0.93% 97.96% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::22 103 0.70% 98.67% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::23 66 0.45% 99.12% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::24 56 0.38% 99.50% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::25 38 0.26% 99.75% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::26 17 0.12% 99.87% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::27 7 0.05% 99.92% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::28 6 0.04% 99.96% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::29 3 0.02% 99.98% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::30 2 0.01% 99.99% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::31 1 0.01% 100.00% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::total 14692 # Writes before turning the bus around for reads +system.mem_ctrls.totQLat 62376294 # Total ticks spent queuing +system.mem_ctrls.totMemAccLat 74030970 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.totBusLat 3067020 # Total ticks spent in databus transfers +system.mem_ctrls.avgQLat 101.69 # Average queueing delay per DRAM burst system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst -system.mem_ctrls.avgMemAccLat 123.16 # Average memory access latency per DRAM burst -system.mem_ctrls.avgRdBW 6639.30 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrls.avgWrBW 2605.20 # Average achieved write bandwidth in MiByte/s -system.mem_ctrls.avgRdBWSys 6742.67 # Average system read bandwidth in MiByte/s -system.mem_ctrls.avgWrBWSys 2638.83 # Average system write bandwidth in MiByte/s +system.mem_ctrls.avgMemAccLat 120.69 # Average memory access latency per DRAM burst +system.mem_ctrls.avgRdBW 6675.29 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 2613.13 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 6779.06 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 2646.16 # Average system write bandwidth in MiByte/s system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrls.busUtil 72.22 # Data bus utilization in percentage -system.mem_ctrls.busUtilRead 51.87 # Data bus utilization in percentage for reads -system.mem_ctrls.busUtilWrite 20.35 # Data bus utilization in percentage for writes -system.mem_ctrls.avgRdQLen 15.52 # Average read queue length when enqueuing -system.mem_ctrls.avgWrQLen 30.69 # Average write queue length when enqueuing -system.mem_ctrls.readRowHits 368879 # Number of row buffer hits during reads -system.mem_ctrls.writeRowHits 235357 # Number of row buffer hits during writes -system.mem_ctrls.readRowHitRate 60.23 # Row buffer hit rate for reads -system.mem_ctrls.writeRowHitRate 97.92 # Row buffer hit rate for writes -system.mem_ctrls.avgGap 6.82 # Average gap between requests -system.mem_ctrls.pageHitRate 70.86 # Row buffer hit rate, read and write combined -system.mem_ctrls.memoryStateTime::IDLE 22 # Time in different power states -system.mem_ctrls.memoryStateTime::REF 197080 # Time in different power states -system.mem_ctrls.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls.memoryStateTime::ACT 5704995 # Time in different power states -system.mem_ctrls.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrls.actEnergy::0 1877972040 # Energy for activate commands per rank (pJ) -system.mem_ctrls.actEnergy::1 0 # Energy for activate commands per rank (pJ) -system.mem_ctrls.preEnergy::0 1043317800 # Energy for precharge commands per rank (pJ) -system.mem_ctrls.preEnergy::1 0 # Energy for precharge commands per rank (pJ) -system.mem_ctrls.readEnergy::0 7640929920 # Energy for read commands per rank (pJ) -system.mem_ctrls.readEnergy::1 0 # Energy for read commands per rank (pJ) -system.mem_ctrls.writeEnergy::0 2491129728 # Energy for write commands per rank (pJ) -system.mem_ctrls.writeEnergy::1 0 # Energy for write commands per rank (pJ) -system.mem_ctrls.refreshEnergy::0 385488480 # Energy for refresh commands per rank (pJ) -system.mem_ctrls.refreshEnergy::1 385488480 # Energy for refresh commands per rank (pJ) -system.mem_ctrls.actBackEnergy::0 4021690860 # Energy for active background per rank (pJ) -system.mem_ctrls.actBackEnergy::1 127544112 # Energy for active background per rank (pJ) -system.mem_ctrls.preBackEnergy::0 13450800 # Energy for precharge background per rank (pJ) -system.mem_ctrls.preBackEnergy::1 3429369000 # Energy for precharge background per rank (pJ) -system.mem_ctrls.totalEnergy::0 17473979628 # Total energy per rank (pJ) -system.mem_ctrls.totalEnergy::1 3942401592 # Total energy per rank (pJ) -system.mem_ctrls.averagePower::0 2960.646204 # Core power per rank (mW) -system.mem_ctrls.averagePower::1 667.967833 # Core power per rank (mW) +system.mem_ctrls.busUtil 72.57 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 52.15 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 20.42 # Data bus utilization in percentage for writes +system.mem_ctrls.avgRdQLen 15.37 # Average read queue length when enqueuing +system.mem_ctrls.avgWrQLen 29.97 # Average write queue length when enqueuing +system.mem_ctrls.readRowHits 367104 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 234563 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 59.85 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate 97.67 # Row buffer hit rate for writes +system.mem_ctrls.avgGap 6.79 # Average gap between requests +system.mem_ctrls.pageHitRate 70.49 # Row buffer hit rate, read and write combined +system.mem_ctrls_0.actEnergy 1903252680 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 1057362600 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 7652062080 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 2488610304 # Energy for write commands per rank (pJ) +system.mem_ctrls_0.refreshEnergy 383962800 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_0.actBackEnergy 4006574460 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 12703200 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.totalEnergy 17504528124 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 2977.600142 # Core power per rank (mW) +system.mem_ctrls_0.memoryStateTime::IDLE 22 # Time in different power states +system.mem_ctrls_0.memoryStateTime::REF 196300 # Time in different power states +system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 5682429 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls_1.actEnergy 0 # Energy for activate commands per rank (pJ) +system.mem_ctrls_1.preEnergy 0 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_1.readEnergy 0 # Energy for read commands per rank (pJ) +system.mem_ctrls_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls_1.refreshEnergy 383962800 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_1.actBackEnergy 127039320 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 3415767600 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.totalEnergy 3926769720 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 667.968386 # Core power per rank (mW) +system.mem_ctrls_1.memoryStateTime::IDLE 5682390 # Time in different power states +system.mem_ctrls_1.memoryStateTime::REF 196300 # Time in different power states +system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 0 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu_clk_domain.clock 1 # Clock period in ticks +system.cpu0.num_reads 99830 # number of read accesses completed +system.cpu0.num_writes 55806 # number of write accesses completed +system.cpu0.num_copies 0 # number of copy accesses completed +system.cpu1.num_reads 99618 # number of read accesses completed +system.cpu1.num_writes 55383 # number of write accesses completed +system.cpu1.num_copies 0 # number of copy accesses completed +system.cpu2.num_reads 99329 # number of read accesses completed +system.cpu2.num_writes 55521 # number of write accesses completed +system.cpu2.num_copies 0 # number of copy accesses completed +system.cpu3.num_reads 99531 # number of read accesses completed +system.cpu3.num_writes 55301 # number of write accesses completed +system.cpu3.num_copies 0 # number of copy accesses completed +system.cpu4.num_reads 99485 # number of read accesses completed +system.cpu4.num_writes 55398 # number of write accesses completed +system.cpu4.num_copies 0 # number of copy accesses completed +system.cpu5.num_reads 99702 # number of read accesses completed +system.cpu5.num_writes 55198 # number of write accesses completed +system.cpu5.num_copies 0 # number of copy accesses completed +system.cpu6.num_reads 99965 # number of read accesses completed +system.cpu6.num_writes 55754 # number of write accesses completed +system.cpu6.num_copies 0 # number of copy accesses completed +system.cpu7.num_reads 100000 # number of read accesses completed +system.cpu7.num_writes 54827 # number of write accesses completed +system.cpu7.num_copies 0 # number of copy accesses completed system.ruby.clk_domain.clock 1 # Clock period in ticks system.ruby.outstanding_req_hist::bucket_size 2 system.ruby.outstanding_req_hist::max_bucket 19 -system.ruby.outstanding_req_hist::samples 626379 -system.ruby.outstanding_req_hist::mean 15.998463 -system.ruby.outstanding_req_hist::gmean 15.997198 -system.ruby.outstanding_req_hist::stdev 0.125855 -system.ruby.outstanding_req_hist | 8 0.00% 0.00% | 16 0.00% 0.00% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.02% | 19 0.00% 0.02% | 626256 99.98% 100.00% | 0 0.00% 100.00% -system.ruby.outstanding_req_hist::total 626379 +system.ruby.outstanding_req_hist::samples 627379 +system.ruby.outstanding_req_hist::mean 15.998465 +system.ruby.outstanding_req_hist::gmean 15.997202 +system.ruby.outstanding_req_hist::stdev 0.125755 +system.ruby.outstanding_req_hist | 8 0.00% 0.00% | 16 0.00% 0.00% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.02% | 19 0.00% 0.02% | 627256 99.98% 100.00% | 0 0.00% 100.00% +system.ruby.outstanding_req_hist::total 627379 system.ruby.latency_hist::bucket_size 512 system.ruby.latency_hist::max_bucket 5119 -system.ruby.latency_hist::samples 626251 -system.ruby.latency_hist::mean 1206.428296 -system.ruby.latency_hist::gmean 904.745732 -system.ruby.latency_hist::stdev 768.364731 -system.ruby.latency_hist | 168539 26.91% 26.91% | 118080 18.86% 45.77% | 109951 17.56% 63.32% | 120505 19.24% 82.57% | 86642 13.84% 96.40% | 20968 3.35% 99.75% | 1529 0.24% 99.99% | 37 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.latency_hist::total 626251 +system.ruby.latency_hist::samples 627251 +system.ruby.latency_hist::mean 1199.957633 +system.ruby.latency_hist::gmean 899.316988 +system.ruby.latency_hist::stdev 764.936546 +system.ruby.latency_hist | 169441 27.01% 27.01% | 117906 18.80% 45.81% | 113026 18.02% 63.83% | 119501 19.05% 82.88% | 85523 13.63% 96.52% | 20392 3.25% 99.77% | 1432 0.23% 100.00% | 30 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.latency_hist::total 627251 system.ruby.hit_latency_hist::bucket_size 512 system.ruby.hit_latency_hist::max_bucket 5119 -system.ruby.hit_latency_hist::samples 2807 -system.ruby.hit_latency_hist::mean 1092.408621 -system.ruby.hit_latency_hist::gmean 552.825422 -system.ruby.hit_latency_hist::stdev 803.774497 -system.ruby.hit_latency_hist | 930 33.13% 33.13% | 469 16.71% 49.84% | 481 17.14% 66.98% | 503 17.92% 84.89% | 338 12.04% 96.94% | 81 2.89% 99.82% | 4 0.14% 99.96% | 1 0.04% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.hit_latency_hist::total 2807 +system.ruby.hit_latency_hist::samples 2844 +system.ruby.hit_latency_hist::mean 1057.367440 +system.ruby.hit_latency_hist::gmean 516.362786 +system.ruby.hit_latency_hist::stdev 803.056004 +system.ruby.hit_latency_hist | 983 34.56% 34.56% | 524 18.42% 52.99% | 459 16.14% 69.13% | 465 16.35% 85.48% | 334 11.74% 97.22% | 70 2.46% 99.68% | 8 0.28% 99.96% | 1 0.04% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.hit_latency_hist::total 2844 system.ruby.miss_latency_hist::bucket_size 512 system.ruby.miss_latency_hist::max_bucket 5119 -system.ruby.miss_latency_hist::samples 623444 -system.ruby.miss_latency_hist::mean 1206.941660 -system.ruby.miss_latency_hist::gmean 906.754630 -system.ruby.miss_latency_hist::stdev 768.164015 -system.ruby.miss_latency_hist | 167609 26.88% 26.88% | 117611 18.86% 45.75% | 109470 17.56% 63.31% | 120002 19.25% 82.56% | 86304 13.84% 96.40% | 20887 3.35% 99.75% | 1525 0.24% 99.99% | 36 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.miss_latency_hist::total 623444 -system.ruby.L1Cache.incomplete_times 1328 -system.ruby.Directory.incomplete_times 622112 -system.ruby.l1_cntrl4.L1Dcache.demand_hits 17 # Number of cache demand hits -system.ruby.l1_cntrl4.L1Dcache.demand_misses 77927 # Number of cache demand misses -system.ruby.l1_cntrl4.L1Dcache.demand_accesses 77944 # Number of cache demand accesses -system.ruby.l1_cntrl4.L1Icache.demand_hits 0 # Number of cache demand hits -system.ruby.l1_cntrl4.L1Icache.demand_misses 0 # Number of cache demand misses -system.ruby.l1_cntrl4.L1Icache.demand_accesses 0 # Number of cache demand accesses -system.cpu_clk_domain.clock 1 # Clock period in ticks -system.ruby.l1_cntrl5.L1Dcache.demand_hits 21 # Number of cache demand hits -system.ruby.l1_cntrl5.L1Dcache.demand_misses 78444 # Number of cache demand misses -system.ruby.l1_cntrl5.L1Dcache.demand_accesses 78465 # Number of cache demand accesses -system.ruby.l1_cntrl5.L1Icache.demand_hits 0 # Number of cache demand hits -system.ruby.l1_cntrl5.L1Icache.demand_misses 0 # Number of cache demand misses -system.ruby.l1_cntrl5.L1Icache.demand_accesses 0 # Number of cache demand accesses -system.ruby.l1_cntrl6.L1Dcache.demand_hits 17 # Number of cache demand hits -system.ruby.l1_cntrl6.L1Dcache.demand_misses 77976 # Number of cache demand misses -system.ruby.l1_cntrl6.L1Dcache.demand_accesses 77993 # Number of cache demand accesses -system.ruby.l1_cntrl6.L1Icache.demand_hits 0 # Number of cache demand hits -system.ruby.l1_cntrl6.L1Icache.demand_misses 0 # Number of cache demand misses -system.ruby.l1_cntrl6.L1Icache.demand_accesses 0 # Number of cache demand accesses -system.ruby.l1_cntrl7.L1Dcache.demand_hits 19 # Number of cache demand hits -system.ruby.l1_cntrl7.L1Dcache.demand_misses 77954 # Number of cache demand misses -system.ruby.l1_cntrl7.L1Dcache.demand_accesses 77973 # Number of cache demand accesses -system.ruby.l1_cntrl7.L1Icache.demand_hits 0 # Number of cache demand hits -system.ruby.l1_cntrl7.L1Icache.demand_misses 0 # Number of cache demand misses -system.ruby.l1_cntrl7.L1Icache.demand_accesses 0 # Number of cache demand accesses -system.ruby.l1_cntrl0.L1Dcache.demand_hits 29 # Number of cache demand hits -system.ruby.l1_cntrl0.L1Dcache.demand_misses 78780 # Number of cache demand misses -system.ruby.l1_cntrl0.L1Dcache.demand_accesses 78809 # Number of cache demand accesses +system.ruby.miss_latency_hist::samples 624407 +system.ruby.miss_latency_hist::mean 1200.607091 +system.ruby.miss_latency_hist::gmean 901.592507 +system.ruby.miss_latency_hist::stdev 764.698426 +system.ruby.miss_latency_hist | 168458 26.98% 26.98% | 117382 18.80% 45.78% | 112567 18.03% 63.81% | 119036 19.06% 82.87% | 85189 13.64% 96.51% | 20322 3.25% 99.77% | 1424 0.23% 100.00% | 29 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.miss_latency_hist::total 624407 +system.ruby.L1Cache.incomplete_times 1293 +system.ruby.Directory.incomplete_times 623110 +system.ruby.l1_cntrl0.L1Dcache.demand_hits 21 # Number of cache demand hits +system.ruby.l1_cntrl0.L1Dcache.demand_misses 78749 # Number of cache demand misses +system.ruby.l1_cntrl0.L1Dcache.demand_accesses 78770 # Number of cache demand accesses system.ruby.l1_cntrl0.L1Icache.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl0.L1Icache.demand_misses 0 # Number of cache demand misses system.ruby.l1_cntrl0.L1Icache.demand_accesses 0 # Number of cache demand accesses -system.ruby.network.routers00.percent_links_utilized 9.742411 -system.ruby.network.routers00.msg_count.Request_Control::1 78780 -system.ruby.network.routers00.msg_count.Response_Data::4 80165 -system.ruby.network.routers00.msg_count.ResponseL2hit_Data::4 245 -system.ruby.network.routers00.msg_count.ResponseLocal_Data::4 173 -system.ruby.network.routers00.msg_count.Response_Control::4 76 -system.ruby.network.routers00.msg_count.Writeback_Data::4 85320 -system.ruby.network.routers00.msg_count.Broadcast_Control::1 626107 -system.ruby.network.routers00.msg_count.Persistent_Control::3 102424 -system.ruby.network.routers00.msg_bytes.Request_Control::1 630240 -system.ruby.network.routers00.msg_bytes.Response_Data::4 5771880 -system.ruby.network.routers00.msg_bytes.ResponseL2hit_Data::4 17640 -system.ruby.network.routers00.msg_bytes.ResponseLocal_Data::4 12456 -system.ruby.network.routers00.msg_bytes.Response_Control::4 608 -system.ruby.network.routers00.msg_bytes.Writeback_Data::4 6143040 -system.ruby.network.routers00.msg_bytes.Broadcast_Control::1 5008856 -system.ruby.network.routers00.msg_bytes.Persistent_Control::3 819392 -system.ruby.l1_cntrl1.L1Dcache.demand_hits 22 # Number of cache demand hits -system.ruby.l1_cntrl1.L1Dcache.demand_misses 78342 # Number of cache demand misses -system.ruby.l1_cntrl1.L1Dcache.demand_accesses 78364 # Number of cache demand accesses +system.ruby.l1_cntrl1.L1Dcache.demand_hits 19 # Number of cache demand hits +system.ruby.l1_cntrl1.L1Dcache.demand_misses 78393 # Number of cache demand misses +system.ruby.l1_cntrl1.L1Dcache.demand_accesses 78412 # Number of cache demand accesses system.ruby.l1_cntrl1.L1Icache.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl1.L1Icache.demand_misses 0 # Number of cache demand misses system.ruby.l1_cntrl1.L1Icache.demand_accesses 0 # Number of cache demand accesses -system.ruby.network.routers01.percent_links_utilized 9.710031 -system.ruby.network.routers01.msg_count.Request_Control::1 78342 -system.ruby.network.routers01.msg_count.Response_Data::4 79850 -system.ruby.network.routers01.msg_count.ResponseL2hit_Data::4 247 -system.ruby.network.routers01.msg_count.ResponseLocal_Data::4 189 -system.ruby.network.routers01.msg_count.Response_Control::4 93 -system.ruby.network.routers01.msg_count.Writeback_Data::4 84812 -system.ruby.network.routers01.msg_count.Broadcast_Control::1 626107 -system.ruby.network.routers01.msg_count.Persistent_Control::3 102444 -system.ruby.network.routers01.msg_bytes.Request_Control::1 626736 -system.ruby.network.routers01.msg_bytes.Response_Data::4 5749200 -system.ruby.network.routers01.msg_bytes.ResponseL2hit_Data::4 17784 -system.ruby.network.routers01.msg_bytes.ResponseLocal_Data::4 13608 -system.ruby.network.routers01.msg_bytes.Response_Control::4 744 -system.ruby.network.routers01.msg_bytes.Writeback_Data::4 6106464 -system.ruby.network.routers01.msg_bytes.Broadcast_Control::1 5008856 -system.ruby.network.routers01.msg_bytes.Persistent_Control::3 819552 -system.ruby.l1_cntrl2.L1Dcache.demand_hits 15 # Number of cache demand hits -system.ruby.l1_cntrl2.L1Dcache.demand_misses 78430 # Number of cache demand misses -system.ruby.l1_cntrl2.L1Dcache.demand_accesses 78445 # Number of cache demand accesses +system.ruby.l1_cntrl2.L1Dcache.demand_hits 27 # Number of cache demand hits +system.ruby.l1_cntrl2.L1Dcache.demand_misses 78544 # Number of cache demand misses +system.ruby.l1_cntrl2.L1Dcache.demand_accesses 78571 # Number of cache demand accesses system.ruby.l1_cntrl2.L1Icache.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl2.L1Icache.demand_misses 0 # Number of cache demand misses system.ruby.l1_cntrl2.L1Icache.demand_accesses 0 # Number of cache demand accesses -system.ruby.network.routers02.percent_links_utilized 9.719589 -system.ruby.network.routers02.msg_count.Request_Control::1 78430 -system.ruby.network.routers02.msg_count.Response_Data::4 80036 -system.ruby.network.routers02.msg_count.ResponseL2hit_Data::4 234 -system.ruby.network.routers02.msg_count.ResponseLocal_Data::4 212 -system.ruby.network.routers02.msg_count.Response_Control::4 106 -system.ruby.network.routers02.msg_count.Writeback_Data::4 84849 -system.ruby.network.routers02.msg_count.Broadcast_Control::1 626107 -system.ruby.network.routers02.msg_count.Persistent_Control::3 102504 -system.ruby.network.routers02.msg_bytes.Request_Control::1 627440 -system.ruby.network.routers02.msg_bytes.Response_Data::4 5762592 -system.ruby.network.routers02.msg_bytes.ResponseL2hit_Data::4 16848 -system.ruby.network.routers02.msg_bytes.ResponseLocal_Data::4 15264 -system.ruby.network.routers02.msg_bytes.Response_Control::4 848 -system.ruby.network.routers02.msg_bytes.Writeback_Data::4 6109128 -system.ruby.network.routers02.msg_bytes.Broadcast_Control::1 5008856 -system.ruby.network.routers02.msg_bytes.Persistent_Control::3 820032 -system.ruby.l1_cntrl3.L1Dcache.demand_hits 23 # Number of cache demand hits -system.ruby.l1_cntrl3.L1Dcache.demand_misses 78256 # Number of cache demand misses -system.ruby.l1_cntrl3.L1Dcache.demand_accesses 78279 # Number of cache demand accesses +system.ruby.l1_cntrl3.L1Dcache.demand_hits 24 # Number of cache demand hits +system.ruby.l1_cntrl3.L1Dcache.demand_misses 78065 # Number of cache demand misses +system.ruby.l1_cntrl3.L1Dcache.demand_accesses 78089 # Number of cache demand accesses system.ruby.l1_cntrl3.L1Icache.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl3.L1Icache.demand_misses 0 # Number of cache demand misses system.ruby.l1_cntrl3.L1Icache.demand_accesses 0 # Number of cache demand accesses -system.ruby.network.routers03.percent_links_utilized 9.695103 -system.ruby.network.routers03.msg_count.Request_Control::1 78256 -system.ruby.network.routers03.msg_count.Response_Data::4 79763 -system.ruby.network.routers03.msg_count.ResponseL2hit_Data::4 209 -system.ruby.network.routers03.msg_count.ResponseLocal_Data::4 161 -system.ruby.network.routers03.msg_count.Response_Control::4 98 -system.ruby.network.routers03.msg_count.Writeback_Data::4 84605 -system.ruby.network.routers03.msg_count.Broadcast_Control::1 626107 -system.ruby.network.routers03.msg_count.Persistent_Control::3 102240 -system.ruby.network.routers03.msg_bytes.Request_Control::1 626048 -system.ruby.network.routers03.msg_bytes.Response_Data::4 5742936 -system.ruby.network.routers03.msg_bytes.ResponseL2hit_Data::4 15048 -system.ruby.network.routers03.msg_bytes.ResponseLocal_Data::4 11592 -system.ruby.network.routers03.msg_bytes.Response_Control::4 784 -system.ruby.network.routers03.msg_bytes.Writeback_Data::4 6091560 -system.ruby.network.routers03.msg_bytes.Broadcast_Control::1 5008856 -system.ruby.network.routers03.msg_bytes.Persistent_Control::3 817920 -system.ruby.network.routers04.percent_links_utilized 9.671218 -system.ruby.network.routers04.msg_count.Request_Control::1 77927 -system.ruby.network.routers04.msg_count.Response_Data::4 79373 -system.ruby.network.routers04.msg_count.ResponseL2hit_Data::4 240 -system.ruby.network.routers04.msg_count.ResponseLocal_Data::4 191 -system.ruby.network.routers04.msg_count.Response_Control::4 96 -system.ruby.network.routers04.msg_count.Writeback_Data::4 84339 -system.ruby.network.routers04.msg_count.Broadcast_Control::1 626107 -system.ruby.network.routers04.msg_count.Persistent_Control::3 102286 -system.ruby.network.routers04.msg_bytes.Request_Control::1 623416 -system.ruby.network.routers04.msg_bytes.Response_Data::4 5714856 -system.ruby.network.routers04.msg_bytes.ResponseL2hit_Data::4 17280 -system.ruby.network.routers04.msg_bytes.ResponseLocal_Data::4 13752 -system.ruby.network.routers04.msg_bytes.Response_Control::4 768 -system.ruby.network.routers04.msg_bytes.Writeback_Data::4 6072408 -system.ruby.network.routers04.msg_bytes.Broadcast_Control::1 5008856 -system.ruby.network.routers04.msg_bytes.Persistent_Control::3 818288 -system.ruby.network.routers05.percent_links_utilized 9.714227 -system.ruby.network.routers05.msg_count.Request_Control::1 78443 -system.ruby.network.routers05.msg_count.Response_Data::4 79833 -system.ruby.network.routers05.msg_count.ResponseL2hit_Data::4 223 -system.ruby.network.routers05.msg_count.ResponseLocal_Data::4 191 -system.ruby.network.routers05.msg_count.Response_Control::4 88 -system.ruby.network.routers05.msg_count.Writeback_Data::4 84971 -system.ruby.network.routers05.msg_count.Broadcast_Control::1 626107 -system.ruby.network.routers05.msg_count.Persistent_Control::3 102260 -system.ruby.network.routers05.msg_bytes.Request_Control::1 627544 -system.ruby.network.routers05.msg_bytes.Response_Data::4 5747976 -system.ruby.network.routers05.msg_bytes.ResponseL2hit_Data::4 16056 -system.ruby.network.routers05.msg_bytes.ResponseLocal_Data::4 13752 -system.ruby.network.routers05.msg_bytes.Response_Control::4 704 -system.ruby.network.routers05.msg_bytes.Writeback_Data::4 6117912 -system.ruby.network.routers05.msg_bytes.Broadcast_Control::1 5008856 -system.ruby.network.routers05.msg_bytes.Persistent_Control::3 818080 -system.ruby.network.routers06.percent_links_utilized 9.677168 -system.ruby.network.routers06.msg_count.Request_Control::1 77976 -system.ruby.network.routers06.msg_count.Response_Data::4 79371 -system.ruby.network.routers06.msg_count.ResponseL2hit_Data::4 225 -system.ruby.network.routers06.msg_count.ResponseLocal_Data::4 160 -system.ruby.network.routers06.msg_count.Response_Control::4 78 -system.ruby.network.routers06.msg_count.Writeback_Data::4 84535 -system.ruby.network.routers06.msg_count.Broadcast_Control::1 626107 -system.ruby.network.routers06.msg_count.Persistent_Control::3 102328 -system.ruby.network.routers06.msg_bytes.Request_Control::1 623808 -system.ruby.network.routers06.msg_bytes.Response_Data::4 5714712 -system.ruby.network.routers06.msg_bytes.ResponseL2hit_Data::4 16200 -system.ruby.network.routers06.msg_bytes.ResponseLocal_Data::4 11520 -system.ruby.network.routers06.msg_bytes.Response_Control::4 624 -system.ruby.network.routers06.msg_bytes.Writeback_Data::4 6086520 -system.ruby.network.routers06.msg_bytes.Broadcast_Control::1 5008856 -system.ruby.network.routers06.msg_bytes.Persistent_Control::3 818624 -system.ruby.network.routers07.percent_links_utilized 9.675588 -system.ruby.network.routers07.msg_count.Request_Control::1 77953 -system.ruby.network.routers07.msg_count.Response_Data::4 79349 -system.ruby.network.routers07.msg_count.ResponseL2hit_Data::4 241 -system.ruby.network.routers07.msg_count.ResponseLocal_Data::4 187 -system.ruby.network.routers07.msg_count.Response_Control::4 91 -system.ruby.network.routers07.msg_count.Writeback_Data::4 84477 -system.ruby.network.routers07.msg_count.Broadcast_Control::1 626107 -system.ruby.network.routers07.msg_count.Persistent_Control::3 102298 -system.ruby.network.routers07.msg_bytes.Request_Control::1 623624 -system.ruby.network.routers07.msg_bytes.Response_Data::4 5713128 -system.ruby.network.routers07.msg_bytes.ResponseL2hit_Data::4 17352 -system.ruby.network.routers07.msg_bytes.ResponseLocal_Data::4 13464 -system.ruby.network.routers07.msg_bytes.Response_Control::4 728 -system.ruby.network.routers07.msg_bytes.Writeback_Data::4 6082344 -system.ruby.network.routers07.msg_bytes.Broadcast_Control::1 5008856 -system.ruby.network.routers07.msg_bytes.Persistent_Control::3 818384 -system.ruby.l2_cntrl0.L2cache.demand_hits 1784 # Number of cache demand hits -system.ruby.l2_cntrl0.L2cache.demand_misses 624319 # Number of cache demand misses -system.ruby.l2_cntrl0.L2cache.demand_accesses 626103 # Number of cache demand accesses -system.ruby.network.routers08.percent_links_utilized 40.519928 -system.ruby.network.routers08.msg_count.Request_Control::1 626105 -system.ruby.network.routers08.msg_count.Request_Control::2 624315 -system.ruby.network.routers08.msg_count.Response_Data::4 7830 -system.ruby.network.routers08.msg_count.ResponseL2hit_Data::4 1784 -system.ruby.network.routers08.msg_count.Response_Control::4 713 -system.ruby.network.routers08.msg_count.Writeback_Data::4 862238 -system.ruby.network.routers08.msg_count.Writeback_Control::4 379354 -system.ruby.network.routers08.msg_count.Persistent_Control::3 90976 -system.ruby.network.routers08.msg_bytes.Request_Control::1 5008840 -system.ruby.network.routers08.msg_bytes.Request_Control::2 4994520 -system.ruby.network.routers08.msg_bytes.Response_Data::4 563760 -system.ruby.network.routers08.msg_bytes.ResponseL2hit_Data::4 128448 -system.ruby.network.routers08.msg_bytes.Response_Control::4 5704 -system.ruby.network.routers08.msg_bytes.Writeback_Data::4 62081136 -system.ruby.network.routers08.msg_bytes.Writeback_Control::4 3034832 -system.ruby.network.routers08.msg_bytes.Persistent_Control::3 727808 -system.ruby.network.routers09.percent_links_utilized 37.644894 -system.ruby.network.routers09.msg_count.Request_Control::2 624315 -system.ruby.network.routers09.msg_count.Response_Data::4 628897 -system.ruby.network.routers09.msg_count.ResponseL2hit_Data::4 80 -system.ruby.network.routers09.msg_count.Response_Control::4 3 -system.ruby.network.routers09.msg_count.Writeback_Data::4 237089 -system.ruby.network.routers09.msg_count.Writeback_Control::4 379353 -system.ruby.network.routers09.msg_count.Persistent_Control::3 90976 -system.ruby.network.routers09.msg_bytes.Request_Control::2 4994520 -system.ruby.network.routers09.msg_bytes.Response_Data::4 45280584 -system.ruby.network.routers09.msg_bytes.ResponseL2hit_Data::4 5760 -system.ruby.network.routers09.msg_bytes.Response_Control::4 24 -system.ruby.network.routers09.msg_bytes.Writeback_Data::4 17070408 -system.ruby.network.routers09.msg_bytes.Writeback_Control::4 3034824 -system.ruby.network.routers09.msg_bytes.Persistent_Control::3 727808 -system.ruby.network.routers10.percent_links_utilized 17.437599 -system.ruby.network.routers10.msg_count.Request_Control::1 626105 -system.ruby.network.routers10.msg_count.Request_Control::2 624315 -system.ruby.network.routers10.msg_count.Response_Data::4 637234 -system.ruby.network.routers10.msg_count.ResponseL2hit_Data::4 1864 -system.ruby.network.routers10.msg_count.ResponseLocal_Data::4 732 -system.ruby.network.routers10.msg_count.Response_Control::4 721 -system.ruby.network.routers10.msg_count.Writeback_Data::4 888618 -system.ruby.network.routers10.msg_count.Writeback_Control::4 379353 -system.ruby.network.routers10.msg_count.Broadcast_Control::1 4382749 -system.ruby.network.routers10.msg_count.Persistent_Control::3 818784 -system.ruby.network.routers10.msg_bytes.Request_Control::1 5008840 -system.ruby.network.routers10.msg_bytes.Request_Control::2 4994520 -system.ruby.network.routers10.msg_bytes.Response_Data::4 45880848 -system.ruby.network.routers10.msg_bytes.ResponseL2hit_Data::4 134208 -system.ruby.network.routers10.msg_bytes.ResponseLocal_Data::4 52704 -system.ruby.network.routers10.msg_bytes.Response_Control::4 5768 -system.ruby.network.routers10.msg_bytes.Writeback_Data::4 63980496 -system.ruby.network.routers10.msg_bytes.Writeback_Control::4 3034824 -system.ruby.network.routers10.msg_bytes.Broadcast_Control::1 35061992 -system.ruby.network.routers10.msg_bytes.Persistent_Control::3 6550272 -system.ruby.network.msg_count.Request_Control 3751262 -system.ruby.network.msg_count.Response_Data 1911701 -system.ruby.network.msg_count.ResponseL2hit_Data 5592 -system.ruby.network.msg_count.ResponseLocal_Data 2196 -system.ruby.network.msg_count.Response_Control 2163 -system.ruby.network.msg_count.Writeback_Data 2665853 -system.ruby.network.msg_count.Writeback_Control 1138060 -system.ruby.network.msg_count.Broadcast_Control 9391605 -system.ruby.network.msg_count.Persistent_Control 1819520 -system.ruby.network.msg_byte.Request_Control 30010096 -system.ruby.network.msg_byte.Response_Data 137642472 -system.ruby.network.msg_byte.ResponseL2hit_Data 402624 -system.ruby.network.msg_byte.ResponseLocal_Data 158112 -system.ruby.network.msg_byte.Response_Control 17304 -system.ruby.network.msg_byte.Writeback_Data 191941416 -system.ruby.network.msg_byte.Writeback_Control 9104480 -system.ruby.network.msg_byte.Broadcast_Control 75132840 -system.ruby.network.msg_byte.Persistent_Control 14556160 +system.ruby.l1_cntrl4.L1Dcache.demand_hits 24 # Number of cache demand hits +system.ruby.l1_cntrl4.L1Dcache.demand_misses 78237 # Number of cache demand misses +system.ruby.l1_cntrl4.L1Dcache.demand_accesses 78261 # Number of cache demand accesses +system.ruby.l1_cntrl4.L1Icache.demand_hits 0 # Number of cache demand hits +system.ruby.l1_cntrl4.L1Icache.demand_misses 0 # Number of cache demand misses +system.ruby.l1_cntrl4.L1Icache.demand_accesses 0 # Number of cache demand accesses +system.ruby.l1_cntrl5.L1Dcache.demand_hits 25 # Number of cache demand hits +system.ruby.l1_cntrl5.L1Dcache.demand_misses 78351 # Number of cache demand misses +system.ruby.l1_cntrl5.L1Dcache.demand_accesses 78376 # Number of cache demand accesses +system.ruby.l1_cntrl5.L1Icache.demand_hits 0 # Number of cache demand hits +system.ruby.l1_cntrl5.L1Icache.demand_misses 0 # Number of cache demand misses +system.ruby.l1_cntrl5.L1Icache.demand_accesses 0 # Number of cache demand accesses +system.ruby.l1_cntrl6.L1Dcache.demand_hits 19 # Number of cache demand hits +system.ruby.l1_cntrl6.L1Dcache.demand_misses 78471 # Number of cache demand misses +system.ruby.l1_cntrl6.L1Dcache.demand_accesses 78490 # Number of cache demand accesses +system.ruby.l1_cntrl6.L1Icache.demand_hits 0 # Number of cache demand hits +system.ruby.l1_cntrl6.L1Icache.demand_misses 0 # Number of cache demand misses +system.ruby.l1_cntrl6.L1Icache.demand_accesses 0 # Number of cache demand accesses +system.ruby.l1_cntrl7.L1Dcache.demand_hits 27 # Number of cache demand hits +system.ruby.l1_cntrl7.L1Dcache.demand_misses 78277 # Number of cache demand misses +system.ruby.l1_cntrl7.L1Dcache.demand_accesses 78304 # Number of cache demand accesses +system.ruby.l1_cntrl7.L1Icache.demand_hits 0 # Number of cache demand hits +system.ruby.l1_cntrl7.L1Icache.demand_misses 0 # Number of cache demand misses +system.ruby.l1_cntrl7.L1Icache.demand_accesses 0 # Number of cache demand accesses +system.ruby.l2_cntrl0.L2cache.demand_hits 1846 # Number of cache demand hits +system.ruby.l2_cntrl0.L2cache.demand_misses 625240 # Number of cache demand misses +system.ruby.l2_cntrl0.L2cache.demand_accesses 627086 # Number of cache demand accesses system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.cpu0.num_reads 99493 # number of read accesses completed -system.cpu0.num_writes 55749 # number of write accesses completed -system.cpu0.num_copies 0 # number of copy accesses completed -system.cpu1.num_reads 99510 # number of read accesses completed -system.cpu1.num_writes 55185 # number of write accesses completed -system.cpu1.num_copies 0 # number of copy accesses completed -system.cpu2.num_reads 100000 # number of read accesses completed -system.cpu2.num_writes 55529 # number of write accesses completed -system.cpu2.num_copies 0 # number of copy accesses completed -system.cpu3.num_reads 99207 # number of read accesses completed -system.cpu3.num_writes 55624 # number of write accesses completed -system.cpu3.num_copies 0 # number of copy accesses completed -system.cpu4.num_reads 99506 # number of read accesses completed -system.cpu4.num_writes 55147 # number of write accesses completed -system.cpu4.num_copies 0 # number of copy accesses completed -system.cpu5.num_reads 99763 # number of read accesses completed -system.cpu5.num_writes 55468 # number of write accesses completed -system.cpu5.num_copies 0 # number of copy accesses completed -system.cpu6.num_reads 98903 # number of read accesses completed -system.cpu6.num_writes 54921 # number of write accesses completed -system.cpu6.num_copies 0 # number of copy accesses completed -system.cpu7.num_reads 99232 # number of read accesses completed -system.cpu7.num_writes 54585 # number of write accesses completed -system.cpu7.num_copies 0 # number of copy accesses completed -system.ruby.network.routers00.throttle0.link_utilization 11.727792 -system.ruby.network.routers00.throttle0.msg_count.Response_Data::4 79274 -system.ruby.network.routers00.throttle0.msg_count.ResponseL2hit_Data::4 233 -system.ruby.network.routers00.throttle0.msg_count.ResponseLocal_Data::4 95 -system.ruby.network.routers00.throttle0.msg_count.Response_Control::4 1 -system.ruby.network.routers00.throttle0.msg_count.Writeback_Data::4 3327 -system.ruby.network.routers00.throttle0.msg_count.Broadcast_Control::1 547327 -system.ruby.network.routers00.throttle0.msg_count.Persistent_Control::3 90976 -system.ruby.network.routers00.throttle0.msg_bytes.Response_Data::4 5707728 -system.ruby.network.routers00.throttle0.msg_bytes.ResponseL2hit_Data::4 16776 -system.ruby.network.routers00.throttle0.msg_bytes.ResponseLocal_Data::4 6840 -system.ruby.network.routers00.throttle0.msg_bytes.Response_Control::4 8 -system.ruby.network.routers00.throttle0.msg_bytes.Writeback_Data::4 239544 -system.ruby.network.routers00.throttle0.msg_bytes.Broadcast_Control::1 4378616 -system.ruby.network.routers00.throttle0.msg_bytes.Persistent_Control::3 727808 -system.ruby.network.routers00.throttle1.link_utilization 7.757029 -system.ruby.network.routers00.throttle1.msg_count.Request_Control::1 78780 -system.ruby.network.routers00.throttle1.msg_count.Response_Data::4 891 -system.ruby.network.routers00.throttle1.msg_count.ResponseL2hit_Data::4 12 -system.ruby.network.routers00.throttle1.msg_count.ResponseLocal_Data::4 78 -system.ruby.network.routers00.throttle1.msg_count.Response_Control::4 75 -system.ruby.network.routers00.throttle1.msg_count.Writeback_Data::4 81993 -system.ruby.network.routers00.throttle1.msg_count.Broadcast_Control::1 78780 -system.ruby.network.routers00.throttle1.msg_count.Persistent_Control::3 11448 -system.ruby.network.routers00.throttle1.msg_bytes.Request_Control::1 630240 -system.ruby.network.routers00.throttle1.msg_bytes.Response_Data::4 64152 -system.ruby.network.routers00.throttle1.msg_bytes.ResponseL2hit_Data::4 864 -system.ruby.network.routers00.throttle1.msg_bytes.ResponseLocal_Data::4 5616 -system.ruby.network.routers00.throttle1.msg_bytes.Response_Control::4 600 -system.ruby.network.routers00.throttle1.msg_bytes.Writeback_Data::4 5903496 -system.ruby.network.routers00.throttle1.msg_bytes.Broadcast_Control::1 630240 -system.ruby.network.routers00.throttle1.msg_bytes.Persistent_Control::3 91584 -system.ruby.network.routers01.throttle0.link_utilization 11.700088 -system.ruby.network.routers01.throttle0.msg_count.Response_Data::4 78881 -system.ruby.network.routers01.throttle0.msg_count.ResponseL2hit_Data::4 231 -system.ruby.network.routers01.throttle0.msg_count.ResponseLocal_Data::4 99 -system.ruby.network.routers01.throttle0.msg_count.Writeback_Data::4 3306 -system.ruby.network.routers01.throttle0.msg_count.Broadcast_Control::1 547765 -system.ruby.network.routers01.throttle0.msg_count.Persistent_Control::3 90976 -system.ruby.network.routers01.throttle0.msg_bytes.Response_Data::4 5679432 -system.ruby.network.routers01.throttle0.msg_bytes.ResponseL2hit_Data::4 16632 -system.ruby.network.routers01.throttle0.msg_bytes.ResponseLocal_Data::4 7128 -system.ruby.network.routers01.throttle0.msg_bytes.Writeback_Data::4 238032 -system.ruby.network.routers01.throttle0.msg_bytes.Broadcast_Control::1 4382120 -system.ruby.network.routers01.throttle0.msg_bytes.Persistent_Control::3 727808 -system.ruby.network.routers01.throttle1.link_utilization 7.719974 -system.ruby.network.routers01.throttle1.msg_count.Request_Control::1 78342 +system.ruby.network.routers00.percent_links_utilized 9.769549 +system.ruby.network.routers00.msg_count.Request_Control::1 78749 +system.ruby.network.routers00.msg_count.Response_Data::4 80262 +system.ruby.network.routers00.msg_count.ResponseL2hit_Data::4 229 +system.ruby.network.routers00.msg_count.ResponseLocal_Data::4 199 +system.ruby.network.routers00.msg_count.Response_Control::4 85 +system.ruby.network.routers00.msg_count.Writeback_Data::4 85149 +system.ruby.network.routers00.msg_count.Broadcast_Control::1 627086 +system.ruby.network.routers00.msg_count.Persistent_Control::3 99744 +system.ruby.network.routers00.msg_bytes.Request_Control::1 629992 +system.ruby.network.routers00.msg_bytes.Response_Data::4 5778864 +system.ruby.network.routers00.msg_bytes.ResponseL2hit_Data::4 16488 +system.ruby.network.routers00.msg_bytes.ResponseLocal_Data::4 14328 +system.ruby.network.routers00.msg_bytes.Response_Control::4 680 +system.ruby.network.routers00.msg_bytes.Writeback_Data::4 6130728 +system.ruby.network.routers00.msg_bytes.Broadcast_Control::1 5016688 +system.ruby.network.routers00.msg_bytes.Persistent_Control::3 797952 +system.ruby.network.routers01.percent_links_utilized 9.734067 +system.ruby.network.routers01.msg_count.Request_Control::1 78393 +system.ruby.network.routers01.msg_count.Response_Data::4 79915 +system.ruby.network.routers01.msg_count.ResponseL2hit_Data::4 248 +system.ruby.network.routers01.msg_count.ResponseLocal_Data::4 173 +system.ruby.network.routers01.msg_count.Response_Control::4 88 +system.ruby.network.routers01.msg_count.Writeback_Data::4 84641 +system.ruby.network.routers01.msg_count.Writeback_Control::4 2 +system.ruby.network.routers01.msg_count.Broadcast_Control::1 627086 +system.ruby.network.routers01.msg_count.Persistent_Control::3 99506 +system.ruby.network.routers01.msg_bytes.Request_Control::1 627144 +system.ruby.network.routers01.msg_bytes.Response_Data::4 5753880 +system.ruby.network.routers01.msg_bytes.ResponseL2hit_Data::4 17856 +system.ruby.network.routers01.msg_bytes.ResponseLocal_Data::4 12456 +system.ruby.network.routers01.msg_bytes.Response_Control::4 704 +system.ruby.network.routers01.msg_bytes.Writeback_Data::4 6094152 +system.ruby.network.routers01.msg_bytes.Writeback_Control::4 16 +system.ruby.network.routers01.msg_bytes.Broadcast_Control::1 5016688 +system.ruby.network.routers01.msg_bytes.Persistent_Control::3 796048 +system.ruby.network.routers02.percent_links_utilized 9.751836 +system.ruby.network.routers02.msg_count.Request_Control::1 78544 +system.ruby.network.routers02.msg_count.Response_Data::4 80094 +system.ruby.network.routers02.msg_count.ResponseL2hit_Data::4 265 +system.ruby.network.routers02.msg_count.ResponseLocal_Data::4 179 +system.ruby.network.routers02.msg_count.Response_Control::4 92 +system.ruby.network.routers02.msg_count.Writeback_Data::4 84876 +system.ruby.network.routers02.msg_count.Writeback_Control::4 2 +system.ruby.network.routers02.msg_count.Broadcast_Control::1 627086 +system.ruby.network.routers02.msg_count.Persistent_Control::3 99598 +system.ruby.network.routers02.msg_bytes.Request_Control::1 628352 +system.ruby.network.routers02.msg_bytes.Response_Data::4 5766768 +system.ruby.network.routers02.msg_bytes.ResponseL2hit_Data::4 19080 +system.ruby.network.routers02.msg_bytes.ResponseLocal_Data::4 12888 +system.ruby.network.routers02.msg_bytes.Response_Control::4 736 +system.ruby.network.routers02.msg_bytes.Writeback_Data::4 6111072 +system.ruby.network.routers02.msg_bytes.Writeback_Control::4 16 +system.ruby.network.routers02.msg_bytes.Broadcast_Control::1 5016688 +system.ruby.network.routers02.msg_bytes.Persistent_Control::3 796784 +system.ruby.network.routers03.percent_links_utilized 9.705650 +system.ruby.network.routers03.msg_count.Request_Control::1 78065 +system.ruby.network.routers03.msg_count.Response_Data::4 79606 +system.ruby.network.routers03.msg_count.ResponseL2hit_Data::4 252 +system.ruby.network.routers03.msg_count.ResponseLocal_Data::4 181 +system.ruby.network.routers03.msg_count.Response_Control::4 73 +system.ruby.network.routers03.msg_count.Writeback_Data::4 84239 +system.ruby.network.routers03.msg_count.Broadcast_Control::1 627087 +system.ruby.network.routers03.msg_count.Persistent_Control::3 99456 +system.ruby.network.routers03.msg_bytes.Request_Control::1 624520 +system.ruby.network.routers03.msg_bytes.Response_Data::4 5731632 +system.ruby.network.routers03.msg_bytes.ResponseL2hit_Data::4 18144 +system.ruby.network.routers03.msg_bytes.ResponseLocal_Data::4 13032 +system.ruby.network.routers03.msg_bytes.Response_Control::4 584 +system.ruby.network.routers03.msg_bytes.Writeback_Data::4 6065208 +system.ruby.network.routers03.msg_bytes.Broadcast_Control::1 5016696 +system.ruby.network.routers03.msg_bytes.Persistent_Control::3 795648 +system.ruby.network.routers04.percent_links_utilized 9.729195 +system.ruby.network.routers04.msg_count.Request_Control::1 78237 +system.ruby.network.routers04.msg_count.Response_Data::4 79812 +system.ruby.network.routers04.msg_count.ResponseL2hit_Data::4 252 +system.ruby.network.routers04.msg_count.ResponseLocal_Data::4 208 +system.ruby.network.routers04.msg_count.Response_Control::4 89 +system.ruby.network.routers04.msg_count.Writeback_Data::4 84584 +system.ruby.network.routers04.msg_count.Broadcast_Control::1 627086 +system.ruby.network.routers04.msg_count.Persistent_Control::3 99606 +system.ruby.network.routers04.msg_bytes.Request_Control::1 625896 +system.ruby.network.routers04.msg_bytes.Response_Data::4 5746464 +system.ruby.network.routers04.msg_bytes.ResponseL2hit_Data::4 18144 +system.ruby.network.routers04.msg_bytes.ResponseLocal_Data::4 14976 +system.ruby.network.routers04.msg_bytes.Response_Control::4 712 +system.ruby.network.routers04.msg_bytes.Writeback_Data::4 6090048 +system.ruby.network.routers04.msg_bytes.Broadcast_Control::1 5016688 +system.ruby.network.routers04.msg_bytes.Persistent_Control::3 796848 +system.ruby.network.routers05.percent_links_utilized 9.733064 +system.ruby.network.routers05.msg_count.Request_Control::1 78351 +system.ruby.network.routers05.msg_count.Response_Data::4 79847 +system.ruby.network.routers05.msg_count.ResponseL2hit_Data::4 229 +system.ruby.network.routers05.msg_count.ResponseLocal_Data::4 176 +system.ruby.network.routers05.msg_count.Response_Control::4 95 +system.ruby.network.routers05.msg_count.Writeback_Data::4 84692 +system.ruby.network.routers05.msg_count.Broadcast_Control::1 627086 +system.ruby.network.routers05.msg_count.Persistent_Control::3 99604 +system.ruby.network.routers05.msg_bytes.Request_Control::1 626808 +system.ruby.network.routers05.msg_bytes.Response_Data::4 5748984 +system.ruby.network.routers05.msg_bytes.ResponseL2hit_Data::4 16488 +system.ruby.network.routers05.msg_bytes.ResponseLocal_Data::4 12672 +system.ruby.network.routers05.msg_bytes.Response_Control::4 760 +system.ruby.network.routers05.msg_bytes.Writeback_Data::4 6097824 +system.ruby.network.routers05.msg_bytes.Broadcast_Control::1 5016688 +system.ruby.network.routers05.msg_bytes.Persistent_Control::3 796832 +system.ruby.network.routers06.percent_links_utilized 9.739151 +system.ruby.network.routers06.msg_count.Request_Control::1 78471 +system.ruby.network.routers06.msg_count.Response_Data::4 80021 +system.ruby.network.routers06.msg_count.ResponseL2hit_Data::4 245 +system.ruby.network.routers06.msg_count.ResponseLocal_Data::4 162 +system.ruby.network.routers06.msg_count.Response_Control::4 76 +system.ruby.network.routers06.msg_count.Writeback_Data::4 84699 +system.ruby.network.routers06.msg_count.Broadcast_Control::1 627086 +system.ruby.network.routers06.msg_count.Persistent_Control::3 99288 +system.ruby.network.routers06.msg_bytes.Request_Control::1 627768 +system.ruby.network.routers06.msg_bytes.Response_Data::4 5761512 +system.ruby.network.routers06.msg_bytes.ResponseL2hit_Data::4 17640 +system.ruby.network.routers06.msg_bytes.ResponseLocal_Data::4 11664 +system.ruby.network.routers06.msg_bytes.Response_Control::4 608 +system.ruby.network.routers06.msg_bytes.Writeback_Data::4 6098328 +system.ruby.network.routers06.msg_bytes.Broadcast_Control::1 5016688 +system.ruby.network.routers06.msg_bytes.Persistent_Control::3 794304 +system.ruby.network.routers07.percent_links_utilized 9.723397 +system.ruby.network.routers07.msg_count.Request_Control::1 78277 +system.ruby.network.routers07.msg_count.Response_Data::4 79832 +system.ruby.network.routers07.msg_count.ResponseL2hit_Data::4 226 +system.ruby.network.routers07.msg_count.ResponseLocal_Data::4 190 +system.ruby.network.routers07.msg_count.Response_Control::4 90 +system.ruby.network.routers07.msg_count.Writeback_Data::4 84486 +system.ruby.network.routers07.msg_count.Broadcast_Control::1 627086 +system.ruby.network.routers07.msg_count.Persistent_Control::3 99302 +system.ruby.network.routers07.msg_bytes.Request_Control::1 626216 +system.ruby.network.routers07.msg_bytes.Response_Data::4 5747904 +system.ruby.network.routers07.msg_bytes.ResponseL2hit_Data::4 16272 +system.ruby.network.routers07.msg_bytes.ResponseLocal_Data::4 13680 +system.ruby.network.routers07.msg_bytes.Response_Control::4 720 +system.ruby.network.routers07.msg_bytes.Writeback_Data::4 6082992 +system.ruby.network.routers07.msg_bytes.Broadcast_Control::1 5016688 +system.ruby.network.routers07.msg_bytes.Persistent_Control::3 794416 +system.ruby.network.routers08.percent_links_utilized 40.706771 +system.ruby.network.routers08.msg_count.Request_Control::1 627086 +system.ruby.network.routers08.msg_count.Request_Control::2 625240 +system.ruby.network.routers08.msg_count.Response_Data::4 8185 +system.ruby.network.routers08.msg_count.ResponseL2hit_Data::4 1849 +system.ruby.network.routers08.msg_count.Response_Control::4 670 +system.ruby.network.routers08.msg_count.Writeback_Data::4 862628 +system.ruby.network.routers08.msg_count.Writeback_Control::4 380561 +system.ruby.network.routers08.msg_count.Persistent_Control::3 88456 +system.ruby.network.routers08.msg_bytes.Request_Control::1 5016688 +system.ruby.network.routers08.msg_bytes.Request_Control::2 5001920 +system.ruby.network.routers08.msg_bytes.Response_Data::4 589320 +system.ruby.network.routers08.msg_bytes.ResponseL2hit_Data::4 133128 +system.ruby.network.routers08.msg_bytes.Response_Control::4 5360 +system.ruby.network.routers08.msg_bytes.Writeback_Data::4 62109216 +system.ruby.network.routers08.msg_bytes.Writeback_Control::4 3044488 +system.ruby.network.routers08.msg_bytes.Persistent_Control::3 707648 +system.ruby.network.routers09.percent_links_utilized 37.815867 +system.ruby.network.routers09.msg_count.Request_Control::2 625238 +system.ruby.network.routers09.msg_count.Response_Data::4 630263 +system.ruby.network.routers09.msg_count.ResponseL2hit_Data::4 97 +system.ruby.network.routers09.msg_count.Response_Control::4 4 +system.ruby.network.routers09.msg_count.Writeback_Data::4 236490 +system.ruby.network.routers09.msg_count.Writeback_Control::4 380565 +system.ruby.network.routers09.msg_count.Persistent_Control::3 88456 +system.ruby.network.routers09.msg_bytes.Request_Control::2 5001904 +system.ruby.network.routers09.msg_bytes.Response_Data::4 45378936 +system.ruby.network.routers09.msg_bytes.ResponseL2hit_Data::4 6984 +system.ruby.network.routers09.msg_bytes.Response_Control::4 32 +system.ruby.network.routers09.msg_bytes.Writeback_Data::4 17027280 +system.ruby.network.routers09.msg_bytes.Writeback_Control::4 3044520 +system.ruby.network.routers09.msg_bytes.Persistent_Control::3 707648 +system.ruby.network.routers10.percent_links_utilized 17.503496 +system.ruby.network.routers10.msg_count.Request_Control::1 627087 +system.ruby.network.routers10.msg_count.Request_Control::2 625240 +system.ruby.network.routers10.msg_count.Response_Data::4 638918 +system.ruby.network.routers10.msg_count.ResponseL2hit_Data::4 1946 +system.ruby.network.routers10.msg_count.ResponseLocal_Data::4 734 +system.ruby.network.routers10.msg_count.Response_Control::4 681 +system.ruby.network.routers10.msg_count.Writeback_Data::4 888242 +system.ruby.network.routers10.msg_count.Writeback_Control::4 380565 +system.ruby.network.routers10.msg_count.Broadcast_Control::1 4389609 +system.ruby.network.routers10.msg_count.Persistent_Control::3 796104 +system.ruby.network.routers10.msg_bytes.Request_Control::1 5016696 +system.ruby.network.routers10.msg_bytes.Request_Control::2 5001920 +system.ruby.network.routers10.msg_bytes.Response_Data::4 46002096 +system.ruby.network.routers10.msg_bytes.ResponseL2hit_Data::4 140112 +system.ruby.network.routers10.msg_bytes.ResponseLocal_Data::4 52848 +system.ruby.network.routers10.msg_bytes.Response_Control::4 5448 +system.ruby.network.routers10.msg_bytes.Writeback_Data::4 63953424 +system.ruby.network.routers10.msg_bytes.Writeback_Control::4 3044520 +system.ruby.network.routers10.msg_bytes.Broadcast_Control::1 35116872 +system.ruby.network.routers10.msg_bytes.Persistent_Control::3 6368832 +system.ruby.network.msg_count.Request_Control 3756978 +system.ruby.network.msg_count.Response_Data 1916755 +system.ruby.network.msg_count.ResponseL2hit_Data 5838 +system.ruby.network.msg_count.ResponseLocal_Data 2202 +system.ruby.network.msg_count.Response_Control 2043 +system.ruby.network.msg_count.Writeback_Data 2664726 +system.ruby.network.msg_count.Writeback_Control 1141695 +system.ruby.network.msg_count.Broadcast_Control 9406298 +system.ruby.network.msg_count.Persistent_Control 1769120 +system.ruby.network.msg_byte.Request_Control 30055824 +system.ruby.network.msg_byte.Response_Data 138006360 +system.ruby.network.msg_byte.ResponseL2hit_Data 420336 +system.ruby.network.msg_byte.ResponseLocal_Data 158544 +system.ruby.network.msg_byte.Response_Control 16344 +system.ruby.network.msg_byte.Writeback_Data 191860272 +system.ruby.network.msg_byte.Writeback_Control 9133560 +system.ruby.network.msg_byte.Broadcast_Control 75250384 +system.ruby.network.msg_byte.Persistent_Control 14152960 +system.ruby.network.routers00.throttle0.link_utilization 11.756719 +system.ruby.network.routers00.throttle0.msg_count.Response_Data::4 79304 +system.ruby.network.routers00.throttle0.msg_count.ResponseL2hit_Data::4 218 +system.ruby.network.routers00.throttle0.msg_count.ResponseLocal_Data::4 108 +system.ruby.network.routers00.throttle0.msg_count.Response_Control::4 2 +system.ruby.network.routers00.throttle0.msg_count.Writeback_Data::4 3264 +system.ruby.network.routers00.throttle0.msg_count.Broadcast_Control::1 548337 +system.ruby.network.routers00.throttle0.msg_count.Persistent_Control::3 88456 +system.ruby.network.routers00.throttle0.msg_bytes.Response_Data::4 5709888 +system.ruby.network.routers00.throttle0.msg_bytes.ResponseL2hit_Data::4 15696 +system.ruby.network.routers00.throttle0.msg_bytes.ResponseLocal_Data::4 7776 +system.ruby.network.routers00.throttle0.msg_bytes.Response_Control::4 16 +system.ruby.network.routers00.throttle0.msg_bytes.Writeback_Data::4 235008 +system.ruby.network.routers00.throttle0.msg_bytes.Broadcast_Control::1 4386696 +system.ruby.network.routers00.throttle0.msg_bytes.Persistent_Control::3 707648 +system.ruby.network.routers00.throttle1.link_utilization 7.782380 +system.ruby.network.routers00.throttle1.msg_count.Request_Control::1 78749 +system.ruby.network.routers00.throttle1.msg_count.Response_Data::4 958 +system.ruby.network.routers00.throttle1.msg_count.ResponseL2hit_Data::4 11 +system.ruby.network.routers00.throttle1.msg_count.ResponseLocal_Data::4 91 +system.ruby.network.routers00.throttle1.msg_count.Response_Control::4 83 +system.ruby.network.routers00.throttle1.msg_count.Writeback_Data::4 81885 +system.ruby.network.routers00.throttle1.msg_count.Broadcast_Control::1 78749 +system.ruby.network.routers00.throttle1.msg_count.Persistent_Control::3 11288 +system.ruby.network.routers00.throttle1.msg_bytes.Request_Control::1 629992 +system.ruby.network.routers00.throttle1.msg_bytes.Response_Data::4 68976 +system.ruby.network.routers00.throttle1.msg_bytes.ResponseL2hit_Data::4 792 +system.ruby.network.routers00.throttle1.msg_bytes.ResponseLocal_Data::4 6552 +system.ruby.network.routers00.throttle1.msg_bytes.Response_Control::4 664 +system.ruby.network.routers00.throttle1.msg_bytes.Writeback_Data::4 5895720 +system.ruby.network.routers00.throttle1.msg_bytes.Broadcast_Control::1 629992 +system.ruby.network.routers00.throttle1.msg_bytes.Persistent_Control::3 90304 +system.ruby.network.routers01.throttle0.link_utilization 11.725925 +system.ruby.network.routers01.throttle0.msg_count.Response_Data::4 78946 +system.ruby.network.routers01.throttle0.msg_count.ResponseL2hit_Data::4 242 +system.ruby.network.routers01.throttle0.msg_count.ResponseLocal_Data::4 74 +system.ruby.network.routers01.throttle0.msg_count.Response_Control::4 1 +system.ruby.network.routers01.throttle0.msg_count.Writeback_Data::4 3190 +system.ruby.network.routers01.throttle0.msg_count.Writeback_Control::4 1 +system.ruby.network.routers01.throttle0.msg_count.Broadcast_Control::1 548693 +system.ruby.network.routers01.throttle0.msg_count.Persistent_Control::3 88456 +system.ruby.network.routers01.throttle0.msg_bytes.Response_Data::4 5684112 +system.ruby.network.routers01.throttle0.msg_bytes.ResponseL2hit_Data::4 17424 +system.ruby.network.routers01.throttle0.msg_bytes.ResponseLocal_Data::4 5328 +system.ruby.network.routers01.throttle0.msg_bytes.Response_Control::4 8 +system.ruby.network.routers01.throttle0.msg_bytes.Writeback_Data::4 229680 +system.ruby.network.routers01.throttle0.msg_bytes.Writeback_Control::4 8 +system.ruby.network.routers01.throttle0.msg_bytes.Broadcast_Control::1 4389544 +system.ruby.network.routers01.throttle0.msg_bytes.Persistent_Control::3 707648 +system.ruby.network.routers01.throttle1.link_utilization 7.742209 +system.ruby.network.routers01.throttle1.msg_count.Request_Control::1 78393 system.ruby.network.routers01.throttle1.msg_count.Response_Data::4 969 -system.ruby.network.routers01.throttle1.msg_count.ResponseL2hit_Data::4 16 -system.ruby.network.routers01.throttle1.msg_count.ResponseLocal_Data::4 90 -system.ruby.network.routers01.throttle1.msg_count.Response_Control::4 93 -system.ruby.network.routers01.throttle1.msg_count.Writeback_Data::4 81506 -system.ruby.network.routers01.throttle1.msg_count.Broadcast_Control::1 78342 -system.ruby.network.routers01.throttle1.msg_count.Persistent_Control::3 11468 -system.ruby.network.routers01.throttle1.msg_bytes.Request_Control::1 626736 +system.ruby.network.routers01.throttle1.msg_count.ResponseL2hit_Data::4 6 +system.ruby.network.routers01.throttle1.msg_count.ResponseLocal_Data::4 99 +system.ruby.network.routers01.throttle1.msg_count.Response_Control::4 87 +system.ruby.network.routers01.throttle1.msg_count.Writeback_Data::4 81451 +system.ruby.network.routers01.throttle1.msg_count.Writeback_Control::4 1 +system.ruby.network.routers01.throttle1.msg_count.Broadcast_Control::1 78393 +system.ruby.network.routers01.throttle1.msg_count.Persistent_Control::3 11050 +system.ruby.network.routers01.throttle1.msg_bytes.Request_Control::1 627144 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-system.ruby.network.routers09.throttle1.msg_count.Writeback_Data::4 300 -system.ruby.network.routers09.throttle1.msg_bytes.Response_Data::4 44779536 -system.ruby.network.routers09.throttle1.msg_bytes.Response_Control::4 8 -system.ruby.network.routers09.throttle1.msg_bytes.Writeback_Data::4 21600 -system.ruby.network.routers10.throttle0.link_utilization 11.630830 -system.ruby.network.routers10.throttle0.msg_count.Response_Data::4 79274 -system.ruby.network.routers10.throttle0.msg_count.ResponseL2hit_Data::4 233 -system.ruby.network.routers10.throttle0.msg_count.ResponseLocal_Data::4 95 -system.ruby.network.routers10.throttle0.msg_count.Response_Control::4 1 -system.ruby.network.routers10.throttle0.msg_count.Writeback_Data::4 3327 -system.ruby.network.routers10.throttle0.msg_count.Broadcast_Control::1 547327 -system.ruby.network.routers10.throttle0.msg_count.Persistent_Control::3 79528 -system.ruby.network.routers10.throttle0.msg_bytes.Response_Data::4 5707728 -system.ruby.network.routers10.throttle0.msg_bytes.ResponseL2hit_Data::4 16776 -system.ruby.network.routers10.throttle0.msg_bytes.ResponseLocal_Data::4 6840 -system.ruby.network.routers10.throttle0.msg_bytes.Response_Control::4 8 -system.ruby.network.routers10.throttle0.msg_bytes.Writeback_Data::4 239544 -system.ruby.network.routers10.throttle0.msg_bytes.Broadcast_Control::1 4378616 -system.ruby.network.routers10.throttle0.msg_bytes.Persistent_Control::3 636224 -system.ruby.network.routers10.throttle1.link_utilization 11.602973 -system.ruby.network.routers10.throttle1.msg_count.Response_Data::4 78882 -system.ruby.network.routers10.throttle1.msg_count.ResponseL2hit_Data::4 231 -system.ruby.network.routers10.throttle1.msg_count.ResponseLocal_Data::4 99 -system.ruby.network.routers10.throttle1.msg_count.Writeback_Data::4 3306 -system.ruby.network.routers10.throttle1.msg_count.Broadcast_Control::1 547765 -system.ruby.network.routers10.throttle1.msg_count.Persistent_Control::3 79508 -system.ruby.network.routers10.throttle1.msg_bytes.Response_Data::4 5679504 -system.ruby.network.routers10.throttle1.msg_bytes.ResponseL2hit_Data::4 16632 -system.ruby.network.routers10.throttle1.msg_bytes.ResponseLocal_Data::4 7128 -system.ruby.network.routers10.throttle1.msg_bytes.Writeback_Data::4 238032 -system.ruby.network.routers10.throttle1.msg_bytes.Broadcast_Control::1 4382120 -system.ruby.network.routers10.throttle1.msg_bytes.Persistent_Control::3 636064 -system.ruby.network.routers10.throttle2.link_utilization 11.610240 -system.ruby.network.routers10.throttle2.msg_count.Response_Data::4 79034 -system.ruby.network.routers10.throttle2.msg_count.ResponseL2hit_Data::4 225 -system.ruby.network.routers10.throttle2.msg_count.ResponseLocal_Data::4 89 -system.ruby.network.routers10.throttle2.msg_count.Writeback_Data::4 3281 -system.ruby.network.routers10.throttle2.msg_count.Broadcast_Control::1 547677 -system.ruby.network.routers10.throttle2.msg_count.Persistent_Control::3 79448 -system.ruby.network.routers10.throttle2.msg_bytes.Response_Data::4 5690448 -system.ruby.network.routers10.throttle2.msg_bytes.ResponseL2hit_Data::4 16200 -system.ruby.network.routers10.throttle2.msg_bytes.ResponseLocal_Data::4 6408 -system.ruby.network.routers10.throttle2.msg_bytes.Writeback_Data::4 236232 -system.ruby.network.routers10.throttle2.msg_bytes.Broadcast_Control::1 4381416 -system.ruby.network.routers10.throttle2.msg_bytes.Persistent_Control::3 635584 -system.ruby.network.routers10.throttle3.link_utilization 11.592538 -system.ruby.network.routers10.throttle3.msg_count.Response_Data::4 78824 -system.ruby.network.routers10.throttle3.msg_count.ResponseL2hit_Data::4 200 -system.ruby.network.routers10.throttle3.msg_count.ResponseLocal_Data::4 76 +system.ruby.network.routers09.throttle0.msg_bytes.Writeback_Data::4 17004528 +system.ruby.network.routers09.throttle0.msg_bytes.Writeback_Control::4 3044504 +system.ruby.network.routers09.throttle0.msg_bytes.Persistent_Control::3 707648 +system.ruby.network.routers09.throttle1.link_utilization 47.688336 +system.ruby.network.routers09.throttle1.msg_count.Response_Data::4 622925 +system.ruby.network.routers09.throttle1.msg_count.Response_Control::4 2 +system.ruby.network.routers09.throttle1.msg_count.Writeback_Data::4 316 +system.ruby.network.routers09.throttle1.msg_count.Writeback_Control::4 2 +system.ruby.network.routers09.throttle1.msg_bytes.Response_Data::4 44850600 +system.ruby.network.routers09.throttle1.msg_bytes.Response_Control::4 16 +system.ruby.network.routers09.throttle1.msg_bytes.Writeback_Data::4 22752 +system.ruby.network.routers09.throttle1.msg_bytes.Writeback_Control::4 16 +system.ruby.network.routers10.throttle0.link_utilization 11.660758 +system.ruby.network.routers10.throttle0.msg_count.Response_Data::4 79304 +system.ruby.network.routers10.throttle0.msg_count.ResponseL2hit_Data::4 218 +system.ruby.network.routers10.throttle0.msg_count.ResponseLocal_Data::4 108 +system.ruby.network.routers10.throttle0.msg_count.Response_Control::4 2 +system.ruby.network.routers10.throttle0.msg_count.Writeback_Data::4 3264 +system.ruby.network.routers10.throttle0.msg_count.Broadcast_Control::1 548338 +system.ruby.network.routers10.throttle0.msg_count.Persistent_Control::3 77168 +system.ruby.network.routers10.throttle0.msg_bytes.Response_Data::4 5709888 +system.ruby.network.routers10.throttle0.msg_bytes.ResponseL2hit_Data::4 15696 +system.ruby.network.routers10.throttle0.msg_bytes.ResponseLocal_Data::4 7776 +system.ruby.network.routers10.throttle0.msg_bytes.Response_Control::4 16 +system.ruby.network.routers10.throttle0.msg_bytes.Writeback_Data::4 235008 +system.ruby.network.routers10.throttle0.msg_bytes.Broadcast_Control::1 4386704 +system.ruby.network.routers10.throttle0.msg_bytes.Persistent_Control::3 617344 +system.ruby.network.routers10.throttle1.link_utilization 11.631988 +system.ruby.network.routers10.throttle1.msg_count.Response_Data::4 78946 +system.ruby.network.routers10.throttle1.msg_count.ResponseL2hit_Data::4 242 +system.ruby.network.routers10.throttle1.msg_count.ResponseLocal_Data::4 74 +system.ruby.network.routers10.throttle1.msg_count.Response_Control::4 1 +system.ruby.network.routers10.throttle1.msg_count.Writeback_Data::4 3190 +system.ruby.network.routers10.throttle1.msg_count.Writeback_Control::4 1 +system.ruby.network.routers10.throttle1.msg_count.Broadcast_Control::1 548694 +system.ruby.network.routers10.throttle1.msg_count.Persistent_Control::3 77406 +system.ruby.network.routers10.throttle1.msg_bytes.Response_Data::4 5684112 +system.ruby.network.routers10.throttle1.msg_bytes.ResponseL2hit_Data::4 17424 +system.ruby.network.routers10.throttle1.msg_bytes.ResponseLocal_Data::4 5328 +system.ruby.network.routers10.throttle1.msg_bytes.Response_Control::4 8 +system.ruby.network.routers10.throttle1.msg_bytes.Writeback_Data::4 229680 +system.ruby.network.routers10.throttle1.msg_bytes.Writeback_Control::4 8 +system.ruby.network.routers10.throttle1.msg_bytes.Broadcast_Control::1 4389552 +system.ruby.network.routers10.throttle1.msg_bytes.Persistent_Control::3 619248 +system.ruby.network.routers10.throttle2.link_utilization 11.647368 +system.ruby.network.routers10.throttle2.msg_count.Response_Data::4 79112 +system.ruby.network.routers10.throttle2.msg_count.ResponseL2hit_Data::4 252 +system.ruby.network.routers10.throttle2.msg_count.ResponseLocal_Data::4 80 +system.ruby.network.routers10.throttle2.msg_count.Response_Control::4 1 +system.ruby.network.routers10.throttle2.msg_count.Writeback_Data::4 3236 +system.ruby.network.routers10.throttle2.msg_count.Writeback_Control::4 1 +system.ruby.network.routers10.throttle2.msg_count.Broadcast_Control::1 548543 +system.ruby.network.routers10.throttle2.msg_count.Persistent_Control::3 77314 +system.ruby.network.routers10.throttle2.msg_bytes.Response_Data::4 5696064 +system.ruby.network.routers10.throttle2.msg_bytes.ResponseL2hit_Data::4 18144 +system.ruby.network.routers10.throttle2.msg_bytes.ResponseLocal_Data::4 5760 +system.ruby.network.routers10.throttle2.msg_bytes.Response_Control::4 8 +system.ruby.network.routers10.throttle2.msg_bytes.Writeback_Data::4 232992 +system.ruby.network.routers10.throttle2.msg_bytes.Writeback_Control::4 8 +system.ruby.network.routers10.throttle2.msg_bytes.Broadcast_Control::1 4388344 +system.ruby.network.routers10.throttle2.msg_bytes.Persistent_Control::3 618512 +system.ruby.network.routers10.throttle3.link_utilization 11.608795 +system.ruby.network.routers10.throttle3.msg_count.Response_Data::4 78622 +system.ruby.network.routers10.throttle3.msg_count.ResponseL2hit_Data::4 241 +system.ruby.network.routers10.throttle3.msg_count.ResponseLocal_Data::4 92 system.ruby.network.routers10.throttle3.msg_count.Response_Control::4 1 -system.ruby.network.routers10.throttle3.msg_count.Writeback_Data::4 3248 -system.ruby.network.routers10.throttle3.msg_count.Broadcast_Control::1 547851 -system.ruby.network.routers10.throttle3.msg_count.Persistent_Control::3 79712 -system.ruby.network.routers10.throttle3.msg_bytes.Response_Data::4 5675328 -system.ruby.network.routers10.throttle3.msg_bytes.ResponseL2hit_Data::4 14400 -system.ruby.network.routers10.throttle3.msg_bytes.ResponseLocal_Data::4 5472 +system.ruby.network.routers10.throttle3.msg_count.Writeback_Data::4 3152 +system.ruby.network.routers10.throttle3.msg_count.Broadcast_Control::1 549022 +system.ruby.network.routers10.throttle3.msg_count.Persistent_Control::3 77456 +system.ruby.network.routers10.throttle3.msg_bytes.Response_Data::4 5660784 +system.ruby.network.routers10.throttle3.msg_bytes.ResponseL2hit_Data::4 17352 +system.ruby.network.routers10.throttle3.msg_bytes.ResponseLocal_Data::4 6624 system.ruby.network.routers10.throttle3.msg_bytes.Response_Control::4 8 -system.ruby.network.routers10.throttle3.msg_bytes.Writeback_Data::4 233856 -system.ruby.network.routers10.throttle3.msg_bytes.Broadcast_Control::1 4382808 -system.ruby.network.routers10.throttle3.msg_bytes.Persistent_Control::3 637696 -system.ruby.network.routers10.throttle4.link_utilization 11.571152 -system.ruby.network.routers10.throttle4.msg_count.Response_Data::4 78435 -system.ruby.network.routers10.throttle4.msg_count.ResponseL2hit_Data::4 234 -system.ruby.network.routers10.throttle4.msg_count.ResponseLocal_Data::4 86 +system.ruby.network.routers10.throttle3.msg_bytes.Writeback_Data::4 226944 +system.ruby.network.routers10.throttle3.msg_bytes.Broadcast_Control::1 4392176 +system.ruby.network.routers10.throttle3.msg_bytes.Persistent_Control::3 619648 +system.ruby.network.routers10.throttle4.link_utilization 11.628094 +system.ruby.network.routers10.throttle4.msg_count.Response_Data::4 78811 +system.ruby.network.routers10.throttle4.msg_count.ResponseL2hit_Data::4 236 +system.ruby.network.routers10.throttle4.msg_count.ResponseLocal_Data::4 108 system.ruby.network.routers10.throttle4.msg_count.Response_Control::4 1 -system.ruby.network.routers10.throttle4.msg_count.Writeback_Data::4 3281 -system.ruby.network.routers10.throttle4.msg_count.Broadcast_Control::1 548180 -system.ruby.network.routers10.throttle4.msg_count.Persistent_Control::3 79666 -system.ruby.network.routers10.throttle4.msg_bytes.Response_Data::4 5647320 -system.ruby.network.routers10.throttle4.msg_bytes.ResponseL2hit_Data::4 16848 -system.ruby.network.routers10.throttle4.msg_bytes.ResponseLocal_Data::4 6192 +system.ruby.network.routers10.throttle4.msg_count.Writeback_Data::4 3240 +system.ruby.network.routers10.throttle4.msg_count.Broadcast_Control::1 548850 +system.ruby.network.routers10.throttle4.msg_count.Persistent_Control::3 77306 +system.ruby.network.routers10.throttle4.msg_bytes.Response_Data::4 5674392 +system.ruby.network.routers10.throttle4.msg_bytes.ResponseL2hit_Data::4 16992 +system.ruby.network.routers10.throttle4.msg_bytes.ResponseLocal_Data::4 7776 system.ruby.network.routers10.throttle4.msg_bytes.Response_Control::4 8 -system.ruby.network.routers10.throttle4.msg_bytes.Writeback_Data::4 236232 -system.ruby.network.routers10.throttle4.msg_bytes.Broadcast_Control::1 4385440 -system.ruby.network.routers10.throttle4.msg_bytes.Persistent_Control::3 637328 -system.ruby.network.routers10.throttle5.link_utilization 11.607953 -system.ruby.network.routers10.throttle5.msg_count.Response_Data::4 78930 -system.ruby.network.routers10.throttle5.msg_count.ResponseL2hit_Data::4 217 -system.ruby.network.routers10.throttle5.msg_count.ResponseLocal_Data::4 90 -system.ruby.network.routers10.throttle5.msg_count.Response_Control::4 3 -system.ruby.network.routers10.throttle5.msg_count.Writeback_Data::4 3336 -system.ruby.network.routers10.throttle5.msg_count.Broadcast_Control::1 547664 -system.ruby.network.routers10.throttle5.msg_count.Persistent_Control::3 79692 -system.ruby.network.routers10.throttle5.msg_bytes.Response_Data::4 5682960 -system.ruby.network.routers10.throttle5.msg_bytes.ResponseL2hit_Data::4 15624 -system.ruby.network.routers10.throttle5.msg_bytes.ResponseLocal_Data::4 6480 -system.ruby.network.routers10.throttle5.msg_bytes.Response_Control::4 24 -system.ruby.network.routers10.throttle5.msg_bytes.Writeback_Data::4 240192 -system.ruby.network.routers10.throttle5.msg_bytes.Broadcast_Control::1 4381312 -system.ruby.network.routers10.throttle5.msg_bytes.Persistent_Control::3 637536 -system.ruby.network.routers10.throttle6.link_utilization 11.576488 -system.ruby.network.routers10.throttle6.msg_count.Response_Data::4 78457 -system.ruby.network.routers10.throttle6.msg_count.ResponseL2hit_Data::4 216 -system.ruby.network.routers10.throttle6.msg_count.ResponseLocal_Data::4 92 -system.ruby.network.routers10.throttle6.msg_count.Response_Control::4 2 -system.ruby.network.routers10.throttle6.msg_count.Writeback_Data::4 3351 -system.ruby.network.routers10.throttle6.msg_count.Broadcast_Control::1 548131 -system.ruby.network.routers10.throttle6.msg_count.Persistent_Control::3 79624 -system.ruby.network.routers10.throttle6.msg_bytes.Response_Data::4 5648904 -system.ruby.network.routers10.throttle6.msg_bytes.ResponseL2hit_Data::4 15552 -system.ruby.network.routers10.throttle6.msg_bytes.ResponseLocal_Data::4 6624 -system.ruby.network.routers10.throttle6.msg_bytes.Response_Control::4 16 -system.ruby.network.routers10.throttle6.msg_bytes.Writeback_Data::4 241272 -system.ruby.network.routers10.throttle6.msg_bytes.Broadcast_Control::1 4385048 -system.ruby.network.routers10.throttle6.msg_bytes.Persistent_Control::3 636992 -system.ruby.network.routers10.throttle7.link_utilization 11.576014 -system.ruby.network.routers10.throttle7.msg_count.Response_Data::4 78439 -system.ruby.network.routers10.throttle7.msg_count.ResponseL2hit_Data::4 228 -system.ruby.network.routers10.throttle7.msg_count.ResponseLocal_Data::4 105 -system.ruby.network.routers10.throttle7.msg_count.Response_Control::4 1 -system.ruby.network.routers10.throttle7.msg_count.Writeback_Data::4 3332 -system.ruby.network.routers10.throttle7.msg_count.Broadcast_Control::1 548154 -system.ruby.network.routers10.throttle7.msg_count.Persistent_Control::3 79654 -system.ruby.network.routers10.throttle7.msg_bytes.Response_Data::4 5647608 -system.ruby.network.routers10.throttle7.msg_bytes.ResponseL2hit_Data::4 16416 -system.ruby.network.routers10.throttle7.msg_bytes.ResponseLocal_Data::4 7560 -system.ruby.network.routers10.throttle7.msg_bytes.Response_Control::4 8 -system.ruby.network.routers10.throttle7.msg_bytes.Writeback_Data::4 239904 -system.ruby.network.routers10.throttle7.msg_bytes.Broadcast_Control::1 4385232 -system.ruby.network.routers10.throttle7.msg_bytes.Persistent_Control::3 637232 -system.ruby.network.routers10.throttle8.link_utilization 53.749905 -system.ruby.network.routers10.throttle8.msg_count.Request_Control::1 626105 -system.ruby.network.routers10.throttle8.msg_count.Response_Control::4 710 -system.ruby.network.routers10.throttle8.msg_count.Writeback_Data::4 625367 -system.ruby.network.routers10.throttle8.msg_count.Persistent_Control::3 90976 -system.ruby.network.routers10.throttle8.msg_bytes.Request_Control::1 5008840 -system.ruby.network.routers10.throttle8.msg_bytes.Response_Control::4 5680 -system.ruby.network.routers10.throttle8.msg_bytes.Writeback_Data::4 45026424 -system.ruby.network.routers10.throttle8.msg_bytes.Persistent_Control::3 727808 -system.ruby.network.routers10.throttle9.link_utilization 27.857899 -system.ruby.network.routers10.throttle9.msg_count.Request_Control::2 624315 -system.ruby.network.routers10.throttle9.msg_count.Response_Data::4 6959 -system.ruby.network.routers10.throttle9.msg_count.ResponseL2hit_Data::4 80 +system.ruby.network.routers10.throttle4.msg_bytes.Writeback_Data::4 233280 +system.ruby.network.routers10.throttle4.msg_bytes.Broadcast_Control::1 4390800 +system.ruby.network.routers10.throttle4.msg_bytes.Persistent_Control::3 618448 +system.ruby.network.routers10.throttle5.link_utilization 11.630891 +system.ruby.network.routers10.throttle5.msg_count.Response_Data::4 78893 +system.ruby.network.routers10.throttle5.msg_count.ResponseL2hit_Data::4 219 +system.ruby.network.routers10.throttle5.msg_count.ResponseLocal_Data::4 83 +system.ruby.network.routers10.throttle5.msg_count.Response_Control::4 1 +system.ruby.network.routers10.throttle5.msg_count.Writeback_Data::4 3249 +system.ruby.network.routers10.throttle5.msg_count.Broadcast_Control::1 548736 +system.ruby.network.routers10.throttle5.msg_count.Persistent_Control::3 77308 +system.ruby.network.routers10.throttle5.msg_bytes.Response_Data::4 5680296 +system.ruby.network.routers10.throttle5.msg_bytes.ResponseL2hit_Data::4 15768 +system.ruby.network.routers10.throttle5.msg_bytes.ResponseLocal_Data::4 5976 +system.ruby.network.routers10.throttle5.msg_bytes.Response_Control::4 8 +system.ruby.network.routers10.throttle5.msg_bytes.Writeback_Data::4 233928 +system.ruby.network.routers10.throttle5.msg_bytes.Broadcast_Control::1 4389888 +system.ruby.network.routers10.throttle5.msg_bytes.Persistent_Control::3 618464 +system.ruby.network.routers10.throttle6.link_utilization 11.639597 +system.ruby.network.routers10.throttle6.msg_count.Response_Data::4 79044 +system.ruby.network.routers10.throttle6.msg_count.ResponseL2hit_Data::4 226 +system.ruby.network.routers10.throttle6.msg_count.ResponseLocal_Data::4 91 +system.ruby.network.routers10.throttle6.msg_count.Response_Control::4 1 +system.ruby.network.routers10.throttle6.msg_count.Writeback_Data::4 3175 +system.ruby.network.routers10.throttle6.msg_count.Broadcast_Control::1 548616 +system.ruby.network.routers10.throttle6.msg_count.Persistent_Control::3 77624 +system.ruby.network.routers10.throttle6.msg_bytes.Response_Data::4 5691168 +system.ruby.network.routers10.throttle6.msg_bytes.ResponseL2hit_Data::4 16272 +system.ruby.network.routers10.throttle6.msg_bytes.ResponseLocal_Data::4 6552 +system.ruby.network.routers10.throttle6.msg_bytes.Response_Control::4 8 +system.ruby.network.routers10.throttle6.msg_bytes.Writeback_Data::4 228600 +system.ruby.network.routers10.throttle6.msg_bytes.Broadcast_Control::1 4388928 +system.ruby.network.routers10.throttle6.msg_bytes.Persistent_Control::3 620992 +system.ruby.network.routers10.throttle7.link_utilization 11.625688 +system.ruby.network.routers10.throttle7.msg_count.Response_Data::4 78848 +system.ruby.network.routers10.throttle7.msg_count.ResponseL2hit_Data::4 215 +system.ruby.network.routers10.throttle7.msg_count.ResponseLocal_Data::4 98 +system.ruby.network.routers10.throttle7.msg_count.Response_Control::4 3 +system.ruby.network.routers10.throttle7.msg_count.Writeback_Data::4 3173 +system.ruby.network.routers10.throttle7.msg_count.Broadcast_Control::1 548810 +system.ruby.network.routers10.throttle7.msg_count.Persistent_Control::3 77610 +system.ruby.network.routers10.throttle7.msg_bytes.Response_Data::4 5677056 +system.ruby.network.routers10.throttle7.msg_bytes.ResponseL2hit_Data::4 15480 +system.ruby.network.routers10.throttle7.msg_bytes.ResponseLocal_Data::4 7056 +system.ruby.network.routers10.throttle7.msg_bytes.Response_Control::4 24 +system.ruby.network.routers10.throttle7.msg_bytes.Writeback_Data::4 228456 +system.ruby.network.routers10.throttle7.msg_bytes.Broadcast_Control::1 4390480 +system.ruby.network.routers10.throttle7.msg_bytes.Persistent_Control::3 620880 +system.ruby.network.routers10.throttle8.link_utilization 54.018361 +system.ruby.network.routers10.throttle8.msg_count.Request_Control::1 627087 +system.ruby.network.routers10.throttle8.msg_count.Response_Control::4 668 +system.ruby.network.routers10.throttle8.msg_count.Writeback_Data::4 626389 +system.ruby.network.routers10.throttle8.msg_count.Persistent_Control::3 88456 +system.ruby.network.routers10.throttle8.msg_bytes.Request_Control::1 5016696 +system.ruby.network.routers10.throttle8.msg_bytes.Response_Control::4 5344 +system.ruby.network.routers10.throttle8.msg_bytes.Writeback_Data::4 45100008 +system.ruby.network.routers10.throttle8.msg_bytes.Persistent_Control::3 707648 +system.ruby.network.routers10.throttle9.link_utilization 27.943416 +system.ruby.network.routers10.throttle9.msg_count.Request_Control::2 625240 +system.ruby.network.routers10.throttle9.msg_count.Response_Data::4 7338 +system.ruby.network.routers10.throttle9.msg_count.ResponseL2hit_Data::4 97 system.ruby.network.routers10.throttle9.msg_count.Response_Control::4 2 -system.ruby.network.routers10.throttle9.msg_count.Writeback_Data::4 236789 -system.ruby.network.routers10.throttle9.msg_count.Writeback_Control::4 379353 -system.ruby.network.routers10.throttle9.msg_count.Persistent_Control::3 90976 -system.ruby.network.routers10.throttle9.msg_bytes.Request_Control::2 4994520 -system.ruby.network.routers10.throttle9.msg_bytes.Response_Data::4 501048 -system.ruby.network.routers10.throttle9.msg_bytes.ResponseL2hit_Data::4 5760 +system.ruby.network.routers10.throttle9.msg_count.Writeback_Data::4 236174 +system.ruby.network.routers10.throttle9.msg_count.Writeback_Control::4 380563 +system.ruby.network.routers10.throttle9.msg_count.Persistent_Control::3 88456 +system.ruby.network.routers10.throttle9.msg_bytes.Request_Control::2 5001920 +system.ruby.network.routers10.throttle9.msg_bytes.Response_Data::4 528336 +system.ruby.network.routers10.throttle9.msg_bytes.ResponseL2hit_Data::4 6984 system.ruby.network.routers10.throttle9.msg_bytes.Response_Control::4 16 -system.ruby.network.routers10.throttle9.msg_bytes.Writeback_Data::4 17048808 -system.ruby.network.routers10.throttle9.msg_bytes.Writeback_Control::4 3034824 -system.ruby.network.routers10.throttle9.msg_bytes.Persistent_Control::3 727808 +system.ruby.network.routers10.throttle9.msg_bytes.Writeback_Data::4 17004528 +system.ruby.network.routers10.throttle9.msg_bytes.Writeback_Control::4 3044504 +system.ruby.network.routers10.throttle9.msg_bytes.Persistent_Control::3 707648 system.ruby.LD.latency_hist::bucket_size 512 system.ruby.LD.latency_hist::max_bucket 5119 -system.ruby.LD.latency_hist::samples 403201 -system.ruby.LD.latency_hist::mean 1206.626358 -system.ruby.LD.latency_hist::gmean 905.407177 -system.ruby.LD.latency_hist::stdev 767.970224 -system.ruby.LD.latency_hist | 108278 26.85% 26.85% | 76136 18.88% 45.74% | 71035 17.62% 63.36% | 77557 19.24% 82.59% | 55661 13.80% 96.40% | 13496 3.35% 99.74% | 1015 0.25% 99.99% | 23 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.latency_hist::total 403201 +system.ruby.LD.latency_hist::samples 404123 +system.ruby.LD.latency_hist::mean 1200.999864 +system.ruby.LD.latency_hist::gmean 900.477274 +system.ruby.LD.latency_hist::stdev 765.116325 +system.ruby.LD.latency_hist | 108804 26.92% 26.92% | 76257 18.87% 45.79% | 72846 18.03% 63.82% | 76798 19.00% 82.82% | 55254 13.67% 96.50% | 13218 3.27% 99.77% | 927 0.23% 100.00% | 19 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.latency_hist::total 404123 system.ruby.LD.hit_latency_hist::bucket_size 512 system.ruby.LD.hit_latency_hist::max_bucket 5119 -system.ruby.LD.hit_latency_hist::samples 1791 -system.ruby.LD.hit_latency_hist::mean 1104.213289 -system.ruby.LD.hit_latency_hist::gmean 581.141844 -system.ruby.LD.hit_latency_hist::stdev 800.023547 -system.ruby.LD.hit_latency_hist | 581 32.44% 32.44% | 303 16.92% 49.36% | 306 17.09% 66.44% | 322 17.98% 84.42% | 222 12.40% 96.82% | 55 3.07% 99.89% | 2 0.11% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.hit_latency_hist::total 1791 +system.ruby.LD.hit_latency_hist::samples 1804 +system.ruby.LD.hit_latency_hist::mean 1046.163525 +system.ruby.LD.hit_latency_hist::gmean 506.824473 +system.ruby.LD.hit_latency_hist::stdev 796.666251 +system.ruby.LD.hit_latency_hist | 637 35.31% 35.31% | 327 18.13% 53.44% | 292 16.19% 69.62% | 287 15.91% 85.53% | 222 12.31% 97.84% | 33 1.83% 99.67% | 6 0.33% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 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3.28% 99.77% | 921 0.23% 100.00% | 19 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.miss_latency_hist::total 402319 system.ruby.ST.latency_hist::bucket_size 512 system.ruby.ST.latency_hist::max_bucket 5119 -system.ruby.ST.latency_hist::samples 223050 -system.ruby.ST.latency_hist::mean 1206.070267 -system.ruby.ST.latency_hist::gmean 903.551282 -system.ruby.ST.latency_hist::stdev 769.078949 -system.ruby.ST.latency_hist | 60261 27.02% 27.02% | 41944 18.80% 45.82% | 38916 17.45% 63.27% | 42948 19.25% 82.52% | 30981 13.89% 96.41% | 7472 3.35% 99.76% | 514 0.23% 99.99% | 14 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.latency_hist::total 223050 +system.ruby.ST.latency_hist::samples 223128 +system.ruby.ST.latency_hist::mean 1198.069973 +system.ruby.ST.latency_hist::gmean 897.219318 +system.ruby.ST.latency_hist::stdev 764.608926 +system.ruby.ST.latency_hist | 60637 27.18% 27.18% | 41649 18.67% 45.84% | 40180 18.01% 63.85% | 42703 19.14% 82.99% | 30269 13.57% 96.55% | 7174 3.22% 99.77% | 505 0.23% 100.00% | 11 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.latency_hist::total 223128 system.ruby.ST.hit_latency_hist::bucket_size 512 system.ruby.ST.hit_latency_hist::max_bucket 5119 -system.ruby.ST.hit_latency_hist::samples 1016 -system.ruby.ST.hit_latency_hist::mean 1071.599409 -system.ruby.ST.hit_latency_hist::gmean 506.227433 -system.ruby.ST.hit_latency_hist::stdev 810.320737 -system.ruby.ST.hit_latency_hist | 349 34.35% 34.35% | 166 16.34% 50.69% | 175 17.22% 67.91% | 181 17.81% 85.73% | 116 11.42% 97.15% | 26 2.56% 99.70% | 2 0.20% 99.90% | 1 0.10% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.hit_latency_hist::total 1016 +system.ruby.ST.hit_latency_hist::samples 1040 +system.ruby.ST.hit_latency_hist::mean 1076.801923 +system.ruby.ST.hit_latency_hist::gmean 533.335801 +system.ruby.ST.hit_latency_hist::stdev 814.040414 +system.ruby.ST.hit_latency_hist | 346 33.27% 33.27% | 197 18.94% 52.21% | 167 16.06% 68.27% | 178 17.12% 85.38% | 112 10.77% 96.15% | 37 3.56% 99.71% | 2 0.19% 99.90% | 1 0.10% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.hit_latency_hist::total 1040 system.ruby.ST.miss_latency_hist::bucket_size 512 system.ruby.ST.miss_latency_hist::max_bucket 5119 -system.ruby.ST.miss_latency_hist::samples 222034 -system.ruby.ST.miss_latency_hist::mean 1206.685589 -system.ruby.ST.miss_latency_hist::gmean 905.949792 -system.ruby.ST.miss_latency_hist::stdev 768.833014 -system.ruby.ST.miss_latency_hist | 59912 26.98% 26.98% | 41778 18.82% 45.80% | 38741 17.45% 63.25% | 42767 19.26% 82.51% | 30865 13.90% 96.41% | 7446 3.35% 99.76% | 512 0.23% 99.99% | 13 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.miss_latency_hist::total 222034 +system.ruby.ST.miss_latency_hist::samples 222088 +system.ruby.ST.miss_latency_hist::mean 1198.637851 +system.ruby.ST.miss_latency_hist::gmean 899.407401 +system.ruby.ST.miss_latency_hist::stdev 764.326618 +system.ruby.ST.miss_latency_hist | 60291 27.15% 27.15% | 41452 18.66% 45.81% | 40013 18.02% 63.83% | 42525 19.15% 82.98% | 30157 13.58% 96.56% | 7137 3.21% 99.77% | 503 0.23% 100.00% | 10 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.miss_latency_hist::total 222088 system.ruby.L1Cache.hit_mach_latency_hist::bucket_size 1 system.ruby.L1Cache.hit_mach_latency_hist::max_bucket 9 -system.ruby.L1Cache.hit_mach_latency_hist::samples 163 +system.ruby.L1Cache.hit_mach_latency_hist::samples 186 system.ruby.L1Cache.hit_mach_latency_hist::mean 2 system.ruby.L1Cache.hit_mach_latency_hist::gmean 2 -system.ruby.L1Cache.hit_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 163 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache.hit_mach_latency_hist::total 163 +system.ruby.L1Cache.hit_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 186 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache.hit_mach_latency_hist::total 186 system.ruby.L1Cache.miss_mach_latency_hist::bucket_size 512 system.ruby.L1Cache.miss_mach_latency_hist::max_bucket 5119 -system.ruby.L1Cache.miss_mach_latency_hist::samples 1328 -system.ruby.L1Cache.miss_mach_latency_hist::mean 1160.911145 -system.ruby.L1Cache.miss_mach_latency_hist::gmean 748.217806 -system.ruby.L1Cache.miss_mach_latency_hist::stdev 787.446867 -system.ruby.L1Cache.miss_mach_latency_hist | 383 28.84% 28.84% | 234 17.62% 46.46% | 247 18.60% 65.06% | 238 17.92% 82.98% | 181 13.63% 96.61% | 42 3.16% 99.77% | 3 0.23% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache.miss_mach_latency_hist::total 1328 +system.ruby.L1Cache.miss_mach_latency_hist::samples 1293 +system.ruby.L1Cache.miss_mach_latency_hist::mean 1158.235886 +system.ruby.L1Cache.miss_mach_latency_hist::gmean 728.356932 +system.ruby.L1Cache.miss_mach_latency_hist::stdev 802.482863 +system.ruby.L1Cache.miss_mach_latency_hist | 388 30.01% 30.01% | 232 17.94% 47.95% | 204 15.78% 63.73% | 256 19.80% 83.53% | 162 12.53% 96.06% | 48 3.71% 99.77% | 2 0.15% 99.92% | 1 0.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache.miss_mach_latency_hist::total 1293 system.ruby.L2Cache.hit_mach_latency_hist::bucket_size 512 system.ruby.L2Cache.hit_mach_latency_hist::max_bucket 5119 -system.ruby.L2Cache.hit_mach_latency_hist::samples 2644 -system.ruby.L2Cache.hit_mach_latency_hist::mean 1159.631241 -system.ruby.L2Cache.hit_mach_latency_hist::gmean 781.821585 -system.ruby.L2Cache.hit_mach_latency_hist::stdev 779.774726 -system.ruby.L2Cache.hit_mach_latency_hist | 767 29.01% 29.01% | 469 17.74% 46.75% | 481 18.19% 64.94% | 503 19.02% 83.96% | 338 12.78% 96.75% | 81 3.06% 99.81% | 4 0.15% 99.96% | 1 0.04% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L2Cache.hit_mach_latency_hist::total 2644 +system.ruby.L2Cache.hit_mach_latency_hist::samples 2658 +system.ruby.L2Cache.hit_mach_latency_hist::mean 1131.219338 +system.ruby.L2Cache.hit_mach_latency_hist::gmean 761.614557 +system.ruby.L2Cache.hit_mach_latency_hist::stdev 778.856804 +system.ruby.L2Cache.hit_mach_latency_hist | 797 29.98% 29.98% | 524 19.71% 49.70% | 459 17.27% 66.97% | 465 17.49% 84.46% | 334 12.57% 97.03% | 70 2.63% 99.66% | 8 0.30% 99.96% | 1 0.04% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L2Cache.hit_mach_latency_hist::total 2658 system.ruby.Directory.miss_mach_latency_hist::bucket_size 512 system.ruby.Directory.miss_mach_latency_hist::max_bucket 5119 -system.ruby.Directory.miss_mach_latency_hist::samples 622116 -system.ruby.Directory.miss_mach_latency_hist::mean 1207.039919 -system.ruby.Directory.miss_mach_latency_hist::gmean 907.126686 -system.ruby.Directory.miss_mach_latency_hist::stdev 768.120033 -system.ruby.Directory.miss_mach_latency_hist | 167226 26.88% 26.88% | 117377 18.87% 45.75% | 109223 17.56% 63.30% | 119764 19.25% 82.56% | 86123 13.84% 96.40% | 20845 3.35% 99.75% | 1522 0.24% 99.99% | 36 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Directory.miss_mach_latency_hist::total 622116 +system.ruby.Directory.miss_mach_latency_hist::samples 623114 +system.ruby.Directory.miss_mach_latency_hist::mean 1200.695014 +system.ruby.Directory.miss_mach_latency_hist::gmean 901.991783 +system.ruby.Directory.miss_mach_latency_hist::stdev 764.616314 +system.ruby.Directory.miss_mach_latency_hist | 168070 26.97% 26.97% | 117150 18.80% 45.77% | 112363 18.03% 63.81% | 118780 19.06% 82.87% | 85027 13.65% 96.51% | 20274 3.25% 99.77% | 1422 0.23% 100.00% | 28 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_mach_latency_hist::total 623114 system.ruby.Directory.miss_latency_hist.issue_to_initial_request::bucket_size 1 system.ruby.Directory.miss_latency_hist.issue_to_initial_request::max_bucket 9 system.ruby.Directory.miss_latency_hist.issue_to_initial_request::samples 4 @@ -1142,436 +1175,449 @@ system.ruby.Directory.miss_latency_hist.first_response_to_completion | system.ruby.Directory.miss_latency_hist.first_response_to_completion::total 4 system.ruby.LD.L1Cache.hit_type_mach_latency_hist::bucket_size 1 system.ruby.LD.L1Cache.hit_type_mach_latency_hist::max_bucket 9 -system.ruby.LD.L1Cache.hit_type_mach_latency_hist::samples 92 +system.ruby.LD.L1Cache.hit_type_mach_latency_hist::samples 120 system.ruby.LD.L1Cache.hit_type_mach_latency_hist::mean 2 system.ruby.LD.L1Cache.hit_type_mach_latency_hist::gmean 2 -system.ruby.LD.L1Cache.hit_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 92 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.L1Cache.hit_type_mach_latency_hist::total 92 +system.ruby.LD.L1Cache.hit_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 120 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.L1Cache.hit_type_mach_latency_hist::total 120 system.ruby.LD.L1Cache.miss_type_mach_latency_hist::bucket_size 512 system.ruby.LD.L1Cache.miss_type_mach_latency_hist::max_bucket 5119 -system.ruby.LD.L1Cache.miss_type_mach_latency_hist::samples 863 -system.ruby.LD.L1Cache.miss_type_mach_latency_hist::mean 1168.529548 -system.ruby.LD.L1Cache.miss_type_mach_latency_hist::gmean 753.386461 -system.ruby.LD.L1Cache.miss_type_mach_latency_hist::stdev 798.015329 -system.ruby.LD.L1Cache.miss_type_mach_latency_hist | 249 28.85% 28.85% | 159 18.42% 47.28% | 146 16.92% 64.19% | 150 17.38% 81.58% | 132 15.30% 96.87% | 25 2.90% 99.77% | 2 0.23% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.L1Cache.miss_type_mach_latency_hist::total 863 +system.ruby.LD.L1Cache.miss_type_mach_latency_hist::samples 858 +system.ruby.LD.L1Cache.miss_type_mach_latency_hist::mean 1181.020979 +system.ruby.LD.L1Cache.miss_type_mach_latency_hist::gmean 749.467450 +system.ruby.LD.L1Cache.miss_type_mach_latency_hist::stdev 801.452334 +system.ruby.LD.L1Cache.miss_type_mach_latency_hist | 252 29.37% 29.37% | 147 17.13% 46.50% | 133 15.50% 62.00% | 180 20.98% 82.98% | 113 13.17% 96.15% | 32 3.73% 99.88% | 0 0.00% 99.88% | 1 0.12% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.L1Cache.miss_type_mach_latency_hist::total 858 system.ruby.LD.L2Cache.hit_type_mach_latency_hist::bucket_size 512 system.ruby.LD.L2Cache.hit_type_mach_latency_hist::max_bucket 5119 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist::samples 1699 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist::mean 1163.897587 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist::gmean 790.070814 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist::stdev 778.028229 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist | 489 28.78% 28.78% | 303 17.83% 46.62% | 306 18.01% 64.63% | 322 18.95% 83.58% | 222 13.07% 96.65% | 55 3.24% 99.88% | 2 0.12% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.L2Cache.hit_type_mach_latency_hist::total 1699 +system.ruby.LD.L2Cache.hit_type_mach_latency_hist::samples 1684 +system.ruby.LD.L2Cache.hit_type_mach_latency_hist::mean 1120.569477 +system.ruby.LD.L2Cache.hit_type_mach_latency_hist::gmean 751.885491 +system.ruby.LD.L2Cache.hit_type_mach_latency_hist::stdev 772.432979 +system.ruby.LD.L2Cache.hit_type_mach_latency_hist | 517 30.70% 30.70% | 327 19.42% 50.12% | 292 17.34% 67.46% | 287 17.04% 84.50% | 222 13.18% 97.68% | 33 1.96% 99.64% | 6 0.36% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.L2Cache.hit_type_mach_latency_hist::total 1684 system.ruby.LD.Directory.miss_type_mach_latency_hist::bucket_size 512 system.ruby.LD.Directory.miss_type_mach_latency_hist::max_bucket 5119 -system.ruby.LD.Directory.miss_type_mach_latency_hist::samples 400547 -system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 1207.166367 -system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 907.563331 -system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 767.727188 -system.ruby.LD.Directory.miss_type_mach_latency_hist | 107448 26.83% 26.83% | 75674 18.89% 45.72% | 70583 17.62% 63.34% | 77085 19.24% 82.58% | 55307 13.81% 96.39% | 13416 3.35% 99.74% | 1011 0.25% 99.99% | 23 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.Directory.miss_type_mach_latency_hist::total 400547 +system.ruby.LD.Directory.miss_type_mach_latency_hist::samples 401461 +system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 1201.738333 +system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 903.160221 +system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 764.822834 +system.ruby.LD.Directory.miss_type_mach_latency_hist | 107915 26.88% 26.88% | 75783 18.88% 45.76% | 72421 18.04% 63.80% | 76331 19.01% 82.81% | 54919 13.68% 96.49% | 13153 3.28% 99.77% | 921 0.23% 100.00% | 18 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.Directory.miss_type_mach_latency_hist::total 401461 system.ruby.ST.L1Cache.hit_type_mach_latency_hist::bucket_size 1 system.ruby.ST.L1Cache.hit_type_mach_latency_hist::max_bucket 9 -system.ruby.ST.L1Cache.hit_type_mach_latency_hist::samples 71 +system.ruby.ST.L1Cache.hit_type_mach_latency_hist::samples 66 system.ruby.ST.L1Cache.hit_type_mach_latency_hist::mean 2 system.ruby.ST.L1Cache.hit_type_mach_latency_hist::gmean 2 -system.ruby.ST.L1Cache.hit_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 71 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.L1Cache.hit_type_mach_latency_hist::total 71 +system.ruby.ST.L1Cache.hit_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 66 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.L1Cache.hit_type_mach_latency_hist::total 66 system.ruby.ST.L1Cache.miss_type_mach_latency_hist::bucket_size 512 system.ruby.ST.L1Cache.miss_type_mach_latency_hist::max_bucket 5119 -system.ruby.ST.L1Cache.miss_type_mach_latency_hist::samples 465 -system.ruby.ST.L1Cache.miss_type_mach_latency_hist::mean 1146.772043 -system.ruby.ST.L1Cache.miss_type_mach_latency_hist::gmean 738.719018 -system.ruby.ST.L1Cache.miss_type_mach_latency_hist::stdev 768.096494 -system.ruby.ST.L1Cache.miss_type_mach_latency_hist | 134 28.82% 28.82% | 75 16.13% 44.95% | 101 21.72% 66.67% | 88 18.92% 85.59% | 49 10.54% 96.13% | 17 3.66% 99.78% | 1 0.22% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.L1Cache.miss_type_mach_latency_hist::total 465 +system.ruby.ST.L1Cache.miss_type_mach_latency_hist::samples 435 +system.ruby.ST.L1Cache.miss_type_mach_latency_hist::mean 1113.294253 +system.ruby.ST.L1Cache.miss_type_mach_latency_hist::gmean 688.445437 +system.ruby.ST.L1Cache.miss_type_mach_latency_hist::stdev 803.539492 +system.ruby.ST.L1Cache.miss_type_mach_latency_hist | 136 31.26% 31.26% | 85 19.54% 50.80% | 71 16.32% 67.13% | 76 17.47% 84.60% | 49 11.26% 95.86% | 16 3.68% 99.54% | 2 0.46% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.L1Cache.miss_type_mach_latency_hist::total 435 system.ruby.ST.L2Cache.hit_type_mach_latency_hist::bucket_size 512 system.ruby.ST.L2Cache.hit_type_mach_latency_hist::max_bucket 5119 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist::samples 945 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist::mean 1151.960847 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist::gmean 767.206460 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist::stdev 783.259144 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist | 278 29.42% 29.42% | 166 17.57% 46.98% | 175 18.52% 65.50% | 181 19.15% 84.66% | 116 12.28% 96.93% | 26 2.75% 99.68% | 2 0.21% 99.89% | 1 0.11% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.L2Cache.hit_type_mach_latency_hist::total 945 +system.ruby.ST.L2Cache.hit_type_mach_latency_hist::samples 974 +system.ruby.ST.L2Cache.hit_type_mach_latency_hist::mean 1149.632444 +system.ruby.ST.L2Cache.hit_type_mach_latency_hist::gmean 778.733573 +system.ruby.ST.L2Cache.hit_type_mach_latency_hist::stdev 789.900332 +system.ruby.ST.L2Cache.hit_type_mach_latency_hist | 280 28.75% 28.75% | 197 20.23% 48.97% | 167 17.15% 66.12% | 178 18.28% 84.39% | 112 11.50% 95.89% | 37 3.80% 99.69% | 2 0.21% 99.90% | 1 0.10% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.L2Cache.hit_type_mach_latency_hist::total 974 system.ruby.ST.Directory.miss_type_mach_latency_hist::bucket_size 512 system.ruby.ST.Directory.miss_type_mach_latency_hist::max_bucket 5119 -system.ruby.ST.Directory.miss_type_mach_latency_hist::samples 221569 -system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 1206.811327 -system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 906.337864 -system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 768.831381 -system.ruby.ST.Directory.miss_type_mach_latency_hist | 59778 26.98% 26.98% | 41703 18.82% 45.80% | 38640 17.44% 63.24% | 42679 19.26% 82.50% | 30816 13.91% 96.41% | 7429 3.35% 99.76% | 511 0.23% 99.99% | 13 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.Directory.miss_type_mach_latency_hist::total 221569 -system.ruby.L1Cache_Controller.Load | 50436 12.51% 12.51% | 50559 12.54% 25.05% | 50756 12.59% 37.64% | 50222 12.46% 50.09% | 50228 12.46% 62.55% | 50377 12.49% 75.04% | 50328 12.48% 87.52% | 50307 12.48% 100.00% -system.ruby.L1Cache_Controller.Load::total 403213 -system.ruby.L1Cache_Controller.Store | 28373 12.72% 12.72% | 27805 12.47% 25.19% | 27689 12.41% 37.60% | 28057 12.58% 50.18% | 27716 12.43% 62.60% | 28088 12.59% 75.19% | 27665 12.40% 87.60% | 27666 12.40% 100.00% -system.ruby.L1Cache_Controller.Store::total 223059 -system.ruby.L1Cache_Controller.L1_Replacement | 1481354 12.58% 12.58% | 1470664 12.49% 25.07% | 1475652 12.53% 37.60% | 1470559 12.49% 50.09% | 1467129 12.46% 62.55% | 1474661 12.52% 75.08% | 1468637 12.47% 87.55% | 1465817 12.45% 100.00% -system.ruby.L1Cache_Controller.L1_Replacement::total 11774473 -system.ruby.L1Cache_Controller.Data_Shared | 208 13.68% 13.68% | 189 12.43% 26.10% | 189 12.43% 38.53% | 157 10.32% 48.85% | 185 12.16% 61.01% | 194 12.75% 73.77% | 182 11.97% 85.73% | 217 14.27% 100.00% -system.ruby.L1Cache_Controller.Data_Shared::total 1521 -system.ruby.L1Cache_Controller.Data_Owner | 41 13.58% 13.58% | 38 12.58% 26.16% | 45 14.90% 41.06% | 30 9.93% 50.99% | 35 11.59% 62.58% | 31 10.26% 72.85% | 25 8.28% 81.13% | 57 18.87% 100.00% -system.ruby.L1Cache_Controller.Data_Owner::total 302 -system.ruby.L1Cache_Controller.Data_All_Tokens | 82680 12.58% 12.58% | 82290 12.52% 25.09% | 82395 12.53% 37.63% | 82161 12.50% 50.12% | 81816 12.44% 62.57% | 82348 12.53% 75.09% | 81909 12.46% 87.55% | 81830 12.45% 100.00% -system.ruby.L1Cache_Controller.Data_All_Tokens::total 657429 -system.ruby.L1Cache_Controller.Ack | 1 11.11% 11.11% | 0 0.00% 11.11% | 0 0.00% 11.11% | 1 11.11% 22.22% | 1 11.11% 33.33% | 3 33.33% 66.67% | 2 22.22% 88.89% | 1 11.11% 100.00% -system.ruby.L1Cache_Controller.Ack::total 9 -system.ruby.L1Cache_Controller.Transient_Local_GETX | 194624 12.47% 12.47% | 195190 12.50% 24.97% | 195307 12.51% 37.49% | 194941 12.49% 49.97% | 195278 12.51% 62.49% | 194913 12.49% 74.97% | 195327 12.51% 87.49% | 195329 12.51% 100.00% -system.ruby.L1Cache_Controller.Transient_Local_GETX::total 1560909 -system.ruby.L1Cache_Controller.Transient_Local_GETS | 352702 12.50% 12.50% | 352574 12.49% 24.99% | 352370 12.49% 37.48% | 352910 12.51% 49.99% | 352902 12.51% 62.49% | 352750 12.50% 74.99% | 352804 12.50% 87.50% | 352825 12.50% 100.00% -system.ruby.L1Cache_Controller.Transient_Local_GETS::total 2821837 -system.ruby.L1Cache_Controller.Transient_Local_GETS_Last_Token | 1 33.33% 33.33% | 1 33.33% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 1 33.33% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.Transient_Local_GETS_Last_Token::total 3 -system.ruby.L1Cache_Controller.Persistent_GETX | 14113 12.48% 12.48% | 14154 12.51% 24.99% | 14109 12.47% 37.46% | 14130 12.49% 49.95% | 14118 12.48% 62.43% | 14160 12.52% 74.95% | 14203 12.56% 87.51% | 14134 12.49% 100.00% -system.ruby.L1Cache_Controller.Persistent_GETX::total 113121 -system.ruby.L1Cache_Controller.Persistent_GETS | 25808 12.49% 12.49% | 25766 12.47% 24.95% | 25783 12.47% 37.42% | 25890 12.53% 49.95% | 25893 12.53% 62.48% | 25876 12.52% 74.99% | 25799 12.48% 87.48% | 25889 12.52% 100.00% -system.ruby.L1Cache_Controller.Persistent_GETS::total 206704 -system.ruby.L1Cache_Controller.Persistent_GETS_Last_Token | 2 50.00% 50.00% | 0 0.00% 50.00% | 1 25.00% 75.00% | 0 0.00% 75.00% | 0 0.00% 75.00% | 0 0.00% 75.00% | 1 25.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.Directory.miss_type_mach_latency_hist::samples 221653 +system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 1198.805340 +system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 899.879339 +system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 764.240219 +system.ruby.ST.Directory.miss_type_mach_latency_hist | 60155 27.14% 27.14% | 41367 18.66% 45.80% | 39942 18.02% 63.82% | 42449 19.15% 82.97% | 30108 13.58% 96.56% | 7121 3.21% 99.77% | 501 0.23% 100.00% | 10 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.Directory.miss_type_mach_latency_hist::total 221653 +system.ruby.Directory_Controller.GETX 237437 0.00% 0.00% +system.ruby.Directory_Controller.GETS 430203 0.00% 0.00% +system.ruby.Directory_Controller.Lockdown 44403 0.00% 0.00% +system.ruby.Directory_Controller.Unlockdown 44053 0.00% 0.00% +system.ruby.Directory_Controller.Data_Owner 298 0.00% 0.00% +system.ruby.Directory_Controller.Data_All_Tokens 243274 0.00% 0.00% +system.ruby.Directory_Controller.Ack_Owner 529 0.00% 0.00% +system.ruby.Directory_Controller.Ack_Owner_All_Tokens 379211 0.00% 0.00% +system.ruby.Directory_Controller.Tokens 147 0.00% 0.00% +system.ruby.Directory_Controller.Ack_All_Tokens 777 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Data 622922 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Ack 243159 0.00% 0.00% +system.ruby.Directory_Controller.O.GETX 220129 0.00% 0.00% +system.ruby.Directory_Controller.O.GETS 398579 0.00% 0.00% +system.ruby.Directory_Controller.O.Lockdown 3733 0.00% 0.00% +system.ruby.Directory_Controller.O.Data_All_Tokens 60 0.00% 0.00% +system.ruby.Directory_Controller.O.Tokens 5 0.00% 0.00% +system.ruby.Directory_Controller.O.Ack_All_Tokens 747 0.00% 0.00% +system.ruby.Directory_Controller.NO.GETX 2154 0.00% 0.00% +system.ruby.Directory_Controller.NO.GETS 4044 0.00% 0.00% +system.ruby.Directory_Controller.NO.Lockdown 17540 0.00% 0.00% +system.ruby.Directory_Controller.NO.Data_Owner 298 0.00% 0.00% +system.ruby.Directory_Controller.NO.Data_All_Tokens 242862 0.00% 0.00% +system.ruby.Directory_Controller.NO.Ack_Owner 529 0.00% 0.00% +system.ruby.Directory_Controller.NO.Ack_Owner_All_Tokens 378819 0.00% 0.00% +system.ruby.Directory_Controller.NO.Tokens 139 0.00% 0.00% +system.ruby.Directory_Controller.L.GETX 127 0.00% 0.00% +system.ruby.Directory_Controller.L.GETS 205 0.00% 0.00% +system.ruby.Directory_Controller.L.Lockdown 318 0.00% 0.00% +system.ruby.Directory_Controller.L.Unlockdown 44051 0.00% 0.00% +system.ruby.Directory_Controller.L.Data_All_Tokens 321 0.00% 0.00% +system.ruby.Directory_Controller.L.Ack_Owner_All_Tokens 392 0.00% 0.00% +system.ruby.Directory_Controller.L.Tokens 2 0.00% 0.00% +system.ruby.Directory_Controller.O_W.GETX 72 0.00% 0.00% +system.ruby.Directory_Controller.O_W.GETS 89 0.00% 0.00% +system.ruby.Directory_Controller.O_W.Lockdown 106 0.00% 0.00% +system.ruby.Directory_Controller.O_W.Data_All_Tokens 31 0.00% 0.00% +system.ruby.Directory_Controller.O_W.Tokens 1 0.00% 0.00% +system.ruby.Directory_Controller.O_W.Memory_Data 2 0.00% 0.00% +system.ruby.Directory_Controller.O_W.Memory_Ack 243053 0.00% 0.00% +system.ruby.Directory_Controller.L_O_W.GETX 48 0.00% 0.00% +system.ruby.Directory_Controller.L_O_W.GETS 63 0.00% 0.00% +system.ruby.Directory_Controller.L_O_W.Lockdown 4 0.00% 0.00% +system.ruby.Directory_Controller.L_O_W.Unlockdown 2 0.00% 0.00% +system.ruby.Directory_Controller.L_O_W.Ack_All_Tokens 15 0.00% 0.00% +system.ruby.Directory_Controller.L_O_W.Memory_Data 4229 0.00% 0.00% +system.ruby.Directory_Controller.L_O_W.Memory_Ack 106 0.00% 0.00% +system.ruby.Directory_Controller.L_NO_W.GETX 466 0.00% 0.00% +system.ruby.Directory_Controller.L_NO_W.GETS 814 0.00% 0.00% +system.ruby.Directory_Controller.L_NO_W.Lockdown 28 0.00% 0.00% +system.ruby.Directory_Controller.L_NO_W.Memory_Data 22674 0.00% 0.00% +system.ruby.Directory_Controller.NO_W.GETX 14441 0.00% 0.00% +system.ruby.Directory_Controller.NO_W.GETS 26409 0.00% 0.00% +system.ruby.Directory_Controller.NO_W.Lockdown 22674 0.00% 0.00% +system.ruby.Directory_Controller.NO_W.Ack_All_Tokens 15 0.00% 0.00% +system.ruby.Directory_Controller.NO_W.Memory_Data 596017 0.00% 0.00% +system.ruby.L1Cache_Controller.Load | 50549 12.51% 12.51% | 50655 12.53% 25.04% | 50543 12.51% 37.55% | 50433 12.48% 50.03% | 50597 12.52% 62.55% | 50378 12.47% 75.01% | 50321 12.45% 87.46% | 50661 12.54% 100.00% +system.ruby.L1Cache_Controller.Load::total 404137 +system.ruby.L1Cache_Controller.Store | 28221 12.65% 12.65% | 27757 12.44% 25.09% | 28028 12.56% 37.65% | 27656 12.39% 50.04% | 27664 12.40% 62.44% | 27998 12.55% 74.99% | 28169 12.62% 87.61% | 27643 12.39% 100.00% +system.ruby.L1Cache_Controller.Store::total 223136 +system.ruby.L1Cache_Controller.L1_Replacement | 1480088 12.55% 12.55% | 1475888 12.52% 25.07% | 1476913 12.53% 37.60% | 1470392 12.47% 50.07% | 1471389 12.48% 62.55% | 1471572 12.48% 75.03% | 1471675 12.48% 87.51% | 1472167 12.49% 100.00% +system.ruby.L1Cache_Controller.L1_Replacement::total 11790084 +system.ruby.L1Cache_Controller.Data_Shared | 197 12.48% 12.48% | 200 12.67% 25.14% | 199 12.60% 37.75% | 194 12.29% 50.03% | 203 12.86% 62.89% | 182 11.53% 74.41% | 203 12.86% 87.27% | 201 12.73% 100.00% +system.ruby.L1Cache_Controller.Data_Shared::total 1579 +system.ruby.L1Cache_Controller.Data_Owner | 29 10.03% 10.03% | 45 15.57% 25.61% | 42 14.53% 40.14% | 29 10.03% 50.17% | 39 13.49% 63.67% | 26 9.00% 72.66% | 40 13.84% 86.51% | 39 13.49% 100.00% +system.ruby.L1Cache_Controller.Data_Owner::total 289 +system.ruby.L1Cache_Controller.Data_All_Tokens | 82668 12.56% 12.56% | 82207 12.49% 25.06% | 82439 12.53% 37.59% | 81884 12.44% 50.03% | 82153 12.49% 62.52% | 82236 12.50% 75.02% | 82293 12.51% 87.52% | 82094 12.48% 100.00% +system.ruby.L1Cache_Controller.Data_All_Tokens::total 657974 +system.ruby.L1Cache_Controller.Ack | 2 20.00% 20.00% | 2 20.00% 40.00% | 1 10.00% 50.00% | 1 10.00% 60.00% | 1 10.00% 70.00% | 1 10.00% 80.00% | 0 0.00% 80.00% | 2 20.00% 100.00% +system.ruby.L1Cache_Controller.Ack::total 10 +system.ruby.L1Cache_Controller.Ack_All_Tokens | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 33.33% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 1 33.33% 66.67% | 1 33.33% 100.00% +system.ruby.L1Cache_Controller.Ack_All_Tokens::total 3 +system.ruby.L1Cache_Controller.Transient_Local_GETX | 194854 12.48% 12.48% | 195320 12.51% 24.99% | 195053 12.49% 37.48% | 195420 12.52% 49.99% | 195412 12.51% 62.51% | 195080 12.49% 75.00% | 194909 12.48% 87.48% | 195435 12.52% 100.00% +system.ruby.L1Cache_Controller.Transient_Local_GETX::total 1561483 +system.ruby.L1Cache_Controller.Transient_Local_GETS | 353483 12.50% 12.50% | 353371 12.49% 24.99% | 353489 12.50% 37.49% | 353602 12.50% 50.00% | 353436 12.50% 62.49% | 353654 12.50% 75.00% | 353706 12.51% 87.50% | 353373 12.50% 100.00% +system.ruby.L1Cache_Controller.Transient_Local_GETS::total 2828114 +system.ruby.L1Cache_Controller.Transient_Local_GETS_Last_Token | 0 0.00% 0.00% | 2 40.00% 40.00% | 0 0.00% 40.00% | 0 0.00% 40.00% | 1 20.00% 60.00% | 1 20.00% 80.00% | 0 0.00% 80.00% | 1 20.00% 100.00% +system.ruby.L1Cache_Controller.Transient_Local_GETS_Last_Token::total 5 +system.ruby.L1Cache_Controller.Persistent_GETX | 13783 12.49% 12.49% | 13801 12.51% 25.00% | 13756 12.47% 37.47% | 13761 12.47% 49.95% | 13777 12.49% 62.43% | 13755 12.47% 74.90% | 13894 12.59% 87.49% | 13796 12.51% 100.00% +system.ruby.L1Cache_Controller.Persistent_GETX::total 110323 +system.ruby.L1Cache_Controller.Persistent_GETS | 24943 12.44% 12.44% | 25035 12.49% 24.93% | 25044 12.49% 37.42% | 25123 12.53% 49.95% | 25028 12.48% 62.43% | 25059 12.50% 74.93% | 25085 12.51% 87.44% | 25178 12.56% 100.00% +system.ruby.L1Cache_Controller.Persistent_GETS::total 200495 +system.ruby.L1Cache_Controller.Persistent_GETS_Last_Token | 1 25.00% 25.00% | 0 0.00% 25.00% | 0 0.00% 25.00% | 1 25.00% 50.00% | 0 0.00% 50.00% | 1 25.00% 75.00% | 1 25.00% 100.00% | 0 0.00% 100.00% system.ruby.L1Cache_Controller.Persistent_GETS_Last_Token::total 4 -system.ruby.L1Cache_Controller.Own_Lock_or_Unlock | 51053 12.51% 12.51% | 51056 12.51% 25.03% | 51083 12.52% 37.55% | 50956 12.49% 50.04% | 50965 12.49% 62.53% | 50940 12.49% 75.02% | 50973 12.49% 87.51% | 50953 12.49% 100.00% -system.ruby.L1Cache_Controller.Own_Lock_or_Unlock::total 407979 -system.ruby.L1Cache_Controller.Request_Timeout | 35893 12.78% 12.78% | 35498 12.64% 25.42% | 35407 12.61% 38.02% | 34645 12.33% 50.36% | 35410 12.61% 62.97% | 34897 12.42% 75.39% | 34128 12.15% 87.54% | 34991 12.46% 100.00% -system.ruby.L1Cache_Controller.Request_Timeout::total 280869 -system.ruby.L1Cache_Controller.Use_TimeoutStarverX | 8 10.00% 10.00% | 6 7.50% 17.50% | 11 13.75% 31.25% | 11 13.75% 45.00% | 11 13.75% 58.75% | 6 7.50% 66.25% | 11 13.75% 80.00% | 16 20.00% 100.00% -system.ruby.L1Cache_Controller.Use_TimeoutStarverX::total 80 -system.ruby.L1Cache_Controller.Use_TimeoutStarverS | 7 5.79% 5.79% | 23 19.01% 24.79% | 14 11.57% 36.36% | 9 7.44% 43.80% | 20 16.53% 60.33% | 18 14.88% 75.21% | 14 11.57% 86.78% | 16 13.22% 100.00% -system.ruby.L1Cache_Controller.Use_TimeoutStarverS::total 121 -system.ruby.L1Cache_Controller.Use_TimeoutNoStarvers | 78546 12.58% 12.58% | 78110 12.51% 25.09% | 78198 12.53% 37.62% | 78066 12.50% 50.12% | 77695 12.45% 62.57% | 78214 12.53% 75.10% | 77757 12.46% 87.55% | 77697 12.45% 100.00% -system.ruby.L1Cache_Controller.Use_TimeoutNoStarvers::total 624283 -system.ruby.L1Cache_Controller.NP.Load | 50396 12.51% 12.51% | 50523 12.54% 25.05% | 50724 12.59% 37.63% | 50182 12.45% 50.09% | 50190 12.46% 62.54% | 50352 12.50% 75.04% | 50293 12.48% 87.52% | 50276 12.48% 100.00% -system.ruby.L1Cache_Controller.NP.Load::total 402936 -system.ruby.L1Cache_Controller.NP.Store | 28349 12.72% 12.72% | 27783 12.47% 25.18% | 27674 12.42% 37.60% | 28036 12.58% 50.18% | 27695 12.43% 62.61% | 28060 12.59% 75.19% | 27646 12.40% 87.60% | 27641 12.40% 100.00% -system.ruby.L1Cache_Controller.NP.Store::total 222884 -system.ruby.L1Cache_Controller.NP.Data_Shared | 17 14.53% 14.53% | 16 13.68% 28.21% | 15 12.82% 41.03% | 12 10.26% 51.28% | 12 10.26% 61.54% | 11 9.40% 70.94% | 9 7.69% 78.63% | 25 21.37% 100.00% -system.ruby.L1Cache_Controller.NP.Data_Shared::total 117 -system.ruby.L1Cache_Controller.NP.Data_Owner | 11 11.46% 11.46% | 10 10.42% 21.88% | 13 13.54% 35.42% | 7 7.29% 42.71% | 11 11.46% 54.17% | 11 11.46% 65.62% | 8 8.33% 73.96% | 25 26.04% 100.00% -system.ruby.L1Cache_Controller.NP.Data_Owner::total 96 -system.ruby.L1Cache_Controller.NP.Data_All_Tokens | 4088 12.46% 12.46% | 4134 12.60% 25.06% | 4147 12.64% 37.70% | 4054 12.35% 50.05% | 4073 12.41% 62.46% | 4098 12.49% 74.95% | 4120 12.56% 87.51% | 4099 12.49% 100.00% -system.ruby.L1Cache_Controller.NP.Data_All_Tokens::total 32813 -system.ruby.L1Cache_Controller.NP.Ack | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 2 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.NP.Ack::total 2 -system.ruby.L1Cache_Controller.NP.Transient_Local_GETX | 194161 12.47% 12.47% | 194721 12.50% 24.97% | 194841 12.51% 37.49% | 194462 12.49% 49.97% | 194791 12.51% 62.48% | 194446 12.49% 74.97% | 194881 12.51% 87.48% | 194886 12.52% 100.00% -system.ruby.L1Cache_Controller.NP.Transient_Local_GETX::total 1557189 -system.ruby.L1Cache_Controller.NP.Transient_Local_GETS | 351907 12.50% 12.50% | 351775 12.50% 25.00% | 351496 12.49% 37.48% | 352130 12.51% 49.99% | 352083 12.51% 62.50% | 351871 12.50% 74.99% | 351944 12.50% 87.50% | 352019 12.50% 100.00% -system.ruby.L1Cache_Controller.NP.Transient_Local_GETS::total 2815225 -system.ruby.L1Cache_Controller.NP.Own_Lock_or_Unlock | 44647 12.50% 12.50% | 44658 12.50% 25.00% | 44641 12.50% 37.50% | 44692 12.51% 50.01% | 44586 12.48% 62.50% | 44684 12.51% 75.01% | 44620 12.49% 87.50% | 44656 12.50% 100.00% -system.ruby.L1Cache_Controller.NP.Own_Lock_or_Unlock::total 357184 -system.ruby.L1Cache_Controller.I.L1_Replacement | 75 10.58% 10.58% | 92 12.98% 23.55% | 106 14.95% 38.50% | 95 13.40% 51.90% | 95 13.40% 65.30% | 81 11.42% 76.73% | 76 10.72% 87.45% | 89 12.55% 100.00% -system.ruby.L1Cache_Controller.I.L1_Replacement::total 709 -system.ruby.L1Cache_Controller.I.Data_All_Tokens | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.I.Data_All_Tokens::total 1 -system.ruby.L1Cache_Controller.I.Transient_Local_GETX | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.I.Transient_Local_GETX::total 1 -system.ruby.L1Cache_Controller.I.Transient_Local_GETS | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.I.Transient_Local_GETS::total 1 -system.ruby.L1Cache_Controller.S.L1_Replacement | 205 12.97% 12.97% | 201 12.71% 25.68% | 201 12.71% 38.39% | 162 10.25% 48.64% | 198 12.52% 61.16% | 208 13.16% 74.32% | 199 12.59% 86.91% | 207 13.09% 100.00% -system.ruby.L1Cache_Controller.S.L1_Replacement::total 1581 -system.ruby.L1Cache_Controller.S.Data_Shared | 4 26.67% 26.67% | 2 13.33% 40.00% | 3 20.00% 60.00% | 2 13.33% 73.33% | 0 0.00% 73.33% | 1 6.67% 80.00% | 0 0.00% 80.00% | 3 20.00% 100.00% -system.ruby.L1Cache_Controller.S.Data_Shared::total 15 -system.ruby.L1Cache_Controller.S.Data_Owner | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.S.Data_Owner::total 1 -system.ruby.L1Cache_Controller.S.Data_All_Tokens | 2 40.00% 40.00% | 1 20.00% 60.00% | 0 0.00% 60.00% | 0 0.00% 60.00% | 1 20.00% 80.00% | 0 0.00% 80.00% | 0 0.00% 80.00% | 1 20.00% 100.00% +system.ruby.L1Cache_Controller.Own_Lock_or_Unlock | 49729 12.53% 12.53% | 49620 12.50% 25.04% | 49656 12.51% 37.55% | 49571 12.49% 50.04% | 49651 12.51% 62.55% | 49641 12.51% 75.06% | 49476 12.47% 87.53% | 49482 12.47% 100.00% +system.ruby.L1Cache_Controller.Own_Lock_or_Unlock::total 396826 +system.ruby.L1Cache_Controller.Request_Timeout | 33619 12.37% 12.37% | 34306 12.62% 24.99% | 34435 12.67% 37.65% | 33457 12.31% 49.96% | 34654 12.75% 62.71% | 33427 12.30% 75.00% | 34346 12.63% 87.64% | 33609 12.36% 100.00% +system.ruby.L1Cache_Controller.Request_Timeout::total 271853 +system.ruby.L1Cache_Controller.Use_TimeoutStarverX | 6 10.71% 10.71% | 5 8.93% 19.64% | 6 10.71% 30.36% | 7 12.50% 42.86% | 8 14.29% 57.14% | 6 10.71% 67.86% | 8 14.29% 82.14% | 10 17.86% 100.00% +system.ruby.L1Cache_Controller.Use_TimeoutStarverX::total 56 +system.ruby.L1Cache_Controller.Use_TimeoutStarverS | 7 5.15% 5.15% | 17 12.50% 17.65% | 15 11.03% 28.68% | 13 9.56% 38.24% | 12 8.82% 47.06% | 25 18.38% 65.44% | 23 16.91% 82.35% | 24 17.65% 100.00% +system.ruby.L1Cache_Controller.Use_TimeoutStarverS::total 136 +system.ruby.L1Cache_Controller.Use_TimeoutNoStarvers | 78528 12.56% 12.56% | 78156 12.50% 25.06% | 78311 12.53% 37.59% | 77846 12.45% 50.04% | 78001 12.48% 62.51% | 78123 12.50% 75.01% | 78233 12.51% 87.52% | 78034 12.48% 100.00% +system.ruby.L1Cache_Controller.Use_TimeoutNoStarvers::total 625232 +system.ruby.L1Cache_Controller.NP.Load | 50509 12.51% 12.51% | 50627 12.54% 25.04% | 50510 12.51% 37.55% | 50389 12.48% 50.03% | 50551 12.52% 62.55% | 50342 12.47% 75.02% | 50285 12.45% 87.47% | 50606 12.53% 100.00% +system.ruby.L1Cache_Controller.NP.Load::total 403819 +system.ruby.L1Cache_Controller.NP.Store | 28202 12.65% 12.65% | 27742 12.44% 25.09% | 28001 12.56% 37.65% | 27633 12.39% 50.04% | 27642 12.40% 62.44% | 27971 12.55% 74.99% | 28144 12.62% 87.61% | 27623 12.39% 100.00% +system.ruby.L1Cache_Controller.NP.Store::total 222958 +system.ruby.L1Cache_Controller.NP.Data_Shared | 11 8.59% 8.59% | 18 14.06% 22.66% | 19 14.84% 37.50% | 14 10.94% 48.44% | 16 12.50% 60.94% | 8 6.25% 67.19% | 23 17.97% 85.16% | 19 14.84% 100.00% +system.ruby.L1Cache_Controller.NP.Data_Shared::total 128 +system.ruby.L1Cache_Controller.NP.Data_Owner | 6 7.14% 7.14% | 14 16.67% 23.81% | 11 13.10% 36.90% | 10 11.90% 48.81% | 12 14.29% 63.10% | 5 5.95% 69.05% | 13 15.48% 84.52% | 13 15.48% 100.00% +system.ruby.L1Cache_Controller.NP.Data_Owner::total 84 +system.ruby.L1Cache_Controller.NP.Data_All_Tokens | 4108 12.67% 12.67% | 4005 12.35% 25.02% | 4095 12.63% 37.64% | 3999 12.33% 49.97% | 4120 12.70% 62.68% | 4067 12.54% 75.22% | 4023 12.40% 87.62% | 4014 12.38% 100.00% +system.ruby.L1Cache_Controller.NP.Data_All_Tokens::total 32431 +system.ruby.L1Cache_Controller.NP.Ack | 0 0.00% 0.00% | 2 50.00% 50.00% | 1 25.00% 75.00% | 1 25.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.NP.Ack::total 4 +system.ruby.L1Cache_Controller.NP.Transient_Local_GETX | 194378 12.48% 12.48% | 194859 12.51% 24.99% | 194607 12.49% 37.48% | 194968 12.52% 49.99% | 194930 12.51% 62.51% | 194649 12.49% 75.00% | 194495 12.48% 87.48% | 194975 12.52% 100.00% +system.ruby.L1Cache_Controller.NP.Transient_Local_GETX::total 1557861 +system.ruby.L1Cache_Controller.NP.Transient_Local_GETS | 352691 12.50% 12.50% | 352515 12.49% 24.99% | 352621 12.50% 37.49% | 352784 12.50% 50.00% | 352579 12.50% 62.49% | 352819 12.50% 75.00% | 352925 12.51% 87.51% | 352525 12.49% 100.00% +system.ruby.L1Cache_Controller.NP.Transient_Local_GETS::total 2821459 +system.ruby.L1Cache_Controller.NP.Own_Lock_or_Unlock | 43402 12.49% 12.49% | 43438 12.50% 24.98% | 43495 12.51% 37.49% | 43450 12.50% 49.99% | 43468 12.50% 62.50% | 43442 12.50% 75.00% | 43468 12.50% 87.50% | 43449 12.50% 100.00% +system.ruby.L1Cache_Controller.NP.Own_Lock_or_Unlock::total 347612 +system.ruby.L1Cache_Controller.I.L1_Replacement | 83 12.46% 12.46% | 85 12.76% 25.23% | 90 13.51% 38.74% | 71 10.66% 49.40% | 86 12.91% 62.31% | 92 13.81% 76.13% | 74 11.11% 87.24% | 85 12.76% 100.00% +system.ruby.L1Cache_Controller.I.L1_Replacement::total 666 +system.ruby.L1Cache_Controller.I.Data_All_Tokens | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 50.00% 50.00% | 0 0.00% 50.00% | 1 50.00% 100.00% +system.ruby.L1Cache_Controller.I.Data_All_Tokens::total 2 +system.ruby.L1Cache_Controller.I.Transient_Local_GETX | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 50.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.I.Transient_Local_GETX::total 2 +system.ruby.L1Cache_Controller.I.Transient_Local_GETS | 1 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.I.Transient_Local_GETS::total 2 +system.ruby.L1Cache_Controller.I.Persistent_GETX | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 50.00% 50.00% | 0 0.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.I.Persistent_GETX::total 2 +system.ruby.L1Cache_Controller.S.L1_Replacement | 197 12.19% 12.19% | 208 12.87% 25.06% | 195 12.07% 37.13% | 202 12.50% 49.63% | 209 12.93% 62.56% | 196 12.13% 74.69% | 206 12.75% 87.44% | 203 12.56% 100.00% +system.ruby.L1Cache_Controller.S.L1_Replacement::total 1616 +system.ruby.L1Cache_Controller.S.Data_Shared | 4 21.05% 21.05% | 2 10.53% 31.58% | 2 10.53% 42.11% | 4 21.05% 63.16% | 2 10.53% 73.68% | 2 10.53% 84.21% | 1 5.26% 89.47% | 2 10.53% 100.00% +system.ruby.L1Cache_Controller.S.Data_Shared::total 19 +system.ruby.L1Cache_Controller.S.Data_All_Tokens | 1 20.00% 20.00% | 0 0.00% 20.00% | 0 0.00% 20.00% | 2 40.00% 60.00% | 1 20.00% 80.00% | 0 0.00% 80.00% | 0 0.00% 80.00% | 1 20.00% 100.00% system.ruby.L1Cache_Controller.S.Data_All_Tokens::total 5 -system.ruby.L1Cache_Controller.S.Transient_Local_GETX | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.S.Transient_Local_GETX::total 1 -system.ruby.L1Cache_Controller.S.Transient_Local_GETS_Last_Token | 1 33.33% 33.33% | 1 33.33% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 1 33.33% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.S.Transient_Local_GETS_Last_Token::total 3 -system.ruby.L1Cache_Controller.S.Persistent_GETX | 0 0.00% 0.00% | 1 33.33% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 1 33.33% 66.67% | 0 0.00% 66.67% | 1 33.33% 100.00% -system.ruby.L1Cache_Controller.S.Persistent_GETX::total 3 -system.ruby.L1Cache_Controller.S.Persistent_GETS_Last_Token | 2 50.00% 50.00% | 0 0.00% 50.00% | 1 25.00% 75.00% | 0 0.00% 75.00% | 0 0.00% 75.00% | 0 0.00% 75.00% | 1 25.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.S.Transient_Local_GETX | 0 0.00% 0.00% | 1 33.33% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 1 33.33% 66.67% | 1 33.33% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.S.Transient_Local_GETX::total 3 +system.ruby.L1Cache_Controller.S.Transient_Local_GETS_Last_Token | 0 0.00% 0.00% | 2 40.00% 40.00% | 0 0.00% 40.00% | 0 0.00% 40.00% | 1 20.00% 60.00% | 1 20.00% 80.00% | 0 0.00% 80.00% | 1 20.00% 100.00% +system.ruby.L1Cache_Controller.S.Transient_Local_GETS_Last_Token::total 5 +system.ruby.L1Cache_Controller.S.Persistent_GETX | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.S.Persistent_GETX::total 1 +system.ruby.L1Cache_Controller.S.Persistent_GETS_Last_Token | 1 25.00% 25.00% | 0 0.00% 25.00% | 0 0.00% 25.00% | 1 25.00% 50.00% | 0 0.00% 50.00% | 1 25.00% 75.00% | 1 25.00% 100.00% | 0 0.00% 100.00% system.ruby.L1Cache_Controller.S.Persistent_GETS_Last_Token::total 4 -system.ruby.L1Cache_Controller.O.L1_Replacement | 62 12.16% 12.16% | 62 12.16% 24.31% | 81 15.88% 40.20% | 49 9.61% 49.80% | 71 13.92% 63.73% | 67 13.14% 76.86% | 53 10.39% 87.25% | 65 12.75% 100.00% -system.ruby.L1Cache_Controller.O.L1_Replacement::total 510 +system.ruby.L1Cache_Controller.O.L1_Replacement | 63 11.98% 11.98% | 79 15.02% 27.00% | 69 13.12% 40.11% | 63 11.98% 52.09% | 69 13.12% 65.21% | 55 10.46% 75.67% | 56 10.65% 86.31% | 72 13.69% 100.00% +system.ruby.L1Cache_Controller.O.L1_Replacement::total 526 system.ruby.L1Cache_Controller.O.Data_All_Tokens | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.L1Cache_Controller.O.Data_All_Tokens::total 2 -system.ruby.L1Cache_Controller.O.Ack | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.O.Ack | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.L1Cache_Controller.O.Ack::total 1 -system.ruby.L1Cache_Controller.O.Persistent_GETS | 1 33.33% 33.33% | 2 66.67% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.O.Persistent_GETS::total 3 -system.ruby.L1Cache_Controller.O.Own_Lock_or_Unlock | 6 13.95% 13.95% | 5 11.63% 25.58% | 6 13.95% 39.53% | 7 16.28% 55.81% | 5 11.63% 67.44% | 5 11.63% 79.07% | 2 4.65% 83.72% | 7 16.28% 100.00% -system.ruby.L1Cache_Controller.O.Own_Lock_or_Unlock::total 43 -system.ruby.L1Cache_Controller.M.Load | 3 12.50% 12.50% | 3 12.50% 25.00% | 3 12.50% 37.50% | 2 8.33% 45.83% | 4 16.67% 62.50% | 3 12.50% 75.00% | 2 8.33% 83.33% | 4 16.67% 100.00% -system.ruby.L1Cache_Controller.M.Load::total 24 -system.ruby.L1Cache_Controller.M.Store | 0 0.00% 0.00% | 1 10.00% 10.00% | 2 20.00% 30.00% | 1 10.00% 40.00% | 1 10.00% 50.00% | 1 10.00% 60.00% | 1 10.00% 70.00% | 3 30.00% 100.00% -system.ruby.L1Cache_Controller.M.Store::total 10 -system.ruby.L1Cache_Controller.M.L1_Replacement | 50107 12.51% 12.51% | 50235 12.54% 25.04% | 50417 12.58% 37.63% | 49956 12.47% 50.09% | 49910 12.46% 62.55% | 50054 12.49% 75.04% | 50028 12.49% 87.53% | 49970 12.47% 100.00% -system.ruby.L1Cache_Controller.M.L1_Replacement::total 400677 -system.ruby.L1Cache_Controller.M.Transient_Local_GETX | 18 10.98% 10.98% | 21 12.80% 23.78% | 33 20.12% 43.90% | 21 12.80% 56.71% | 20 12.20% 68.90% | 19 11.59% 80.49% | 12 7.32% 87.80% | 20 12.20% 100.00% -system.ruby.L1Cache_Controller.M.Transient_Local_GETX::total 164 -system.ruby.L1Cache_Controller.M.Transient_Local_GETS | 33 10.68% 10.68% | 36 11.65% 22.33% | 50 16.18% 38.51% | 26 8.41% 46.93% | 47 15.21% 62.14% | 48 15.53% 77.67% | 36 11.65% 89.32% | 33 10.68% 100.00% -system.ruby.L1Cache_Controller.M.Transient_Local_GETS::total 309 -system.ruby.L1Cache_Controller.M.Persistent_GETX | 10 14.71% 14.71% | 14 20.59% 35.29% | 4 5.88% 41.18% | 5 7.35% 48.53% | 7 10.29% 58.82% | 8 11.76% 70.59% | 9 13.24% 83.82% | 11 16.18% 100.00% -system.ruby.L1Cache_Controller.M.Persistent_GETX::total 68 -system.ruby.L1Cache_Controller.M.Persistent_GETS | 16 12.70% 12.70% | 16 12.70% 25.40% | 20 15.87% 41.27% | 17 13.49% 54.76% | 14 11.11% 65.87% | 15 11.90% 77.78% | 19 15.08% 92.86% | 9 7.14% 100.00% -system.ruby.L1Cache_Controller.M.Persistent_GETS::total 126 -system.ruby.L1Cache_Controller.M.Own_Lock_or_Unlock | 336 13.03% 13.03% | 302 11.71% 24.75% | 322 12.49% 37.24% | 314 12.18% 49.42% | 336 13.03% 62.45% | 318 12.34% 74.79% | 350 13.58% 88.36% | 300 11.64% 100.00% -system.ruby.L1Cache_Controller.M.Own_Lock_or_Unlock::total 2578 -system.ruby.L1Cache_Controller.MM.Load | 3 30.00% 30.00% | 2 20.00% 50.00% | 0 0.00% 50.00% | 1 10.00% 60.00% | 1 10.00% 70.00% | 1 10.00% 80.00% | 1 10.00% 90.00% | 1 10.00% 100.00% -system.ruby.L1Cache_Controller.MM.Load::total 10 -system.ruby.L1Cache_Controller.MM.Store | 2 22.22% 22.22% | 1 11.11% 33.33% | 1 11.11% 44.44% | 3 33.33% 77.78% | 0 0.00% 77.78% | 0 0.00% 77.78% | 1 11.11% 88.89% | 1 11.11% 100.00% -system.ruby.L1Cache_Controller.MM.Store::total 9 -system.ruby.L1Cache_Controller.MM.L1_Replacement | 28327 12.73% 12.73% | 27748 12.47% 25.19% | 27621 12.41% 37.60% | 27990 12.57% 50.17% | 27649 12.42% 62.59% | 28030 12.59% 75.19% | 27616 12.41% 87.59% | 27619 12.41% 100.00% -system.ruby.L1Cache_Controller.MM.L1_Replacement::total 222600 -system.ruby.L1Cache_Controller.MM.Transient_Local_GETX | 13 15.29% 15.29% | 10 11.76% 27.06% | 14 16.47% 43.53% | 15 17.65% 61.18% | 11 12.94% 74.12% | 12 14.12% 88.24% | 2 2.35% 90.59% | 8 9.41% 100.00% -system.ruby.L1Cache_Controller.MM.Transient_Local_GETX::total 85 -system.ruby.L1Cache_Controller.MM.Transient_Local_GETS | 14 8.05% 8.05% | 23 13.22% 21.26% | 26 14.94% 36.21% | 23 13.22% 49.43% | 27 15.52% 64.94% | 22 12.64% 77.59% | 18 10.34% 87.93% | 21 12.07% 100.00% -system.ruby.L1Cache_Controller.MM.Transient_Local_GETS::total 174 -system.ruby.L1Cache_Controller.MM.Persistent_GETX | 4 15.38% 15.38% | 1 3.85% 19.23% | 5 19.23% 38.46% | 5 19.23% 57.69% | 3 11.54% 69.23% | 2 7.69% 76.92% | 3 11.54% 88.46% | 3 11.54% 100.00% -system.ruby.L1Cache_Controller.MM.Persistent_GETX::total 26 -system.ruby.L1Cache_Controller.MM.Persistent_GETS | 5 8.20% 8.20% | 7 11.48% 19.67% | 9 14.75% 34.43% | 8 13.11% 47.54% | 8 13.11% 60.66% | 6 9.84% 70.49% | 14 22.95% 93.44% | 4 6.56% 100.00% -system.ruby.L1Cache_Controller.MM.Persistent_GETS::total 61 -system.ruby.L1Cache_Controller.MM.Own_Lock_or_Unlock | 179 12.77% 12.77% | 171 12.20% 24.96% | 180 12.84% 37.80% | 144 10.27% 48.07% | 206 14.69% 62.77% | 162 11.55% 74.32% | 172 12.27% 86.59% | 188 13.41% 100.00% -system.ruby.L1Cache_Controller.MM.Own_Lock_or_Unlock::total 1402 -system.ruby.L1Cache_Controller.M_W.Load | 10 23.81% 23.81% | 8 19.05% 42.86% | 3 7.14% 50.00% | 6 14.29% 64.29% | 1 2.38% 66.67% | 4 9.52% 76.19% | 6 14.29% 90.48% | 4 9.52% 100.00% -system.ruby.L1Cache_Controller.M_W.Load::total 42 -system.ruby.L1Cache_Controller.M_W.Store | 6 17.65% 17.65% | 3 8.82% 26.47% | 2 5.88% 32.35% | 6 17.65% 50.00% | 3 8.82% 58.82% | 9 26.47% 85.29% | 2 5.88% 91.18% | 3 8.82% 100.00% -system.ruby.L1Cache_Controller.M_W.Store::total 34 -system.ruby.L1Cache_Controller.M_W.L1_Replacement | 368409 12.51% 12.51% | 366891 12.46% 24.97% | 370081 12.57% 37.54% | 369093 12.53% 50.07% | 366788 12.45% 62.52% | 368135 12.50% 75.02% | 368286 12.51% 87.53% | 367236 12.47% 100.00% -system.ruby.L1Cache_Controller.M_W.L1_Replacement::total 2944919 -system.ruby.L1Cache_Controller.M_W.Transient_Local_GETX | 65 13.08% 13.08% | 59 11.87% 24.95% | 55 11.07% 36.02% | 71 14.29% 50.30% | 68 13.68% 63.98% | 64 12.88% 76.86% | 59 11.87% 88.73% | 56 11.27% 100.00% -system.ruby.L1Cache_Controller.M_W.Transient_Local_GETX::total 497 -system.ruby.L1Cache_Controller.M_W.Transient_Local_GETS | 100 11.92% 11.92% | 107 12.75% 24.67% | 105 12.51% 37.19% | 92 10.97% 48.15% | 98 11.68% 59.83% | 104 12.40% 72.23% | 121 14.42% 86.65% | 112 13.35% 100.00% -system.ruby.L1Cache_Controller.M_W.Transient_Local_GETS::total 839 -system.ruby.L1Cache_Controller.M_W.Persistent_GETX | 6 12.24% 12.24% | 4 8.16% 20.41% | 7 14.29% 34.69% | 6 12.24% 46.94% | 5 10.20% 57.14% | 2 4.08% 61.22% | 8 16.33% 77.55% | 11 22.45% 100.00% -system.ruby.L1Cache_Controller.M_W.Persistent_GETX::total 49 -system.ruby.L1Cache_Controller.M_W.Persistent_GETS | 4 5.97% 5.97% | 12 17.91% 23.88% | 9 13.43% 37.31% | 3 4.48% 41.79% | 12 17.91% 59.70% | 11 16.42% 76.12% | 7 10.45% 86.57% | 9 13.43% 100.00% -system.ruby.L1Cache_Controller.M_W.Persistent_GETS::total 67 -system.ruby.L1Cache_Controller.M_W.Own_Lock_or_Unlock | 482 13.53% 13.53% | 458 12.85% 26.38% | 499 14.01% 40.39% | 442 12.41% 52.79% | 426 11.96% 64.75% | 429 12.04% 76.79% | 409 11.48% 88.27% | 418 11.73% 100.00% -system.ruby.L1Cache_Controller.M_W.Own_Lock_or_Unlock::total 3563 -system.ruby.L1Cache_Controller.M_W.Use_TimeoutStarverX | 6 11.32% 11.32% | 4 7.55% 18.87% | 8 15.09% 33.96% | 6 11.32% 45.28% | 6 11.32% 56.60% | 2 3.77% 60.38% | 9 16.98% 77.36% | 12 22.64% 100.00% -system.ruby.L1Cache_Controller.M_W.Use_TimeoutStarverX::total 53 -system.ruby.L1Cache_Controller.M_W.Use_TimeoutStarverS | 4 5.41% 5.41% | 14 18.92% 24.32% | 10 13.51% 37.84% | 4 5.41% 43.24% | 12 16.22% 59.46% | 12 16.22% 75.68% | 7 9.46% 85.14% | 11 14.86% 100.00% -system.ruby.L1Cache_Controller.M_W.Use_TimeoutStarverS::total 74 -system.ruby.L1Cache_Controller.M_W.Use_TimeoutNoStarvers | 50183 12.50% 12.50% | 50322 12.54% 25.04% | 50525 12.59% 37.63% | 50026 12.46% 50.10% | 49998 12.46% 62.55% | 50143 12.49% 75.05% | 50105 12.48% 87.53% | 50045 12.47% 100.00% -system.ruby.L1Cache_Controller.M_W.Use_TimeoutNoStarvers::total 401347 -system.ruby.L1Cache_Controller.MM_W.Load | 3 18.75% 18.75% | 1 6.25% 25.00% | 0 0.00% 25.00% | 3 18.75% 43.75% | 4 25.00% 68.75% | 0 0.00% 68.75% | 3 18.75% 87.50% | 2 12.50% 100.00% -system.ruby.L1Cache_Controller.MM_W.Load::total 16 -system.ruby.L1Cache_Controller.MM_W.Store | 2 11.11% 11.11% | 3 16.67% 27.78% | 4 22.22% 50.00% | 1 5.56% 55.56% | 3 16.67% 72.22% | 3 16.67% 88.89% | 1 5.56% 94.44% | 1 5.56% 100.00% -system.ruby.L1Cache_Controller.MM_W.Store::total 18 -system.ruby.L1Cache_Controller.MM_W.L1_Replacement | 207903 12.76% 12.76% | 199705 12.26% 25.02% | 201929 12.40% 37.42% | 203693 12.50% 49.92% | 204500 12.55% 62.48% | 205369 12.61% 75.09% | 204273 12.54% 87.63% | 201565 12.37% 100.00% -system.ruby.L1Cache_Controller.MM_W.L1_Replacement::total 1628937 -system.ruby.L1Cache_Controller.MM_W.Transient_Local_GETX | 19 7.72% 7.72% | 26 10.57% 18.29% | 31 12.60% 30.89% | 38 15.45% 46.34% | 41 16.67% 63.01% | 32 13.01% 76.02% | 29 11.79% 87.80% | 30 12.20% 100.00% -system.ruby.L1Cache_Controller.MM_W.Transient_Local_GETX::total 246 -system.ruby.L1Cache_Controller.MM_W.Transient_Local_GETS | 45 9.98% 9.98% | 51 11.31% 21.29% | 67 14.86% 36.14% | 58 12.86% 49.00% | 59 13.08% 62.08% | 58 12.86% 74.94% | 62 13.75% 88.69% | 51 11.31% 100.00% -system.ruby.L1Cache_Controller.MM_W.Transient_Local_GETS::total 451 -system.ruby.L1Cache_Controller.MM_W.Persistent_GETX | 1 4.17% 4.17% | 2 8.33% 12.50% | 3 12.50% 25.00% | 4 16.67% 41.67% | 4 16.67% 58.33% | 4 16.67% 75.00% | 2 8.33% 83.33% | 4 16.67% 100.00% -system.ruby.L1Cache_Controller.MM_W.Persistent_GETX::total 24 -system.ruby.L1Cache_Controller.MM_W.Persistent_GETS | 3 6.98% 6.98% | 9 20.93% 27.91% | 4 9.30% 37.21% | 5 11.63% 48.84% | 7 16.28% 65.12% | 6 13.95% 79.07% | 6 13.95% 93.02% | 3 6.98% 100.00% -system.ruby.L1Cache_Controller.MM_W.Persistent_GETS::total 43 -system.ruby.L1Cache_Controller.MM_W.Own_Lock_or_Unlock | 263 13.34% 13.34% | 245 12.43% 25.77% | 253 12.84% 38.61% | 264 13.39% 52.00% | 260 13.19% 65.20% | 223 11.31% 76.51% | 217 11.01% 87.52% | 246 12.48% 100.00% -system.ruby.L1Cache_Controller.MM_W.Own_Lock_or_Unlock::total 1971 -system.ruby.L1Cache_Controller.MM_W.Use_TimeoutStarverX | 2 7.41% 7.41% | 2 7.41% 14.81% | 3 11.11% 25.93% | 5 18.52% 44.44% | 5 18.52% 62.96% | 4 14.81% 77.78% | 2 7.41% 85.19% | 4 14.81% 100.00% -system.ruby.L1Cache_Controller.MM_W.Use_TimeoutStarverX::total 27 -system.ruby.L1Cache_Controller.MM_W.Use_TimeoutStarverS | 3 6.38% 6.38% | 9 19.15% 25.53% | 4 8.51% 34.04% | 5 10.64% 44.68% | 8 17.02% 61.70% | 6 12.77% 74.47% | 7 14.89% 89.36% | 5 10.64% 100.00% -system.ruby.L1Cache_Controller.MM_W.Use_TimeoutStarverS::total 47 -system.ruby.L1Cache_Controller.MM_W.Use_TimeoutNoStarvers | 28363 12.72% 12.72% | 27788 12.46% 25.19% | 27673 12.41% 37.60% | 28040 12.58% 50.18% | 27697 12.42% 62.60% | 28071 12.59% 75.19% | 27652 12.40% 87.60% | 27652 12.40% 100.00% -system.ruby.L1Cache_Controller.MM_W.Use_TimeoutNoStarvers::total 222936 -system.ruby.L1Cache_Controller.IM.L1_Replacement | 299163 12.81% 12.81% | 291113 12.46% 25.27% | 289146 12.38% 37.65% | 289625 12.40% 50.04% | 292483 12.52% 62.56% | 295149 12.63% 75.20% | 289912 12.41% 87.61% | 289481 12.39% 100.00% -system.ruby.L1Cache_Controller.IM.L1_Replacement::total 2336072 -system.ruby.L1Cache_Controller.IM.Data_All_Tokens | 28362 12.72% 12.72% | 27796 12.47% 25.19% | 27679 12.41% 37.60% | 28044 12.58% 50.18% | 27705 12.43% 62.60% | 28071 12.59% 75.19% | 27657 12.40% 87.60% | 27656 12.40% 100.00% -system.ruby.L1Cache_Controller.IM.Data_All_Tokens::total 222970 -system.ruby.L1Cache_Controller.IM.Ack | 1 16.67% 16.67% | 0 0.00% 16.67% | 0 0.00% 16.67% | 0 0.00% 16.67% | 1 16.67% 33.33% | 1 16.67% 50.00% | 2 33.33% 83.33% | 1 16.67% 100.00% -system.ruby.L1Cache_Controller.IM.Ack::total 6 -system.ruby.L1Cache_Controller.IM.Transient_Local_GETX | 99 13.08% 13.08% | 90 11.89% 24.97% | 77 10.17% 35.14% | 92 12.15% 47.29% | 115 15.19% 62.48% | 103 13.61% 76.09% | 87 11.49% 87.58% | 94 12.42% 100.00% -system.ruby.L1Cache_Controller.IM.Transient_Local_GETX::total 757 -system.ruby.L1Cache_Controller.IM.Transient_Local_GETS | 156 11.69% 11.69% | 161 12.06% 23.75% | 159 11.91% 35.66% | 156 11.69% 47.34% | 170 12.73% 60.07% | 202 15.13% 75.21% | 176 13.18% 88.39% | 155 11.61% 100.00% -system.ruby.L1Cache_Controller.IM.Transient_Local_GETS::total 1335 -system.ruby.L1Cache_Controller.IM.Persistent_GETX | 9 13.24% 13.24% | 13 19.12% 32.35% | 10 14.71% 47.06% | 8 11.76% 58.82% | 7 10.29% 69.12% | 8 11.76% 80.88% | 7 10.29% 91.18% | 6 8.82% 100.00% -system.ruby.L1Cache_Controller.IM.Persistent_GETX::total 68 -system.ruby.L1Cache_Controller.IM.Persistent_GETS | 12 8.39% 8.39% | 20 13.99% 22.38% | 15 10.49% 32.87% | 14 9.79% 42.66% | 21 14.69% 57.34% | 18 12.59% 69.93% | 21 14.69% 84.62% | 22 15.38% 100.00% -system.ruby.L1Cache_Controller.IM.Persistent_GETS::total 143 -system.ruby.L1Cache_Controller.IM.Own_Lock_or_Unlock | 1777 12.60% 12.60% | 1748 12.40% 25.00% | 1787 12.67% 37.67% | 1755 12.45% 50.11% | 1772 12.57% 62.68% | 1769 12.54% 75.22% | 1726 12.24% 87.46% | 1768 12.54% 100.00% -system.ruby.L1Cache_Controller.IM.Own_Lock_or_Unlock::total 14102 -system.ruby.L1Cache_Controller.IM.Request_Timeout | 12748 12.91% 12.91% | 12072 12.23% 25.14% | 12469 12.63% 37.77% | 12565 12.73% 50.50% | 12512 12.67% 63.17% | 12178 12.34% 75.51% | 12291 12.45% 87.96% | 11887 12.04% 100.00% -system.ruby.L1Cache_Controller.IM.Request_Timeout::total 98722 -system.ruby.L1Cache_Controller.IS.L1_Replacement | 526465 12.44% 12.44% | 533733 12.61% 25.05% | 535335 12.65% 37.70% | 529186 12.50% 50.20% | 524621 12.39% 62.59% | 526992 12.45% 75.04% | 527555 12.46% 87.51% | 528820 12.49% 100.00% -system.ruby.L1Cache_Controller.IS.L1_Replacement::total 4232707 -system.ruby.L1Cache_Controller.IS.Data_Shared | 187 13.47% 13.47% | 171 12.32% 25.79% | 171 12.32% 38.11% | 142 10.23% 48.34% | 173 12.46% 60.81% | 182 13.11% 73.92% | 173 12.46% 86.38% | 189 13.62% 100.00% -system.ruby.L1Cache_Controller.IS.Data_Shared::total 1388 -system.ruby.L1Cache_Controller.IS.Data_Owner | 29 14.15% 14.15% | 28 13.66% 27.80% | 32 15.61% 43.41% | 23 11.22% 54.63% | 24 11.71% 66.34% | 20 9.76% 76.10% | 17 8.29% 84.39% | 32 15.61% 100.00% -system.ruby.L1Cache_Controller.IS.Data_Owner::total 205 -system.ruby.L1Cache_Controller.IS.Data_All_Tokens | 50199 12.50% 12.50% | 50340 12.54% 25.04% | 50545 12.59% 37.63% | 50041 12.46% 50.09% | 50019 12.46% 62.55% | 50165 12.49% 75.05% | 50124 12.48% 87.53% | 50069 12.47% 100.00% -system.ruby.L1Cache_Controller.IS.Data_All_Tokens::total 401502 -system.ruby.L1Cache_Controller.IS.Transient_Local_GETX | 174 12.95% 12.95% | 188 13.99% 26.93% | 170 12.65% 39.58% | 160 11.90% 51.49% | 156 11.61% 63.10% | 158 11.76% 74.85% | 179 13.32% 88.17% | 159 11.83% 100.00% -system.ruby.L1Cache_Controller.IS.Transient_Local_GETX::total 1344 -system.ruby.L1Cache_Controller.IS.Transient_Local_GETS | 308 12.65% 12.65% | 287 11.79% 24.45% | 338 13.89% 38.33% | 293 12.04% 50.37% | 296 12.16% 62.53% | 297 12.20% 74.73% | 315 12.94% 87.67% | 300 12.33% 100.00% -system.ruby.L1Cache_Controller.IS.Transient_Local_GETS::total 2434 -system.ruby.L1Cache_Controller.IS.Persistent_GETX | 12 8.96% 8.96% | 22 16.42% 25.37% | 16 11.94% 37.31% | 16 11.94% 49.25% | 22 16.42% 65.67% | 10 7.46% 73.13% | 20 14.93% 88.06% | 16 11.94% 100.00% -system.ruby.L1Cache_Controller.IS.Persistent_GETX::total 134 -system.ruby.L1Cache_Controller.IS.Persistent_GETS | 23 10.36% 10.36% | 27 12.16% 22.52% | 31 13.96% 36.49% | 27 12.16% 48.65% | 30 13.51% 62.16% | 27 12.16% 74.32% | 23 10.36% 84.68% | 34 15.32% 100.00% -system.ruby.L1Cache_Controller.IS.Persistent_GETS::total 222 -system.ruby.L1Cache_Controller.IS.Own_Lock_or_Unlock | 3220 12.48% 12.48% | 3284 12.72% 25.20% | 3229 12.51% 37.71% | 3182 12.33% 50.04% | 3192 12.37% 62.41% | 3201 12.40% 74.81% | 3302 12.79% 87.60% | 3200 12.40% 100.00% -system.ruby.L1Cache_Controller.IS.Own_Lock_or_Unlock::total 25810 -system.ruby.L1Cache_Controller.IS.Request_Timeout | 23004 12.71% 12.71% | 23289 12.87% 25.58% | 22739 12.57% 38.15% | 21960 12.14% 50.28% | 22817 12.61% 62.89% | 22505 12.44% 75.33% | 21709 12.00% 87.32% | 22937 12.68% 100.00% -system.ruby.L1Cache_Controller.IS.Request_Timeout::total 180960 -system.ruby.L1Cache_Controller.I_L.Load | 21 11.35% 11.35% | 22 11.89% 23.24% | 26 14.05% 37.30% | 28 15.14% 52.43% | 28 15.14% 67.57% | 17 9.19% 76.76% | 23 12.43% 89.19% | 20 10.81% 100.00% -system.ruby.L1Cache_Controller.I_L.Load::total 185 -system.ruby.L1Cache_Controller.I_L.Store | 14 13.46% 13.46% | 14 13.46% 26.92% | 6 5.77% 32.69% | 10 9.62% 42.31% | 14 13.46% 55.77% | 15 14.42% 70.19% | 14 13.46% 83.65% | 17 16.35% 100.00% -system.ruby.L1Cache_Controller.I_L.Store::total 104 -system.ruby.L1Cache_Controller.I_L.L1_Replacement | 114 9.60% 9.60% | 190 16.01% 25.61% | 113 9.52% 35.13% | 133 11.20% 46.34% | 115 9.69% 56.02% | 141 11.88% 67.90% | 177 14.91% 82.81% | 204 17.19% 100.00% -system.ruby.L1Cache_Controller.I_L.L1_Replacement::total 1187 -system.ruby.L1Cache_Controller.I_L.Data_All_Tokens | 28 24.56% 24.56% | 16 14.04% 38.60% | 21 18.42% 57.02% | 20 17.54% 74.56% | 15 13.16% 87.72% | 10 8.77% 96.49% | 4 3.51% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.I_L.Data_All_Tokens::total 114 -system.ruby.L1Cache_Controller.I_L.Transient_Local_GETX | 74 11.86% 11.86% | 75 12.02% 23.88% | 86 13.78% 37.66% | 80 12.82% 50.48% | 76 12.18% 62.66% | 79 12.66% 75.32% | 78 12.50% 87.82% | 76 12.18% 100.00% -system.ruby.L1Cache_Controller.I_L.Transient_Local_GETX::total 624 -system.ruby.L1Cache_Controller.I_L.Transient_Local_GETS | 139 13.03% 13.03% | 133 12.46% 25.49% | 129 12.09% 37.58% | 132 12.37% 49.95% | 122 11.43% 61.39% | 148 13.87% 75.26% | 130 12.18% 87.44% | 134 12.56% 100.00% -system.ruby.L1Cache_Controller.I_L.Transient_Local_GETS::total 1067 -system.ruby.L1Cache_Controller.I_L.Persistent_GETX | 14071 12.48% 12.48% | 14096 12.51% 24.99% | 14063 12.48% 37.47% | 14085 12.50% 49.96% | 14063 12.48% 62.44% | 14120 12.53% 74.97% | 14143 12.55% 87.51% | 14075 12.49% 100.00% -system.ruby.L1Cache_Controller.I_L.Persistent_GETX::total 112716 -system.ruby.L1Cache_Controller.I_L.Persistent_GETS | 25744 12.50% 12.50% | 25668 12.46% 24.97% | 25687 12.47% 37.44% | 25805 12.53% 49.97% | 25786 12.52% 62.49% | 25771 12.51% 75.01% | 25691 12.48% 87.48% | 25777 12.52% 100.00% -system.ruby.L1Cache_Controller.I_L.Persistent_GETS::total 205929 -system.ruby.L1Cache_Controller.I_L.Own_Lock_or_Unlock | 30 10.49% 10.49% | 38 13.29% 23.78% | 33 11.54% 35.31% | 35 12.24% 47.55% | 37 12.94% 60.49% | 29 10.14% 70.63% | 44 15.38% 86.01% | 40 13.99% 100.00% -system.ruby.L1Cache_Controller.I_L.Own_Lock_or_Unlock::total 286 -system.ruby.L1Cache_Controller.S_L.L1_Replacement | 39 12.79% 12.79% | 51 16.72% 29.51% | 22 7.21% 36.72% | 46 15.08% 51.80% | 26 8.52% 60.33% | 23 7.54% 67.87% | 43 14.10% 81.97% | 55 18.03% 100.00% -system.ruby.L1Cache_Controller.S_L.L1_Replacement::total 305 -system.ruby.L1Cache_Controller.S_L.Persistent_GETS | 0 0.00% 0.00% | 0 0.00% 0.00% | 3 12.00% 12.00% | 2 8.00% 20.00% | 3 12.00% 32.00% | 7 28.00% 60.00% | 3 12.00% 72.00% | 7 28.00% 100.00% -system.ruby.L1Cache_Controller.S_L.Persistent_GETS::total 25 -system.ruby.L1Cache_Controller.S_L.Own_Lock_or_Unlock | 23 11.11% 11.11% | 32 15.46% 26.57% | 31 14.98% 41.55% | 21 10.14% 51.69% | 26 12.56% 64.25% | 27 13.04% 77.29% | 27 13.04% 90.34% | 20 9.66% 100.00% -system.ruby.L1Cache_Controller.S_L.Own_Lock_or_Unlock::total 207 -system.ruby.L1Cache_Controller.IM_L.L1_Replacement | 185 11.08% 11.08% | 258 15.45% 26.53% | 235 14.07% 40.60% | 170 10.18% 50.78% | 277 16.59% 67.37% | 192 11.50% 78.86% | 184 11.02% 89.88% | 169 10.12% 100.00% -system.ruby.L1Cache_Controller.IM_L.L1_Replacement::total 1670 -system.ruby.L1Cache_Controller.IM_L.Data_All_Tokens | 1 11.11% 11.11% | 0 0.00% 11.11% | 0 0.00% 11.11% | 1 11.11% 22.22% | 2 22.22% 44.44% | 1 11.11% 55.56% | 2 22.22% 77.78% | 2 22.22% 100.00% -system.ruby.L1Cache_Controller.IM_L.Data_All_Tokens::total 9 -system.ruby.L1Cache_Controller.IM_L.Transient_Local_GETS | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.IM_L.Transient_Local_GETS::total 1 -system.ruby.L1Cache_Controller.IM_L.Persistent_GETX | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 9.09% 9.09% | 0 0.00% 9.09% | 2 18.18% 27.27% | 2 18.18% 45.45% | 4 36.36% 81.82% | 2 18.18% 100.00% -system.ruby.L1Cache_Controller.IM_L.Persistent_GETX::total 11 -system.ruby.L1Cache_Controller.IM_L.Persistent_GETS | 0 0.00% 0.00% | 1 2.86% 2.86% | 1 2.86% 5.71% | 5 14.29% 20.00% | 6 17.14% 37.14% | 5 14.29% 51.43% | 9 25.71% 77.14% | 8 22.86% 100.00% -system.ruby.L1Cache_Controller.IM_L.Persistent_GETS::total 35 -system.ruby.L1Cache_Controller.IM_L.Own_Lock_or_Unlock | 34 11.11% 11.11% | 47 15.36% 26.47% | 31 10.13% 36.60% | 31 10.13% 46.73% | 40 13.07% 59.80% | 40 13.07% 72.88% | 40 13.07% 85.95% | 43 14.05% 100.00% -system.ruby.L1Cache_Controller.IM_L.Own_Lock_or_Unlock::total 306 -system.ruby.L1Cache_Controller.IM_L.Request_Timeout | 33 7.88% 7.88% | 43 10.26% 18.14% | 55 13.13% 31.26% | 25 5.97% 37.23% | 31 7.40% 44.63% | 116 27.68% 72.32% | 63 15.04% 87.35% | 53 12.65% 100.00% -system.ruby.L1Cache_Controller.IM_L.Request_Timeout::total 419 -system.ruby.L1Cache_Controller.IS_L.L1_Replacement | 300 11.54% 11.54% | 385 14.81% 26.36% | 365 14.04% 40.40% | 361 13.89% 54.29% | 396 15.24% 69.53% | 220 8.46% 77.99% | 235 9.04% 87.03% | 337 12.97% 100.00% -system.ruby.L1Cache_Controller.IS_L.L1_Replacement::total 2599 -system.ruby.L1Cache_Controller.IS_L.Data_Shared | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.IS_L.Data_Shared::total 1 -system.ruby.L1Cache_Controller.IS_L.Data_All_Tokens | 0 0.00% 0.00% | 3 23.08% 23.08% | 2 15.38% 38.46% | 1 7.69% 46.15% | 1 7.69% 53.85% | 1 7.69% 61.54% | 2 15.38% 76.92% | 3 23.08% 100.00% -system.ruby.L1Cache_Controller.IS_L.Data_All_Tokens::total 13 -system.ruby.L1Cache_Controller.IS_L.Transient_Local_GETX | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.IS_L.Transient_Local_GETX::total 1 -system.ruby.L1Cache_Controller.IS_L.Transient_Local_GETS | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.IS_L.Transient_Local_GETS::total 1 -system.ruby.L1Cache_Controller.IS_L.Persistent_GETX | 0 0.00% 0.00% | 1 4.55% 4.55% | 0 0.00% 4.55% | 1 4.55% 9.09% | 5 22.73% 31.82% | 3 13.64% 45.45% | 7 31.82% 77.27% | 5 22.73% 100.00% -system.ruby.L1Cache_Controller.IS_L.Persistent_GETX::total 22 -system.ruby.L1Cache_Controller.IS_L.Persistent_GETS | 0 0.00% 0.00% | 4 8.00% 8.00% | 4 8.00% 16.00% | 4 8.00% 24.00% | 6 12.00% 36.00% | 10 20.00% 56.00% | 6 12.00% 68.00% | 16 32.00% 100.00% -system.ruby.L1Cache_Controller.IS_L.Persistent_GETS::total 50 -system.ruby.L1Cache_Controller.IS_L.Own_Lock_or_Unlock | 56 10.63% 10.63% | 68 12.90% 23.53% | 71 13.47% 37.00% | 69 13.09% 50.09% | 79 14.99% 65.09% | 53 10.06% 75.14% | 64 12.14% 87.29% | 67 12.71% 100.00% -system.ruby.L1Cache_Controller.IS_L.Own_Lock_or_Unlock::total 527 -system.ruby.L1Cache_Controller.IS_L.Request_Timeout | 108 14.06% 14.06% | 94 12.24% 26.30% | 144 18.75% 45.05% | 95 12.37% 57.42% | 50 6.51% 63.93% | 98 12.76% 76.69% | 65 8.46% 85.16% | 114 14.84% 100.00% -system.ruby.L1Cache_Controller.IS_L.Request_Timeout::total 768 -system.ruby.L2Cache_Controller.L1_GETS 403094 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_GETS_Last_Token 23 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_GETX 222986 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_INV 710 0.00% 0.00% -system.ruby.L2Cache_Controller.L2_Replacement 598155 0.00% 0.00% +system.ruby.L1Cache_Controller.O.Transient_Local_GETS | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.O.Transient_Local_GETS::total 1 +system.ruby.L1Cache_Controller.O.Persistent_GETX | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.O.Persistent_GETX::total 1 +system.ruby.L1Cache_Controller.O.Persistent_GETS | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 25.00% 25.00% | 0 0.00% 25.00% | 3 75.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.O.Persistent_GETS::total 4 +system.ruby.L1Cache_Controller.O.Own_Lock_or_Unlock | 8 14.81% 14.81% | 7 12.96% 27.78% | 7 12.96% 40.74% | 2 3.70% 44.44% | 5 9.26% 53.70% | 9 16.67% 70.37% | 7 12.96% 83.33% | 9 16.67% 100.00% +system.ruby.L1Cache_Controller.O.Own_Lock_or_Unlock::total 54 +system.ruby.L1Cache_Controller.M.Load | 0 0.00% 0.00% | 2 6.90% 6.90% | 7 24.14% 31.03% | 5 17.24% 48.28% | 5 17.24% 65.52% | 3 10.34% 75.86% | 2 6.90% 82.76% | 5 17.24% 100.00% +system.ruby.L1Cache_Controller.M.Load::total 29 +system.ruby.L1Cache_Controller.M.Store | 1 6.67% 6.67% | 2 13.33% 20.00% | 3 20.00% 40.00% | 2 13.33% 53.33% | 1 6.67% 60.00% | 3 20.00% 80.00% | 2 13.33% 93.33% | 1 6.67% 100.00% +system.ruby.L1Cache_Controller.M.Store::total 15 +system.ruby.L1Cache_Controller.M.L1_Replacement | 50241 12.51% 12.51% | 50317 12.53% 25.04% | 50222 12.51% 37.55% | 50111 12.48% 50.03% | 50241 12.51% 62.54% | 50069 12.47% 75.01% | 50018 12.46% 87.46% | 50338 12.54% 100.00% +system.ruby.L1Cache_Controller.M.L1_Replacement::total 401557 +system.ruby.L1Cache_Controller.M.Transient_Local_GETX | 17 11.18% 11.18% | 18 11.84% 23.03% | 22 14.47% 37.50% | 20 13.16% 50.66% | 33 21.71% 72.37% | 19 12.50% 84.87% | 8 5.26% 90.13% | 15 9.87% 100.00% +system.ruby.L1Cache_Controller.M.Transient_Local_GETX::total 152 +system.ruby.L1Cache_Controller.M.Transient_Local_GETS | 41 12.39% 12.39% | 48 14.50% 26.89% | 41 12.39% 39.27% | 44 13.29% 52.57% | 45 13.60% 66.16% | 35 10.57% 76.74% | 30 9.06% 85.80% | 47 14.20% 100.00% +system.ruby.L1Cache_Controller.M.Transient_Local_GETS::total 331 +system.ruby.L1Cache_Controller.M.Persistent_GETX | 8 12.12% 12.12% | 9 13.64% 25.76% | 6 9.09% 34.85% | 10 15.15% 50.00% | 11 16.67% 66.67% | 9 13.64% 80.30% | 7 10.61% 90.91% | 6 9.09% 100.00% +system.ruby.L1Cache_Controller.M.Persistent_GETX::total 66 +system.ruby.L1Cache_Controller.M.Persistent_GETS | 14 13.86% 13.86% | 18 17.82% 31.68% | 6 5.94% 37.62% | 18 17.82% 55.45% | 15 14.85% 70.30% | 10 9.90% 80.20% | 10 9.90% 90.10% | 10 9.90% 100.00% +system.ruby.L1Cache_Controller.M.Persistent_GETS::total 101 +system.ruby.L1Cache_Controller.M.Own_Lock_or_Unlock | 348 14.36% 14.36% | 327 13.50% 27.86% | 305 12.59% 40.45% | 299 12.34% 52.79% | 285 11.76% 64.55% | 303 12.51% 77.05% | 293 12.09% 89.15% | 263 10.85% 100.00% +system.ruby.L1Cache_Controller.M.Own_Lock_or_Unlock::total 2423 +system.ruby.L1Cache_Controller.MM.Load | 5 31.25% 31.25% | 1 6.25% 37.50% | 1 6.25% 43.75% | 4 25.00% 68.75% | 2 12.50% 81.25% | 0 0.00% 81.25% | 1 6.25% 87.50% | 2 12.50% 100.00% +system.ruby.L1Cache_Controller.MM.Load::total 16 +system.ruby.L1Cache_Controller.MM.Store | 2 25.00% 25.00% | 0 0.00% 25.00% | 3 37.50% 62.50% | 1 12.50% 75.00% | 0 0.00% 75.00% | 0 0.00% 75.00% | 0 0.00% 75.00% | 2 25.00% 100.00% +system.ruby.L1Cache_Controller.MM.Store::total 8 +system.ruby.L1Cache_Controller.MM.L1_Replacement | 28161 12.65% 12.65% | 27700 12.44% 25.08% | 27964 12.56% 37.64% | 27614 12.40% 50.04% | 27628 12.41% 62.45% | 27935 12.54% 74.99% | 28113 12.62% 87.62% | 27575 12.38% 100.00% +system.ruby.L1Cache_Controller.MM.L1_Replacement::total 222690 +system.ruby.L1Cache_Controller.MM.Transient_Local_GETX | 8 9.20% 9.20% | 11 12.64% 21.84% | 14 16.09% 37.93% | 8 9.20% 47.13% | 6 6.90% 54.02% | 14 16.09% 70.11% | 14 16.09% 86.21% | 12 13.79% 100.00% +system.ruby.L1Cache_Controller.MM.Transient_Local_GETX::total 87 +system.ruby.L1Cache_Controller.MM.Transient_Local_GETS | 25 15.34% 15.34% | 22 13.50% 28.83% | 22 13.50% 42.33% | 17 10.43% 52.76% | 16 9.82% 62.58% | 25 15.34% 77.91% | 18 11.04% 88.96% | 18 11.04% 100.00% +system.ruby.L1Cache_Controller.MM.Transient_Local_GETS::total 163 +system.ruby.L1Cache_Controller.MM.Persistent_GETX | 5 13.16% 13.16% | 5 13.16% 26.32% | 8 21.05% 47.37% | 2 5.26% 52.63% | 3 7.89% 60.53% | 2 5.26% 65.79% | 5 13.16% 78.95% | 8 21.05% 100.00% +system.ruby.L1Cache_Controller.MM.Persistent_GETX::total 38 +system.ruby.L1Cache_Controller.MM.Persistent_GETS | 8 15.09% 15.09% | 8 15.09% 30.19% | 7 13.21% 43.40% | 4 7.55% 50.94% | 4 7.55% 58.49% | 7 13.21% 71.70% | 8 15.09% 86.79% | 7 13.21% 100.00% +system.ruby.L1Cache_Controller.MM.Persistent_GETS::total 53 +system.ruby.L1Cache_Controller.MM.Own_Lock_or_Unlock | 173 13.08% 13.08% | 166 12.55% 25.62% | 133 10.05% 35.68% | 184 13.91% 49.58% | 170 12.85% 62.43% | 162 12.24% 74.68% | 142 10.73% 85.41% | 193 14.59% 100.00% +system.ruby.L1Cache_Controller.MM.Own_Lock_or_Unlock::total 1323 +system.ruby.L1Cache_Controller.M_W.Load | 5 10.87% 10.87% | 4 8.70% 19.57% | 5 10.87% 30.43% | 6 13.04% 43.48% | 8 17.39% 60.87% | 7 15.22% 76.09% | 5 10.87% 86.96% | 6 13.04% 100.00% +system.ruby.L1Cache_Controller.M_W.Load::total 46 +system.ruby.L1Cache_Controller.M_W.Store | 1 3.45% 3.45% | 4 13.79% 17.24% | 3 10.34% 27.59% | 3 10.34% 37.93% | 5 17.24% 55.17% | 4 13.79% 68.97% | 6 20.69% 89.66% | 3 10.34% 100.00% +system.ruby.L1Cache_Controller.M_W.Store::total 29 +system.ruby.L1Cache_Controller.M_W.L1_Replacement | 370210 12.51% 12.51% | 372575 12.59% 25.10% | 370139 12.51% 37.61% | 371169 12.54% 50.15% | 368462 12.45% 62.61% | 368601 12.46% 75.06% | 366548 12.39% 87.45% | 371410 12.55% 100.00% +system.ruby.L1Cache_Controller.M_W.L1_Replacement::total 2959114 +system.ruby.L1Cache_Controller.M_W.Transient_Local_GETX | 56 12.70% 12.70% | 55 12.47% 25.17% | 58 13.15% 38.32% | 57 12.93% 51.25% | 61 13.83% 65.08% | 53 12.02% 77.10% | 46 10.43% 87.53% | 55 12.47% 100.00% +system.ruby.L1Cache_Controller.M_W.Transient_Local_GETX::total 441 +system.ruby.L1Cache_Controller.M_W.Transient_Local_GETS | 84 9.81% 9.81% | 131 15.30% 25.12% | 119 13.90% 39.02% | 124 14.49% 53.50% | 103 12.03% 65.54% | 97 11.33% 76.87% | 96 11.21% 88.08% | 102 11.92% 100.00% +system.ruby.L1Cache_Controller.M_W.Transient_Local_GETS::total 856 +system.ruby.L1Cache_Controller.M_W.Persistent_GETX | 3 10.00% 10.00% | 2 6.67% 16.67% | 4 13.33% 30.00% | 3 10.00% 40.00% | 7 23.33% 63.33% | 4 13.33% 76.67% | 5 16.67% 93.33% | 2 6.67% 100.00% +system.ruby.L1Cache_Controller.M_W.Persistent_GETX::total 30 +system.ruby.L1Cache_Controller.M_W.Persistent_GETS | 2 2.38% 2.38% | 11 13.10% 15.48% | 11 13.10% 28.57% | 10 11.90% 40.48% | 7 8.33% 48.81% | 13 15.48% 64.29% | 17 20.24% 84.52% | 13 15.48% 100.00% +system.ruby.L1Cache_Controller.M_W.Persistent_GETS::total 84 +system.ruby.L1Cache_Controller.M_W.Own_Lock_or_Unlock | 440 12.63% 12.63% | 415 11.91% 24.53% | 440 12.63% 37.16% | 413 11.85% 49.01% | 428 12.28% 61.29% | 446 12.80% 74.09% | 472 13.54% 87.63% | 431 12.37% 100.00% +system.ruby.L1Cache_Controller.M_W.Own_Lock_or_Unlock::total 3485 +system.ruby.L1Cache_Controller.M_W.Use_TimeoutStarverX | 3 10.00% 10.00% | 2 6.67% 16.67% | 4 13.33% 30.00% | 3 10.00% 40.00% | 7 23.33% 63.33% | 4 13.33% 76.67% | 5 16.67% 93.33% | 2 6.67% 100.00% +system.ruby.L1Cache_Controller.M_W.Use_TimeoutStarverX::total 30 +system.ruby.L1Cache_Controller.M_W.Use_TimeoutStarverS | 2 2.20% 2.20% | 11 12.09% 14.29% | 11 12.09% 26.37% | 10 10.99% 37.36% | 9 9.89% 47.25% | 15 16.48% 63.74% | 18 19.78% 83.52% | 15 16.48% 100.00% +system.ruby.L1Cache_Controller.M_W.Use_TimeoutStarverS::total 91 +system.ruby.L1Cache_Controller.M_W.Use_TimeoutNoStarvers | 50321 12.51% 12.51% | 50412 12.53% 25.04% | 50299 12.51% 37.55% | 50203 12.48% 50.03% | 50345 12.52% 62.55% | 50143 12.47% 75.02% | 50076 12.45% 87.47% | 50415 12.53% 100.00% +system.ruby.L1Cache_Controller.M_W.Use_TimeoutNoStarvers::total 402214 +system.ruby.L1Cache_Controller.MM_W.Load | 5 17.24% 17.24% | 4 13.79% 31.03% | 2 6.90% 37.93% | 3 10.34% 48.28% | 2 6.90% 55.17% | 6 20.69% 75.86% | 2 6.90% 82.76% | 5 17.24% 100.00% +system.ruby.L1Cache_Controller.MM_W.Load::total 29 +system.ruby.L1Cache_Controller.MM_W.Store | 2 14.29% 14.29% | 2 14.29% 28.57% | 3 21.43% 50.00% | 0 0.00% 50.00% | 1 7.14% 57.14% | 2 14.29% 71.43% | 1 7.14% 78.57% | 3 21.43% 100.00% +system.ruby.L1Cache_Controller.MM_W.Store::total 14 +system.ruby.L1Cache_Controller.MM_W.L1_Replacement | 204288 12.51% 12.51% | 203606 12.47% 24.97% | 204500 12.52% 37.50% | 202849 12.42% 49.92% | 203274 12.45% 62.36% | 204548 12.52% 74.89% | 207925 12.73% 87.62% | 202241 12.38% 100.00% +system.ruby.L1Cache_Controller.MM_W.L1_Replacement::total 1633231 +system.ruby.L1Cache_Controller.MM_W.Transient_Local_GETX | 35 12.82% 12.82% | 24 8.79% 21.61% | 38 13.92% 35.53% | 36 13.19% 48.72% | 33 12.09% 60.81% | 33 12.09% 72.89% | 35 12.82% 85.71% | 39 14.29% 100.00% +system.ruby.L1Cache_Controller.MM_W.Transient_Local_GETX::total 273 +system.ruby.L1Cache_Controller.MM_W.Transient_Local_GETS | 50 10.35% 10.35% | 55 11.39% 21.74% | 62 12.84% 34.58% | 55 11.39% 45.96% | 64 13.25% 59.21% | 69 14.29% 73.50% | 61 12.63% 86.13% | 67 13.87% 100.00% +system.ruby.L1Cache_Controller.MM_W.Transient_Local_GETS::total 483 +system.ruby.L1Cache_Controller.MM_W.Persistent_GETX | 3 12.00% 12.00% | 3 12.00% 24.00% | 2 8.00% 32.00% | 4 16.00% 48.00% | 1 4.00% 52.00% | 2 8.00% 60.00% | 3 12.00% 72.00% | 7 28.00% 100.00% +system.ruby.L1Cache_Controller.MM_W.Persistent_GETX::total 25 +system.ruby.L1Cache_Controller.MM_W.Persistent_GETS | 5 11.36% 11.36% | 5 11.36% 22.73% | 4 9.09% 31.82% | 3 6.82% 38.64% | 3 6.82% 45.45% | 10 22.73% 68.18% | 5 11.36% 79.55% | 9 20.45% 100.00% +system.ruby.L1Cache_Controller.MM_W.Persistent_GETS::total 44 +system.ruby.L1Cache_Controller.MM_W.Own_Lock_or_Unlock | 266 13.73% 13.73% | 227 11.72% 25.45% | 273 14.09% 39.55% | 235 12.13% 51.68% | 237 12.24% 63.91% | 234 12.08% 75.99% | 225 11.62% 87.61% | 240 12.39% 100.00% +system.ruby.L1Cache_Controller.MM_W.Own_Lock_or_Unlock::total 1937 +system.ruby.L1Cache_Controller.MM_W.Use_TimeoutStarverX | 3 11.54% 11.54% | 3 11.54% 23.08% | 2 7.69% 30.77% | 4 15.38% 46.15% | 1 3.85% 50.00% | 2 7.69% 57.69% | 3 11.54% 69.23% | 8 30.77% 100.00% +system.ruby.L1Cache_Controller.MM_W.Use_TimeoutStarverX::total 26 +system.ruby.L1Cache_Controller.MM_W.Use_TimeoutStarverS | 5 11.11% 11.11% | 6 13.33% 24.44% | 4 8.89% 33.33% | 3 6.67% 40.00% | 3 6.67% 46.67% | 10 22.22% 68.89% | 5 11.11% 80.00% | 9 20.00% 100.00% +system.ruby.L1Cache_Controller.MM_W.Use_TimeoutStarverS::total 45 +system.ruby.L1Cache_Controller.MM_W.Use_TimeoutNoStarvers | 28207 12.65% 12.65% | 27744 12.44% 25.09% | 28012 12.56% 37.65% | 27643 12.39% 50.04% | 27656 12.40% 62.44% | 27980 12.55% 74.99% | 28157 12.63% 87.62% | 27619 12.38% 100.00% +system.ruby.L1Cache_Controller.MM_W.Use_TimeoutNoStarvers::total 223018 +system.ruby.L1Cache_Controller.IM.L1_Replacement | 297233 12.73% 12.73% | 289886 12.42% 25.15% | 289674 12.41% 37.56% | 288888 12.37% 49.93% | 292575 12.53% 62.46% | 292468 12.53% 74.99% | 295557 12.66% 87.65% | 288386 12.35% 100.00% +system.ruby.L1Cache_Controller.IM.L1_Replacement::total 2334667 +system.ruby.L1Cache_Controller.IM.Data_Owner | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 33.33% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 1 33.33% 66.67% | 1 33.33% 100.00% +system.ruby.L1Cache_Controller.IM.Data_Owner::total 3 +system.ruby.L1Cache_Controller.IM.Data_All_Tokens | 28214 12.65% 12.65% | 27748 12.44% 25.09% | 28014 12.56% 37.65% | 27648 12.40% 50.04% | 27655 12.40% 62.44% | 27988 12.55% 74.99% | 28158 12.62% 87.61% | 27632 12.39% 100.00% +system.ruby.L1Cache_Controller.IM.Data_All_Tokens::total 223057 +system.ruby.L1Cache_Controller.IM.Ack | 1 20.00% 20.00% | 0 0.00% 20.00% | 0 0.00% 20.00% | 0 0.00% 20.00% | 1 20.00% 40.00% | 1 20.00% 60.00% | 0 0.00% 60.00% | 2 40.00% 100.00% +system.ruby.L1Cache_Controller.IM.Ack::total 5 +system.ruby.L1Cache_Controller.IM.Transient_Local_GETX | 97 13.80% 13.80% | 99 14.08% 27.88% | 72 10.24% 38.12% | 102 14.51% 52.63% | 79 11.24% 63.87% | 86 12.23% 76.10% | 72 10.24% 86.34% | 96 13.66% 100.00% +system.ruby.L1Cache_Controller.IM.Transient_Local_GETX::total 703 +system.ruby.L1Cache_Controller.IM.Transient_Local_GETS | 157 12.07% 12.07% | 146 11.22% 23.29% | 173 13.30% 36.59% | 141 10.84% 47.43% | 168 12.91% 60.34% | 186 14.30% 74.63% | 157 12.07% 86.70% | 173 13.30% 100.00% +system.ruby.L1Cache_Controller.IM.Transient_Local_GETS::total 1301 +system.ruby.L1Cache_Controller.IM.Persistent_GETX | 6 12.00% 12.00% | 5 10.00% 22.00% | 5 10.00% 32.00% | 5 10.00% 42.00% | 6 12.00% 54.00% | 9 18.00% 72.00% | 9 18.00% 90.00% | 5 10.00% 100.00% +system.ruby.L1Cache_Controller.IM.Persistent_GETX::total 50 +system.ruby.L1Cache_Controller.IM.Persistent_GETS | 11 10.48% 10.48% | 13 12.38% 22.86% | 17 16.19% 39.05% | 10 9.52% 48.57% | 13 12.38% 60.95% | 15 14.29% 75.24% | 13 12.38% 87.62% | 13 12.38% 100.00% +system.ruby.L1Cache_Controller.IM.Persistent_GETS::total 105 +system.ruby.L1Cache_Controller.IM.Own_Lock_or_Unlock | 1706 12.40% 12.40% | 1723 12.52% 24.92% | 1721 12.51% 37.43% | 1759 12.78% 50.21% | 1740 12.65% 62.86% | 1764 12.82% 75.68% | 1632 11.86% 87.54% | 1715 12.46% 100.00% +system.ruby.L1Cache_Controller.IM.Own_Lock_or_Unlock::total 13760 +system.ruby.L1Cache_Controller.IM.Request_Timeout | 11760 12.12% 12.12% | 12506 12.89% 25.02% | 12482 12.87% 37.89% | 12270 12.65% 50.54% | 11911 12.28% 62.82% | 11774 12.14% 74.96% | 11971 12.34% 87.30% | 12321 12.70% 100.00% +system.ruby.L1Cache_Controller.IM.Request_Timeout::total 96995 +system.ruby.L1Cache_Controller.OM.L1_Replacement | 0 0.00% 0.00% | 0 0.00% 0.00% | 24 63.16% 63.16% | 0 0.00% 63.16% | 0 0.00% 63.16% | 0 0.00% 63.16% | 2 5.26% 68.42% | 12 31.58% 100.00% +system.ruby.L1Cache_Controller.OM.L1_Replacement::total 38 +system.ruby.L1Cache_Controller.OM.Ack_All_Tokens | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 33.33% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 1 33.33% 66.67% | 1 33.33% 100.00% +system.ruby.L1Cache_Controller.OM.Ack_All_Tokens::total 3 +system.ruby.L1Cache_Controller.OM.Own_Lock_or_Unlock | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 1 50.00% 100.00% +system.ruby.L1Cache_Controller.OM.Own_Lock_or_Unlock::total 2 +system.ruby.L1Cache_Controller.OM.Request_Timeout | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 1 50.00% 100.00% +system.ruby.L1Cache_Controller.OM.Request_Timeout::total 2 +system.ruby.L1Cache_Controller.IS.L1_Replacement | 529103 12.51% 12.51% | 530672 12.54% 25.05% | 533381 12.61% 37.66% | 528913 12.50% 50.16% | 528203 12.49% 62.65% | 526767 12.45% 75.10% | 522401 12.35% 87.45% | 531078 12.55% 100.00% +system.ruby.L1Cache_Controller.IS.L1_Replacement::total 4230518 +system.ruby.L1Cache_Controller.IS.Data_Shared | 182 12.74% 12.74% | 180 12.60% 25.33% | 177 12.39% 37.72% | 176 12.32% 50.03% | 184 12.88% 62.91% | 172 12.04% 74.95% | 179 12.53% 87.47% | 179 12.53% 100.00% +system.ruby.L1Cache_Controller.IS.Data_Shared::total 1429 +system.ruby.L1Cache_Controller.IS.Data_Owner | 23 11.39% 11.39% | 31 15.35% 26.73% | 30 14.85% 41.58% | 19 9.41% 50.99% | 27 13.37% 64.36% | 21 10.40% 74.75% | 26 12.87% 87.62% | 25 12.38% 100.00% +system.ruby.L1Cache_Controller.IS.Data_Owner::total 202 +system.ruby.L1Cache_Controller.IS.Data_All_Tokens | 50326 12.51% 12.51% | 50430 12.53% 25.04% | 50318 12.51% 37.55% | 50220 12.48% 50.03% | 50365 12.52% 62.55% | 50164 12.47% 75.01% | 50104 12.45% 87.47% | 50434 12.53% 100.00% +system.ruby.L1Cache_Controller.IS.Data_All_Tokens::total 402361 +system.ruby.L1Cache_Controller.IS.Transient_Local_GETX | 166 13.17% 13.17% | 158 12.54% 25.71% | 158 12.54% 38.25% | 143 11.35% 49.60% | 183 14.52% 64.13% | 147 11.67% 75.79% | 148 11.75% 87.54% | 157 12.46% 100.00% +system.ruby.L1Cache_Controller.IS.Transient_Local_GETX::total 1260 +system.ruby.L1Cache_Controller.IS.Transient_Local_GETS | 290 12.11% 12.11% | 316 13.19% 25.30% | 302 12.61% 37.91% | 301 12.57% 50.48% | 323 13.49% 63.97% | 281 11.73% 75.70% | 277 11.57% 87.27% | 305 12.73% 100.00% +system.ruby.L1Cache_Controller.IS.Transient_Local_GETS::total 2395 +system.ruby.L1Cache_Controller.IS.Persistent_GETX | 7 6.93% 6.93% | 24 23.76% 30.69% | 15 14.85% 45.54% | 11 10.89% 56.44% | 13 12.87% 69.31% | 15 14.85% 84.16% | 9 8.91% 93.07% | 7 6.93% 100.00% +system.ruby.L1Cache_Controller.IS.Persistent_GETX::total 101 +system.ruby.L1Cache_Controller.IS.Persistent_GETS | 30 13.39% 13.39% | 30 13.39% 26.79% | 30 13.39% 40.18% | 19 8.48% 48.66% | 28 12.50% 61.16% | 24 10.71% 71.88% | 31 13.84% 85.71% | 32 14.29% 100.00% +system.ruby.L1Cache_Controller.IS.Persistent_GETS::total 224 +system.ruby.L1Cache_Controller.IS.Own_Lock_or_Unlock | 3245 12.99% 12.99% | 3160 12.65% 25.63% | 3132 12.53% 38.17% | 3085 12.35% 50.51% | 3159 12.64% 63.15% | 3121 12.49% 75.64% | 3072 12.29% 87.94% | 3014 12.06% 100.00% +system.ruby.L1Cache_Controller.IS.Own_Lock_or_Unlock::total 24988 +system.ruby.L1Cache_Controller.IS.Request_Timeout | 21713 12.50% 12.50% | 21677 12.48% 24.98% | 21741 12.52% 37.50% | 21122 12.16% 49.66% | 22600 13.01% 62.67% | 21444 12.35% 75.02% | 22164 12.76% 87.78% | 21223 12.22% 100.00% +system.ruby.L1Cache_Controller.IS.Request_Timeout::total 173684 +system.ruby.L1Cache_Controller.I_L.Load | 25 12.63% 12.63% | 17 8.59% 21.21% | 18 9.09% 30.30% | 26 13.13% 43.43% | 29 14.65% 58.08% | 20 10.10% 68.18% | 26 13.13% 81.31% | 37 18.69% 100.00% +system.ruby.L1Cache_Controller.I_L.Load::total 198 +system.ruby.L1Cache_Controller.I_L.Store | 13 11.61% 11.61% | 7 6.25% 17.86% | 15 13.39% 31.25% | 17 15.18% 46.43% | 15 13.39% 59.82% | 18 16.07% 75.89% | 16 14.29% 90.18% | 11 9.82% 100.00% +system.ruby.L1Cache_Controller.I_L.Store::total 112 +system.ruby.L1Cache_Controller.I_L.L1_Replacement | 95 7.85% 7.85% | 180 14.88% 22.73% | 131 10.83% 33.55% | 79 6.53% 40.08% | 151 12.48% 52.56% | 218 18.02% 70.58% | 150 12.40% 82.98% | 206 17.02% 100.00% +system.ruby.L1Cache_Controller.I_L.L1_Replacement::total 1210 +system.ruby.L1Cache_Controller.I_L.Data_All_Tokens | 18 17.14% 17.14% | 23 21.90% 39.05% | 11 10.48% 49.52% | 15 14.29% 63.81% | 10 9.52% 73.33% | 12 11.43% 84.76% | 7 6.67% 91.43% | 9 8.57% 100.00% +system.ruby.L1Cache_Controller.I_L.Data_All_Tokens::total 105 +system.ruby.L1Cache_Controller.I_L.Transient_Local_GETX | 97 13.84% 13.84% | 95 13.55% 27.39% | 83 11.84% 39.23% | 85 12.13% 51.36% | 87 12.41% 63.77% | 78 11.13% 74.89% | 90 12.84% 87.73% | 86 12.27% 100.00% +system.ruby.L1Cache_Controller.I_L.Transient_Local_GETX::total 701 +system.ruby.L1Cache_Controller.I_L.Transient_Local_GETS | 144 12.85% 12.85% | 138 12.31% 25.16% | 149 13.29% 38.45% | 135 12.04% 50.49% | 137 12.22% 62.71% | 142 12.67% 75.38% | 140 12.49% 87.87% | 136 12.13% 100.00% +system.ruby.L1Cache_Controller.I_L.Transient_Local_GETS::total 1121 +system.ruby.L1Cache_Controller.I_L.Persistent_GETX | 13750 12.50% 12.50% | 13751 12.50% 25.01% | 13711 12.47% 37.47% | 13722 12.48% 49.95% | 13734 12.49% 62.44% | 13710 12.47% 74.90% | 13851 12.59% 87.50% | 13752 12.50% 100.00% +system.ruby.L1Cache_Controller.I_L.Persistent_GETX::total 109981 +system.ruby.L1Cache_Controller.I_L.Persistent_GETS | 24873 12.45% 12.45% | 24947 12.49% 24.94% | 24964 12.50% 37.43% | 25049 12.54% 49.97% | 24936 12.48% 62.45% | 24961 12.49% 74.95% | 24980 12.50% 87.45% | 25073 12.55% 100.00% +system.ruby.L1Cache_Controller.I_L.Persistent_GETS::total 199783 +system.ruby.L1Cache_Controller.I_L.Own_Lock_or_Unlock | 33 12.45% 12.45% | 33 12.45% 24.91% | 32 12.08% 36.98% | 27 10.19% 47.17% | 31 11.70% 58.87% | 35 13.21% 72.08% | 33 12.45% 84.53% | 41 15.47% 100.00% +system.ruby.L1Cache_Controller.I_L.Own_Lock_or_Unlock::total 265 +system.ruby.L1Cache_Controller.S_L.L1_Replacement | 38 11.55% 11.55% | 61 18.54% 30.09% | 26 7.90% 37.99% | 51 15.50% 53.50% | 62 18.84% 72.34% | 10 3.04% 75.38% | 62 18.84% 94.22% | 19 5.78% 100.00% +system.ruby.L1Cache_Controller.S_L.L1_Replacement::total 329 +system.ruby.L1Cache_Controller.S_L.Data_All_Tokens | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.S_L.Data_All_Tokens::total 1 +system.ruby.L1Cache_Controller.S_L.Persistent_GETS | 0 0.00% 0.00% | 1 2.94% 2.94% | 2 5.88% 8.82% | 1 2.94% 11.76% | 7 20.59% 32.35% | 8 23.53% 55.88% | 9 26.47% 82.35% | 6 17.65% 100.00% +system.ruby.L1Cache_Controller.S_L.Persistent_GETS::total 34 +system.ruby.L1Cache_Controller.S_L.Own_Lock_or_Unlock | 17 8.50% 8.50% | 29 14.50% 23.00% | 18 9.00% 32.00% | 29 14.50% 46.50% | 27 13.50% 60.00% | 26 13.00% 73.00% | 29 14.50% 87.50% | 25 12.50% 100.00% +system.ruby.L1Cache_Controller.S_L.Own_Lock_or_Unlock::total 200 +system.ruby.L1Cache_Controller.IM_L.L1_Replacement | 166 11.01% 11.01% | 156 10.34% 21.35% | 235 15.58% 36.94% | 157 10.41% 47.35% | 147 9.75% 57.10% | 250 16.58% 73.67% | 227 15.05% 88.73% | 170 11.27% 100.00% +system.ruby.L1Cache_Controller.IM_L.L1_Replacement::total 1508 +system.ruby.L1Cache_Controller.IM_L.Data_All_Tokens | 0 0.00% 0.00% | 1 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 1 50.00% 100.00% +system.ruby.L1Cache_Controller.IM_L.Data_All_Tokens::total 2 +system.ruby.L1Cache_Controller.IM_L.Persistent_GETX | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 14.29% 14.29% | 0 0.00% 14.29% | 0 0.00% 14.29% | 0 0.00% 14.29% | 4 57.14% 71.43% | 2 28.57% 100.00% +system.ruby.L1Cache_Controller.IM_L.Persistent_GETX::total 7 +system.ruby.L1Cache_Controller.IM_L.Persistent_GETS | 0 0.00% 0.00% | 1 4.55% 4.55% | 1 4.55% 9.09% | 4 18.18% 27.27% | 1 4.55% 31.82% | 6 27.27% 59.09% | 3 13.64% 72.73% | 6 27.27% 100.00% +system.ruby.L1Cache_Controller.IM_L.Persistent_GETS::total 22 +system.ruby.L1Cache_Controller.IM_L.Own_Lock_or_Unlock | 30 11.32% 11.32% | 24 9.06% 20.38% | 37 13.96% 34.34% | 32 12.08% 46.42% | 34 12.83% 59.25% | 42 15.85% 75.09% | 38 14.34% 89.43% | 28 10.57% 100.00% +system.ruby.L1Cache_Controller.IM_L.Own_Lock_or_Unlock::total 265 +system.ruby.L1Cache_Controller.IM_L.Request_Timeout | 24 6.11% 6.11% | 43 10.94% 17.05% | 48 12.21% 29.26% | 26 6.62% 35.88% | 18 4.58% 40.46% | 66 16.79% 57.25% | 138 35.11% 92.37% | 30 7.63% 100.00% +system.ruby.L1Cache_Controller.IM_L.Request_Timeout::total 393 +system.ruby.L1Cache_Controller.IS_L.L1_Replacement | 210 8.70% 8.70% | 363 15.04% 23.74% | 263 10.89% 34.63% | 225 9.32% 43.95% | 282 11.68% 55.63% | 363 15.04% 70.67% | 336 13.92% 84.59% | 372 15.41% 100.00% +system.ruby.L1Cache_Controller.IS_L.L1_Replacement::total 2414 +system.ruby.L1Cache_Controller.IS_L.Data_Shared | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 33.33% 33.33% | 0 0.00% 33.33% | 1 33.33% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 1 33.33% 100.00% +system.ruby.L1Cache_Controller.IS_L.Data_Shared::total 3 +system.ruby.L1Cache_Controller.IS_L.Data_All_Tokens | 1 12.50% 12.50% | 0 0.00% 12.50% | 0 0.00% 12.50% | 0 0.00% 12.50% | 2 25.00% 37.50% | 2 25.00% 62.50% | 1 12.50% 75.00% | 2 25.00% 100.00% +system.ruby.L1Cache_Controller.IS_L.Data_All_Tokens::total 8 +system.ruby.L1Cache_Controller.IS_L.Transient_Local_GETS | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.IS_L.Transient_Local_GETS::total 2 +system.ruby.L1Cache_Controller.IS_L.Persistent_GETX | 0 0.00% 0.00% | 2 9.52% 9.52% | 4 19.05% 28.57% | 3 14.29% 42.86% | 1 4.76% 47.62% | 3 14.29% 61.90% | 1 4.76% 66.67% | 7 33.33% 100.00% +system.ruby.L1Cache_Controller.IS_L.Persistent_GETX::total 21 +system.ruby.L1Cache_Controller.IS_L.Persistent_GETS | 0 0.00% 0.00% | 1 2.44% 2.44% | 1 2.44% 4.88% | 5 12.20% 17.07% | 11 26.83% 43.90% | 5 12.20% 56.10% | 9 21.95% 78.05% | 9 21.95% 100.00% +system.ruby.L1Cache_Controller.IS_L.Persistent_GETS::total 41 +system.ruby.L1Cache_Controller.IS_L.Own_Lock_or_Unlock | 61 11.91% 11.91% | 71 13.87% 25.78% | 62 12.11% 37.89% | 56 10.94% 48.83% | 67 13.09% 61.91% | 57 11.13% 73.05% | 65 12.70% 85.74% | 73 14.26% 100.00% +system.ruby.L1Cache_Controller.IS_L.Own_Lock_or_Unlock::total 512 +system.ruby.L1Cache_Controller.IS_L.Request_Timeout | 122 15.66% 15.66% | 80 10.27% 25.93% | 163 20.92% 46.85% | 39 5.01% 51.86% | 125 16.05% 67.91% | 143 18.36% 86.26% | 73 9.37% 95.64% | 34 4.36% 100.00% +system.ruby.L1Cache_Controller.IS_L.Request_Timeout::total 779 +system.ruby.L2Cache_Controller.L1_GETS 403983 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_GETS_Last_Token 34 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_GETX 223069 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_INV 668 0.00% 0.00% +system.ruby.L2Cache_Controller.L2_Replacement 599911 0.00% 0.00% system.ruby.L2Cache_Controller.Writeback_Shared_Data 988 0.00% 0.00% -system.ruby.L2Cache_Controller.Writeback_All_Tokens 623923 0.00% 0.00% +system.ruby.L2Cache_Controller.Writeback_All_Tokens 624946 0.00% 0.00% system.ruby.L2Cache_Controller.Writeback_Owned 455 0.00% 0.00% -system.ruby.L2Cache_Controller.Persistent_GETX 16161 0.00% 0.00% -system.ruby.L2Cache_Controller.Persistent_GETS 29526 0.00% 0.00% -system.ruby.L2Cache_Controller.Persistent_GETS_Last_Token 3 0.00% 0.00% -system.ruby.L2Cache_Controller.Own_Lock_or_Unlock 45286 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.L1_GETS 401858 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.L1_GETX 222292 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.L1_INV 514 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.Writeback_Shared_Data 918 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.Writeback_All_Tokens 596876 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.Writeback_Owned 369 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.Own_Lock_or_Unlock 38185 0.00% 0.00% -system.ruby.L2Cache_Controller.I.L1_GETS 48 0.00% 0.00% -system.ruby.L2Cache_Controller.I.L1_GETX 20 0.00% 0.00% -system.ruby.L2Cache_Controller.I.L2_Replacement 7228 0.00% 0.00% -system.ruby.L2Cache_Controller.I.Writeback_All_Tokens 471 0.00% 0.00% -system.ruby.L2Cache_Controller.I.Writeback_Owned 6 0.00% 0.00% -system.ruby.L2Cache_Controller.I.Persistent_GETX 15 0.00% 0.00% -system.ruby.L2Cache_Controller.I.Persistent_GETS 24 0.00% 0.00% -system.ruby.L2Cache_Controller.S.L1_GETS_Last_Token 23 0.00% 0.00% -system.ruby.L2Cache_Controller.S.L2_Replacement 848 0.00% 0.00% -system.ruby.L2Cache_Controller.S.Writeback_Shared_Data 3 0.00% 0.00% -system.ruby.L2Cache_Controller.S.Writeback_All_Tokens 55 0.00% 0.00% -system.ruby.L2Cache_Controller.S.Writeback_Owned 2 0.00% 0.00% -system.ruby.L2Cache_Controller.S.Persistent_GETS 3 0.00% 0.00% -system.ruby.L2Cache_Controller.S.Persistent_GETS_Last_Token 1 0.00% 0.00% -system.ruby.L2Cache_Controller.O.L1_GETS 19 0.00% 0.00% -system.ruby.L2Cache_Controller.O.L2_Replacement 879 0.00% 0.00% -system.ruby.L2Cache_Controller.O.Writeback_Shared_Data 3 0.00% 0.00% -system.ruby.L2Cache_Controller.O.Writeback_All_Tokens 593 0.00% 0.00% -system.ruby.L2Cache_Controller.O.Persistent_GETX 2 0.00% 0.00% -system.ruby.L2Cache_Controller.O.Persistent_GETS 11 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L1_GETS 1108 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L1_GETX 634 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L2_Replacement 588428 0.00% 0.00% -system.ruby.L2Cache_Controller.M.Persistent_GETX 2726 0.00% 0.00% -system.ruby.L2Cache_Controller.M.Persistent_GETS 5091 0.00% 0.00% -system.ruby.L2Cache_Controller.I_L.L1_GETS 61 0.00% 0.00% -system.ruby.L2Cache_Controller.I_L.L1_GETX 40 0.00% 0.00% -system.ruby.L2Cache_Controller.I_L.L1_INV 196 0.00% 0.00% -system.ruby.L2Cache_Controller.I_L.L2_Replacement 771 0.00% 0.00% -system.ruby.L2Cache_Controller.I_L.Writeback_Shared_Data 64 0.00% 0.00% -system.ruby.L2Cache_Controller.I_L.Writeback_All_Tokens 25928 0.00% 0.00% -system.ruby.L2Cache_Controller.I_L.Writeback_Owned 78 0.00% 0.00% -system.ruby.L2Cache_Controller.I_L.Persistent_GETX 13418 0.00% 0.00% -system.ruby.L2Cache_Controller.I_L.Persistent_GETS 24397 0.00% 0.00% -system.ruby.L2Cache_Controller.I_L.Own_Lock_or_Unlock 7087 0.00% 0.00% -system.ruby.L2Cache_Controller.S_L.L2_Replacement 1 0.00% 0.00% -system.ruby.L2Cache_Controller.S_L.Persistent_GETS_Last_Token 2 0.00% 0.00% -system.ruby.L2Cache_Controller.S_L.Own_Lock_or_Unlock 14 0.00% 0.00% -system.ruby.Directory_Controller.GETX 238416 0.00% 0.00% -system.ruby.Directory_Controller.GETS 430906 0.00% 0.00% -system.ruby.Directory_Controller.Lockdown 45690 0.00% 0.00% -system.ruby.Directory_Controller.Unlockdown 45286 0.00% 0.00% -system.ruby.Directory_Controller.Data_Owner 310 0.00% 0.00% -system.ruby.Directory_Controller.Data_All_Tokens 243497 0.00% 0.00% -system.ruby.Directory_Controller.Ack_Owner 539 0.00% 0.00% -system.ruby.Directory_Controller.Ack_Owner_All_Tokens 377964 0.00% 0.00% -system.ruby.Directory_Controller.Tokens 139 0.00% 0.00% -system.ruby.Directory_Controller.Ack_All_Tokens 778 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Data 621933 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Ack 243403 0.00% 0.00% -system.ruby.Directory_Controller.O.GETX 219960 0.00% 0.00% -system.ruby.Directory_Controller.O.GETS 397659 0.00% 0.00% -system.ruby.Directory_Controller.O.Lockdown 3830 0.00% 0.00% -system.ruby.Directory_Controller.O.Data_All_Tokens 61 0.00% 0.00% -system.ruby.Directory_Controller.O.Tokens 9 0.00% 0.00% -system.ruby.Directory_Controller.O.Ack_All_Tokens 769 0.00% 0.00% -system.ruby.Directory_Controller.NO.GETX 2247 0.00% 0.00% -system.ruby.Directory_Controller.NO.GETS 4060 0.00% 0.00% -system.ruby.Directory_Controller.NO.Lockdown 17747 0.00% 0.00% -system.ruby.Directory_Controller.NO.Data_Owner 309 0.00% 0.00% -system.ruby.Directory_Controller.NO.Data_All_Tokens 243096 0.00% 0.00% -system.ruby.Directory_Controller.NO.Ack_Owner 538 0.00% 0.00% -system.ruby.Directory_Controller.NO.Ack_Owner_All_Tokens 377582 0.00% 0.00% -system.ruby.Directory_Controller.NO.Tokens 129 0.00% 0.00% -system.ruby.Directory_Controller.L.GETX 143 0.00% 0.00% -system.ruby.Directory_Controller.L.GETS 246 0.00% 0.00% -system.ruby.Directory_Controller.L.Lockdown 355 0.00% 0.00% -system.ruby.Directory_Controller.L.Unlockdown 45285 0.00% 0.00% -system.ruby.Directory_Controller.L.Data_Owner 1 0.00% 0.00% -system.ruby.Directory_Controller.L.Data_All_Tokens 305 0.00% 0.00% -system.ruby.Directory_Controller.L.Ack_Owner 1 0.00% 0.00% -system.ruby.Directory_Controller.L.Ack_Owner_All_Tokens 382 0.00% 0.00% -system.ruby.Directory_Controller.O_W.GETX 63 0.00% 0.00% -system.ruby.Directory_Controller.O_W.GETS 106 0.00% 0.00% -system.ruby.Directory_Controller.O_W.Lockdown 111 0.00% 0.00% -system.ruby.Directory_Controller.O_W.Data_All_Tokens 35 0.00% 0.00% -system.ruby.Directory_Controller.O_W.Tokens 1 0.00% 0.00% -system.ruby.Directory_Controller.O_W.Memory_Data 1 0.00% 0.00% -system.ruby.Directory_Controller.O_W.Memory_Ack 243292 0.00% 0.00% -system.ruby.Directory_Controller.L_O_W.GETX 54 0.00% 0.00% -system.ruby.Directory_Controller.L_O_W.GETS 94 0.00% 0.00% -system.ruby.Directory_Controller.L_O_W.Lockdown 12 0.00% 0.00% -system.ruby.Directory_Controller.L_O_W.Unlockdown 1 0.00% 0.00% -system.ruby.Directory_Controller.L_O_W.Memory_Data 4323 0.00% 0.00% -system.ruby.Directory_Controller.L_O_W.Memory_Ack 111 0.00% 0.00% -system.ruby.Directory_Controller.L_NO_W.GETX 508 0.00% 0.00% -system.ruby.Directory_Controller.L_NO_W.GETS 910 0.00% 0.00% -system.ruby.Directory_Controller.L_NO_W.Lockdown 37 0.00% 0.00% -system.ruby.Directory_Controller.L_NO_W.Memory_Data 23598 0.00% 0.00% -system.ruby.Directory_Controller.NO_W.GETX 15441 0.00% 0.00% -system.ruby.Directory_Controller.NO_W.GETS 27831 0.00% 0.00% -system.ruby.Directory_Controller.NO_W.Lockdown 23598 0.00% 0.00% -system.ruby.Directory_Controller.NO_W.Ack_All_Tokens 9 0.00% 0.00% -system.ruby.Directory_Controller.NO_W.Memory_Data 594011 0.00% 0.00% +system.ruby.L2Cache_Controller.Persistent_GETX 15761 0.00% 0.00% +system.ruby.L2Cache_Controller.Persistent_GETS 28642 0.00% 0.00% +system.ruby.L2Cache_Controller.Own_Lock_or_Unlock 44053 0.00% 0.00% +system.ruby.L2Cache_Controller.NP.L1_GETS 402707 0.00% 0.00% +system.ruby.L2Cache_Controller.NP.L1_GETX 222334 0.00% 0.00% +system.ruby.L2Cache_Controller.NP.L1_INV 488 0.00% 0.00% +system.ruby.L2Cache_Controller.NP.Writeback_Shared_Data 916 0.00% 0.00% +system.ruby.L2Cache_Controller.NP.Writeback_All_Tokens 598635 0.00% 0.00% +system.ruby.L2Cache_Controller.NP.Writeback_Owned 368 0.00% 0.00% +system.ruby.L2Cache_Controller.NP.Own_Lock_or_Unlock 36593 0.00% 0.00% +system.ruby.L2Cache_Controller.I.L1_GETS 55 0.00% 0.00% +system.ruby.L2Cache_Controller.I.L1_GETX 24 0.00% 0.00% +system.ruby.L2Cache_Controller.I.L1_INV 2 0.00% 0.00% +system.ruby.L2Cache_Controller.I.L2_Replacement 7638 0.00% 0.00% +system.ruby.L2Cache_Controller.I.Writeback_Shared_Data 4 0.00% 0.00% +system.ruby.L2Cache_Controller.I.Writeback_All_Tokens 472 0.00% 0.00% +system.ruby.L2Cache_Controller.I.Writeback_Owned 15 0.00% 0.00% +system.ruby.L2Cache_Controller.I.Persistent_GETX 2 0.00% 0.00% +system.ruby.L2Cache_Controller.I.Persistent_GETS 16 0.00% 0.00% +system.ruby.L2Cache_Controller.S.L1_GETS_Last_Token 34 0.00% 0.00% +system.ruby.L2Cache_Controller.S.L2_Replacement 821 0.00% 0.00% +system.ruby.L2Cache_Controller.S.Writeback_Shared_Data 5 0.00% 0.00% +system.ruby.L2Cache_Controller.S.Writeback_All_Tokens 71 0.00% 0.00% +system.ruby.L2Cache_Controller.S.Writeback_Owned 1 0.00% 0.00% +system.ruby.L2Cache_Controller.S.Persistent_GETX 1 0.00% 0.00% +system.ruby.L2Cache_Controller.S.Persistent_GETS 1 0.00% 0.00% +system.ruby.L2Cache_Controller.O.L1_GETS 21 0.00% 0.00% +system.ruby.L2Cache_Controller.O.L1_GETX 3 0.00% 0.00% +system.ruby.L2Cache_Controller.O.L2_Replacement 877 0.00% 0.00% +system.ruby.L2Cache_Controller.O.Writeback_Shared_Data 1 0.00% 0.00% +system.ruby.L2Cache_Controller.O.Writeback_All_Tokens 628 0.00% 0.00% +system.ruby.L2Cache_Controller.O.Persistent_GETS 8 0.00% 0.00% +system.ruby.L2Cache_Controller.M.L1_GETS 1132 0.00% 0.00% +system.ruby.L2Cache_Controller.M.L1_GETX 659 0.00% 0.00% +system.ruby.L2Cache_Controller.M.L2_Replacement 589830 0.00% 0.00% +system.ruby.L2Cache_Controller.M.Persistent_GETX 2834 0.00% 0.00% +system.ruby.L2Cache_Controller.M.Persistent_GETS 5343 0.00% 0.00% +system.ruby.L2Cache_Controller.I_L.L1_GETS 68 0.00% 0.00% +system.ruby.L2Cache_Controller.I_L.L1_GETX 49 0.00% 0.00% +system.ruby.L2Cache_Controller.I_L.L1_INV 178 0.00% 0.00% +system.ruby.L2Cache_Controller.I_L.L2_Replacement 745 0.00% 0.00% +system.ruby.L2Cache_Controller.I_L.Writeback_Shared_Data 62 0.00% 0.00% +system.ruby.L2Cache_Controller.I_L.Writeback_All_Tokens 25140 0.00% 0.00% +system.ruby.L2Cache_Controller.I_L.Writeback_Owned 71 0.00% 0.00% +system.ruby.L2Cache_Controller.I_L.Persistent_GETX 12924 0.00% 0.00% +system.ruby.L2Cache_Controller.I_L.Persistent_GETS 23274 0.00% 0.00% +system.ruby.L2Cache_Controller.I_L.Own_Lock_or_Unlock 7451 0.00% 0.00% +system.ruby.L2Cache_Controller.S_L.Own_Lock_or_Unlock 9 0.00% 0.00% ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt index 03a62fad6..c6e069465 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt @@ -1,48 +1,48 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.004762 # Number of seconds simulated -sim_ticks 4761781 # Number of ticks simulated -final_tick 4761781 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.004718 # Number of seconds simulated +sim_ticks 4717737 # Number of ticks simulated +final_tick 4717737 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 26949 # Simulator tick rate (ticks/s) -host_mem_usage 651208 # Number of bytes of host memory used -host_seconds 176.70 # Real time elapsed on the host +host_tick_rate 46146 # Simulator tick rate (ticks/s) +host_mem_usage 663608 # Number of bytes of host memory used +host_seconds 102.24 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks -system.mem_ctrls.bytes_read::ruby.dir_cntrl0 38848448 # Number of bytes read from this memory -system.mem_ctrls.bytes_read::total 38848448 # Number of bytes read from this memory -system.mem_ctrls.bytes_written::ruby.dir_cntrl0 14135424 # Number of bytes written to this memory -system.mem_ctrls.bytes_written::total 14135424 # Number of bytes written to this memory -system.mem_ctrls.num_reads::ruby.dir_cntrl0 607007 # Number of read requests responded to by this memory -system.mem_ctrls.num_reads::total 607007 # Number of read requests responded to by this memory -system.mem_ctrls.num_writes::ruby.dir_cntrl0 220866 # Number of write requests responded to by this memory -system.mem_ctrls.num_writes::total 220866 # Number of write requests responded to by this memory -system.mem_ctrls.bw_read::ruby.dir_cntrl0 8158386116 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_read::total 8158386116 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::ruby.dir_cntrl0 2968516192 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::total 2968516192 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_total::ruby.dir_cntrl0 11126902308 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.bw_total::total 11126902308 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.readReqs 607023 # Number of read requests accepted -system.mem_ctrls.writeReqs 220866 # Number of write requests accepted -system.mem_ctrls.readBursts 607023 # Number of DRAM read bursts, including those serviced by the write queue -system.mem_ctrls.writeBursts 220866 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrls.bytesReadDRAM 37843264 # Total number of bytes read from DRAM -system.mem_ctrls.bytesReadWrQ 1005824 # Total number of bytes read from write queue -system.mem_ctrls.bytesWritten 13945792 # Total number of bytes written to DRAM -system.mem_ctrls.bytesReadSys 38849472 # Total read bytes from the system interface side -system.mem_ctrls.bytesWrittenSys 14135424 # Total written bytes from the system interface side -system.mem_ctrls.servicedByWrQ 15716 # Number of DRAM read bursts serviced by the write queue -system.mem_ctrls.mergedWrBursts 2913 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.bytes_read::ruby.dir_cntrl0 38891008 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 38891008 # Number of bytes read from this memory +system.mem_ctrls.bytes_written::ruby.dir_cntrl0 14178496 # Number of bytes written to this memory +system.mem_ctrls.bytes_written::total 14178496 # Number of bytes written to this memory +system.mem_ctrls.num_reads::ruby.dir_cntrl0 607672 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 607672 # Number of read requests responded to by this memory +system.mem_ctrls.num_writes::ruby.dir_cntrl0 221539 # Number of write requests responded to by this memory +system.mem_ctrls.num_writes::total 221539 # Number of write requests responded to by this memory +system.mem_ctrls.bw_read::ruby.dir_cntrl0 8243572713 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 8243572713 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::ruby.dir_cntrl0 3005359561 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::total 3005359561 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::ruby.dir_cntrl0 11248932274 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 11248932274 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.readReqs 607686 # Number of read requests accepted +system.mem_ctrls.writeReqs 221539 # Number of write requests accepted +system.mem_ctrls.readBursts 607686 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.writeBursts 221539 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrls.bytesReadDRAM 37901760 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 989888 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 13990016 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadSys 38891904 # Total read bytes from the system interface side +system.mem_ctrls.bytesWrittenSys 14178496 # Total written bytes from the system interface side +system.mem_ctrls.servicedByWrQ 15467 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 2896 # Number of DRAM write bursts merged with an existing one system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.mem_ctrls.perBankRdBursts::0 73725 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::1 74070 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::2 73899 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::3 74128 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::4 73783 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::5 73790 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::6 73969 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::7 73937 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::0 74248 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::1 73965 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::2 74362 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 73718 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 73629 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::5 74182 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::6 74198 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 73913 # Per bank write bursts system.mem_ctrls.perBankRdBursts::8 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::9 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::10 0 # Per bank write bursts @@ -51,14 +51,14 @@ system.mem_ctrls.perBankRdBursts::12 0 # Pe system.mem_ctrls.perBankRdBursts::13 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::14 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::15 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::0 27482 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::1 27277 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::2 27210 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::3 27258 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::4 27255 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::5 27079 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::6 27033 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::7 27309 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 27580 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::1 27153 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::2 27465 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 27217 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 27251 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 27223 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::6 27298 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::7 27407 # Per bank write bursts system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::10 0 # Per bank write bursts @@ -68,54 +68,54 @@ system.mem_ctrls.perBankWrBursts::13 0 # Pe system.mem_ctrls.perBankWrBursts::14 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry -system.mem_ctrls.numWrRetry 342 # Number of times write queue was full causing retry -system.mem_ctrls.totGap 4761762 # Total gap between requests +system.mem_ctrls.numWrRetry 341 # Number of times write queue was full causing retry +system.mem_ctrls.totGap 4717717 # Total gap between requests system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::6 607023 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 607686 # Read request sizes (log2) system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::6 220866 # Write request sizes (log2) -system.mem_ctrls.rdQLenPdf::0 181 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::1 455 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::2 845 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::3 1380 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::4 2033 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::5 2935 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::6 3979 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::7 5130 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::8 6504 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::9 8329 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::10 11310 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::11 15935 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::12 23242 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::13 33896 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::14 47467 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::15 60476 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::16 68838 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::17 70112 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::18 62885 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::19 49064 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::20 34859 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::21 23771 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::22 16687 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::23 12606 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::24 9780 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::25 7459 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::26 5197 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::27 3229 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::28 1706 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::29 751 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::30 231 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::31 35 # What read queue length does an incoming req see +system.mem_ctrls.writePktSize::6 221539 # Write request sizes (log2) +system.mem_ctrls.rdQLenPdf::0 173 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::1 425 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::2 892 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::3 1471 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::4 2214 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::5 3131 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::6 4313 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::7 5653 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::8 7328 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::9 9462 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::10 12392 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::11 16826 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::12 24221 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::13 34718 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::14 47678 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::15 60525 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::16 68415 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::17 69451 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::18 61971 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::19 48773 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::20 34538 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::21 23158 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::22 15821 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::23 11733 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::24 9215 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::25 7008 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::26 4874 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::27 3036 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::28 1729 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::29 772 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::30 260 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::31 43 # What read queue length does an incoming req see system.mem_ctrls.wrQLenPdf::0 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::1 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::2 1 # What write queue length does an incoming req see @@ -140,992 +140,996 @@ system.mem_ctrls.wrQLenPdf::20 1 # Wh system.mem_ctrls.wrQLenPdf::21 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::22 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::23 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::24 2 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::24 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::25 2 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::26 3 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::27 5 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::28 8 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::26 2 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::27 6 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::28 9 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::29 14 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::30 31 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::31 55 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::32 75 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::33 107 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::34 167 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::35 222 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::36 301 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::37 426 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::38 602 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::39 1418 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::40 3050 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::41 5274 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::42 7692 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::43 9880 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::44 11429 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::45 12821 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::46 13884 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::47 14674 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::48 15391 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::49 16299 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::50 16813 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::51 16410 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::52 16033 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::53 16244 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::54 17262 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::55 12153 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::56 4599 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::57 1544 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::58 860 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::59 596 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::60 368 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::61 307 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::62 271 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::63 637 # What write queue length does an incoming req see -system.mem_ctrls.bytesPerActivate::samples 214623 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::mean 241.295295 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::gmean 191.288039 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::stdev 173.301221 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::0-127 35466 16.52% 16.52% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::128-255 90893 42.35% 58.87% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::256-383 45716 21.30% 80.18% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::384-511 21225 9.89% 90.06% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::512-639 10997 5.12% 95.19% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::640-767 5731 2.67% 97.86% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::768-895 2748 1.28% 99.14% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::896-1023 1136 0.53% 99.67% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::1024-1151 711 0.33% 100.00% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::total 214623 # Bytes accessed per row activation -system.mem_ctrls.rdPerTurnAround::samples 13609 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::mean 43.445147 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::gmean 31.477862 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::stdev 25.391105 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::0-15 3000 22.04% 22.04% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::16-31 1539 11.31% 33.35% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::32-47 2539 18.66% 52.01% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::48-63 3040 22.34% 74.35% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::64-79 2614 19.21% 93.56% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::80-95 821 6.03% 99.59% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::96-111 53 0.39% 99.98% # Reads before turning the bus around for writes +system.mem_ctrls.wrQLenPdf::30 24 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::31 54 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::32 90 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::33 132 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::34 196 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::35 295 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::36 386 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::37 531 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::38 677 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::39 1545 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::40 3338 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::41 5862 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::42 8353 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::43 10675 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::44 12511 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::45 13693 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::46 14394 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::47 15002 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::48 15530 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::49 16080 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::50 16988 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::51 16432 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::52 15907 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::53 15871 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::54 16756 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::55 10206 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::56 3495 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::57 1016 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::58 632 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::59 462 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::60 337 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::61 300 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::62 230 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::63 585 # What write queue length does an incoming req see +system.mem_ctrls.bytesPerActivate::samples 217832 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 238.215138 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 188.366987 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 172.557799 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 37638 17.28% 17.28% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 92585 42.50% 59.78% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 45398 20.84% 80.62% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 21076 9.68% 90.30% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 10973 5.04% 95.33% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 5549 2.55% 97.88% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 2719 1.25% 99.13% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 1199 0.55% 99.68% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 695 0.32% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 217832 # Bytes accessed per row activation +system.mem_ctrls.rdPerTurnAround::samples 13655 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::mean 43.367704 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::gmean 31.670415 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::stdev 25.872524 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::0-15 3074 22.51% 22.51% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::16-31 1792 13.12% 35.64% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::32-47 2254 16.51% 52.14% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::48-63 2805 20.54% 72.68% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::64-79 2763 20.23% 92.92% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::80-95 909 6.66% 99.58% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::96-111 55 0.40% 99.98% # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::112-127 2 0.01% 99.99% # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::256-271 1 0.01% 100.00% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::total 13609 # Reads before turning the bus around for writes -system.mem_ctrls.wrPerTurnAround::samples 13609 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::mean 16.011683 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::gmean 16.009721 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::stdev 0.292863 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::16 13571 99.72% 99.72% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::17 11 0.08% 99.80% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::18 8 0.06% 99.86% # Writes before turning the bus around for reads +system.mem_ctrls.rdPerTurnAround::total 13655 # Reads before turning the bus around for writes +system.mem_ctrls.wrPerTurnAround::samples 13655 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::mean 16.008349 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::gmean 16.007193 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::stdev 0.215662 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::16 13627 99.79% 99.79% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::17 6 0.04% 99.84% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::18 3 0.02% 99.86% # Writes before turning the bus around for reads system.mem_ctrls.wrPerTurnAround::19 5 0.04% 99.90% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::21 3 0.02% 99.92% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::22 2 0.01% 99.93% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::23 1 0.01% 99.94% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::24 2 0.01% 99.96% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::26 3 0.02% 99.98% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::28 2 0.01% 99.99% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::29 1 0.01% 100.00% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::total 13609 # Writes before turning the bus around for reads -system.mem_ctrls.totQLat 76204752 # Total ticks spent queuing -system.mem_ctrls.totMemAccLat 87439471 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrls.totBusLat 2956505 # Total ticks spent in databus transfers -system.mem_ctrls.avgQLat 128.88 # Average queueing delay per DRAM burst +system.mem_ctrls.wrPerTurnAround::20 2 0.01% 99.91% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::21 4 0.03% 99.94% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::22 1 0.01% 99.95% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::23 4 0.03% 99.98% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::24 2 0.01% 99.99% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::25 1 0.01% 100.00% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::total 13655 # Writes before turning the bus around for reads +system.mem_ctrls.totQLat 74136636 # Total ticks spent queuing +system.mem_ctrls.totMemAccLat 85388721 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.totBusLat 2961075 # Total ticks spent in databus transfers +system.mem_ctrls.avgQLat 125.18 # Average queueing delay per DRAM burst system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst -system.mem_ctrls.avgMemAccLat 147.87 # Average memory access latency per DRAM burst -system.mem_ctrls.avgRdBW 7947.29 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrls.avgWrBW 2928.69 # Average achieved write bandwidth in MiByte/s -system.mem_ctrls.avgRdBWSys 8158.60 # Average system read bandwidth in MiByte/s -system.mem_ctrls.avgWrBWSys 2968.52 # Average system write bandwidth in MiByte/s +system.mem_ctrls.avgMemAccLat 144.18 # Average memory access latency per DRAM burst +system.mem_ctrls.avgRdBW 8033.89 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 2965.41 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 8243.76 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 3005.36 # Average system write bandwidth in MiByte/s system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrls.busUtil 84.97 # Data bus utilization in percentage -system.mem_ctrls.busUtilRead 62.09 # Data bus utilization in percentage for reads -system.mem_ctrls.busUtilWrite 22.88 # Data bus utilization in percentage for writes -system.mem_ctrls.avgRdQLen 19.97 # Average read queue length when enqueuing -system.mem_ctrls.avgWrQLen 50.51 # Average write queue length when enqueuing -system.mem_ctrls.readRowHits 383126 # Number of row buffer hits during reads -system.mem_ctrls.writeRowHits 211448 # Number of row buffer hits during writes -system.mem_ctrls.readRowHitRate 64.79 # Row buffer hit rate for reads -system.mem_ctrls.writeRowHitRate 97.02 # Row buffer hit rate for writes -system.mem_ctrls.avgGap 5.75 # Average gap between requests -system.mem_ctrls.pageHitRate 73.47 # Row buffer hit rate, read and write combined -system.mem_ctrls.memoryStateTime::IDLE 11 # Time in different power states -system.mem_ctrls.memoryStateTime::REF 158860 # Time in different power states -system.mem_ctrls.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls.memoryStateTime::ACT 4598696 # Time in different power states -system.mem_ctrls.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrls.actEnergy::0 1621105920 # Energy for activate commands per rank (pJ) -system.mem_ctrls.actEnergy::1 0 # Energy for activate commands per rank (pJ) -system.mem_ctrls.preEnergy::0 900614400 # Energy for precharge commands per rank (pJ) -system.mem_ctrls.preEnergy::1 0 # Energy for precharge commands per rank (pJ) -system.mem_ctrls.readEnergy::0 7372759680 # Energy for read commands per rank (pJ) -system.mem_ctrls.readEnergy::1 0 # Energy for read commands per rank (pJ) -system.mem_ctrls.writeEnergy::0 2257061760 # Energy for write commands per rank (pJ) -system.mem_ctrls.writeEnergy::1 0 # Energy for write commands per rank (pJ) -system.mem_ctrls.refreshEnergy::0 310730160 # Energy for refresh commands per rank (pJ) -system.mem_ctrls.refreshEnergy::1 310730160 # Energy for refresh commands per rank (pJ) -system.mem_ctrls.actBackEnergy::0 3241151100 # Energy for active background per rank (pJ) -system.mem_ctrls.actBackEnergy::1 102809304 # Energy for active background per rank (pJ) -system.mem_ctrls.preBackEnergy::0 11416800 # Energy for precharge background per rank (pJ) -system.mem_ctrls.preBackEnergy::1 2764348200 # Energy for precharge background per rank (pJ) -system.mem_ctrls.totalEnergy::0 15714839820 # Total energy per rank (pJ) -system.mem_ctrls.totalEnergy::1 3177887664 # Total energy per rank (pJ) -system.mem_ctrls.averagePower::0 3303.134998 # Core power per rank (mW) -system.mem_ctrls.averagePower::1 667.966844 # Core power per rank (mW) +system.mem_ctrls.busUtil 85.93 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 62.76 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 23.17 # Data bus utilization in percentage for writes +system.mem_ctrls.avgRdQLen 19.65 # Average read queue length when enqueuing +system.mem_ctrls.avgWrQLen 50.35 # Average write queue length when enqueuing +system.mem_ctrls.readRowHits 380729 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 212242 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 64.29 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate 97.07 # Row buffer hit rate for writes +system.mem_ctrls.avgGap 5.69 # Average gap between requests +system.mem_ctrls.pageHitRate 73.13 # Row buffer hit rate, read and write combined +system.mem_ctrls_0.actEnergy 1644443640 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 913579800 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 7379698560 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 2262898944 # Energy for write commands per rank (pJ) +system.mem_ctrls_0.refreshEnergy 307678800 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_0.actBackEnergy 3210618024 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 10162200 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.totalEnergy 15729079968 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 3338.923999 # Core power per rank (mW) +system.mem_ctrls_0.memoryStateTime::IDLE 11 # Time in different power states +system.mem_ctrls_0.memoryStateTime::REF 157300 # Time in different power states +system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 4553526 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls_1.actEnergy 0 # Energy for activate commands per rank (pJ) +system.mem_ctrls_1.preEnergy 0 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_1.readEnergy 0 # Energy for read commands per rank (pJ) +system.mem_ctrls_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls_1.refreshEnergy 307678800 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_1.actBackEnergy 101799720 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 2737167600 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.totalEnergy 3146646120 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 667.967681 # Core power per rank (mW) +system.mem_ctrls_1.memoryStateTime::IDLE 4553490 # Time in different power states +system.mem_ctrls_1.memoryStateTime::REF 157300 # Time in different power states +system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 0 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu_clk_domain.clock 1 # Clock period in ticks +system.cpu0.num_reads 98877 # number of read accesses completed +system.cpu0.num_writes 55675 # number of write accesses completed +system.cpu0.num_copies 0 # number of copy accesses completed +system.cpu1.num_reads 99785 # number of read accesses completed +system.cpu1.num_writes 55900 # number of write accesses completed +system.cpu1.num_copies 0 # number of copy accesses completed +system.cpu2.num_reads 99496 # number of read accesses completed +system.cpu2.num_writes 55477 # number of write accesses completed +system.cpu2.num_copies 0 # number of copy accesses completed +system.cpu3.num_reads 98960 # number of read accesses completed +system.cpu3.num_writes 55077 # number of write accesses completed +system.cpu3.num_copies 0 # number of copy accesses completed +system.cpu4.num_reads 99813 # number of read accesses completed +system.cpu4.num_writes 56095 # number of write accesses completed +system.cpu4.num_copies 0 # number of copy accesses completed +system.cpu5.num_reads 99616 # number of read accesses completed +system.cpu5.num_writes 55503 # number of write accesses completed +system.cpu5.num_copies 0 # number of copy accesses completed +system.cpu6.num_reads 98898 # number of read accesses completed +system.cpu6.num_writes 55431 # number of write accesses completed +system.cpu6.num_copies 0 # number of copy accesses completed +system.cpu7.num_reads 100000 # number of read accesses completed +system.cpu7.num_writes 55483 # number of write accesses completed +system.cpu7.num_copies 0 # number of copy accesses completed system.ruby.clk_domain.clock 1 # Clock period in ticks system.ruby.outstanding_req_hist::bucket_size 2 system.ruby.outstanding_req_hist::max_bucket 19 -system.ruby.outstanding_req_hist::samples 628111 -system.ruby.outstanding_req_hist::mean 15.998456 -system.ruby.outstanding_req_hist::gmean 15.997194 -system.ruby.outstanding_req_hist::stdev 0.125726 -system.ruby.outstanding_req_hist | 8 0.00% 0.00% | 16 0.00% 0.00% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.02% | 26 0.00% 0.02% | 627981 99.98% 100.00% | 0 0.00% 100.00% -system.ruby.outstanding_req_hist::total 628111 +system.ruby.outstanding_req_hist::samples 628930 +system.ruby.outstanding_req_hist::mean 15.998458 +system.ruby.outstanding_req_hist::gmean 15.997198 +system.ruby.outstanding_req_hist::stdev 0.125644 +system.ruby.outstanding_req_hist | 8 0.00% 0.00% | 16 0.00% 0.00% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.02% | 26 0.00% 0.02% | 628800 99.98% 100.00% | 0 0.00% 100.00% +system.ruby.outstanding_req_hist::total 628930 system.ruby.latency_hist::bucket_size 512 system.ruby.latency_hist::max_bucket 5119 -system.ruby.latency_hist::samples 627983 -system.ruby.latency_hist::mean 970.449089 -system.ruby.latency_hist::gmean 693.046339 -system.ruby.latency_hist::stdev 679.084515 -system.ruby.latency_hist | 234051 37.27% 37.27% | 116033 18.48% 55.75% | 114404 18.22% 73.97% | 122030 19.43% 93.40% | 38244 6.09% 99.49% | 3110 0.50% 99.98% | 106 0.02% 100.00% | 5 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.latency_hist::total 627983 +system.ruby.latency_hist::samples 628802 +system.ruby.latency_hist::mean 960.194053 +system.ruby.latency_hist::gmean 685.947832 +system.ruby.latency_hist::stdev 670.704695 +system.ruby.latency_hist | 235493 37.45% 37.45% | 115985 18.45% 55.90% | 117829 18.74% 74.64% | 122332 19.45% 94.09% | 34636 5.51% 99.60% | 2468 0.39% 99.99% | 59 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.latency_hist::total 628802 system.ruby.hit_latency_hist::bucket_size 128 system.ruby.hit_latency_hist::max_bucket 1279 -system.ruby.hit_latency_hist::samples 674 -system.ruby.hit_latency_hist::mean 113.305638 -system.ruby.hit_latency_hist::gmean 38.452852 -system.ruby.hit_latency_hist::stdev 152.633110 -system.ruby.hit_latency_hist | 461 68.40% 68.40% | 126 18.69% 87.09% | 48 7.12% 94.21% | 22 3.26% 97.48% | 8 1.19% 98.66% | 3 0.45% 99.11% | 3 0.45% 99.55% | 0 0.00% 99.55% | 2 0.30% 99.85% | 1 0.15% 100.00% -system.ruby.hit_latency_hist::total 674 +system.ruby.hit_latency_hist::samples 688 +system.ruby.hit_latency_hist::mean 97.577035 +system.ruby.hit_latency_hist::gmean 32.486686 +system.ruby.hit_latency_hist::stdev 126.810521 +system.ruby.hit_latency_hist | 485 70.49% 70.49% | 131 19.04% 89.53% | 50 7.27% 96.80% | 10 1.45% 98.26% | 5 0.73% 98.98% | 4 0.58% 99.56% | 3 0.44% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.hit_latency_hist::total 688 system.ruby.miss_latency_hist::bucket_size 512 system.ruby.miss_latency_hist::max_bucket 5119 -system.ruby.miss_latency_hist::samples 627309 -system.ruby.miss_latency_hist::mean 971.370030 -system.ruby.miss_latency_hist::gmean 695.202908 -system.ruby.miss_latency_hist::stdev 678.849054 -system.ruby.miss_latency_hist | 233394 37.21% 37.21% | 116019 18.49% 55.70% | 114401 18.24% 73.94% | 122030 19.45% 93.39% | 38244 6.10% 99.49% | 3110 0.50% 99.98% | 106 0.02% 100.00% | 5 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.miss_latency_hist::total 627309 -system.ruby.L1Cache.incomplete_times 991 -system.ruby.Directory.incomplete_times 155619 -system.ruby.l1_cntrl4.L1Dcache.demand_hits 17 # Number of cache demand hits -system.ruby.l1_cntrl4.L1Dcache.demand_misses 78343 # Number of cache demand misses -system.ruby.l1_cntrl4.L1Dcache.demand_accesses 78360 # Number of cache demand accesses -system.ruby.l1_cntrl4.L1Icache.demand_hits 0 # Number of cache demand hits -system.ruby.l1_cntrl4.L1Icache.demand_misses 0 # Number of cache demand misses -system.ruby.l1_cntrl4.L1Icache.demand_accesses 0 # Number of cache demand accesses -system.ruby.l1_cntrl4.L2cache.demand_hits 72 # Number of cache demand hits -system.ruby.l1_cntrl4.L2cache.demand_misses 78271 # Number of cache demand misses -system.ruby.l1_cntrl4.L2cache.demand_accesses 78343 # Number of cache demand accesses -system.cpu_clk_domain.clock 1 # Clock period in ticks -system.ruby.l1_cntrl5.L1Dcache.demand_hits 12 # Number of cache demand hits -system.ruby.l1_cntrl5.L1Dcache.demand_misses 78394 # Number of cache demand misses -system.ruby.l1_cntrl5.L1Dcache.demand_accesses 78406 # Number of cache demand accesses -system.ruby.l1_cntrl5.L1Icache.demand_hits 0 # Number of cache demand hits -system.ruby.l1_cntrl5.L1Icache.demand_misses 0 # Number of cache demand misses -system.ruby.l1_cntrl5.L1Icache.demand_accesses 0 # Number of cache demand accesses -system.ruby.l1_cntrl5.L2cache.demand_hits 64 # Number of cache demand hits -system.ruby.l1_cntrl5.L2cache.demand_misses 78330 # Number of cache demand misses -system.ruby.l1_cntrl5.L2cache.demand_accesses 78394 # Number of cache demand accesses -system.ruby.l1_cntrl6.L1Dcache.demand_hits 17 # Number of cache demand hits -system.ruby.l1_cntrl6.L1Dcache.demand_misses 78610 # Number of cache demand misses -system.ruby.l1_cntrl6.L1Dcache.demand_accesses 78627 # Number of cache demand accesses -system.ruby.l1_cntrl6.L1Icache.demand_hits 0 # Number of cache demand hits -system.ruby.l1_cntrl6.L1Icache.demand_misses 0 # Number of cache demand misses -system.ruby.l1_cntrl6.L1Icache.demand_accesses 0 # Number of cache demand accesses -system.ruby.l1_cntrl6.L2cache.demand_hits 68 # Number of cache demand hits -system.ruby.l1_cntrl6.L2cache.demand_misses 78542 # Number of cache demand misses -system.ruby.l1_cntrl6.L2cache.demand_accesses 78610 # Number of cache demand accesses -system.ruby.l1_cntrl7.L1Dcache.demand_hits 14 # Number of cache demand hits -system.ruby.l1_cntrl7.L1Dcache.demand_misses 78278 # Number of cache demand misses -system.ruby.l1_cntrl7.L1Dcache.demand_accesses 78292 # Number of cache demand accesses -system.ruby.l1_cntrl7.L1Icache.demand_hits 0 # Number of cache demand hits -system.ruby.l1_cntrl7.L1Icache.demand_misses 0 # Number of cache demand misses -system.ruby.l1_cntrl7.L1Icache.demand_accesses 0 # Number of cache demand accesses -system.ruby.l1_cntrl7.L2cache.demand_hits 56 # Number of cache demand hits -system.ruby.l1_cntrl7.L2cache.demand_misses 78222 # Number of cache demand misses -system.ruby.l1_cntrl7.L2cache.demand_accesses 78278 # Number of cache demand accesses -system.ruby.l1_cntrl0.L1Dcache.demand_hits 14 # Number of cache demand hits -system.ruby.l1_cntrl0.L1Dcache.demand_misses 78739 # Number of cache demand misses -system.ruby.l1_cntrl0.L1Dcache.demand_accesses 78753 # Number of cache demand accesses +system.ruby.miss_latency_hist::samples 628114 +system.ruby.miss_latency_hist::mean 961.138914 +system.ruby.miss_latency_hist::gmean 688.243254 +system.ruby.miss_latency_hist::stdev 670.450585 +system.ruby.miss_latency_hist | 234817 37.38% 37.38% | 115973 18.46% 55.85% | 117829 18.76% 74.61% | 122332 19.48% 94.08% | 34636 5.51% 99.60% | 2468 0.39% 99.99% | 59 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.miss_latency_hist::total 628114 +system.ruby.L1Cache.incomplete_times 1076 +system.ruby.Directory.incomplete_times 174126 +system.ruby.dir_cntrl0.probeFilter.demand_hits 0 # Number of cache demand hits +system.ruby.dir_cntrl0.probeFilter.demand_misses 0 # Number of cache demand misses +system.ruby.dir_cntrl0.probeFilter.demand_accesses 0 # Number of cache demand accesses +system.ruby.l1_cntrl0.L1Dcache.demand_hits 19 # Number of cache demand hits +system.ruby.l1_cntrl0.L1Dcache.demand_misses 78377 # Number of cache demand misses +system.ruby.l1_cntrl0.L1Dcache.demand_accesses 78396 # Number of cache demand accesses system.ruby.l1_cntrl0.L1Icache.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl0.L1Icache.demand_misses 0 # Number of cache demand misses system.ruby.l1_cntrl0.L1Icache.demand_accesses 0 # Number of cache demand accesses -system.ruby.l1_cntrl0.L2cache.demand_hits 80 # Number of cache demand hits -system.ruby.l1_cntrl0.L2cache.demand_misses 78659 # Number of cache demand misses -system.ruby.l1_cntrl0.L2cache.demand_accesses 78739 # Number of cache demand accesses -system.ruby.network.routers0.percent_links_utilized 15.611459 -system.ruby.network.routers0.msg_count.Request_Control::2 78659 -system.ruby.network.routers0.msg_count.Request_Control::3 126 -system.ruby.network.routers0.msg_count.Response_Data::4 81155 -system.ruby.network.routers0.msg_count.Response_Control::4 1092655 -system.ruby.network.routers0.msg_count.Writeback_Data::5 27808 -system.ruby.network.routers0.msg_count.Writeback_Control::2 74263 -system.ruby.network.routers0.msg_count.Writeback_Control::3 74259 -system.ruby.network.routers0.msg_count.Writeback_Control::5 46285 -system.ruby.network.routers0.msg_count.Broadcast_Control::3 547799 -system.ruby.network.routers0.msg_count.Unblock_Control::5 78821 -system.ruby.network.routers0.msg_bytes.Request_Control::2 629272 -system.ruby.network.routers0.msg_bytes.Request_Control::3 1008 -system.ruby.network.routers0.msg_bytes.Response_Data::4 5843160 -system.ruby.network.routers0.msg_bytes.Response_Control::4 8741240 -system.ruby.network.routers0.msg_bytes.Writeback_Data::5 2002176 -system.ruby.network.routers0.msg_bytes.Writeback_Control::2 594104 -system.ruby.network.routers0.msg_bytes.Writeback_Control::3 594072 -system.ruby.network.routers0.msg_bytes.Writeback_Control::5 370280 -system.ruby.network.routers0.msg_bytes.Broadcast_Control::3 4382392 -system.ruby.network.routers0.msg_bytes.Unblock_Control::5 630568 -system.ruby.l1_cntrl1.L1Dcache.demand_hits 14 # Number of cache demand hits -system.ruby.l1_cntrl1.L1Dcache.demand_misses 78406 # Number of cache demand misses -system.ruby.l1_cntrl1.L1Dcache.demand_accesses 78420 # Number of cache demand accesses +system.ruby.l1_cntrl0.L2cache.demand_hits 65 # Number of cache demand hits +system.ruby.l1_cntrl0.L2cache.demand_misses 78312 # Number of cache demand misses +system.ruby.l1_cntrl0.L2cache.demand_accesses 78377 # Number of cache demand accesses +system.ruby.l1_cntrl1.L1Dcache.demand_hits 12 # Number of cache demand hits +system.ruby.l1_cntrl1.L1Dcache.demand_misses 78839 # Number of cache demand misses +system.ruby.l1_cntrl1.L1Dcache.demand_accesses 78851 # Number of cache demand accesses system.ruby.l1_cntrl1.L1Icache.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl1.L1Icache.demand_misses 0 # Number of cache demand misses system.ruby.l1_cntrl1.L1Icache.demand_accesses 0 # Number of cache demand accesses -system.ruby.l1_cntrl1.L2cache.demand_hits 79 # Number of cache demand hits -system.ruby.l1_cntrl1.L2cache.demand_misses 78327 # Number of cache demand misses -system.ruby.l1_cntrl1.L2cache.demand_accesses 78406 # Number of cache demand accesses -system.ruby.network.routers1.percent_links_utilized 15.566439 -system.ruby.network.routers1.msg_count.Request_Control::2 78327 -system.ruby.network.routers1.msg_count.Request_Control::3 117 -system.ruby.network.routers1.msg_count.Response_Data::4 80869 -system.ruby.network.routers1.msg_count.Response_Control::4 1090742 -system.ruby.network.routers1.msg_count.Writeback_Data::5 27485 -system.ruby.network.routers1.msg_count.Writeback_Control::2 73881 -system.ruby.network.routers1.msg_count.Writeback_Control::3 73878 -system.ruby.network.routers1.msg_count.Writeback_Control::5 46209 -system.ruby.network.routers1.msg_count.Broadcast_Control::3 548111 -system.ruby.network.routers1.msg_count.Unblock_Control::5 78508 -system.ruby.network.routers1.msg_bytes.Request_Control::2 626616 -system.ruby.network.routers1.msg_bytes.Request_Control::3 936 -system.ruby.network.routers1.msg_bytes.Response_Data::4 5822568 -system.ruby.network.routers1.msg_bytes.Response_Control::4 8725936 -system.ruby.network.routers1.msg_bytes.Writeback_Data::5 1978920 -system.ruby.network.routers1.msg_bytes.Writeback_Control::2 591048 -system.ruby.network.routers1.msg_bytes.Writeback_Control::3 591024 -system.ruby.network.routers1.msg_bytes.Writeback_Control::5 369672 -system.ruby.network.routers1.msg_bytes.Broadcast_Control::3 4384888 -system.ruby.network.routers1.msg_bytes.Unblock_Control::5 628064 -system.ruby.l1_cntrl2.L1Dcache.demand_hits 18 # Number of cache demand hits -system.ruby.l1_cntrl2.L1Dcache.demand_misses 78504 # Number of cache demand misses -system.ruby.l1_cntrl2.L1Dcache.demand_accesses 78522 # Number of cache demand accesses +system.ruby.l1_cntrl1.L2cache.demand_hits 60 # Number of cache demand hits +system.ruby.l1_cntrl1.L2cache.demand_misses 78779 # Number of cache demand misses +system.ruby.l1_cntrl1.L2cache.demand_accesses 78839 # Number of cache demand accesses +system.ruby.l1_cntrl2.L1Dcache.demand_hits 20 # Number of cache demand hits +system.ruby.l1_cntrl2.L1Dcache.demand_misses 78721 # Number of cache demand misses +system.ruby.l1_cntrl2.L1Dcache.demand_accesses 78741 # Number of cache demand accesses system.ruby.l1_cntrl2.L1Icache.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl2.L1Icache.demand_misses 0 # Number of cache demand misses system.ruby.l1_cntrl2.L1Icache.demand_accesses 0 # Number of cache demand accesses -system.ruby.l1_cntrl2.L2cache.demand_hits 59 # Number of cache demand hits -system.ruby.l1_cntrl2.L2cache.demand_misses 78445 # Number of cache demand misses -system.ruby.l1_cntrl2.L2cache.demand_accesses 78504 # Number of cache demand accesses -system.ruby.network.routers2.percent_links_utilized 15.582589 -system.ruby.network.routers2.msg_count.Request_Control::2 78445 -system.ruby.network.routers2.msg_count.Request_Control::3 123 -system.ruby.network.routers2.msg_count.Response_Data::4 80995 -system.ruby.network.routers2.msg_count.Response_Control::4 1091483 -system.ruby.network.routers2.msg_count.Writeback_Data::5 27579 -system.ruby.network.routers2.msg_count.Writeback_Control::2 73989 -system.ruby.network.routers2.msg_count.Writeback_Control::3 73986 -system.ruby.network.routers2.msg_count.Writeback_Control::5 46222 -system.ruby.network.routers2.msg_count.Broadcast_Control::3 547994 -system.ruby.network.routers2.msg_count.Unblock_Control::5 78627 -system.ruby.network.routers2.msg_bytes.Request_Control::2 627560 -system.ruby.network.routers2.msg_bytes.Request_Control::3 984 -system.ruby.network.routers2.msg_bytes.Response_Data::4 5831640 -system.ruby.network.routers2.msg_bytes.Response_Control::4 8731864 -system.ruby.network.routers2.msg_bytes.Writeback_Data::5 1985688 -system.ruby.network.routers2.msg_bytes.Writeback_Control::2 591912 -system.ruby.network.routers2.msg_bytes.Writeback_Control::3 591888 -system.ruby.network.routers2.msg_bytes.Writeback_Control::5 369776 -system.ruby.network.routers2.msg_bytes.Broadcast_Control::3 4383952 -system.ruby.network.routers2.msg_bytes.Unblock_Control::5 629016 -system.ruby.l1_cntrl3.L1Dcache.demand_hits 17 # Number of cache demand hits -system.ruby.l1_cntrl3.L1Dcache.demand_misses 78610 # Number of cache demand misses -system.ruby.l1_cntrl3.L1Dcache.demand_accesses 78627 # Number of cache demand accesses +system.ruby.l1_cntrl2.L2cache.demand_hits 62 # Number of cache demand hits +system.ruby.l1_cntrl2.L2cache.demand_misses 78659 # Number of cache demand misses +system.ruby.l1_cntrl2.L2cache.demand_accesses 78721 # Number of cache demand accesses +system.ruby.l1_cntrl3.L1Dcache.demand_hits 20 # Number of cache demand hits +system.ruby.l1_cntrl3.L1Dcache.demand_misses 78291 # Number of cache demand misses +system.ruby.l1_cntrl3.L1Dcache.demand_accesses 78311 # Number of cache demand accesses system.ruby.l1_cntrl3.L1Icache.demand_hits 0 # Number of cache demand hits system.ruby.l1_cntrl3.L1Icache.demand_misses 0 # Number of cache demand misses system.ruby.l1_cntrl3.L1Icache.demand_accesses 0 # Number of cache demand accesses -system.ruby.l1_cntrl3.L2cache.demand_hits 73 # Number of cache demand hits -system.ruby.l1_cntrl3.L2cache.demand_misses 78537 # Number of cache demand misses -system.ruby.l1_cntrl3.L2cache.demand_accesses 78610 # Number of cache demand accesses -system.ruby.network.routers3.percent_links_utilized 15.594811 -system.ruby.network.routers3.msg_count.Request_Control::2 78537 -system.ruby.network.routers3.msg_count.Request_Control::3 103 -system.ruby.network.routers3.msg_count.Response_Data::4 81093 -system.ruby.network.routers3.msg_count.Response_Control::4 1091782 -system.ruby.network.routers3.msg_count.Writeback_Data::5 27685 -system.ruby.network.routers3.msg_count.Writeback_Control::2 74059 -system.ruby.network.routers3.msg_count.Writeback_Control::3 74056 -system.ruby.network.routers3.msg_count.Writeback_Control::5 46186 -system.ruby.network.routers3.msg_count.Broadcast_Control::3 547920 -system.ruby.network.routers3.msg_count.Unblock_Control::5 78718 -system.ruby.network.routers3.msg_bytes.Request_Control::2 628296 -system.ruby.network.routers3.msg_bytes.Request_Control::3 824 -system.ruby.network.routers3.msg_bytes.Response_Data::4 5838696 -system.ruby.network.routers3.msg_bytes.Response_Control::4 8734256 -system.ruby.network.routers3.msg_bytes.Writeback_Data::5 1993320 -system.ruby.network.routers3.msg_bytes.Writeback_Control::2 592472 -system.ruby.network.routers3.msg_bytes.Writeback_Control::3 592448 -system.ruby.network.routers3.msg_bytes.Writeback_Control::5 369488 -system.ruby.network.routers3.msg_bytes.Broadcast_Control::3 4383360 -system.ruby.network.routers3.msg_bytes.Unblock_Control::5 629744 -system.ruby.network.routers4.percent_links_utilized 15.571973 -system.ruby.network.routers4.msg_count.Request_Control::2 78271 -system.ruby.network.routers4.msg_count.Request_Control::3 145 -system.ruby.network.routers4.msg_count.Response_Data::4 80771 -system.ruby.network.routers4.msg_count.Response_Control::4 1090522 -system.ruby.network.routers4.msg_count.Writeback_Data::5 27786 -system.ruby.network.routers4.msg_count.Writeback_Control::2 73811 -system.ruby.network.routers4.msg_count.Writeback_Control::3 73807 -system.ruby.network.routers4.msg_count.Writeback_Control::5 45834 -system.ruby.network.routers4.msg_count.Broadcast_Control::3 548156 -system.ruby.network.routers4.msg_count.Unblock_Control::5 78454 -system.ruby.network.routers4.msg_bytes.Request_Control::2 626168 -system.ruby.network.routers4.msg_bytes.Request_Control::3 1160 -system.ruby.network.routers4.msg_bytes.Response_Data::4 5815512 -system.ruby.network.routers4.msg_bytes.Response_Control::4 8724176 -system.ruby.network.routers4.msg_bytes.Writeback_Data::5 2000592 -system.ruby.network.routers4.msg_bytes.Writeback_Control::2 590488 -system.ruby.network.routers4.msg_bytes.Writeback_Control::3 590456 -system.ruby.network.routers4.msg_bytes.Writeback_Control::5 366672 -system.ruby.network.routers4.msg_bytes.Broadcast_Control::3 4385248 -system.ruby.network.routers4.msg_bytes.Unblock_Control::5 627632 -system.ruby.network.routers5.percent_links_utilized 15.557021 -system.ruby.network.routers5.msg_count.Request_Control::2 78330 -system.ruby.network.routers5.msg_count.Request_Control::3 113 -system.ruby.network.routers5.msg_count.Response_Data::4 80870 -system.ruby.network.routers5.msg_count.Response_Control::4 1090637 -system.ruby.network.routers5.msg_count.Writeback_Data::5 27326 -system.ruby.network.routers5.msg_count.Writeback_Control::2 73739 -system.ruby.network.routers5.msg_count.Writeback_Control::3 73737 -system.ruby.network.routers5.msg_count.Writeback_Control::5 46227 -system.ruby.network.routers5.msg_count.Broadcast_Control::3 548107 -system.ruby.network.routers5.msg_count.Unblock_Control::5 78511 -system.ruby.network.routers5.msg_bytes.Request_Control::2 626640 -system.ruby.network.routers5.msg_bytes.Request_Control::3 904 -system.ruby.network.routers5.msg_bytes.Response_Data::4 5822640 -system.ruby.network.routers5.msg_bytes.Response_Control::4 8725096 -system.ruby.network.routers5.msg_bytes.Writeback_Data::5 1967472 -system.ruby.network.routers5.msg_bytes.Writeback_Control::2 589912 -system.ruby.network.routers5.msg_bytes.Writeback_Control::3 589896 -system.ruby.network.routers5.msg_bytes.Writeback_Control::5 369816 -system.ruby.network.routers5.msg_bytes.Broadcast_Control::3 4384856 -system.ruby.network.routers5.msg_bytes.Unblock_Control::5 628088 -system.ruby.network.routers6.percent_links_utilized 15.603526 -system.ruby.network.routers6.msg_count.Request_Control::2 78540 -system.ruby.network.routers6.msg_count.Request_Control::3 143 -system.ruby.network.routers6.msg_count.Response_Data::4 81105 -system.ruby.network.routers6.msg_count.Response_Control::4 1091896 -system.ruby.network.routers6.msg_count.Writeback_Data::5 27859 -system.ruby.network.routers6.msg_count.Writeback_Control::2 74064 -system.ruby.network.routers6.msg_count.Writeback_Control::3 74061 -system.ruby.network.routers6.msg_count.Writeback_Control::5 46043 -system.ruby.network.routers6.msg_count.Broadcast_Control::3 547908 -system.ruby.network.routers6.msg_count.Unblock_Control::5 78695 -system.ruby.network.routers6.msg_bytes.Request_Control::2 628320 -system.ruby.network.routers6.msg_bytes.Request_Control::3 1144 -system.ruby.network.routers6.msg_bytes.Response_Data::4 5839560 -system.ruby.network.routers6.msg_bytes.Response_Control::4 8735168 -system.ruby.network.routers6.msg_bytes.Writeback_Data::5 2005848 -system.ruby.network.routers6.msg_bytes.Writeback_Control::2 592512 -system.ruby.network.routers6.msg_bytes.Writeback_Control::3 592488 -system.ruby.network.routers6.msg_bytes.Writeback_Control::5 368344 -system.ruby.network.routers6.msg_bytes.Broadcast_Control::3 4383264 -system.ruby.network.routers6.msg_bytes.Unblock_Control::5 629560 -system.ruby.network.routers7.percent_links_utilized 15.548248 -system.ruby.network.routers7.msg_count.Request_Control::2 78222 -system.ruby.network.routers7.msg_count.Request_Control::3 120 -system.ruby.network.routers7.msg_count.Response_Data::4 80754 -system.ruby.network.routers7.msg_count.Response_Control::4 1090091 -system.ruby.network.routers7.msg_count.Writeback_Data::5 27338 -system.ruby.network.routers7.msg_count.Writeback_Control::2 73710 -system.ruby.network.routers7.msg_count.Writeback_Control::3 73709 -system.ruby.network.routers7.msg_count.Writeback_Control::5 46180 -system.ruby.network.routers7.msg_count.Broadcast_Control::3 548224 -system.ruby.network.routers7.msg_count.Unblock_Control::5 78410 -system.ruby.network.routers7.msg_bytes.Request_Control::2 625776 -system.ruby.network.routers7.msg_bytes.Request_Control::3 960 -system.ruby.network.routers7.msg_bytes.Response_Data::4 5814288 -system.ruby.network.routers7.msg_bytes.Response_Control::4 8720728 -system.ruby.network.routers7.msg_bytes.Writeback_Data::5 1968336 -system.ruby.network.routers7.msg_bytes.Writeback_Control::2 589680 -system.ruby.network.routers7.msg_bytes.Writeback_Control::3 589672 -system.ruby.network.routers7.msg_bytes.Writeback_Control::5 369440 -system.ruby.network.routers7.msg_bytes.Broadcast_Control::3 4385792 -system.ruby.network.routers7.msg_bytes.Unblock_Control::5 627280 -system.ruby.dir_cntrl0.probeFilter.demand_hits 0 # Number of cache demand hits -system.ruby.dir_cntrl0.probeFilter.demand_misses 0 # Number of cache demand misses -system.ruby.dir_cntrl0.probeFilter.demand_accesses 0 # Number of cache demand accesses -system.ruby.network.routers8.percent_links_utilized 57.155007 -system.ruby.network.routers8.msg_count.Request_Control::2 627331 -system.ruby.network.routers8.msg_count.Request_Control::3 990 -system.ruby.network.routers8.msg_count.Response_Data::4 607002 -system.ruby.network.routers8.msg_count.Writeback_Data::5 220866 -system.ruby.network.routers8.msg_count.Writeback_Control::2 591516 -system.ruby.network.routers8.msg_count.Writeback_Control::3 591493 -system.ruby.network.routers8.msg_count.Writeback_Control::5 369186 -system.ruby.network.routers8.msg_count.Broadcast_Control::3 626317 -system.ruby.network.routers8.msg_count.Unblock_Control::5 628744 -system.ruby.network.routers8.msg_bytes.Request_Control::2 5018648 -system.ruby.network.routers8.msg_bytes.Request_Control::3 7920 -system.ruby.network.routers8.msg_bytes.Response_Data::4 43704144 -system.ruby.network.routers8.msg_bytes.Writeback_Data::5 15902352 -system.ruby.network.routers8.msg_bytes.Writeback_Control::2 4732128 -system.ruby.network.routers8.msg_bytes.Writeback_Control::3 4731944 -system.ruby.network.routers8.msg_bytes.Writeback_Control::5 2953488 -system.ruby.network.routers8.msg_bytes.Broadcast_Control::3 5010536 -system.ruby.network.routers8.msg_bytes.Unblock_Control::5 5029952 -system.ruby.network.routers9.percent_links_utilized 22.391181 -system.ruby.network.routers9.msg_count.Request_Control::2 627331 -system.ruby.network.routers9.msg_count.Request_Control::3 990 -system.ruby.network.routers9.msg_count.Response_Data::4 627308 -system.ruby.network.routers9.msg_count.Response_Control::4 4364904 -system.ruby.network.routers9.msg_count.Writeback_Data::5 220866 -system.ruby.network.routers9.msg_count.Writeback_Control::2 591516 -system.ruby.network.routers9.msg_count.Writeback_Control::3 591493 -system.ruby.network.routers9.msg_count.Writeback_Control::5 369186 -system.ruby.network.routers9.msg_count.Broadcast_Control::3 4384219 -system.ruby.network.routers9.msg_count.Unblock_Control::5 628744 -system.ruby.network.routers9.msg_bytes.Request_Control::2 5018648 -system.ruby.network.routers9.msg_bytes.Request_Control::3 7920 -system.ruby.network.routers9.msg_bytes.Response_Data::4 45166176 -system.ruby.network.routers9.msg_bytes.Response_Control::4 34919232 -system.ruby.network.routers9.msg_bytes.Writeback_Data::5 15902352 -system.ruby.network.routers9.msg_bytes.Writeback_Control::2 4732128 -system.ruby.network.routers9.msg_bytes.Writeback_Control::3 4731944 -system.ruby.network.routers9.msg_bytes.Writeback_Control::5 2953488 -system.ruby.network.routers9.msg_bytes.Broadcast_Control::3 35073752 -system.ruby.network.routers9.msg_bytes.Unblock_Control::5 5029952 -system.ruby.network.msg_count.Request_Control 1884963 -system.ruby.network.msg_count.Response_Data 1881922 -system.ruby.network.msg_count.Response_Control 13094712 -system.ruby.network.msg_count.Writeback_Data 662598 -system.ruby.network.msg_count.Writeback_Control 4656585 -system.ruby.network.msg_count.Broadcast_Control 9394755 -system.ruby.network.msg_count.Unblock_Control 1886232 -system.ruby.network.msg_byte.Request_Control 15079704 -system.ruby.network.msg_byte.Response_Data 135498384 -system.ruby.network.msg_byte.Response_Control 104757696 -system.ruby.network.msg_byte.Writeback_Data 47707056 -system.ruby.network.msg_byte.Writeback_Control 37252680 -system.ruby.network.msg_byte.Broadcast_Control 75158040 -system.ruby.network.msg_byte.Unblock_Control 15089856 +system.ruby.l1_cntrl3.L2cache.demand_hits 68 # Number of cache demand hits +system.ruby.l1_cntrl3.L2cache.demand_misses 78223 # Number of cache demand misses +system.ruby.l1_cntrl3.L2cache.demand_accesses 78291 # Number of cache demand accesses +system.ruby.l1_cntrl4.L1Dcache.demand_hits 28 # Number of cache demand hits +system.ruby.l1_cntrl4.L1Dcache.demand_misses 78804 # Number of cache demand misses +system.ruby.l1_cntrl4.L1Dcache.demand_accesses 78832 # Number of cache demand accesses +system.ruby.l1_cntrl4.L1Icache.demand_hits 0 # Number of cache demand hits +system.ruby.l1_cntrl4.L1Icache.demand_misses 0 # Number of cache demand misses +system.ruby.l1_cntrl4.L1Icache.demand_accesses 0 # Number of cache demand accesses +system.ruby.l1_cntrl4.L2cache.demand_hits 69 # Number of cache demand hits +system.ruby.l1_cntrl4.L2cache.demand_misses 78735 # Number of cache demand misses +system.ruby.l1_cntrl4.L2cache.demand_accesses 78804 # Number of cache demand accesses +system.ruby.l1_cntrl5.L1Dcache.demand_hits 17 # Number of cache demand hits +system.ruby.l1_cntrl5.L1Dcache.demand_misses 78597 # Number of cache demand misses +system.ruby.l1_cntrl5.L1Dcache.demand_accesses 78614 # Number of cache demand accesses +system.ruby.l1_cntrl5.L1Icache.demand_hits 0 # Number of cache demand hits +system.ruby.l1_cntrl5.L1Icache.demand_misses 0 # Number of cache demand misses +system.ruby.l1_cntrl5.L1Icache.demand_accesses 0 # Number of cache demand accesses +system.ruby.l1_cntrl5.L2cache.demand_hits 61 # Number of cache demand hits +system.ruby.l1_cntrl5.L2cache.demand_misses 78536 # Number of cache demand misses +system.ruby.l1_cntrl5.L2cache.demand_accesses 78597 # Number of cache demand accesses +system.ruby.l1_cntrl6.L1Dcache.demand_hits 14 # Number of cache demand hits +system.ruby.l1_cntrl6.L1Dcache.demand_misses 78489 # Number of cache demand misses +system.ruby.l1_cntrl6.L1Dcache.demand_accesses 78503 # Number of cache demand accesses +system.ruby.l1_cntrl6.L1Icache.demand_hits 0 # Number of cache demand hits +system.ruby.l1_cntrl6.L1Icache.demand_misses 0 # Number of cache demand misses +system.ruby.l1_cntrl6.L1Icache.demand_accesses 0 # Number of cache demand accesses +system.ruby.l1_cntrl6.L2cache.demand_hits 82 # Number of cache demand hits +system.ruby.l1_cntrl6.L2cache.demand_misses 78407 # Number of cache demand misses +system.ruby.l1_cntrl6.L2cache.demand_accesses 78489 # Number of cache demand accesses +system.ruby.l1_cntrl7.L1Dcache.demand_hits 15 # Number of cache demand hits +system.ruby.l1_cntrl7.L1Dcache.demand_misses 78561 # Number of cache demand misses +system.ruby.l1_cntrl7.L1Dcache.demand_accesses 78576 # Number of cache demand accesses +system.ruby.l1_cntrl7.L1Icache.demand_hits 0 # Number of cache demand hits +system.ruby.l1_cntrl7.L1Icache.demand_misses 0 # Number of cache demand misses +system.ruby.l1_cntrl7.L1Icache.demand_accesses 0 # Number of cache demand accesses +system.ruby.l1_cntrl7.L2cache.demand_hits 76 # Number of cache demand hits +system.ruby.l1_cntrl7.L2cache.demand_misses 78485 # Number of cache demand misses +system.ruby.l1_cntrl7.L2cache.demand_accesses 78561 # Number of cache demand accesses system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.cpu0.num_reads 99219 # number of read accesses completed -system.cpu0.num_writes 55551 # number of write accesses completed -system.cpu0.num_copies 0 # number of copy accesses completed -system.cpu1.num_reads 99783 # number of read accesses completed -system.cpu1.num_writes 55285 # number of write accesses completed -system.cpu1.num_copies 0 # number of copy accesses completed -system.cpu2.num_reads 98991 # number of read accesses completed -system.cpu2.num_writes 55373 # number of write accesses completed -system.cpu2.num_copies 0 # number of copy accesses completed -system.cpu3.num_reads 99031 # number of read accesses completed -system.cpu3.num_writes 55449 # number of write accesses completed -system.cpu3.num_copies 0 # number of copy accesses completed -system.cpu4.num_reads 98792 # number of read accesses completed -system.cpu4.num_writes 55139 # number of write accesses completed -system.cpu4.num_copies 0 # number of copy accesses completed -system.cpu5.num_reads 99529 # number of read accesses completed -system.cpu5.num_writes 55264 # number of write accesses completed -system.cpu5.num_copies 0 # number of copy accesses completed -system.cpu6.num_reads 100000 # number of read accesses completed -system.cpu6.num_writes 55596 # number of write accesses completed -system.cpu6.num_copies 0 # number of copy accesses completed -system.cpu7.num_reads 98769 # number of read accesses completed -system.cpu7.num_writes 55429 # number of write accesses completed -system.cpu7.num_copies 0 # number of copy accesses completed -system.ruby.network.routers0.throttle0.link_utilization 19.712173 -system.ruby.network.routers0.throttle0.msg_count.Request_Control::3 126 -system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 78654 -system.ruby.network.routers0.throttle0.msg_count.Response_Control::4 547231 -system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 74259 -system.ruby.network.routers0.throttle0.msg_count.Broadcast_Control::3 547799 -system.ruby.network.routers0.throttle0.msg_bytes.Request_Control::3 1008 -system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 5663088 -system.ruby.network.routers0.throttle0.msg_bytes.Response_Control::4 4377848 -system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 594072 -system.ruby.network.routers0.throttle0.msg_bytes.Broadcast_Control::3 4382392 -system.ruby.network.routers0.throttle1.link_utilization 11.510746 -system.ruby.network.routers0.throttle1.msg_count.Request_Control::2 78659 -system.ruby.network.routers0.throttle1.msg_count.Response_Data::4 2501 -system.ruby.network.routers0.throttle1.msg_count.Response_Control::4 545424 -system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::5 27808 -system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::2 74263 -system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::5 46285 -system.ruby.network.routers0.throttle1.msg_count.Unblock_Control::5 78821 -system.ruby.network.routers0.throttle1.msg_bytes.Request_Control::2 629272 -system.ruby.network.routers0.throttle1.msg_bytes.Response_Data::4 180072 -system.ruby.network.routers0.throttle1.msg_bytes.Response_Control::4 4363392 -system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::5 2002176 -system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::2 594104 -system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::5 370280 -system.ruby.network.routers0.throttle1.msg_bytes.Unblock_Control::5 630568 -system.ruby.network.routers1.throttle0.link_utilization 19.657361 -system.ruby.network.routers1.throttle0.msg_count.Request_Control::3 117 -system.ruby.network.routers1.throttle0.msg_count.Response_Data::4 78324 -system.ruby.network.routers1.throttle0.msg_count.Response_Control::4 545059 -system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::3 73878 -system.ruby.network.routers1.throttle0.msg_count.Broadcast_Control::3 548111 -system.ruby.network.routers1.throttle0.msg_bytes.Request_Control::3 936 -system.ruby.network.routers1.throttle0.msg_bytes.Response_Data::4 5639328 -system.ruby.network.routers1.throttle0.msg_bytes.Response_Control::4 4360472 -system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::3 591024 -system.ruby.network.routers1.throttle0.msg_bytes.Broadcast_Control::3 4384888 -system.ruby.network.routers1.throttle1.link_utilization 11.475517 -system.ruby.network.routers1.throttle1.msg_count.Request_Control::2 78327 -system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 2545 -system.ruby.network.routers1.throttle1.msg_count.Response_Control::4 545683 -system.ruby.network.routers1.throttle1.msg_count.Writeback_Data::5 27485 -system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::2 73881 -system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::5 46209 -system.ruby.network.routers1.throttle1.msg_count.Unblock_Control::5 78508 -system.ruby.network.routers1.throttle1.msg_bytes.Request_Control::2 626616 -system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 183240 -system.ruby.network.routers1.throttle1.msg_bytes.Response_Control::4 4365464 -system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Data::5 1978920 -system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::2 591048 -system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::5 369672 -system.ruby.network.routers1.throttle1.msg_bytes.Unblock_Control::5 628064 -system.ruby.network.routers2.throttle0.link_utilization 19.677511 -system.ruby.network.routers2.throttle0.msg_count.Request_Control::3 123 -system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 78442 -system.ruby.network.routers2.throttle0.msg_count.Response_Control::4 545919 -system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 73986 -system.ruby.network.routers2.throttle0.msg_count.Broadcast_Control::3 547994 -system.ruby.network.routers2.throttle0.msg_bytes.Request_Control::3 984 -system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 5647824 -system.ruby.network.routers2.throttle0.msg_bytes.Response_Control::4 4367352 -system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 591888 -system.ruby.network.routers2.throttle0.msg_bytes.Broadcast_Control::3 4383952 -system.ruby.network.routers2.throttle1.link_utilization 11.487666 -system.ruby.network.routers2.throttle1.msg_count.Request_Control::2 78445 -system.ruby.network.routers2.throttle1.msg_count.Response_Data::4 2553 -system.ruby.network.routers2.throttle1.msg_count.Response_Control::4 545564 -system.ruby.network.routers2.throttle1.msg_count.Writeback_Data::5 27579 -system.ruby.network.routers2.throttle1.msg_count.Writeback_Control::2 73989 -system.ruby.network.routers2.throttle1.msg_count.Writeback_Control::5 46222 -system.ruby.network.routers2.throttle1.msg_count.Unblock_Control::5 78627 -system.ruby.network.routers2.throttle1.msg_bytes.Request_Control::2 627560 -system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::4 183816 -system.ruby.network.routers2.throttle1.msg_bytes.Response_Control::4 4364512 -system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Data::5 1985688 -system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Control::2 591912 -system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Control::5 369776 -system.ruby.network.routers2.throttle1.msg_bytes.Unblock_Control::5 629016 -system.ruby.network.routers3.throttle0.link_utilization 19.690143 -system.ruby.network.routers3.throttle0.msg_count.Request_Control::3 103 -system.ruby.network.routers3.throttle0.msg_count.Response_Data::4 78534 -system.ruby.network.routers3.throttle0.msg_count.Response_Control::4 546318 -system.ruby.network.routers3.throttle0.msg_count.Writeback_Control::3 74056 -system.ruby.network.routers3.throttle0.msg_count.Broadcast_Control::3 547920 -system.ruby.network.routers3.throttle0.msg_bytes.Request_Control::3 824 -system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::4 5654448 -system.ruby.network.routers3.throttle0.msg_bytes.Response_Control::4 4370544 -system.ruby.network.routers3.throttle0.msg_bytes.Writeback_Control::3 592448 -system.ruby.network.routers3.throttle0.msg_bytes.Broadcast_Control::3 4383360 -system.ruby.network.routers3.throttle1.link_utilization 11.499479 -system.ruby.network.routers3.throttle1.msg_count.Request_Control::2 78537 -system.ruby.network.routers3.throttle1.msg_count.Response_Data::4 2559 -system.ruby.network.routers3.throttle1.msg_count.Response_Control::4 545464 -system.ruby.network.routers3.throttle1.msg_count.Writeback_Data::5 27685 -system.ruby.network.routers3.throttle1.msg_count.Writeback_Control::2 74059 -system.ruby.network.routers3.throttle1.msg_count.Writeback_Control::5 46186 -system.ruby.network.routers3.throttle1.msg_count.Unblock_Control::5 78718 -system.ruby.network.routers3.throttle1.msg_bytes.Request_Control::2 628296 -system.ruby.network.routers3.throttle1.msg_bytes.Response_Data::4 184248 -system.ruby.network.routers3.throttle1.msg_bytes.Response_Control::4 4363712 -system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::5 1993320 -system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::2 592472 -system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::5 369488 -system.ruby.network.routers3.throttle1.msg_bytes.Unblock_Control::5 629744 -system.ruby.network.routers4.throttle0.link_utilization 19.648489 -system.ruby.network.routers4.throttle0.msg_count.Request_Control::3 145 -system.ruby.network.routers4.throttle0.msg_count.Response_Data::4 78267 -system.ruby.network.routers4.throttle0.msg_count.Response_Control::4 544725 -system.ruby.network.routers4.throttle0.msg_count.Writeback_Control::3 73807 -system.ruby.network.routers4.throttle0.msg_count.Broadcast_Control::3 548156 -system.ruby.network.routers4.throttle0.msg_bytes.Request_Control::3 1160 -system.ruby.network.routers4.throttle0.msg_bytes.Response_Data::4 5635224 -system.ruby.network.routers4.throttle0.msg_bytes.Response_Control::4 4357800 -system.ruby.network.routers4.throttle0.msg_bytes.Writeback_Control::3 590456 -system.ruby.network.routers4.throttle0.msg_bytes.Broadcast_Control::3 4385248 -system.ruby.network.routers4.throttle1.link_utilization 11.495457 -system.ruby.network.routers4.throttle1.msg_count.Request_Control::2 78271 -system.ruby.network.routers4.throttle1.msg_count.Response_Data::4 2504 -system.ruby.network.routers4.throttle1.msg_count.Response_Control::4 545797 -system.ruby.network.routers4.throttle1.msg_count.Writeback_Data::5 27786 -system.ruby.network.routers4.throttle1.msg_count.Writeback_Control::2 73811 -system.ruby.network.routers4.throttle1.msg_count.Writeback_Control::5 45834 -system.ruby.network.routers4.throttle1.msg_count.Unblock_Control::5 78454 -system.ruby.network.routers4.throttle1.msg_bytes.Request_Control::2 626168 -system.ruby.network.routers4.throttle1.msg_bytes.Response_Data::4 180288 -system.ruby.network.routers4.throttle1.msg_bytes.Response_Control::4 4366376 -system.ruby.network.routers4.throttle1.msg_bytes.Writeback_Data::5 2000592 -system.ruby.network.routers4.throttle1.msg_bytes.Writeback_Control::2 590488 -system.ruby.network.routers4.throttle1.msg_bytes.Writeback_Control::5 366672 -system.ruby.network.routers4.throttle1.msg_bytes.Unblock_Control::5 627632 -system.ruby.network.routers5.throttle0.link_utilization 19.655041 -system.ruby.network.routers5.throttle0.msg_count.Request_Control::3 113 -system.ruby.network.routers5.throttle0.msg_count.Response_Data::4 78327 -system.ruby.network.routers5.throttle0.msg_count.Response_Control::4 544960 -system.ruby.network.routers5.throttle0.msg_count.Writeback_Control::3 73737 -system.ruby.network.routers5.throttle0.msg_count.Broadcast_Control::3 548107 -system.ruby.network.routers5.throttle0.msg_bytes.Request_Control::3 904 -system.ruby.network.routers5.throttle0.msg_bytes.Response_Data::4 5639544 -system.ruby.network.routers5.throttle0.msg_bytes.Response_Control::4 4359680 -system.ruby.network.routers5.throttle0.msg_bytes.Writeback_Control::3 589896 -system.ruby.network.routers5.throttle0.msg_bytes.Broadcast_Control::3 4384856 -system.ruby.network.routers5.throttle1.link_utilization 11.459000 -system.ruby.network.routers5.throttle1.msg_count.Request_Control::2 78330 -system.ruby.network.routers5.throttle1.msg_count.Response_Data::4 2543 -system.ruby.network.routers5.throttle1.msg_count.Response_Control::4 545677 -system.ruby.network.routers5.throttle1.msg_count.Writeback_Data::5 27326 -system.ruby.network.routers5.throttle1.msg_count.Writeback_Control::2 73739 -system.ruby.network.routers5.throttle1.msg_count.Writeback_Control::5 46227 -system.ruby.network.routers5.throttle1.msg_count.Unblock_Control::5 78511 -system.ruby.network.routers5.throttle1.msg_bytes.Request_Control::2 626640 -system.ruby.network.routers5.throttle1.msg_bytes.Response_Data::4 183096 -system.ruby.network.routers5.throttle1.msg_bytes.Response_Control::4 4365416 -system.ruby.network.routers5.throttle1.msg_bytes.Writeback_Data::5 1967472 -system.ruby.network.routers5.throttle1.msg_bytes.Writeback_Control::2 589912 -system.ruby.network.routers5.throttle1.msg_bytes.Writeback_Control::5 369816 -system.ruby.network.routers5.throttle1.msg_bytes.Unblock_Control::5 628088 -system.ruby.network.routers6.throttle0.link_utilization 19.691907 -system.ruby.network.routers6.throttle0.msg_count.Request_Control::3 143 -system.ruby.network.routers6.throttle0.msg_count.Response_Data::4 78539 -system.ruby.network.routers6.throttle0.msg_count.Response_Control::4 546411 -system.ruby.network.routers6.throttle0.msg_count.Writeback_Control::3 74061 -system.ruby.network.routers6.throttle0.msg_count.Broadcast_Control::3 547908 -system.ruby.network.routers6.throttle0.msg_bytes.Request_Control::3 1144 -system.ruby.network.routers6.throttle0.msg_bytes.Response_Data::4 5654808 -system.ruby.network.routers6.throttle0.msg_bytes.Response_Control::4 4371288 -system.ruby.network.routers6.throttle0.msg_bytes.Writeback_Control::3 592488 -system.ruby.network.routers6.throttle0.msg_bytes.Broadcast_Control::3 4383264 -system.ruby.network.routers6.throttle1.link_utilization 11.515145 -system.ruby.network.routers6.throttle1.msg_count.Request_Control::2 78540 -system.ruby.network.routers6.throttle1.msg_count.Response_Data::4 2566 -system.ruby.network.routers6.throttle1.msg_count.Response_Control::4 545485 -system.ruby.network.routers6.throttle1.msg_count.Writeback_Data::5 27859 -system.ruby.network.routers6.throttle1.msg_count.Writeback_Control::2 74064 -system.ruby.network.routers6.throttle1.msg_count.Writeback_Control::5 46043 -system.ruby.network.routers6.throttle1.msg_count.Unblock_Control::5 78695 -system.ruby.network.routers6.throttle1.msg_bytes.Request_Control::2 628320 -system.ruby.network.routers6.throttle1.msg_bytes.Response_Data::4 184752 -system.ruby.network.routers6.throttle1.msg_bytes.Response_Control::4 4363880 -system.ruby.network.routers6.throttle1.msg_bytes.Writeback_Data::5 2005848 -system.ruby.network.routers6.throttle1.msg_bytes.Writeback_Control::2 592512 -system.ruby.network.routers6.throttle1.msg_bytes.Writeback_Control::5 368344 -system.ruby.network.routers6.throttle1.msg_bytes.Unblock_Control::5 629560 -system.ruby.network.routers7.throttle0.link_utilization 19.638807 -system.ruby.network.routers7.throttle0.msg_count.Request_Control::3 120 -system.ruby.network.routers7.throttle0.msg_count.Response_Data::4 78220 -system.ruby.network.routers7.throttle0.msg_count.Response_Control::4 544281 -system.ruby.network.routers7.throttle0.msg_count.Writeback_Control::3 73709 -system.ruby.network.routers7.throttle0.msg_count.Broadcast_Control::3 548224 -system.ruby.network.routers7.throttle0.msg_bytes.Request_Control::3 960 -system.ruby.network.routers7.throttle0.msg_bytes.Response_Data::4 5631840 -system.ruby.network.routers7.throttle0.msg_bytes.Response_Control::4 4354248 -system.ruby.network.routers7.throttle0.msg_bytes.Writeback_Control::3 589672 -system.ruby.network.routers7.throttle0.msg_bytes.Broadcast_Control::3 4385792 -system.ruby.network.routers7.throttle1.link_utilization 11.457688 -system.ruby.network.routers7.throttle1.msg_count.Request_Control::2 78222 -system.ruby.network.routers7.throttle1.msg_count.Response_Data::4 2534 -system.ruby.network.routers7.throttle1.msg_count.Response_Control::4 545810 -system.ruby.network.routers7.throttle1.msg_count.Writeback_Data::5 27338 -system.ruby.network.routers7.throttle1.msg_count.Writeback_Control::2 73710 -system.ruby.network.routers7.throttle1.msg_count.Writeback_Control::5 46180 -system.ruby.network.routers7.throttle1.msg_count.Unblock_Control::5 78410 -system.ruby.network.routers7.throttle1.msg_bytes.Request_Control::2 625776 -system.ruby.network.routers7.throttle1.msg_bytes.Response_Data::4 182448 -system.ruby.network.routers7.throttle1.msg_bytes.Response_Control::4 4366480 -system.ruby.network.routers7.throttle1.msg_bytes.Writeback_Data::5 1968336 -system.ruby.network.routers7.throttle1.msg_bytes.Writeback_Control::2 589680 -system.ruby.network.routers7.throttle1.msg_bytes.Writeback_Control::5 369440 -system.ruby.network.routers7.throttle1.msg_bytes.Unblock_Control::5 627280 -system.ruby.network.routers8.throttle0.link_utilization 44.149143 -system.ruby.network.routers8.throttle0.msg_count.Request_Control::2 627331 -system.ruby.network.routers8.throttle0.msg_count.Writeback_Data::5 220866 -system.ruby.network.routers8.throttle0.msg_count.Writeback_Control::2 591516 -system.ruby.network.routers8.throttle0.msg_count.Writeback_Control::5 369186 -system.ruby.network.routers8.throttle0.msg_count.Unblock_Control::5 628744 -system.ruby.network.routers8.throttle0.msg_bytes.Request_Control::2 5018648 -system.ruby.network.routers8.throttle0.msg_bytes.Writeback_Data::5 15902352 -system.ruby.network.routers8.throttle0.msg_bytes.Writeback_Control::2 4732128 -system.ruby.network.routers8.throttle0.msg_bytes.Writeback_Control::5 2953488 -system.ruby.network.routers8.throttle0.msg_bytes.Unblock_Control::5 5029952 -system.ruby.network.routers8.throttle1.link_utilization 70.160870 -system.ruby.network.routers8.throttle1.msg_count.Request_Control::3 990 -system.ruby.network.routers8.throttle1.msg_count.Response_Data::4 607002 -system.ruby.network.routers8.throttle1.msg_count.Writeback_Control::3 591493 -system.ruby.network.routers8.throttle1.msg_count.Broadcast_Control::3 626317 -system.ruby.network.routers8.throttle1.msg_bytes.Request_Control::3 7920 -system.ruby.network.routers8.throttle1.msg_bytes.Response_Data::4 43704144 -system.ruby.network.routers8.throttle1.msg_bytes.Writeback_Control::3 4731944 -system.ruby.network.routers8.throttle1.msg_bytes.Broadcast_Control::3 5010536 -system.ruby.network.routers9.throttle0.link_utilization 19.712173 -system.ruby.network.routers9.throttle0.msg_count.Request_Control::3 126 -system.ruby.network.routers9.throttle0.msg_count.Response_Data::4 78654 -system.ruby.network.routers9.throttle0.msg_count.Response_Control::4 547231 -system.ruby.network.routers9.throttle0.msg_count.Writeback_Control::3 74259 -system.ruby.network.routers9.throttle0.msg_count.Broadcast_Control::3 547799 -system.ruby.network.routers9.throttle0.msg_bytes.Request_Control::3 1008 -system.ruby.network.routers9.throttle0.msg_bytes.Response_Data::4 5663088 -system.ruby.network.routers9.throttle0.msg_bytes.Response_Control::4 4377848 -system.ruby.network.routers9.throttle0.msg_bytes.Writeback_Control::3 594072 -system.ruby.network.routers9.throttle0.msg_bytes.Broadcast_Control::3 4382392 -system.ruby.network.routers9.throttle1.link_utilization 19.657361 -system.ruby.network.routers9.throttle1.msg_count.Request_Control::3 117 -system.ruby.network.routers9.throttle1.msg_count.Response_Data::4 78324 -system.ruby.network.routers9.throttle1.msg_count.Response_Control::4 545059 -system.ruby.network.routers9.throttle1.msg_count.Writeback_Control::3 73878 -system.ruby.network.routers9.throttle1.msg_count.Broadcast_Control::3 548111 -system.ruby.network.routers9.throttle1.msg_bytes.Request_Control::3 936 -system.ruby.network.routers9.throttle1.msg_bytes.Response_Data::4 5639328 -system.ruby.network.routers9.throttle1.msg_bytes.Response_Control::4 4360472 -system.ruby.network.routers9.throttle1.msg_bytes.Writeback_Control::3 591024 -system.ruby.network.routers9.throttle1.msg_bytes.Broadcast_Control::3 4384888 -system.ruby.network.routers9.throttle2.link_utilization 19.677511 -system.ruby.network.routers9.throttle2.msg_count.Request_Control::3 123 -system.ruby.network.routers9.throttle2.msg_count.Response_Data::4 78442 -system.ruby.network.routers9.throttle2.msg_count.Response_Control::4 545919 -system.ruby.network.routers9.throttle2.msg_count.Writeback_Control::3 73986 -system.ruby.network.routers9.throttle2.msg_count.Broadcast_Control::3 547994 -system.ruby.network.routers9.throttle2.msg_bytes.Request_Control::3 984 -system.ruby.network.routers9.throttle2.msg_bytes.Response_Data::4 5647824 -system.ruby.network.routers9.throttle2.msg_bytes.Response_Control::4 4367352 -system.ruby.network.routers9.throttle2.msg_bytes.Writeback_Control::3 591888 -system.ruby.network.routers9.throttle2.msg_bytes.Broadcast_Control::3 4383952 -system.ruby.network.routers9.throttle3.link_utilization 19.690143 -system.ruby.network.routers9.throttle3.msg_count.Request_Control::3 103 -system.ruby.network.routers9.throttle3.msg_count.Response_Data::4 78534 -system.ruby.network.routers9.throttle3.msg_count.Response_Control::4 546318 -system.ruby.network.routers9.throttle3.msg_count.Writeback_Control::3 74056 -system.ruby.network.routers9.throttle3.msg_count.Broadcast_Control::3 547920 -system.ruby.network.routers9.throttle3.msg_bytes.Request_Control::3 824 -system.ruby.network.routers9.throttle3.msg_bytes.Response_Data::4 5654448 -system.ruby.network.routers9.throttle3.msg_bytes.Response_Control::4 4370544 -system.ruby.network.routers9.throttle3.msg_bytes.Writeback_Control::3 592448 -system.ruby.network.routers9.throttle3.msg_bytes.Broadcast_Control::3 4383360 -system.ruby.network.routers9.throttle4.link_utilization 19.648489 -system.ruby.network.routers9.throttle4.msg_count.Request_Control::3 145 -system.ruby.network.routers9.throttle4.msg_count.Response_Data::4 78267 -system.ruby.network.routers9.throttle4.msg_count.Response_Control::4 544725 -system.ruby.network.routers9.throttle4.msg_count.Writeback_Control::3 73807 -system.ruby.network.routers9.throttle4.msg_count.Broadcast_Control::3 548156 -system.ruby.network.routers9.throttle4.msg_bytes.Request_Control::3 1160 -system.ruby.network.routers9.throttle4.msg_bytes.Response_Data::4 5635224 -system.ruby.network.routers9.throttle4.msg_bytes.Response_Control::4 4357800 -system.ruby.network.routers9.throttle4.msg_bytes.Writeback_Control::3 590456 -system.ruby.network.routers9.throttle4.msg_bytes.Broadcast_Control::3 4385248 -system.ruby.network.routers9.throttle5.link_utilization 19.655041 -system.ruby.network.routers9.throttle5.msg_count.Request_Control::3 113 -system.ruby.network.routers9.throttle5.msg_count.Response_Data::4 78327 -system.ruby.network.routers9.throttle5.msg_count.Response_Control::4 544960 -system.ruby.network.routers9.throttle5.msg_count.Writeback_Control::3 73737 -system.ruby.network.routers9.throttle5.msg_count.Broadcast_Control::3 548107 -system.ruby.network.routers9.throttle5.msg_bytes.Request_Control::3 904 -system.ruby.network.routers9.throttle5.msg_bytes.Response_Data::4 5639544 -system.ruby.network.routers9.throttle5.msg_bytes.Response_Control::4 4359680 -system.ruby.network.routers9.throttle5.msg_bytes.Writeback_Control::3 589896 -system.ruby.network.routers9.throttle5.msg_bytes.Broadcast_Control::3 4384856 -system.ruby.network.routers9.throttle6.link_utilization 19.691939 -system.ruby.network.routers9.throttle6.msg_count.Request_Control::3 143 -system.ruby.network.routers9.throttle6.msg_count.Response_Data::4 78539 -system.ruby.network.routers9.throttle6.msg_count.Response_Control::4 546411 -system.ruby.network.routers9.throttle6.msg_count.Writeback_Control::3 74061 -system.ruby.network.routers9.throttle6.msg_count.Broadcast_Control::3 547908 -system.ruby.network.routers9.throttle6.msg_bytes.Request_Control::3 1144 -system.ruby.network.routers9.throttle6.msg_bytes.Response_Data::4 5654808 -system.ruby.network.routers9.throttle6.msg_bytes.Response_Control::4 4371288 -system.ruby.network.routers9.throttle6.msg_bytes.Writeback_Control::3 592488 -system.ruby.network.routers9.throttle6.msg_bytes.Broadcast_Control::3 4383264 -system.ruby.network.routers9.throttle7.link_utilization 19.638828 -system.ruby.network.routers9.throttle7.msg_count.Request_Control::3 120 -system.ruby.network.routers9.throttle7.msg_count.Response_Data::4 78221 -system.ruby.network.routers9.throttle7.msg_count.Response_Control::4 544281 -system.ruby.network.routers9.throttle7.msg_count.Writeback_Control::3 73709 -system.ruby.network.routers9.throttle7.msg_count.Broadcast_Control::3 548224 -system.ruby.network.routers9.throttle7.msg_bytes.Request_Control::3 960 -system.ruby.network.routers9.throttle7.msg_bytes.Response_Data::4 5631912 -system.ruby.network.routers9.throttle7.msg_bytes.Response_Control::4 4354248 -system.ruby.network.routers9.throttle7.msg_bytes.Writeback_Control::3 589672 -system.ruby.network.routers9.throttle7.msg_bytes.Broadcast_Control::3 4385792 -system.ruby.network.routers9.throttle8.link_utilization 44.149143 -system.ruby.network.routers9.throttle8.msg_count.Request_Control::2 627331 -system.ruby.network.routers9.throttle8.msg_count.Writeback_Data::5 220866 -system.ruby.network.routers9.throttle8.msg_count.Writeback_Control::2 591516 -system.ruby.network.routers9.throttle8.msg_count.Writeback_Control::5 369186 -system.ruby.network.routers9.throttle8.msg_count.Unblock_Control::5 628744 -system.ruby.network.routers9.throttle8.msg_bytes.Request_Control::2 5018648 -system.ruby.network.routers9.throttle8.msg_bytes.Writeback_Data::5 15902352 -system.ruby.network.routers9.throttle8.msg_bytes.Writeback_Control::2 4732128 -system.ruby.network.routers9.throttle8.msg_bytes.Writeback_Control::5 2953488 -system.ruby.network.routers9.throttle8.msg_bytes.Unblock_Control::5 5029952 +system.ruby.network.routers0.percent_links_utilized 15.728579 +system.ruby.network.routers0.msg_count.Request_Control::2 78312 +system.ruby.network.routers0.msg_count.Request_Control::3 136 +system.ruby.network.routers0.msg_count.Response_Data::4 80809 +system.ruby.network.routers0.msg_count.Response_Control::4 1091306 +system.ruby.network.routers0.msg_count.Writeback_Data::5 27751 +system.ruby.network.routers0.msg_count.Writeback_Control::2 73970 +system.ruby.network.routers0.msg_count.Writeback_Control::3 73966 +system.ruby.network.routers0.msg_count.Writeback_Control::5 46017 +system.ruby.network.routers0.msg_count.Broadcast_Control::3 548880 +system.ruby.network.routers0.msg_count.Unblock_Control::5 78505 +system.ruby.network.routers0.msg_bytes.Request_Control::2 626496 +system.ruby.network.routers0.msg_bytes.Request_Control::3 1088 +system.ruby.network.routers0.msg_bytes.Response_Data::4 5818248 +system.ruby.network.routers0.msg_bytes.Response_Control::4 8730448 +system.ruby.network.routers0.msg_bytes.Writeback_Data::5 1998072 +system.ruby.network.routers0.msg_bytes.Writeback_Control::2 591760 +system.ruby.network.routers0.msg_bytes.Writeback_Control::3 591728 +system.ruby.network.routers0.msg_bytes.Writeback_Control::5 368136 +system.ruby.network.routers0.msg_bytes.Broadcast_Control::3 4391040 +system.ruby.network.routers0.msg_bytes.Unblock_Control::5 628040 +system.ruby.network.routers1.percent_links_utilized 15.782026 +system.ruby.network.routers1.msg_count.Request_Control::2 78779 +system.ruby.network.routers1.msg_count.Request_Control::3 148 +system.ruby.network.routers1.msg_count.Response_Data::4 81395 +system.ruby.network.routers1.msg_count.Response_Control::4 1094135 +system.ruby.network.routers1.msg_count.Writeback_Data::5 27827 +system.ruby.network.routers1.msg_count.Writeback_Control::2 74272 +system.ruby.network.routers1.msg_count.Writeback_Control::3 74272 +system.ruby.network.routers1.msg_count.Writeback_Control::5 46271 +system.ruby.network.routers1.msg_count.Broadcast_Control::3 548392 +system.ruby.network.routers1.msg_count.Unblock_Control::5 78951 +system.ruby.network.routers1.msg_bytes.Request_Control::2 630232 +system.ruby.network.routers1.msg_bytes.Request_Control::3 1184 +system.ruby.network.routers1.msg_bytes.Response_Data::4 5860440 +system.ruby.network.routers1.msg_bytes.Response_Control::4 8753080 +system.ruby.network.routers1.msg_bytes.Writeback_Data::5 2003544 +system.ruby.network.routers1.msg_bytes.Writeback_Control::2 594176 +system.ruby.network.routers1.msg_bytes.Writeback_Control::3 594176 +system.ruby.network.routers1.msg_bytes.Writeback_Control::5 370168 +system.ruby.network.routers1.msg_bytes.Broadcast_Control::3 4387136 +system.ruby.network.routers1.msg_bytes.Unblock_Control::5 631608 +system.ruby.network.routers2.percent_links_utilized 15.769611 +system.ruby.network.routers2.msg_count.Request_Control::2 78659 +system.ruby.network.routers2.msg_count.Request_Control::3 126 +system.ruby.network.routers2.msg_count.Response_Data::4 81173 +system.ruby.network.routers2.msg_count.Response_Control::4 1093393 +system.ruby.network.routers2.msg_count.Writeback_Data::5 27922 +system.ruby.network.routers2.msg_count.Writeback_Control::2 74193 +system.ruby.network.routers2.msg_count.Writeback_Control::3 74193 +system.ruby.network.routers2.msg_count.Writeback_Control::5 46097 +system.ruby.network.routers2.msg_count.Broadcast_Control::3 548534 +system.ruby.network.routers2.msg_count.Unblock_Control::5 78830 +system.ruby.network.routers2.msg_bytes.Request_Control::2 629272 +system.ruby.network.routers2.msg_bytes.Request_Control::3 1008 +system.ruby.network.routers2.msg_bytes.Response_Data::4 5844456 +system.ruby.network.routers2.msg_bytes.Response_Control::4 8747144 +system.ruby.network.routers2.msg_bytes.Writeback_Data::5 2010384 +system.ruby.network.routers2.msg_bytes.Writeback_Control::2 593544 +system.ruby.network.routers2.msg_bytes.Writeback_Control::3 593544 +system.ruby.network.routers2.msg_bytes.Writeback_Control::5 368776 +system.ruby.network.routers2.msg_bytes.Broadcast_Control::3 4388272 +system.ruby.network.routers2.msg_bytes.Unblock_Control::5 630640 +system.ruby.network.routers3.percent_links_utilized 15.703970 +system.ruby.network.routers3.msg_count.Request_Control::2 78223 +system.ruby.network.routers3.msg_count.Request_Control::3 132 +system.ruby.network.routers3.msg_count.Response_Data::4 80832 +system.ruby.network.routers3.msg_count.Response_Control::4 1090649 +system.ruby.network.routers3.msg_count.Writeback_Data::5 27301 +system.ruby.network.routers3.msg_count.Writeback_Control::2 73799 +system.ruby.network.routers3.msg_count.Writeback_Control::3 73799 +system.ruby.network.routers3.msg_count.Writeback_Control::5 46306 +system.ruby.network.routers3.msg_count.Broadcast_Control::3 548971 +system.ruby.network.routers3.msg_count.Unblock_Control::5 78412 +system.ruby.network.routers3.msg_bytes.Request_Control::2 625784 +system.ruby.network.routers3.msg_bytes.Request_Control::3 1056 +system.ruby.network.routers3.msg_bytes.Response_Data::4 5819904 +system.ruby.network.routers3.msg_bytes.Response_Control::4 8725192 +system.ruby.network.routers3.msg_bytes.Writeback_Data::5 1965672 +system.ruby.network.routers3.msg_bytes.Writeback_Control::2 590392 +system.ruby.network.routers3.msg_bytes.Writeback_Control::3 590392 +system.ruby.network.routers3.msg_bytes.Writeback_Control::5 370448 +system.ruby.network.routers3.msg_bytes.Broadcast_Control::3 4391768 +system.ruby.network.routers3.msg_bytes.Unblock_Control::5 627296 +system.ruby.network.routers4.percent_links_utilized 15.778847 +system.ruby.network.routers4.msg_count.Request_Control::2 78735 +system.ruby.network.routers4.msg_count.Request_Control::3 123 +system.ruby.network.routers4.msg_count.Response_Data::4 81281 +system.ruby.network.routers4.msg_count.Response_Control::4 1093730 +system.ruby.network.routers4.msg_count.Writeback_Data::5 27948 +system.ruby.network.routers4.msg_count.Writeback_Control::2 74240 +system.ruby.network.routers4.msg_count.Writeback_Control::3 74240 +system.ruby.network.routers4.msg_count.Writeback_Control::5 46087 +system.ruby.network.routers4.msg_count.Broadcast_Control::3 548464 +system.ruby.network.routers4.msg_count.Unblock_Control::5 78938 +system.ruby.network.routers4.msg_bytes.Request_Control::2 629880 +system.ruby.network.routers4.msg_bytes.Request_Control::3 984 +system.ruby.network.routers4.msg_bytes.Response_Data::4 5852232 +system.ruby.network.routers4.msg_bytes.Response_Control::4 8749840 +system.ruby.network.routers4.msg_bytes.Writeback_Data::5 2012256 +system.ruby.network.routers4.msg_bytes.Writeback_Control::2 593920 +system.ruby.network.routers4.msg_bytes.Writeback_Control::3 593920 +system.ruby.network.routers4.msg_bytes.Writeback_Control::5 368696 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+system.ruby.network.routers5.msg_bytes.Response_Data::4 5836392 +system.ruby.network.routers5.msg_bytes.Response_Control::4 8740456 +system.ruby.network.routers5.msg_bytes.Writeback_Data::5 1989504 +system.ruby.network.routers5.msg_bytes.Writeback_Control::2 591984 +system.ruby.network.routers5.msg_bytes.Writeback_Control::3 591976 +system.ruby.network.routers5.msg_bytes.Writeback_Control::5 369400 +system.ruby.network.routers5.msg_bytes.Broadcast_Control::3 4389264 +system.ruby.network.routers5.msg_bytes.Unblock_Control::5 629776 +system.ruby.network.routers6.percent_links_utilized 15.733200 +system.ruby.network.routers6.msg_count.Request_Control::2 78407 +system.ruby.network.routers6.msg_count.Request_Control::3 131 +system.ruby.network.routers6.msg_count.Response_Data::4 80952 +system.ruby.network.routers6.msg_count.Response_Control::4 1091931 +system.ruby.network.routers6.msg_count.Writeback_Data::5 27600 +system.ruby.network.routers6.msg_count.Writeback_Control::2 73996 +system.ruby.network.routers6.msg_count.Writeback_Control::3 73995 +system.ruby.network.routers6.msg_count.Writeback_Control::5 46241 +system.ruby.network.routers6.msg_count.Broadcast_Control::3 548778 +system.ruby.network.routers6.msg_count.Unblock_Control::5 78557 +system.ruby.network.routers6.msg_bytes.Request_Control::2 627256 +system.ruby.network.routers6.msg_bytes.Request_Control::3 1048 +system.ruby.network.routers6.msg_bytes.Response_Data::4 5828544 +system.ruby.network.routers6.msg_bytes.Response_Control::4 8735448 +system.ruby.network.routers6.msg_bytes.Writeback_Data::5 1987200 +system.ruby.network.routers6.msg_bytes.Writeback_Control::2 591968 +system.ruby.network.routers6.msg_bytes.Writeback_Control::3 591960 +system.ruby.network.routers6.msg_bytes.Writeback_Control::5 369928 +system.ruby.network.routers6.msg_bytes.Broadcast_Control::3 4390224 +system.ruby.network.routers6.msg_bytes.Unblock_Control::5 628456 +system.ruby.network.routers7.percent_links_utilized 15.739607 +system.ruby.network.routers7.msg_count.Request_Control::2 78484 +system.ruby.network.routers7.msg_count.Request_Control::3 139 +system.ruby.network.routers7.msg_count.Response_Data::4 81051 +system.ruby.network.routers7.msg_count.Response_Control::4 1092302 +system.ruby.network.routers7.msg_count.Writeback_Data::5 27559 +system.ruby.network.routers7.msg_count.Writeback_Control::2 74059 +system.ruby.network.routers7.msg_count.Writeback_Control::3 74059 +system.ruby.network.routers7.msg_count.Writeback_Control::5 46308 +system.ruby.network.routers7.msg_count.Broadcast_Control::3 548701 +system.ruby.network.routers7.msg_count.Unblock_Control::5 78674 +system.ruby.network.routers7.msg_bytes.Request_Control::2 627872 +system.ruby.network.routers7.msg_bytes.Request_Control::3 1112 +system.ruby.network.routers7.msg_bytes.Response_Data::4 5835672 +system.ruby.network.routers7.msg_bytes.Response_Control::4 8738416 +system.ruby.network.routers7.msg_bytes.Writeback_Data::5 1984248 +system.ruby.network.routers7.msg_bytes.Writeback_Control::2 592472 +system.ruby.network.routers7.msg_bytes.Writeback_Control::3 592472 +system.ruby.network.routers7.msg_bytes.Writeback_Control::5 370464 +system.ruby.network.routers7.msg_bytes.Broadcast_Control::3 4389608 +system.ruby.network.routers7.msg_bytes.Unblock_Control::5 629392 +system.ruby.network.routers8.percent_links_utilized 57.777998 +system.ruby.network.routers8.msg_count.Request_Control::2 628133 +system.ruby.network.routers8.msg_count.Request_Control::3 1073 +system.ruby.network.routers8.msg_count.Response_Data::4 607668 +system.ruby.network.routers8.msg_count.Writeback_Data::5 221539 +system.ruby.network.routers8.msg_count.Writeback_Control::2 592525 +system.ruby.network.routers8.msg_count.Writeback_Control::3 592521 +system.ruby.network.routers8.msg_count.Writeback_Control::5 369502 +system.ruby.network.routers8.msg_count.Broadcast_Control::3 627055 +system.ruby.network.routers8.msg_count.Unblock_Control::5 629589 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+system.ruby.network.routers9.throttle1.msg_bytes.Broadcast_Control::3 4387144 +system.ruby.network.routers9.throttle2.link_utilization 19.903717 +system.ruby.network.routers9.throttle2.msg_count.Request_Control::3 126 +system.ruby.network.routers9.throttle2.msg_count.Response_Data::4 78656 +system.ruby.network.routers9.throttle2.msg_count.Response_Control::4 547252 +system.ruby.network.routers9.throttle2.msg_count.Writeback_Control::3 74193 +system.ruby.network.routers9.throttle2.msg_count.Broadcast_Control::3 548535 +system.ruby.network.routers9.throttle2.msg_bytes.Request_Control::3 1008 +system.ruby.network.routers9.throttle2.msg_bytes.Response_Data::4 5663232 +system.ruby.network.routers9.throttle2.msg_bytes.Response_Control::4 4378016 +system.ruby.network.routers9.throttle2.msg_bytes.Writeback_Control::3 593544 +system.ruby.network.routers9.throttle2.msg_bytes.Broadcast_Control::3 4388280 +system.ruby.network.routers9.throttle3.link_utilization 19.829868 +system.ruby.network.routers9.throttle3.msg_count.Request_Control::3 132 +system.ruby.network.routers9.throttle3.msg_count.Response_Data::4 78220 +system.ruby.network.routers9.throttle3.msg_count.Response_Control::4 544159 +system.ruby.network.routers9.throttle3.msg_count.Writeback_Control::3 73799 +system.ruby.network.routers9.throttle3.msg_count.Broadcast_Control::3 548972 +system.ruby.network.routers9.throttle3.msg_bytes.Request_Control::3 1056 +system.ruby.network.routers9.throttle3.msg_bytes.Response_Data::4 5631840 +system.ruby.network.routers9.throttle3.msg_bytes.Response_Control::4 4353272 +system.ruby.network.routers9.throttle3.msg_bytes.Writeback_Control::3 590392 +system.ruby.network.routers9.throttle3.msg_bytes.Broadcast_Control::3 4391776 +system.ruby.network.routers9.throttle4.link_utilization 19.915449 +system.ruby.network.routers9.throttle4.msg_count.Request_Control::3 123 +system.ruby.network.routers9.throttle4.msg_count.Response_Data::4 78733 +system.ruby.network.routers9.throttle4.msg_count.Response_Control::4 547692 +system.ruby.network.routers9.throttle4.msg_count.Writeback_Control::3 74240 +system.ruby.network.routers9.throttle4.msg_count.Broadcast_Control::3 548465 +system.ruby.network.routers9.throttle4.msg_bytes.Request_Control::3 984 +system.ruby.network.routers9.throttle4.msg_bytes.Response_Data::4 5668776 +system.ruby.network.routers9.throttle4.msg_bytes.Response_Control::4 4381536 +system.ruby.network.routers9.throttle4.msg_bytes.Writeback_Control::3 593920 +system.ruby.network.routers9.throttle4.msg_bytes.Broadcast_Control::3 4387720 +system.ruby.network.routers9.throttle5.link_utilization 19.881153 +system.ruby.network.routers9.throttle5.msg_count.Request_Control::3 138 +system.ruby.network.routers9.throttle5.msg_count.Response_Data::4 78533 +system.ruby.network.routers9.throttle5.msg_count.Response_Control::4 546290 +system.ruby.network.routers9.throttle5.msg_count.Writeback_Control::3 73997 +system.ruby.network.routers9.throttle5.msg_count.Broadcast_Control::3 548659 +system.ruby.network.routers9.throttle5.msg_bytes.Request_Control::3 1104 +system.ruby.network.routers9.throttle5.msg_bytes.Response_Data::4 5654376 +system.ruby.network.routers9.throttle5.msg_bytes.Response_Control::4 4370320 +system.ruby.network.routers9.throttle5.msg_bytes.Writeback_Control::3 591976 +system.ruby.network.routers9.throttle5.msg_bytes.Broadcast_Control::3 4389272 +system.ruby.network.routers9.throttle6.link_utilization 19.862383 +system.ruby.network.routers9.throttle6.msg_count.Request_Control::3 131 +system.ruby.network.routers9.throttle6.msg_count.Response_Data::4 78404 +system.ruby.network.routers9.throttle6.msg_count.Response_Control::4 545570 +system.ruby.network.routers9.throttle6.msg_count.Writeback_Control::3 73995 +system.ruby.network.routers9.throttle6.msg_count.Broadcast_Control::3 548778 +system.ruby.network.routers9.throttle6.msg_bytes.Request_Control::3 1048 +system.ruby.network.routers9.throttle6.msg_bytes.Response_Data::4 5645088 +system.ruby.network.routers9.throttle6.msg_bytes.Response_Control::4 4364560 +system.ruby.network.routers9.throttle6.msg_bytes.Writeback_Control::3 591960 +system.ruby.network.routers9.throttle6.msg_bytes.Broadcast_Control::3 4390224 +system.ruby.network.routers9.throttle7.link_utilization 19.874762 +system.ruby.network.routers9.throttle7.msg_count.Request_Control::3 139 +system.ruby.network.routers9.throttle7.msg_count.Response_Data::4 78483 +system.ruby.network.routers9.throttle7.msg_count.Response_Control::4 546031 +system.ruby.network.routers9.throttle7.msg_count.Writeback_Control::3 74059 +system.ruby.network.routers9.throttle7.msg_count.Broadcast_Control::3 548702 +system.ruby.network.routers9.throttle7.msg_bytes.Request_Control::3 1112 +system.ruby.network.routers9.throttle7.msg_bytes.Response_Data::4 5650776 +system.ruby.network.routers9.throttle7.msg_bytes.Response_Control::4 4368248 +system.ruby.network.routers9.throttle7.msg_bytes.Writeback_Control::3 592472 +system.ruby.network.routers9.throttle7.msg_bytes.Broadcast_Control::3 4389616 +system.ruby.network.routers9.throttle8.link_utilization 44.657025 +system.ruby.network.routers9.throttle8.msg_count.Request_Control::2 628134 +system.ruby.network.routers9.throttle8.msg_count.Writeback_Data::5 221539 +system.ruby.network.routers9.throttle8.msg_count.Writeback_Control::2 592526 +system.ruby.network.routers9.throttle8.msg_count.Writeback_Control::5 369502 +system.ruby.network.routers9.throttle8.msg_count.Unblock_Control::5 629589 +system.ruby.network.routers9.throttle8.msg_bytes.Request_Control::2 5025072 +system.ruby.network.routers9.throttle8.msg_bytes.Writeback_Data::5 15950808 +system.ruby.network.routers9.throttle8.msg_bytes.Writeback_Control::2 4740208 +system.ruby.network.routers9.throttle8.msg_bytes.Writeback_Control::5 2956016 +system.ruby.network.routers9.throttle8.msg_bytes.Unblock_Control::5 5036712 system.ruby.LD.latency_hist::bucket_size 512 system.ruby.LD.latency_hist::max_bucket 5119 -system.ruby.LD.latency_hist::samples 404465 -system.ruby.LD.latency_hist::mean 970.299534 -system.ruby.LD.latency_hist::gmean 692.486480 -system.ruby.LD.latency_hist::stdev 679.694632 -system.ruby.LD.latency_hist | 150760 37.27% 37.27% | 74841 18.50% 55.78% | 73607 18.20% 73.98% | 78428 19.39% 93.37% | 24696 6.11% 99.47% | 2062 0.51% 99.98% | 68 0.02% 100.00% | 3 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.latency_hist::total 404465 +system.ruby.LD.latency_hist::samples 404426 +system.ruby.LD.latency_hist::mean 960.911900 +system.ruby.LD.latency_hist::gmean 686.068526 +system.ruby.LD.latency_hist::stdev 671.376530 +system.ruby.LD.latency_hist | 151361 37.43% 37.43% | 74618 18.45% 55.88% | 75709 18.72% 74.60% | 78644 19.45% 94.04% | 22474 5.56% 99.60% | 1576 0.39% 99.99% | 44 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.latency_hist::total 404426 system.ruby.LD.hit_latency_hist::bucket_size 128 system.ruby.LD.hit_latency_hist::max_bucket 1279 -system.ruby.LD.hit_latency_hist::samples 430 -system.ruby.LD.hit_latency_hist::mean 108.311628 -system.ruby.LD.hit_latency_hist::gmean 37.444576 -system.ruby.LD.hit_latency_hist::stdev 140.737967 -system.ruby.LD.hit_latency_hist | 301 70.00% 70.00% | 77 17.91% 87.91% | 28 6.51% 94.42% | 15 3.49% 97.91% | 5 1.16% 99.07% | 2 0.47% 99.53% | 1 0.23% 99.77% | 0 0.00% 99.77% | 1 0.23% 100.00% | 0 0.00% 100.00% -system.ruby.LD.hit_latency_hist::total 430 +system.ruby.LD.hit_latency_hist::samples 463 +system.ruby.LD.hit_latency_hist::mean 100.805616 +system.ruby.LD.hit_latency_hist::gmean 32.902089 +system.ruby.LD.hit_latency_hist::stdev 133.872383 +system.ruby.LD.hit_latency_hist | 323 69.76% 69.76% | 89 19.22% 88.98% | 32 6.91% 95.90% | 8 1.73% 97.62% | 5 1.08% 98.70% | 3 0.65% 99.35% | 3 0.65% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.hit_latency_hist::total 463 system.ruby.LD.miss_latency_hist::bucket_size 512 system.ruby.LD.miss_latency_hist::max_bucket 5119 -system.ruby.LD.miss_latency_hist::samples 404035 -system.ruby.LD.miss_latency_hist::mean 971.216917 -system.ruby.LD.miss_latency_hist::gmean 694.639931 -system.ruby.LD.miss_latency_hist::stdev 679.458476 -system.ruby.LD.miss_latency_hist | 150339 37.21% 37.21% | 74833 18.52% 55.73% | 73606 18.22% 73.95% | 78428 19.41% 93.36% | 24696 6.11% 99.47% | 2062 0.51% 99.98% | 68 0.02% 100.00% | 3 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.miss_latency_hist::total 404035 +system.ruby.LD.miss_latency_hist::samples 403963 +system.ruby.LD.miss_latency_hist::mean 961.897706 +system.ruby.LD.miss_latency_hist::gmean 688.461131 +system.ruby.LD.miss_latency_hist::stdev 671.113774 +system.ruby.LD.miss_latency_hist | 150909 37.36% 37.36% | 74607 18.47% 55.83% | 75709 18.74% 74.57% | 78644 19.47% 94.04% | 22474 5.56% 99.60% | 1576 0.39% 99.99% | 44 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.miss_latency_hist::total 403963 system.ruby.ST.latency_hist::bucket_size 512 system.ruby.ST.latency_hist::max_bucket 5119 -system.ruby.ST.latency_hist::samples 223518 -system.ruby.ST.latency_hist::mean 970.719714 -system.ruby.ST.latency_hist::gmean 694.060578 -system.ruby.ST.latency_hist::stdev 677.980523 -system.ruby.ST.latency_hist | 83291 37.26% 37.26% | 41192 18.43% 55.69% | 40797 18.25% 73.94% | 43602 19.51% 93.45% | 13548 6.06% 99.51% | 1048 0.47% 99.98% | 38 0.02% 100.00% | 2 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.latency_hist::total 223518 +system.ruby.ST.latency_hist::samples 224376 +system.ruby.ST.latency_hist::mean 958.900172 +system.ruby.ST.latency_hist::gmean 685.730341 +system.ruby.ST.latency_hist::stdev 669.491597 +system.ruby.ST.latency_hist | 84132 37.50% 37.50% | 41367 18.44% 55.93% | 42120 18.77% 74.70% | 43688 19.47% 94.18% | 12162 5.42% 99.60% | 892 0.40% 99.99% | 15 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.latency_hist::total 224376 system.ruby.ST.hit_latency_hist::bucket_size 128 system.ruby.ST.hit_latency_hist::max_bucket 1279 -system.ruby.ST.hit_latency_hist::samples 244 -system.ruby.ST.hit_latency_hist::mean 122.106557 -system.ruby.ST.hit_latency_hist::gmean 40.296267 -system.ruby.ST.hit_latency_hist::stdev 171.556530 -system.ruby.ST.hit_latency_hist | 160 65.57% 65.57% | 49 20.08% 85.66% | 20 8.20% 93.85% | 7 2.87% 96.72% | 3 1.23% 97.95% | 1 0.41% 98.36% | 2 0.82% 99.18% | 0 0.00% 99.18% | 1 0.41% 99.59% | 1 0.41% 100.00% -system.ruby.ST.hit_latency_hist::total 244 +system.ruby.ST.hit_latency_hist::samples 225 +system.ruby.ST.hit_latency_hist::mean 90.933333 +system.ruby.ST.hit_latency_hist::gmean 31.648307 +system.ruby.ST.hit_latency_hist::stdev 110.860031 +system.ruby.ST.hit_latency_hist | 162 72.00% 72.00% | 42 18.67% 90.67% | 18 8.00% 98.67% | 2 0.89% 99.56% | 0 0.00% 99.56% | 1 0.44% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.hit_latency_hist::total 225 system.ruby.ST.miss_latency_hist::bucket_size 512 system.ruby.ST.miss_latency_hist::max_bucket 5119 -system.ruby.ST.miss_latency_hist::samples 223274 -system.ruby.ST.miss_latency_hist::mean 971.647102 -system.ruby.ST.miss_latency_hist::gmean 696.222826 -system.ruby.ST.miss_latency_hist::stdev 677.746286 -system.ruby.ST.miss_latency_hist | 83055 37.20% 37.20% | 41186 18.45% 55.65% | 40795 18.27% 73.92% | 43602 19.53% 93.44% | 13548 6.07% 99.51% | 1048 0.47% 99.98% | 38 0.02% 100.00% | 2 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.miss_latency_hist::total 223274 +system.ruby.ST.miss_latency_hist::samples 224151 +system.ruby.ST.miss_latency_hist::mean 959.771426 +system.ruby.ST.miss_latency_hist::gmean 687.850771 +system.ruby.ST.miss_latency_hist::stdev 669.253056 +system.ruby.ST.miss_latency_hist | 83908 37.43% 37.43% | 41366 18.45% 55.89% | 42120 18.79% 74.68% | 43688 19.49% 94.17% | 12162 5.43% 99.60% | 892 0.40% 99.99% | 15 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.miss_latency_hist::total 224151 system.ruby.L1Cache.hit_mach_latency_hist::bucket_size 1 system.ruby.L1Cache.hit_mach_latency_hist::max_bucket 9 -system.ruby.L1Cache.hit_mach_latency_hist::samples 123 +system.ruby.L1Cache.hit_mach_latency_hist::samples 145 system.ruby.L1Cache.hit_mach_latency_hist::mean 2 system.ruby.L1Cache.hit_mach_latency_hist::gmean 2 -system.ruby.L1Cache.hit_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 123 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache.hit_mach_latency_hist::total 123 +system.ruby.L1Cache.hit_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 145 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache.hit_mach_latency_hist::total 145 system.ruby.L1Cache.miss_mach_latency_hist::bucket_size 512 system.ruby.L1Cache.miss_mach_latency_hist::max_bucket 5119 -system.ruby.L1Cache.miss_mach_latency_hist::samples 22727 -system.ruby.L1Cache.miss_mach_latency_hist::mean 917.922031 -system.ruby.L1Cache.miss_mach_latency_hist::gmean 627.174318 -system.ruby.L1Cache.miss_mach_latency_hist::stdev 674.707077 -system.ruby.L1Cache.miss_mach_latency_hist | 9145 40.24% 40.24% | 4043 17.79% 58.03% | 4103 18.05% 76.08% | 4239 18.65% 94.73% | 1113 4.90% 99.63% | 82 0.36% 99.99% | 1 0.00% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache.miss_mach_latency_hist::total 22727 +system.ruby.L1Cache.miss_mach_latency_hist::samples 23221 +system.ruby.L1Cache.miss_mach_latency_hist::mean 918.506481 +system.ruby.L1Cache.miss_mach_latency_hist::gmean 632.567536 +system.ruby.L1Cache.miss_mach_latency_hist::stdev 669.101339 +system.ruby.L1Cache.miss_mach_latency_hist | 9304 40.07% 40.07% | 4045 17.42% 57.49% | 4386 18.89% 76.37% | 4323 18.62% 94.99% | 1085 4.67% 99.66% | 76 0.33% 99.99% | 2 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache.miss_mach_latency_hist::total 23221 system.ruby.L1Cache.miss_latency_hist.issue_to_initial_request::bucket_size 512 system.ruby.L1Cache.miss_latency_hist.issue_to_initial_request::max_bucket 5119 -system.ruby.L1Cache.miss_latency_hist.issue_to_initial_request::samples 21736 -system.ruby.L1Cache.miss_latency_hist.issue_to_initial_request::mean 776.334008 -system.ruby.L1Cache.miss_latency_hist.issue_to_initial_request::gmean 326.213645 -system.ruby.L1Cache.miss_latency_hist.issue_to_initial_request::stdev 670.419505 -system.ruby.L1Cache.miss_latency_hist.issue_to_initial_request | 9839 45.27% 45.27% | 3725 17.14% 62.40% | 4328 19.91% 82.32% | 3280 15.09% 97.41% | 536 2.47% 99.87% | 26 0.12% 99.99% | 2 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache.miss_latency_hist.issue_to_initial_request::total 21736 +system.ruby.L1Cache.miss_latency_hist.issue_to_initial_request::samples 22145 +system.ruby.L1Cache.miss_latency_hist.issue_to_initial_request::mean 776.302009 +system.ruby.L1Cache.miss_latency_hist.issue_to_initial_request::gmean 328.435965 +system.ruby.L1Cache.miss_latency_hist.issue_to_initial_request::stdev 665.090173 +system.ruby.L1Cache.miss_latency_hist.issue_to_initial_request | 10009 45.20% 45.20% | 3705 16.73% 61.93% | 4615 20.84% 82.77% | 3282 14.82% 97.59% | 507 2.29% 99.88% | 27 0.12% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache.miss_latency_hist.issue_to_initial_request::total 22145 system.ruby.L1Cache.miss_latency_hist.initial_to_forward::bucket_size 128 system.ruby.L1Cache.miss_latency_hist.initial_to_forward::max_bucket 1279 -system.ruby.L1Cache.miss_latency_hist.initial_to_forward::samples 21736 -system.ruby.L1Cache.miss_latency_hist.initial_to_forward::mean 50.119295 -system.ruby.L1Cache.miss_latency_hist.initial_to_forward::gmean 21.370001 -system.ruby.L1Cache.miss_latency_hist.initial_to_forward::stdev 76.768610 -system.ruby.L1Cache.miss_latency_hist.initial_to_forward | 18902 86.96% 86.96% | 2171 9.99% 96.95% | 544 2.50% 99.45% | 73 0.34% 99.79% | 36 0.17% 99.95% | 9 0.04% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache.miss_latency_hist.initial_to_forward::total 21736 +system.ruby.L1Cache.miss_latency_hist.initial_to_forward::samples 22145 +system.ruby.L1Cache.miss_latency_hist.initial_to_forward::mean 49.022940 +system.ruby.L1Cache.miss_latency_hist.initial_to_forward::gmean 20.850081 +system.ruby.L1Cache.miss_latency_hist.initial_to_forward::stdev 75.532500 +system.ruby.L1Cache.miss_latency_hist.initial_to_forward | 19287 87.09% 87.09% | 2230 10.07% 97.16% | 500 2.26% 99.42% | 82 0.37% 99.79% | 36 0.16% 99.95% | 10 0.05% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache.miss_latency_hist.initial_to_forward::total 22145 system.ruby.L1Cache.miss_latency_hist.forward_to_first_response::bucket_size 32 system.ruby.L1Cache.miss_latency_hist.forward_to_first_response::max_bucket 319 -system.ruby.L1Cache.miss_latency_hist.forward_to_first_response::samples 21736 -system.ruby.L1Cache.miss_latency_hist.forward_to_first_response::mean 82.657481 -system.ruby.L1Cache.miss_latency_hist.forward_to_first_response::gmean 68.643430 -system.ruby.L1Cache.miss_latency_hist.forward_to_first_response::stdev 48.070946 -system.ruby.L1Cache.miss_latency_hist.forward_to_first_response | 3869 17.80% 17.80% | 5031 23.15% 40.95% | 5327 24.51% 65.45% | 3337 15.35% 80.81% | 2295 10.56% 91.36% | 1371 6.31% 97.67% | 466 2.14% 99.82% | 38 0.17% 99.99% | 1 0.00% 100.00% | 1 0.00% 100.00% -system.ruby.L1Cache.miss_latency_hist.forward_to_first_response::total 21736 +system.ruby.L1Cache.miss_latency_hist.forward_to_first_response::samples 22145 +system.ruby.L1Cache.miss_latency_hist.forward_to_first_response::mean 86.190969 +system.ruby.L1Cache.miss_latency_hist.forward_to_first_response::gmean 71.331937 +system.ruby.L1Cache.miss_latency_hist.forward_to_first_response::stdev 49.787970 +system.ruby.L1Cache.miss_latency_hist.forward_to_first_response | 3827 17.28% 17.28% | 4742 21.41% 38.69% | 5321 24.03% 62.72% | 3379 15.26% 77.98% | 2575 11.63% 89.61% | 1714 7.74% 97.35% | 533 2.41% 99.76% | 54 0.24% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache.miss_latency_hist.forward_to_first_response::total 22145 system.ruby.L1Cache.miss_latency_hist.first_response_to_completion::bucket_size 32 system.ruby.L1Cache.miss_latency_hist.first_response_to_completion::max_bucket 319 -system.ruby.L1Cache.miss_latency_hist.first_response_to_completion::samples 21736 -system.ruby.L1Cache.miss_latency_hist.first_response_to_completion::mean 8.922203 -system.ruby.L1Cache.miss_latency_hist.first_response_to_completion::stdev 20.770663 -system.ruby.L1Cache.miss_latency_hist.first_response_to_completion | 19926 91.67% 91.67% | 870 4.00% 95.68% | 588 2.71% 98.38% | 282 1.30% 99.68% | 62 0.29% 99.96% | 6 0.03% 99.99% | 2 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache.miss_latency_hist.first_response_to_completion::total 21736 +system.ruby.L1Cache.miss_latency_hist.first_response_to_completion::samples 22145 +system.ruby.L1Cache.miss_latency_hist.first_response_to_completion::mean 10.022533 +system.ruby.L1Cache.miss_latency_hist.first_response_to_completion::stdev 22.682118 +system.ruby.L1Cache.miss_latency_hist.first_response_to_completion | 19996 90.30% 90.30% | 982 4.43% 94.73% | 714 3.22% 97.95% | 355 1.60% 99.56% | 88 0.40% 99.95% | 8 0.04% 99.99% | 2 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache.miss_latency_hist.first_response_to_completion::total 22145 system.ruby.L2Cache.hit_mach_latency_hist::bucket_size 128 system.ruby.L2Cache.hit_mach_latency_hist::max_bucket 1279 -system.ruby.L2Cache.hit_mach_latency_hist::samples 551 -system.ruby.L2Cache.hit_mach_latency_hist::mean 138.152450 -system.ruby.L2Cache.hit_mach_latency_hist::gmean 74.393307 -system.ruby.L2Cache.hit_mach_latency_hist::stdev 158.485922 -system.ruby.L2Cache.hit_mach_latency_hist | 338 61.34% 61.34% | 126 22.87% 84.21% | 48 8.71% 92.92% | 22 3.99% 96.91% | 8 1.45% 98.37% | 3 0.54% 98.91% | 3 0.54% 99.46% | 0 0.00% 99.46% | 2 0.36% 99.82% | 1 0.18% 100.00% -system.ruby.L2Cache.hit_mach_latency_hist::total 551 +system.ruby.L2Cache.hit_mach_latency_hist::samples 543 +system.ruby.L2Cache.hit_mach_latency_hist::mean 123.099448 +system.ruby.L2Cache.hit_mach_latency_hist::gmean 68.390868 +system.ruby.L2Cache.hit_mach_latency_hist::stdev 131.478301 +system.ruby.L2Cache.hit_mach_latency_hist | 340 62.62% 62.62% | 131 24.13% 86.74% | 50 9.21% 95.95% | 10 1.84% 97.79% | 5 0.92% 98.71% | 4 0.74% 99.45% | 3 0.55% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L2Cache.hit_mach_latency_hist::total 543 system.ruby.Directory.miss_mach_latency_hist::bucket_size 512 system.ruby.Directory.miss_mach_latency_hist::max_bucket 5119 -system.ruby.Directory.miss_mach_latency_hist::samples 604582 -system.ruby.Directory.miss_mach_latency_hist::mean 973.379207 -system.ruby.Directory.miss_mach_latency_hist::gmean 697.899337 -system.ruby.Directory.miss_mach_latency_hist::stdev 678.922764 -system.ruby.Directory.miss_mach_latency_hist | 224249 37.09% 37.09% | 111976 18.52% 55.61% | 110298 18.24% 73.86% | 117791 19.48% 93.34% | 37131 6.14% 99.48% | 3028 0.50% 99.98% | 105 0.02% 100.00% | 4 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Directory.miss_mach_latency_hist::total 604582 +system.ruby.Directory.miss_mach_latency_hist::samples 604893 +system.ruby.Directory.miss_mach_latency_hist::mean 962.775514 +system.ruby.Directory.miss_mach_latency_hist::gmean 690.475594 +system.ruby.Directory.miss_mach_latency_hist::stdev 670.448849 +system.ruby.Directory.miss_mach_latency_hist | 225513 37.28% 37.28% | 111928 18.50% 55.79% | 113443 18.75% 74.54% | 118009 19.51% 94.05% | 33551 5.55% 99.60% | 2392 0.40% 99.99% | 57 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_mach_latency_hist::total 604893 system.ruby.Directory.miss_latency_hist.issue_to_initial_request::bucket_size 512 system.ruby.Directory.miss_latency_hist.issue_to_initial_request::max_bucket 5119 -system.ruby.Directory.miss_latency_hist.issue_to_initial_request::samples 448963 -system.ruby.Directory.miss_latency_hist.issue_to_initial_request::mean 790.361304 -system.ruby.Directory.miss_latency_hist.issue_to_initial_request::gmean 343.581530 -system.ruby.Directory.miss_latency_hist.issue_to_initial_request::stdev 668.650065 -system.ruby.Directory.miss_latency_hist.issue_to_initial_request | 200571 44.67% 44.67% | 75584 16.84% 61.51% | 92688 20.64% 82.15% | 67953 15.14% 97.29% | 11576 2.58% 99.87% | 574 0.13% 100.00% | 17 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Directory.miss_latency_hist.issue_to_initial_request::total 448963 +system.ruby.Directory.miss_latency_hist.issue_to_initial_request::samples 430767 +system.ruby.Directory.miss_latency_hist.issue_to_initial_request::mean 785.966174 +system.ruby.Directory.miss_latency_hist.issue_to_initial_request::gmean 348.017396 +system.ruby.Directory.miss_latency_hist.issue_to_initial_request::stdev 659.442663 +system.ruby.Directory.miss_latency_hist.issue_to_initial_request | 192325 44.65% 44.65% | 73086 16.97% 61.61% | 91651 21.28% 82.89% | 63254 14.68% 97.57% | 10020 2.33% 99.90% | 427 0.10% 100.00% | 4 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 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-system.ruby.Directory.miss_latency_hist.forward_to_first_response::stdev 32.952264 -system.ruby.Directory.miss_latency_hist.forward_to_first_response | 109386 24.36% 24.36% | 156482 34.85% 59.22% | 113962 25.38% 84.60% | 48318 10.76% 95.36% | 17372 3.87% 99.23% | 3270 0.73% 99.96% | 172 0.04% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Directory.miss_latency_hist.forward_to_first_response::total 448963 +system.ruby.Directory.miss_latency_hist.forward_to_first_response::samples 430767 +system.ruby.Directory.miss_latency_hist.forward_to_first_response::mean 61.207381 +system.ruby.Directory.miss_latency_hist.forward_to_first_response::gmean 52.822325 +system.ruby.Directory.miss_latency_hist.forward_to_first_response::stdev 33.575954 +system.ruby.Directory.miss_latency_hist.forward_to_first_response | 108043 25.08% 25.08% | 144975 33.66% 58.74% | 108992 25.30% 84.04% | 47420 11.01% 95.05% | 17597 4.09% 99.13% | 3561 0.83% 99.96% | 178 0.04% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_latency_hist.forward_to_first_response::total 430767 system.ruby.Directory.miss_latency_hist.first_response_to_completion::bucket_size 128 system.ruby.Directory.miss_latency_hist.first_response_to_completion::max_bucket 1279 -system.ruby.Directory.miss_latency_hist.first_response_to_completion::samples 448963 -system.ruby.Directory.miss_latency_hist.first_response_to_completion::mean 141.425737 -system.ruby.Directory.miss_latency_hist.first_response_to_completion::stdev 105.102148 -system.ruby.Directory.miss_latency_hist.first_response_to_completion | 237351 52.87% 52.87% | 156354 34.83% 87.69% | 40339 8.98% 96.68% | 9952 2.22% 98.89% | 4722 1.05% 99.95% | 244 0.05% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Directory.miss_latency_hist.first_response_to_completion::total 448963 +system.ruby.Directory.miss_latency_hist.first_response_to_completion::samples 430767 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100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.L1Cache.hit_type_mach_latency_hist::total 78 +system.ruby.LD.L1Cache.hit_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 100 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.L1Cache.hit_type_mach_latency_hist::total 100 system.ruby.LD.L1Cache.miss_type_mach_latency_hist::bucket_size 512 system.ruby.LD.L1Cache.miss_type_mach_latency_hist::max_bucket 5119 -system.ruby.LD.L1Cache.miss_type_mach_latency_hist::samples 13125 -system.ruby.LD.L1Cache.miss_type_mach_latency_hist::mean 912.161600 -system.ruby.LD.L1Cache.miss_type_mach_latency_hist::gmean 618.732413 -system.ruby.LD.L1Cache.miss_type_mach_latency_hist::stdev 673.071954 -system.ruby.LD.L1Cache.miss_type_mach_latency_hist | 5337 40.66% 40.66% | 2281 17.38% 58.04% | 2397 18.26% 76.30% | 2468 18.80% 95.11% | 597 4.55% 99.66% | 45 0.34% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.L1Cache.miss_type_mach_latency_hist::total 13125 +system.ruby.LD.L1Cache.miss_type_mach_latency_hist::samples 13143 +system.ruby.LD.L1Cache.miss_type_mach_latency_hist::mean 916.963250 +system.ruby.LD.L1Cache.miss_type_mach_latency_hist::gmean 626.263580 +system.ruby.LD.L1Cache.miss_type_mach_latency_hist::stdev 671.582246 +system.ruby.LD.L1Cache.miss_type_mach_latency_hist | 5258 40.01% 40.01% | 2297 17.48% 57.48% | 2504 19.05% 76.54% | 2412 18.35% 94.89% | 623 4.74% 99.63% | 49 0.37% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.L1Cache.miss_type_mach_latency_hist::total 13143 system.ruby.LD.L2Cache.hit_type_mach_latency_hist::bucket_size 128 system.ruby.LD.L2Cache.hit_type_mach_latency_hist::max_bucket 1279 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist::samples 352 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+system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 690.656874 +system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 671.046581 +system.ruby.LD.Directory.miss_type_mach_latency_hist | 145651 37.27% 37.27% | 72310 18.50% 55.77% | 73205 18.73% 74.50% | 76232 19.51% 94.01% | 21851 5.59% 99.60% | 1527 0.39% 99.99% | 44 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.Directory.miss_type_mach_latency_hist::total 390820 system.ruby.ST.L1Cache.hit_type_mach_latency_hist::bucket_size 1 system.ruby.ST.L1Cache.hit_type_mach_latency_hist::max_bucket 9 system.ruby.ST.L1Cache.hit_type_mach_latency_hist::samples 45 @@ -1135,377 +1139,367 @@ system.ruby.ST.L1Cache.hit_type_mach_latency_hist | 0 0.00% system.ruby.ST.L1Cache.hit_type_mach_latency_hist::total 45 system.ruby.ST.L1Cache.miss_type_mach_latency_hist::bucket_size 512 system.ruby.ST.L1Cache.miss_type_mach_latency_hist::max_bucket 5119 -system.ruby.ST.L1Cache.miss_type_mach_latency_hist::samples 9602 -system.ruby.ST.L1Cache.miss_type_mach_latency_hist::mean 925.795980 -system.ruby.ST.L1Cache.miss_type_mach_latency_hist::gmean 638.900214 -system.ruby.ST.L1Cache.miss_type_mach_latency_hist::stdev 676.891520 -system.ruby.ST.L1Cache.miss_type_mach_latency_hist | 3808 39.66% 39.66% | 1762 18.35% 58.01% | 1706 17.77% 75.78% | 1771 18.44% 94.22% | 516 5.37% 99.59% | 37 0.39% 99.98% | 1 0.01% 99.99% | 1 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.L1Cache.miss_type_mach_latency_hist::total 9602 +system.ruby.ST.L1Cache.miss_type_mach_latency_hist::samples 10078 +system.ruby.ST.L1Cache.miss_type_mach_latency_hist::mean 920.519051 +system.ruby.ST.L1Cache.miss_type_mach_latency_hist::gmean 640.884134 +system.ruby.ST.L1Cache.miss_type_mach_latency_hist::stdev 665.879942 +system.ruby.ST.L1Cache.miss_type_mach_latency_hist | 4046 40.15% 40.15% | 1748 17.34% 57.49% | 1882 18.67% 76.17% | 1911 18.96% 95.13% | 462 4.58% 99.71% | 27 0.27% 99.98% | 2 0.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.L1Cache.miss_type_mach_latency_hist::total 10078 system.ruby.ST.L2Cache.hit_type_mach_latency_hist::bucket_size 128 system.ruby.ST.L2Cache.hit_type_mach_latency_hist::max_bucket 1279 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist::samples 199 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist::mean 149.266332 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist::gmean 79.468000 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist::stdev 179.166771 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist | 115 57.79% 57.79% | 49 24.62% 82.41% | 20 10.05% 92.46% | 7 3.52% 95.98% | 3 1.51% 97.49% | 1 0.50% 97.99% | 2 1.01% 98.99% | 0 0.00% 98.99% | 1 0.50% 99.50% | 1 0.50% 100.00% -system.ruby.ST.L2Cache.hit_type_mach_latency_hist::total 199 +system.ruby.ST.L2Cache.hit_type_mach_latency_hist::samples 180 +system.ruby.ST.L2Cache.hit_type_mach_latency_hist::mean 113.166667 +system.ruby.ST.L2Cache.hit_type_mach_latency_hist::gmean 63.121979 +system.ruby.ST.L2Cache.hit_type_mach_latency_hist::stdev 113.552562 +system.ruby.ST.L2Cache.hit_type_mach_latency_hist | 117 65.00% 65.00% | 42 23.33% 88.33% | 18 10.00% 98.33% | 2 1.11% 99.44% | 0 0.00% 99.44% | 1 0.56% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.L2Cache.hit_type_mach_latency_hist::total 180 system.ruby.ST.Directory.miss_type_mach_latency_hist::bucket_size 512 system.ruby.ST.Directory.miss_type_mach_latency_hist::max_bucket 5119 -system.ruby.ST.Directory.miss_type_mach_latency_hist::samples 213672 -system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 973.707561 -system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 698.916238 -system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 677.713425 -system.ruby.ST.Directory.miss_type_mach_latency_hist | 79247 37.09% 37.09% | 39424 18.45% 55.54% | 39089 18.29% 73.83% | 41831 19.58% 93.41% | 13032 6.10% 99.51% | 1011 0.47% 99.98% | 37 0.02% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.Directory.miss_type_mach_latency_hist::total 213672 -system.ruby.L1Cache_Controller.Load | 50661 12.52% 12.52% | 50602 12.50% 25.02% | 50623 12.51% 37.52% | 50689 12.52% 50.05% | 50291 12.42% 62.47% | 50786 12.55% 75.02% | 50489 12.47% 87.49% | 50629 12.51% 100.00% -system.ruby.L1Cache_Controller.Load::total 404770 -system.ruby.L1Cache_Controller.Store | 28155 12.59% 12.59% | 27873 12.46% 25.05% | 27954 12.50% 37.55% | 27997 12.52% 50.06% | 28127 12.57% 62.64% | 27687 12.38% 75.01% | 28186 12.60% 87.61% | 27704 12.39% 100.00% -system.ruby.L1Cache_Controller.Store::total 223683 -system.ruby.L1Cache_Controller.L2_Replacement | 78645 12.54% 12.54% | 78315 12.49% 25.02% | 78435 12.50% 37.53% | 78525 12.52% 50.05% | 78254 12.48% 62.52% | 78318 12.49% 75.01% | 78531 12.52% 87.53% | 78210 12.47% 100.00% -system.ruby.L1Cache_Controller.L2_Replacement::total 627233 -system.ruby.L1Cache_Controller.L1_to_L2 | 963838 12.49% 12.49% | 963397 12.49% 24.98% | 965289 12.51% 37.49% | 966306 12.52% 50.01% | 963961 12.49% 62.50% | 964279 12.50% 75.00% | 965132 12.51% 87.51% | 963900 12.49% 100.00% -system.ruby.L1Cache_Controller.L1_to_L2::total 7716102 -system.ruby.L1Cache_Controller.Trigger_L2_to_L1D | 83 14.64% 14.64% | 80 14.11% 28.75% | 59 10.41% 39.15% | 75 13.23% 52.38% | 78 13.76% 66.14% | 65 11.46% 77.60% | 69 12.17% 89.77% | 58 10.23% 100.00% -system.ruby.L1Cache_Controller.Trigger_L2_to_L1D::total 567 -system.ruby.L1Cache_Controller.Complete_L2_to_L1 | 83 14.64% 14.64% | 80 14.11% 28.75% | 59 10.41% 39.15% | 75 13.23% 52.38% | 78 13.76% 66.14% | 65 11.46% 77.60% | 69 12.17% 89.77% | 58 10.23% 100.00% -system.ruby.L1Cache_Controller.Complete_L2_to_L1::total 567 -system.ruby.L1Cache_Controller.Other_GETX | 195183 12.49% 12.49% | 195457 12.51% 24.99% | 195358 12.50% 37.49% | 195331 12.50% 49.99% | 195205 12.49% 62.48% | 195645 12.52% 75.00% | 195130 12.48% 87.48% | 195609 12.52% 100.00% -system.ruby.L1Cache_Controller.Other_GETX::total 1562918 -system.ruby.L1Cache_Controller.Other_GETS | 352616 12.50% 12.50% | 352654 12.50% 25.00% | 352636 12.50% 37.50% | 352589 12.50% 49.99% | 352951 12.51% 62.50% | 352462 12.49% 75.00% | 352778 12.50% 87.50% | 352615 12.50% 100.00% -system.ruby.L1Cache_Controller.Other_GETS::total 2821301 -system.ruby.L1Cache_Controller.Merged_GETS | 126 12.73% 12.73% | 117 11.82% 24.55% | 123 12.42% 36.97% | 103 10.40% 47.37% | 145 14.65% 62.02% | 113 11.41% 73.43% | 143 14.44% 87.88% | 120 12.12% 100.00% -system.ruby.L1Cache_Controller.Merged_GETS::total 990 -system.ruby.L1Cache_Controller.Ack | 547200 12.54% 12.54% | 545018 12.49% 25.02% | 545878 12.51% 37.53% | 546264 12.52% 50.05% | 544679 12.48% 62.53% | 544911 12.48% 75.01% | 546354 12.52% 87.53% | 544225 12.47% 100.00% -system.ruby.L1Cache_Controller.Ack::total 4364529 -system.ruby.L1Cache_Controller.Shared_Ack | 31 8.27% 8.27% | 41 10.93% 19.20% | 41 10.93% 30.13% | 54 14.40% 44.53% | 46 12.27% 56.80% | 49 13.07% 69.87% | 57 15.20% 85.07% | 56 14.93% 100.00% -system.ruby.L1Cache_Controller.Shared_Ack::total 375 -system.ruby.L1Cache_Controller.Data | 3440 12.43% 12.43% | 3377 12.20% 24.63% | 3352 12.11% 36.74% | 3580 12.93% 49.67% | 3475 12.55% 62.22% | 3501 12.65% 74.87% | 3448 12.46% 87.33% | 3508 12.67% 100.00% -system.ruby.L1Cache_Controller.Data::total 27681 -system.ruby.L1Cache_Controller.Shared_Data | 1192 12.40% 12.40% | 1173 12.20% 24.60% | 1206 12.55% 37.15% | 1220 12.69% 49.84% | 1176 12.23% 62.07% | 1276 13.27% 75.35% | 1184 12.32% 87.66% | 1186 12.34% 100.00% -system.ruby.L1Cache_Controller.Shared_Data::total 9613 -system.ruby.L1Cache_Controller.Exclusive_Data | 74022 12.55% 12.55% | 73774 12.50% 25.05% | 73884 12.52% 37.57% | 73734 12.50% 50.07% | 73616 12.48% 62.55% | 73550 12.47% 75.01% | 73907 12.53% 87.54% | 73526 12.46% 100.00% -system.ruby.L1Cache_Controller.Exclusive_Data::total 590013 -system.ruby.L1Cache_Controller.Writeback_Ack | 74259 12.55% 12.55% | 73878 12.49% 25.04% | 73986 12.51% 37.55% | 74056 12.52% 50.07% | 73807 12.48% 62.55% | 73737 12.47% 75.02% | 74060 12.52% 87.54% | 73709 12.46% 100.00% -system.ruby.L1Cache_Controller.Writeback_Ack::total 591492 -system.ruby.L1Cache_Controller.Writeback_Nack | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.Writeback_Nack::total 1 -system.ruby.L1Cache_Controller.All_acks | 1220 12.28% 12.28% | 1207 12.15% 24.43% | 1244 12.52% 36.95% | 1265 12.73% 49.68% | 1214 12.22% 61.90% | 1317 13.26% 75.16% | 1235 12.43% 87.59% | 1233 12.41% 100.00% -system.ruby.L1Cache_Controller.All_acks::total 9935 -system.ruby.L1Cache_Controller.All_acks_no_sharers | 77435 12.54% 12.54% | 77117 12.49% 25.03% | 77198 12.50% 37.54% | 77268 12.52% 50.05% | 77053 12.48% 62.53% | 77010 12.47% 75.01% | 77303 12.52% 87.53% | 76986 12.47% 100.00% -system.ruby.L1Cache_Controller.All_acks_no_sharers::total 617370 -system.ruby.L1Cache_Controller.I.Load | 50567 12.51% 12.51% | 50509 12.50% 25.02% | 50529 12.51% 37.52% | 50592 12.52% 50.04% | 50200 12.42% 62.47% | 50701 12.55% 75.01% | 50397 12.47% 87.49% | 50557 12.51% 100.00% -system.ruby.L1Cache_Controller.I.Load::total 404052 -system.ruby.L1Cache_Controller.I.Store | 28088 12.58% 12.58% | 27817 12.46% 25.04% | 27916 12.50% 37.54% | 27943 12.52% 50.06% | 28064 12.57% 62.63% | 27628 12.37% 75.00% | 28144 12.61% 87.61% | 27663 12.39% 100.00% -system.ruby.L1Cache_Controller.I.Store::total 223263 -system.ruby.L1Cache_Controller.I.L2_Replacement | 1147 12.07% 12.07% | 1210 12.73% 24.81% | 1229 12.93% 37.74% | 1174 12.36% 50.09% | 1173 12.34% 62.44% | 1171 12.32% 74.76% | 1198 12.61% 87.37% | 1200 12.63% 100.00% -system.ruby.L1Cache_Controller.I.L2_Replacement::total 9502 -system.ruby.L1Cache_Controller.I.L1_to_L2 | 95 11.85% 11.85% | 109 13.59% 25.44% | 82 10.22% 35.66% | 115 14.34% 50.00% | 96 11.97% 61.97% | 100 12.47% 74.44% | 106 13.22% 87.66% | 99 12.34% 100.00% -system.ruby.L1Cache_Controller.I.L1_to_L2::total 802 -system.ruby.L1Cache_Controller.I.Trigger_L2_to_L1D | 2 20.00% 20.00% | 1 10.00% 30.00% | 0 0.00% 30.00% | 1 10.00% 40.00% | 3 30.00% 70.00% | 1 10.00% 80.00% | 1 10.00% 90.00% | 1 10.00% 100.00% +system.ruby.ST.Directory.miss_type_mach_latency_hist::samples 214073 +system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 961.619326 +system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 690.144763 +system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 669.356252 +system.ruby.ST.Directory.miss_type_mach_latency_hist | 79862 37.31% 37.31% | 39618 18.51% 55.81% | 40238 18.80% 74.61% | 41777 19.52% 94.12% | 11700 5.47% 99.59% | 865 0.40% 99.99% | 13 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.Directory.miss_type_mach_latency_hist::total 214073 +system.ruby.Directory_Controller.GETX 228066 0.00% 0.00% +system.ruby.Directory_Controller.GETS 409919 0.00% 0.00% +system.ruby.Directory_Controller.PUT 606117 0.00% 0.00% +system.ruby.Directory_Controller.Unblock 1478 0.00% 0.00% +system.ruby.Directory_Controller.UnblockS 26200 0.00% 0.00% +system.ruby.Directory_Controller.UnblockM 601910 0.00% 0.00% +system.ruby.Directory_Controller.Writeback_Clean 7982 0.00% 0.00% +system.ruby.Directory_Controller.Writeback_Dirty 1462 0.00% 0.00% +system.ruby.Directory_Controller.Writeback_Exclusive_Clean 361520 0.00% 0.00% +system.ruby.Directory_Controller.Writeback_Exclusive_Dirty 220077 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Data 607668 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Ack 221538 0.00% 0.00% +system.ruby.Directory_Controller.All_Unblocks 1073 0.00% 0.00% +system.ruby.Directory_Controller.NX.GETX 64 0.00% 0.00% +system.ruby.Directory_Controller.NX.GETS 111 0.00% 0.00% +system.ruby.Directory_Controller.NX.PUT 10889 0.00% 0.00% +system.ruby.Directory_Controller.NO.GETX 7240 0.00% 0.00% +system.ruby.Directory_Controller.NO.GETS 11956 0.00% 0.00% +system.ruby.Directory_Controller.NO.PUT 581636 0.00% 0.00% +system.ruby.Directory_Controller.O.GETX 9346 0.00% 0.00% +system.ruby.Directory_Controller.O.GETS 16569 0.00% 0.00% +system.ruby.Directory_Controller.E.GETX 207506 0.00% 0.00% +system.ruby.Directory_Controller.E.GETS 374265 0.00% 0.00% +system.ruby.Directory_Controller.NO_B.GETX 569 0.00% 0.00% +system.ruby.Directory_Controller.NO_B.GETS 1073 0.00% 0.00% +system.ruby.Directory_Controller.NO_B.PUT 13366 0.00% 0.00% +system.ruby.Directory_Controller.NO_B.UnblockS 8495 0.00% 0.00% +system.ruby.Directory_Controller.NO_B.UnblockM 600329 0.00% 0.00% +system.ruby.Directory_Controller.NO_B_X.GETX 2 0.00% 0.00% +system.ruby.Directory_Controller.NO_B_X.PUT 10 0.00% 0.00% +system.ruby.Directory_Controller.NO_B_X.UnblockS 19 0.00% 0.00% +system.ruby.Directory_Controller.NO_B_X.UnblockM 550 0.00% 0.00% +system.ruby.Directory_Controller.NO_B_S.GETS 3 0.00% 0.00% +system.ruby.Directory_Controller.NO_B_S.PUT 33 0.00% 0.00% +system.ruby.Directory_Controller.NO_B_S.UnblockS 42 0.00% 0.00% +system.ruby.Directory_Controller.NO_B_S.UnblockM 1031 0.00% 0.00% +system.ruby.Directory_Controller.NO_B_S_W.GETX 3 0.00% 0.00% +system.ruby.Directory_Controller.NO_B_S_W.GETS 3 0.00% 0.00% +system.ruby.Directory_Controller.NO_B_S_W.PUT 121 0.00% 0.00% +system.ruby.Directory_Controller.NO_B_S_W.UnblockS 1076 0.00% 0.00% +system.ruby.Directory_Controller.NO_B_S_W.All_Unblocks 1073 0.00% 0.00% +system.ruby.Directory_Controller.O_B.GETX 13 0.00% 0.00% +system.ruby.Directory_Controller.O_B.GETS 15 0.00% 0.00% +system.ruby.Directory_Controller.O_B.UnblockS 16568 0.00% 0.00% +system.ruby.Directory_Controller.NO_B_W.GETX 1985 0.00% 0.00% +system.ruby.Directory_Controller.NO_B_W.GETS 3422 0.00% 0.00% +system.ruby.Directory_Controller.NO_B_W.Memory_Data 591100 0.00% 0.00% +system.ruby.Directory_Controller.O_B_W.GETX 48 0.00% 0.00% +system.ruby.Directory_Controller.O_B_W.GETS 118 0.00% 0.00% +system.ruby.Directory_Controller.O_B_W.Memory_Data 16568 0.00% 0.00% +system.ruby.Directory_Controller.WB.GETX 1246 0.00% 0.00% +system.ruby.Directory_Controller.WB.GETS 2323 0.00% 0.00% +system.ruby.Directory_Controller.WB.PUT 62 0.00% 0.00% +system.ruby.Directory_Controller.WB.Unblock 1478 0.00% 0.00% +system.ruby.Directory_Controller.WB.Writeback_Clean 7982 0.00% 0.00% +system.ruby.Directory_Controller.WB.Writeback_Dirty 1462 0.00% 0.00% +system.ruby.Directory_Controller.WB.Writeback_Exclusive_Clean 361520 0.00% 0.00% +system.ruby.Directory_Controller.WB.Writeback_Exclusive_Dirty 220077 0.00% 0.00% +system.ruby.Directory_Controller.WB_O_W.Memory_Ack 1462 0.00% 0.00% +system.ruby.Directory_Controller.WB_E_W.GETX 44 0.00% 0.00% +system.ruby.Directory_Controller.WB_E_W.GETS 61 0.00% 0.00% +system.ruby.Directory_Controller.WB_E_W.Memory_Ack 220076 0.00% 0.00% +system.ruby.L1Cache_Controller.Load | 50385 12.45% 12.45% | 50687 12.52% 24.97% | 50468 12.47% 37.44% | 50666 12.52% 49.96% | 50623 12.51% 62.47% | 50650 12.51% 74.98% | 50545 12.49% 87.47% | 50723 12.53% 100.00% +system.ruby.L1Cache_Controller.Load::total 404747 +system.ruby.L1Cache_Controller.Store | 28072 12.50% 12.50% | 28228 12.57% 25.07% | 28321 12.61% 37.69% | 27699 12.34% 50.02% | 28273 12.59% 62.61% | 28020 12.48% 75.09% | 28027 12.48% 87.57% | 27908 12.43% 100.00% +system.ruby.L1Cache_Controller.Store::total 224548 +system.ruby.L1Cache_Controller.L2_Replacement | 78299 12.47% 12.47% | 78765 12.54% 25.01% | 78648 12.52% 37.53% | 78211 12.45% 49.98% | 78724 12.53% 62.52% | 78526 12.50% 75.02% | 78393 12.48% 87.51% | 78471 12.49% 100.00% +system.ruby.L1Cache_Controller.L2_Replacement::total 628037 +system.ruby.L1Cache_Controller.L1_to_L2 | 979507 12.50% 12.50% | 981167 12.52% 25.01% | 980052 12.50% 37.51% | 977154 12.47% 49.98% | 982076 12.53% 62.51% | 980285 12.51% 75.01% | 977927 12.48% 87.49% | 980636 12.51% 100.00% +system.ruby.L1Cache_Controller.L1_to_L2::total 7838804 +system.ruby.L1Cache_Controller.Trigger_L2_to_L1D | 67 11.90% 11.90% | 65 11.55% 23.45% | 63 11.19% 34.64% | 70 12.43% 47.07% | 72 12.79% 59.86% | 62 11.01% 70.87% | 85 15.10% 85.97% | 79 14.03% 100.00% +system.ruby.L1Cache_Controller.Trigger_L2_to_L1D::total 563 +system.ruby.L1Cache_Controller.Complete_L2_to_L1 | 67 11.90% 11.90% | 65 11.55% 23.45% | 63 11.19% 34.64% | 70 12.43% 47.07% | 72 12.79% 59.86% | 62 11.01% 70.87% | 85 15.10% 85.97% | 79 14.03% 100.00% +system.ruby.L1Cache_Controller.Complete_L2_to_L1::total 563 +system.ruby.L1Cache_Controller.Other_GETX | 196134 12.50% 12.50% | 195975 12.49% 24.99% | 195874 12.48% 37.47% | 196504 12.52% 50.00% | 195940 12.49% 62.48% | 196190 12.50% 74.99% | 196188 12.50% 87.49% | 196280 12.51% 100.00% +system.ruby.L1Cache_Controller.Other_GETX::total 1569085 +system.ruby.L1Cache_Controller.Other_GETS | 352746 12.51% 12.51% | 352417 12.50% 25.00% | 352660 12.50% 37.51% | 352467 12.50% 50.01% | 352524 12.50% 62.50% | 352468 12.50% 75.00% | 352590 12.50% 87.50% | 352421 12.50% 100.00% +system.ruby.L1Cache_Controller.Other_GETS::total 2820293 +system.ruby.L1Cache_Controller.Merged_GETS | 136 12.67% 12.67% | 148 13.79% 26.47% | 126 11.74% 38.21% | 132 12.30% 50.51% | 123 11.46% 61.98% | 138 12.86% 74.84% | 131 12.21% 87.05% | 139 12.95% 100.00% +system.ruby.L1Cache_Controller.Merged_GETS::total 1073 +system.ruby.L1Cache_Controller.Ack | 544749 12.47% 12.47% | 548151 12.54% 25.01% | 547200 12.52% 37.53% | 544104 12.45% 49.99% | 547634 12.53% 62.52% | 546228 12.50% 75.02% | 545522 12.48% 87.50% | 545987 12.50% 100.00% +system.ruby.L1Cache_Controller.Ack::total 4369575 +system.ruby.L1Cache_Controller.Shared_Ack | 44 10.38% 10.38% | 64 15.09% 25.47% | 49 11.56% 37.03% | 55 12.97% 50.00% | 58 13.68% 63.68% | 62 14.62% 78.30% | 48 11.32% 89.62% | 44 10.38% 100.00% +system.ruby.L1Cache_Controller.Shared_Ack::total 424 +system.ruby.L1Cache_Controller.Data | 3431 12.51% 12.51% | 3478 12.68% 25.20% | 3487 12.72% 37.91% | 3316 12.09% 50.00% | 3463 12.63% 62.63% | 3469 12.65% 75.28% | 3357 12.24% 87.52% | 3421 12.48% 100.00% +system.ruby.L1Cache_Controller.Data::total 27422 +system.ruby.L1Cache_Controller.Shared_Data | 1205 12.51% 12.51% | 1184 12.29% 24.80% | 1195 12.41% 37.21% | 1186 12.31% 49.52% | 1199 12.45% 61.97% | 1238 12.85% 74.82% | 1198 12.44% 87.26% | 1227 12.74% 100.00% +system.ruby.L1Cache_Controller.Shared_Data::total 9632 +system.ruby.L1Cache_Controller.Exclusive_Data | 73671 12.46% 12.46% | 74114 12.54% 25.00% | 73974 12.52% 37.52% | 73718 12.47% 49.99% | 74071 12.53% 62.52% | 73826 12.49% 75.01% | 73849 12.49% 87.51% | 73835 12.49% 100.00% +system.ruby.L1Cache_Controller.Exclusive_Data::total 591058 +system.ruby.L1Cache_Controller.Writeback_Ack | 73966 12.48% 12.48% | 74272 12.53% 25.02% | 74193 12.52% 37.54% | 73799 12.46% 49.99% | 74240 12.53% 62.52% | 73997 12.49% 75.01% | 73995 12.49% 87.50% | 74059 12.50% 100.00% +system.ruby.L1Cache_Controller.Writeback_Ack::total 592521 +system.ruby.L1Cache_Controller.All_acks | 1242 12.43% 12.43% | 1233 12.34% 24.77% | 1238 12.39% 37.16% | 1235 12.36% 49.52% | 1246 12.47% 61.99% | 1291 12.92% 74.91% | 1239 12.40% 87.31% | 1268 12.69% 100.00% +system.ruby.L1Cache_Controller.All_acks::total 9992 +system.ruby.L1Cache_Controller.All_acks_no_sharers | 77066 12.47% 12.47% | 77544 12.55% 25.01% | 77418 12.52% 37.54% | 76985 12.45% 49.99% | 77487 12.54% 62.53% | 77242 12.50% 75.02% | 77165 12.48% 87.51% | 77215 12.49% 100.00% +system.ruby.L1Cache_Controller.All_acks_no_sharers::total 618122 +system.ruby.L1Cache_Controller.I.Load | 50288 12.45% 12.45% | 50598 12.53% 24.97% | 50377 12.47% 37.44% | 50572 12.52% 49.96% | 50518 12.51% 62.47% | 50570 12.52% 74.99% | 50439 12.49% 87.47% | 50607 12.53% 100.00% +system.ruby.L1Cache_Controller.I.Load::total 403969 +system.ruby.L1Cache_Controller.I.Store | 28021 12.50% 12.50% | 28176 12.57% 25.07% | 28281 12.62% 37.69% | 27649 12.34% 50.02% | 28214 12.59% 62.61% | 27965 12.48% 75.09% | 27964 12.48% 87.56% | 27875 12.44% 100.00% +system.ruby.L1Cache_Controller.I.Store::total 224145 +system.ruby.L1Cache_Controller.I.L2_Replacement | 1108 11.60% 11.60% | 1263 13.22% 24.81% | 1214 12.71% 37.52% | 1261 13.20% 50.72% | 1167 12.21% 62.93% | 1204 12.60% 75.53% | 1194 12.50% 88.03% | 1144 11.97% 100.00% +system.ruby.L1Cache_Controller.I.L2_Replacement::total 9555 +system.ruby.L1Cache_Controller.I.L1_to_L2 | 85 10.98% 10.98% | 100 12.92% 23.90% | 96 12.40% 36.30% | 96 12.40% 48.71% | 85 10.98% 59.69% | 104 13.44% 73.13% | 117 15.12% 88.24% | 91 11.76% 100.00% +system.ruby.L1Cache_Controller.I.L1_to_L2::total 774 +system.ruby.L1Cache_Controller.I.Trigger_L2_to_L1D | 1 10.00% 10.00% | 1 10.00% 20.00% | 1 10.00% 30.00% | 0 0.00% 30.00% | 2 20.00% 50.00% | 1 10.00% 60.00% | 1 10.00% 70.00% | 3 30.00% 100.00% system.ruby.L1Cache_Controller.I.Trigger_L2_to_L1D::total 10 -system.ruby.L1Cache_Controller.I.Other_GETX | 194128 12.49% 12.49% | 194346 12.51% 25.00% | 194236 12.50% 37.49% | 194228 12.50% 49.99% | 194087 12.49% 62.48% | 194552 12.52% 75.00% | 194037 12.49% 87.48% | 194519 12.52% 100.00% -system.ruby.L1Cache_Controller.I.Other_GETX::total 1554133 -system.ruby.L1Cache_Controller.I.Other_GETS | 350781 12.50% 12.50% | 350787 12.50% 25.00% | 350767 12.50% 37.50% | 350672 12.50% 49.99% | 351174 12.51% 62.51% | 350517 12.49% 75.00% | 350891 12.50% 87.50% | 350707 12.50% 100.00% -system.ruby.L1Cache_Controller.I.Other_GETS::total 2806296 -system.ruby.L1Cache_Controller.S.Load | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 50.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.S.Load::total 2 -system.ruby.L1Cache_Controller.S.Store | 1 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.I.Other_GETX | 195054 12.50% 12.50% | 194813 12.49% 24.99% | 194750 12.48% 37.47% | 195324 12.52% 49.99% | 194790 12.49% 62.48% | 195048 12.50% 74.98% | 195089 12.51% 87.49% | 195205 12.51% 100.00% +system.ruby.L1Cache_Controller.I.Other_GETX::total 1560073 +system.ruby.L1Cache_Controller.I.Other_GETS | 350845 12.51% 12.51% | 350506 12.49% 25.00% | 350840 12.51% 37.51% | 350591 12.50% 50.01% | 350672 12.50% 62.51% | 350617 12.50% 75.00% | 350657 12.50% 87.50% | 350525 12.50% 100.00% +system.ruby.L1Cache_Controller.I.Other_GETS::total 2805253 +system.ruby.L1Cache_Controller.S.Load | 2 22.22% 22.22% | 0 0.00% 22.22% | 0 0.00% 22.22% | 0 0.00% 22.22% | 0 0.00% 22.22% | 1 11.11% 33.33% | 4 44.44% 77.78% | 2 22.22% 100.00% +system.ruby.L1Cache_Controller.S.Load::total 9 +system.ruby.L1Cache_Controller.S.Store | 1 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% system.ruby.L1Cache_Controller.S.Store::total 2 -system.ruby.L1Cache_Controller.S.L2_Replacement | 3235 12.34% 12.34% | 3224 12.30% 24.64% | 3217 12.27% 36.91% | 3292 12.56% 49.47% | 3270 12.47% 61.94% | 3408 13.00% 74.94% | 3268 12.47% 87.41% | 3300 12.59% 100.00% -system.ruby.L1Cache_Controller.S.L2_Replacement::total 26214 -system.ruby.L1Cache_Controller.S.L1_to_L2 | 3265 12.34% 12.34% | 3252 12.29% 24.62% | 3252 12.29% 36.91% | 3319 12.54% 49.45% | 3309 12.50% 61.95% | 3438 12.99% 74.94% | 3301 12.47% 87.41% | 3331 12.59% 100.00% -system.ruby.L1Cache_Controller.S.L1_to_L2::total 26467 -system.ruby.L1Cache_Controller.S.Trigger_L2_to_L1D | 1 7.14% 7.14% | 2 14.29% 21.43% | 2 14.29% 35.71% | 2 14.29% 50.00% | 4 28.57% 78.57% | 0 0.00% 78.57% | 1 7.14% 85.71% | 2 14.29% 100.00% -system.ruby.L1Cache_Controller.S.Trigger_L2_to_L1D::total 14 -system.ruby.L1Cache_Controller.S.Other_GETX | 32 12.31% 12.31% | 29 11.15% 23.46% | 36 13.85% 37.31% | 28 10.77% 48.08% | 34 13.08% 61.15% | 31 11.92% 73.08% | 37 14.23% 87.31% | 33 12.69% 100.00% -system.ruby.L1Cache_Controller.S.Other_GETX::total 260 -system.ruby.L1Cache_Controller.S.Other_GETS | 44 11.73% 11.73% | 50 13.33% 25.07% | 52 13.87% 38.93% | 41 10.93% 49.87% | 43 11.47% 61.33% | 62 16.53% 77.87% | 37 9.87% 87.73% | 46 12.27% 100.00% -system.ruby.L1Cache_Controller.S.Other_GETS::total 375 -system.ruby.L1Cache_Controller.O.Load | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.O.Load::total 1 -system.ruby.L1Cache_Controller.O.L2_Replacement | 872 12.65% 12.65% | 877 12.72% 25.38% | 862 12.51% 37.88% | 862 12.51% 50.39% | 846 12.28% 62.67% | 873 12.67% 75.33% | 864 12.54% 87.87% | 836 12.13% 100.00% -system.ruby.L1Cache_Controller.O.L2_Replacement::total 6892 -system.ruby.L1Cache_Controller.O.L1_to_L2 | 63 10.47% 10.47% | 75 12.46% 22.92% | 90 14.95% 37.87% | 86 14.29% 52.16% | 79 13.12% 65.28% | 72 11.96% 77.24% | 72 11.96% 89.20% | 65 10.80% 100.00% -system.ruby.L1Cache_Controller.O.L1_to_L2::total 602 -system.ruby.L1Cache_Controller.O.Trigger_L2_to_L1D | 1 20.00% 20.00% | 0 0.00% 20.00% | 1 20.00% 40.00% | 0 0.00% 40.00% | 2 40.00% 80.00% | 0 0.00% 80.00% | 0 0.00% 80.00% | 1 20.00% 100.00% -system.ruby.L1Cache_Controller.O.Trigger_L2_to_L1D::total 5 -system.ruby.L1Cache_Controller.O.Other_GETX | 7 14.58% 14.58% | 2 4.17% 18.75% | 6 12.50% 31.25% | 10 20.83% 52.08% | 7 14.58% 66.67% | 7 14.58% 81.25% | 2 4.17% 85.42% | 7 14.58% 100.00% -system.ruby.L1Cache_Controller.O.Other_GETX::total 48 -system.ruby.L1Cache_Controller.O.Other_GETS | 3 5.08% 5.08% | 4 6.78% 11.86% | 7 11.86% 23.73% | 11 18.64% 42.37% | 9 15.25% 57.63% | 7 11.86% 69.49% | 10 16.95% 86.44% | 8 13.56% 100.00% -system.ruby.L1Cache_Controller.O.Other_GETS::total 59 -system.ruby.L1Cache_Controller.O.Merged_GETS | 3 14.29% 14.29% | 1 4.76% 19.05% | 3 14.29% 33.33% | 4 19.05% 52.38% | 3 14.29% 66.67% | 0 0.00% 66.67% | 5 23.81% 90.48% | 2 9.52% 100.00% -system.ruby.L1Cache_Controller.O.Merged_GETS::total 21 -system.ruby.L1Cache_Controller.M.Load | 1 5.56% 5.56% | 2 11.11% 16.67% | 3 16.67% 33.33% | 4 22.22% 55.56% | 3 16.67% 72.22% | 3 16.67% 88.89% | 1 5.56% 94.44% | 1 5.56% 100.00% -system.ruby.L1Cache_Controller.M.Load::total 18 -system.ruby.L1Cache_Controller.M.Store | 4 19.05% 19.05% | 0 0.00% 19.05% | 2 9.52% 28.57% | 4 19.05% 47.62% | 3 14.29% 61.90% | 0 0.00% 61.90% | 4 19.05% 80.95% | 4 19.05% 100.00% -system.ruby.L1Cache_Controller.M.Store::total 21 -system.ruby.L1Cache_Controller.M.L2_Replacement | 45980 12.53% 12.53% | 45916 12.51% 25.04% | 45952 12.52% 37.55% | 45945 12.52% 50.07% | 45597 12.42% 62.49% | 45962 12.52% 75.01% | 45778 12.47% 87.49% | 45934 12.51% 100.00% -system.ruby.L1Cache_Controller.M.L2_Replacement::total 367064 -system.ruby.L1Cache_Controller.M.L1_to_L2 | 47218 12.53% 12.53% | 47164 12.52% 25.05% | 47173 12.52% 37.56% | 47162 12.52% 50.08% | 46805 12.42% 62.50% | 47183 12.52% 75.02% | 47003 12.47% 87.49% | 47135 12.51% 100.00% -system.ruby.L1Cache_Controller.M.L1_to_L2::total 376843 -system.ruby.L1Cache_Controller.M.Trigger_L2_to_L1D | 42 13.55% 13.55% | 42 13.55% 27.10% | 30 9.68% 36.77% | 44 14.19% 50.97% | 45 14.52% 65.48% | 35 11.29% 76.77% | 39 12.58% 89.35% | 33 10.65% 100.00% -system.ruby.L1Cache_Controller.M.Trigger_L2_to_L1D::total 310 -system.ruby.L1Cache_Controller.M.Other_GETX | 450 12.17% 12.17% | 479 12.95% 25.12% | 475 12.84% 37.97% | 473 12.79% 50.76% | 464 12.55% 63.30% | 444 12.01% 75.31% | 459 12.41% 87.72% | 454 12.28% 100.00% -system.ruby.L1Cache_Controller.M.Other_GETX::total 3698 -system.ruby.L1Cache_Controller.M.Other_GETS | 774 12.68% 12.68% | 778 12.75% 25.43% | 761 12.47% 37.91% | 781 12.80% 50.70% | 728 11.93% 62.64% | 781 12.80% 75.43% | 749 12.27% 87.71% | 750 12.29% 100.00% -system.ruby.L1Cache_Controller.M.Other_GETS::total 6102 -system.ruby.L1Cache_Controller.M.Merged_GETS | 66 13.02% 13.02% | 58 11.44% 24.46% | 70 13.81% 38.26% | 48 9.47% 47.73% | 79 15.58% 63.31% | 49 9.66% 72.98% | 79 15.58% 88.56% | 58 11.44% 100.00% -system.ruby.L1Cache_Controller.M.Merged_GETS::total 507 -system.ruby.L1Cache_Controller.MM.Load | 1 8.33% 8.33% | 1 8.33% 16.67% | 2 16.67% 33.33% | 2 16.67% 50.00% | 1 8.33% 58.33% | 1 8.33% 66.67% | 2 16.67% 83.33% | 2 16.67% 100.00% -system.ruby.L1Cache_Controller.MM.Load::total 12 -system.ruby.L1Cache_Controller.MM.Store | 2 20.00% 20.00% | 0 0.00% 20.00% | 1 10.00% 30.00% | 2 20.00% 50.00% | 1 10.00% 60.00% | 1 10.00% 70.00% | 2 20.00% 90.00% | 1 10.00% 100.00% -system.ruby.L1Cache_Controller.MM.Store::total 10 -system.ruby.L1Cache_Controller.MM.L2_Replacement | 27411 12.60% 12.60% | 27088 12.45% 25.05% | 27175 12.49% 37.54% | 27252 12.53% 50.07% | 27368 12.58% 62.65% | 26904 12.37% 75.01% | 27423 12.60% 87.62% | 26940 12.38% 100.00% -system.ruby.L1Cache_Controller.MM.L2_Replacement::total 217561 -system.ruby.L1Cache_Controller.MM.L1_to_L2 | 28093 12.59% 12.59% | 27802 12.46% 25.05% | 27903 12.50% 37.55% | 27924 12.51% 50.07% | 28049 12.57% 62.64% | 27597 12.37% 75.01% | 28124 12.60% 87.61% | 27644 12.39% 100.00% -system.ruby.L1Cache_Controller.MM.L1_to_L2::total 223136 -system.ruby.L1Cache_Controller.MM.Trigger_L2_to_L1D | 37 16.23% 16.23% | 35 15.35% 31.58% | 26 11.40% 42.98% | 28 12.28% 55.26% | 24 10.53% 65.79% | 29 12.72% 78.51% | 28 12.28% 90.79% | 21 9.21% 100.00% -system.ruby.L1Cache_Controller.MM.Trigger_L2_to_L1D::total 228 -system.ruby.L1Cache_Controller.MM.Other_GETX | 238 11.94% 11.94% | 259 12.99% 24.92% | 260 13.04% 37.96% | 220 11.03% 49.00% | 271 13.59% 62.59% | 241 12.09% 74.67% | 258 12.94% 87.61% | 247 12.39% 100.00% -system.ruby.L1Cache_Controller.MM.Other_GETX::total 1994 -system.ruby.L1Cache_Controller.MM.Other_GETS | 422 12.02% 12.02% | 442 12.59% 24.60% | 452 12.87% 37.47% | 444 12.64% 50.11% | 400 11.39% 61.50% | 449 12.78% 74.29% | 443 12.61% 86.90% | 460 13.10% 100.00% -system.ruby.L1Cache_Controller.MM.Other_GETS::total 3512 -system.ruby.L1Cache_Controller.MM.Merged_GETS | 40 11.98% 11.98% | 43 12.87% 24.85% | 38 11.38% 36.23% | 43 12.87% 49.10% | 47 14.07% 63.17% | 50 14.97% 78.14% | 38 11.38% 89.52% | 35 10.48% 100.00% -system.ruby.L1Cache_Controller.MM.Merged_GETS::total 334 -system.ruby.L1Cache_Controller.IR.Load | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 2 66.67% 66.67% | 0 0.00% 66.67% | 1 33.33% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.IR.Load::total 3 -system.ruby.L1Cache_Controller.IR.Store | 2 28.57% 28.57% | 1 14.29% 42.86% | 0 0.00% 42.86% | 1 14.29% 57.14% | 1 14.29% 71.43% | 1 14.29% 85.71% | 0 0.00% 85.71% | 1 14.29% 100.00% -system.ruby.L1Cache_Controller.IR.Store::total 7 -system.ruby.L1Cache_Controller.IR.L1_to_L2 | 10 43.48% 43.48% | 0 0.00% 43.48% | 0 0.00% 43.48% | 7 30.43% 73.91% | 1 4.35% 78.26% | 0 0.00% 78.26% | 5 21.74% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.IR.L1_to_L2::total 23 -system.ruby.L1Cache_Controller.SR.Load | 1 10.00% 10.00% | 2 20.00% 30.00% | 2 20.00% 50.00% | 1 10.00% 60.00% | 2 20.00% 80.00% | 0 0.00% 80.00% | 1 10.00% 90.00% | 1 10.00% 100.00% -system.ruby.L1Cache_Controller.SR.Load::total 10 -system.ruby.L1Cache_Controller.SR.Store | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 25.00% 25.00% | 2 50.00% 75.00% | 0 0.00% 75.00% | 0 0.00% 75.00% | 1 25.00% 100.00% -system.ruby.L1Cache_Controller.SR.Store::total 4 -system.ruby.L1Cache_Controller.SR.L1_to_L2 | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.SR.L1_to_L2::total 1 -system.ruby.L1Cache_Controller.OR.Load | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 33.33% 33.33% | 0 0.00% 33.33% | 1 33.33% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 1 33.33% 100.00% -system.ruby.L1Cache_Controller.OR.Load::total 3 -system.ruby.L1Cache_Controller.OR.Store | 1 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.S.L2_Replacement | 3221 12.41% 12.41% | 3230 12.44% 24.85% | 3241 12.49% 37.34% | 3151 12.14% 49.48% | 3317 12.78% 62.26% | 3324 12.81% 75.07% | 3203 12.34% 87.41% | 3268 12.59% 100.00% +system.ruby.L1Cache_Controller.S.L2_Replacement::total 25955 +system.ruby.L1Cache_Controller.S.L1_to_L2 | 3248 12.40% 12.40% | 3268 12.48% 24.88% | 3269 12.48% 37.36% | 3185 12.16% 49.53% | 3341 12.76% 62.28% | 3367 12.86% 75.14% | 3224 12.31% 87.45% | 3286 12.55% 100.00% +system.ruby.L1Cache_Controller.S.L1_to_L2::total 26188 +system.ruby.L1Cache_Controller.S.Trigger_L2_to_L1D | 2 7.14% 7.14% | 7 25.00% 32.14% | 2 7.14% 39.29% | 6 21.43% 60.71% | 4 14.29% 75.00% | 3 10.71% 85.71% | 2 7.14% 92.86% | 2 7.14% 100.00% +system.ruby.L1Cache_Controller.S.Trigger_L2_to_L1D::total 28 +system.ruby.L1Cache_Controller.S.Other_GETX | 28 12.07% 12.07% | 35 15.09% 27.16% | 28 12.07% 39.22% | 33 14.22% 53.45% | 23 9.91% 63.36% | 45 19.40% 82.76% | 20 8.62% 91.38% | 20 8.62% 100.00% +system.ruby.L1Cache_Controller.S.Other_GETX::total 232 +system.ruby.L1Cache_Controller.S.Other_GETS | 62 14.62% 14.62% | 53 12.50% 27.12% | 44 10.38% 37.50% | 42 9.91% 47.41% | 54 12.74% 60.14% | 47 11.08% 71.23% | 67 15.80% 87.03% | 55 12.97% 100.00% +system.ruby.L1Cache_Controller.S.Other_GETS::total 424 +system.ruby.L1Cache_Controller.O.L2_Replacement | 838 12.35% 12.35% | 856 12.62% 24.97% | 806 11.88% 36.86% | 859 12.66% 49.52% | 821 12.10% 61.62% | 862 12.71% 74.33% | 851 12.55% 86.88% | 890 13.12% 100.00% +system.ruby.L1Cache_Controller.O.L2_Replacement::total 6783 +system.ruby.L1Cache_Controller.O.L1_to_L2 | 81 13.92% 13.92% | 64 11.00% 24.91% | 74 12.71% 37.63% | 70 12.03% 49.66% | 59 10.14% 59.79% | 67 11.51% 71.31% | 86 14.78% 86.08% | 81 13.92% 100.00% +system.ruby.L1Cache_Controller.O.L1_to_L2::total 582 +system.ruby.L1Cache_Controller.O.Trigger_L2_to_L1D | 1 11.11% 11.11% | 1 11.11% 22.22% | 2 22.22% 44.44% | 0 0.00% 44.44% | 2 22.22% 66.67% | 0 0.00% 66.67% | 2 22.22% 88.89% | 1 11.11% 100.00% +system.ruby.L1Cache_Controller.O.Trigger_L2_to_L1D::total 9 +system.ruby.L1Cache_Controller.O.Other_GETX | 5 16.67% 16.67% | 2 6.67% 23.33% | 5 16.67% 40.00% | 6 20.00% 60.00% | 7 23.33% 83.33% | 1 3.33% 86.67% | 3 10.00% 96.67% | 1 3.33% 100.00% +system.ruby.L1Cache_Controller.O.Other_GETX::total 30 +system.ruby.L1Cache_Controller.O.Other_GETS | 11 16.42% 16.42% | 8 11.94% 28.36% | 6 8.96% 37.31% | 10 14.93% 52.24% | 9 13.43% 65.67% | 9 13.43% 79.10% | 5 7.46% 86.57% | 9 13.43% 100.00% +system.ruby.L1Cache_Controller.O.Other_GETS::total 67 +system.ruby.L1Cache_Controller.O.Merged_GETS | 0 0.00% 0.00% | 2 11.11% 11.11% | 3 16.67% 27.78% | 1 5.56% 33.33% | 4 22.22% 55.56% | 4 22.22% 77.78% | 1 5.56% 83.33% | 3 16.67% 100.00% +system.ruby.L1Cache_Controller.O.Merged_GETS::total 18 +system.ruby.L1Cache_Controller.M.Load | 7 21.21% 21.21% | 3 9.09% 30.30% | 7 21.21% 51.52% | 1 3.03% 54.55% | 5 15.15% 69.70% | 4 12.12% 81.82% | 2 6.06% 87.88% | 4 12.12% 100.00% +system.ruby.L1Cache_Controller.M.Load::total 33 +system.ruby.L1Cache_Controller.M.Store | 2 13.33% 13.33% | 0 0.00% 13.33% | 1 6.67% 20.00% | 3 20.00% 40.00% | 4 26.67% 66.67% | 2 13.33% 80.00% | 3 20.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.M.Store::total 15 +system.ruby.L1Cache_Controller.M.L2_Replacement | 45788 12.46% 12.46% | 46023 12.52% 24.98% | 45848 12.48% 37.46% | 46041 12.53% 49.99% | 45893 12.49% 62.48% | 45908 12.49% 74.97% | 45944 12.50% 87.48% | 46021 12.52% 100.00% +system.ruby.L1Cache_Controller.M.L2_Replacement::total 367466 +system.ruby.L1Cache_Controller.M.L1_to_L2 | 46942 12.45% 12.45% | 47247 12.53% 24.98% | 47018 12.47% 37.45% | 47302 12.54% 49.99% | 47109 12.49% 62.48% | 47115 12.49% 74.98% | 47118 12.50% 87.47% | 47240 12.53% 100.00% +system.ruby.L1Cache_Controller.M.L1_to_L2::total 377091 +system.ruby.L1Cache_Controller.M.Trigger_L2_to_L1D | 39 12.30% 12.30% | 35 11.04% 23.34% | 34 10.73% 34.07% | 45 14.20% 48.26% | 36 11.36% 59.62% | 34 10.73% 70.35% | 43 13.56% 83.91% | 51 16.09% 100.00% +system.ruby.L1Cache_Controller.M.Trigger_L2_to_L1D::total 317 +system.ruby.L1Cache_Controller.M.Other_GETX | 426 11.63% 11.63% | 469 12.80% 24.43% | 474 12.94% 37.36% | 499 13.62% 50.98% | 473 12.91% 63.89% | 454 12.39% 76.28% | 433 11.82% 88.10% | 436 11.90% 100.00% +system.ruby.L1Cache_Controller.M.Other_GETX::total 3664 +system.ruby.L1Cache_Controller.M.Other_GETS | 726 12.31% 12.31% | 735 12.46% 24.77% | 709 12.02% 36.79% | 751 12.73% 49.52% | 725 12.29% 61.81% | 746 12.65% 74.45% | 739 12.53% 86.98% | 768 13.02% 100.00% +system.ruby.L1Cache_Controller.M.Other_GETS::total 5899 +system.ruby.L1Cache_Controller.M.Merged_GETS | 78 13.59% 13.59% | 87 15.16% 28.75% | 57 9.93% 38.68% | 69 12.02% 50.70% | 61 10.63% 61.32% | 73 12.72% 74.04% | 73 12.72% 86.76% | 76 13.24% 100.00% +system.ruby.L1Cache_Controller.M.Merged_GETS::total 574 +system.ruby.L1Cache_Controller.MM.Load | 1 5.56% 5.56% | 2 11.11% 16.67% | 1 5.56% 22.22% | 6 33.33% 55.56% | 3 16.67% 72.22% | 1 5.56% 77.78% | 1 5.56% 83.33% | 3 16.67% 100.00% +system.ruby.L1Cache_Controller.MM.Load::total 18 +system.ruby.L1Cache_Controller.MM.Store | 0 0.00% 0.00% | 0 0.00% 0.00% | 3 42.86% 42.86% | 0 0.00% 42.86% | 2 28.57% 71.43% | 0 0.00% 71.43% | 0 0.00% 71.43% | 2 28.57% 100.00% +system.ruby.L1Cache_Controller.MM.Store::total 7 +system.ruby.L1Cache_Controller.MM.L2_Replacement | 27344 12.53% 12.53% | 27393 12.55% 25.08% | 27539 12.62% 37.69% | 26899 12.32% 50.02% | 27526 12.61% 62.63% | 27228 12.47% 75.10% | 27201 12.46% 87.56% | 27148 12.44% 100.00% +system.ruby.L1Cache_Controller.MM.L2_Replacement::total 218278 +system.ruby.L1Cache_Controller.MM.L1_to_L2 | 28016 12.51% 12.51% | 28156 12.57% 25.08% | 28260 12.62% 37.69% | 27634 12.34% 50.03% | 28206 12.59% 62.62% | 27940 12.47% 75.09% | 27939 12.47% 87.56% | 27858 12.44% 100.00% +system.ruby.L1Cache_Controller.MM.L1_to_L2::total 224009 +system.ruby.L1Cache_Controller.MM.Trigger_L2_to_L1D | 24 12.06% 12.06% | 21 10.55% 22.61% | 24 12.06% 34.67% | 19 9.55% 44.22% | 28 14.07% 58.29% | 24 12.06% 70.35% | 37 18.59% 88.94% | 22 11.06% 100.00% +system.ruby.L1Cache_Controller.MM.Trigger_L2_to_L1D::total 199 +system.ruby.L1Cache_Controller.MM.Other_GETX | 248 11.64% 11.64% | 283 13.29% 24.93% | 265 12.44% 37.37% | 277 13.00% 50.38% | 266 12.49% 62.86% | 250 11.74% 74.60% | 302 14.18% 88.78% | 239 11.22% 100.00% +system.ruby.L1Cache_Controller.MM.Other_GETX::total 2130 +system.ruby.L1Cache_Controller.MM.Other_GETS | 402 11.45% 11.45% | 475 13.53% 24.98% | 443 12.62% 37.60% | 447 12.73% 50.33% | 400 11.39% 61.72% | 455 12.96% 74.68% | 437 12.45% 87.13% | 452 12.87% 100.00% +system.ruby.L1Cache_Controller.MM.Other_GETS::total 3511 +system.ruby.L1Cache_Controller.MM.Merged_GETS | 40 11.66% 11.66% | 38 11.08% 22.74% | 45 13.12% 35.86% | 45 13.12% 48.98% | 42 12.24% 61.22% | 44 12.83% 74.05% | 42 12.24% 86.30% | 47 13.70% 100.00% +system.ruby.L1Cache_Controller.MM.Merged_GETS::total 343 +system.ruby.L1Cache_Controller.IR.Load | 1 11.11% 11.11% | 1 11.11% 22.22% | 1 11.11% 33.33% | 0 0.00% 33.33% | 2 22.22% 55.56% | 1 11.11% 66.67% | 1 11.11% 77.78% | 2 22.22% 100.00% +system.ruby.L1Cache_Controller.IR.Load::total 9 +system.ruby.L1Cache_Controller.IR.Store | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% +system.ruby.L1Cache_Controller.IR.Store::total 1 +system.ruby.L1Cache_Controller.IR.L1_to_L2 | 0 0.00% 0.00% | 10 71.43% 71.43% | 0 0.00% 71.43% | 0 0.00% 71.43% | 1 7.14% 78.57% | 0 0.00% 78.57% | 1 7.14% 85.71% | 2 14.29% 100.00% +system.ruby.L1Cache_Controller.IR.L1_to_L2::total 14 +system.ruby.L1Cache_Controller.SR.Load | 2 10.00% 10.00% | 4 20.00% 30.00% | 2 10.00% 40.00% | 4 20.00% 60.00% | 3 15.00% 75.00% | 3 15.00% 90.00% | 0 0.00% 90.00% | 2 10.00% 100.00% +system.ruby.L1Cache_Controller.SR.Load::total 20 +system.ruby.L1Cache_Controller.SR.Store | 0 0.00% 0.00% | 3 37.50% 37.50% | 0 0.00% 37.50% | 2 25.00% 62.50% | 1 12.50% 75.00% | 0 0.00% 75.00% | 2 25.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.SR.Store::total 8 +system.ruby.L1Cache_Controller.SR.L1_to_L2 | 8 12.70% 12.70% | 13 20.63% 33.33% | 6 9.52% 42.86% | 18 28.57% 71.43% | 12 19.05% 90.48% | 6 9.52% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.SR.L1_to_L2::total 63 +system.ruby.L1Cache_Controller.OR.Load | 0 0.00% 0.00% | 0 0.00% 0.00% | 2 28.57% 28.57% | 0 0.00% 28.57% | 2 28.57% 57.14% | 0 0.00% 57.14% | 2 28.57% 85.71% | 1 14.29% 100.00% +system.ruby.L1Cache_Controller.OR.Load::total 7 +system.ruby.L1Cache_Controller.OR.Store | 1 50.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.L1Cache_Controller.OR.Store::total 2 -system.ruby.L1Cache_Controller.OR.L1_to_L2 | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.OR.L1_to_L2::total 1 -system.ruby.L1Cache_Controller.MR.Load | 25 13.09% 13.09% | 23 12.04% 25.13% | 21 10.99% 36.13% | 29 15.18% 51.31% | 31 16.23% 67.54% | 16 8.38% 75.92% | 26 13.61% 89.53% | 20 10.47% 100.00% -system.ruby.L1Cache_Controller.MR.Load::total 191 -system.ruby.L1Cache_Controller.MR.Store | 17 14.29% 14.29% | 19 15.97% 30.25% | 9 7.56% 37.82% | 15 12.61% 50.42% | 14 11.76% 62.18% | 19 15.97% 78.15% | 13 10.92% 89.08% | 13 10.92% 100.00% -system.ruby.L1Cache_Controller.MR.Store::total 119 -system.ruby.L1Cache_Controller.MR.L1_to_L2 | 94 15.75% 15.75% | 102 17.09% 32.83% | 50 8.38% 41.21% | 86 14.41% 55.61% | 74 12.40% 68.01% | 83 13.90% 81.91% | 76 12.73% 94.64% | 32 5.36% 100.00% -system.ruby.L1Cache_Controller.MR.L1_to_L2::total 597 -system.ruby.L1Cache_Controller.MMR.Load | 23 15.54% 15.54% | 22 14.86% 30.41% | 21 14.19% 44.59% | 20 13.51% 58.11% | 10 6.76% 64.86% | 17 11.49% 76.35% | 21 14.19% 90.54% | 14 9.46% 100.00% -system.ruby.L1Cache_Controller.MMR.Load::total 148 -system.ruby.L1Cache_Controller.MMR.Store | 14 17.50% 17.50% | 13 16.25% 33.75% | 5 6.25% 40.00% | 8 10.00% 50.00% | 14 17.50% 67.50% | 12 15.00% 82.50% | 7 8.75% 91.25% | 7 8.75% 100.00% -system.ruby.L1Cache_Controller.MMR.Store::total 80 -system.ruby.L1Cache_Controller.MMR.L1_to_L2 | 69 17.38% 17.38% | 39 9.82% 27.20% | 42 10.58% 37.78% | 55 13.85% 51.64% | 39 9.82% 61.46% | 89 22.42% 83.88% | 28 7.05% 90.93% | 36 9.07% 100.00% -system.ruby.L1Cache_Controller.MMR.L1_to_L2::total 397 -system.ruby.L1Cache_Controller.IM.L1_to_L2 | 274713 12.40% 12.40% | 274213 12.37% 24.77% | 276032 12.46% 37.23% | 277552 12.52% 49.75% | 280112 12.64% 62.39% | 276280 12.47% 74.86% | 283147 12.78% 87.64% | 274015 12.36% 100.00% -system.ruby.L1Cache_Controller.IM.L1_to_L2::total 2216064 -system.ruby.L1Cache_Controller.IM.Other_GETX | 59 13.00% 13.00% | 50 11.01% 24.01% | 45 9.91% 33.92% | 57 12.56% 46.48% | 54 11.89% 58.37% | 72 15.86% 74.23% | 65 14.32% 88.55% | 52 11.45% 100.00% -system.ruby.L1Cache_Controller.IM.Other_GETX::total 454 -system.ruby.L1Cache_Controller.IM.Other_GETS | 85 9.74% 9.74% | 98 11.23% 20.96% | 117 13.40% 34.36% | 120 13.75% 48.11% | 111 12.71% 60.82% | 113 12.94% 73.77% | 106 12.14% 85.91% | 123 14.09% 100.00% -system.ruby.L1Cache_Controller.IM.Other_GETS::total 873 -system.ruby.L1Cache_Controller.IM.Ack | 143024 12.60% 12.60% | 140883 12.41% 25.01% | 141838 12.50% 37.51% | 142363 12.54% 50.05% | 142609 12.56% 62.62% | 141109 12.43% 75.05% | 142897 12.59% 87.64% | 140315 12.36% 100.00% -system.ruby.L1Cache_Controller.IM.Ack::total 1135038 -system.ruby.L1Cache_Controller.IM.Data | 1363 12.61% 12.61% | 1297 12.00% 24.62% | 1305 12.08% 36.70% | 1478 13.68% 50.37% | 1340 12.40% 62.78% | 1337 12.37% 75.15% | 1326 12.27% 87.42% | 1359 12.58% 100.00% -system.ruby.L1Cache_Controller.IM.Data::total 10805 -system.ruby.L1Cache_Controller.IM.Exclusive_Data | 26726 12.58% 12.58% | 26520 12.48% 25.06% | 26611 12.53% 37.59% | 26464 12.46% 50.04% | 26725 12.58% 62.62% | 26292 12.37% 75.00% | 26818 12.62% 87.62% | 26305 12.38% 100.00% -system.ruby.L1Cache_Controller.IM.Exclusive_Data::total 212461 -system.ruby.L1Cache_Controller.SM.L1_to_L2 | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 5 71.43% 71.43% | 2 28.57% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.SM.L1_to_L2::total 7 -system.ruby.L1Cache_Controller.SM.Ack | 7 25.00% 25.00% | 0 0.00% 25.00% | 0 0.00% 25.00% | 7 25.00% 50.00% | 14 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.SM.Ack::total 28 -system.ruby.L1Cache_Controller.SM.Data | 1 16.67% 16.67% | 0 0.00% 16.67% | 0 0.00% 16.67% | 1 16.67% 33.33% | 3 50.00% 83.33% | 0 0.00% 83.33% | 0 0.00% 83.33% | 1 16.67% 100.00% -system.ruby.L1Cache_Controller.SM.Data::total 6 -system.ruby.L1Cache_Controller.OM.L1_to_L2 | 10 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.OM.L1_to_L2::total 10 -system.ruby.L1Cache_Controller.OM.Ack | 7 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 7 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.OR.L1_to_L2 | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 7.14% 7.14% | 0 0.00% 7.14% | 7 50.00% 57.14% | 0 0.00% 57.14% | 0 0.00% 57.14% | 6 42.86% 100.00% +system.ruby.L1Cache_Controller.OR.L1_to_L2::total 14 +system.ruby.L1Cache_Controller.MR.Load | 27 12.62% 12.62% | 21 9.81% 22.43% | 24 11.21% 33.64% | 30 14.02% 47.66% | 23 10.75% 58.41% | 22 10.28% 68.69% | 29 13.55% 82.24% | 38 17.76% 100.00% +system.ruby.L1Cache_Controller.MR.Load::total 214 +system.ruby.L1Cache_Controller.MR.Store | 12 11.65% 11.65% | 14 13.59% 25.24% | 10 9.71% 34.95% | 15 14.56% 49.51% | 13 12.62% 62.14% | 12 11.65% 73.79% | 14 13.59% 87.38% | 13 12.62% 100.00% +system.ruby.L1Cache_Controller.MR.Store::total 103 +system.ruby.L1Cache_Controller.MR.L1_to_L2 | 54 9.57% 9.57% | 59 10.46% 20.04% | 75 13.30% 33.33% | 104 18.44% 51.77% | 53 9.40% 61.17% | 57 10.11% 71.28% | 95 16.84% 88.12% | 67 11.88% 100.00% +system.ruby.L1Cache_Controller.MR.L1_to_L2::total 564 +system.ruby.L1Cache_Controller.MMR.Load | 18 14.75% 14.75% | 8 6.56% 21.31% | 19 15.57% 36.89% | 9 7.38% 44.26% | 14 11.48% 55.74% | 14 11.48% 67.21% | 25 20.49% 87.70% | 15 12.30% 100.00% +system.ruby.L1Cache_Controller.MMR.Load::total 122 +system.ruby.L1Cache_Controller.MMR.Store | 6 7.79% 7.79% | 13 16.88% 24.68% | 5 6.49% 31.17% | 10 12.99% 44.16% | 14 18.18% 62.34% | 10 12.99% 75.32% | 12 15.58% 90.91% | 7 9.09% 100.00% +system.ruby.L1Cache_Controller.MMR.Store::total 77 +system.ruby.L1Cache_Controller.MMR.L1_to_L2 | 70 21.60% 21.60% | 45 13.89% 35.49% | 31 9.57% 45.06% | 21 6.48% 51.54% | 26 8.02% 59.57% | 33 10.19% 69.75% | 71 21.91% 91.67% | 27 8.33% 100.00% +system.ruby.L1Cache_Controller.MMR.L1_to_L2::total 324 +system.ruby.L1Cache_Controller.IM.L1_to_L2 | 278922 12.54% 12.54% | 278884 12.54% 25.09% | 280828 12.63% 37.71% | 276004 12.41% 50.13% | 281673 12.67% 62.79% | 275479 12.39% 75.18% | 275157 12.37% 87.56% | 276670 12.44% 100.00% +system.ruby.L1Cache_Controller.IM.L1_to_L2::total 2223617 +system.ruby.L1Cache_Controller.IM.Other_GETX | 62 11.50% 11.50% | 80 14.84% 26.35% | 63 11.69% 38.03% | 64 11.87% 49.91% | 49 9.09% 59.00% | 79 14.66% 73.65% | 68 12.62% 86.27% | 74 13.73% 100.00% +system.ruby.L1Cache_Controller.IM.Other_GETX::total 539 +system.ruby.L1Cache_Controller.IM.Other_GETS | 122 13.19% 13.19% | 114 12.32% 25.51% | 111 12.00% 37.51% | 122 13.19% 50.70% | 132 14.27% 64.97% | 114 12.32% 77.30% | 111 12.00% 89.30% | 99 10.70% 100.00% +system.ruby.L1Cache_Controller.IM.Other_GETS::total 925 +system.ruby.L1Cache_Controller.IM.Ack | 136672 12.48% 12.48% | 137498 12.56% 25.04% | 139357 12.73% 37.77% | 134236 12.26% 50.03% | 137674 12.57% 62.61% | 136413 12.46% 75.07% | 136515 12.47% 87.54% | 136466 12.46% 100.00% +system.ruby.L1Cache_Controller.IM.Ack::total 1094831 +system.ruby.L1Cache_Controller.IM.Data | 1385 12.77% 12.77% | 1390 12.82% 25.59% | 1413 13.03% 38.62% | 1313 12.11% 50.72% | 1321 12.18% 62.90% | 1338 12.34% 75.24% | 1325 12.22% 87.46% | 1360 12.54% 100.00% +system.ruby.L1Cache_Controller.IM.Data::total 10845 +system.ruby.L1Cache_Controller.IM.Exclusive_Data | 26634 12.49% 12.49% | 26785 12.56% 25.04% | 26868 12.60% 37.64% | 26334 12.35% 49.99% | 26894 12.61% 62.60% | 26626 12.48% 75.08% | 26639 12.49% 87.57% | 26515 12.43% 100.00% +system.ruby.L1Cache_Controller.IM.Exclusive_Data::total 213295 +system.ruby.L1Cache_Controller.SM.L1_to_L2 | 4 7.27% 7.27% | 12 21.82% 29.09% | 0 0.00% 29.09% | 0 0.00% 29.09% | 0 0.00% 29.09% | 0 0.00% 29.09% | 39 70.91% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.SM.L1_to_L2::total 55 +system.ruby.L1Cache_Controller.SM.Other_GETX | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.SM.Other_GETX::total 1 +system.ruby.L1Cache_Controller.SM.Ack | 0 0.00% 0.00% | 14 60.87% 60.87% | 0 0.00% 60.87% | 8 34.78% 95.65% | 0 0.00% 95.65% | 0 0.00% 95.65% | 1 4.35% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.SM.Ack::total 23 +system.ruby.L1Cache_Controller.SM.Data | 1 11.11% 11.11% | 3 33.33% 44.44% | 0 0.00% 44.44% | 2 22.22% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 3 33.33% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.SM.Data::total 9 +system.ruby.L1Cache_Controller.OM.L1_to_L2 | 32 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.OM.L1_to_L2::total 32 +system.ruby.L1Cache_Controller.OM.Ack | 7 50.00% 50.00% | 7 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.L1Cache_Controller.OM.Ack::total 14 -system.ruby.L1Cache_Controller.OM.All_acks_no_sharers | 1 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.OM.All_acks_no_sharers | 1 50.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.L1Cache_Controller.OM.All_acks_no_sharers::total 2 -system.ruby.L1Cache_Controller.ISM.L1_to_L2 | 1007 10.85% 10.85% | 1353 14.58% 25.42% | 1037 11.17% 36.59% | 1556 16.76% 53.36% | 1024 11.03% 64.39% | 1087 11.71% 76.10% | 1067 11.49% 87.59% | 1152 12.41% 100.00% -system.ruby.L1Cache_Controller.ISM.L1_to_L2::total 9283 -system.ruby.L1Cache_Controller.ISM.Ack | 2517 11.99% 11.99% | 2466 11.75% 23.74% | 2543 12.12% 35.86% | 2993 14.26% 50.11% | 2755 13.13% 63.24% | 2586 12.32% 75.56% | 2564 12.22% 87.78% | 2566 12.22% 100.00% -system.ruby.L1Cache_Controller.ISM.Ack::total 20990 -system.ruby.L1Cache_Controller.ISM.All_acks_no_sharers | 1364 12.62% 12.62% | 1297 12.00% 24.61% | 1305 12.07% 36.68% | 1479 13.68% 50.37% | 1343 12.42% 62.79% | 1337 12.37% 75.15% | 1326 12.27% 87.42% | 1360 12.58% 100.00% -system.ruby.L1Cache_Controller.ISM.All_acks_no_sharers::total 10811 -system.ruby.L1Cache_Controller.M_W.Load | 0 0.00% 0.00% | 6 22.22% 22.22% | 2 7.41% 29.63% | 3 11.11% 40.74% | 4 14.81% 55.56% | 6 22.22% 77.78% | 5 18.52% 96.30% | 1 3.70% 100.00% -system.ruby.L1Cache_Controller.M_W.Load::total 27 -system.ruby.L1Cache_Controller.M_W.Store | 3 37.50% 37.50% | 0 0.00% 37.50% | 2 25.00% 62.50% | 0 0.00% 62.50% | 1 12.50% 75.00% | 0 0.00% 75.00% | 2 25.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.M_W.Store::total 8 -system.ruby.L1Cache_Controller.M_W.L1_to_L2 | 63122 12.28% 12.28% | 64179 12.48% 24.76% | 64634 12.57% 37.33% | 63376 12.33% 49.66% | 64257 12.50% 62.16% | 65116 12.67% 74.83% | 64478 12.54% 87.37% | 64945 12.63% 100.00% -system.ruby.L1Cache_Controller.M_W.L1_to_L2::total 514107 -system.ruby.L1Cache_Controller.M_W.Ack | 87604 12.42% 12.42% | 87878 12.45% 24.87% | 88420 12.53% 37.40% | 88219 12.50% 49.90% | 87686 12.43% 62.33% | 89091 12.63% 74.96% | 87950 12.46% 87.42% | 88748 12.58% 100.00% -system.ruby.L1Cache_Controller.M_W.Ack::total 705596 -system.ruby.L1Cache_Controller.M_W.All_acks_no_sharers | 47293 12.53% 12.53% | 47254 12.52% 25.04% | 47271 12.52% 37.56% | 47269 12.52% 50.08% | 46889 12.42% 62.50% | 47258 12.52% 75.02% | 47086 12.47% 87.49% | 47220 12.51% 100.00% -system.ruby.L1Cache_Controller.M_W.All_acks_no_sharers::total 377540 -system.ruby.L1Cache_Controller.MM_W.Load | 1 5.88% 5.88% | 2 11.76% 17.65% | 3 17.65% 35.29% | 1 5.88% 41.18% | 3 17.65% 58.82% | 1 5.88% 64.71% | 1 5.88% 70.59% | 5 29.41% 100.00% -system.ruby.L1Cache_Controller.MM_W.Load::total 17 -system.ruby.L1Cache_Controller.MM_W.Store | 1 16.67% 16.67% | 3 50.00% 66.67% | 2 33.33% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.MM_W.Store::total 6 -system.ruby.L1Cache_Controller.MM_W.L1_to_L2 | 36722 12.63% 12.63% | 36826 12.67% 25.30% | 37113 12.76% 38.06% | 35896 12.35% 50.41% | 36377 12.51% 62.92% | 35600 12.24% 75.16% | 36168 12.44% 87.60% | 36049 12.40% 100.00% -system.ruby.L1Cache_Controller.MM_W.L1_to_L2::total 290751 -system.ruby.L1Cache_Controller.MM_W.Ack | 50176 12.55% 12.55% | 50453 12.62% 25.18% | 50220 12.56% 37.74% | 49306 12.34% 50.07% | 50222 12.56% 62.64% | 48806 12.21% 74.85% | 50636 12.67% 87.52% | 49898 12.48% 100.00% -system.ruby.L1Cache_Controller.MM_W.Ack::total 399717 -system.ruby.L1Cache_Controller.MM_W.All_acks_no_sharers | 26729 12.58% 12.58% | 26520 12.48% 25.06% | 26613 12.53% 37.59% | 26464 12.46% 50.04% | 26726 12.58% 62.62% | 26292 12.37% 75.00% | 26820 12.62% 87.62% | 26305 12.38% 100.00% -system.ruby.L1Cache_Controller.MM_W.All_acks_no_sharers::total 212469 -system.ruby.L1Cache_Controller.IS.L1_to_L2 | 504630 12.56% 12.56% | 503087 12.52% 25.08% | 502873 12.52% 37.60% | 504272 12.55% 50.15% | 499060 12.42% 62.57% | 502572 12.51% 75.08% | 496893 12.37% 87.45% | 504309 12.55% 100.00% -system.ruby.L1Cache_Controller.IS.L1_to_L2::total 4017696 -system.ruby.L1Cache_Controller.IS.Other_GETX | 103 11.61% 11.61% | 108 12.18% 23.79% | 115 12.97% 36.75% | 129 14.54% 51.30% | 101 11.39% 62.68% | 113 12.74% 75.42% | 112 12.63% 88.05% | 106 11.95% 100.00% -system.ruby.L1Cache_Controller.IS.Other_GETX::total 887 -system.ruby.L1Cache_Controller.IS.Other_GETS | 192 11.83% 11.83% | 215 13.25% 25.08% | 196 12.08% 37.15% | 188 11.58% 48.74% | 193 11.89% 60.63% | 216 13.31% 73.94% | 199 12.26% 86.20% | 224 13.80% 100.00% -system.ruby.L1Cache_Controller.IS.Other_GETS::total 1623 -system.ruby.L1Cache_Controller.IS.Ack | 257105 12.56% 12.56% | 256488 12.53% 25.08% | 255973 12.50% 37.58% | 256498 12.53% 50.11% | 254407 12.42% 62.54% | 256125 12.51% 75.05% | 255415 12.47% 87.52% | 255541 12.48% 100.00% -system.ruby.L1Cache_Controller.IS.Ack::total 2047552 -system.ruby.L1Cache_Controller.IS.Shared_Ack | 21 7.50% 7.50% | 28 10.00% 17.50% | 33 11.79% 29.29% | 46 16.43% 45.71% | 35 12.50% 58.21% | 39 13.93% 72.14% | 39 13.93% 86.07% | 39 13.93% 100.00% -system.ruby.L1Cache_Controller.IS.Shared_Ack::total 280 -system.ruby.L1Cache_Controller.IS.Data | 2076 12.31% 12.31% | 2080 12.33% 24.64% | 2047 12.13% 36.77% | 2101 12.45% 49.22% | 2132 12.64% 61.86% | 2164 12.83% 74.69% | 2122 12.58% 87.27% | 2148 12.73% 100.00% -system.ruby.L1Cache_Controller.IS.Data::total 16870 -system.ruby.L1Cache_Controller.IS.Shared_Data | 1192 12.40% 12.40% | 1173 12.20% 24.60% | 1206 12.55% 37.15% | 1220 12.69% 49.84% | 1176 12.23% 62.07% | 1276 13.27% 75.35% | 1184 12.32% 87.66% | 1186 12.34% 100.00% -system.ruby.L1Cache_Controller.IS.Shared_Data::total 9613 -system.ruby.L1Cache_Controller.IS.Exclusive_Data | 47296 12.53% 12.53% | 47254 12.52% 25.04% | 47273 12.52% 37.56% | 47270 12.52% 50.08% | 46891 12.42% 62.50% | 47258 12.52% 75.02% | 47089 12.47% 87.49% | 47221 12.51% 100.00% -system.ruby.L1Cache_Controller.IS.Exclusive_Data::total 377552 -system.ruby.L1Cache_Controller.SS.Load | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.ISM.L1_to_L2 | 1654 14.08% 14.08% | 1334 11.36% 25.44% | 1564 13.32% 38.75% | 1401 11.93% 50.68% | 1584 13.49% 64.17% | 1430 12.17% 76.34% | 1334 11.36% 87.70% | 1445 12.30% 100.00% +system.ruby.L1Cache_Controller.ISM.L1_to_L2::total 11746 +system.ruby.L1Cache_Controller.ISM.Ack | 3080 13.09% 13.09% | 2971 12.63% 25.72% | 2974 12.64% 38.36% | 2882 12.25% 50.61% | 2947 12.52% 63.13% | 3048 12.95% 76.08% | 2844 12.09% 88.17% | 2783 11.83% 100.00% +system.ruby.L1Cache_Controller.ISM.Ack::total 23529 +system.ruby.L1Cache_Controller.ISM.All_acks_no_sharers | 1386 12.77% 12.77% | 1393 12.83% 25.60% | 1413 13.02% 38.62% | 1315 12.12% 50.74% | 1321 12.17% 62.91% | 1338 12.33% 75.23% | 1328 12.24% 87.47% | 1360 12.53% 100.00% +system.ruby.L1Cache_Controller.ISM.All_acks_no_sharers::total 10854 +system.ruby.L1Cache_Controller.M_W.Load | 1 5.00% 5.00% | 2 10.00% 15.00% | 3 15.00% 30.00% | 3 15.00% 45.00% | 5 25.00% 70.00% | 4 20.00% 90.00% | 1 5.00% 95.00% | 1 5.00% 100.00% +system.ruby.L1Cache_Controller.M_W.Load::total 20 +system.ruby.L1Cache_Controller.M_W.Store | 2 12.50% 12.50% | 1 6.25% 18.75% | 3 18.75% 37.50% | 4 25.00% 62.50% | 4 25.00% 87.50% | 1 6.25% 93.75% | 0 0.00% 93.75% | 1 6.25% 100.00% +system.ruby.L1Cache_Controller.M_W.Store::total 16 +system.ruby.L1Cache_Controller.M_W.L1_to_L2 | 74211 12.51% 12.51% | 73890 12.45% 24.96% | 73594 12.40% 37.36% | 74076 12.48% 49.84% | 74874 12.62% 62.46% | 75025 12.64% 75.10% | 73018 12.30% 87.40% | 74757 12.60% 100.00% +system.ruby.L1Cache_Controller.M_W.L1_to_L2::total 593445 +system.ruby.L1Cache_Controller.M_W.Ack | 97926 12.44% 12.44% | 97718 12.42% 24.86% | 98794 12.55% 37.42% | 98518 12.52% 49.94% | 99085 12.59% 62.53% | 98436 12.51% 75.04% | 97279 12.36% 87.40% | 99172 12.60% 100.00% +system.ruby.L1Cache_Controller.M_W.Ack::total 786928 +system.ruby.L1Cache_Controller.M_W.All_acks_no_sharers | 47035 12.45% 12.45% | 47328 12.53% 24.98% | 47103 12.47% 37.45% | 47380 12.54% 49.99% | 47173 12.49% 62.48% | 47199 12.49% 74.98% | 47210 12.50% 87.47% | 47319 12.53% 100.00% +system.ruby.L1Cache_Controller.M_W.All_acks_no_sharers::total 377747 +system.ruby.L1Cache_Controller.MM_W.Load | 1 5.26% 5.26% | 3 15.79% 21.05% | 1 5.26% 26.32% | 3 15.79% 42.11% | 4 21.05% 63.16% | 2 10.53% 73.68% | 3 15.79% 89.47% | 2 10.53% 100.00% +system.ruby.L1Cache_Controller.MM_W.Load::total 19 +system.ruby.L1Cache_Controller.MM_W.Store | 3 42.86% 42.86% | 0 0.00% 42.86% | 1 14.29% 57.14% | 0 0.00% 57.14% | 1 14.29% 71.43% | 2 28.57% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.MM_W.Store::total 7 +system.ruby.L1Cache_Controller.MM_W.L1_to_L2 | 42529 12.65% 12.65% | 42714 12.70% 25.35% | 41979 12.48% 37.83% | 41933 12.47% 50.30% | 42121 12.53% 62.83% | 41515 12.35% 75.17% | 41809 12.43% 87.61% | 41681 12.39% 100.00% +system.ruby.L1Cache_Controller.MM_W.L1_to_L2::total 336281 +system.ruby.L1Cache_Controller.MM_W.Ack | 55486 12.51% 12.51% | 55882 12.60% 25.11% | 54740 12.34% 37.45% | 55509 12.52% 49.97% | 56002 12.63% 62.60% | 55351 12.48% 75.08% | 55541 12.52% 87.60% | 54986 12.40% 100.00% +system.ruby.L1Cache_Controller.MM_W.Ack::total 443497 +system.ruby.L1Cache_Controller.MM_W.All_acks_no_sharers | 26636 12.49% 12.49% | 26786 12.56% 25.04% | 26871 12.60% 37.64% | 26338 12.35% 49.99% | 26898 12.61% 62.60% | 26627 12.48% 75.08% | 26639 12.49% 87.57% | 26516 12.43% 100.00% +system.ruby.L1Cache_Controller.MM_W.All_acks_no_sharers::total 213311 +system.ruby.L1Cache_Controller.IS.L1_to_L2 | 498344 12.45% 12.45% | 499845 12.49% 24.94% | 498249 12.45% 37.39% | 500193 12.50% 49.89% | 497512 12.43% 62.32% | 502981 12.57% 74.89% | 502709 12.56% 87.45% | 502230 12.55% 100.00% +system.ruby.L1Cache_Controller.IS.L1_to_L2::total 4002063 +system.ruby.L1Cache_Controller.IS.Other_GETX | 113 12.07% 12.07% | 119 12.71% 24.79% | 115 12.29% 37.07% | 109 11.65% 48.72% | 125 13.35% 62.07% | 123 13.14% 75.21% | 120 12.82% 88.03% | 112 11.97% 100.00% +system.ruby.L1Cache_Controller.IS.Other_GETX::total 936 +system.ruby.L1Cache_Controller.IS.Other_GETS | 228 14.04% 14.04% | 201 12.38% 26.42% | 192 11.82% 38.24% | 206 12.68% 50.92% | 192 11.82% 62.75% | 195 12.01% 74.75% | 229 14.10% 88.85% | 181 11.15% 100.00% +system.ruby.L1Cache_Controller.IS.Other_GETS::total 1624 +system.ruby.L1Cache_Controller.IS.Ack | 244442 12.45% 12.45% | 246481 12.56% 25.01% | 244196 12.44% 37.45% | 245842 12.52% 49.98% | 244425 12.45% 62.43% | 245791 12.52% 74.95% | 246310 12.55% 87.50% | 245330 12.50% 100.00% +system.ruby.L1Cache_Controller.IS.Ack::total 1962817 +system.ruby.L1Cache_Controller.IS.Shared_Ack | 33 10.93% 10.93% | 41 13.58% 24.50% | 32 10.60% 35.10% | 36 11.92% 47.02% | 41 13.58% 60.60% | 49 16.23% 76.82% | 35 11.59% 88.41% | 35 11.59% 100.00% +system.ruby.L1Cache_Controller.IS.Shared_Ack::total 302 +system.ruby.L1Cache_Controller.IS.Data | 2045 12.34% 12.34% | 2085 12.58% 24.93% | 2074 12.52% 37.45% | 2001 12.08% 49.52% | 2142 12.93% 62.45% | 2131 12.86% 75.31% | 2029 12.25% 87.56% | 2061 12.44% 100.00% +system.ruby.L1Cache_Controller.IS.Data::total 16568 +system.ruby.L1Cache_Controller.IS.Shared_Data | 1205 12.51% 12.51% | 1184 12.29% 24.80% | 1195 12.41% 37.21% | 1186 12.31% 49.52% | 1199 12.45% 61.97% | 1238 12.85% 74.82% | 1198 12.44% 87.26% | 1227 12.74% 100.00% +system.ruby.L1Cache_Controller.IS.Shared_Data::total 9632 +system.ruby.L1Cache_Controller.IS.Exclusive_Data | 47037 12.45% 12.45% | 47329 12.53% 24.98% | 47106 12.47% 37.45% | 47384 12.54% 49.99% | 47177 12.49% 62.48% | 47200 12.49% 74.98% | 47210 12.50% 87.47% | 47320 12.53% 100.00% +system.ruby.L1Cache_Controller.IS.Exclusive_Data::total 377763 +system.ruby.L1Cache_Controller.SS.Load | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.L1Cache_Controller.SS.Load::total 1 -system.ruby.L1Cache_Controller.SS.L1_to_L2 | 4391 11.77% 11.77% | 4934 13.23% 25.00% | 4841 12.98% 37.98% | 4629 12.41% 50.38% | 4379 11.74% 62.12% | 4778 12.81% 74.93% | 4436 11.89% 86.82% | 4915 13.18% 100.00% -system.ruby.L1Cache_Controller.SS.L1_to_L2::total 37303 -system.ruby.L1Cache_Controller.SS.Ack | 6760 12.16% 12.16% | 6850 12.32% 24.48% | 6884 12.38% 36.86% | 6878 12.37% 49.24% | 6979 12.55% 61.79% | 7194 12.94% 74.73% | 6892 12.40% 87.13% | 7157 12.87% 100.00% -system.ruby.L1Cache_Controller.SS.Ack::total 55594 -system.ruby.L1Cache_Controller.SS.Shared_Ack | 10 10.53% 10.53% | 13 13.68% 24.21% | 8 8.42% 32.63% | 8 8.42% 41.05% | 11 11.58% 52.63% | 10 10.53% 63.16% | 18 18.95% 82.11% | 17 17.89% 100.00% -system.ruby.L1Cache_Controller.SS.Shared_Ack::total 95 -system.ruby.L1Cache_Controller.SS.All_acks | 1220 12.28% 12.28% | 1207 12.15% 24.43% | 1244 12.52% 36.95% | 1265 12.73% 49.68% | 1214 12.22% 61.90% | 1317 13.26% 75.16% | 1235 12.43% 87.59% | 1233 12.41% 100.00% -system.ruby.L1Cache_Controller.SS.All_acks::total 9935 -system.ruby.L1Cache_Controller.SS.All_acks_no_sharers | 2048 12.38% 12.38% | 2046 12.36% 24.74% | 2009 12.14% 36.88% | 2056 12.42% 49.31% | 2094 12.65% 61.96% | 2123 12.83% 74.79% | 2071 12.52% 87.30% | 2101 12.70% 100.00% -system.ruby.L1Cache_Controller.SS.All_acks_no_sharers::total 16548 -system.ruby.L1Cache_Controller.OI.Load | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.OI.Load::total 1 -system.ruby.L1Cache_Controller.OI.Store | 0 0.00% 0.00% | 1 33.33% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 1 33.33% 66.67% | 0 0.00% 66.67% | 1 33.33% 100.00% -system.ruby.L1Cache_Controller.OI.Store::total 3 -system.ruby.L1Cache_Controller.OI.Other_GETX | 4 16.67% 16.67% | 3 12.50% 29.17% | 4 16.67% 45.83% | 3 12.50% 58.33% | 3 12.50% 70.83% | 3 12.50% 83.33% | 3 12.50% 95.83% | 1 4.17% 100.00% -system.ruby.L1Cache_Controller.OI.Other_GETX::total 24 -system.ruby.L1Cache_Controller.OI.Other_GETS | 0 0.00% 0.00% | 3 15.00% 15.00% | 3 15.00% 30.00% | 5 25.00% 55.00% | 1 5.00% 60.00% | 1 5.00% 65.00% | 1 5.00% 70.00% | 6 30.00% 100.00% -system.ruby.L1Cache_Controller.OI.Other_GETS::total 20 -system.ruby.L1Cache_Controller.OI.Merged_GETS | 4 20.00% 20.00% | 2 10.00% 30.00% | 2 10.00% 40.00% | 3 15.00% 55.00% | 1 5.00% 60.00% | 2 10.00% 70.00% | 3 15.00% 85.00% | 3 15.00% 100.00% -system.ruby.L1Cache_Controller.OI.Merged_GETS::total 20 -system.ruby.L1Cache_Controller.OI.Writeback_Ack | 1196 12.70% 12.70% | 1164 12.36% 25.06% | 1149 12.20% 37.26% | 1191 12.65% 49.91% | 1150 12.21% 62.12% | 1198 12.72% 74.84% | 1221 12.97% 87.81% | 1148 12.19% 100.00% -system.ruby.L1Cache_Controller.OI.Writeback_Ack::total 9417 -system.ruby.L1Cache_Controller.MI.Load | 13 10.57% 10.57% | 20 16.26% 26.83% | 18 14.63% 41.46% | 14 11.38% 52.85% | 11 8.94% 61.79% | 25 20.33% 82.11% | 9 7.32% 89.43% | 13 10.57% 100.00% -system.ruby.L1Cache_Controller.MI.Load::total 123 -system.ruby.L1Cache_Controller.MI.Store | 5 9.80% 9.80% | 3 5.88% 15.69% | 8 15.69% 31.37% | 3 5.88% 37.25% | 12 23.53% 60.78% | 10 19.61% 80.39% | 3 5.88% 86.27% | 7 13.73% 100.00% -system.ruby.L1Cache_Controller.MI.Store::total 51 -system.ruby.L1Cache_Controller.MI.Other_GETX | 162 11.43% 11.43% | 181 12.77% 24.21% | 181 12.77% 36.98% | 182 12.84% 49.82% | 184 12.99% 62.81% | 181 12.77% 75.58% | 156 11.01% 86.59% | 190 13.41% 100.00% -system.ruby.L1Cache_Controller.MI.Other_GETX::total 1417 -system.ruby.L1Cache_Controller.MI.Other_GETS | 315 12.90% 12.90% | 277 11.35% 24.25% | 281 11.51% 35.76% | 327 13.40% 49.16% | 292 11.96% 61.12% | 316 12.95% 74.07% | 342 14.01% 88.08% | 291 11.92% 100.00% -system.ruby.L1Cache_Controller.MI.Other_GETS::total 2441 -system.ruby.L1Cache_Controller.MI.Merged_GETS | 13 12.04% 12.04% | 13 12.04% 24.07% | 10 9.26% 33.33% | 5 4.63% 37.96% | 15 13.89% 51.85% | 12 11.11% 62.96% | 18 16.67% 79.63% | 22 20.37% 100.00% -system.ruby.L1Cache_Controller.MI.Merged_GETS::total 108 -system.ruby.L1Cache_Controller.MI.Writeback_Ack | 72897 12.55% 12.55% | 72530 12.49% 25.05% | 72652 12.51% 37.56% | 72680 12.52% 50.08% | 72470 12.48% 62.56% | 72355 12.46% 75.02% | 72681 12.52% 87.54% | 72370 12.46% 100.00% -system.ruby.L1Cache_Controller.MI.Writeback_Ack::total 580635 -system.ruby.L1Cache_Controller.II.Store | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% -system.ruby.L1Cache_Controller.II.Store::total 1 -system.ruby.L1Cache_Controller.II.Other_GETX | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 33.33% 33.33% | 0 0.00% 33.33% | 1 33.33% 66.67% | 1 33.33% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.II.Other_GETX::total 3 -system.ruby.L1Cache_Controller.II.Writeback_Ack | 166 11.53% 11.53% | 184 12.78% 24.31% | 185 12.85% 37.15% | 185 12.85% 50.00% | 187 12.99% 62.99% | 184 12.78% 75.76% | 158 10.97% 86.74% | 191 13.26% 100.00% -system.ruby.L1Cache_Controller.II.Writeback_Ack::total 1440 -system.ruby.L1Cache_Controller.II.Writeback_Nack | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.II.Writeback_Nack::total 1 -system.ruby.L1Cache_Controller.IT.Load | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.IT.Load::total 1 -system.ruby.L1Cache_Controller.IT.Store | 1 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.IT.Store::total 2 -system.ruby.L1Cache_Controller.IT.L1_to_L2 | 10 22.73% 22.73% | 0 0.00% 22.73% | 0 0.00% 22.73% | 7 15.91% 38.64% | 15 34.09% 72.73% | 7 15.91% 88.64% | 5 11.36% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.IT.L1_to_L2::total 44 -system.ruby.L1Cache_Controller.IT.Complete_L2_to_L1 | 2 20.00% 20.00% | 1 10.00% 30.00% | 0 0.00% 30.00% | 1 10.00% 40.00% | 3 30.00% 70.00% | 1 10.00% 80.00% | 1 10.00% 90.00% | 1 10.00% 100.00% +system.ruby.L1Cache_Controller.SS.L1_to_L2 | 5041 12.61% 12.61% | 5297 13.25% 25.86% | 4845 12.12% 37.98% | 4861 12.16% 50.14% | 5186 12.97% 63.12% | 4925 12.32% 75.44% | 4836 12.10% 87.53% | 4983 12.47% 100.00% +system.ruby.L1Cache_Controller.SS.L1_to_L2::total 39974 +system.ruby.L1Cache_Controller.SS.Ack | 7136 12.32% 12.32% | 7580 13.08% 25.40% | 7139 12.32% 37.72% | 7109 12.27% 49.99% | 7501 12.95% 62.94% | 7189 12.41% 75.35% | 7032 12.14% 87.49% | 7250 12.51% 100.00% +system.ruby.L1Cache_Controller.SS.Ack::total 57936 +system.ruby.L1Cache_Controller.SS.Shared_Ack | 11 9.02% 9.02% | 23 18.85% 27.87% | 17 13.93% 41.80% | 19 15.57% 57.38% | 17 13.93% 71.31% | 13 10.66% 81.97% | 13 10.66% 92.62% | 9 7.38% 100.00% +system.ruby.L1Cache_Controller.SS.Shared_Ack::total 122 +system.ruby.L1Cache_Controller.SS.All_acks | 1242 12.43% 12.43% | 1233 12.34% 24.77% | 1238 12.39% 37.16% | 1235 12.36% 49.52% | 1246 12.47% 61.99% | 1291 12.92% 74.91% | 1239 12.40% 87.31% | 1268 12.69% 100.00% +system.ruby.L1Cache_Controller.SS.All_acks::total 9992 +system.ruby.L1Cache_Controller.SS.All_acks_no_sharers | 2008 12.39% 12.39% | 2036 12.56% 24.95% | 2031 12.53% 37.48% | 1952 12.04% 49.52% | 2095 12.93% 62.45% | 2078 12.82% 75.27% | 1988 12.27% 87.54% | 2020 12.46% 100.00% +system.ruby.L1Cache_Controller.SS.All_acks_no_sharers::total 16208 +system.ruby.L1Cache_Controller.OI.Load | 0 0.00% 0.00% | 2 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.OI.Load::total 2 +system.ruby.L1Cache_Controller.OI.Other_GETX | 1 6.25% 6.25% | 1 6.25% 12.50% | 4 25.00% 37.50% | 2 12.50% 50.00% | 2 12.50% 62.50% | 2 12.50% 75.00% | 2 12.50% 87.50% | 2 12.50% 100.00% +system.ruby.L1Cache_Controller.OI.Other_GETX::total 16 +system.ruby.L1Cache_Controller.OI.Other_GETS | 2 7.41% 7.41% | 3 11.11% 18.52% | 5 18.52% 37.04% | 4 14.81% 51.85% | 3 11.11% 62.96% | 3 11.11% 74.07% | 2 7.41% 81.48% | 5 18.52% 100.00% +system.ruby.L1Cache_Controller.OI.Other_GETS::total 27 +system.ruby.L1Cache_Controller.OI.Merged_GETS | 4 16.67% 16.67% | 4 16.67% 33.33% | 5 20.83% 54.17% | 3 12.50% 66.67% | 1 4.17% 70.83% | 1 4.17% 75.00% | 3 12.50% 87.50% | 3 12.50% 100.00% +system.ruby.L1Cache_Controller.OI.Merged_GETS::total 24 +system.ruby.L1Cache_Controller.OI.Writeback_Ack | 1199 12.70% 12.70% | 1194 12.64% 25.34% | 1128 11.94% 37.28% | 1165 12.34% 49.62% | 1171 12.40% 62.02% | 1158 12.26% 74.28% | 1204 12.75% 87.03% | 1225 12.97% 100.00% +system.ruby.L1Cache_Controller.OI.Writeback_Ack::total 9444 +system.ruby.L1Cache_Controller.MI.Load | 15 12.82% 12.82% | 22 18.80% 31.62% | 10 8.55% 40.17% | 11 9.40% 49.57% | 19 16.24% 65.81% | 10 8.55% 74.36% | 12 10.26% 84.62% | 18 15.38% 100.00% +system.ruby.L1Cache_Controller.MI.Load::total 117 +system.ruby.L1Cache_Controller.MI.Store | 13 16.46% 16.46% | 7 8.86% 25.32% | 9 11.39% 36.71% | 4 5.06% 41.77% | 8 10.13% 51.90% | 14 17.72% 69.62% | 18 22.78% 92.41% | 6 7.59% 100.00% +system.ruby.L1Cache_Controller.MI.Store::total 79 +system.ruby.L1Cache_Controller.MI.Other_GETX | 197 13.47% 13.47% | 173 11.83% 25.31% | 170 11.63% 36.94% | 190 13.00% 49.93% | 203 13.89% 63.82% | 188 12.86% 76.68% | 151 10.33% 87.00% | 190 13.00% 100.00% +system.ruby.L1Cache_Controller.MI.Other_GETX::total 1462 +system.ruby.L1Cache_Controller.MI.Other_GETS | 348 13.58% 13.58% | 322 12.56% 26.14% | 310 12.10% 38.24% | 294 11.47% 49.71% | 337 13.15% 62.86% | 282 11.00% 73.86% | 343 13.38% 87.24% | 327 12.76% 100.00% +system.ruby.L1Cache_Controller.MI.Other_GETS::total 2563 +system.ruby.L1Cache_Controller.MI.Merged_GETS | 14 12.28% 12.28% | 17 14.91% 27.19% | 16 14.04% 41.23% | 14 12.28% 53.51% | 15 13.16% 66.67% | 16 14.04% 80.70% | 12 10.53% 91.23% | 10 8.77% 100.00% +system.ruby.L1Cache_Controller.MI.Merged_GETS::total 114 +system.ruby.L1Cache_Controller.MI.Writeback_Ack | 72569 12.48% 12.48% | 72904 12.54% 25.01% | 72891 12.53% 37.55% | 72442 12.46% 50.00% | 72864 12.53% 62.53% | 72649 12.49% 75.02% | 72638 12.49% 87.51% | 72642 12.49% 100.00% +system.ruby.L1Cache_Controller.MI.Writeback_Ack::total 581599 +system.ruby.L1Cache_Controller.II.Other_GETX | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 1 50.00% 100.00% +system.ruby.L1Cache_Controller.II.Other_GETX::total 2 +system.ruby.L1Cache_Controller.II.Writeback_Ack | 198 13.40% 13.40% | 174 11.77% 25.17% | 174 11.77% 36.94% | 192 12.99% 49.93% | 205 13.87% 63.80% | 190 12.86% 76.66% | 153 10.35% 87.01% | 192 12.99% 100.00% +system.ruby.L1Cache_Controller.II.Writeback_Ack::total 1478 +system.ruby.L1Cache_Controller.IT.Load | 1 16.67% 16.67% | 1 16.67% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 1 16.67% 50.00% | 0 0.00% 50.00% | 2 33.33% 83.33% | 1 16.67% 100.00% +system.ruby.L1Cache_Controller.IT.Load::total 6 +system.ruby.L1Cache_Controller.IT.L1_to_L2 | 0 0.00% 0.00% | 10 18.87% 18.87% | 0 0.00% 18.87% | 0 0.00% 18.87% | 7 13.21% 32.08% | 0 0.00% 32.08% | 34 64.15% 96.23% | 2 3.77% 100.00% +system.ruby.L1Cache_Controller.IT.L1_to_L2::total 53 +system.ruby.L1Cache_Controller.IT.Complete_L2_to_L1 | 1 10.00% 10.00% | 1 10.00% 20.00% | 1 10.00% 30.00% | 0 0.00% 30.00% | 2 20.00% 50.00% | 1 10.00% 60.00% | 1 10.00% 70.00% | 3 30.00% 100.00% system.ruby.L1Cache_Controller.IT.Complete_L2_to_L1::total 10 -system.ruby.L1Cache_Controller.ST.Load | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.ST.Load::total 1 -system.ruby.L1Cache_Controller.ST.Store | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 33.33% 33.33% | 2 66.67% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.ST.Load | 1 14.29% 14.29% | 2 28.57% 42.86% | 1 14.29% 57.14% | 1 14.29% 71.43% | 0 0.00% 71.43% | 2 28.57% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.ST.Load::total 7 +system.ruby.L1Cache_Controller.ST.Store | 0 0.00% 0.00% | 1 33.33% 33.33% | 0 0.00% 33.33% | 1 33.33% 66.67% | 1 33.33% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.L1Cache_Controller.ST.Store::total 3 -system.ruby.L1Cache_Controller.ST.L1_to_L2 | 9 25.71% 25.71% | 0 0.00% 25.71% | 7 20.00% 45.71% | 1 2.86% 48.57% | 8 22.86% 71.43% | 0 0.00% 71.43% | 8 22.86% 94.29% | 2 5.71% 100.00% -system.ruby.L1Cache_Controller.ST.L1_to_L2::total 35 -system.ruby.L1Cache_Controller.ST.Complete_L2_to_L1 | 1 7.14% 7.14% | 2 14.29% 21.43% | 2 14.29% 35.71% | 2 14.29% 50.00% | 4 28.57% 78.57% | 0 0.00% 78.57% | 1 7.14% 85.71% | 2 14.29% 100.00% -system.ruby.L1Cache_Controller.ST.Complete_L2_to_L1::total 14 -system.ruby.L1Cache_Controller.OT.Store | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_Controller.OT.Store::total 1 -system.ruby.L1Cache_Controller.OT.Complete_L2_to_L1 | 1 20.00% 20.00% | 0 0.00% 20.00% | 1 20.00% 40.00% | 0 0.00% 40.00% | 2 40.00% 80.00% | 0 0.00% 80.00% | 0 0.00% 80.00% | 1 20.00% 100.00% -system.ruby.L1Cache_Controller.OT.Complete_L2_to_L1::total 5 -system.ruby.L1Cache_Controller.MT.Load | 15 16.30% 16.30% | 8 8.70% 25.00% | 11 11.96% 36.96% | 13 14.13% 51.09% | 17 18.48% 69.57% | 8 8.70% 78.26% | 14 15.22% 93.48% | 6 6.52% 100.00% -system.ruby.L1Cache_Controller.MT.Load::total 92 -system.ruby.L1Cache_Controller.MT.Store | 10 15.38% 15.38% | 10 15.38% 30.77% | 6 9.23% 40.00% | 13 20.00% 60.00% | 6 9.23% 69.23% | 9 13.85% 83.08% | 8 12.31% 95.38% | 3 4.62% 100.00% -system.ruby.L1Cache_Controller.MT.Store::total 65 -system.ruby.L1Cache_Controller.MT.L1_to_L2 | 168 14.13% 14.13% | 216 18.17% 32.30% | 73 6.14% 38.44% | 172 14.47% 52.90% | 184 15.48% 68.38% | 141 11.86% 80.24% | 120 10.09% 90.33% | 115 9.67% 100.00% -system.ruby.L1Cache_Controller.MT.L1_to_L2::total 1189 -system.ruby.L1Cache_Controller.MT.Complete_L2_to_L1 | 42 13.55% 13.55% | 42 13.55% 27.10% | 30 9.68% 36.77% | 44 14.19% 50.97% | 45 14.52% 65.48% | 35 11.29% 76.77% | 39 12.58% 89.35% | 33 10.65% 100.00% -system.ruby.L1Cache_Controller.MT.Complete_L2_to_L1::total 310 -system.ruby.L1Cache_Controller.MMT.Load | 13 19.40% 19.40% | 7 10.45% 29.85% | 9 13.43% 43.28% | 7 10.45% 53.73% | 5 7.46% 61.19% | 8 11.94% 73.13% | 10 14.93% 88.06% | 8 11.94% 100.00% -system.ruby.L1Cache_Controller.MMT.Load::total 67 -system.ruby.L1Cache_Controller.MMT.Store | 6 17.14% 17.14% | 6 17.14% 34.29% | 3 8.57% 42.86% | 5 14.29% 57.14% | 4 11.43% 68.57% | 6 17.14% 85.71% | 3 8.57% 94.29% | 2 5.71% 100.00% -system.ruby.L1Cache_Controller.MMT.Store::total 35 -system.ruby.L1Cache_Controller.MMT.L1_to_L2 | 149 20.03% 20.03% | 46 6.18% 26.21% | 86 11.56% 37.77% | 85 11.42% 49.19% | 91 12.23% 61.42% | 136 18.28% 79.70% | 95 12.77% 92.47% | 56 7.53% 100.00% -system.ruby.L1Cache_Controller.MMT.L1_to_L2::total 744 -system.ruby.L1Cache_Controller.MMT.Complete_L2_to_L1 | 37 16.23% 16.23% | 35 15.35% 31.58% | 26 11.40% 42.98% | 28 12.28% 55.26% | 24 10.53% 65.79% | 29 12.72% 78.51% | 28 12.28% 90.79% | 21 9.21% 100.00% -system.ruby.L1Cache_Controller.MMT.Complete_L2_to_L1::total 228 -system.ruby.Directory_Controller.GETX 227092 0.00% 0.00% -system.ruby.Directory_Controller.GETS 409941 0.00% 0.00% -system.ruby.Directory_Controller.PUT 604133 0.00% 0.00% -system.ruby.Directory_Controller.Unblock 1440 0.00% 0.00% -system.ruby.Directory_Controller.UnblockS 26482 0.00% 0.00% -system.ruby.Directory_Controller.UnblockM 600822 0.00% 0.00% -system.ruby.Directory_Controller.Writeback_Clean 8072 0.00% 0.00% -system.ruby.Directory_Controller.Writeback_Dirty 1345 0.00% 0.00% -system.ruby.Directory_Controller.Writeback_Exclusive_Clean 361114 0.00% 0.00% -system.ruby.Directory_Controller.Writeback_Exclusive_Dirty 219521 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Data 607003 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Ack 220866 0.00% 0.00% -system.ruby.Directory_Controller.All_Unblocks 990 0.00% 0.00% -system.ruby.Directory_Controller.NX.GETX 86 0.00% 0.00% -system.ruby.Directory_Controller.NX.GETS 100 0.00% 0.00% -system.ruby.Directory_Controller.NX.PUT 10824 0.00% 0.00% -system.ruby.Directory_Controller.NO.GETX 7097 0.00% 0.00% -system.ruby.Directory_Controller.NO.GETS 12034 0.00% 0.00% -system.ruby.Directory_Controller.NO.PUT 580691 0.00% 0.00% -system.ruby.Directory_Controller.O.GETX 9322 0.00% 0.00% -system.ruby.Directory_Controller.O.GETS 16870 0.00% 0.00% -system.ruby.Directory_Controller.E.GETX 206773 0.00% 0.00% -system.ruby.Directory_Controller.E.GETS 374058 0.00% 0.00% -system.ruby.Directory_Controller.E.PUT 1 0.00% 0.00% -system.ruby.Directory_Controller.NO_B.GETX 541 0.00% 0.00% -system.ruby.Directory_Controller.NO_B.GETS 990 0.00% 0.00% -system.ruby.Directory_Controller.NO_B.PUT 12396 0.00% 0.00% -system.ruby.Directory_Controller.NO_B.UnblockS 8550 0.00% 0.00% -system.ruby.Directory_Controller.NO_B.UnblockM 599363 0.00% 0.00% -system.ruby.Directory_Controller.NO_B_X.GETX 1 0.00% 0.00% -system.ruby.Directory_Controller.NO_B_X.PUT 17 0.00% 0.00% -system.ruby.Directory_Controller.NO_B_X.UnblockS 31 0.00% 0.00% -system.ruby.Directory_Controller.NO_B_X.UnblockM 510 0.00% 0.00% -system.ruby.Directory_Controller.NO_B_S.GETS 1 0.00% 0.00% -system.ruby.Directory_Controller.NO_B_S.PUT 28 0.00% 0.00% -system.ruby.Directory_Controller.NO_B_S.UnblockS 41 0.00% 0.00% -system.ruby.Directory_Controller.NO_B_S.UnblockM 949 0.00% 0.00% -system.ruby.Directory_Controller.NO_B_S_W.GETX 2 0.00% 0.00% -system.ruby.Directory_Controller.NO_B_S_W.GETS 4 0.00% 0.00% -system.ruby.Directory_Controller.NO_B_S_W.PUT 105 0.00% 0.00% -system.ruby.Directory_Controller.NO_B_S_W.UnblockS 991 0.00% 0.00% -system.ruby.Directory_Controller.NO_B_S_W.All_Unblocks 990 0.00% 0.00% -system.ruby.Directory_Controller.O_B.GETX 9 0.00% 0.00% -system.ruby.Directory_Controller.O_B.GETS 21 0.00% 0.00% -system.ruby.Directory_Controller.O_B.UnblockS 16869 0.00% 0.00% -system.ruby.Directory_Controller.NO_B_W.GETX 1892 0.00% 0.00% -system.ruby.Directory_Controller.NO_B_W.GETS 3482 0.00% 0.00% -system.ruby.Directory_Controller.NO_B_W.Memory_Data 590133 0.00% 0.00% -system.ruby.Directory_Controller.O_B_W.GETX 63 0.00% 0.00% -system.ruby.Directory_Controller.O_B_W.GETS 87 0.00% 0.00% -system.ruby.Directory_Controller.O_B_W.Memory_Data 16870 0.00% 0.00% -system.ruby.Directory_Controller.WB.GETX 1268 0.00% 0.00% -system.ruby.Directory_Controller.WB.GETS 2222 0.00% 0.00% -system.ruby.Directory_Controller.WB.PUT 71 0.00% 0.00% -system.ruby.Directory_Controller.WB.Unblock 1440 0.00% 0.00% -system.ruby.Directory_Controller.WB.Writeback_Clean 8072 0.00% 0.00% -system.ruby.Directory_Controller.WB.Writeback_Dirty 1345 0.00% 0.00% -system.ruby.Directory_Controller.WB.Writeback_Exclusive_Clean 361114 0.00% 0.00% -system.ruby.Directory_Controller.WB.Writeback_Exclusive_Dirty 219521 0.00% 0.00% -system.ruby.Directory_Controller.WB_O_W.GETS 1 0.00% 0.00% -system.ruby.Directory_Controller.WB_O_W.Memory_Ack 1345 0.00% 0.00% -system.ruby.Directory_Controller.WB_E_W.GETX 38 0.00% 0.00% -system.ruby.Directory_Controller.WB_E_W.GETS 71 0.00% 0.00% -system.ruby.Directory_Controller.WB_E_W.Memory_Ack 219521 0.00% 0.00% +system.ruby.L1Cache_Controller.ST.L1_to_L2 | 8 8.08% 8.08% | 21 21.21% 29.29% | 6 6.06% 35.35% | 20 20.20% 55.56% | 26 26.26% 81.82% | 7 7.07% 88.89% | 11 11.11% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_Controller.ST.L1_to_L2::total 99 +system.ruby.L1Cache_Controller.ST.Complete_L2_to_L1 | 2 7.14% 7.14% | 7 25.00% 32.14% | 2 7.14% 39.29% | 6 21.43% 60.71% | 4 14.29% 75.00% | 3 10.71% 85.71% | 2 7.14% 92.86% | 2 7.14% 100.00% +system.ruby.L1Cache_Controller.ST.Complete_L2_to_L1::total 28 +system.ruby.L1Cache_Controller.OT.Load | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 33.33% 33.33% | 0 0.00% 33.33% | 1 33.33% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 1 33.33% 100.00% +system.ruby.L1Cache_Controller.OT.Load::total 3 +system.ruby.L1Cache_Controller.OT.L1_to_L2 | 10 27.03% 27.03% | 0 0.00% 27.03% | 1 2.70% 29.73% | 0 0.00% 29.73% | 20 54.05% 83.78% | 0 0.00% 83.78% | 0 0.00% 83.78% | 6 16.22% 100.00% +system.ruby.L1Cache_Controller.OT.L1_to_L2::total 37 +system.ruby.L1Cache_Controller.OT.Complete_L2_to_L1 | 1 11.11% 11.11% | 1 11.11% 22.22% | 2 22.22% 44.44% | 0 0.00% 44.44% | 2 22.22% 66.67% | 0 0.00% 66.67% | 2 22.22% 88.89% | 1 11.11% 100.00% +system.ruby.L1Cache_Controller.OT.Complete_L2_to_L1::total 9 +system.ruby.L1Cache_Controller.MT.Load | 8 7.48% 7.48% | 12 11.21% 18.69% | 12 11.21% 29.91% | 21 19.63% 49.53% | 13 12.15% 61.68% | 9 8.41% 70.09% | 14 13.08% 83.18% | 18 16.82% 100.00% +system.ruby.L1Cache_Controller.MT.Load::total 107 +system.ruby.L1Cache_Controller.MT.Store | 6 13.04% 13.04% | 4 8.70% 21.74% | 5 10.87% 32.61% | 9 19.57% 52.17% | 8 17.39% 69.57% | 6 13.04% 82.61% | 7 15.22% 97.83% | 1 2.17% 100.00% +system.ruby.L1Cache_Controller.MT.Store::total 46 +system.ruby.L1Cache_Controller.MT.L1_to_L2 | 162 14.36% 14.36% | 102 9.04% 23.40% | 101 8.95% 32.36% | 198 17.55% 49.91% | 105 9.31% 59.22% | 124 10.99% 70.21% | 181 16.05% 86.26% | 155 13.74% 100.00% +system.ruby.L1Cache_Controller.MT.L1_to_L2::total 1128 +system.ruby.L1Cache_Controller.MT.Complete_L2_to_L1 | 39 12.30% 12.30% | 35 11.04% 23.34% | 34 10.73% 34.07% | 45 14.20% 48.26% | 36 11.36% 59.62% | 34 10.73% 70.35% | 43 13.56% 83.91% | 51 16.09% 100.00% +system.ruby.L1Cache_Controller.MT.Complete_L2_to_L1::total 317 +system.ruby.L1Cache_Controller.MMT.Load | 12 18.75% 18.75% | 5 7.81% 26.56% | 7 10.94% 37.50% | 5 7.81% 45.31% | 10 15.62% 60.94% | 7 10.94% 71.88% | 10 15.62% 87.50% | 8 12.50% 100.00% +system.ruby.L1Cache_Controller.MMT.Load::total 64 +system.ruby.L1Cache_Controller.MMT.Store | 5 13.51% 13.51% | 8 21.62% 35.14% | 3 8.11% 43.24% | 2 5.41% 48.65% | 3 8.11% 56.76% | 8 21.62% 78.38% | 6 16.22% 94.59% | 2 5.41% 100.00% +system.ruby.L1Cache_Controller.MMT.Store::total 37 +system.ruby.L1Cache_Controller.MMT.L1_to_L2 | 86 13.21% 13.21% | 96 14.75% 27.96% | 55 8.45% 36.41% | 38 5.84% 42.24% | 69 10.60% 52.84% | 110 16.90% 69.74% | 148 22.73% 92.47% | 49 7.53% 100.00% +system.ruby.L1Cache_Controller.MMT.L1_to_L2::total 651 +system.ruby.L1Cache_Controller.MMT.Complete_L2_to_L1 | 24 12.06% 12.06% | 21 10.55% 22.61% | 24 12.06% 34.67% | 19 9.55% 44.22% | 28 14.07% 58.29% | 24 12.06% 70.35% | 37 18.59% 88.94% | 22 11.06% 100.00% +system.ruby.L1Cache_Controller.MMT.Complete_L2_to_L1::total 199 ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt index 35e569592..6ebb8a63f 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt @@ -1,48 +1,48 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.007640 # Number of seconds simulated -sim_ticks 7640346 # Number of ticks simulated -final_tick 7640346 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.007583 # Number of seconds simulated +sim_ticks 7582589 # Number of ticks simulated +final_tick 7582589 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 121940 # Simulator tick rate (ticks/s) -host_mem_usage 688424 # Number of bytes of host memory used -host_seconds 62.66 # Real time elapsed on the host +host_tick_rate 210657 # Simulator tick rate (ticks/s) +host_mem_usage 700452 # Number of bytes of host memory used +host_seconds 36.00 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks -system.mem_ctrls.bytes_read::ruby.dir_cntrl0 39630976 # Number of bytes read from this memory -system.mem_ctrls.bytes_read::total 39630976 # Number of bytes read from this memory -system.mem_ctrls.bytes_written::ruby.dir_cntrl0 39629440 # Number of bytes written to this memory -system.mem_ctrls.bytes_written::total 39629440 # Number of bytes written to this memory -system.mem_ctrls.num_reads::ruby.dir_cntrl0 619234 # Number of read requests responded to by this memory -system.mem_ctrls.num_reads::total 619234 # Number of read requests responded to by this memory -system.mem_ctrls.num_writes::ruby.dir_cntrl0 619210 # Number of write requests responded to by this memory -system.mem_ctrls.num_writes::total 619210 # Number of write requests responded to by this memory -system.mem_ctrls.bw_read::ruby.dir_cntrl0 5187065612 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_read::total 5187065612 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::ruby.dir_cntrl0 5186864574 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::total 5186864574 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_total::ruby.dir_cntrl0 10373930186 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.bw_total::total 10373930186 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.readReqs 619241 # Number of read requests accepted -system.mem_ctrls.writeReqs 619210 # Number of write requests accepted -system.mem_ctrls.readBursts 619241 # Number of DRAM read bursts, including those serviced by the write queue -system.mem_ctrls.writeBursts 619210 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrls.bytesReadDRAM 38759744 # Total number of bytes read from DRAM -system.mem_ctrls.bytesReadWrQ 871680 # Total number of bytes read from write queue -system.mem_ctrls.bytesWritten 39127168 # Total number of bytes written to DRAM -system.mem_ctrls.bytesReadSys 39631424 # Total read bytes from the system interface side -system.mem_ctrls.bytesWrittenSys 39629440 # Total written bytes from the system interface side -system.mem_ctrls.servicedByWrQ 13620 # Number of DRAM read bursts serviced by the write queue -system.mem_ctrls.mergedWrBursts 7808 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.bytes_read::ruby.dir_cntrl0 39656192 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 39656192 # Number of bytes read from this memory +system.mem_ctrls.bytes_written::ruby.dir_cntrl0 39654720 # Number of bytes written to this memory +system.mem_ctrls.bytes_written::total 39654720 # Number of bytes written to this memory +system.mem_ctrls.num_reads::ruby.dir_cntrl0 619628 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 619628 # Number of read requests responded to by this memory +system.mem_ctrls.num_writes::ruby.dir_cntrl0 619605 # Number of write requests responded to by this memory +system.mem_ctrls.num_writes::total 619605 # Number of write requests responded to by this memory +system.mem_ctrls.bw_read::ruby.dir_cntrl0 5229901291 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 5229901291 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::ruby.dir_cntrl0 5229707162 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::total 5229707162 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::ruby.dir_cntrl0 10459608453 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 10459608453 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.readReqs 619636 # Number of read requests accepted +system.mem_ctrls.writeReqs 619605 # Number of write requests accepted +system.mem_ctrls.readBursts 619636 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.writeBursts 619605 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrls.bytesReadDRAM 38799872 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 856832 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 39161920 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadSys 39656704 # Total read bytes from the system interface side +system.mem_ctrls.bytesWrittenSys 39654720 # Total written bytes from the system interface side +system.mem_ctrls.servicedByWrQ 13388 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 7653 # Number of DRAM write bursts merged with an existing one system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.mem_ctrls.perBankRdBursts::0 75930 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::1 75800 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::2 75762 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::3 75572 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::4 76043 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::5 75649 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::6 75203 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::7 75662 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::0 76050 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::1 75867 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::2 75889 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 76027 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 75490 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::5 75499 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::6 75763 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 75663 # Per bank write bursts system.mem_ctrls.perBankRdBursts::8 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::9 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::10 0 # Per bank write bursts @@ -51,14 +51,14 @@ system.mem_ctrls.perBankRdBursts::12 0 # Pe system.mem_ctrls.perBankRdBursts::13 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::14 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::15 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::0 76645 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::1 76483 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::2 76463 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::3 76307 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::4 76789 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::5 76366 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::6 75891 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::7 76418 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 76733 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::1 76551 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::2 76672 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 76745 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 76164 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 76242 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::6 76436 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::7 76362 # Per bank write bursts system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::10 0 # Per bank write bursts @@ -68,53 +68,53 @@ system.mem_ctrls.perBankWrBursts::13 0 # Pe system.mem_ctrls.perBankWrBursts::14 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry -system.mem_ctrls.numWrRetry 1386 # Number of times write queue was full causing retry -system.mem_ctrls.totGap 7640332 # Total gap between requests +system.mem_ctrls.numWrRetry 1316 # Number of times write queue was full causing retry +system.mem_ctrls.totGap 7582575 # Total gap between requests system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::6 619241 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 619636 # Read request sizes (log2) system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::6 619210 # Write request sizes (log2) -system.mem_ctrls.rdQLenPdf::0 39 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::1 371 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::2 1410 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::3 4295 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::4 10092 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::5 18847 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::6 28680 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::7 38557 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::8 46760 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::9 50653 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::10 50719 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::11 46401 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::12 41225 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::13 35682 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::14 30672 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::15 27887 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::16 25992 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::17 24547 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::18 23522 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::19 22441 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::20 20725 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::21 18091 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::22 14601 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::23 10683 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::24 6775 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::25 3686 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::26 1571 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::27 534 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::28 134 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::29 24 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::30 5 # What read queue length does an incoming req see +system.mem_ctrls.writePktSize::6 619605 # Write request sizes (log2) +system.mem_ctrls.rdQLenPdf::0 32 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::1 346 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::2 1534 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::3 4652 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::4 10530 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::5 19183 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::6 29616 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::7 40220 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::8 47540 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::9 50473 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::10 49842 # What read queue length does an incoming req see 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14793 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::23 10821 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::24 6989 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::25 3723 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::26 1662 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::27 594 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::28 130 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::29 20 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::30 2 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see system.mem_ctrls.wrQLenPdf::0 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::1 1 # What write queue length does an incoming req see @@ -147,514 +147,519 @@ system.mem_ctrls.wrQLenPdf::27 1 # Wh system.mem_ctrls.wrQLenPdf::28 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::29 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::30 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::31 3 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::32 43 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::33 177 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::34 596 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::35 1371 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::36 2500 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::37 4217 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::38 6791 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::39 10074 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::40 14120 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::41 17497 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::42 20411 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::43 22971 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::44 24800 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::45 25688 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::46 26455 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::47 27360 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::48 29089 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::49 30783 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::50 32098 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::51 33250 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::52 34420 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::53 35549 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::54 38553 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::55 56835 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::56 47905 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::57 21239 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::58 16122 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::59 12076 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::60 8373 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::61 4889 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::62 2426 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::63 2690 # What write queue length does an incoming req see -system.mem_ctrls.bytesPerActivate::samples 244065 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::mean 319.119448 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::gmean 243.936703 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::stdev 225.750518 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::0-127 33066 13.55% 13.55% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::128-255 74051 30.34% 43.89% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::256-383 47584 19.50% 63.39% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::384-511 35781 14.66% 78.05% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::512-639 24395 10.00% 88.04% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::640-767 14385 5.89% 93.93% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::768-895 7558 3.10% 97.03% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::896-1023 3779 1.55% 98.58% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::1024-1151 3466 1.42% 100.00% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::total 244065 # Bytes accessed per row activation -system.mem_ctrls.rdPerTurnAround::samples 38211 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::mean 15.849389 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::gmean 8.733627 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::stdev 11.471953 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::0-3 12664 33.14% 33.14% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::4-7 1717 4.49% 37.64% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::8-11 411 1.08% 38.71% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::12-15 217 0.57% 39.28% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::16-19 3256 8.52% 47.80% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::20-23 6962 18.22% 66.02% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::24-27 6191 16.20% 82.22% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::28-31 5489 14.36% 96.59% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::32-35 1268 3.32% 99.91% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::36-39 35 0.09% 100.00% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::80-83 1 0.00% 100.00% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::total 38211 # Reads before turning the bus around for writes -system.mem_ctrls.wrPerTurnAround::samples 38210 # Writes before turning the bus around for reads +system.mem_ctrls.wrQLenPdf::31 15 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::32 57 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::33 237 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::34 662 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::35 1409 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::36 2720 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::37 4680 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::38 7358 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::39 11234 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::40 14859 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::41 18277 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::42 20903 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::43 23502 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::44 25176 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::45 26140 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::46 27165 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::47 28236 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::48 29242 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::49 30684 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::50 31940 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::51 34045 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::52 34472 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::53 35205 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::54 37597 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::55 55809 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::56 46546 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::57 20844 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::58 15539 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::59 11583 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::60 6918 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::61 4170 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::62 2108 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::63 2589 # What write queue length does an incoming req see +system.mem_ctrls.bytesPerActivate::samples 245657 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 317.354620 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 242.734089 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 224.484514 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 33363 13.58% 13.58% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 75184 30.61% 44.19% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 48043 19.56% 63.74% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 35710 14.54% 78.28% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 24482 9.97% 88.25% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 14306 5.82% 94.07% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 7560 3.08% 97.15% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 3712 1.51% 98.66% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 3297 1.34% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 245657 # Bytes accessed per row activation +system.mem_ctrls.rdPerTurnAround::samples 38245 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::mean 15.851693 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::gmean 8.811529 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::stdev 11.405114 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::0-3 12517 32.73% 32.73% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::4-7 1776 4.64% 37.37% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::8-11 493 1.29% 38.66% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::12-15 184 0.48% 39.14% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::16-19 3224 8.43% 47.57% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::20-23 7216 18.87% 66.44% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::24-27 6295 16.46% 82.90% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::28-31 5266 13.77% 96.67% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::32-35 1235 3.23% 99.90% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::36-39 38 0.10% 100.00% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::68-71 1 0.00% 100.00% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::total 38245 # Reads before turning the bus around for writes +system.mem_ctrls.wrPerTurnAround::samples 38244 # Writes before turning the bus around for reads system.mem_ctrls.wrPerTurnAround::mean 16 # Writes before turning the bus around for reads system.mem_ctrls.wrPerTurnAround::gmean 16.000000 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::16 38210 100.00% 100.00% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::total 38210 # Writes before turning the bus around for reads -system.mem_ctrls.totQLat 113136166 # Total ticks spent queuing -system.mem_ctrls.totMemAccLat 124642965 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrls.totBusLat 3028105 # Total ticks spent in databus transfers -system.mem_ctrls.avgQLat 186.81 # Average queueing delay per DRAM burst +system.mem_ctrls.wrPerTurnAround::16 38244 100.00% 100.00% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::total 38244 # Writes before turning the bus around for reads +system.mem_ctrls.totQLat 111772725 # Total ticks spent queuing +system.mem_ctrls.totMemAccLat 123291437 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.totBusLat 3031240 # Total ticks spent in databus transfers +system.mem_ctrls.avgQLat 184.37 # Average queueing delay per DRAM burst system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst -system.mem_ctrls.avgMemAccLat 205.81 # Average memory access latency per DRAM burst -system.mem_ctrls.avgRdBW 5073.04 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrls.avgWrBW 5121.13 # Average achieved write bandwidth in MiByte/s -system.mem_ctrls.avgRdBWSys 5187.12 # Average system read bandwidth in MiByte/s -system.mem_ctrls.avgWrBWSys 5186.86 # Average system write bandwidth in MiByte/s +system.mem_ctrls.avgMemAccLat 203.37 # Average memory access latency per DRAM burst +system.mem_ctrls.avgRdBW 5116.97 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 5164.72 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 5229.97 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 5229.71 # Average system write bandwidth in MiByte/s system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrls.busUtil 79.64 # Data bus utilization in percentage -system.mem_ctrls.busUtilRead 39.63 # Data bus utilization in percentage for reads -system.mem_ctrls.busUtilWrite 40.01 # Data bus utilization in percentage for writes -system.mem_ctrls.avgRdQLen 18.22 # Average read queue length when enqueuing -system.mem_ctrls.avgWrQLen 53.30 # Average write queue length when enqueuing -system.mem_ctrls.readRowHits 371319 # Number of row buffer hits during reads -system.mem_ctrls.writeRowHits 601592 # Number of row buffer hits during writes -system.mem_ctrls.readRowHitRate 61.31 # Row buffer hit rate for reads -system.mem_ctrls.writeRowHitRate 98.40 # Row buffer hit rate for writes -system.mem_ctrls.avgGap 6.17 # Average gap between requests -system.mem_ctrls.pageHitRate 79.94 # Row buffer hit rate, read and write combined -system.mem_ctrls.memoryStateTime::IDLE 12 # Time in different power states -system.mem_ctrls.memoryStateTime::REF 255060 # Time in different power states -system.mem_ctrls.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls.memoryStateTime::ACT 7383304 # Time in different power states -system.mem_ctrls.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrls.actEnergy::0 1844632440 # Energy for activate commands per rank (pJ) -system.mem_ctrls.actEnergy::1 0 # Energy for activate commands per rank (pJ) -system.mem_ctrls.preEnergy::0 1024795800 # Energy for precharge commands per rank (pJ) -system.mem_ctrls.preEnergy::1 0 # Energy for precharge commands per rank (pJ) -system.mem_ctrls.readEnergy::0 7555941120 # Energy for read commands per rank (pJ) -system.mem_ctrls.readEnergy::1 0 # Energy for read commands per rank (pJ) -system.mem_ctrls.writeEnergy::0 6336921600 # Energy for write commands per rank (pJ) -system.mem_ctrls.writeEnergy::1 0 # Energy for write commands per rank (pJ) -system.mem_ctrls.refreshEnergy::0 498897360 # Energy for refresh commands per rank (pJ) -system.mem_ctrls.refreshEnergy::1 498897360 # Energy for refresh commands per rank (pJ) -system.mem_ctrls.actBackEnergy::0 5201932860 # Energy for active background per rank (pJ) -system.mem_ctrls.actBackEnergy::1 165066984 # Energy for active background per rank (pJ) -system.mem_ctrls.preBackEnergy::0 19918200 # Energy for precharge background per rank (pJ) -system.mem_ctrls.preBackEnergy::1 4438221600 # Energy for precharge background per rank (pJ) -system.mem_ctrls.totalEnergy::0 22483039380 # Total energy per rank (pJ) -system.mem_ctrls.totalEnergy::1 5102185944 # Total energy per rank (pJ) -system.mem_ctrls.averagePower::0 2943.437268 # Core power per rank (mW) -system.mem_ctrls.averagePower::1 667.968596 # Core power per rank (mW) +system.mem_ctrls.busUtil 80.33 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 39.98 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 40.35 # Data bus utilization in percentage for writes +system.mem_ctrls.avgRdQLen 18.20 # Average read queue length when enqueuing +system.mem_ctrls.avgWrQLen 53.15 # Average write queue length when enqueuing +system.mem_ctrls.readRowHits 370717 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 601771 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 61.15 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate 98.34 # Row buffer hit rate for writes +system.mem_ctrls.avgGap 6.12 # Average gap between requests +system.mem_ctrls.pageHitRate 79.83 # Row buffer hit rate, read and write combined +system.mem_ctrls_0.actEnergy 1855594440 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 1030885800 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 7559160960 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 6338580480 # Energy for write commands per rank (pJ) +system.mem_ctrls_0.refreshEnergy 494828880 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_0.actBackEnergy 5163405192 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 16345200 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.totalEnergy 22458800952 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 2964.435559 # Core power per rank (mW) +system.mem_ctrls_0.memoryStateTime::IDLE 12 # Time in different power states +system.mem_ctrls_0.memoryStateTime::REF 252980 # Time in different power states +system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 7323102 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls_1.actEnergy 0 # Energy for activate commands per rank (pJ) +system.mem_ctrls_1.preEnergy 0 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_1.readEnergy 0 # Energy for read commands per rank (pJ) +system.mem_ctrls_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls_1.refreshEnergy 494828880 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_1.actBackEnergy 163720872 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 4401999600 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.totalEnergy 5060549352 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 667.969023 # Core power per rank (mW) +system.mem_ctrls_1.memoryStateTime::IDLE 7323058 # Time in different power states +system.mem_ctrls_1.memoryStateTime::REF 252980 # Time in different power states +system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 0 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu_clk_domain.clock 1 # Clock period in ticks +system.cpu0.num_reads 99415 # number of read accesses completed +system.cpu0.num_writes 55396 # number of write accesses completed +system.cpu0.num_copies 0 # number of copy accesses completed +system.cpu1.num_reads 99989 # number of read accesses completed +system.cpu1.num_writes 55766 # number of write accesses completed +system.cpu1.num_copies 0 # number of copy accesses completed +system.cpu2.num_reads 100000 # number of read accesses completed +system.cpu2.num_writes 55829 # number of write accesses completed +system.cpu2.num_copies 0 # number of copy accesses completed +system.cpu3.num_reads 99767 # number of read accesses completed +system.cpu3.num_writes 55101 # number of write accesses completed +system.cpu3.num_copies 0 # number of copy accesses completed +system.cpu4.num_reads 99087 # number of read accesses completed +system.cpu4.num_writes 55181 # number of write accesses completed +system.cpu4.num_copies 0 # number of copy accesses completed +system.cpu5.num_reads 99334 # number of read accesses completed +system.cpu5.num_writes 55288 # number of write accesses completed +system.cpu5.num_copies 0 # number of copy accesses completed +system.cpu6.num_reads 98895 # number of read accesses completed +system.cpu6.num_writes 55228 # number of write accesses completed +system.cpu6.num_copies 0 # number of copy accesses completed +system.cpu7.num_reads 99279 # number of read accesses completed +system.cpu7.num_writes 55473 # number of write accesses completed +system.cpu7.num_copies 0 # number of copy accesses completed system.ruby.clk_domain.clock 1 # Clock period in ticks system.ruby.delayHist::bucket_size 32 # delay histogram for all message system.ruby.delayHist::max_bucket 319 # delay histogram for all message -system.ruby.delayHist::samples 1259370 # delay histogram for all message -system.ruby.delayHist::mean 2.196570 # delay histogram for all message -system.ruby.delayHist::stdev 7.715497 # delay histogram for all message -system.ruby.delayHist | 1242104 98.63% 98.63% | 10923 0.87% 99.50% | 5617 0.45% 99.94% | 569 0.05% 99.99% | 127 0.01% 100.00% | 28 0.00% 100.00% | 2 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message -system.ruby.delayHist::total 1259370 # delay histogram for all message +system.ruby.delayHist::samples 1259803 # delay histogram for all message +system.ruby.delayHist::mean 2.138829 # delay histogram for all message +system.ruby.delayHist::stdev 7.497358 # delay histogram for all message +system.ruby.delayHist | 1243420 98.70% 98.70% | 10426 0.83% 99.53% | 5324 0.42% 99.95% | 510 0.04% 99.99% | 106 0.01% 100.00% | 17 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message +system.ruby.delayHist::total 1259803 # delay histogram for all message system.ruby.outstanding_req_hist::bucket_size 2 system.ruby.outstanding_req_hist::max_bucket 19 -system.ruby.outstanding_req_hist::samples 627888 -system.ruby.outstanding_req_hist::mean 15.998458 -system.ruby.outstanding_req_hist::gmean 15.997196 -system.ruby.outstanding_req_hist::stdev 0.125735 -system.ruby.outstanding_req_hist | 8 0.00% 0.00% | 16 0.00% 0.00% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.02% | 24 0.00% 0.02% | 627760 99.98% 100.00% | 0 0.00% 100.00% -system.ruby.outstanding_req_hist::total 627888 +system.ruby.outstanding_req_hist::samples 628107 +system.ruby.outstanding_req_hist::mean 15.998448 +system.ruby.outstanding_req_hist::gmean 15.997186 +system.ruby.outstanding_req_hist::stdev 0.125758 +system.ruby.outstanding_req_hist | 8 0.00% 0.00% | 16 0.00% 0.00% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.02% | 31 0.00% 0.02% | 627972 99.98% 100.00% | 0 0.00% 100.00% +system.ruby.outstanding_req_hist::total 628107 system.ruby.latency_hist::bucket_size 512 system.ruby.latency_hist::max_bucket 5119 -system.ruby.latency_hist::samples 627760 -system.ruby.latency_hist::mean 1557.693635 -system.ruby.latency_hist::gmean 1534.797226 -system.ruby.latency_hist::stdev 267.213644 -system.ruby.latency_hist | 66 0.01% 0.01% | 7337 1.17% 1.18% | 304531 48.51% 49.69% | 288472 45.95% 95.64% | 27150 4.32% 99.97% | 204 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.latency_hist::total 627760 +system.ruby.latency_hist::samples 627979 +system.ruby.latency_hist::mean 1545.382761 +system.ruby.latency_hist::gmean 1522.867536 +system.ruby.latency_hist::stdev 263.957857 +system.ruby.latency_hist | 68 0.01% 0.01% | 7984 1.27% 1.28% | 316387 50.38% 51.66% | 279515 44.51% 96.17% | 23839 3.80% 99.97% | 186 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.latency_hist::total 627979 system.ruby.miss_latency_hist::bucket_size 512 system.ruby.miss_latency_hist::max_bucket 5119 -system.ruby.miss_latency_hist::samples 627760 -system.ruby.miss_latency_hist::mean 1557.693635 -system.ruby.miss_latency_hist::gmean 1534.797226 -system.ruby.miss_latency_hist::stdev 267.213644 -system.ruby.miss_latency_hist | 66 0.01% 0.01% | 7337 1.17% 1.18% | 304531 48.51% 49.69% | 288472 45.95% 95.64% | 27150 4.32% 99.97% | 204 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.miss_latency_hist::total 627760 -system.ruby.L1Cache.incomplete_times 8531 -system.ruby.Directory.incomplete_times 619225 -system.ruby.l1_cntrl4.cacheMemory.demand_hits 0 # Number of cache demand hits -system.ruby.l1_cntrl4.cacheMemory.demand_misses 78662 # Number of cache demand misses -system.ruby.l1_cntrl4.cacheMemory.demand_accesses 78662 # Number of cache demand accesses -system.cpu_clk_domain.clock 1 # Clock period in ticks -system.ruby.l1_cntrl5.cacheMemory.demand_hits 0 # Number of cache demand hits -system.ruby.l1_cntrl5.cacheMemory.demand_misses 78584 # Number of cache demand misses -system.ruby.l1_cntrl5.cacheMemory.demand_accesses 78584 # Number of cache demand accesses -system.ruby.l1_cntrl6.cacheMemory.demand_hits 0 # Number of cache demand hits -system.ruby.l1_cntrl6.cacheMemory.demand_misses 78465 # Number of cache demand misses -system.ruby.l1_cntrl6.cacheMemory.demand_accesses 78465 # Number of cache demand accesses -system.ruby.l1_cntrl7.cacheMemory.demand_hits 0 # Number of cache demand hits -system.ruby.l1_cntrl7.cacheMemory.demand_misses 78643 # Number of cache demand misses -system.ruby.l1_cntrl7.cacheMemory.demand_accesses 78643 # Number of cache demand accesses +system.ruby.miss_latency_hist::samples 627979 +system.ruby.miss_latency_hist::mean 1545.382761 +system.ruby.miss_latency_hist::gmean 1522.867536 +system.ruby.miss_latency_hist::stdev 263.957857 +system.ruby.miss_latency_hist | 68 0.01% 0.01% | 7984 1.27% 1.28% | 316387 50.38% 51.66% | 279515 44.51% 96.17% | 23839 3.80% 99.97% | 186 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.miss_latency_hist::total 627979 +system.ruby.L1Cache.incomplete_times 8356 +system.ruby.Directory.incomplete_times 619619 system.ruby.l1_cntrl0.cacheMemory.demand_hits 0 # Number of cache demand hits -system.ruby.l1_cntrl0.cacheMemory.demand_misses 78250 # Number of cache demand misses -system.ruby.l1_cntrl0.cacheMemory.demand_accesses 78250 # Number of cache demand accesses -system.ruby.network.routers0.percent_links_utilized 5.136551 -system.ruby.network.routers0.msg_count.Control::2 78250 -system.ruby.network.routers0.msg_count.Data::2 77666 -system.ruby.network.routers0.msg_count.Response_Data::4 79314 -system.ruby.network.routers0.msg_count.Writeback_Control::3 78731 -system.ruby.network.routers0.msg_bytes.Control::2 626000 -system.ruby.network.routers0.msg_bytes.Data::2 5591952 -system.ruby.network.routers0.msg_bytes.Response_Data::4 5710608 -system.ruby.network.routers0.msg_bytes.Writeback_Control::3 629848 +system.ruby.l1_cntrl0.cacheMemory.demand_misses 78629 # Number of cache demand misses +system.ruby.l1_cntrl0.cacheMemory.demand_accesses 78629 # Number of cache demand accesses system.ruby.l1_cntrl1.cacheMemory.demand_hits 0 # Number of cache demand hits -system.ruby.l1_cntrl1.cacheMemory.demand_misses 78453 # Number of cache demand misses -system.ruby.l1_cntrl1.cacheMemory.demand_accesses 78453 # Number of cache demand accesses -system.ruby.network.routers1.percent_links_utilized 5.150235 -system.ruby.network.routers1.msg_count.Control::2 78453 -system.ruby.network.routers1.msg_count.Data::2 77872 -system.ruby.network.routers1.msg_count.Response_Data::4 79526 -system.ruby.network.routers1.msg_count.Writeback_Control::3 78948 -system.ruby.network.routers1.msg_bytes.Control::2 627624 -system.ruby.network.routers1.msg_bytes.Data::2 5606784 -system.ruby.network.routers1.msg_bytes.Response_Data::4 5725872 -system.ruby.network.routers1.msg_bytes.Writeback_Control::3 631584 +system.ruby.l1_cntrl1.cacheMemory.demand_misses 78616 # Number of cache demand misses +system.ruby.l1_cntrl1.cacheMemory.demand_accesses 78616 # Number of cache demand accesses system.ruby.l1_cntrl2.cacheMemory.demand_hits 0 # Number of cache demand hits -system.ruby.l1_cntrl2.cacheMemory.demand_misses 78358 # Number of cache demand misses -system.ruby.l1_cntrl2.cacheMemory.demand_accesses 78358 # Number of cache demand accesses -system.ruby.network.routers2.percent_links_utilized 5.143052 -system.ruby.network.routers2.msg_count.Control::2 78358 -system.ruby.network.routers2.msg_count.Data::2 77773 -system.ruby.network.routers2.msg_count.Response_Data::4 79406 -system.ruby.network.routers2.msg_count.Writeback_Control::3 78822 -system.ruby.network.routers2.msg_bytes.Control::2 626864 -system.ruby.network.routers2.msg_bytes.Data::2 5599656 -system.ruby.network.routers2.msg_bytes.Response_Data::4 5717232 -system.ruby.network.routers2.msg_bytes.Writeback_Control::3 630576 +system.ruby.l1_cntrl2.cacheMemory.demand_misses 78776 # Number of cache demand misses +system.ruby.l1_cntrl2.cacheMemory.demand_accesses 78776 # Number of cache demand accesses system.ruby.l1_cntrl3.cacheMemory.demand_hits 0 # Number of cache demand hits -system.ruby.l1_cntrl3.cacheMemory.demand_misses 78360 # Number of cache demand misses -system.ruby.l1_cntrl3.cacheMemory.demand_accesses 78360 # Number of cache demand accesses -system.ruby.network.routers3.percent_links_utilized 5.142804 -system.ruby.network.routers3.msg_count.Control::2 78360 -system.ruby.network.routers3.msg_count.Data::2 77812 -system.ruby.network.routers3.msg_count.Response_Data::4 79359 -system.ruby.network.routers3.msg_count.Writeback_Control::3 78813 -system.ruby.network.routers3.msg_bytes.Control::2 626880 -system.ruby.network.routers3.msg_bytes.Data::2 5602464 -system.ruby.network.routers3.msg_bytes.Response_Data::4 5713848 -system.ruby.network.routers3.msg_bytes.Writeback_Control::3 630504 -system.ruby.network.routers4.percent_links_utilized 5.163339 -system.ruby.network.routers4.msg_count.Control::2 78660 -system.ruby.network.routers4.msg_count.Data::2 78072 -system.ruby.network.routers4.msg_count.Response_Data::4 79727 -system.ruby.network.routers4.msg_count.Writeback_Control::3 79138 -system.ruby.network.routers4.msg_bytes.Control::2 629280 -system.ruby.network.routers4.msg_bytes.Data::2 5621184 -system.ruby.network.routers4.msg_bytes.Response_Data::4 5740344 -system.ruby.network.routers4.msg_bytes.Writeback_Control::3 633104 -system.ruby.network.routers5.percent_links_utilized 5.158644 -system.ruby.network.routers5.msg_count.Control::2 78584 -system.ruby.network.routers5.msg_count.Data::2 77942 -system.ruby.network.routers5.msg_count.Response_Data::4 79713 -system.ruby.network.routers5.msg_count.Writeback_Control::3 79074 -system.ruby.network.routers5.msg_bytes.Control::2 628672 -system.ruby.network.routers5.msg_bytes.Data::2 5611824 -system.ruby.network.routers5.msg_bytes.Response_Data::4 5739336 -system.ruby.network.routers5.msg_bytes.Writeback_Control::3 632592 -system.ruby.network.routers6.percent_links_utilized 5.151013 -system.ruby.network.routers6.msg_count.Control::2 78465 -system.ruby.network.routers6.msg_count.Data::2 77892 -system.ruby.network.routers6.msg_count.Response_Data::4 79530 -system.ruby.network.routers6.msg_count.Writeback_Control::3 78958 -system.ruby.network.routers6.msg_bytes.Control::2 627720 -system.ruby.network.routers6.msg_bytes.Data::2 5608224 -system.ruby.network.routers6.msg_bytes.Response_Data::4 5726160 -system.ruby.network.routers6.msg_bytes.Writeback_Control::3 631664 -system.ruby.network.routers7.percent_links_utilized 5.162335 -system.ruby.network.routers7.msg_count.Control::2 78643 -system.ruby.network.routers7.msg_count.Data::2 78052 -system.ruby.network.routers7.msg_count.Response_Data::4 79716 -system.ruby.network.routers7.msg_count.Writeback_Control::3 79126 -system.ruby.network.routers7.msg_bytes.Control::2 629144 -system.ruby.network.routers7.msg_bytes.Data::2 5619744 -system.ruby.network.routers7.msg_bytes.Response_Data::4 5739552 -system.ruby.network.routers7.msg_bytes.Writeback_Control::3 633008 -system.ruby.network.routers8.percent_links_utilized 40.705513 -system.ruby.network.routers8.msg_count.Control::2 627773 -system.ruby.network.routers8.msg_count.Data::2 623080 -system.ruby.network.routers8.msg_count.Response_Data::4 619230 -system.ruby.network.routers8.msg_count.Writeback_Control::3 631610 -system.ruby.network.routers8.msg_bytes.Control::2 5022184 -system.ruby.network.routers8.msg_bytes.Data::2 44861760 -system.ruby.network.routers8.msg_bytes.Response_Data::4 44584560 -system.ruby.network.routers8.msg_bytes.Writeback_Control::3 5052880 -system.ruby.network.routers9.percent_links_utilized 9.101498 -system.ruby.network.routers9.msg_count.Control::2 627773 -system.ruby.network.routers9.msg_count.Data::2 623081 -system.ruby.network.routers9.msg_count.Response_Data::4 627760 -system.ruby.network.routers9.msg_count.Writeback_Control::3 631610 -system.ruby.network.routers9.msg_bytes.Control::2 5022184 -system.ruby.network.routers9.msg_bytes.Data::2 44861832 -system.ruby.network.routers9.msg_bytes.Response_Data::4 45198720 -system.ruby.network.routers9.msg_bytes.Writeback_Control::3 5052880 -system.ruby.network.msg_count.Control 1883319 -system.ruby.network.msg_count.Data 1869242 -system.ruby.network.msg_count.Response_Data 1883281 -system.ruby.network.msg_count.Writeback_Control 1894830 -system.ruby.network.msg_byte.Control 15066552 -system.ruby.network.msg_byte.Data 134585424 -system.ruby.network.msg_byte.Response_Data 135596232 -system.ruby.network.msg_byte.Writeback_Control 15158640 +system.ruby.l1_cntrl3.cacheMemory.demand_misses 78236 # Number of cache demand misses +system.ruby.l1_cntrl3.cacheMemory.demand_accesses 78236 # Number of cache demand accesses +system.ruby.l1_cntrl4.cacheMemory.demand_hits 0 # Number of cache demand hits +system.ruby.l1_cntrl4.cacheMemory.demand_misses 78211 # Number of cache demand misses +system.ruby.l1_cntrl4.cacheMemory.demand_accesses 78211 # Number of cache demand accesses +system.ruby.l1_cntrl5.cacheMemory.demand_hits 0 # Number of cache demand hits +system.ruby.l1_cntrl5.cacheMemory.demand_misses 78653 # Number of cache demand misses +system.ruby.l1_cntrl5.cacheMemory.demand_accesses 78653 # Number of cache demand accesses +system.ruby.l1_cntrl6.cacheMemory.demand_hits 0 # Number of cache demand hits +system.ruby.l1_cntrl6.cacheMemory.demand_misses 78454 # Number of cache demand misses +system.ruby.l1_cntrl6.cacheMemory.demand_accesses 78454 # Number of cache demand accesses +system.ruby.l1_cntrl7.cacheMemory.demand_hits 0 # Number of cache demand hits +system.ruby.l1_cntrl7.cacheMemory.demand_misses 78418 # Number of cache demand misses +system.ruby.l1_cntrl7.cacheMemory.demand_accesses 78418 # Number of cache demand accesses system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.cpu0.num_reads 99347 # number of read accesses completed -system.cpu0.num_writes 55561 # number of write accesses completed -system.cpu0.num_copies 0 # number of copy accesses completed -system.cpu1.num_reads 99174 # number of read accesses completed -system.cpu1.num_writes 55699 # number of write accesses completed -system.cpu1.num_copies 0 # number of copy accesses completed -system.cpu2.num_reads 100001 # number of read accesses completed -system.cpu2.num_writes 55396 # number of write accesses completed -system.cpu2.num_copies 0 # number of copy accesses completed -system.cpu3.num_reads 99891 # number of read accesses completed -system.cpu3.num_writes 55171 # number of write accesses completed -system.cpu3.num_copies 0 # number of copy accesses completed -system.cpu4.num_reads 99714 # number of read accesses completed -system.cpu4.num_writes 55703 # number of write accesses completed -system.cpu4.num_copies 0 # number of copy accesses completed -system.cpu5.num_reads 99497 # number of read accesses completed -system.cpu5.num_writes 55733 # number of write accesses completed -system.cpu5.num_copies 0 # number of copy accesses completed -system.cpu6.num_reads 99258 # number of read accesses completed -system.cpu6.num_writes 55713 # number of write accesses completed -system.cpu6.num_copies 0 # number of copy accesses completed -system.cpu7.num_reads 99613 # number of read accesses completed -system.cpu7.num_writes 55877 # number of write accesses completed -system.cpu7.num_copies 0 # number of copy accesses completed -system.ruby.network.routers0.throttle0.link_utilization 5.123930 -system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 78249 -system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 78731 -system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 5633928 -system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 629848 -system.ruby.network.routers0.throttle1.link_utilization 5.149171 -system.ruby.network.routers0.throttle1.msg_count.Control::2 78250 -system.ruby.network.routers0.throttle1.msg_count.Data::2 77666 -system.ruby.network.routers0.throttle1.msg_count.Response_Data::4 1065 -system.ruby.network.routers0.throttle1.msg_bytes.Control::2 626000 -system.ruby.network.routers0.throttle1.msg_bytes.Data::2 5591952 -system.ruby.network.routers0.throttle1.msg_bytes.Response_Data::4 76680 -system.ruby.network.routers1.throttle0.link_utilization 5.137189 -system.ruby.network.routers1.throttle0.msg_count.Response_Data::4 78450 -system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::3 78948 -system.ruby.network.routers1.throttle0.msg_bytes.Response_Data::4 5648400 -system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::3 631584 -system.ruby.network.routers1.throttle1.link_utilization 5.163281 -system.ruby.network.routers1.throttle1.msg_count.Control::2 78453 -system.ruby.network.routers1.throttle1.msg_count.Data::2 77872 -system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 1076 -system.ruby.network.routers1.throttle1.msg_bytes.Control::2 627624 -system.ruby.network.routers1.throttle1.msg_bytes.Data::2 5606784 -system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 77472 -system.ruby.network.routers2.throttle0.link_utilization 5.130867 -system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 78357 -system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 78822 -system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 5641704 -system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 630576 -system.ruby.network.routers2.throttle1.link_utilization 5.155238 -system.ruby.network.routers2.throttle1.msg_count.Control::2 78358 -system.ruby.network.routers2.throttle1.msg_count.Data::2 77773 -system.ruby.network.routers2.throttle1.msg_count.Response_Data::4 1049 -system.ruby.network.routers2.throttle1.msg_bytes.Control::2 626864 -system.ruby.network.routers2.throttle1.msg_bytes.Data::2 5599656 -system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::4 75528 -system.ruby.network.routers3.throttle0.link_utilization 5.130887 -system.ruby.network.routers3.throttle0.msg_count.Response_Data::4 78358 -system.ruby.network.routers3.throttle0.msg_count.Writeback_Control::3 78813 -system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::4 5641776 -system.ruby.network.routers3.throttle0.msg_bytes.Writeback_Control::3 630504 -system.ruby.network.routers3.throttle1.link_utilization 5.154721 -system.ruby.network.routers3.throttle1.msg_count.Control::2 78360 -system.ruby.network.routers3.throttle1.msg_count.Data::2 77812 -system.ruby.network.routers3.throttle1.msg_count.Response_Data::4 1001 -system.ruby.network.routers3.throttle1.msg_bytes.Control::2 626880 -system.ruby.network.routers3.throttle1.msg_bytes.Data::2 5602464 -system.ruby.network.routers3.throttle1.msg_bytes.Response_Data::4 72072 -system.ruby.network.routers4.throttle0.link_utilization 5.150742 -system.ruby.network.routers4.throttle0.msg_count.Response_Data::4 78659 -system.ruby.network.routers4.throttle0.msg_count.Writeback_Control::3 79138 -system.ruby.network.routers4.throttle0.msg_bytes.Response_Data::4 5663448 -system.ruby.network.routers4.throttle0.msg_bytes.Writeback_Control::3 633104 -system.ruby.network.routers4.throttle1.link_utilization 5.175937 -system.ruby.network.routers4.throttle1.msg_count.Control::2 78660 -system.ruby.network.routers4.throttle1.msg_count.Data::2 78072 -system.ruby.network.routers4.throttle1.msg_count.Response_Data::4 1068 -system.ruby.network.routers4.throttle1.msg_bytes.Control::2 629280 -system.ruby.network.routers4.throttle1.msg_bytes.Data::2 5621184 -system.ruby.network.routers4.throttle1.msg_bytes.Response_Data::4 76896 -system.ruby.network.routers5.throttle0.link_utilization 5.145729 -system.ruby.network.routers5.throttle0.msg_count.Response_Data::4 78581 -system.ruby.network.routers5.throttle0.msg_count.Writeback_Control::3 79074 -system.ruby.network.routers5.throttle0.msg_bytes.Response_Data::4 5657832 -system.ruby.network.routers5.throttle0.msg_bytes.Writeback_Control::3 632592 -system.ruby.network.routers5.throttle1.link_utilization 5.171559 -system.ruby.network.routers5.throttle1.msg_count.Control::2 78584 -system.ruby.network.routers5.throttle1.msg_count.Data::2 77942 -system.ruby.network.routers5.throttle1.msg_count.Response_Data::4 1132 -system.ruby.network.routers5.throttle1.msg_bytes.Control::2 628672 -system.ruby.network.routers5.throttle1.msg_bytes.Data::2 5611824 -system.ruby.network.routers5.throttle1.msg_bytes.Response_Data::4 81504 -system.ruby.network.routers6.throttle0.link_utilization 5.138079 -system.ruby.network.routers6.throttle0.msg_count.Response_Data::4 78464 -system.ruby.network.routers6.throttle0.msg_count.Writeback_Control::3 78958 -system.ruby.network.routers6.throttle0.msg_bytes.Response_Data::4 5649408 -system.ruby.network.routers6.throttle0.msg_bytes.Writeback_Control::3 631664 -system.ruby.network.routers6.throttle1.link_utilization 5.163948 -system.ruby.network.routers6.throttle1.msg_count.Control::2 78465 -system.ruby.network.routers6.throttle1.msg_count.Data::2 77892 -system.ruby.network.routers6.throttle1.msg_count.Response_Data::4 1066 -system.ruby.network.routers6.throttle1.msg_bytes.Control::2 627720 -system.ruby.network.routers6.throttle1.msg_bytes.Data::2 5608224 -system.ruby.network.routers6.throttle1.msg_bytes.Response_Data::4 76752 -system.ruby.network.routers7.throttle0.link_utilization 5.149662 -system.ruby.network.routers7.throttle0.msg_count.Response_Data::4 78642 -system.ruby.network.routers7.throttle0.msg_count.Writeback_Control::3 79126 -system.ruby.network.routers7.throttle0.msg_bytes.Response_Data::4 5662224 -system.ruby.network.routers7.throttle0.msg_bytes.Writeback_Control::3 633008 -system.ruby.network.routers7.throttle1.link_utilization 5.175008 -system.ruby.network.routers7.throttle1.msg_count.Control::2 78643 -system.ruby.network.routers7.throttle1.msg_count.Data::2 78052 -system.ruby.network.routers7.throttle1.msg_count.Response_Data::4 1074 -system.ruby.network.routers7.throttle1.msg_bytes.Control::2 629144 -system.ruby.network.routers7.throttle1.msg_bytes.Data::2 5619744 -system.ruby.network.routers7.throttle1.msg_bytes.Response_Data::4 77328 -system.ruby.network.routers8.throttle0.link_utilization 40.806352 -system.ruby.network.routers8.throttle0.msg_count.Control::2 627773 -system.ruby.network.routers8.throttle0.msg_count.Data::2 623080 -system.ruby.network.routers8.throttle0.msg_bytes.Control::2 5022184 -system.ruby.network.routers8.throttle0.msg_bytes.Data::2 44861760 -system.ruby.network.routers8.throttle1.link_utilization 40.604673 -system.ruby.network.routers8.throttle1.msg_count.Response_Data::4 619230 -system.ruby.network.routers8.throttle1.msg_count.Writeback_Control::3 631610 -system.ruby.network.routers8.throttle1.msg_bytes.Response_Data::4 44584560 -system.ruby.network.routers8.throttle1.msg_bytes.Writeback_Control::3 5052880 -system.ruby.network.routers9.throttle0.link_utilization 5.123930 -system.ruby.network.routers9.throttle0.msg_count.Response_Data::4 78249 -system.ruby.network.routers9.throttle0.msg_count.Writeback_Control::3 78731 -system.ruby.network.routers9.throttle0.msg_bytes.Response_Data::4 5633928 -system.ruby.network.routers9.throttle0.msg_bytes.Writeback_Control::3 629848 -system.ruby.network.routers9.throttle1.link_utilization 5.137189 -system.ruby.network.routers9.throttle1.msg_count.Response_Data::4 78450 -system.ruby.network.routers9.throttle1.msg_count.Writeback_Control::3 78948 -system.ruby.network.routers9.throttle1.msg_bytes.Response_Data::4 5648400 -system.ruby.network.routers9.throttle1.msg_bytes.Writeback_Control::3 631584 -system.ruby.network.routers9.throttle2.link_utilization 5.130887 -system.ruby.network.routers9.throttle2.msg_count.Response_Data::4 78357 -system.ruby.network.routers9.throttle2.msg_count.Writeback_Control::3 78822 -system.ruby.network.routers9.throttle2.msg_bytes.Response_Data::4 5641704 -system.ruby.network.routers9.throttle2.msg_bytes.Writeback_Control::3 630576 -system.ruby.network.routers9.throttle3.link_utilization 5.130887 -system.ruby.network.routers9.throttle3.msg_count.Response_Data::4 78358 -system.ruby.network.routers9.throttle3.msg_count.Writeback_Control::3 78813 -system.ruby.network.routers9.throttle3.msg_bytes.Response_Data::4 5641776 -system.ruby.network.routers9.throttle3.msg_bytes.Writeback_Control::3 630504 -system.ruby.network.routers9.throttle4.link_utilization 5.150742 -system.ruby.network.routers9.throttle4.msg_count.Response_Data::4 78659 -system.ruby.network.routers9.throttle4.msg_count.Writeback_Control::3 79138 -system.ruby.network.routers9.throttle4.msg_bytes.Response_Data::4 5663448 -system.ruby.network.routers9.throttle4.msg_bytes.Writeback_Control::3 633104 -system.ruby.network.routers9.throttle5.link_utilization 5.145729 -system.ruby.network.routers9.throttle5.msg_count.Response_Data::4 78581 -system.ruby.network.routers9.throttle5.msg_count.Writeback_Control::3 79074 -system.ruby.network.routers9.throttle5.msg_bytes.Response_Data::4 5657832 -system.ruby.network.routers9.throttle5.msg_bytes.Writeback_Control::3 632592 -system.ruby.network.routers9.throttle6.link_utilization 5.138079 -system.ruby.network.routers9.throttle6.msg_count.Response_Data::4 78464 -system.ruby.network.routers9.throttle6.msg_count.Writeback_Control::3 78958 -system.ruby.network.routers9.throttle6.msg_bytes.Response_Data::4 5649408 -system.ruby.network.routers9.throttle6.msg_bytes.Writeback_Control::3 631664 -system.ruby.network.routers9.throttle7.link_utilization 5.149662 -system.ruby.network.routers9.throttle7.msg_count.Response_Data::4 78642 -system.ruby.network.routers9.throttle7.msg_count.Writeback_Control::3 79126 -system.ruby.network.routers9.throttle7.msg_bytes.Response_Data::4 5662224 -system.ruby.network.routers9.throttle7.msg_bytes.Writeback_Control::3 633008 -system.ruby.network.routers9.throttle8.link_utilization 40.806378 -system.ruby.network.routers9.throttle8.msg_count.Control::2 627773 -system.ruby.network.routers9.throttle8.msg_count.Data::2 623081 -system.ruby.network.routers9.throttle8.msg_bytes.Control::2 5022184 -system.ruby.network.routers9.throttle8.msg_bytes.Data::2 44861832 +system.ruby.network.routers0.percent_links_utilized 5.200734 +system.ruby.network.routers0.msg_count.Control::2 78629 +system.ruby.network.routers0.msg_count.Data::2 78049 +system.ruby.network.routers0.msg_count.Response_Data::4 79691 +system.ruby.network.routers0.msg_count.Writeback_Control::3 79112 +system.ruby.network.routers0.msg_bytes.Control::2 629032 +system.ruby.network.routers0.msg_bytes.Data::2 5619528 +system.ruby.network.routers0.msg_bytes.Response_Data::4 5737752 +system.ruby.network.routers0.msg_bytes.Writeback_Control::3 632896 +system.ruby.network.routers1.percent_links_utilized 5.199646 +system.ruby.network.routers1.msg_count.Control::2 78616 +system.ruby.network.routers1.msg_count.Data::2 78080 +system.ruby.network.routers1.msg_count.Response_Data::4 79627 +system.ruby.network.routers1.msg_count.Writeback_Control::3 79092 +system.ruby.network.routers1.msg_bytes.Control::2 628928 +system.ruby.network.routers1.msg_bytes.Data::2 5621760 +system.ruby.network.routers1.msg_bytes.Response_Data::4 5733144 +system.ruby.network.routers1.msg_bytes.Writeback_Control::3 632736 +system.ruby.network.routers2.percent_links_utilized 5.209992 +system.ruby.network.routers2.msg_count.Control::2 78776 +system.ruby.network.routers2.msg_count.Data::2 78168 +system.ruby.network.routers2.msg_count.Response_Data::4 79853 +system.ruby.network.routers2.msg_count.Writeback_Control::3 79247 +system.ruby.network.routers2.msg_bytes.Control::2 630208 +system.ruby.network.routers2.msg_bytes.Data::2 5628096 +system.ruby.network.routers2.msg_bytes.Response_Data::4 5749416 +system.ruby.network.routers2.msg_bytes.Writeback_Control::3 633976 +system.ruby.network.routers3.percent_links_utilized 5.174657 +system.ruby.network.routers3.msg_count.Control::2 78236 +system.ruby.network.routers3.msg_count.Data::2 77624 +system.ruby.network.routers3.msg_count.Response_Data::4 79325 +system.ruby.network.routers3.msg_count.Writeback_Control::3 78715 +system.ruby.network.routers3.msg_bytes.Control::2 625888 +system.ruby.network.routers3.msg_bytes.Data::2 5588928 +system.ruby.network.routers3.msg_bytes.Response_Data::4 5711400 +system.ruby.network.routers3.msg_bytes.Writeback_Control::3 629720 +system.ruby.network.routers4.percent_links_utilized 5.172053 +system.ruby.network.routers4.msg_count.Control::2 78211 +system.ruby.network.routers4.msg_count.Data::2 77629 +system.ruby.network.routers4.msg_count.Response_Data::4 79241 +system.ruby.network.routers4.msg_count.Writeback_Control::3 78661 +system.ruby.network.routers4.msg_bytes.Control::2 625688 +system.ruby.network.routers4.msg_bytes.Data::2 5589288 +system.ruby.network.routers4.msg_bytes.Response_Data::4 5705352 +system.ruby.network.routers4.msg_bytes.Writeback_Control::3 629288 +system.ruby.network.routers5.percent_links_utilized 5.201822 +system.ruby.network.routers5.msg_count.Control::2 78653 +system.ruby.network.routers5.msg_count.Data::2 78120 +system.ruby.network.routers5.msg_count.Response_Data::4 79653 +system.ruby.network.routers5.msg_count.Writeback_Control::3 79121 +system.ruby.network.routers5.msg_bytes.Control::2 629224 +system.ruby.network.routers5.msg_bytes.Data::2 5624640 +system.ruby.network.routers5.msg_bytes.Response_Data::4 5735016 +system.ruby.network.routers5.msg_bytes.Writeback_Control::3 632968 +system.ruby.network.routers6.percent_links_utilized 5.189062 +system.ruby.network.routers6.msg_count.Control::2 78454 +system.ruby.network.routers6.msg_count.Data::2 77910 +system.ruby.network.routers6.msg_count.Response_Data::4 79476 +system.ruby.network.routers6.msg_count.Writeback_Control::3 78933 +system.ruby.network.routers6.msg_bytes.Control::2 627632 +system.ruby.network.routers6.msg_bytes.Data::2 5609520 +system.ruby.network.routers6.msg_bytes.Response_Data::4 5722272 +system.ruby.network.routers6.msg_bytes.Writeback_Control::3 631464 +system.ruby.network.routers7.percent_links_utilized 5.188175 +system.ruby.network.routers7.msg_count.Control::2 78418 +system.ruby.network.routers7.msg_count.Data::2 77890 +system.ruby.network.routers7.msg_count.Response_Data::4 79469 +system.ruby.network.routers7.msg_count.Writeback_Control::3 78943 +system.ruby.network.routers7.msg_bytes.Control::2 627344 +system.ruby.network.routers7.msg_bytes.Data::2 5608080 +system.ruby.network.routers7.msg_bytes.Response_Data::4 5721768 +system.ruby.network.routers7.msg_bytes.Writeback_Control::3 631544 +system.ruby.network.routers8.percent_links_utilized 41.040267 +system.ruby.network.routers8.msg_count.Control::2 627993 +system.ruby.network.routers8.msg_count.Data::2 623470 +system.ruby.network.routers8.msg_count.Response_Data::4 619624 +system.ruby.network.routers8.msg_count.Writeback_Control::3 631825 +system.ruby.network.routers8.msg_bytes.Control::2 5023944 +system.ruby.network.routers8.msg_bytes.Data::2 44889840 +system.ruby.network.routers8.msg_bytes.Response_Data::4 44612928 +system.ruby.network.routers8.msg_bytes.Writeback_Control::3 5054600 +system.ruby.network.routers9.percent_links_utilized 9.175156 +system.ruby.network.routers9.msg_count.Control::2 627993 +system.ruby.network.routers9.msg_count.Data::2 623470 +system.ruby.network.routers9.msg_count.Response_Data::4 627979 +system.ruby.network.routers9.msg_count.Writeback_Control::3 631825 +system.ruby.network.routers9.msg_bytes.Control::2 5023944 +system.ruby.network.routers9.msg_bytes.Data::2 44889840 +system.ruby.network.routers9.msg_bytes.Response_Data::4 45214488 +system.ruby.network.routers9.msg_bytes.Writeback_Control::3 5054600 +system.ruby.network.msg_count.Control 1883979 +system.ruby.network.msg_count.Data 1870410 +system.ruby.network.msg_count.Response_Data 1883938 +system.ruby.network.msg_count.Writeback_Control 1895474 +system.ruby.network.msg_byte.Control 15071832 +system.ruby.network.msg_byte.Data 134669520 +system.ruby.network.msg_byte.Response_Data 135643536 +system.ruby.network.msg_byte.Writeback_Control 15163792 +system.ruby.network.routers0.throttle0.link_utilization 5.187964 +system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 78628 +system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 79112 +system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 5661216 +system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 632896 +system.ruby.network.routers0.throttle1.link_utilization 5.213503 +system.ruby.network.routers0.throttle1.msg_count.Control::2 78629 +system.ruby.network.routers0.throttle1.msg_count.Data::2 78049 +system.ruby.network.routers0.throttle1.msg_count.Response_Data::4 1063 +system.ruby.network.routers0.throttle1.msg_bytes.Control::2 629032 +system.ruby.network.routers0.throttle1.msg_bytes.Data::2 5619528 +system.ruby.network.routers0.throttle1.msg_bytes.Response_Data::4 76536 +system.ruby.network.routers1.throttle0.link_utilization 5.186942 +system.ruby.network.routers1.throttle0.msg_count.Response_Data::4 78613 +system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::3 79092 +system.ruby.network.routers1.throttle0.msg_bytes.Response_Data::4 5660136 +system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::3 632736 +system.ruby.network.routers1.throttle1.link_utilization 5.212349 +system.ruby.network.routers1.throttle1.msg_count.Control::2 78616 +system.ruby.network.routers1.throttle1.msg_count.Data::2 78080 +system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 1014 +system.ruby.network.routers1.throttle1.msg_bytes.Control::2 628928 +system.ruby.network.routers1.throttle1.msg_bytes.Data::2 5621760 +system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 73008 +system.ruby.network.routers2.throttle0.link_utilization 5.197499 +system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 78774 +system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 79247 +system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 5671728 +system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 633976 +system.ruby.network.routers2.throttle1.link_utilization 5.222484 +system.ruby.network.routers2.throttle1.msg_count.Control::2 78776 +system.ruby.network.routers2.throttle1.msg_count.Data::2 78168 +system.ruby.network.routers2.throttle1.msg_count.Response_Data::4 1079 +system.ruby.network.routers2.throttle1.msg_bytes.Control::2 630208 +system.ruby.network.routers2.throttle1.msg_bytes.Data::2 5628096 +system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::4 77688 +system.ruby.network.routers3.throttle0.link_utilization 5.161964 +system.ruby.network.routers3.throttle0.msg_count.Response_Data::4 78234 +system.ruby.network.routers3.throttle0.msg_count.Writeback_Control::3 78715 +system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::4 5632848 +system.ruby.network.routers3.throttle0.msg_bytes.Writeback_Control::3 629720 +system.ruby.network.routers3.throttle1.link_utilization 5.187351 +system.ruby.network.routers3.throttle1.msg_count.Control::2 78236 +system.ruby.network.routers3.throttle1.msg_count.Data::2 77624 +system.ruby.network.routers3.throttle1.msg_count.Response_Data::4 1091 +system.ruby.network.routers3.throttle1.msg_bytes.Control::2 625888 +system.ruby.network.routers3.throttle1.msg_bytes.Data::2 5588928 +system.ruby.network.routers3.throttle1.msg_bytes.Response_Data::4 78552 +system.ruby.network.routers4.throttle0.link_utilization 5.160124 +system.ruby.network.routers4.throttle0.msg_count.Response_Data::4 78209 +system.ruby.network.routers4.throttle0.msg_count.Writeback_Control::3 78661 +system.ruby.network.routers4.throttle0.msg_bytes.Response_Data::4 5631048 +system.ruby.network.routers4.throttle0.msg_bytes.Writeback_Control::3 629288 +system.ruby.network.routers4.throttle1.link_utilization 5.183981 +system.ruby.network.routers4.throttle1.msg_count.Control::2 78211 +system.ruby.network.routers4.throttle1.msg_count.Data::2 77629 +system.ruby.network.routers4.throttle1.msg_count.Response_Data::4 1032 +system.ruby.network.routers4.throttle1.msg_bytes.Control::2 625688 +system.ruby.network.routers4.throttle1.msg_bytes.Data::2 5589288 +system.ruby.network.routers4.throttle1.msg_bytes.Response_Data::4 74304 +system.ruby.network.routers5.throttle0.link_utilization 5.189448 +system.ruby.network.routers5.throttle0.msg_count.Response_Data::4 78652 +system.ruby.network.routers5.throttle0.msg_count.Writeback_Control::3 79121 +system.ruby.network.routers5.throttle0.msg_bytes.Response_Data::4 5662944 +system.ruby.network.routers5.throttle0.msg_bytes.Writeback_Control::3 632968 +system.ruby.network.routers5.throttle1.link_utilization 5.214195 +system.ruby.network.routers5.throttle1.msg_count.Control::2 78653 +system.ruby.network.routers5.throttle1.msg_count.Data::2 78120 +system.ruby.network.routers5.throttle1.msg_count.Response_Data::4 1001 +system.ruby.network.routers5.throttle1.msg_bytes.Control::2 629224 +system.ruby.network.routers5.throttle1.msg_bytes.Data::2 5624640 +system.ruby.network.routers5.throttle1.msg_bytes.Response_Data::4 72072 +system.ruby.network.routers6.throttle0.link_utilization 5.176398 +system.ruby.network.routers6.throttle0.msg_count.Response_Data::4 78453 +system.ruby.network.routers6.throttle0.msg_count.Writeback_Control::3 78933 +system.ruby.network.routers6.throttle0.msg_bytes.Response_Data::4 5648616 +system.ruby.network.routers6.throttle0.msg_bytes.Writeback_Control::3 631464 +system.ruby.network.routers6.throttle1.link_utilization 5.201726 +system.ruby.network.routers6.throttle1.msg_count.Control::2 78454 +system.ruby.network.routers6.throttle1.msg_count.Data::2 77910 +system.ruby.network.routers6.throttle1.msg_count.Response_Data::4 1023 +system.ruby.network.routers6.throttle1.msg_bytes.Control::2 627632 +system.ruby.network.routers6.throttle1.msg_bytes.Data::2 5609520 +system.ruby.network.routers6.throttle1.msg_bytes.Response_Data::4 73656 +system.ruby.network.routers7.throttle0.link_utilization 5.174268 +system.ruby.network.routers7.throttle0.msg_count.Response_Data::4 78416 +system.ruby.network.routers7.throttle0.msg_count.Writeback_Control::3 78943 +system.ruby.network.routers7.throttle0.msg_bytes.Response_Data::4 5645952 +system.ruby.network.routers7.throttle0.msg_bytes.Writeback_Control::3 631544 +system.ruby.network.routers7.throttle1.link_utilization 5.202082 +system.ruby.network.routers7.throttle1.msg_count.Control::2 78418 +system.ruby.network.routers7.throttle1.msg_count.Data::2 77890 +system.ruby.network.routers7.throttle1.msg_count.Response_Data::4 1053 +system.ruby.network.routers7.throttle1.msg_bytes.Control::2 627344 +system.ruby.network.routers7.throttle1.msg_bytes.Data::2 5608080 +system.ruby.network.routers7.throttle1.msg_bytes.Response_Data::4 75816 +system.ruby.network.routers8.throttle0.link_utilization 41.141772 +system.ruby.network.routers8.throttle0.msg_count.Control::2 627993 +system.ruby.network.routers8.throttle0.msg_count.Data::2 623470 +system.ruby.network.routers8.throttle0.msg_bytes.Control::2 5023944 +system.ruby.network.routers8.throttle0.msg_bytes.Data::2 44889840 +system.ruby.network.routers8.throttle1.link_utilization 40.938761 +system.ruby.network.routers8.throttle1.msg_count.Response_Data::4 619624 +system.ruby.network.routers8.throttle1.msg_count.Writeback_Control::3 631825 +system.ruby.network.routers8.throttle1.msg_bytes.Response_Data::4 44612928 +system.ruby.network.routers8.throttle1.msg_bytes.Writeback_Control::3 5054600 +system.ruby.network.routers9.throttle0.link_utilization 5.187964 +system.ruby.network.routers9.throttle0.msg_count.Response_Data::4 78628 +system.ruby.network.routers9.throttle0.msg_count.Writeback_Control::3 79112 +system.ruby.network.routers9.throttle0.msg_bytes.Response_Data::4 5661216 +system.ruby.network.routers9.throttle0.msg_bytes.Writeback_Control::3 632896 +system.ruby.network.routers9.throttle1.link_utilization 5.186949 +system.ruby.network.routers9.throttle1.msg_count.Response_Data::4 78613 +system.ruby.network.routers9.throttle1.msg_count.Writeback_Control::3 79093 +system.ruby.network.routers9.throttle1.msg_bytes.Response_Data::4 5660136 +system.ruby.network.routers9.throttle1.msg_bytes.Writeback_Control::3 632744 +system.ruby.network.routers9.throttle2.link_utilization 5.197519 +system.ruby.network.routers9.throttle2.msg_count.Response_Data::4 78774 +system.ruby.network.routers9.throttle2.msg_count.Writeback_Control::3 79247 +system.ruby.network.routers9.throttle2.msg_bytes.Response_Data::4 5671728 +system.ruby.network.routers9.throttle2.msg_bytes.Writeback_Control::3 633976 +system.ruby.network.routers9.throttle3.link_utilization 5.161964 +system.ruby.network.routers9.throttle3.msg_count.Response_Data::4 78234 +system.ruby.network.routers9.throttle3.msg_count.Writeback_Control::3 78715 +system.ruby.network.routers9.throttle3.msg_bytes.Response_Data::4 5632848 +system.ruby.network.routers9.throttle3.msg_bytes.Writeback_Control::3 629720 +system.ruby.network.routers9.throttle4.link_utilization 5.160124 +system.ruby.network.routers9.throttle4.msg_count.Response_Data::4 78209 +system.ruby.network.routers9.throttle4.msg_count.Writeback_Control::3 78661 +system.ruby.network.routers9.throttle4.msg_bytes.Response_Data::4 5631048 +system.ruby.network.routers9.throttle4.msg_bytes.Writeback_Control::3 629288 +system.ruby.network.routers9.throttle5.link_utilization 5.189448 +system.ruby.network.routers9.throttle5.msg_count.Response_Data::4 78652 +system.ruby.network.routers9.throttle5.msg_count.Writeback_Control::3 79121 +system.ruby.network.routers9.throttle5.msg_bytes.Response_Data::4 5662944 +system.ruby.network.routers9.throttle5.msg_bytes.Writeback_Control::3 632968 +system.ruby.network.routers9.throttle6.link_utilization 5.176398 +system.ruby.network.routers9.throttle6.msg_count.Response_Data::4 78453 +system.ruby.network.routers9.throttle6.msg_count.Writeback_Control::3 78933 +system.ruby.network.routers9.throttle6.msg_bytes.Response_Data::4 5648616 +system.ruby.network.routers9.throttle6.msg_bytes.Writeback_Control::3 631464 +system.ruby.network.routers9.throttle7.link_utilization 5.174268 +system.ruby.network.routers9.throttle7.msg_count.Response_Data::4 78416 +system.ruby.network.routers9.throttle7.msg_count.Writeback_Control::3 78943 +system.ruby.network.routers9.throttle7.msg_bytes.Response_Data::4 5645952 +system.ruby.network.routers9.throttle7.msg_bytes.Writeback_Control::3 631544 +system.ruby.network.routers9.throttle8.link_utilization 41.141772 +system.ruby.network.routers9.throttle8.msg_count.Control::2 627993 +system.ruby.network.routers9.throttle8.msg_count.Data::2 623470 +system.ruby.network.routers9.throttle8.msg_bytes.Control::2 5023944 +system.ruby.network.routers9.throttle8.msg_bytes.Data::2 44889840 system.ruby.delayVCHist.vnet_1::bucket_size 4 # delay histogram for vnet_1 system.ruby.delayVCHist.vnet_1::max_bucket 39 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::samples 627760 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::mean 0.272321 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::stdev 1.331534 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1 | 602027 95.90% 95.90% | 18741 2.99% 98.89% | 5956 0.95% 99.83% | 834 0.13% 99.97% | 162 0.03% 99.99% | 34 0.01% 100.00% | 6 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::total 627760 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::samples 627979 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::mean 0.257658 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::stdev 1.293410 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1 | 603579 96.11% 96.11% | 17844 2.84% 98.96% | 5625 0.90% 99.85% | 739 0.12% 99.97% | 162 0.03% 100.00% | 24 0.00% 100.00% | 6 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::total 627979 # delay histogram for vnet_1 system.ruby.delayVCHist.vnet_2::bucket_size 32 # delay histogram for vnet_2 system.ruby.delayVCHist.vnet_2::max_bucket 319 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::samples 631610 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::mean 4.109089 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::stdev 10.468759 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2 | 614344 97.27% 97.27% | 10923 1.73% 99.00% | 5617 0.89% 99.89% | 569 0.09% 99.98% | 127 0.02% 100.00% | 28 0.00% 100.00% | 2 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::total 631610 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::samples 631824 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::mean 4.008551 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::stdev 10.168722 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2 | 615441 97.41% 97.41% | 10426 1.65% 99.06% | 5324 0.84% 99.90% | 510 0.08% 99.98% | 106 0.02% 100.00% | 17 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::total 631824 # delay histogram for vnet_2 system.ruby.LD.latency_hist::bucket_size 512 system.ruby.LD.latency_hist::max_bucket 5119 -system.ruby.LD.latency_hist::samples 403546 -system.ruby.LD.latency_hist::mean 1557.548146 -system.ruby.LD.latency_hist::gmean 1534.608299 -system.ruby.LD.latency_hist::stdev 267.377915 -system.ruby.LD.latency_hist | 45 0.01% 0.01% | 4772 1.18% 1.19% | 195796 48.52% 49.71% | 185358 45.93% 95.64% | 17446 4.32% 99.97% | 129 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.latency_hist::total 403546 +system.ruby.LD.latency_hist::samples 404144 +system.ruby.LD.latency_hist::mean 1545.571497 +system.ruby.LD.latency_hist::gmean 1523.054184 +system.ruby.LD.latency_hist::stdev 263.999078 +system.ruby.LD.latency_hist | 46 0.01% 0.01% | 5096 1.26% 1.27% | 203787 50.42% 51.70% | 179678 44.46% 96.16% | 15429 3.82% 99.97% | 108 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.latency_hist::total 404144 system.ruby.LD.miss_latency_hist::bucket_size 512 system.ruby.LD.miss_latency_hist::max_bucket 5119 -system.ruby.LD.miss_latency_hist::samples 403546 -system.ruby.LD.miss_latency_hist::mean 1557.548146 -system.ruby.LD.miss_latency_hist::gmean 1534.608299 -system.ruby.LD.miss_latency_hist::stdev 267.377915 -system.ruby.LD.miss_latency_hist | 45 0.01% 0.01% | 4772 1.18% 1.19% | 195796 48.52% 49.71% | 185358 45.93% 95.64% | 17446 4.32% 99.97% | 129 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.miss_latency_hist::total 403546 +system.ruby.LD.miss_latency_hist::samples 404144 +system.ruby.LD.miss_latency_hist::mean 1545.571497 +system.ruby.LD.miss_latency_hist::gmean 1523.054184 +system.ruby.LD.miss_latency_hist::stdev 263.999078 +system.ruby.LD.miss_latency_hist | 46 0.01% 0.01% | 5096 1.26% 1.27% | 203787 50.42% 51.70% | 179678 44.46% 96.16% | 15429 3.82% 99.97% | 108 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.miss_latency_hist::total 404144 system.ruby.ST.latency_hist::bucket_size 512 system.ruby.ST.latency_hist::max_bucket 5119 -system.ruby.ST.latency_hist::samples 224214 -system.ruby.ST.latency_hist::mean 1557.955489 -system.ruby.ST.latency_hist::gmean 1535.137320 -system.ruby.ST.latency_hist::stdev 266.918128 -system.ruby.ST.latency_hist | 21 0.01% 0.01% | 2565 1.14% 1.15% | 108735 48.50% 49.65% | 103114 45.99% 95.64% | 9704 4.33% 99.97% | 75 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.latency_hist::total 224214 +system.ruby.ST.latency_hist::samples 223835 +system.ruby.ST.latency_hist::mean 1545.041991 +system.ruby.ST.latency_hist::gmean 1522.530592 +system.ruby.ST.latency_hist::stdev 263.883663 +system.ruby.ST.latency_hist | 22 0.01% 0.01% | 2888 1.29% 1.30% | 112600 50.30% 51.60% | 99837 44.60% 96.21% | 8410 3.76% 99.97% | 78 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.latency_hist::total 223835 system.ruby.ST.miss_latency_hist::bucket_size 512 system.ruby.ST.miss_latency_hist::max_bucket 5119 -system.ruby.ST.miss_latency_hist::samples 224214 -system.ruby.ST.miss_latency_hist::mean 1557.955489 -system.ruby.ST.miss_latency_hist::gmean 1535.137320 -system.ruby.ST.miss_latency_hist::stdev 266.918128 -system.ruby.ST.miss_latency_hist | 21 0.01% 0.01% | 2565 1.14% 1.15% | 108735 48.50% 49.65% | 103114 45.99% 95.64% | 9704 4.33% 99.97% | 75 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.miss_latency_hist::total 224214 -system.ruby.L1Cache.miss_mach_latency_hist::bucket_size 256 -system.ruby.L1Cache.miss_mach_latency_hist::max_bucket 2559 -system.ruby.L1Cache.miss_mach_latency_hist::samples 8531 -system.ruby.L1Cache.miss_mach_latency_hist::mean 1448.565233 -system.ruby.L1Cache.miss_mach_latency_hist::gmean 1423.519365 -system.ruby.L1Cache.miss_mach_latency_hist::stdev 270.374184 -system.ruby.L1Cache.miss_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 17 0.20% 0.20% | 336 3.94% 4.14% | 2048 24.01% 28.14% | 3165 37.10% 65.24% | 2039 23.90% 89.15% | 737 8.64% 97.78% | 163 1.91% 99.70% | 26 0.30% 100.00% -system.ruby.L1Cache.miss_mach_latency_hist::total 8531 +system.ruby.ST.miss_latency_hist::samples 223835 +system.ruby.ST.miss_latency_hist::mean 1545.041991 +system.ruby.ST.miss_latency_hist::gmean 1522.530592 +system.ruby.ST.miss_latency_hist::stdev 263.883663 +system.ruby.ST.miss_latency_hist | 22 0.01% 0.01% | 2888 1.29% 1.30% | 112600 50.30% 51.60% | 99837 44.60% 96.21% | 8410 3.76% 99.97% | 78 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.miss_latency_hist::total 223835 +system.ruby.L1Cache.miss_mach_latency_hist::bucket_size 512 +system.ruby.L1Cache.miss_mach_latency_hist::max_bucket 5119 +system.ruby.L1Cache.miss_mach_latency_hist::samples 8356 +system.ruby.L1Cache.miss_mach_latency_hist::mean 1439.556127 +system.ruby.L1Cache.miss_mach_latency_hist::gmean 1414.820611 +system.ruby.L1Cache.miss_mach_latency_hist::stdev 268.620110 +system.ruby.L1Cache.miss_mach_latency_hist | 0 0.00% 0.00% | 325 3.89% 3.89% | 5166 61.82% 65.71% | 2690 32.19% 97.91% | 173 2.07% 99.98% | 2 0.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache.miss_mach_latency_hist::total 8356 system.ruby.Directory.miss_mach_latency_hist::bucket_size 512 system.ruby.Directory.miss_mach_latency_hist::max_bucket 5119 -system.ruby.Directory.miss_mach_latency_hist::samples 619229 -system.ruby.Directory.miss_mach_latency_hist::mean 1559.197076 -system.ruby.Directory.miss_mach_latency_hist::gmean 1536.389523 -system.ruby.Directory.miss_mach_latency_hist::stdev 266.858602 -system.ruby.Directory.miss_mach_latency_hist | 66 0.01% 0.01% | 6984 1.13% 1.14% | 299318 48.34% 49.48% | 285696 46.14% 95.61% | 26961 4.35% 99.97% | 204 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Directory.miss_mach_latency_hist::total 619229 +system.ruby.Directory.miss_mach_latency_hist::samples 619623 +system.ruby.Directory.miss_mach_latency_hist::mean 1546.809899 +system.ruby.Directory.miss_mach_latency_hist::gmean 1524.379638 +system.ruby.Directory.miss_mach_latency_hist::stdev 263.604468 +system.ruby.Directory.miss_mach_latency_hist | 68 0.01% 0.01% | 7659 1.24% 1.25% | 311221 50.23% 51.47% | 276825 44.68% 96.15% | 23666 3.82% 99.97% | 184 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_mach_latency_hist::total 619623 system.ruby.Directory.miss_latency_hist.issue_to_initial_request::bucket_size 1 system.ruby.Directory.miss_latency_hist.issue_to_initial_request::max_bucket 9 system.ruby.Directory.miss_latency_hist.issue_to_initial_request::samples 4 @@ -678,84 +683,84 @@ system.ruby.Directory.miss_latency_hist.first_response_to_completion::gmean 8 system.ruby.Directory.miss_latency_hist.first_response_to_completion::stdev 6.454972 system.ruby.Directory.miss_latency_hist.first_response_to_completion | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 25.00% 25.00% | 3 75.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.Directory.miss_latency_hist.first_response_to_completion::total 4 -system.ruby.LD.L1Cache.miss_type_mach_latency_hist::bucket_size 256 -system.ruby.LD.L1Cache.miss_type_mach_latency_hist::max_bucket 2559 -system.ruby.LD.L1Cache.miss_type_mach_latency_hist::samples 5413 -system.ruby.LD.L1Cache.miss_type_mach_latency_hist::mean 1445.669499 -system.ruby.LD.L1Cache.miss_type_mach_latency_hist::gmean 1420.780527 -system.ruby.LD.L1Cache.miss_type_mach_latency_hist::stdev 269.907745 -system.ruby.LD.L1Cache.miss_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 8 0.15% 0.15% | 212 3.92% 4.06% | 1326 24.50% 28.56% | 2026 37.43% 65.99% | 1262 23.31% 89.30% | 452 8.35% 97.65% | 110 2.03% 99.69% | 17 0.31% 100.00% -system.ruby.LD.L1Cache.miss_type_mach_latency_hist::total 5413 +system.ruby.LD.L1Cache.miss_type_mach_latency_hist::bucket_size 512 +system.ruby.LD.L1Cache.miss_type_mach_latency_hist::max_bucket 5119 +system.ruby.LD.L1Cache.miss_type_mach_latency_hist::samples 5357 +system.ruby.LD.L1Cache.miss_type_mach_latency_hist::mean 1439.042561 +system.ruby.LD.L1Cache.miss_type_mach_latency_hist::gmean 1414.108080 +system.ruby.LD.L1Cache.miss_type_mach_latency_hist::stdev 269.675535 +system.ruby.LD.L1Cache.miss_type_mach_latency_hist | 0 0.00% 0.00% | 221 4.13% 4.13% | 3291 61.43% 65.56% | 1732 32.33% 97.89% | 112 2.09% 99.98% | 1 0.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.L1Cache.miss_type_mach_latency_hist::total 5357 system.ruby.LD.Directory.miss_type_mach_latency_hist::bucket_size 512 system.ruby.LD.Directory.miss_type_mach_latency_hist::max_bucket 5119 -system.ruby.LD.Directory.miss_type_mach_latency_hist::samples 398133 -system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 1559.069243 -system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 1536.217141 -system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 267.020897 -system.ruby.LD.Directory.miss_type_mach_latency_hist | 45 0.01% 0.01% | 4552 1.14% 1.15% | 192444 48.34% 49.49% | 183644 46.13% 95.62% | 17319 4.35% 99.97% | 129 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.Directory.miss_type_mach_latency_hist::total 398133 -system.ruby.ST.L1Cache.miss_type_mach_latency_hist::bucket_size 256 -system.ruby.ST.L1Cache.miss_type_mach_latency_hist::max_bucket 2559 -system.ruby.ST.L1Cache.miss_type_mach_latency_hist::samples 3118 -system.ruby.ST.L1Cache.miss_type_mach_latency_hist::mean 1453.592367 -system.ruby.ST.L1Cache.miss_type_mach_latency_hist::gmean 1428.286665 -system.ruby.ST.L1Cache.miss_type_mach_latency_hist::stdev 271.151930 -system.ruby.ST.L1Cache.miss_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 9 0.29% 0.29% | 124 3.98% 4.27% | 722 23.16% 27.42% | 1139 36.53% 63.95% | 777 24.92% 88.87% | 285 9.14% 98.01% | 53 1.70% 99.71% | 9 0.29% 100.00% -system.ruby.ST.L1Cache.miss_type_mach_latency_hist::total 3118 +system.ruby.LD.Directory.miss_type_mach_latency_hist::samples 398787 +system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 1547.002525 +system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 1524.573421 +system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 263.629488 +system.ruby.LD.Directory.miss_type_mach_latency_hist | 46 0.01% 0.01% | 4875 1.22% 1.23% | 200496 50.28% 51.51% | 177946 44.62% 96.13% | 15317 3.84% 99.97% | 107 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.Directory.miss_type_mach_latency_hist::total 398787 +system.ruby.ST.L1Cache.miss_type_mach_latency_hist::bucket_size 512 +system.ruby.ST.L1Cache.miss_type_mach_latency_hist::max_bucket 5119 +system.ruby.ST.L1Cache.miss_type_mach_latency_hist::samples 2999 +system.ruby.ST.L1Cache.miss_type_mach_latency_hist::mean 1440.473491 +system.ruby.ST.L1Cache.miss_type_mach_latency_hist::gmean 1416.094271 +system.ruby.ST.L1Cache.miss_type_mach_latency_hist::stdev 266.766826 +system.ruby.ST.L1Cache.miss_type_mach_latency_hist | 0 0.00% 0.00% | 104 3.47% 3.47% | 1875 62.52% 65.99% | 958 31.94% 97.93% | 61 2.03% 99.97% | 1 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.L1Cache.miss_type_mach_latency_hist::total 2999 system.ruby.ST.Directory.miss_type_mach_latency_hist::bucket_size 512 system.ruby.ST.Directory.miss_type_mach_latency_hist::max_bucket 5119 -system.ruby.ST.Directory.miss_type_mach_latency_hist::samples 221096 -system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 1559.427267 -system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 1536.699982 -system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 266.566552 -system.ruby.ST.Directory.miss_type_mach_latency_hist | 21 0.01% 0.01% | 2432 1.10% 1.11% | 106874 48.34% 49.45% | 102052 46.16% 95.61% | 9642 4.36% 99.97% | 75 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.Directory.miss_type_mach_latency_hist::total 221096 -system.ruby.L1Cache_Controller.Load | 50242 12.45% 12.45% | 50323 12.47% 24.92% | 50493 12.51% 37.43% | 50644 12.55% 49.98% | 50567 12.53% 62.51% | 50426 12.50% 75.01% | 50403 12.49% 87.50% | 50459 12.50% 100.00% -system.ruby.L1Cache_Controller.Load::total 403557 -system.ruby.L1Cache_Controller.Store | 28008 12.49% 12.49% | 28130 12.55% 25.04% | 27865 12.43% 37.46% | 27716 12.36% 49.83% | 28095 12.53% 62.36% | 28158 12.56% 74.91% | 28062 12.52% 87.43% | 28184 12.57% 100.00% -system.ruby.L1Cache_Controller.Store::total 224218 -system.ruby.L1Cache_Controller.Data | 78249 12.46% 12.46% | 78450 12.50% 24.96% | 78357 12.48% 37.44% | 78358 12.48% 49.93% | 78659 12.53% 62.46% | 78581 12.52% 74.97% | 78464 12.50% 87.47% | 78642 12.53% 100.00% -system.ruby.L1Cache_Controller.Data::total 627760 -system.ruby.L1Cache_Controller.Fwd_GETX | 1065 12.48% 12.48% | 1076 12.61% 25.10% | 1049 12.30% 37.39% | 1001 11.73% 49.13% | 1068 12.52% 61.65% | 1132 13.27% 74.92% | 1066 12.50% 87.41% | 1074 12.59% 100.00% -system.ruby.L1Cache_Controller.Fwd_GETX::total 8531 -system.ruby.L1Cache_Controller.Replacement | 78246 12.46% 12.46% | 78449 12.50% 24.96% | 78354 12.48% 37.44% | 78356 12.48% 49.93% | 78658 12.53% 62.46% | 78580 12.52% 74.97% | 78461 12.50% 87.47% | 78639 12.53% 100.00% -system.ruby.L1Cache_Controller.Replacement::total 627743 -system.ruby.L1Cache_Controller.Writeback_Ack | 77181 12.46% 12.46% | 77373 12.50% 24.96% | 77305 12.48% 37.44% | 77355 12.49% 49.94% | 77587 12.53% 62.47% | 77448 12.51% 74.97% | 77395 12.50% 87.47% | 77565 12.53% 100.00% -system.ruby.L1Cache_Controller.Writeback_Ack::total 619209 -system.ruby.L1Cache_Controller.Writeback_Nack | 485 12.53% 12.53% | 499 12.89% 25.43% | 468 12.09% 37.52% | 457 11.81% 49.33% | 483 12.48% 61.81% | 494 12.76% 74.57% | 497 12.84% 87.42% | 487 12.58% 100.00% -system.ruby.L1Cache_Controller.Writeback_Nack::total 3870 -system.ruby.L1Cache_Controller.I.Load | 50242 12.45% 12.45% | 50323 12.47% 24.92% | 50493 12.51% 37.43% | 50644 12.55% 49.98% | 50567 12.53% 62.51% | 50426 12.50% 75.01% | 50403 12.49% 87.50% | 50459 12.50% 100.00% -system.ruby.L1Cache_Controller.I.Load::total 403557 -system.ruby.L1Cache_Controller.I.Store | 28008 12.49% 12.49% | 28130 12.55% 25.04% | 27865 12.43% 37.46% | 27716 12.36% 49.83% | 28095 12.53% 62.36% | 28158 12.56% 74.91% | 28062 12.52% 87.43% | 28184 12.57% 100.00% -system.ruby.L1Cache_Controller.I.Store::total 224218 -system.ruby.L1Cache_Controller.I.Replacement | 580 12.44% 12.44% | 577 12.38% 24.82% | 581 12.47% 37.29% | 544 11.67% 48.96% | 585 12.55% 61.51% | 638 13.69% 75.20% | 569 12.21% 87.41% | 587 12.59% 100.00% -system.ruby.L1Cache_Controller.I.Replacement::total 4661 -system.ruby.L1Cache_Controller.II.Writeback_Nack | 485 12.53% 12.53% | 499 12.89% 25.43% | 468 12.09% 37.52% | 457 11.81% 49.33% | 483 12.48% 61.81% | 494 12.76% 74.57% | 497 12.84% 87.42% | 487 12.58% 100.00% -system.ruby.L1Cache_Controller.II.Writeback_Nack::total 3870 -system.ruby.L1Cache_Controller.M.Fwd_GETX | 580 12.44% 12.44% | 577 12.38% 24.82% | 581 12.47% 37.29% | 544 11.67% 48.96% | 585 12.55% 61.51% | 638 13.69% 75.20% | 569 12.21% 87.41% | 587 12.59% 100.00% -system.ruby.L1Cache_Controller.M.Fwd_GETX::total 4661 -system.ruby.L1Cache_Controller.M.Replacement | 77666 12.46% 12.46% | 77872 12.50% 24.96% | 77773 12.48% 37.44% | 77812 12.49% 49.93% | 78073 12.53% 62.46% | 77942 12.51% 74.97% | 77892 12.50% 87.47% | 78052 12.53% 100.00% -system.ruby.L1Cache_Controller.M.Replacement::total 623082 -system.ruby.L1Cache_Controller.MI.Fwd_GETX | 485 12.53% 12.53% | 499 12.89% 25.43% | 468 12.09% 37.52% | 457 11.81% 49.33% | 483 12.48% 61.81% | 494 12.76% 74.57% | 497 12.84% 87.42% | 487 12.58% 100.00% -system.ruby.L1Cache_Controller.MI.Fwd_GETX::total 3870 -system.ruby.L1Cache_Controller.MI.Writeback_Ack | 77181 12.46% 12.46% | 77373 12.50% 24.96% | 77305 12.48% 37.44% | 77355 12.49% 49.94% | 77587 12.53% 62.47% | 77448 12.51% 74.97% | 77395 12.50% 87.47% | 77565 12.53% 100.00% -system.ruby.L1Cache_Controller.MI.Writeback_Ack::total 619209 -system.ruby.L1Cache_Controller.IS.Data | 50241 12.45% 12.45% | 50321 12.47% 24.92% | 50492 12.51% 37.43% | 50642 12.55% 49.98% | 50566 12.53% 62.51% | 50424 12.50% 75.01% | 50402 12.49% 87.50% | 50458 12.50% 100.00% -system.ruby.L1Cache_Controller.IS.Data::total 403546 -system.ruby.L1Cache_Controller.IM.Data | 28008 12.49% 12.49% | 28129 12.55% 25.04% | 27865 12.43% 37.47% | 27716 12.36% 49.83% | 28093 12.53% 62.36% | 28157 12.56% 74.91% | 28062 12.52% 87.43% | 28184 12.57% 100.00% -system.ruby.L1Cache_Controller.IM.Data::total 224214 -system.ruby.Directory_Controller.GETX 693666 0.00% 0.00% -system.ruby.Directory_Controller.PUTX 619210 0.00% 0.00% -system.ruby.Directory_Controller.PUTX_NotOwner 3870 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Data 619230 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Ack 619209 0.00% 0.00% -system.ruby.Directory_Controller.I.GETX 619241 0.00% 0.00% -system.ruby.Directory_Controller.M.GETX 8531 0.00% 0.00% -system.ruby.Directory_Controller.M.PUTX 619210 0.00% 0.00% -system.ruby.Directory_Controller.M.PUTX_NotOwner 3870 0.00% 0.00% -system.ruby.Directory_Controller.IM.GETX 65555 0.00% 0.00% -system.ruby.Directory_Controller.IM.Memory_Data 619230 0.00% 0.00% -system.ruby.Directory_Controller.MI.GETX 339 0.00% 0.00% -system.ruby.Directory_Controller.MI.Memory_Ack 619209 0.00% 0.00% +system.ruby.ST.Directory.miss_type_mach_latency_hist::samples 220836 +system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 1546.462053 +system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 1524.029766 +system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 263.559522 +system.ruby.ST.Directory.miss_type_mach_latency_hist | 22 0.01% 0.01% | 2784 1.26% 1.27% | 110725 50.14% 51.41% | 98879 44.77% 96.18% | 8349 3.78% 99.97% | 77 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.Directory.miss_type_mach_latency_hist::total 220836 +system.ruby.Directory_Controller.GETX 692595 0.00% 0.00% +system.ruby.Directory_Controller.PUTX 619605 0.00% 0.00% +system.ruby.Directory_Controller.PUTX_NotOwner 3865 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Data 619624 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Ack 619604 0.00% 0.00% +system.ruby.Directory_Controller.I.GETX 619636 0.00% 0.00% +system.ruby.Directory_Controller.M.GETX 8356 0.00% 0.00% +system.ruby.Directory_Controller.M.PUTX 619605 0.00% 0.00% +system.ruby.Directory_Controller.M.PUTX_NotOwner 3865 0.00% 0.00% +system.ruby.Directory_Controller.IM.GETX 64332 0.00% 0.00% +system.ruby.Directory_Controller.IM.Memory_Data 619624 0.00% 0.00% +system.ruby.Directory_Controller.MI.GETX 271 0.00% 0.00% +system.ruby.Directory_Controller.MI.Memory_Ack 619604 0.00% 0.00% +system.ruby.L1Cache_Controller.Load | 50680 12.54% 12.54% | 50607 12.52% 25.06% | 50500 12.50% 37.56% | 50509 12.50% 50.05% | 50226 12.43% 62.48% | 50766 12.56% 75.04% | 50488 12.49% 87.54% | 50375 12.46% 100.00% +system.ruby.L1Cache_Controller.Load::total 404151 +system.ruby.L1Cache_Controller.Store | 27949 12.49% 12.49% | 28009 12.51% 25.00% | 28276 12.63% 37.63% | 27727 12.39% 50.02% | 27985 12.50% 62.52% | 27887 12.46% 74.98% | 27966 12.49% 87.47% | 28043 12.53% 100.00% +system.ruby.L1Cache_Controller.Store::total 223842 +system.ruby.L1Cache_Controller.Data | 78628 12.52% 12.52% | 78613 12.52% 25.04% | 78774 12.54% 37.58% | 78234 12.46% 50.04% | 78209 12.45% 62.50% | 78652 12.52% 75.02% | 78453 12.49% 87.51% | 78416 12.49% 100.00% +system.ruby.L1Cache_Controller.Data::total 627979 +system.ruby.L1Cache_Controller.Fwd_GETX | 1063 12.72% 12.72% | 1014 12.13% 24.86% | 1079 12.91% 37.77% | 1091 13.06% 50.83% | 1032 12.35% 63.18% | 1001 11.98% 75.16% | 1023 12.24% 87.40% | 1053 12.60% 100.00% +system.ruby.L1Cache_Controller.Fwd_GETX::total 8356 +system.ruby.L1Cache_Controller.Replacement | 78625 12.52% 12.52% | 78612 12.52% 25.04% | 78772 12.54% 37.58% | 78232 12.46% 50.04% | 78207 12.45% 62.50% | 78649 12.52% 75.02% | 78450 12.49% 87.51% | 78414 12.49% 100.00% +system.ruby.L1Cache_Controller.Replacement::total 627961 +system.ruby.L1Cache_Controller.Writeback_Ack | 77562 12.52% 12.52% | 77596 12.52% 25.04% | 77693 12.54% 37.58% | 77141 12.45% 50.03% | 77175 12.46% 62.49% | 77648 12.53% 75.02% | 77427 12.50% 87.51% | 77361 12.49% 100.00% +system.ruby.L1Cache_Controller.Writeback_Ack::total 619603 +system.ruby.L1Cache_Controller.Writeback_Nack | 487 12.60% 12.60% | 482 12.47% 25.07% | 475 12.29% 37.36% | 483 12.50% 49.86% | 454 11.75% 61.60% | 472 12.21% 73.82% | 483 12.50% 86.31% | 529 13.69% 100.00% +system.ruby.L1Cache_Controller.Writeback_Nack::total 3865 +system.ruby.L1Cache_Controller.I.Load | 50680 12.54% 12.54% | 50607 12.52% 25.06% | 50500 12.50% 37.56% | 50509 12.50% 50.05% | 50226 12.43% 62.48% | 50766 12.56% 75.04% | 50488 12.49% 87.54% | 50375 12.46% 100.00% +system.ruby.L1Cache_Controller.I.Load::total 404151 +system.ruby.L1Cache_Controller.I.Store | 27949 12.49% 12.49% | 28009 12.51% 25.00% | 28276 12.63% 37.63% | 27727 12.39% 50.02% | 27985 12.50% 62.52% | 27887 12.46% 74.98% | 27966 12.49% 87.47% | 28043 12.53% 100.00% +system.ruby.L1Cache_Controller.I.Store::total 223842 +system.ruby.L1Cache_Controller.I.Replacement | 576 12.83% 12.83% | 532 11.85% 24.67% | 604 13.45% 38.12% | 608 13.54% 51.66% | 578 12.87% 64.53% | 529 11.78% 76.31% | 540 12.02% 88.33% | 524 11.67% 100.00% +system.ruby.L1Cache_Controller.I.Replacement::total 4491 +system.ruby.L1Cache_Controller.II.Writeback_Nack | 487 12.60% 12.60% | 482 12.47% 25.07% | 475 12.29% 37.36% | 483 12.50% 49.86% | 454 11.75% 61.60% | 472 12.21% 73.82% | 483 12.50% 86.31% | 529 13.69% 100.00% +system.ruby.L1Cache_Controller.II.Writeback_Nack::total 3865 +system.ruby.L1Cache_Controller.M.Fwd_GETX | 576 12.83% 12.83% | 532 11.85% 24.67% | 604 13.45% 38.12% | 608 13.54% 51.66% | 578 12.87% 64.53% | 529 11.78% 76.31% | 540 12.02% 88.33% | 524 11.67% 100.00% +system.ruby.L1Cache_Controller.M.Fwd_GETX::total 4491 +system.ruby.L1Cache_Controller.M.Replacement | 78049 12.52% 12.52% | 78080 12.52% 25.04% | 78168 12.54% 37.58% | 77624 12.45% 50.03% | 77629 12.45% 62.48% | 78120 12.53% 75.01% | 77910 12.50% 87.51% | 77890 12.49% 100.00% +system.ruby.L1Cache_Controller.M.Replacement::total 623470 +system.ruby.L1Cache_Controller.MI.Fwd_GETX | 487 12.60% 12.60% | 482 12.47% 25.07% | 475 12.29% 37.36% | 483 12.50% 49.86% | 454 11.75% 61.60% | 472 12.21% 73.82% | 483 12.50% 86.31% | 529 13.69% 100.00% +system.ruby.L1Cache_Controller.MI.Fwd_GETX::total 3865 +system.ruby.L1Cache_Controller.MI.Writeback_Ack | 77562 12.52% 12.52% | 77596 12.52% 25.04% | 77693 12.54% 37.58% | 77141 12.45% 50.03% | 77175 12.46% 62.49% | 77648 12.53% 75.02% | 77427 12.50% 87.51% | 77361 12.49% 100.00% +system.ruby.L1Cache_Controller.MI.Writeback_Ack::total 619603 +system.ruby.L1Cache_Controller.IS.Data | 50680 12.54% 12.54% | 50605 12.52% 25.06% | 50498 12.50% 37.56% | 50509 12.50% 50.05% | 50225 12.43% 62.48% | 50765 12.56% 75.04% | 50488 12.49% 87.54% | 50374 12.46% 100.00% +system.ruby.L1Cache_Controller.IS.Data::total 404144 +system.ruby.L1Cache_Controller.IM.Data | 27948 12.49% 12.49% | 28008 12.51% 25.00% | 28276 12.63% 37.63% | 27725 12.39% 50.02% | 27984 12.50% 62.52% | 27887 12.46% 74.98% | 27965 12.49% 87.47% | 28042 12.53% 100.00% +system.ruby.L1Cache_Controller.IM.Data::total 223835 ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/stats.txt b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/stats.txt index c4d69701f..f5fe53ea2 100644 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/stats.txt +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/stats.txt @@ -4,9 +4,9 @@ sim_seconds 0.000323 # Nu sim_ticks 322881 # Number of ticks simulated final_tick 322881 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 1612482 # Simulator tick rate (ticks/s) -host_mem_usage 434296 # Number of bytes of host memory used -host_seconds 0.20 # Real time elapsed on the host +host_tick_rate 2952595 # Simulator tick rate (ticks/s) +host_mem_usage 447776 # Number of bytes of host memory used +host_seconds 0.11 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks system.mem_ctrls.bytes_read::ruby.dir_cntrl0 54144 # Number of bytes read from this memory @@ -235,29 +235,34 @@ system.mem_ctrls.readRowHitRate 79.08 # Ro system.mem_ctrls.writeRowHitRate 95.59 # Row buffer hit rate for writes system.mem_ctrls.avgGap 201.77 # Average gap between requests system.mem_ctrls.pageHitRate 86.97 # Row buffer hit rate, read and write combined -system.mem_ctrls.memoryStateTime::IDLE 7291 # Time in different power states -system.mem_ctrls.memoryStateTime::REF 10660 # Time in different power states -system.mem_ctrls.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls.memoryStateTime::ACT 301549 # Time in different power states -system.mem_ctrls.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrls.actEnergy::0 1171800 # Energy for activate commands per rank (pJ) -system.mem_ctrls.actEnergy::1 0 # Energy for activate commands per rank (pJ) -system.mem_ctrls.preEnergy::0 651000 # Energy for precharge commands per rank (pJ) -system.mem_ctrls.preEnergy::1 0 # Energy for precharge commands per rank (pJ) -system.mem_ctrls.readEnergy::0 8835840 # Energy for read commands per rank (pJ) -system.mem_ctrls.readEnergy::1 0 # Energy for read commands per rank (pJ) -system.mem_ctrls.writeEnergy::0 6407424 # Energy for write commands per rank (pJ) -system.mem_ctrls.writeEnergy::1 0 # Energy for write commands per rank (pJ) -system.mem_ctrls.refreshEnergy::0 20850960 # Energy for refresh commands per rank (pJ) -system.mem_ctrls.refreshEnergy::1 20850960 # Energy for refresh commands per rank (pJ) -system.mem_ctrls.actBackEnergy::0 212765724 # Energy for active background per rank (pJ) -system.mem_ctrls.actBackEnergy::1 6898824 # Energy for active background per rank (pJ) -system.mem_ctrls.preBackEnergy::0 5055000 # Energy for precharge background per rank (pJ) -system.mem_ctrls.preBackEnergy::1 185640000 # Energy for precharge background per rank (pJ) -system.mem_ctrls.totalEnergy::0 255737748 # Total energy per rank (pJ) -system.mem_ctrls.totalEnergy::1 213389784 # Total energy per rank (pJ) -system.mem_ctrls.averagePower::0 800.466211 # Core power per rank (mW) -system.mem_ctrls.averagePower::1 667.915915 # Core power per rank (mW) +system.mem_ctrls_0.actEnergy 1171800 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 651000 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 8835840 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 6407424 # Energy for write commands per rank (pJ) +system.mem_ctrls_0.refreshEnergy 20850960 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_0.actBackEnergy 212765724 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 5055000 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.totalEnergy 255737748 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 800.466211 # Core power per rank (mW) +system.mem_ctrls_0.memoryStateTime::IDLE 7291 # Time in different power states +system.mem_ctrls_0.memoryStateTime::REF 10660 # Time in different power states +system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 301549 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls_1.actEnergy 0 # Energy for activate commands per rank (pJ) +system.mem_ctrls_1.preEnergy 0 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_1.readEnergy 0 # Energy for read commands per rank (pJ) +system.mem_ctrls_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls_1.refreshEnergy 20850960 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_1.actBackEnergy 6898824 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 185631600 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.totalEnergy 213381384 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 667.918891 # Core power per rank (mW) +system.mem_ctrls_1.memoryStateTime::IDLE 308826 # Time in different power states +system.mem_ctrls_1.memoryStateTime::REF 10660 # Time in different power states +system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 0 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.ruby.clk_domain.clock 1 # Clock period in ticks system.ruby.delayHist::bucket_size 512 # delay histogram for all message system.ruby.delayHist::max_bucket 5119 # delay histogram for all message @@ -317,6 +322,10 @@ system.ruby.l1_cntrl0.sequencer.store_waiting_on_load 4 system.ruby.l1_cntrl0.sequencer.store_waiting_on_store 77 # Number of times a store aliased with a pending store system.ruby.l1_cntrl0.sequencer.load_waiting_on_store 11 # Number of times a load aliased with a pending store system.ruby.l1_cntrl0.sequencer.load_waiting_on_load 1 # Number of times a load aliased with a pending load +system.ruby.l2_cntrl0.L2cache.demand_hits 29 # Number of cache demand hits +system.ruby.l2_cntrl0.L2cache.demand_misses 846 # Number of cache demand misses +system.ruby.l2_cntrl0.L2cache.demand_accesses 875 # Number of cache demand accesses +system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks system.ruby.network.routers0.percent_links_utilized 1.655176 system.ruby.network.routers0.msg_count.Control::0 876 system.ruby.network.routers0.msg_count.Request_Control::2 528 @@ -334,9 +343,6 @@ system.ruby.network.routers0.msg_bytes.Response_Control::2 6576 system.ruby.network.routers0.msg_bytes.Writeback_Data::0 49680 system.ruby.network.routers0.msg_bytes.Writeback_Data::1 34056 system.ruby.network.routers0.msg_bytes.Writeback_Control::0 272 -system.ruby.l2_cntrl0.L2cache.demand_hits 29 # Number of cache demand hits -system.ruby.l2_cntrl0.L2cache.demand_misses 846 # Number of cache demand misses -system.ruby.l2_cntrl0.L2cache.demand_accesses 875 # Number of cache demand accesses system.ruby.network.routers1.percent_links_utilized 2.907186 system.ruby.network.routers1.msg_count.Control::0 1722 system.ruby.network.routers1.msg_count.Request_Control::2 528 @@ -390,7 +396,6 @@ system.ruby.network.msg_byte.Response_Data 534312 system.ruby.network.msg_byte.Response_Control 60720 system.ruby.network.msg_byte.Writeback_Data 251208 system.ruby.network.msg_byte.Writeback_Control 816 -system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks system.ruby.network.routers0.throttle0.link_utilization 1.412750 system.ruby.network.routers0.throttle0.msg_count.Request_Control::2 528 system.ruby.network.routers0.throttle0.msg_count.Response_Data::1 875 @@ -559,6 +564,16 @@ system.ruby.IFETCH.miss_latency_hist::gmean 799.675557 system.ruby.IFETCH.miss_latency_hist::stdev 325.423919 system.ruby.IFETCH.miss_latency_hist | 1 1.96% 1.96% | 5 9.80% 11.76% | 17 33.33% 45.10% | 17 33.33% 78.43% | 4 7.84% 86.27% | 5 9.80% 96.08% | 2 3.92% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.miss_latency_hist::total 51 +system.ruby.Directory_Controller.Fetch 846 0.00% 0.00% +system.ruby.Directory_Controller.Data 752 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Data 846 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Ack 752 0.00% 0.00% +system.ruby.Directory_Controller.CleanReplacement 89 0.00% 0.00% +system.ruby.Directory_Controller.I.Fetch 846 0.00% 0.00% +system.ruby.Directory_Controller.M.Data 752 0.00% 0.00% +system.ruby.Directory_Controller.M.CleanReplacement 89 0.00% 0.00% +system.ruby.Directory_Controller.IM.Memory_Data 846 0.00% 0.00% +system.ruby.Directory_Controller.MI.Memory_Ack 752 0.00% 0.00% system.ruby.L1Cache_Controller.Load 49 0.00% 0.00% system.ruby.L1Cache_Controller.Ifetch 58 0.00% 0.00% system.ruby.L1Cache_Controller.Store 841 0.00% 0.00% @@ -633,15 +648,5 @@ system.ruby.L2Cache_Controller.MT_MB.L1_PUTX 15 0.00% 0.00% system.ruby.L2Cache_Controller.MT_MB.L1_PUTX_old 143 0.00% 0.00% system.ruby.L2Cache_Controller.MT_MB.L2_Replacement_clean 331 0.00% 0.00% system.ruby.L2Cache_Controller.MT_MB.Exclusive_Unblock 817 0.00% 0.00% -system.ruby.Directory_Controller.Fetch 846 0.00% 0.00% -system.ruby.Directory_Controller.Data 752 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Data 846 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Ack 752 0.00% 0.00% -system.ruby.Directory_Controller.CleanReplacement 89 0.00% 0.00% -system.ruby.Directory_Controller.I.Fetch 846 0.00% 0.00% -system.ruby.Directory_Controller.M.Data 752 0.00% 0.00% -system.ruby.Directory_Controller.M.CleanReplacement 89 0.00% 0.00% -system.ruby.Directory_Controller.IM.Memory_Data 846 0.00% 0.00% -system.ruby.Directory_Controller.MI.Memory_Ack 752 0.00% 0.00% ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt index bbe924bff..79972c69a 100644 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt @@ -4,9 +4,9 @@ sim_seconds 0.000330 # Nu sim_ticks 330331 # Number of ticks simulated final_tick 330331 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 620421 # Simulator tick rate (ticks/s) -host_mem_usage 435392 # Number of bytes of host memory used -host_seconds 0.53 # Real time elapsed on the host +host_tick_rate 797019 # Simulator tick rate (ticks/s) +host_mem_usage 449656 # Number of bytes of host memory used +host_seconds 0.41 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks system.mem_ctrls.bytes_read::ruby.dir_cntrl0 54784 # Number of bytes read from this memory @@ -236,29 +236,34 @@ system.mem_ctrls.readRowHitRate 78.28 # Ro system.mem_ctrls.writeRowHitRate 94.50 # Row buffer hit rate for writes system.mem_ctrls.avgGap 203.82 # Average gap between requests system.mem_ctrls.pageHitRate 86.08 # Row buffer hit rate, read and write combined -system.mem_ctrls.memoryStateTime::IDLE 5756 # Time in different power states -system.mem_ctrls.memoryStateTime::REF 10920 # Time in different power states -system.mem_ctrls.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls.memoryStateTime::ACT 310724 # Time in different power states -system.mem_ctrls.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrls.actEnergy::0 1202040 # Energy for activate commands per rank (pJ) -system.mem_ctrls.actEnergy::1 0 # Energy for activate commands per rank (pJ) -system.mem_ctrls.preEnergy::0 667800 # Energy for precharge commands per rank (pJ) -system.mem_ctrls.preEnergy::1 0 # Energy for precharge commands per rank (pJ) -system.mem_ctrls.readEnergy::0 8448960 # Energy for read commands per rank (pJ) -system.mem_ctrls.readEnergy::1 0 # Energy for read commands per rank (pJ) -system.mem_ctrls.writeEnergy::0 6189696 # Energy for write commands per rank (pJ) -system.mem_ctrls.writeEnergy::1 0 # Energy for write commands per rank (pJ) -system.mem_ctrls.refreshEnergy::0 21359520 # Energy for refresh commands per rank (pJ) -system.mem_ctrls.refreshEnergy::1 21359520 # Energy for refresh commands per rank (pJ) -system.mem_ctrls.actBackEnergy::0 219200112 # Energy for active background per rank (pJ) -system.mem_ctrls.actBackEnergy::1 7067088 # Energy for active background per rank (pJ) -system.mem_ctrls.preBackEnergy::0 4082400 # Energy for precharge background per rank (pJ) -system.mem_ctrls.preBackEnergy::1 190164000 # Energy for precharge background per rank (pJ) -system.mem_ctrls.totalEnergy::0 261150528 # Total energy per rank (pJ) -system.mem_ctrls.totalEnergy::1 218590608 # Total energy per rank (pJ) -system.mem_ctrls.averagePower::0 797.961720 # Core power per rank (mW) -system.mem_ctrls.averagePower::1 667.917231 # Core power per rank (mW) +system.mem_ctrls_0.actEnergy 1202040 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 667800 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 8448960 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 6189696 # Energy for write commands per rank (pJ) +system.mem_ctrls_0.refreshEnergy 21359520 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_0.actBackEnergy 219200112 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 4082400 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.totalEnergy 261150528 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 797.961720 # Core power per rank (mW) +system.mem_ctrls_0.memoryStateTime::IDLE 5756 # Time in different power states +system.mem_ctrls_0.memoryStateTime::REF 10920 # Time in different power states +system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 310724 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls_1.actEnergy 0 # Energy for activate commands per rank (pJ) +system.mem_ctrls_1.preEnergy 0 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_1.readEnergy 0 # Energy for read commands per rank (pJ) +system.mem_ctrls_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls_1.refreshEnergy 21359520 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_1.actBackEnergy 7067088 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 190155600 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.totalEnergy 218582208 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 667.920136 # Core power per rank (mW) +system.mem_ctrls_1.memoryStateTime::IDLE 316352 # Time in different power states +system.mem_ctrls_1.memoryStateTime::REF 10920 # Time in different power states +system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 0 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.ruby.clk_domain.clock 1 # Clock period in ticks system.ruby.outstanding_req_hist::bucket_size 2 system.ruby.outstanding_req_hist::max_bucket 19 @@ -302,6 +307,10 @@ system.ruby.l1_cntrl0.sequencer.store_waiting_on_load 3 system.ruby.l1_cntrl0.sequencer.store_waiting_on_store 93 # Number of times a store aliased with a pending store system.ruby.l1_cntrl0.sequencer.load_waiting_on_store 8 # Number of times a load aliased with a pending store system.ruby.l1_cntrl0.sequencer.load_waiting_on_load 1 # Number of times a load aliased with a pending load +system.ruby.l2_cntrl0.L2cache.demand_hits 44 # Number of cache demand hits +system.ruby.l2_cntrl0.L2cache.demand_misses 857 # Number of cache demand misses +system.ruby.l2_cntrl0.L2cache.demand_accesses 901 # Number of cache demand accesses +system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks system.ruby.network.routers0.percent_links_utilized 1.492064 system.ruby.network.routers0.msg_count.Request_Control::0 901 system.ruby.network.routers0.msg_count.Response_Data::2 855 @@ -315,9 +324,6 @@ system.ruby.network.routers0.msg_bytes.ResponseL2hit_Data::2 3168 system.ruby.network.routers0.msg_bytes.Writeback_Data::2 64296 system.ruby.network.routers0.msg_bytes.Writeback_Control::0 14304 system.ruby.network.routers0.msg_bytes.Unblock_Control::2 7184 -system.ruby.l2_cntrl0.L2cache.demand_hits 44 # Number of cache demand hits -system.ruby.l2_cntrl0.L2cache.demand_misses 857 # Number of cache demand misses -system.ruby.l2_cntrl0.L2cache.demand_accesses 901 # Number of cache demand accesses system.ruby.network.routers1.percent_links_utilized 2.839803 system.ruby.network.routers1.msg_count.Request_Control::0 901 system.ruby.network.routers1.msg_count.Request_Control::1 857 @@ -375,7 +381,6 @@ system.ruby.network.msg_byte.ResponseL2hit_Data 9504 system.ruby.network.msg_byte.Writeback_Data 357696 system.ruby.network.msg_byte.Writeback_Control 79544 system.ruby.network.msg_byte.Unblock_Control 42048 -system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks system.ruby.network.routers0.throttle0.link_utilization 1.359848 system.ruby.network.routers0.throttle0.msg_count.Response_Data::2 855 system.ruby.network.routers0.throttle0.msg_count.ResponseL2hit_Data::2 44 @@ -527,6 +532,31 @@ system.ruby.IFETCH.miss_latency_hist::gmean 629.917289 system.ruby.IFETCH.miss_latency_hist::stdev 289.399275 system.ruby.IFETCH.miss_latency_hist | 4 7.41% 7.41% | 8 14.81% 22.22% | 22 40.74% 62.96% | 12 22.22% 85.19% | 6 11.11% 96.30% | 2 3.70% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.miss_latency_hist::total 54 +system.ruby.Directory_Controller.GETX 768 0.00% 0.00% +system.ruby.Directory_Controller.GETS 90 0.00% 0.00% +system.ruby.Directory_Controller.PUTX 763 0.00% 0.00% +system.ruby.Directory_Controller.Unblock 77 0.00% 0.00% +system.ruby.Directory_Controller.Last_Unblock 10 0.00% 0.00% +system.ruby.Directory_Controller.Exclusive_Unblock 767 0.00% 0.00% +system.ruby.Directory_Controller.Dirty_Writeback 763 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Data 856 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Ack 763 0.00% 0.00% +system.ruby.Directory_Controller.I.GETX 708 0.00% 0.00% +system.ruby.Directory_Controller.I.GETS 78 0.00% 0.00% +system.ruby.Directory_Controller.I.Memory_Ack 760 0.00% 0.00% +system.ruby.Directory_Controller.S.GETX 60 0.00% 0.00% +system.ruby.Directory_Controller.S.GETS 10 0.00% 0.00% +system.ruby.Directory_Controller.M.PUTX 763 0.00% 0.00% +system.ruby.Directory_Controller.IS.Unblock 77 0.00% 0.00% +system.ruby.Directory_Controller.IS.Memory_Data 78 0.00% 0.00% +system.ruby.Directory_Controller.IS.Memory_Ack 1 0.00% 0.00% +system.ruby.Directory_Controller.SS.Last_Unblock 10 0.00% 0.00% +system.ruby.Directory_Controller.SS.Memory_Data 10 0.00% 0.00% +system.ruby.Directory_Controller.MM.Exclusive_Unblock 767 0.00% 0.00% +system.ruby.Directory_Controller.MM.Memory_Data 768 0.00% 0.00% +system.ruby.Directory_Controller.MM.Memory_Ack 2 0.00% 0.00% +system.ruby.Directory_Controller.MI.GETS 2 0.00% 0.00% +system.ruby.Directory_Controller.MI.Dirty_Writeback 763 0.00% 0.00% system.ruby.L1Cache_Controller.Load 46 0.00% 0.00% system.ruby.L1Cache_Controller.Ifetch 243 0.00% 0.00% system.ruby.L1Cache_Controller.Store 1035 0.00% 0.00% @@ -610,30 +640,5 @@ system.ruby.L2Cache_Controller.OO.Exclusive_Unblock 8 0.00% system.ruby.L2Cache_Controller.MI.L1_GETS 85 0.00% 0.00% system.ruby.L2Cache_Controller.MI.L1_GETX 1 0.00% 0.00% system.ruby.L2Cache_Controller.MI.Writeback_Ack 763 0.00% 0.00% -system.ruby.Directory_Controller.GETX 768 0.00% 0.00% -system.ruby.Directory_Controller.GETS 90 0.00% 0.00% -system.ruby.Directory_Controller.PUTX 763 0.00% 0.00% -system.ruby.Directory_Controller.Unblock 77 0.00% 0.00% -system.ruby.Directory_Controller.Last_Unblock 10 0.00% 0.00% -system.ruby.Directory_Controller.Exclusive_Unblock 767 0.00% 0.00% -system.ruby.Directory_Controller.Dirty_Writeback 763 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Data 856 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Ack 763 0.00% 0.00% -system.ruby.Directory_Controller.I.GETX 708 0.00% 0.00% -system.ruby.Directory_Controller.I.GETS 78 0.00% 0.00% -system.ruby.Directory_Controller.I.Memory_Ack 760 0.00% 0.00% -system.ruby.Directory_Controller.S.GETX 60 0.00% 0.00% -system.ruby.Directory_Controller.S.GETS 10 0.00% 0.00% -system.ruby.Directory_Controller.M.PUTX 763 0.00% 0.00% -system.ruby.Directory_Controller.IS.Unblock 77 0.00% 0.00% -system.ruby.Directory_Controller.IS.Memory_Data 78 0.00% 0.00% -system.ruby.Directory_Controller.IS.Memory_Ack 1 0.00% 0.00% -system.ruby.Directory_Controller.SS.Last_Unblock 10 0.00% 0.00% -system.ruby.Directory_Controller.SS.Memory_Data 10 0.00% 0.00% -system.ruby.Directory_Controller.MM.Exclusive_Unblock 767 0.00% 0.00% -system.ruby.Directory_Controller.MM.Memory_Data 768 0.00% 0.00% -system.ruby.Directory_Controller.MM.Memory_Ack 2 0.00% 0.00% -system.ruby.Directory_Controller.MI.GETS 2 0.00% 0.00% -system.ruby.Directory_Controller.MI.Dirty_Writeback 763 0.00% 0.00% ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt index 6c54d9927..5f532e15e 100644 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt @@ -4,9 +4,9 @@ sim_seconds 0.000238 # Nu sim_ticks 237931 # Number of ticks simulated final_tick 237931 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 1532175 # Simulator tick rate (ticks/s) -host_mem_usage 434360 # Number of bytes of host memory used -host_seconds 0.16 # Real time elapsed on the host +host_tick_rate 2289780 # Simulator tick rate (ticks/s) +host_mem_usage 448616 # Number of bytes of host memory used +host_seconds 0.10 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks system.mem_ctrls.bytes_read::ruby.dir_cntrl0 55552 # Number of bytes read from this memory @@ -236,29 +236,34 @@ system.mem_ctrls.readRowHitRate 82.47 # Ro system.mem_ctrls.writeRowHitRate 95.96 # Row buffer hit rate for writes system.mem_ctrls.avgGap 143.45 # Average gap between requests system.mem_ctrls.pageHitRate 89.01 # Row buffer hit rate, read and write combined -system.mem_ctrls.memoryStateTime::IDLE 1511 # Time in different power states -system.mem_ctrls.memoryStateTime::REF 7800 # Time in different power states -system.mem_ctrls.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls.memoryStateTime::ACT 224543 # Time in different power states -system.mem_ctrls.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrls.actEnergy::0 1028160 # Energy for activate commands per rank (pJ) -system.mem_ctrls.actEnergy::1 0 # Energy for activate commands per rank (pJ) -system.mem_ctrls.preEnergy::0 571200 # Energy for precharge commands per rank (pJ) -system.mem_ctrls.preEnergy::1 0 # Energy for precharge commands per rank (pJ) -system.mem_ctrls.readEnergy::0 8973120 # Energy for read commands per rank (pJ) -system.mem_ctrls.readEnergy::1 0 # Energy for read commands per rank (pJ) -system.mem_ctrls.writeEnergy::0 6811776 # Energy for write commands per rank (pJ) -system.mem_ctrls.writeEnergy::1 0 # Energy for write commands per rank (pJ) -system.mem_ctrls.refreshEnergy::0 15256800 # Energy for refresh commands per rank (pJ) -system.mem_ctrls.refreshEnergy::1 15256800 # Energy for refresh commands per rank (pJ) -system.mem_ctrls.actBackEnergy::0 158348052 # Energy for active background per rank (pJ) -system.mem_ctrls.actBackEnergy::1 5047920 # Energy for active background per rank (pJ) -system.mem_ctrls.preBackEnergy::0 1402200 # Energy for precharge background per rank (pJ) -system.mem_ctrls.preBackEnergy::1 135876000 # Energy for precharge background per rank (pJ) -system.mem_ctrls.totalEnergy::0 192391308 # Total energy per rank (pJ) -system.mem_ctrls.totalEnergy::1 156180720 # Total energy per rank (pJ) -system.mem_ctrls.averagePower::0 822.747639 # Core power per rank (mW) -system.mem_ctrls.averagePower::1 667.895655 # Core power per rank (mW) +system.mem_ctrls_0.actEnergy 1028160 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 571200 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 8973120 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 6811776 # Energy for write commands per rank (pJ) +system.mem_ctrls_0.refreshEnergy 15256800 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_0.actBackEnergy 158348052 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 1402200 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.totalEnergy 192391308 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 822.747639 # Core power per rank (mW) +system.mem_ctrls_0.memoryStateTime::IDLE 1511 # Time in different power states +system.mem_ctrls_0.memoryStateTime::REF 7800 # Time in different power states +system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 224543 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls_1.actEnergy 0 # Energy for activate commands per rank (pJ) +system.mem_ctrls_1.preEnergy 0 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_1.readEnergy 0 # Energy for read commands per rank (pJ) +system.mem_ctrls_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls_1.refreshEnergy 15256800 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_1.actBackEnergy 5047920 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 135867600 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.totalEnergy 156172320 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 667.899720 # Core power per rank (mW) +system.mem_ctrls_1.memoryStateTime::IDLE 226040 # Time in different power states +system.mem_ctrls_1.memoryStateTime::REF 7800 # Time in different power states +system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 0 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.ruby.clk_domain.clock 1 # Clock period in ticks system.ruby.outstanding_req_hist::bucket_size 2 system.ruby.outstanding_req_hist::max_bucket 19 @@ -302,6 +307,10 @@ system.ruby.l1_cntrl0.L1Icache.demand_accesses 56 system.ruby.l1_cntrl0.sequencer.store_waiting_on_load 7 # Number of times a store aliased with a pending load system.ruby.l1_cntrl0.sequencer.store_waiting_on_store 90 # Number of times a store aliased with a pending store system.ruby.l1_cntrl0.sequencer.load_waiting_on_store 4 # Number of times a load aliased with a pending store +system.ruby.l2_cntrl0.L2cache.demand_hits 38 # Number of cache demand hits +system.ruby.l2_cntrl0.L2cache.demand_misses 877 # Number of cache demand misses +system.ruby.l2_cntrl0.L2cache.demand_accesses 915 # Number of cache demand accesses +system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks system.ruby.network.routers0.percent_links_utilized 2.062783 system.ruby.network.routers0.msg_count.Request_Control::1 915 system.ruby.network.routers0.msg_count.Response_Data::4 915 @@ -315,9 +324,6 @@ system.ruby.network.routers0.msg_bytes.ResponseL2hit_Data::4 2880 system.ruby.network.routers0.msg_bytes.Response_Control::4 24 system.ruby.network.routers0.msg_bytes.Writeback_Data::4 74808 system.ruby.network.routers0.msg_bytes.Persistent_Control::3 6144 -system.ruby.l2_cntrl0.L2cache.demand_hits 38 # Number of cache demand hits -system.ruby.l2_cntrl0.L2cache.demand_misses 877 # Number of cache demand misses -system.ruby.l2_cntrl0.L2cache.demand_accesses 915 # Number of cache demand accesses system.ruby.network.routers1.percent_links_utilized 1.886681 system.ruby.network.routers1.msg_count.Request_Control::1 915 system.ruby.network.routers1.msg_count.Request_Control::2 877 @@ -377,7 +383,6 @@ system.ruby.network.msg_byte.Response_Control 72 system.ruby.network.msg_byte.Writeback_Data 377352 system.ruby.network.msg_byte.Writeback_Control 1728 system.ruby.network.msg_byte.Persistent_Control 18432 -system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks system.ruby.network.routers0.throttle0.link_utilization 1.970739 system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 894 system.ruby.network.routers0.throttle0.msg_count.ResponseL2hit_Data::4 40 @@ -613,6 +618,37 @@ system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 439.837439 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 188.502356 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 1 2.17% 2.17% | 5 10.87% 13.04% | 8 17.39% 30.43% | 9 19.57% 50.00% | 17 36.96% 86.96% | 3 6.52% 93.48% | 1 2.17% 95.65% | 2 4.35% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total 46 +system.ruby.Directory_Controller.GETX 808 0.00% 0.00% +system.ruby.Directory_Controller.GETS 105 0.00% 0.00% +system.ruby.Directory_Controller.Lockdown 192 0.00% 0.00% +system.ruby.Directory_Controller.Unlockdown 192 0.00% 0.00% +system.ruby.Directory_Controller.Data_Owner 1 0.00% 0.00% +system.ruby.Directory_Controller.Data_All_Tokens 792 0.00% 0.00% +system.ruby.Directory_Controller.Ack_Owner_All_Tokens 72 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Data 868 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Ack 788 0.00% 0.00% +system.ruby.Directory_Controller.O.GETX 778 0.00% 0.00% +system.ruby.Directory_Controller.O.GETS 81 0.00% 0.00% +system.ruby.Directory_Controller.O.Lockdown 9 0.00% 0.00% +system.ruby.Directory_Controller.NO.GETX 6 0.00% 0.00% +system.ruby.Directory_Controller.NO.GETS 3 0.00% 0.00% +system.ruby.Directory_Controller.NO.Lockdown 169 0.00% 0.00% +system.ruby.Directory_Controller.NO.Data_Owner 1 0.00% 0.00% +system.ruby.Directory_Controller.NO.Data_All_Tokens 787 0.00% 0.00% +system.ruby.Directory_Controller.NO.Ack_Owner_All_Tokens 72 0.00% 0.00% +system.ruby.Directory_Controller.L.GETX 7 0.00% 0.00% +system.ruby.Directory_Controller.L.GETS 1 0.00% 0.00% +system.ruby.Directory_Controller.L.Unlockdown 191 0.00% 0.00% +system.ruby.Directory_Controller.L.Data_All_Tokens 5 0.00% 0.00% +system.ruby.Directory_Controller.O_W.Memory_Data 1 0.00% 0.00% +system.ruby.Directory_Controller.O_W.Memory_Ack 788 0.00% 0.00% +system.ruby.Directory_Controller.L_O_W.GETX 17 0.00% 0.00% +system.ruby.Directory_Controller.L_O_W.GETS 20 0.00% 0.00% +system.ruby.Directory_Controller.L_O_W.Unlockdown 1 0.00% 0.00% +system.ruby.Directory_Controller.L_O_W.Memory_Data 8 0.00% 0.00% +system.ruby.Directory_Controller.L_NO_W.Memory_Data 14 0.00% 0.00% +system.ruby.Directory_Controller.NO_W.Lockdown 14 0.00% 0.00% +system.ruby.Directory_Controller.NO_W.Memory_Data 845 0.00% 0.00% system.ruby.L1Cache_Controller.Load 44 0.00% 0.00% system.ruby.L1Cache_Controller.Ifetch 56 0.00% 0.00% system.ruby.L1Cache_Controller.Store 917 0.00% 0.00% @@ -690,36 +726,5 @@ system.ruby.L2Cache_Controller.I_L.Writeback_All_Tokens 63 0.00% system.ruby.L2Cache_Controller.I_L.Persistent_GETX 149 0.00% 0.00% system.ruby.L2Cache_Controller.I_L.Persistent_GETS 15 0.00% 0.00% system.ruby.L2Cache_Controller.I_L.Own_Lock_or_Unlock 26 0.00% 0.00% -system.ruby.Directory_Controller.GETX 808 0.00% 0.00% -system.ruby.Directory_Controller.GETS 105 0.00% 0.00% -system.ruby.Directory_Controller.Lockdown 192 0.00% 0.00% -system.ruby.Directory_Controller.Unlockdown 192 0.00% 0.00% -system.ruby.Directory_Controller.Data_Owner 1 0.00% 0.00% -system.ruby.Directory_Controller.Data_All_Tokens 792 0.00% 0.00% -system.ruby.Directory_Controller.Ack_Owner_All_Tokens 72 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Data 868 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Ack 788 0.00% 0.00% -system.ruby.Directory_Controller.O.GETX 778 0.00% 0.00% -system.ruby.Directory_Controller.O.GETS 81 0.00% 0.00% -system.ruby.Directory_Controller.O.Lockdown 9 0.00% 0.00% -system.ruby.Directory_Controller.NO.GETX 6 0.00% 0.00% -system.ruby.Directory_Controller.NO.GETS 3 0.00% 0.00% -system.ruby.Directory_Controller.NO.Lockdown 169 0.00% 0.00% -system.ruby.Directory_Controller.NO.Data_Owner 1 0.00% 0.00% -system.ruby.Directory_Controller.NO.Data_All_Tokens 787 0.00% 0.00% -system.ruby.Directory_Controller.NO.Ack_Owner_All_Tokens 72 0.00% 0.00% -system.ruby.Directory_Controller.L.GETX 7 0.00% 0.00% -system.ruby.Directory_Controller.L.GETS 1 0.00% 0.00% -system.ruby.Directory_Controller.L.Unlockdown 191 0.00% 0.00% -system.ruby.Directory_Controller.L.Data_All_Tokens 5 0.00% 0.00% -system.ruby.Directory_Controller.O_W.Memory_Data 1 0.00% 0.00% -system.ruby.Directory_Controller.O_W.Memory_Ack 788 0.00% 0.00% -system.ruby.Directory_Controller.L_O_W.GETX 17 0.00% 0.00% -system.ruby.Directory_Controller.L_O_W.GETS 20 0.00% 0.00% -system.ruby.Directory_Controller.L_O_W.Unlockdown 1 0.00% 0.00% -system.ruby.Directory_Controller.L_O_W.Memory_Data 8 0.00% 0.00% -system.ruby.Directory_Controller.L_NO_W.Memory_Data 14 0.00% 0.00% -system.ruby.Directory_Controller.NO_W.Lockdown 14 0.00% 0.00% -system.ruby.Directory_Controller.NO_W.Memory_Data 845 0.00% 0.00% ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt index b61f52446..b30732380 100644 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt @@ -4,9 +4,9 @@ sim_seconds 0.000180 # Nu sim_ticks 180391 # Number of ticks simulated final_tick 180391 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 754935 # Simulator tick rate (ticks/s) -host_mem_usage 435272 # Number of bytes of host memory used -host_seconds 0.24 # Real time elapsed on the host +host_tick_rate 2115130 # Simulator tick rate (ticks/s) +host_mem_usage 447992 # Number of bytes of host memory used +host_seconds 0.09 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks system.mem_ctrls.bytes_read::ruby.dir_cntrl0 54784 # Number of bytes read from this memory @@ -238,29 +238,34 @@ system.mem_ctrls.readRowHitRate 81.81 # Ro system.mem_ctrls.writeRowHitRate 94.85 # Row buffer hit rate for writes system.mem_ctrls.avgGap 110.69 # Average gap between requests system.mem_ctrls.pageHitRate 88.14 # Row buffer hit rate, read and write combined -system.mem_ctrls.memoryStateTime::IDLE 348 # Time in different power states -system.mem_ctrls.memoryStateTime::REF 5980 # Time in different power states -system.mem_ctrls.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls.memoryStateTime::ACT 173024 # Time in different power states -system.mem_ctrls.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrls.actEnergy::0 1028160 # Energy for activate commands per rank (pJ) -system.mem_ctrls.actEnergy::1 0 # Energy for activate commands per rank (pJ) -system.mem_ctrls.preEnergy::0 571200 # Energy for precharge commands per rank (pJ) -system.mem_ctrls.preEnergy::1 0 # Energy for precharge commands per rank (pJ) -system.mem_ctrls.readEnergy::0 8910720 # Energy for read commands per rank (pJ) -system.mem_ctrls.readEnergy::1 0 # Energy for read commands per rank (pJ) -system.mem_ctrls.writeEnergy::0 6770304 # Energy for write commands per rank (pJ) -system.mem_ctrls.writeEnergy::1 0 # Energy for write commands per rank (pJ) -system.mem_ctrls.refreshEnergy::0 11696880 # Energy for refresh commands per rank (pJ) -system.mem_ctrls.refreshEnergy::1 11696880 # Energy for refresh commands per rank (pJ) -system.mem_ctrls.actBackEnergy::0 121998240 # Energy for active background per rank (pJ) -system.mem_ctrls.actBackEnergy::1 3870072 # Energy for active background per rank (pJ) -system.mem_ctrls.preBackEnergy::0 586800 # Energy for precharge background per rank (pJ) -system.mem_ctrls.preBackEnergy::1 104208000 # Energy for precharge background per rank (pJ) -system.mem_ctrls.totalEnergy::0 151562304 # Total energy per rank (pJ) -system.mem_ctrls.totalEnergy::1 119774952 # Total energy per rank (pJ) -system.mem_ctrls.averagePower::0 845.120967 # Core power per rank (mW) -system.mem_ctrls.averagePower::1 667.872687 # Core power per rank (mW) +system.mem_ctrls_0.actEnergy 1028160 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 571200 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 8910720 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 6770304 # Energy for write commands per rank (pJ) +system.mem_ctrls_0.refreshEnergy 11696880 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_0.actBackEnergy 121998240 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 586800 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.totalEnergy 151562304 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 845.120967 # Core power per rank (mW) +system.mem_ctrls_0.memoryStateTime::IDLE 348 # Time in different power states +system.mem_ctrls_0.memoryStateTime::REF 5980 # Time in different power states +system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 173024 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls_1.actEnergy 0 # Energy for activate commands per rank (pJ) +system.mem_ctrls_1.preEnergy 0 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_1.readEnergy 0 # Energy for read commands per rank (pJ) +system.mem_ctrls_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls_1.refreshEnergy 11696880 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_1.actBackEnergy 3870072 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 104199600 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.totalEnergy 119766552 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 667.877986 # Core power per rank (mW) +system.mem_ctrls_1.memoryStateTime::IDLE 173358 # Time in different power states +system.mem_ctrls_1.memoryStateTime::REF 5980 # Time in different power states +system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 0 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.ruby.clk_domain.clock 1 # Clock period in ticks system.ruby.outstanding_req_hist::bucket_size 2 system.ruby.outstanding_req_hist::max_bucket 19 @@ -295,7 +300,9 @@ system.ruby.miss_latency_hist::stdev 1102.294906 system.ruby.miss_latency_hist | 91 10.67% 10.67% | 6 0.70% 11.37% | 126 14.77% 26.14% | 516 60.49% 86.64% | 112 13.13% 99.77% | 2 0.23% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.miss_latency_hist::total 853 system.ruby.Directory.incomplete_times 853 -system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks +system.ruby.dir_cntrl0.probeFilter.demand_hits 0 # Number of cache demand hits +system.ruby.dir_cntrl0.probeFilter.demand_misses 0 # Number of cache demand misses +system.ruby.dir_cntrl0.probeFilter.demand_accesses 0 # Number of cache demand accesses system.ruby.l1_cntrl0.L1Dcache.demand_hits 80 # Number of cache demand hits system.ruby.l1_cntrl0.L1Dcache.demand_misses 854 # Number of cache demand misses system.ruby.l1_cntrl0.L1Dcache.demand_accesses 934 # Number of cache demand accesses @@ -308,6 +315,7 @@ system.ruby.l1_cntrl0.L2cache.demand_accesses 912 system.ruby.l1_cntrl0.sequencer.store_waiting_on_load 7 # Number of times a store aliased with a pending load system.ruby.l1_cntrl0.sequencer.store_waiting_on_store 86 # Number of times a store aliased with a pending store system.ruby.l1_cntrl0.sequencer.load_waiting_on_store 5 # Number of times a load aliased with a pending store +system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks system.ruby.network.routers0.percent_links_utilized 2.513845 system.ruby.network.routers0.msg_count.Request_Control::2 858 system.ruby.network.routers0.msg_count.Response_Data::4 856 @@ -323,9 +331,6 @@ system.ruby.network.routers0.msg_bytes.Writeback_Control::2 6808 system.ruby.network.routers0.msg_bytes.Writeback_Control::3 6792 system.ruby.network.routers0.msg_bytes.Writeback_Control::5 616 system.ruby.network.routers0.msg_bytes.Unblock_Control::5 6816 -system.ruby.dir_cntrl0.probeFilter.demand_hits 0 # Number of cache demand hits -system.ruby.dir_cntrl0.probeFilter.demand_misses 0 # Number of cache demand misses -system.ruby.dir_cntrl0.probeFilter.demand_accesses 0 # Number of cache demand accesses system.ruby.network.routers1.percent_links_utilized 2.513291 system.ruby.network.routers1.msg_count.Request_Control::2 856 system.ruby.network.routers1.msg_count.Response_Data::4 856 @@ -598,6 +603,30 @@ system.ruby.FLUSH.L1Cache.hit_type_mach_latency_hist::gmean 3955.937145 system.ruby.FLUSH.L1Cache.hit_type_mach_latency_hist::stdev 544.674521 system.ruby.FLUSH.L1Cache.hit_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 2 66.67% 66.67% | 1 33.33% 100.00% | 0 0.00% 100.00% system.ruby.FLUSH.L1Cache.hit_type_mach_latency_hist::total 3 +system.ruby.Directory_Controller.GETX 768 0.00% 0.00% +system.ruby.Directory_Controller.GETS 88 0.00% 0.00% +system.ruby.Directory_Controller.PUT 927 0.00% 0.00% +system.ruby.Directory_Controller.UnblockM 851 0.00% 0.00% +system.ruby.Directory_Controller.Writeback_Exclusive_Clean 77 0.00% 0.00% +system.ruby.Directory_Controller.Writeback_Exclusive_Dirty 772 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Data 856 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Ack 772 0.00% 0.00% +system.ruby.Directory_Controller.GETF 3 0.00% 0.00% +system.ruby.Directory_Controller.PUTF 3 0.00% 0.00% +system.ruby.Directory_Controller.NO.PUT 846 0.00% 0.00% +system.ruby.Directory_Controller.E.GETX 768 0.00% 0.00% +system.ruby.Directory_Controller.E.GETS 85 0.00% 0.00% +system.ruby.Directory_Controller.E.GETF 3 0.00% 0.00% +system.ruby.Directory_Controller.NO_B.PUT 81 0.00% 0.00% +system.ruby.Directory_Controller.NO_B.UnblockM 851 0.00% 0.00% +system.ruby.Directory_Controller.NO_B_W.Memory_Data 853 0.00% 0.00% +system.ruby.Directory_Controller.WB.GETS 2 0.00% 0.00% +system.ruby.Directory_Controller.WB.Writeback_Exclusive_Clean 77 0.00% 0.00% +system.ruby.Directory_Controller.WB.Writeback_Exclusive_Dirty 772 0.00% 0.00% +system.ruby.Directory_Controller.WB_E_W.GETS 1 0.00% 0.00% +system.ruby.Directory_Controller.WB_E_W.Memory_Ack 772 0.00% 0.00% +system.ruby.Directory_Controller.NO_F.PUTF 3 0.00% 0.00% +system.ruby.Directory_Controller.NO_F_W.Memory_Data 3 0.00% 0.00% system.ruby.L1Cache_Controller.Load 44 0.00% 0.00% system.ruby.L1Cache_Controller.Ifetch 65 0.00% 0.00% system.ruby.L1Cache_Controller.Store 914 0.00% 0.00% @@ -651,29 +680,5 @@ system.ruby.L1Cache_Controller.MMT.Complete_L2_to_L1 47 0.00% system.ruby.L1Cache_Controller.MI_F.Writeback_Ack 3 0.00% 0.00% system.ruby.L1Cache_Controller.IM_F.Exclusive_Data 3 0.00% 0.00% system.ruby.L1Cache_Controller.MM_WF.All_acks_no_sharers 3 0.00% 0.00% -system.ruby.Directory_Controller.GETX 768 0.00% 0.00% -system.ruby.Directory_Controller.GETS 88 0.00% 0.00% -system.ruby.Directory_Controller.PUT 927 0.00% 0.00% -system.ruby.Directory_Controller.UnblockM 851 0.00% 0.00% -system.ruby.Directory_Controller.Writeback_Exclusive_Clean 77 0.00% 0.00% -system.ruby.Directory_Controller.Writeback_Exclusive_Dirty 772 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Data 856 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Ack 772 0.00% 0.00% -system.ruby.Directory_Controller.GETF 3 0.00% 0.00% -system.ruby.Directory_Controller.PUTF 3 0.00% 0.00% -system.ruby.Directory_Controller.NO.PUT 846 0.00% 0.00% -system.ruby.Directory_Controller.E.GETX 768 0.00% 0.00% -system.ruby.Directory_Controller.E.GETS 85 0.00% 0.00% -system.ruby.Directory_Controller.E.GETF 3 0.00% 0.00% -system.ruby.Directory_Controller.NO_B.PUT 81 0.00% 0.00% -system.ruby.Directory_Controller.NO_B.UnblockM 851 0.00% 0.00% -system.ruby.Directory_Controller.NO_B_W.Memory_Data 853 0.00% 0.00% -system.ruby.Directory_Controller.WB.GETS 2 0.00% 0.00% -system.ruby.Directory_Controller.WB.Writeback_Exclusive_Clean 77 0.00% 0.00% -system.ruby.Directory_Controller.WB.Writeback_Exclusive_Dirty 772 0.00% 0.00% -system.ruby.Directory_Controller.WB_E_W.GETS 1 0.00% 0.00% -system.ruby.Directory_Controller.WB_E_W.Memory_Ack 772 0.00% 0.00% -system.ruby.Directory_Controller.NO_F.PUTF 3 0.00% 0.00% -system.ruby.Directory_Controller.NO_F_W.Memory_Data 3 0.00% 0.00% ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt index 013496257..318f529ad 100644 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt @@ -4,9 +4,9 @@ sim_seconds 0.000233 # Nu sim_ticks 233251 # Number of ticks simulated final_tick 233251 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 3056189 # Simulator tick rate (ticks/s) -host_mem_usage 433064 # Number of bytes of host memory used -host_seconds 0.08 # Real time elapsed on the host +host_tick_rate 4652644 # Simulator tick rate (ticks/s) +host_mem_usage 446260 # Number of bytes of host memory used +host_seconds 0.05 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks system.mem_ctrls.bytes_read::ruby.dir_cntrl0 58944 # Number of bytes read from this memory @@ -233,29 +233,34 @@ system.mem_ctrls.readRowHitRate 80.66 # Ro system.mem_ctrls.writeRowHitRate 95.51 # Row buffer hit rate for writes system.mem_ctrls.avgGap 126.67 # Average gap between requests system.mem_ctrls.pageHitRate 88.14 # Row buffer hit rate, read and write combined -system.mem_ctrls.memoryStateTime::IDLE 697 # Time in different power states -system.mem_ctrls.memoryStateTime::REF 7540 # Time in different power states -system.mem_ctrls.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls.memoryStateTime::ACT 218097 # Time in different power states -system.mem_ctrls.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrls.actEnergy::0 1171800 # Energy for activate commands per rank (pJ) -system.mem_ctrls.actEnergy::1 0 # Energy for activate commands per rank (pJ) -system.mem_ctrls.preEnergy::0 651000 # Energy for precharge commands per rank (pJ) -system.mem_ctrls.preEnergy::1 0 # Energy for precharge commands per rank (pJ) -system.mem_ctrls.readEnergy::0 9597120 # Energy for read commands per rank (pJ) -system.mem_ctrls.readEnergy::1 0 # Energy for read commands per rank (pJ) -system.mem_ctrls.writeEnergy::0 7848576 # Energy for write commands per rank (pJ) -system.mem_ctrls.writeEnergy::1 0 # Energy for write commands per rank (pJ) -system.mem_ctrls.refreshEnergy::0 14748240 # Energy for refresh commands per rank (pJ) -system.mem_ctrls.refreshEnergy::1 14748240 # Energy for refresh commands per rank (pJ) -system.mem_ctrls.actBackEnergy::0 153780300 # Energy for active background per rank (pJ) -system.mem_ctrls.actBackEnergy::1 4879656 # Energy for active background per rank (pJ) -system.mem_ctrls.preBackEnergy::0 737400 # Energy for precharge background per rank (pJ) -system.mem_ctrls.preBackEnergy::1 131352000 # Energy for precharge background per rank (pJ) -system.mem_ctrls.totalEnergy::0 188534436 # Total energy per rank (pJ) -system.mem_ctrls.totalEnergy::1 150979896 # Total energy per rank (pJ) -system.mem_ctrls.averagePower::0 834.023888 # Core power per rank (mW) -system.mem_ctrls.averagePower::1 667.893052 # Core power per rank (mW) +system.mem_ctrls_0.actEnergy 1171800 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 651000 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 9597120 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 7848576 # Energy for write commands per rank (pJ) +system.mem_ctrls_0.refreshEnergy 14748240 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_0.actBackEnergy 153780300 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 737400 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.totalEnergy 188534436 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 834.023888 # Core power per rank (mW) +system.mem_ctrls_0.memoryStateTime::IDLE 697 # Time in different power states +system.mem_ctrls_0.memoryStateTime::REF 7540 # Time in different power states +system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 218097 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls_1.actEnergy 0 # Energy for activate commands per rank (pJ) +system.mem_ctrls_1.preEnergy 0 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_1.readEnergy 0 # Energy for read commands per rank (pJ) +system.mem_ctrls_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls_1.refreshEnergy 14748240 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_1.actBackEnergy 4879656 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 131343600 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.totalEnergy 150971496 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 667.897257 # Core power per rank (mW) +system.mem_ctrls_1.memoryStateTime::IDLE 218514 # Time in different power states +system.mem_ctrls_1.memoryStateTime::REF 7540 # Time in different power states +system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 0 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.ruby.clk_domain.clock 1 # Clock period in ticks system.ruby.delayHist::bucket_size 2 # delay histogram for all message system.ruby.delayHist::max_bucket 19 # delay histogram for all message @@ -297,7 +302,6 @@ system.ruby.miss_latency_hist::stdev 532.898268 system.ruby.miss_latency_hist | 4 0.43% 0.43% | 4 0.43% 0.87% | 28 3.04% 3.91% | 584 63.41% 67.32% | 297 32.25% 99.57% | 4 0.43% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.miss_latency_hist::total 921 system.ruby.Directory.incomplete_times 921 -system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks system.ruby.l1_cntrl0.cacheMemory.demand_hits 35 # Number of cache demand hits system.ruby.l1_cntrl0.cacheMemory.demand_misses 923 # Number of cache demand misses system.ruby.l1_cntrl0.cacheMemory.demand_accesses 958 # Number of cache demand accesses @@ -305,6 +309,7 @@ system.ruby.l1_cntrl0.sequencer.store_waiting_on_load 14 system.ruby.l1_cntrl0.sequencer.store_waiting_on_store 117 # Number of times a store aliased with a pending store system.ruby.l1_cntrl0.sequencer.load_waiting_on_store 11 # Number of times a load aliased with a pending store system.ruby.l1_cntrl0.sequencer.load_waiting_on_load 1 # Number of times a load aliased with a pending load +system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks system.ruby.network.routers0.percent_links_utilized 1.971696 system.ruby.network.routers0.msg_count.Control::2 921 system.ruby.network.routers0.msg_count.Data::2 919 @@ -488,6 +493,14 @@ system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 3875.103542 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 441.985729 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 1.89% 1.89% | 13 24.53% 26.42% | 19 35.85% 62.26% | 17 32.08% 94.34% | 3 5.66% 100.00% system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total 53 +system.ruby.Directory_Controller.GETX 921 0.00% 0.00% +system.ruby.Directory_Controller.PUTX 918 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Data 921 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Ack 918 0.00% 0.00% +system.ruby.Directory_Controller.I.GETX 921 0.00% 0.00% +system.ruby.Directory_Controller.M.PUTX 918 0.00% 0.00% +system.ruby.Directory_Controller.IM.Memory_Data 921 0.00% 0.00% +system.ruby.Directory_Controller.MI.Memory_Ack 918 0.00% 0.00% system.ruby.L1Cache_Controller.Load 46 0.00% 0.00% system.ruby.L1Cache_Controller.Ifetch 55 0.00% 0.00% system.ruby.L1Cache_Controller.Store 857 0.00% 0.00% @@ -504,13 +517,5 @@ system.ruby.L1Cache_Controller.M.Replacement 920 0.00% 0.00% system.ruby.L1Cache_Controller.MI.Writeback_Ack 918 0.00% 0.00% system.ruby.L1Cache_Controller.IS.Data 98 0.00% 0.00% system.ruby.L1Cache_Controller.IM.Data 823 0.00% 0.00% -system.ruby.Directory_Controller.GETX 921 0.00% 0.00% -system.ruby.Directory_Controller.PUTX 918 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Data 921 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Ack 918 0.00% 0.00% -system.ruby.Directory_Controller.I.GETX 921 0.00% 0.00% -system.ruby.Directory_Controller.M.PUTX 918 0.00% 0.00% -system.ruby.Directory_Controller.IM.Memory_Data 921 0.00% 0.00% -system.ruby.Directory_Controller.MI.Memory_Ack 918 0.00% 0.00% ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/stats.txt b/tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/stats.txt index 8a9cf2f50..0808c4e4e 100644 --- a/tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/stats.txt +++ b/tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/stats.txt @@ -4,9 +4,9 @@ sim_seconds 0.100000 # Nu sim_ticks 100000000000 # Number of ticks simulated final_tick 100000000000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_tick_rate 8686903737 # Simulator tick rate (ticks/s) -host_mem_usage 208524 # Number of bytes of host memory used -host_seconds 11.51 # Real time elapsed on the host +host_tick_rate 8581932612 # Simulator tick rate (ticks/s) +host_mem_usage 264172 # Number of bytes of host memory used +host_seconds 11.65 # Real time elapsed on the host system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu 106649408 # Number of bytes read from this memory @@ -27,46 +27,46 @@ system.physmem.readReqs 1666397 # Nu system.physmem.writeReqs 1666879 # Number of write requests accepted system.physmem.readBursts 1666397 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 1666879 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 106647872 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 1536 # Total number of bytes read from write queue +system.physmem.bytesReadDRAM 106648000 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 1408 # Total number of bytes read from write queue system.physmem.bytesWritten 106676864 # Total number of bytes written to DRAM system.physmem.bytesReadSys 106649408 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 106680256 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 24 # Number of DRAM read bursts serviced by the write queue +system.physmem.servicedByWrQ 22 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 30 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 104030 # Per bank write bursts -system.physmem.perBankRdBursts::1 103994 # Per bank write bursts +system.physmem.perBankRdBursts::1 103995 # Per bank write bursts system.physmem.perBankRdBursts::2 104918 # Per bank write bursts -system.physmem.perBankRdBursts::3 104596 # Per bank write bursts +system.physmem.perBankRdBursts::3 104597 # Per bank write bursts system.physmem.perBankRdBursts::4 103869 # Per bank write bursts system.physmem.perBankRdBursts::5 103935 # Per bank write bursts -system.physmem.perBankRdBursts::6 103649 # Per bank write bursts +system.physmem.perBankRdBursts::6 103648 # Per bank write bursts system.physmem.perBankRdBursts::7 104313 # Per bank write bursts -system.physmem.perBankRdBursts::8 103869 # Per bank write bursts +system.physmem.perBankRdBursts::8 103868 # Per bank write bursts system.physmem.perBankRdBursts::9 104354 # Per bank write bursts system.physmem.perBankRdBursts::10 103835 # Per bank write bursts system.physmem.perBankRdBursts::11 104272 # Per bank write bursts -system.physmem.perBankRdBursts::12 104076 # Per bank write bursts -system.physmem.perBankRdBursts::13 104034 # Per bank write bursts +system.physmem.perBankRdBursts::12 104077 # Per bank write bursts +system.physmem.perBankRdBursts::13 104035 # Per bank write bursts system.physmem.perBankRdBursts::14 104583 # Per bank write bursts system.physmem.perBankRdBursts::15 104046 # Per bank write bursts system.physmem.perBankWrBursts::0 104357 # Per bank write bursts -system.physmem.perBankWrBursts::1 104090 # Per bank write bursts +system.physmem.perBankWrBursts::1 104091 # Per bank write bursts system.physmem.perBankWrBursts::2 104175 # Per bank write bursts system.physmem.perBankWrBursts::3 103885 # Per bank write bursts system.physmem.perBankWrBursts::4 104730 # Per bank write bursts -system.physmem.perBankWrBursts::5 104508 # Per bank write bursts -system.physmem.perBankWrBursts::6 104083 # Per bank write bursts +system.physmem.perBankWrBursts::5 104507 # Per bank write bursts +system.physmem.perBankWrBursts::6 104082 # Per bank write bursts system.physmem.perBankWrBursts::7 104226 # Per bank write bursts -system.physmem.perBankWrBursts::8 104319 # Per bank write bursts +system.physmem.perBankWrBursts::8 104320 # Per bank write bursts system.physmem.perBankWrBursts::9 104219 # Per bank write bursts -system.physmem.perBankWrBursts::10 104229 # Per bank write bursts -system.physmem.perBankWrBursts::11 103701 # Per bank write bursts -system.physmem.perBankWrBursts::12 104102 # Per bank write bursts +system.physmem.perBankWrBursts::10 104228 # Per bank write bursts +system.physmem.perBankWrBursts::11 103702 # Per bank write bursts +system.physmem.perBankWrBursts::12 104104 # Per bank write bursts system.physmem.perBankWrBursts::13 103983 # Per bank write bursts system.physmem.perBankWrBursts::14 104296 # Per bank write bursts -system.physmem.perBankWrBursts::15 103923 # Per bank write bursts +system.physmem.perBankWrBursts::15 103921 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry system.physmem.totGap 99999956143 # Total gap between requests @@ -84,21 +84,21 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 1666879 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 749477 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 767791 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 84595 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 34424 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 14110 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 7738 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 4506 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 2212 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 927 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 435 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 124 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 24 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 8 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 750686 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 769672 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 84683 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 33857 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 13541 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 7101 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 3883 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1779 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 720 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 340 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 84 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 25 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see @@ -131,33 +131,33 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 11355 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 15130 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 38121 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 87361 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 105787 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 108512 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 113649 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 112259 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 107672 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 105658 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 125741 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 107375 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 108402 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 107991 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 100241 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 100173 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 100040 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 11292 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 15175 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 37870 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 87757 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 105663 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 108535 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 113878 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 112245 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 107898 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 105677 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 126067 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 107322 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 108328 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 108001 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 100239 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 100135 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 100039 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 100007 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 3871 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 3019 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 2113 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 1304 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 696 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 272 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 69 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 3759 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 2878 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 2001 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 1208 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 594 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 208 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 50 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see @@ -180,12 +180,12 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 3296263 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 64.716933 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 64.192638 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 23.994317 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 3288284 99.76% 99.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 5824 0.18% 99.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 3296308 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 64.716127 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 64.192082 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 23.993116 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 3288370 99.76% 99.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 5783 0.18% 99.93% # Bytes accessed per row activation system.physmem.bytesPerActivate::256-383 32 0.00% 99.94% # Bytes accessed per row activation system.physmem.bytesPerActivate::384-511 32 0.00% 99.94% # Bytes accessed per row activation system.physmem.bytesPerActivate::512-639 32 0.00% 99.94% # Bytes accessed per row activation @@ -193,41 +193,41 @@ system.physmem.bytesPerActivate::640-767 32 0.00% 99.94% # By system.physmem.bytesPerActivate::768-895 32 0.00% 99.94% # Bytes accessed per row activation system.physmem.bytesPerActivate::896-1023 32 0.00% 99.94% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 1963 0.06% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 3296263 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 99238 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 16.791612 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 15.446176 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 106.010489 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 99237 100.00% 100.00% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::total 3296308 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 99265 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 16.787065 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 15.442881 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 105.996031 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 99264 100.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::32768-34815 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 99238 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 99238 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.796247 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.714914 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.763911 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 78818 79.42% 79.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 3091 3.11% 82.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 3042 3.07% 85.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 1750 1.76% 87.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 1374 1.38% 88.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 8750 8.82% 97.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 1949 1.96% 99.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 293 0.30% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 65 0.07% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 43 0.04% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 29 0.03% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 17 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 10 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::29 2 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30 4 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 99265 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 99265 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.791679 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.710831 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.758038 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 78980 79.56% 79.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 3022 3.04% 82.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 3011 3.03% 85.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 1773 1.79% 87.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 1415 1.43% 88.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 8615 8.68% 97.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 2003 2.02% 99.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 293 0.30% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 66 0.07% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 33 0.03% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 21 0.02% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 21 0.02% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 8 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::29 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30 2 0.00% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::32 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 99238 # Writes before turning the bus around for reads -system.physmem.totQLat 61644213329 # Total ticks spent queuing -system.physmem.totMemAccLat 92888707079 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 8331865000 # Total ticks spent in databus transfers -system.physmem.avgQLat 36993.05 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::total 99265 # Writes before turning the bus around for reads +system.physmem.totQLat 60762575042 # Total ticks spent queuing +system.physmem.totMemAccLat 92007106292 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 8331875000 # Total ticks spent in databus transfers +system.physmem.avgQLat 36463.93 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 55743.05 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 55213.93 # Average memory access latency per DRAM burst system.physmem.avgRdBW 1066.48 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 1066.77 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 1066.49 # Average system read bandwidth in MiByte/s @@ -236,37 +236,45 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 16.67 # Data bus utilization in percentage system.physmem.busUtilRead 8.33 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 8.33 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.72 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.71 # Average read queue length when enqueuing system.physmem.avgWrQLen 25.44 # Average write queue length when enqueuing -system.physmem.readRowHits 32184 # Number of row buffer hits during reads -system.physmem.writeRowHits 4741 # Number of row buffer hits during writes +system.physmem.readRowHits 32179 # Number of row buffer hits during reads +system.physmem.writeRowHits 4705 # Number of row buffer hits during writes system.physmem.readRowHitRate 1.93 # Row buffer hit rate for reads system.physmem.writeRowHitRate 0.28 # Row buffer hit rate for writes system.physmem.avgGap 30000.50 # Average gap between requests system.physmem.pageHitRate 1.11 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 5342990 # Time in different power states -system.physmem.memoryStateTime::REF 3339180000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 96654559510 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 12463083360 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 12456445680 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 6800293500 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 6796671750 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 6499693200 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 6497868000 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 5404598640 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 5396297760 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 6531436080 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 6531436080 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 67803083460 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 67799803680 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 523052250 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 525929250 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 106025240490 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 106004452200 # Total energy per rank (pJ) -system.physmem.averagePower::0 1060.262279 # Core power per rank (mW) -system.physmem.averagePower::1 1060.054394 # Core power per rank (mW) +system.physmem_0.actEnergy 12463295040 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 6800409000 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 6499701000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 5404592160 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 6531436080 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 67776382665 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 546474000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 106022289945 # Total energy per rank (pJ) +system.physmem_0.averagePower 1060.232773 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 531628571 # Time in different power states +system.physmem_0.memoryStateTime::REF 3339180000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 96128273929 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 12456559080 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 6796733625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 6497875800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 5396304240 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 6531436080 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 67774932585 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 547746000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 106001587410 # Total energy per rank (pJ) +system.physmem_1.averagePower 1060.025746 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 534269274 # Time in different power states +system.physmem_1.memoryStateTime::REF 3339180000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 96125633226 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.numPackets 3333276 # Number of packets generated +system.cpu.numRetries 0 # Number of retries +system.cpu.retryTicks 0 # Time spent waiting due to back-pressure (ticks) system.membus.trans_dist::ReadReq 1666397 # Transaction distribution system.membus.trans_dist::ReadResp 1666397 # Transaction distribution system.membus.trans_dist::WriteReq 1666879 # Transaction distribution @@ -277,7 +285,7 @@ system.membus.pkt_size_system.monitor-master::system.physmem.port 213329664 system.membus.pkt_size::total 213329664 # Cumulative packet size per connected master and slave (bytes) system.membus.reqLayer0.occupancy 11679751447 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 11.7 # Layer utilization (%) -system.membus.respLayer0.occupancy 11427712781 # Layer occupancy (ticks) +system.membus.respLayer0.occupancy 11428907481 # Layer occupancy (ticks) system.membus.respLayer0.utilization 11.4 # Layer utilization (%) system.monitor.readBurstLengthHist::samples 1666397 # Histogram of burst lengths of transmitted packets system.monitor.readBurstLengthHist::mean 64 # Histogram of burst lengths of transmitted packets @@ -331,8 +339,8 @@ system.monitor.writeBurstLengthHist::76-79 0 0.00% 100.00% # system.monitor.writeBurstLengthHist::total 1666879 # Histogram of burst lengths of transmitted packets system.monitor.readBandwidthHist::samples 100 # Histogram of read bandwidth per sample period (bytes/s) system.monitor.readBandwidthHist::mean 1066494080 # Histogram of read bandwidth per sample period (bytes/s) -system.monitor.readBandwidthHist::gmean 1063154546.015704 # Histogram of read bandwidth per sample period (bytes/s) -system.monitor.readBandwidthHist::stdev 107915737.892311 # Histogram of read bandwidth per sample period (bytes/s) +system.monitor.readBandwidthHist::gmean 1063154535.263763 # Histogram of read bandwidth per sample period (bytes/s) +system.monitor.readBandwidthHist::stdev 107915844.091091 # Histogram of read bandwidth per sample period (bytes/s) system.monitor.readBandwidthHist::0-1.34218e+08 0 0.00% 0.00% # Histogram of read bandwidth per sample period (bytes/s) system.monitor.readBandwidthHist::1.34218e+08-2.68435e+08 0 0.00% 0.00% # Histogram of read bandwidth per sample period (bytes/s) system.monitor.readBandwidthHist::2.68435e+08-4.02653e+08 0 0.00% 0.00% # Histogram of read bandwidth per sample period (bytes/s) @@ -384,34 +392,34 @@ system.monitor.writeBandwidthHist::total 100 # Hi system.monitor.averageWriteBandwidth 1066802560 0.00% 0.00% # Average write bandwidth (bytes/s) system.monitor.totalWrittenBytes 106680256 # Number of bytes written system.monitor.readLatencyHist::samples 1666397 # Read request-response latency -system.monitor.readLatencyHist::mean 75762.275031 # Read request-response latency -system.monitor.readLatencyHist::gmean 69897.504803 # Read request-response latency -system.monitor.readLatencyHist::stdev 42102.080811 # Read request-response latency -system.monitor.readLatencyHist::0-32767 24 0.00% 0.00% # Read request-response latency -system.monitor.readLatencyHist::32768-65535 443180 26.60% 26.60% # Read request-response latency -system.monitor.readLatencyHist::65536-98303 1020210 61.22% 87.82% # Read request-response latency -system.monitor.readLatencyHist::98304-131071 76869 4.61% 92.43% # Read request-response latency -system.monitor.readLatencyHist::131072-163839 59066 3.54% 95.98% # Read request-response latency -system.monitor.readLatencyHist::163840-196607 25573 1.53% 97.51% # Read request-response latency -system.monitor.readLatencyHist::196608-229375 9468 0.57% 98.08% # Read request-response latency -system.monitor.readLatencyHist::229376-262143 7856 0.47% 98.55% # Read request-response latency -system.monitor.readLatencyHist::262144-294911 8007 0.48% 99.03% # Read request-response latency -system.monitor.readLatencyHist::294912-327679 7912 0.47% 99.51% # Read request-response latency -system.monitor.readLatencyHist::327680-360447 4865 0.29% 99.80% # Read request-response latency -system.monitor.readLatencyHist::360448-393215 1179 0.07% 99.87% # Read request-response latency -system.monitor.readLatencyHist::393216-425983 915 0.05% 99.92% # Read request-response latency -system.monitor.readLatencyHist::425984-458751 775 0.05% 99.97% # Read request-response latency -system.monitor.readLatencyHist::458752-491519 416 0.02% 100.00% # Read request-response latency -system.monitor.readLatencyHist::491520-524287 74 0.00% 100.00% # Read request-response latency -system.monitor.readLatencyHist::524288-557055 5 0.00% 100.00% # Read request-response latency -system.monitor.readLatencyHist::557056-589823 1 0.00% 100.00% # Read request-response latency -system.monitor.readLatencyHist::589824-622591 2 0.00% 100.00% # Read request-response latency +system.monitor.readLatencyHist::mean 75229.617239 # Read request-response latency +system.monitor.readLatencyHist::gmean 69644.568825 # Read request-response latency +system.monitor.readLatencyHist::stdev 40693.683003 # Read request-response latency +system.monitor.readLatencyHist::0-32767 22 0.00% 0.00% # Read request-response latency +system.monitor.readLatencyHist::32768-65535 444791 26.69% 26.69% # Read request-response latency +system.monitor.readLatencyHist::65536-98303 1023501 61.42% 88.11% # Read request-response latency +system.monitor.readLatencyHist::98304-131071 76998 4.62% 92.73% # Read request-response latency +system.monitor.readLatencyHist::131072-163839 56964 3.42% 96.15% # Read request-response latency +system.monitor.readLatencyHist::163840-196607 25239 1.51% 97.67% # Read request-response latency +system.monitor.readLatencyHist::196608-229375 9180 0.55% 98.22% # Read request-response latency +system.monitor.readLatencyHist::229376-262143 7794 0.47% 98.69% # Read request-response latency +system.monitor.readLatencyHist::262144-294911 7780 0.47% 99.15% # Read request-response latency +system.monitor.readLatencyHist::294912-327679 7547 0.45% 99.61% # Read request-response latency +system.monitor.readLatencyHist::327680-360447 3313 0.20% 99.80% # Read request-response latency +system.monitor.readLatencyHist::360448-393215 1429 0.09% 99.89% # Read request-response latency +system.monitor.readLatencyHist::393216-425983 850 0.05% 99.94% # Read request-response latency +system.monitor.readLatencyHist::425984-458751 662 0.04% 99.98% # Read request-response latency +system.monitor.readLatencyHist::458752-491519 284 0.02% 100.00% # Read request-response latency +system.monitor.readLatencyHist::491520-524287 42 0.00% 100.00% # Read request-response latency +system.monitor.readLatencyHist::524288-557055 1 0.00% 100.00% # Read request-response latency +system.monitor.readLatencyHist::557056-589823 0 0.00% 100.00% # Read request-response latency +system.monitor.readLatencyHist::589824-622591 0 0.00% 100.00% # Read request-response latency system.monitor.readLatencyHist::622592-655359 0 0.00% 100.00% # Read request-response latency system.monitor.readLatencyHist::total 1666397 # Read request-response latency system.monitor.writeLatencyHist::samples 1666879 # Write request-response latency -system.monitor.writeLatencyHist::mean 10554.999998 # Write request-response latency -system.monitor.writeLatencyHist::gmean 10497.332887 # Write request-response latency -system.monitor.writeLatencyHist::stdev 1184.671741 # Write request-response latency +system.monitor.writeLatencyHist::mean 10556.022655 # Write request-response latency +system.monitor.writeLatencyHist::gmean 10498.307841 # Write request-response latency +system.monitor.writeLatencyHist::stdev 1185.079839 # Write request-response latency system.monitor.writeLatencyHist::0-1023 0 0.00% 0.00% # Write request-response latency system.monitor.writeLatencyHist::1024-2047 0 0.00% 0.00% # Write request-response latency system.monitor.writeLatencyHist::2048-3071 0 0.00% 0.00% # Write request-response latency @@ -421,13 +429,13 @@ system.monitor.writeLatencyHist::5120-6143 0 0.00% 0.00% # system.monitor.writeLatencyHist::6144-7167 0 0.00% 0.00% # Write request-response latency system.monitor.writeLatencyHist::7168-8191 0 0.00% 0.00% # Write request-response latency system.monitor.writeLatencyHist::8192-9215 0 0.00% 0.00% # Write request-response latency -system.monitor.writeLatencyHist::9216-10239 1277601 76.65% 76.65% # Write request-response latency -system.monitor.writeLatencyHist::10240-11263 91250 5.47% 82.12% # Write request-response latency -system.monitor.writeLatencyHist::11264-12287 110692 6.64% 88.76% # Write request-response latency -system.monitor.writeLatencyHist::12288-13311 90268 5.42% 94.18% # Write request-response latency -system.monitor.writeLatencyHist::13312-14335 61253 3.67% 97.85% # Write request-response latency -system.monitor.writeLatencyHist::14336-15359 31832 1.91% 99.76% # Write request-response latency -system.monitor.writeLatencyHist::15360-16383 3983 0.24% 100.00% # Write request-response latency +system.monitor.writeLatencyHist::9216-10239 1276777 76.60% 76.60% # Write request-response latency +system.monitor.writeLatencyHist::10240-11263 91385 5.48% 82.08% # Write request-response latency +system.monitor.writeLatencyHist::11264-12287 111087 6.66% 88.74% # Write request-response latency +system.monitor.writeLatencyHist::12288-13311 90448 5.43% 94.17% # Write request-response latency +system.monitor.writeLatencyHist::13312-14335 61415 3.68% 97.85% # Write request-response latency +system.monitor.writeLatencyHist::14336-15359 31809 1.91% 99.76% # Write request-response latency +system.monitor.writeLatencyHist::15360-16383 3958 0.24% 100.00% # Write request-response latency system.monitor.writeLatencyHist::16384-17407 0 0.00% 100.00% # Write request-response latency system.monitor.writeLatencyHist::17408-18431 0 0.00% 100.00% # Write request-response latency system.monitor.writeLatencyHist::18432-19455 0 0.00% 100.00% # Write request-response latency @@ -518,13 +526,13 @@ system.monitor.ittReqReq::min_value 28000 # Re system.monitor.ittReqReq::max_value 1041309 # Request-to-request inter transaction time system.monitor.ittReqReq::total 3333275 # Request-to-request inter transaction time system.monitor.outstandingReadsHist::samples 100 # Outstanding read transactions -system.monitor.outstandingReadsHist::mean 1.230000 # Outstanding read transactions +system.monitor.outstandingReadsHist::mean 1.210000 # Outstanding read transactions system.monitor.outstandingReadsHist::gmean 0 # Outstanding read transactions -system.monitor.outstandingReadsHist::stdev 1.309291 # Outstanding read transactions -system.monitor.outstandingReadsHist::0 28 28.00% 28.00% # Outstanding read transactions -system.monitor.outstandingReadsHist::1 44 44.00% 72.00% # Outstanding read transactions -system.monitor.outstandingReadsHist::2 17 17.00% 89.00% # Outstanding read transactions -system.monitor.outstandingReadsHist::3 6 6.00% 95.00% # Outstanding read transactions +system.monitor.outstandingReadsHist::stdev 1.281532 # Outstanding read transactions +system.monitor.outstandingReadsHist::0 27 27.00% 27.00% # Outstanding read transactions +system.monitor.outstandingReadsHist::1 46 46.00% 73.00% # Outstanding read transactions +system.monitor.outstandingReadsHist::2 18 18.00% 91.00% # Outstanding read transactions +system.monitor.outstandingReadsHist::3 4 4.00% 95.00% # Outstanding read transactions system.monitor.outstandingReadsHist::4 1 1.00% 96.00% # Outstanding read transactions system.monitor.outstandingReadsHist::5 3 3.00% 99.00% # Outstanding read transactions system.monitor.outstandingReadsHist::6 0 0.00% 99.00% # Outstanding read transactions @@ -617,8 +625,5 @@ system.monitor.writeTransHist::17408-18431 0 0.00% 100.00% # system.monitor.writeTransHist::18432-19455 0 0.00% 100.00% # Histogram of read transactions per sample period system.monitor.writeTransHist::19456-20479 0 0.00% 100.00% # Histogram of read transactions per sample period system.monitor.writeTransHist::total 100 # Histogram of read transactions per sample period -system.cpu.numPackets 3333276 # Number of packets generated -system.cpu.numRetries 0 # Number of retries -system.cpu.retryTicks 0 # Time spent waiting due to back-pressure (ticks) ---------- End Simulation Statistics ---------- |