diff options
| author | Steve Reinhardt <steve.reinhardt@amd.com> | 2016-03-17 10:30:58 -0700 |
|---|---|---|
| committer | Steve Reinhardt <steve.reinhardt@amd.com> | 2016-03-17 10:30:58 -0700 |
| commit | 4fc69db8f89049a881a5f4aa68545840818b124c (patch) | |
| tree | 7388f5b2755f6f4937b7ce9b8ba889f0d48bc403 /tests | |
| parent | dbad391a9b4e861fd3d660069ed448db85144e17 (diff) | |
| download | gem5-4fc69db8f89049a881a5f4aa68545840818b124c.tar.xz | |
stats: update stats for mmap changes
Diffstat (limited to 'tests')
46 files changed, 3801 insertions, 3699 deletions
diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout index 4c5d4c468..072ce04c3 100755 --- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout +++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout @@ -3,9 +3,9 @@ Redirecting stderr to build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing/sim gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 15 2016 19:39:16 -gem5 started Mar 15 2016 19:40:29 -gem5 executing on dinar2c11, pid 3692 +gem5 compiled Mar 16 2016 15:38:19 +gem5 started Mar 16 2016 15:38:47 +gem5 executing on dinar2c11, pid 14352 command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing -re /home/stever/gem5-public/tests/run.py build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt index 19e7a4fbe..63290598f 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt @@ -4,46 +4,46 @@ sim_seconds 0.061602 # Nu sim_ticks 61602281500 # Number of ticks simulated final_tick 61602281500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 59652 # Simulator instruction rate (inst/s) -host_op_rate 105038 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 23259273 # Simulator tick rate (ticks/s) -host_mem_usage 445096 # Number of bytes of host memory used -host_seconds 2648.50 # Real time elapsed on the host +host_inst_rate 60207 # Simulator instruction rate (inst/s) +host_op_rate 106015 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 23475786 # Simulator tick rate (ticks/s) +host_mem_usage 445092 # Number of bytes of host memory used +host_seconds 2624.08 # Real time elapsed on the host sim_insts 157988547 # Number of instructions simulated sim_ops 278192464 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 63872 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1883136 # Number of bytes read from this memory -system.physmem.bytes_read::total 1947008 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1883072 # Number of bytes read from this memory +system.physmem.bytes_read::total 1946944 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 63872 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 63872 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 12160 # Number of bytes written to this memory system.physmem.bytes_written::total 12160 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 998 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 29424 # Number of read requests responded to by this memory -system.physmem.num_reads::total 30422 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 29423 # Number of read requests responded to by this memory +system.physmem.num_reads::total 30421 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 190 # Number of write requests responded to by this memory system.physmem.num_writes::total 190 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.inst 1036845 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 30569257 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 31606102 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 30568218 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 31605063 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 1036845 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 1036845 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_write::writebacks 197395 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::total 197395 # Write bandwidth from this memory (bytes/s) system.physmem.bw_total::writebacks 197395 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 1036845 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 30569257 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 31803497 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 30422 # Number of read requests accepted +system.physmem.bw_total::cpu.data 30568218 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 31802458 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 30421 # Number of read requests accepted system.physmem.writeReqs 190 # Number of write requests accepted -system.physmem.readBursts 30422 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 30421 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 190 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 1941504 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 1941440 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 5504 # Total number of bytes read from write queue system.physmem.bytesWritten 10240 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 1947008 # Total read bytes from the system interface side +system.physmem.bytesReadSys 1946944 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 12160 # Total written bytes from the system interface side system.physmem.servicedByWrQ 86 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 1 # Number of DRAM write bursts merged with an existing one @@ -57,7 +57,7 @@ system.physmem.perBankRdBursts::5 1901 # Pe system.physmem.perBankRdBursts::6 1952 # Per bank write bursts system.physmem.perBankRdBursts::7 1864 # Per bank write bursts system.physmem.perBankRdBursts::8 1938 # Per bank write bursts -system.physmem.perBankRdBursts::9 1932 # Per bank write bursts +system.physmem.perBankRdBursts::9 1931 # Per bank write bursts system.physmem.perBankRdBursts::10 1804 # Per bank write bursts system.physmem.perBankRdBursts::11 1794 # Per bank write bursts system.physmem.perBankRdBursts::12 1792 # Per bank write bursts @@ -89,7 +89,7 @@ system.physmem.readPktSize::2 0 # Re system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 30422 # Read request sizes (log2) +system.physmem.readPktSize::6 30421 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -98,7 +98,7 @@ system.physmem.writePktSize::4 0 # Wr system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 190 # Write request sizes (log2) system.physmem.rdQLenPdf::0 29853 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 381 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 380 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 85 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see @@ -194,11 +194,11 @@ system.physmem.wrQLenPdf::61 0 # Wh system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see system.physmem.bytesPerActivate::samples 2721 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 716.489526 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 515.486965 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 387.954881 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 364 13.38% 13.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 231 8.49% 21.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 716.466005 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 515.355667 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 387.992511 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 365 13.41% 13.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 230 8.45% 21.87% # Bytes accessed per row activation system.physmem.bytesPerActivate::256-383 123 4.52% 26.39% # Bytes accessed per row activation system.physmem.bytesPerActivate::384-511 120 4.41% 30.80% # Bytes accessed per row activation system.physmem.bytesPerActivate::512-639 92 3.38% 34.18% # Bytes accessed per row activation @@ -208,8 +208,8 @@ system.physmem.bytesPerActivate::896-1023 67 2.46% 45.61% # B system.physmem.bytesPerActivate::1024-1151 1480 54.39% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 2721 # Bytes accessed per row activation system.physmem.rdPerTurnAround::samples 9 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 3363.777778 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 10055.709980 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 3363.666667 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 10055.376646 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::0-1023 8 88.89% 88.89% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::29696-30719 1 11.11% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::total 9 # Reads before turning the bus around for writes @@ -221,11 +221,11 @@ system.physmem.wrPerTurnAround::16 1 11.11% 11.11% # Wr system.physmem.wrPerTurnAround::18 8 88.89% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::total 9 # Writes before turning the bus around for reads system.physmem.totQLat 133021500 # Total ticks spent queuing -system.physmem.totMemAccLat 701821500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 151680000 # Total ticks spent in databus transfers -system.physmem.avgQLat 4384.94 # Average queueing delay per DRAM burst +system.physmem.totMemAccLat 701802750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 151675000 # Total ticks spent in databus transfers +system.physmem.avgQLat 4385.08 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 23134.94 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 23135.08 # Average memory access latency per DRAM burst system.physmem.avgRdBW 31.52 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.17 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 31.61 # Average system read bandwidth in MiByte/s @@ -236,11 +236,11 @@ system.physmem.busUtilRead 0.25 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing system.physmem.avgWrQLen 15.67 # Average write queue length when enqueuing -system.physmem.readRowHits 27659 # Number of row buffer hits during reads +system.physmem.readRowHits 27658 # Number of row buffer hits during reads system.physmem.writeRowHits 106 # Number of row buffer hits during writes system.physmem.readRowHitRate 91.18 # Row buffer hit rate for reads system.physmem.writeRowHitRate 56.08 # Row buffer hit rate for writes -system.physmem.avgGap 2012351.25 # Average gap between requests +system.physmem.avgGap 2012416.99 # Average gap between requests system.physmem.pageHitRate 90.96 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 10924200 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 5960625 # Energy for precharge commands per rank (pJ) @@ -258,13 +258,13 @@ system.physmem_0.memoryStateTime::ACT 2211196750 # Ti system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.physmem_1.actEnergy 9608760 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 5242875 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 114207600 # Energy for read commands per rank (pJ) +system.physmem_1.readEnergy 114199800 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 51840 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 4023218160 # Energy for refresh commands per rank (pJ) system.physmem_1.actBackEnergy 3020047245 # Energy for active background per rank (pJ) system.physmem_1.preBackEnergy 34309197750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 41481574230 # Total energy per rank (pJ) -system.physmem_1.averagePower 673.432024 # Core power per rank (mW) +system.physmem_1.totalEnergy 41481566430 # Total energy per rank (pJ) +system.physmem_1.averagePower 673.431898 # Core power per rank (mW) system.physmem_1.memoryStateTime::IDLE 57061053250 # Time in different power states system.physmem_1.memoryStateTime::REF 2056860000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states @@ -350,7 +350,7 @@ system.cpu.iq.iqNonSpecInstsAdded 2340 # Nu system.cpu.iq.iqInstsIssued 306103027 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 45906 # Number of squashed instructions issued system.cpu.iq.iqSquashedInstsExamined 44111268 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 63882730 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedOperandsExamined 63882734 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 1895 # Number of squashed non-spec instructions that were removed system.cpu.iq.issued_per_cycle::samples 123139703 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::mean 2.485819 # Number of insts issued each cycle @@ -443,7 +443,7 @@ system.cpu.iq.fu_busy_cnt 3969927 # FU system.cpu.iq.fu_busy_rate 0.012969 # FU busy rate (busy events/executed inst) system.cpu.iq.int_inst_queue_reads 739361233 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 366454635 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 304282659 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_wakeup_accesses 304282658 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 357 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 618 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 133 # Number of floating instruction queue wakeup accesses @@ -483,8 +483,8 @@ system.cpu.iew.exec_refs 131430384 # nu system.cpu.iew.exec_branches 31401849 # Number of branches executed system.cpu.iew.exec_stores 33679798 # Number of stores executed system.cpu.iew.exec_rate 2.476830 # Inst execution rate -system.cpu.iew.wb_sent 304565842 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 304282792 # cumulative count of insts written-back +system.cpu.iew.wb_sent 304565843 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 304282791 # cumulative count of insts written-back system.cpu.iew.wb_producers 230213909 # num instructions producing a value system.cpu.iew.wb_consumers 333860423 # num instructions consuming a value system.cpu.iew.wb_rate 2.469736 # insts written-back per cycle @@ -573,22 +573,22 @@ system.cpu.cc_regfile_reads 107533030 # nu system.cpu.cc_regfile_writes 64416979 # number of cc regfile writes system.cpu.misc_regfile_reads 195275946 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.replacements 2072313 # number of replacements -system.cpu.dcache.tags.tagsinuse 4068.012890 # Cycle average of tags in use +system.cpu.dcache.tags.replacements 2072312 # number of replacements +system.cpu.dcache.tags.tagsinuse 4068.008256 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 68071038 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2076409 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 32.783059 # Average number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2076408 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 32.783074 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 19455459500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4068.012890 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.993167 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.993167 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 4068.008256 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.993166 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.993166 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 633 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 3336 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 127 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 143788645 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 143788645 # Number of data accesses +system.cpu.dcache.tags.tag_accesses 143788642 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 143788642 # Number of data accesses system.cpu.dcache.ReadReq_hits::cpu.data 36725212 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 36725212 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 31345825 # number of WriteReq hits @@ -597,30 +597,30 @@ system.cpu.dcache.demand_hits::cpu.data 68071037 # nu system.cpu.dcache.demand_hits::total 68071037 # number of demand (read+write) hits system.cpu.dcache.overall_hits::cpu.data 68071037 # number of overall hits system.cpu.dcache.overall_hits::total 68071037 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2691154 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2691154 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::cpu.data 2691153 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2691153 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 93927 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 93927 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2785081 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2785081 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2785081 # number of overall misses -system.cpu.dcache.overall_misses::total 2785081 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 32304267000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 32304267000 # number of ReadReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 2785080 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2785080 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2785080 # number of overall misses +system.cpu.dcache.overall_misses::total 2785080 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 32304195500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 32304195500 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 2956614994 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 2956614994 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 35260881994 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 35260881994 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 35260881994 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 35260881994 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 39416366 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 39416366 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 35260810494 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 35260810494 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 35260810494 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 35260810494 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 39416365 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 39416365 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 31439752 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 70856118 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 70856118 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 70856118 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 70856118 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 70856117 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 70856117 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 70856117 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 70856117 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.068275 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.068275 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002988 # miss rate for WriteReq accesses @@ -629,14 +629,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.039306 system.cpu.dcache.demand_miss_rate::total 0.039306 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.039306 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.039306 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12003.871573 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 12003.871573 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12003.849465 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 12003.849465 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31477.796523 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 31477.796523 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 12660.630694 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 12660.630694 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 12660.630694 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 12660.630694 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 12660.609567 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 12660.609567 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 12660.609567 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 12660.609567 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 221476 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 43220 # number of cycles access was blocked @@ -655,22 +655,22 @@ system.cpu.dcache.demand_mshr_hits::cpu.data 708671 system.cpu.dcache.demand_mshr_hits::total 708671 # number of demand (read+write) MSHR hits system.cpu.dcache.overall_mshr_hits::cpu.data 708671 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits::total 708671 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1994366 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1994366 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1994365 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1994365 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82044 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 82044 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2076410 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2076410 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2076410 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2076410 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24195993500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 24195993500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 2076409 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2076409 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2076409 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2076409 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24195923000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 24195923000 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2799396995 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 2799396995 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26995390495 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 26995390495 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26995390495 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 26995390495 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26995319995 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 26995319995 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26995319995 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 26995319995 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.050597 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.050597 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002610 # mshr miss rate for WriteReq accesses @@ -679,14 +679,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.029305 system.cpu.dcache.demand_mshr_miss_rate::total 0.029305 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.029305 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.029305 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12132.173082 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12132.173082 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12132.143815 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12132.143815 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34120.679087 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34120.679087 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13000.992335 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 13000.992335 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13000.992335 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 13000.992335 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13000.964644 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 13000.964644 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13000.964644 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 13000.964644 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 53 # number of replacements system.cpu.icache.tags.tagsinuse 825.039758 # Cycle average of tags in use @@ -783,27 +783,27 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 76349.112426 system.cpu.icache.overall_avg_mshr_miss_latency::total 76349.112426 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 493 # number of replacements -system.cpu.l2cache.tags.tagsinuse 20712.318868 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 4035103 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 30411 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 132.685640 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 20711.322176 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 4035102 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 30410 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 132.689970 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 19791.559632 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.inst 674.841856 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 245.917380 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 244.920687 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.603990 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.020595 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.007505 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.632090 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 29918 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_percent::cpu.data 0.007474 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.632059 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 29917 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 66 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::2 782 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1386 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27623 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.913025 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 33310473 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 33310473 # Number of data accesses +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27622 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.912994 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 33310456 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 33310456 # Number of data accesses system.cpu.l2cache.WritebackDirty_hits::writebacks 2066601 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 2066601 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 53 # number of WritebackClean hits @@ -826,26 +826,26 @@ system.cpu.l2cache.ReadExReq_misses::cpu.data 28998 system.cpu.l2cache.ReadExReq_misses::total 28998 # number of ReadExReq misses system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 998 # number of ReadCleanReq misses system.cpu.l2cache.ReadCleanReq_misses::total 998 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 426 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 426 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 425 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 425 # number of ReadSharedReq misses system.cpu.l2cache.demand_misses::cpu.inst 998 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 29424 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 30422 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 29423 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 30421 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 998 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 29424 # number of overall misses -system.cpu.l2cache.overall_misses::total 30422 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 29423 # number of overall misses +system.cpu.l2cache.overall_misses::total 30421 # number of overall misses system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2118138000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 2118138000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 75717000 # number of ReadCleanReq miss cycles system.cpu.l2cache.ReadCleanReq_miss_latency::total 75717000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 32704000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 32704000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 32635000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 32635000 # number of ReadSharedReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 75717000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 2150842000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 2226559000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 2150773000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 2226490000 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 75717000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 2150842000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 2226559000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 2150773000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 2226490000 # number of overall miss cycles system.cpu.l2cache.WritebackDirty_accesses::writebacks 2066601 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackDirty_accesses::total 2066601 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::writebacks 53 # number of WritebackClean accesses(hits+misses) @@ -856,38 +856,38 @@ system.cpu.l2cache.ReadExReq_accesses::cpu.data 82069 system.cpu.l2cache.ReadExReq_accesses::total 82069 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1014 # number of ReadCleanReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::total 1014 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1994340 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 1994340 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1994339 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 1994339 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 1014 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 2076409 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2077423 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 2076408 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2077422 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 1014 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 2076409 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2077423 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 2076408 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2077422 # number of overall (read+write) accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.353337 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.353337 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.984221 # miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.984221 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.000214 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.000214 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.000213 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.000213 # miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.984221 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.014171 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.014170 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.014644 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.984221 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.014171 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.014170 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.014644 # miss rate for overall accesses system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73044.278916 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73044.278916 # average ReadExReq miss latency system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75868.737475 # average ReadCleanReq miss latency system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75868.737475 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 76769.953052 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 76769.953052 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 76788.235294 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 76788.235294 # average ReadSharedReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75868.737475 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73098.219141 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 73189.106568 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73098.358427 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 73189.244272 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75868.737475 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73098.219141 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 73189.106568 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73098.358427 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 73189.244272 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -902,117 +902,117 @@ system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 28998 system.cpu.l2cache.ReadExReq_mshr_misses::total 28998 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 998 # number of ReadCleanReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::total 998 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 426 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 426 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 425 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 425 # number of ReadSharedReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 998 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 29424 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 30422 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 29423 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 30421 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 998 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 29424 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 30422 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 29423 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 30421 # number of overall MSHR misses system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1828158000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1828158000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 65737000 # number of ReadCleanReq MSHR miss cycles system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 65737000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 28444000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 28444000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 28385000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 28385000 # number of ReadSharedReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 65737000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1856602000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 1922339000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1856543000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 1922280000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 65737000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1856602000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 1922339000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1856543000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1922280000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.353337 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.353337 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.984221 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.984221 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000214 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000214 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000213 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000213 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.984221 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014171 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014170 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.014644 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.984221 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014171 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014170 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.014644 # mshr miss rate for overall accesses system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63044.278916 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63044.278916 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65868.737475 # average ReadCleanReq mshr miss latency system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65868.737475 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 66769.953052 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 66769.953052 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 66788.235294 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 66788.235294 # average ReadSharedReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65868.737475 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63098.219141 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63189.106568 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63098.358427 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63189.244272 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65868.737475 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63098.219141 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63189.106568 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63098.358427 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63189.244272 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 4149790 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2072370 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 4149788 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2072369 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 42 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 279 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 279 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadResp 1995354 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 1995353 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 2066791 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 53 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 6015 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 6014 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 1 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 1 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 82069 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 82069 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 1014 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1994340 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1994339 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2081 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6225133 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 6227214 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6225130 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 6227211 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 68288 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 265152640 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 265220928 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 265152576 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 265220864 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 493 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 2077917 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 2077916 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 0.000156 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0.012505 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 2077592 99.98% 99.98% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 2077591 99.98% 99.98% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 325 0.02% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 2077917 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4141549000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 2077916 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4141548000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 6.7 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 1521000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3114614000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3114612500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 5.1 # Layer utilization (%) -system.membus.trans_dist::ReadResp 1424 # Transaction distribution +system.membus.trans_dist::ReadResp 1423 # Transaction distribution system.membus.trans_dist::WritebackDirty 190 # Transaction distribution system.membus.trans_dist::CleanEvict 24 # Transaction distribution system.membus.trans_dist::ReadExReq 28998 # Transaction distribution system.membus.trans_dist::ReadExResp 28998 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 1424 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 61058 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 61058 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 61058 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1959168 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 1959168 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 1959168 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 1423 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 61056 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 61056 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 61056 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1959104 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 1959104 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 1959104 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 30636 # Request fanout histogram +system.membus.snoop_fanout::samples 30635 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 30636 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 30635 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 30636 # Request fanout histogram -system.membus.reqLayer0.occupancy 42770500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 30635 # Request fanout histogram +system.membus.reqLayer0.occupancy 42769000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 160321750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 160316500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.3 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/arm/linux/minor-timing/config.ini b/tests/long/se/20.parser/ref/arm/linux/minor-timing/config.ini index a401ada34..e8f37d0a8 100644 --- a/tests/long/se/20.parser/ref/arm/linux/minor-timing/config.ini +++ b/tests/long/se/20.parser/ref/arm/linux/minor-timing/config.ini @@ -15,6 +15,7 @@ boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain eventq_index=0 +exit_on_work_items=false init_param=0 kernel= kernel_addr_check=true @@ -24,6 +25,7 @@ mem_mode=timing mem_ranges= memories=system.physmem mmap_using_noreserve=false +multi_thread=false num_work_ids=16 readfile= symbolfile= @@ -132,9 +134,9 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +clusivity=mostly_incl demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=2 is_read_only=false max_miss_count=0 @@ -148,6 +150,7 @@ system=system tags=system.cpu.dcache.tags tgts_per_mshr=20 write_buffers=8 +writeback_clean=false cpu_side=system.cpu.dcache_port mem_side=system.cpu.toL2Bus.slave[1] @@ -591,9 +594,9 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +clusivity=mostly_incl demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=2 is_read_only=true max_miss_count=0 @@ -607,6 +610,7 @@ system=system tags=system.cpu.icache.tags tgts_per_mshr=20 write_buffers=8 +writeback_clean=true cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.slave[0] @@ -626,6 +630,7 @@ eventq_index=0 [system.cpu.isa] type=ArmISA +decoderFlavour=Generic eventq_index=0 fpsid=1090793632 id_aa64afr0_el1=0 @@ -701,9 +706,9 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +clusivity=mostly_incl demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=20 is_read_only=false max_miss_count=0 @@ -717,6 +722,7 @@ system=system tags=system.cpu.l2cache.tags tgts_per_mshr=12 write_buffers=8 +writeback_clean=false cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] @@ -732,12 +738,14 @@ size=2097152 [system.cpu.toL2Bus] type=CoherentXBar +children=snoop_filter clk_domain=system.cpu_clk_domain eventq_index=0 forward_latency=0 frontend_latency=1 +point_of_coherency=false response_latency=1 -snoop_filter=Null +snoop_filter=system.cpu.toL2Bus.snoop_filter snoop_response_latency=1 system=system use_default_range=false @@ -745,6 +753,13 @@ width=32 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port +[system.cpu.toL2Bus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=0 +max_capacity=8388608 +system=system + [system.cpu.tracer] type=ExeTracer eventq_index=0 @@ -759,9 +774,9 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/parser +executable=/dist/m5/cpu2000/binaries/arm/linux/parser gid=100 -input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in +input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in kvmInSE=false max_stack_size=67108864 output=cout @@ -794,6 +809,7 @@ clk_domain=system.clk_domain eventq_index=0 forward_latency=4 frontend_latency=3 +point_of_coherency=true response_latency=2 snoop_filter=Null snoop_response_latency=4 diff --git a/tests/long/se/20.parser/ref/arm/linux/minor-timing/simerr b/tests/long/se/20.parser/ref/arm/linux/minor-timing/simerr index be90b0340..eeb19437b 100755 --- a/tests/long/se/20.parser/ref/arm/linux/minor-timing/simerr +++ b/tests/long/se/20.parser/ref/arm/linux/minor-timing/simerr @@ -1,3 +1,2 @@ warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) -warn: Sockets disabled, not accepting gdb connections warn: CP14 unimplemented crn[8], opc1[2], crm[9], opc2[4] diff --git a/tests/long/se/20.parser/ref/arm/linux/minor-timing/simout b/tests/long/se/20.parser/ref/arm/linux/minor-timing/simout index 984c172ad..73f574cb5 100755 --- a/tests/long/se/20.parser/ref/arm/linux/minor-timing/simout +++ b/tests/long/se/20.parser/ref/arm/linux/minor-timing/simout @@ -3,10 +3,10 @@ Redirecting stderr to build/ARM/tests/opt/long/se/20.parser/arm/linux/minor-timi gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 14 2015 23:29:19 -gem5 started Sep 15 2015 03:04:52 -gem5 executing on ribera.cs.wisc.edu -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/minor-timing -re /scratch/nilay/GEM5/gem5/tests/run.py build/ARM/tests/opt/long/se/20.parser/arm/linux/minor-timing +gem5 compiled Mar 16 2016 15:51:04 +gem5 started Mar 16 2016 15:55:43 +gem5 executing on dinar2c11, pid 15340 +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/minor-timing -re /home/stever/gem5-public/tests/run.py build/ARM/tests/opt/long/se/20.parser/arm/linux/minor-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -70,4 +70,4 @@ info: Increasing stack size by one page. about 2 million people attended the five best costumes got prizes No errors! -Exiting @ tick 363605295500 because target called exit() +Exiting @ tick 363608804500 because target called exit() diff --git a/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt index 2d282091b..415eb183d 100644 --- a/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt @@ -1,104 +1,104 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.363578 # Number of seconds simulated -sim_ticks 363578056500 # Number of ticks simulated -final_tick 363578056500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.363609 # Number of seconds simulated +sim_ticks 363608804500 # Number of ticks simulated +final_tick 363608804500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 233007 # Simulator instruction rate (inst/s) -host_op_rate 252377 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 167231069 # Simulator tick rate (ticks/s) -host_mem_usage 322224 # Number of bytes of host memory used -host_seconds 2174.11 # Real time elapsed on the host -sim_insts 506582156 # Number of instructions simulated -sim_ops 548695379 # Number of ops (including micro ops) simulated +host_inst_rate 100066 # Simulator instruction rate (inst/s) +host_op_rate 108385 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 71824585 # Simulator tick rate (ticks/s) +host_mem_usage 304984 # Number of bytes of host memory used +host_seconds 5062.46 # Real time elapsed on the host +sim_insts 506579366 # Number of instructions simulated +sim_ops 548692589 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 179648 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9032384 # Number of bytes read from this memory -system.physmem.bytes_read::total 9212032 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 179648 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 179648 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6219008 # Number of bytes written to this memory -system.physmem.bytes_written::total 6219008 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2807 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 141131 # Number of read requests responded to by this memory -system.physmem.num_reads::total 143938 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 97172 # Number of write requests responded to by this memory -system.physmem.num_writes::total 97172 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 494111 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 24843039 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 25337151 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 494111 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 494111 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 17105015 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 17105015 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 17105015 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 494111 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 24843039 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 42442165 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 143938 # Number of read requests accepted -system.physmem.writeReqs 97172 # Number of write requests accepted -system.physmem.readBursts 143938 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 97172 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 9204928 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 7104 # Total number of bytes read from write queue -system.physmem.bytesWritten 6217152 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 9212032 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6219008 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 111 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 179584 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9028480 # Number of bytes read from this memory +system.physmem.bytes_read::total 9208064 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 179584 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 179584 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6218624 # Number of bytes written to this memory +system.physmem.bytes_written::total 6218624 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 2806 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 141070 # Number of read requests responded to by this memory +system.physmem.num_reads::total 143876 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 97166 # Number of write requests responded to by this memory +system.physmem.num_writes::total 97166 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 493893 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 24830202 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 25324095 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 493893 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 493893 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 17102512 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 17102512 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 17102512 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 493893 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 24830202 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 42426607 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 143876 # Number of read requests accepted +system.physmem.writeReqs 97166 # Number of write requests accepted +system.physmem.readBursts 143876 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 97166 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 9201472 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 6592 # Total number of bytes read from write queue +system.physmem.bytesWritten 6217344 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 9208064 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6218624 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 103 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 9337 # Per bank write bursts -system.physmem.perBankRdBursts::1 8920 # Per bank write bursts -system.physmem.perBankRdBursts::2 8993 # Per bank write bursts -system.physmem.perBankRdBursts::3 8670 # Per bank write bursts -system.physmem.perBankRdBursts::4 9385 # Per bank write bursts +system.physmem.perBankRdBursts::0 9345 # Per bank write bursts +system.physmem.perBankRdBursts::1 8917 # Per bank write bursts +system.physmem.perBankRdBursts::2 8955 # Per bank write bursts +system.physmem.perBankRdBursts::3 8654 # Per bank write bursts +system.physmem.perBankRdBursts::4 9386 # Per bank write bursts system.physmem.perBankRdBursts::5 9354 # Per bank write bursts -system.physmem.perBankRdBursts::6 8954 # Per bank write bursts +system.physmem.perBankRdBursts::6 8955 # Per bank write bursts system.physmem.perBankRdBursts::7 8104 # Per bank write bursts -system.physmem.perBankRdBursts::8 8602 # Per bank write bursts +system.physmem.perBankRdBursts::8 8603 # Per bank write bursts system.physmem.perBankRdBursts::9 8629 # Per bank write bursts -system.physmem.perBankRdBursts::10 8738 # Per bank write bursts -system.physmem.perBankRdBursts::11 9458 # Per bank write bursts -system.physmem.perBankRdBursts::12 9338 # Per bank write bursts -system.physmem.perBankRdBursts::13 9514 # Per bank write bursts -system.physmem.perBankRdBursts::14 8722 # Per bank write bursts -system.physmem.perBankRdBursts::15 9109 # Per bank write bursts -system.physmem.perBankWrBursts::0 6210 # Per bank write bursts -system.physmem.perBankWrBursts::1 6096 # Per bank write bursts +system.physmem.perBankRdBursts::10 8742 # Per bank write bursts +system.physmem.perBankRdBursts::11 9454 # Per bank write bursts +system.physmem.perBankRdBursts::12 9335 # Per bank write bursts +system.physmem.perBankRdBursts::13 9509 # Per bank write bursts +system.physmem.perBankRdBursts::14 8712 # Per bank write bursts +system.physmem.perBankRdBursts::15 9119 # Per bank write bursts +system.physmem.perBankWrBursts::0 6212 # Per bank write bursts +system.physmem.perBankWrBursts::1 6095 # Per bank write bursts system.physmem.perBankWrBursts::2 6031 # Per bank write bursts -system.physmem.perBankWrBursts::3 5885 # Per bank write bursts -system.physmem.perBankWrBursts::4 6239 # Per bank write bursts -system.physmem.perBankWrBursts::5 6240 # Per bank write bursts -system.physmem.perBankWrBursts::6 6045 # Per bank write bursts -system.physmem.perBankWrBursts::7 5507 # Per bank write bursts -system.physmem.perBankWrBursts::8 5786 # Per bank write bursts -system.physmem.perBankWrBursts::9 5860 # Per bank write bursts -system.physmem.perBankWrBursts::10 5977 # Per bank write bursts -system.physmem.perBankWrBursts::11 6497 # Per bank write bursts -system.physmem.perBankWrBursts::12 6353 # Per bank write bursts -system.physmem.perBankWrBursts::13 6323 # Per bank write bursts -system.physmem.perBankWrBursts::14 6005 # Per bank write bursts -system.physmem.perBankWrBursts::15 6089 # Per bank write bursts +system.physmem.perBankWrBursts::3 5882 # Per bank write bursts +system.physmem.perBankWrBursts::4 6240 # Per bank write bursts +system.physmem.perBankWrBursts::5 6242 # Per bank write bursts +system.physmem.perBankWrBursts::6 6046 # Per bank write bursts +system.physmem.perBankWrBursts::7 5509 # Per bank write bursts +system.physmem.perBankWrBursts::8 5790 # Per bank write bursts +system.physmem.perBankWrBursts::9 5862 # Per bank write bursts +system.physmem.perBankWrBursts::10 5980 # Per bank write bursts +system.physmem.perBankWrBursts::11 6494 # Per bank write bursts +system.physmem.perBankWrBursts::12 6352 # Per bank write bursts +system.physmem.perBankWrBursts::13 6321 # Per bank write bursts +system.physmem.perBankWrBursts::14 5998 # Per bank write bursts +system.physmem.perBankWrBursts::15 6092 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 363578030500 # Total gap between requests +system.physmem.totGap 363608778500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 143938 # Read request sizes (log2) +system.physmem.readPktSize::6 143876 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 97172 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 143477 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 330 # What read queue length does an incoming req see +system.physmem.writePktSize::6 97166 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 143433 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 320 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 20 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -144,37 +144,37 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2944 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3098 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5566 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5669 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5692 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5696 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5718 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5717 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5719 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 5721 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5717 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5713 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5741 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 5750 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 5692 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5700 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5635 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2923 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5563 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5694 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5686 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5706 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5721 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5699 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5724 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 5731 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5734 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5734 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5738 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 5711 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 5678 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5681 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5643 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 5621 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 7 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::41 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see @@ -193,112 +193,109 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 65452 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 235.611563 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 156.275569 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 241.348204 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 24841 37.95% 37.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 18422 28.15% 66.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6870 10.50% 76.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 7970 12.18% 88.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2117 3.23% 92.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1100 1.68% 93.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 791 1.21% 94.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 584 0.89% 95.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 2757 4.21% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 65452 # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 65427 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 235.654638 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 156.256012 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 241.782834 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 24843 37.97% 37.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 18425 28.16% 66.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6952 10.63% 76.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 7899 12.07% 88.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2020 3.09% 91.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1104 1.69% 93.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 778 1.19% 94.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 662 1.01% 95.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 2744 4.19% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 65427 # Bytes accessed per row activation system.physmem.rdPerTurnAround::samples 5612 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 25.626515 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 380.491009 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 25.618496 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 380.574654 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::0-1023 5610 99.96% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::27648-28671 1 0.02% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::total 5612 # Reads before turning the bus around for writes system.physmem.wrPerTurnAround::samples 5612 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.309872 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.213078 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 2.394006 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-17 2658 47.36% 47.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18-19 2810 50.07% 97.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-21 50 0.89% 98.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22-23 29 0.52% 98.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-25 20 0.36% 99.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26-27 11 0.20% 99.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-29 6 0.11% 99.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30-31 6 0.11% 99.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-33 3 0.05% 99.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::34-35 7 0.12% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-37 1 0.02% 99.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::38-39 1 0.02% 99.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-41 1 0.02% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-45 1 0.02% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::46-47 1 0.02% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-49 1 0.02% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::50-51 1 0.02% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-53 2 0.04% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-57 1 0.02% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.310406 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.214262 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 2.369355 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-17 2682 47.79% 47.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18-19 2777 49.48% 97.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-21 56 1.00% 98.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22-23 33 0.59% 98.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-25 17 0.30% 99.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26-27 10 0.18% 99.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-29 7 0.12% 99.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30-31 5 0.09% 99.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-33 7 0.12% 99.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::34-35 4 0.07% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-37 3 0.05% 99.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-41 2 0.04% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::42-43 4 0.07% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-49 1 0.02% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::50-51 1 0.02% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-53 1 0.02% 99.96% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::72-73 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-97 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::98-99 1 0.02% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::total 5612 # Writes before turning the bus around for reads -system.physmem.totQLat 1537591000 # Total ticks spent queuing -system.physmem.totMemAccLat 4234347250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 719135000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10690.56 # Average queueing delay per DRAM burst +system.physmem.totQLat 1539890250 # Total ticks spent queuing +system.physmem.totMemAccLat 4235634000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 718865000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10710.57 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29440.56 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 25.32 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 29460.57 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 25.31 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 17.10 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 25.34 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 17.11 # Average system write bandwidth in MiByte/s +system.physmem.avgRdBWSys 25.32 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 17.10 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.33 # Data bus utilization in percentage system.physmem.busUtilRead 0.20 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.13 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing -system.physmem.avgWrQLen 19.82 # Average write queue length when enqueuing -system.physmem.readRowHits 110822 # Number of row buffer hits during reads -system.physmem.writeRowHits 64690 # Number of row buffer hits during writes +system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing +system.physmem.avgWrQLen 19.45 # Average write queue length when enqueuing +system.physmem.readRowHits 110770 # Number of row buffer hits during reads +system.physmem.writeRowHits 64716 # Number of row buffer hits during writes system.physmem.readRowHitRate 77.05 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 66.57 # Row buffer hit rate for writes -system.physmem.avgGap 1507934.26 # Average gap between requests +system.physmem.writeRowHitRate 66.60 # Row buffer hit rate for writes +system.physmem.avgGap 1508487.23 # Average gap between requests system.physmem.pageHitRate 72.83 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 249245640 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 135997125 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 559174200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 312459120 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 23746700640 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 47224643355 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 176717716500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 248945936580 # Total energy per rank (pJ) -system.physmem_0.averagePower 684.723644 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 293681207750 # Time in different power states -system.physmem_0.memoryStateTime::REF 12140440000 # Time in different power states +system.physmem_0.actEnergy 249041520 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 135885750 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 558807600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 312407280 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 23748734880 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 47272879035 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 176694091500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 248971847565 # Total energy per rank (pJ) +system.physmem_0.averagePower 684.736255 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 293641319750 # Time in different power states +system.physmem_0.memoryStateTime::REF 12141480000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 57750923750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 57820495250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 245314440 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 133852125 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 562247400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 316716480 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 23746700640 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 46957257495 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 176952265500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 248914354080 # Total energy per rank (pJ) -system.physmem_1.averagePower 684.636777 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 294072895750 # Time in different power states -system.physmem_1.memoryStateTime::REF 12140440000 # Time in different power states +system.physmem_1.actEnergy 245269080 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 133827375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 562192800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 316684080 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 23748734880 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 46853247600 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 177062189250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 248922145065 # Total energy per rank (pJ) +system.physmem_1.averagePower 684.599560 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 294255473500 # Time in different power states +system.physmem_1.memoryStateTime::REF 12141480000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 57359475250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 57206580500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 131892190 # Number of BP lookups -system.cpu.branchPred.condPredicted 98029664 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 6137262 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 68271020 # Number of BTB lookups -system.cpu.branchPred.BTBHits 64393265 # Number of BTB hits +system.cpu.branchPred.lookups 131890227 # Number of BP lookups +system.cpu.branchPred.condPredicted 98029520 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 6134595 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 68518889 # Number of BTB lookups +system.cpu.branchPred.BTBHits 64416393 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 94.320057 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 9980136 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 17826 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 94.012606 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 9980436 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 18277 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -417,24 +414,24 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu.numCycles 727156113 # number of cpu cycles simulated +system.cpu.numCycles 727217609 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 506582156 # Number of instructions committed -system.cpu.committedOps 548695379 # Number of ops (including micro ops) committed -system.cpu.discardedOps 13195789 # Number of ops (including micro ops) which were discarded before commit +system.cpu.committedInsts 506579366 # Number of instructions committed +system.cpu.committedOps 548692589 # Number of ops (including micro ops) committed +system.cpu.discardedOps 13188504 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.435416 # CPI: cycles per instruction -system.cpu.ipc 0.696662 # IPC: instructions per cycle -system.cpu.tickCycles 690690437 # Number of cycles that the object actually ticked -system.cpu.idleCycles 36465676 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 1139983 # number of replacements -system.cpu.dcache.tags.tagsinuse 4070.787946 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 171168228 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1144079 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 149.612245 # Average number of references to valid blocks. +system.cpu.cpi 1.435545 # CPI: cycles per instruction +system.cpu.ipc 0.696599 # IPC: instructions per cycle +system.cpu.tickCycles 690736700 # Number of cycles that the object actually ticked +system.cpu.idleCycles 36480909 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 1141376 # number of replacements +system.cpu.dcache.tags.tagsinuse 4070.790078 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 171162589 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1145472 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 149.425380 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 4896334500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4070.787946 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 4070.790078 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.993845 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.993845 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id @@ -443,72 +440,72 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::1 18 system.cpu.dcache.tags.age_task_id_blocks_1024::2 551 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 3500 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 346591347 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 346591347 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 114649758 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 114649758 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 53538635 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 53538635 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 2753 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 2753 # number of SoftPFReq hits +system.cpu.dcache.tags.tag_accesses 346584178 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 346584178 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 114644865 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 114644865 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 53537898 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 53537898 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 2744 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 2744 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488541 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 1488541 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 168188393 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 168188393 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 168191146 # number of overall hits -system.cpu.dcache.overall_hits::total 168191146 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 854719 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 854719 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 700671 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 700671 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 16 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 16 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 1555390 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1555390 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1555406 # number of overall misses -system.cpu.dcache.overall_misses::total 1555406 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 14046321000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 14046321000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 21904504500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 21904504500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 35950825500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 35950825500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 35950825500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 35950825500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 115504477 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 115504477 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 2769 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 2769 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 168182763 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 168182763 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 168185507 # number of overall hits +system.cpu.dcache.overall_hits::total 168185507 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 855598 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 855598 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 701151 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 701151 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 15 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 15 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 1556749 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1556749 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1556764 # number of overall misses +system.cpu.dcache.overall_misses::total 1556764 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 14056066500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 14056066500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 21917357000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 21917357000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 35973423500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 35973423500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 35973423500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 35973423500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 115500463 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 115500463 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 54239049 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 54239049 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 2759 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 2759 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488541 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 1488541 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 169743783 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 169743783 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 169746552 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 169746552 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.007400 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.007400 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.012918 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.012918 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.005778 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.005778 # miss rate for SoftPFReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.009163 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.009163 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.009163 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.009163 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16433.846679 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 16433.846679 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31262.182251 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 31262.182251 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 23113.704923 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 23113.704923 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 23113.467159 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 23113.467159 # average overall miss latency +system.cpu.dcache.demand_accesses::cpu.data 169739512 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 169739512 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 169742271 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 169742271 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.007408 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.007408 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.012927 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.012927 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.005437 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.005437 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.009171 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.009171 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.009171 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.009171 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16428.353619 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 16428.353619 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31259.111090 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 31259.111090 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 23108.043429 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 23108.043429 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 23107.820774 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 23107.820774 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -517,111 +514,111 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1068257 # number of writebacks -system.cpu.dcache.writebacks::total 1068257 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 66817 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 66817 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 344507 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 344507 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 411324 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 411324 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 411324 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 411324 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 787902 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 787902 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 356164 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 356164 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 13 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 13 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1144066 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1144066 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1144079 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1144079 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12362476000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 12362476000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11126251500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 11126251500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1030500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1030500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23488727500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 23488727500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23489758000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 23489758000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006821 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006821 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006567 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006567 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.004695 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.004695 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006740 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.006740 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006740 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.006740 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15690.372661 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15690.372661 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31239.124392 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31239.124392 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 79269.230769 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 79269.230769 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20530.919982 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20530.919982 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20531.587417 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20531.587417 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 1069283 # number of writebacks +system.cpu.dcache.writebacks::total 1069283 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 66543 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 66543 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 344746 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 344746 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 411289 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 411289 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 411289 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 411289 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 789055 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 789055 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 356405 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 356405 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 12 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 12 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1145460 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1145460 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1145472 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1145472 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12372636000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 12372636000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11132196500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 11132196500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 944000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 944000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23504832500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 23504832500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23505776500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 23505776500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006832 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006832 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006571 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006571 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.004349 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.004349 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006748 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.006748 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006748 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.006748 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15680.321397 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15680.321397 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31234.681051 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31234.681051 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 78666.666667 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 78666.666667 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20519.994151 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20519.994151 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20520.603297 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20520.603297 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 17711 # number of replacements -system.cpu.icache.tags.tagsinuse 1188.286888 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 199302654 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 19583 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 10177.330031 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 17687 # number of replacements +system.cpu.icache.tags.tagsinuse 1188.299437 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 199347924 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 19559 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 10192.132727 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1188.286888 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.580218 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.580218 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1188.299437 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.580224 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.580224 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1872 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 62 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 57 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 309 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1403 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 63 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 59 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 305 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1404 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.914062 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 398664057 # Number of tag accesses -system.cpu.icache.tags.data_accesses 398664057 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 199302654 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 199302654 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 199302654 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 199302654 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 199302654 # number of overall hits -system.cpu.icache.overall_hits::total 199302654 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 19583 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 19583 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 19583 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 19583 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 19583 # number of overall misses -system.cpu.icache.overall_misses::total 19583 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 449788500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 449788500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 449788500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 449788500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 449788500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 449788500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 199322237 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 199322237 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 199322237 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 199322237 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 199322237 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 199322237 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 398754525 # Number of tag accesses +system.cpu.icache.tags.data_accesses 398754525 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 199347924 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 199347924 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 199347924 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 199347924 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 199347924 # number of overall hits +system.cpu.icache.overall_hits::total 199347924 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 19559 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 19559 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 19559 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 19559 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 19559 # number of overall misses +system.cpu.icache.overall_misses::total 19559 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 449446000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 449446000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 449446000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 449446000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 449446000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 449446000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 199367483 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 199367483 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 199367483 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 199367483 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 199367483 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 199367483 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000098 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000098 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000098 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000098 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000098 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000098 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22968.314354 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 22968.314354 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 22968.314354 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 22968.314354 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 22968.314354 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 22968.314354 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22978.986656 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 22978.986656 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 22978.986656 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 22978.986656 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 22978.986656 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 22978.986656 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -630,134 +627,134 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks::writebacks 17711 # number of writebacks -system.cpu.icache.writebacks::total 17711 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 19583 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 19583 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 19583 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 19583 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 19583 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 19583 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 430205500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 430205500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 430205500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 430205500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 430205500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 430205500 # number of overall MSHR miss cycles +system.cpu.icache.writebacks::writebacks 17687 # number of writebacks +system.cpu.icache.writebacks::total 17687 # number of writebacks +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 19559 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 19559 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 19559 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 19559 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 19559 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 19559 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 429887000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 429887000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 429887000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 429887000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 429887000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 429887000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000098 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000098 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000098 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000098 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000098 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000098 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21968.314354 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21968.314354 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21968.314354 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 21968.314354 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21968.314354 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 21968.314354 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21978.986656 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21978.986656 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21978.986656 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 21978.986656 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21978.986656 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 21978.986656 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 112366 # number of replacements -system.cpu.l2cache.tags.tagsinuse 27636.027175 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1768435 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 143575 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 12.317151 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 163253484000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 23509.918170 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 308.069777 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 3818.039228 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.717466 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.009402 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.116517 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.843385 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 31209 # Occupied blocks per task id +system.cpu.l2cache.tags.replacements 112304 # number of replacements +system.cpu.l2cache.tags.tagsinuse 27637.803257 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1771245 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 143514 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 12.341967 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 163256914000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 23514.215736 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 307.353699 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 3816.233823 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.717597 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.009380 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.116462 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.843439 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 31210 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::2 321 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4938 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 25851 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.952423 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 19031534 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 19031534 # Number of data accesses -system.cpu.l2cache.WritebackDirty_hits::writebacks 1068257 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 1068257 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 17475 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 17475 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 255492 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 255492 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 16775 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 16775 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 747442 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 747442 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 16775 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1002934 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1019709 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 16775 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1002934 # number of overall hits -system.cpu.l2cache.overall_hits::total 1019709 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 100923 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 100923 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2808 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 2808 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 40222 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 40222 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 2808 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 141145 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 143953 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 2808 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 141145 # number of overall misses -system.cpu.l2cache.overall_misses::total 143953 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7911788000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 7911788000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 224015500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 224015500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 3310285500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 3310285500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 224015500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 11222073500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 11446089000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 224015500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 11222073500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 11446089000 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 1068257 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 1068257 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 17475 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 17475 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 356415 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 356415 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 19583 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 19583 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 787664 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 787664 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 19583 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1144079 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 1163662 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 19583 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1144079 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 1163662 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.283161 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.283161 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.143390 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.143390 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.051065 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.051065 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.143390 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.123370 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.123707 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.143390 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.123370 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.123707 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78394.300605 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78394.300605 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 79777.599715 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 79777.599715 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 82300.370444 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 82300.370444 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79777.599715 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79507.410819 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 79512.681222 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79777.599715 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79507.410819 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 79512.681222 # average overall miss latency +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4944 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 25846 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.952454 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 19053033 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 19053033 # Number of data accesses +system.cpu.l2cache.WritebackDirty_hits::writebacks 1069283 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 1069283 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 17449 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 17449 # number of WritebackClean hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 255738 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 255738 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 16752 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 16752 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 748650 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 748650 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 16752 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 1004388 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1021140 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 16752 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 1004388 # number of overall hits +system.cpu.l2cache.overall_hits::total 1021140 # number of overall hits +system.cpu.l2cache.ReadExReq_misses::cpu.data 100917 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 100917 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2807 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 2807 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 40167 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 40167 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 2807 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 141084 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 143891 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 2807 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 141084 # number of overall misses +system.cpu.l2cache.overall_misses::total 143891 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7914773500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 7914773500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 223970500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 223970500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 3305851000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 3305851000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 223970500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 11220624500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 11444595000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 223970500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 11220624500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 11444595000 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 1069283 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 1069283 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 17449 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 17449 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 356655 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 356655 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 19559 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 19559 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 788817 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 788817 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 19559 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1145472 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 1165031 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 19559 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1145472 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 1165031 # number of overall (read+write) accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.282954 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.282954 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.143514 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.143514 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.050921 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.050921 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.143514 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.123167 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.123508 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.143514 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.123167 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.123508 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78428.545240 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78428.545240 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 79789.989312 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 79789.989312 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 82302.661389 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 82302.661389 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79789.989312 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79531.516685 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 79536.558923 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79789.989312 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79531.516685 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 79536.558923 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -766,8 +763,8 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 97172 # number of writebacks -system.cpu.l2cache.writebacks::total 97172 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 97166 # number of writebacks +system.cpu.l2cache.writebacks::total 97166 # number of writebacks system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 14 # number of ReadSharedReq MSHR hits @@ -778,117 +775,117 @@ system.cpu.l2cache.demand_mshr_hits::total 15 # system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 14 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 15 # number of overall MSHR hits -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 100923 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 100923 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2807 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2807 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 40208 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 40208 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 2807 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 141131 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 143938 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 2807 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 141131 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 143938 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6902558000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6902558000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 195877500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 195877500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2907247000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2907247000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 195877500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9809805000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 10005682500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 195877500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9809805000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 10005682500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.283161 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.283161 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.143339 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.143339 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.051047 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.051047 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.143339 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.123358 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.123694 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.143339 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.123358 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.123694 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68394.300605 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68394.300605 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69781.795511 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69781.795511 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72305.188022 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72305.188022 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69781.795511 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69508.506281 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69513.835818 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69781.795511 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69508.506281 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69513.835818 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 100917 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 100917 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2806 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2806 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 40153 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 40153 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2806 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 141070 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 143876 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2806 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 141070 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 143876 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6905603500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6905603500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 195670500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 195670500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2903188500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2903188500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 195670500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9808792000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 10004462500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 195670500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9808792000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 10004462500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.282954 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.282954 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.143463 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.143463 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.050903 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.050903 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.143463 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.123154 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.123495 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.143463 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.123154 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.123495 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68428.545240 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68428.545240 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69732.893799 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69732.893799 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72303.152940 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72303.152940 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69732.893799 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69531.381584 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69535.311657 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69732.893799 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69531.381584 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69535.311657 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 2321356 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 1157764 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 4913 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 2623 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2620 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 2324094 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 1159133 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 4986 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 2609 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2606 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 3 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadResp 807247 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 1165429 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 17711 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 86920 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 356415 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 356415 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 19583 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 787664 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 56877 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3428141 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 3485018 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2386816 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141589504 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 143976320 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 112366 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 1276028 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.005963 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.077021 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadResp 808376 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 1166449 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 17687 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 87231 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 356655 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 356655 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 19559 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 788817 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 56805 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3432320 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 3489125 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2383744 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141744320 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 144128064 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 112304 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 1277335 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.006003 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.077277 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 1268422 99.40% 99.40% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 7603 0.60% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 1269670 99.40% 99.40% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 7662 0.60% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 3 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 1276028 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 2246646000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 1277335 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 2249017000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 29392963 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 29357961 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1716126983 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1718215984 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) -system.membus.trans_dist::ReadResp 43015 # Transaction distribution -system.membus.trans_dist::WritebackDirty 97172 # Transaction distribution -system.membus.trans_dist::CleanEvict 12571 # Transaction distribution -system.membus.trans_dist::ReadExReq 100923 # Transaction distribution -system.membus.trans_dist::ReadExResp 100923 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 43015 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 397619 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 397619 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15431040 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 15431040 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadResp 42959 # Transaction distribution +system.membus.trans_dist::WritebackDirty 97166 # Transaction distribution +system.membus.trans_dist::CleanEvict 12529 # Transaction distribution +system.membus.trans_dist::ReadExReq 100917 # Transaction distribution +system.membus.trans_dist::ReadExResp 100917 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 42959 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 397447 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 397447 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15426688 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 15426688 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 253681 # Request fanout histogram +system.membus.snoop_fanout::samples 253571 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 253681 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 253571 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 253681 # Request fanout histogram -system.membus.reqLayer0.occupancy 685231500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 253571 # Request fanout histogram +system.membus.reqLayer0.occupancy 685058500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 764006500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 763682500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/config.ini index 8010a167e..7cd34eb9f 100644 --- a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/config.ini @@ -15,6 +15,7 @@ boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain eventq_index=0 +exit_on_work_items=false init_param=0 kernel= kernel_addr_check=true @@ -24,6 +25,7 @@ mem_mode=atomic mem_ranges= memories=system.physmem mmap_using_noreserve=false +multi_thread=false num_work_ids=16 readfile= symbolfile= @@ -130,6 +132,7 @@ eventq_index=0 [system.cpu.isa] type=ArmISA +decoderFlavour=Generic eventq_index=0 fpsid=1090793632 id_aa64afr0_el1=0 @@ -213,9 +216,9 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/parser +executable=/dist/m5/cpu2000/binaries/arm/linux/parser gid=100 -input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in +input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in kvmInSE=false max_stack_size=67108864 output=cout @@ -248,6 +251,7 @@ clk_domain=system.clk_domain eventq_index=0 forward_latency=4 frontend_latency=3 +point_of_coherency=true response_latency=2 snoop_filter=Null snoop_response_latency=4 diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/simerr b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/simerr index 1a4f96712..e69de29bb 100755 --- a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/simerr +++ b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/simerr @@ -1 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/simout b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/simout index af6242a6d..b0dd0015e 100755 --- a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/simout +++ b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/simout @@ -1,12 +1,14 @@ +Redirecting stdout to build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-atomic/simout +Redirecting stderr to build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-atomic/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2014 12:08:08 -gem5 started Jan 23 2014 17:19:30 -gem5 executing on u200540-lin -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-atomic +gem5 compiled Mar 16 2016 15:51:04 +gem5 started Mar 16 2016 16:37:21 +gem5 executing on dinar2c11, pid 16154 +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-atomic -re /home/stever/gem5-public/tests/run.py build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-atomic + Global frequency set at 1000000000000 ticks per second - 0: system.cpu.isa: ISA system set to: 0 0x5d016c0 info: Entering event queue @ 0. Starting simulation... Reading the dictionary files: ************************************************* @@ -68,4 +70,4 @@ info: Increasing stack size by one page. about 2 million people attended the five best costumes got prizes No errors! -Exiting @ tick 290498967000 because target called exit() +Exiting @ tick 279360903000 because target called exit() diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt index 04541cf46..99322fb1a 100644 --- a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt @@ -1,40 +1,40 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.279362 # Number of seconds simulated -sim_ticks 279362298000 # Number of ticks simulated -final_tick 279362298000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.279361 # Number of seconds simulated +sim_ticks 279360903000 # Number of ticks simulated +final_tick 279360903000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1944100 # Simulator instruction rate (inst/s) -host_op_rate 2105717 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1072104103 # Simulator tick rate (ticks/s) -host_mem_usage 306580 # Number of bytes of host memory used -host_seconds 260.57 # Real time elapsed on the host -sim_insts 506581608 # Number of instructions simulated -sim_ops 548694829 # Number of ops (including micro ops) simulated +host_inst_rate 505182 # Simulator instruction rate (inst/s) +host_op_rate 547179 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 278590581 # Simulator tick rate (ticks/s) +host_mem_usage 293956 # Number of bytes of host memory used +host_seconds 1002.77 # Real time elapsed on the host +sim_insts 506578818 # Number of instructions simulated +sim_ops 548692039 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 2066445504 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 422852701 # Number of bytes read from this memory -system.physmem.bytes_read::total 2489298205 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 2066445504 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 2066445504 # Number of instructions bytes read from this memory -system.physmem.bytes_written::cpu.data 216067624 # Number of bytes written to this memory -system.physmem.bytes_written::total 216067624 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 516611376 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 115591527 # Number of read requests responded to by this memory -system.physmem.num_reads::total 632202903 # Number of read requests responded to by this memory -system.physmem.num_writes::cpu.data 55727847 # Number of write requests responded to by this memory -system.physmem.num_writes::total 55727847 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 7397009256 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1513635534 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 8910644789 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 7397009256 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 7397009256 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 773431582 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 773431582 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 7397009256 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2287067115 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 9684076371 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 2066434344 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 422848347 # Number of bytes read from this memory +system.physmem.bytes_read::total 2489282691 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 2066434344 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 2066434344 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 216066596 # Number of bytes written to this memory +system.physmem.bytes_written::total 216066596 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 516608586 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 115590054 # Number of read requests responded to by this memory +system.physmem.num_reads::total 632198640 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 55727590 # Number of write requests responded to by this memory +system.physmem.num_writes::total 55727590 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 7397006245 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1513627506 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 8910633751 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 7397006245 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 7397006245 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 773431764 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 773431764 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 7397006245 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2287059270 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 9684065515 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -153,33 +153,33 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu.numCycles 558724597 # number of cpu cycles simulated +system.cpu.numCycles 558721807 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 506581608 # Number of instructions committed -system.cpu.committedOps 548694829 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 448454356 # Number of integer alu accesses +system.cpu.committedInsts 506578818 # Number of instructions committed +system.cpu.committedOps 548692039 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 448447005 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses system.cpu.num_func_calls 19311615 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 90667196 # number of instructions that are conditional controls -system.cpu.num_int_insts 448454356 # number of integer instructions +system.cpu.num_conditional_control_insts 90670594 # number of instructions that are conditional controls +system.cpu.num_int_insts 448447005 # number of integer instructions system.cpu.num_fp_insts 16 # number of float instructions -system.cpu.num_int_register_reads 749039746 # number of times the integer registers were read -system.cpu.num_int_register_writes 290003067 # number of times the integer registers were written +system.cpu.num_int_register_reads 749023756 # number of times the integer registers were read +system.cpu.num_int_register_writes 289993515 # number of times the integer registers were written system.cpu.num_fp_register_reads 16 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_cc_register_reads 1634230250 # number of times the CC registers were read -system.cpu.num_cc_register_writes 344080722 # number of times the CC registers were written -system.cpu.num_mem_refs 172745235 # number of memory refs -system.cpu.num_load_insts 115884756 # Number of load instructions -system.cpu.num_store_insts 56860479 # Number of store instructions +system.cpu.num_cc_register_reads 1634221880 # number of times the CC registers were read +system.cpu.num_cc_register_writes 344062197 # number of times the CC registers were written +system.cpu.num_mem_refs 172743505 # number of memory refs +system.cpu.num_load_insts 115883283 # Number of load instructions +system.cpu.num_store_insts 56860222 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 558724596.998000 # Number of busy cycles +system.cpu.num_busy_cycles 558721806.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 121548302 # Number of branches fetched +system.cpu.Branches 121552863 # Number of branches fetched system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 375610922 68.46% 68.46% # Class of executed instruction +system.cpu.op_class::IntAlu 375609862 68.46% 68.46% # Class of executed instruction system.cpu.op_class::IntMult 339219 0.06% 68.52% # Class of executed instruction system.cpu.op_class::IntDiv 0 0.00% 68.52% # Class of executed instruction system.cpu.op_class::FloatAdd 0 0.00% 68.52% # Class of executed instruction @@ -208,36 +208,36 @@ system.cpu.op_class::SimdFloatMisc 3 0.00% 68.52% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 68.52% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 68.52% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 68.52% # Class of executed instruction -system.cpu.op_class::MemRead 115884756 21.12% 89.64% # Class of executed instruction -system.cpu.op_class::MemWrite 56860479 10.36% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 115883283 21.12% 89.64% # Class of executed instruction +system.cpu.op_class::MemWrite 56860222 10.36% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 548695379 # Class of executed instruction -system.membus.trans_dist::ReadReq 630711791 # Transaction distribution -system.membus.trans_dist::ReadResp 632200332 # Transaction distribution -system.membus.trans_dist::WriteReq 54239306 # Transaction distribution -system.membus.trans_dist::WriteResp 54239306 # Transaction distribution +system.cpu.op_class::total 548692589 # Class of executed instruction +system.membus.trans_dist::ReadReq 630707528 # Transaction distribution +system.membus.trans_dist::ReadResp 632196069 # Transaction distribution +system.membus.trans_dist::WriteReq 54239049 # Transaction distribution +system.membus.trans_dist::WriteResp 54239049 # Transaction distribution system.membus.trans_dist::SoftPFReq 2571 # Transaction distribution system.membus.trans_dist::SoftPFResp 2571 # Transaction distribution system.membus.trans_dist::LoadLockedReq 1488541 # Transaction distribution system.membus.trans_dist::StoreCondReq 1488541 # Transaction distribution system.membus.trans_dist::StoreCondResp 1488541 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 1033222752 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 342638748 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1375861500 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 2066445504 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 638920325 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 2705365829 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 1033217172 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 342635288 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1375852460 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 2066434344 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 638914943 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 2705349287 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 687930750 # Request fanout histogram -system.membus.snoop_fanout::mean 0.750964 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.432455 # Request fanout histogram +system.membus.snoop_fanout::samples 687926230 # Request fanout histogram +system.membus.snoop_fanout::mean 0.750965 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.432454 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 171319374 24.90% 24.90% # Request fanout histogram -system.membus.snoop_fanout::1 516611376 75.10% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 171317644 24.90% 24.90% # Request fanout histogram +system.membus.snoop_fanout::1 516608586 75.10% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 687930750 # Request fanout histogram +system.membus.snoop_fanout::total 687926230 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini b/tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini index bc3661e7a..46644e2cb 100644 --- a/tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini @@ -15,6 +15,7 @@ boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain eventq_index=0 +exit_on_work_items=false init_param=0 kernel= kernel_addr_check=true @@ -24,6 +25,7 @@ mem_mode=timing mem_ranges= memories=system.physmem mmap_using_noreserve=false +multi_thread=false num_work_ids=16 readfile= symbolfile= @@ -85,9 +87,9 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +clusivity=mostly_incl demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=2 is_read_only=false max_miss_count=0 @@ -101,6 +103,7 @@ system=system tags=system.cpu.dcache.tags tgts_per_mshr=20 write_buffers=8 +writeback_clean=false cpu_side=system.cpu.dcache_port mem_side=system.cpu.toL2Bus.slave[1] @@ -161,9 +164,9 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +clusivity=mostly_incl demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=2 is_read_only=true max_miss_count=0 @@ -177,6 +180,7 @@ system=system tags=system.cpu.icache.tags tgts_per_mshr=20 write_buffers=8 +writeback_clean=true cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.slave[0] @@ -196,6 +200,7 @@ eventq_index=0 [system.cpu.isa] type=ArmISA +decoderFlavour=Generic eventq_index=0 fpsid=1090793632 id_aa64afr0_el1=0 @@ -271,9 +276,9 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +clusivity=mostly_incl demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=20 is_read_only=false max_miss_count=0 @@ -287,6 +292,7 @@ system=system tags=system.cpu.l2cache.tags tgts_per_mshr=12 write_buffers=8 +writeback_clean=false cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] @@ -302,12 +308,14 @@ size=2097152 [system.cpu.toL2Bus] type=CoherentXBar +children=snoop_filter clk_domain=system.cpu_clk_domain eventq_index=0 forward_latency=0 frontend_latency=1 +point_of_coherency=false response_latency=1 -snoop_filter=Null +snoop_filter=system.cpu.toL2Bus.snoop_filter snoop_response_latency=1 system=system use_default_range=false @@ -315,6 +323,13 @@ width=32 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port +[system.cpu.toL2Bus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=0 +max_capacity=8388608 +system=system + [system.cpu.tracer] type=ExeTracer eventq_index=0 @@ -329,9 +344,9 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/parser +executable=/dist/m5/cpu2000/binaries/arm/linux/parser gid=100 -input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in +input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in kvmInSE=false max_stack_size=67108864 output=cout @@ -364,6 +379,7 @@ clk_domain=system.clk_domain eventq_index=0 forward_latency=4 frontend_latency=3 +point_of_coherency=true response_latency=2 snoop_filter=Null snoop_response_latency=4 diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/simerr b/tests/long/se/20.parser/ref/arm/linux/simple-timing/simerr index 1a4f96712..e69de29bb 100755 --- a/tests/long/se/20.parser/ref/arm/linux/simple-timing/simerr +++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/simerr @@ -1 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/simout b/tests/long/se/20.parser/ref/arm/linux/simple-timing/simout index 36fd0e9c5..7596ee7d2 100755 --- a/tests/long/se/20.parser/ref/arm/linux/simple-timing/simout +++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/simout @@ -1,12 +1,14 @@ +Redirecting stdout to build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-timing/simout +Redirecting stderr to build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2014 12:08:08 -gem5 started Jan 23 2014 17:21:27 -gem5 executing on u200540-lin -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-timing +gem5 compiled Mar 16 2016 15:51:04 +gem5 started Mar 16 2016 15:51:37 +gem5 executing on dinar2c11, pid 15211 +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-timing -re /home/stever/gem5-public/tests/run.py build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-timing + Global frequency set at 1000000000000 ticks per second - 0: system.cpu.isa: ISA system set to: 0 0x6322040 info: Entering event queue @ 0. Starting simulation... Reading the dictionary files: ************************************************* @@ -68,4 +70,4 @@ info: Increasing stack size by one page. about 2 million people attended the five best costumes got prizes No errors! -Exiting @ tick 717366012000 because target called exit() +Exiting @ tick 708539449500 because target called exit() diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt index d35883c7b..0a916209d 100644 --- a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.708526 # Number of seconds simulated -sim_ticks 708526400500 # Number of ticks simulated -final_tick 708526400500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.708539 # Number of seconds simulated +sim_ticks 708539449500 # Number of ticks simulated +final_tick 708539449500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 942956 # Simulator instruction rate (inst/s) -host_op_rate 1021179 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1323022561 # Simulator tick rate (ticks/s) -host_mem_usage 320452 # Number of bytes of host memory used -host_seconds 535.54 # Real time elapsed on the host -sim_insts 504986854 # Number of instructions simulated -sim_ops 546878105 # Number of ops (including micro ops) simulated +host_inst_rate 318121 # Simulator instruction rate (inst/s) +host_op_rate 344511 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 446353500 # Simulator tick rate (ticks/s) +host_mem_usage 303968 # Number of bytes of host memory used +host_seconds 1587.40 # Real time elapsed on the host +sim_insts 504984064 # Number of instructions simulated +sim_ops 546875315 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 147392 # Number of bytes read from this memory @@ -25,17 +25,17 @@ system.physmem.num_reads::cpu.data 140061 # Nu system.physmem.num_reads::total 142364 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 96330 # Number of write requests responded to by this memory system.physmem.num_writes::total 96330 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 208026 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 12651475 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 12859501 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 208026 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 208026 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 8701327 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 8701327 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 8701327 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 208026 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 12651475 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 21560828 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 208022 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 12651242 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 12859264 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 208022 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 208022 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 8701167 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 8701167 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 8701167 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 208022 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 12651242 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 21560431 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -154,33 +154,33 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu.numCycles 1417052801 # number of cpu cycles simulated +system.cpu.numCycles 1417078899 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 504986854 # Number of instructions committed -system.cpu.committedOps 546878105 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 448454356 # Number of integer alu accesses +system.cpu.committedInsts 504984064 # Number of instructions committed +system.cpu.committedOps 546875315 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 448447005 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses system.cpu.num_func_calls 19311615 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 90667196 # number of instructions that are conditional controls -system.cpu.num_int_insts 448454356 # number of integer instructions +system.cpu.num_conditional_control_insts 90670594 # number of instructions that are conditional controls +system.cpu.num_int_insts 448447005 # number of integer instructions system.cpu.num_fp_insts 16 # number of float instructions -system.cpu.num_int_register_reads 748355652 # number of times the integer registers were read -system.cpu.num_int_register_writes 290003067 # number of times the integer registers were written +system.cpu.num_int_register_reads 748339662 # number of times the integer registers were read +system.cpu.num_int_register_writes 289993515 # number of times the integer registers were written system.cpu.num_fp_register_reads 16 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_cc_register_reads 1984297859 # number of times the CC registers were read -system.cpu.num_cc_register_writes 344080722 # number of times the CC registers were written -system.cpu.num_mem_refs 172745235 # number of memory refs -system.cpu.num_load_insts 115884756 # Number of load instructions -system.cpu.num_store_insts 56860479 # Number of store instructions +system.cpu.num_cc_register_reads 1984285070 # number of times the CC registers were read +system.cpu.num_cc_register_writes 344062197 # number of times the CC registers were written +system.cpu.num_mem_refs 172743505 # number of memory refs +system.cpu.num_load_insts 115883283 # Number of load instructions +system.cpu.num_store_insts 56860222 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 1417052800.998000 # Number of busy cycles +system.cpu.num_busy_cycles 1417078898.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 121548302 # Number of branches fetched +system.cpu.Branches 121552863 # Number of branches fetched system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 375610922 68.46% 68.46% # Class of executed instruction +system.cpu.op_class::IntAlu 375609862 68.46% 68.46% # Class of executed instruction system.cpu.op_class::IntMult 339219 0.06% 68.52% # Class of executed instruction system.cpu.op_class::IntDiv 0 0.00% 68.52% # Class of executed instruction system.cpu.op_class::FloatAdd 0 0.00% 68.52% # Class of executed instruction @@ -209,18 +209,18 @@ system.cpu.op_class::SimdFloatMisc 3 0.00% 68.52% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 68.52% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 68.52% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 68.52% # Class of executed instruction -system.cpu.op_class::MemRead 115884756 21.12% 89.64% # Class of executed instruction -system.cpu.op_class::MemWrite 56860479 10.36% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 115883283 21.12% 89.64% # Class of executed instruction +system.cpu.op_class::MemWrite 56860222 10.36% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 548695379 # Class of executed instruction -system.cpu.dcache.tags.replacements 1134822 # number of replacements -system.cpu.dcache.tags.tagsinuse 4065.260615 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 170180456 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1138918 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 149.422922 # Average number of references to valid blocks. +system.cpu.op_class::total 548692589 # Class of executed instruction +system.cpu.dcache.tags.replacements 1136276 # number of replacements +system.cpu.dcache.tags.tagsinuse 4065.261181 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 170177272 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1140372 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 149.229613 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 11750119500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4065.260615 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 4065.261181 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.992495 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.992495 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id @@ -230,72 +230,72 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 343 system.cpu.dcache.tags.age_task_id_blocks_1024::3 3546 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 165 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 343777666 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 343777666 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 113317758 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 113317758 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 53883046 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 53883046 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 343775660 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 343775660 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 113315079 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 113315079 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 53882541 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 53882541 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 2570 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 2570 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488541 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 1488541 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 167200804 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 167200804 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 167203374 # number of overall hits -system.cpu.dcache.overall_hits::total 167203374 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 782657 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 782657 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 356260 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 356260 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 167197620 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 167197620 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 167200190 # number of overall hits +system.cpu.dcache.overall_hits::total 167200190 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 783863 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 783863 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 356508 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 356508 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 1 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 1 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 1138917 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1138917 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1138918 # number of overall misses -system.cpu.dcache.overall_misses::total 1138918 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 12104797500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 12104797500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 9574077500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 9574077500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 21678875000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 21678875000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 21678875000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 21678875000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 114100415 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 114100415 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 1140371 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1140371 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1140372 # number of overall misses +system.cpu.dcache.overall_misses::total 1140372 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 12120585500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 12120585500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 9577302500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 9577302500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 21697888000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 21697888000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 21697888000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 21697888000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 114098942 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 114098942 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 54239049 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 54239049 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 2571 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::total 2571 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488541 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 1488541 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 168339721 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 168339721 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 168342292 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 168342292 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.006859 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.006859 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006568 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.006568 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 168337991 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 168337991 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 168340562 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 168340562 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.006870 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.006870 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006573 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.006573 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000389 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 0.000389 # miss rate for SoftPFReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.006766 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.006766 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.006765 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.006765 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15466.286636 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 15466.286636 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26873.849155 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 26873.849155 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 19034.639925 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 19034.639925 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 19034.623213 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 19034.623213 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.006774 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.006774 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.006774 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.006774 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15462.632501 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 15462.632501 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26864.200803 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 26864.200803 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 19027.042954 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 19027.042954 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 19027.026269 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 19027.026269 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -304,58 +304,58 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1064678 # number of writebacks -system.cpu.dcache.writebacks::total 1064678 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 782657 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 782657 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 356260 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 356260 # number of WriteReq MSHR misses +system.cpu.dcache.writebacks::writebacks 1065708 # number of writebacks +system.cpu.dcache.writebacks::total 1065708 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 783863 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 783863 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 356508 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 356508 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1138917 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1138917 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1138918 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1138918 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 11322140500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 11322140500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9217817500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 9217817500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 1140371 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1140371 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1140372 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1140372 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 11336722500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 11336722500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9220794500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 9220794500 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 61000 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 61000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 20539958000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 20539958000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 20540019000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 20540019000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006859 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006859 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006568 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006568 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 20557517000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 20557517000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 20557578000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 20557578000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006870 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006870 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006573 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006573 # mshr miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.000389 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.000389 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006766 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.006766 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006765 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.006765 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14466.286636 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14466.286636 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25873.849155 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25873.849155 # average WriteReq mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006774 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.006774 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006774 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.006774 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14462.632501 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14462.632501 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25864.200803 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25864.200803 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 61000 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 61000 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18034.639925 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 18034.639925 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18034.677650 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 18034.677650 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18027.042954 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 18027.042954 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18027.080637 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 18027.080637 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 9788 # number of replacements -system.cpu.icache.tags.tagsinuse 983.180611 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 516599856 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 983.198764 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 516597066 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 11521 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 44839.845152 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 44839.602986 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 983.180611 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.480069 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.480069 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 983.198764 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.480078 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.480078 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1733 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 24 # Occupied blocks per task id @@ -363,44 +363,44 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2 24 system.cpu.icache.tags.age_task_id_blocks_1024::3 256 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1402 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.846191 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 1033234275 # Number of tag accesses -system.cpu.icache.tags.data_accesses 1033234275 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 516599856 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 516599856 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 516599856 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 516599856 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 516599856 # number of overall hits -system.cpu.icache.overall_hits::total 516599856 # number of overall hits +system.cpu.icache.tags.tag_accesses 1033228695 # Number of tag accesses +system.cpu.icache.tags.data_accesses 1033228695 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 516597066 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 516597066 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 516597066 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 516597066 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 516597066 # number of overall hits +system.cpu.icache.overall_hits::total 516597066 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 11521 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 11521 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 11521 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 11521 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 11521 # number of overall misses system.cpu.icache.overall_misses::total 11521 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 263208000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 263208000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 263208000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 263208000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 263208000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 263208000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 516611377 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 516611377 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 516611377 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 516611377 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 516611377 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 516611377 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 263211000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 263211000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 263211000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 263211000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 263211000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 263211000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 516608587 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 516608587 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 516608587 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 516608587 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 516608587 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 516608587 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000022 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000022 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000022 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000022 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000022 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000022 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22845.933513 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 22845.933513 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 22845.933513 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 22845.933513 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 22845.933513 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 22845.933513 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22846.193907 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 22846.193907 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 22846.193907 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 22846.193907 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 22846.193907 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 22846.193907 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -417,62 +417,62 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 11521 system.cpu.icache.demand_mshr_misses::total 11521 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 11521 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 11521 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 251687000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 251687000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 251687000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 251687000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 251687000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 251687000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 251690000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 251690000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 251690000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 251690000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 251690000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 251690000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000022 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000022 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000022 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21845.933513 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21845.933513 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21845.933513 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 21845.933513 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21845.933513 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 21845.933513 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21846.193907 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21846.193907 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21846.193907 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 21846.193907 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21846.193907 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 21846.193907 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 110394 # number of replacements -system.cpu.l2cache.tags.tagsinuse 27250.637055 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1744409 # Total number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 27252.086651 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1747015 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 141582 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 12.320839 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 339114860000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 23374.350264 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 240.190674 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 3636.096117 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.713329 # Average percentage of cache occupancy +system.cpu.l2cache.tags.avg_refs 12.339245 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 339115608000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 23375.830047 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 240.203585 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 3636.053019 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.713374 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.007330 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.110965 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.831623 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.110964 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.831668 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 31188 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 72 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::2 283 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3657 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27176 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.951782 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 18830546 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 18830546 # Number of data accesses -system.cpu.l2cache.WritebackDirty_hits::writebacks 1064678 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 1064678 # number of WritebackDirty hits +system.cpu.l2cache.tags.tag_accesses 18853226 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 18853226 # Number of data accesses +system.cpu.l2cache.WritebackDirty_hits::writebacks 1065708 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 1065708 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 9751 # number of WritebackClean hits system.cpu.l2cache.WritebackClean_hits::total 9751 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 255472 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 255472 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 255720 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 255720 # number of ReadExReq hits system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 9218 # number of ReadCleanReq hits system.cpu.l2cache.ReadCleanReq_hits::total 9218 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 743385 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 743385 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 744591 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 744591 # number of ReadSharedReq hits system.cpu.l2cache.demand_hits::cpu.inst 9218 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 998857 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1008075 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 1000311 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1009529 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 9218 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 998857 # number of overall hits -system.cpu.l2cache.overall_hits::total 1008075 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 1000311 # number of overall hits +system.cpu.l2cache.overall_hits::total 1009529 # number of overall hits system.cpu.l2cache.ReadExReq_misses::cpu.data 100788 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 100788 # number of ReadExReq misses system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2303 # number of ReadCleanReq misses @@ -485,58 +485,58 @@ system.cpu.l2cache.demand_misses::total 142364 # nu system.cpu.l2cache.overall_misses::cpu.inst 2303 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 140061 # number of overall misses system.cpu.l2cache.overall_misses::total 142364 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6000938500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 6000938500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 137230000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 137230000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 2339453000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 2339453000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 137230000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 8340391500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 8477621500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 137230000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 8340391500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 8477621500 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 1064678 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 1064678 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6000939500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 6000939500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 137232000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 137232000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 2339459000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 2339459000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 137232000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 8340398500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 8477630500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 137232000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 8340398500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 8477630500 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 1065708 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 1065708 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::writebacks 9751 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::total 9751 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 356260 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 356260 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 356508 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 356508 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 11521 # number of ReadCleanReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::total 11521 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 782658 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 782658 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 783864 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 783864 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 11521 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1138918 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 1150439 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1140372 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 1151893 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 11521 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1138918 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 1150439 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.282906 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.282906 # miss rate for ReadExReq accesses +system.cpu.l2cache.overall_accesses::cpu.data 1140372 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 1151893 # number of overall (read+write) accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.282709 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.282709 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.199896 # miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.199896 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.050179 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.050179 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.050102 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.050102 # miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.199896 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.122977 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.123748 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.122820 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.123591 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.199896 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.122977 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.123748 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59540.208160 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59540.208160 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59587.494572 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59587.494572 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59568.991419 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59568.991419 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59587.494572 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59548.278964 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 59548.913349 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59587.494572 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59548.278964 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 59548.913349 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::cpu.data 0.122820 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.123591 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59540.218082 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59540.218082 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59588.363005 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59588.363005 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59569.144196 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59569.144196 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59588.363005 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59548.328942 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 59548.976567 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59588.363005 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59548.328942 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 59548.976567 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -561,82 +561,82 @@ system.cpu.l2cache.demand_mshr_misses::total 142364 system.cpu.l2cache.overall_mshr_misses::cpu.inst 2303 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 140061 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 142364 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4993058500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4993058500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 114200000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 114200000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1946723000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1946723000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 114200000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6939781500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 7053981500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 114200000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6939781500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 7053981500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4993059500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4993059500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 114202000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 114202000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1946729000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1946729000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 114202000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6939788500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 7053990500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 114202000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6939788500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 7053990500 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.282906 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.282906 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.282709 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.282709 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.199896 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.199896 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.050179 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.050179 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.050102 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.050102 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.199896 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.122977 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.123748 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.122820 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.123591 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.199896 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.122977 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.123748 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49540.208160 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49540.208160 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49587.494572 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49587.494572 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49568.991419 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49568.991419 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49587.494572 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49548.278964 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49548.913349 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49587.494572 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49548.278964 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49548.913349 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.122820 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.123591 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49540.218082 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49540.218082 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49588.363005 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49588.363005 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49569.144196 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49569.144196 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49588.363005 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49548.328942 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49548.976567 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49588.363005 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49548.328942 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49548.976567 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 2295049 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 1144662 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3461 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 2297957 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 1146116 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3565 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 2146 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2145 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadResp 794179 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 1161008 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 795385 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 1162038 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 9788 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 84208 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 356260 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 356260 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 84632 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 356508 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 356508 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 11521 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 782658 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 783864 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 32830 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3412658 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 3445488 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3417020 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 3449850 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1363776 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141030144 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 142393920 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141189120 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 142552896 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 110394 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 1260833 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.004489 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.066862 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 1262287 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.004566 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.067432 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 1255174 99.55% 99.55% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 5658 0.45% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 1256524 99.54% 99.54% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 5762 0.46% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 1260833 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 2221990500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 1262287 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 2224474500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 17281500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1708377000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1710558000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) system.membus.trans_dist::ReadResp 41576 # Transaction distribution system.membus.trans_dist::WritebackDirty 96330 # Transaction distribution @@ -659,7 +659,7 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 250615 # Request fanout histogram -system.membus.reqLayer0.occupancy 644475328 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 644476328 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) system.membus.respLayer1.occupancy 711820000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/config.ini b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/config.ini index bdb9561f0..9f3703298 100644 --- a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/config.ini +++ b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/config.ini @@ -15,6 +15,7 @@ boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain eventq_index=0 +exit_on_work_items=false init_param=0 kernel= kernel_addr_check=true @@ -24,6 +25,7 @@ mem_mode=atomic mem_ranges= memories=system.physmem mmap_using_noreserve=false +multi_thread=false num_work_ids=16 readfile= symbolfile= @@ -147,9 +149,9 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/parser +executable=/dist/m5/cpu2000/binaries/x86/linux/parser gid=100 -input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in +input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in kvmInSE=false max_stack_size=67108864 output=cout @@ -182,6 +184,7 @@ clk_domain=system.clk_domain eventq_index=0 forward_latency=4 frontend_latency=3 +point_of_coherency=true response_latency=2 snoop_filter=Null snoop_response_latency=4 diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simerr b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simerr index 1a4f96712..e69de29bb 100755 --- a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simerr +++ b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simerr @@ -1 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simout b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simout index cbb107c47..ff0a5c91f 100755 --- a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simout +++ b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simout @@ -1,10 +1,13 @@ +Redirecting stdout to build/X86/tests/opt/long/se/20.parser/x86/linux/simple-atomic/simout +Redirecting stderr to build/X86/tests/opt/long/se/20.parser/x86/linux/simple-atomic/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 22 2014 17:10:34 -gem5 started Jan 22 2014 20:48:32 -gem5 executing on u200540-lin -command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/simple-atomic +gem5 compiled Mar 16 2016 15:38:19 +gem5 started Mar 16 2016 15:38:59 +gem5 executing on dinar2c11, pid 14361 +command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/simple-atomic -re /home/stever/gem5-public/tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/simple-atomic + Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -69,4 +72,4 @@ info: Increasing stack size by one page. about 2 million people attended the five best costumes got prizes No errors! -Exiting @ tick 885229328000 because target called exit() +Exiting @ tick 885256008500 because target called exit() diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt index 1702837e8..a821d05f5 100644 --- a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt @@ -1,72 +1,72 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.885229 # Number of seconds simulated -sim_ticks 885229328000 # Number of ticks simulated -final_tick 885229328000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.885256 # Number of seconds simulated +sim_ticks 885256008500 # Number of ticks simulated +final_tick 885256008500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1361574 # Simulator instruction rate (inst/s) -host_op_rate 2517703 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1457659146 # Simulator tick rate (ticks/s) -host_mem_usage 313840 # Number of bytes of host memory used -host_seconds 607.30 # Real time elapsed on the host -sim_insts 826877110 # Number of instructions simulated -sim_ops 1528988702 # Number of ops (including micro ops) simulated +host_inst_rate 362789 # Simulator instruction rate (inst/s) +host_op_rate 670835 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 388389023 # Simulator tick rate (ticks/s) +host_mem_usage 304128 # Number of bytes of host memory used +host_seconds 2279.30 # Real time elapsed on the host +sim_insts 826906380 # Number of instructions simulated +sim_ops 1529035683 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 8546776520 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 2285655658 # Number of bytes read from this memory -system.physmem.bytes_read::total 10832432178 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 8546776520 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 8546776520 # Number of instructions bytes read from this memory -system.physmem.bytes_written::cpu.data 991849462 # Number of bytes written to this memory -system.physmem.bytes_written::total 991849462 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1068347065 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 384102186 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1452449251 # Number of read requests responded to by this memory -system.physmem.num_writes::cpu.data 149160202 # Number of write requests responded to by this memory -system.physmem.num_writes::total 149160202 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 9654872754 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2581992695 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 12236865449 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 9654872754 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 9654872754 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1120443517 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1120443517 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 9654872754 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3702436212 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 13357308966 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 8547061720 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 2285750420 # Number of bytes read from this memory +system.physmem.bytes_read::total 10832812140 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 8547061720 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 8547061720 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 991875282 # Number of bytes written to this memory +system.physmem.bytes_written::total 991875282 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 1068382715 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 384117854 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1452500569 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 149164510 # Number of write requests responded to by this memory +system.physmem.num_writes::total 149164510 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 9654903935 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2582021921 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 12236925856 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 9654903935 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 9654903935 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1120438915 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1120438915 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 9654903935 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3702460837 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 13357364772 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 551 # Number of system calls -system.cpu.numCycles 1770458657 # number of cpu cycles simulated +system.cpu.numCycles 1770512018 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 826877110 # Number of instructions committed -system.cpu.committedOps 1528988702 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 1526605510 # Number of integer alu accesses +system.cpu.committedInsts 826906380 # Number of instructions committed +system.cpu.committedOps 1529035683 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 1526653037 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu.num_func_calls 35346287 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 92658795 # number of instructions that are conditional controls -system.cpu.num_int_insts 1526605510 # number of integer instructions +system.cpu.num_conditional_control_insts 92662756 # number of instructions that are conditional controls +system.cpu.num_int_insts 1526653037 # number of integer instructions system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 3293771378 # number of times the integer registers were read -system.cpu.num_int_register_writes 1237355109 # number of times the integer registers were written +system.cpu.num_int_register_reads 3293861747 # number of times the integer registers were read +system.cpu.num_int_register_writes 1237389453 # number of times the integer registers were written system.cpu.num_fp_register_reads 0 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_cc_register_reads 561334882 # number of times the CC registers were read -system.cpu.num_cc_register_writes 376685745 # number of times the CC registers were written -system.cpu.num_mem_refs 533262343 # number of memory refs -system.cpu.num_load_insts 384102157 # Number of load instructions -system.cpu.num_store_insts 149160186 # Number of store instructions +system.cpu.num_cc_register_reads 561356848 # number of times the CC registers were read +system.cpu.num_cc_register_writes 376698535 # number of times the CC registers were written +system.cpu.num_mem_refs 533282319 # number of memory refs +system.cpu.num_load_insts 384117825 # Number of load instructions +system.cpu.num_store_insts 149164494 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 1770458656.998000 # Number of busy cycles +system.cpu.num_busy_cycles 1770512017.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 149758583 # Number of branches fetched -system.cpu.op_class::No_OpClass 1819099 0.12% 0.12% # Class of executed instruction -system.cpu.op_class::IntAlu 989721890 64.73% 64.85% # Class of executed instruction +system.cpu.Branches 149762544 # Number of branches fetched +system.cpu.op_class::No_OpClass 1818553 0.12% 0.12% # Class of executed instruction +system.cpu.op_class::IntAlu 989751625 64.73% 64.85% # Class of executed instruction system.cpu.op_class::IntMult 306834 0.02% 64.87% # Class of executed instruction -system.cpu.op_class::IntDiv 3878536 0.25% 65.12% # Class of executed instruction +system.cpu.op_class::IntDiv 3876352 0.25% 65.12% # Class of executed instruction system.cpu.op_class::FloatAdd 0 0.00% 65.12% # Class of executed instruction system.cpu.op_class::FloatCmp 0 0.00% 65.12% # Class of executed instruction system.cpu.op_class::FloatCvt 0 0.00% 65.12% # Class of executed instruction @@ -93,35 +93,35 @@ system.cpu.op_class::SimdFloatMisc 0 0.00% 65.12% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 65.12% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.12% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.12% # Class of executed instruction -system.cpu.op_class::MemRead 384102157 25.12% 90.24% # Class of executed instruction -system.cpu.op_class::MemWrite 149160186 9.76% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 384117825 25.12% 90.24% # Class of executed instruction +system.cpu.op_class::MemWrite 149164494 9.76% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 1528988702 # Class of executed instruction -system.membus.trans_dist::ReadReq 1452449251 # Transaction distribution -system.membus.trans_dist::ReadResp 1452449251 # Transaction distribution -system.membus.trans_dist::WriteReq 149160202 # Transaction distribution -system.membus.trans_dist::WriteResp 149160202 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 2136694130 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.icache_port::total 2136694130 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 1066524776 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::total 1066524776 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 3203218906 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 8546776520 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::total 8546776520 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 3277505120 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::total 3277505120 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 11824281640 # Cumulative packet size per connected master and slave (bytes) +system.cpu.op_class::total 1529035683 # Class of executed instruction +system.membus.trans_dist::ReadReq 1452500569 # Transaction distribution +system.membus.trans_dist::ReadResp 1452500569 # Transaction distribution +system.membus.trans_dist::WriteReq 149164510 # Transaction distribution +system.membus.trans_dist::WriteResp 149164510 # Transaction distribution +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 2136765430 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.icache_port::total 2136765430 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 1066564728 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::total 1066564728 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 3203330158 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 8547061720 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::total 8547061720 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 3277625702 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::total 3277625702 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 11824687422 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 1601609453 # Request fanout histogram -system.membus.snoop_fanout::mean 0.667046 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.471270 # Request fanout histogram +system.membus.snoop_fanout::samples 1601665079 # Request fanout histogram +system.membus.snoop_fanout::mean 0.667045 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.471271 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 533262388 33.30% 33.30% # Request fanout histogram -system.membus.snoop_fanout::1 1068347065 66.70% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 533282364 33.30% 33.30% # Request fanout histogram +system.membus.snoop_fanout::1 1068382715 66.70% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 1601609453 # Request fanout histogram +system.membus.snoop_fanout::total 1601665079 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini b/tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini index bab78d9da..4292720d5 100644 --- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini +++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini @@ -15,6 +15,7 @@ boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain eventq_index=0 +exit_on_work_items=false init_param=0 kernel= kernel_addr_check=true @@ -24,6 +25,7 @@ mem_mode=timing mem_ranges= memories=system.physmem mmap_using_noreserve=false +multi_thread=false num_work_ids=16 readfile= symbolfile= @@ -89,9 +91,9 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +clusivity=mostly_incl demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=2 is_read_only=false max_miss_count=0 @@ -105,6 +107,7 @@ system=system tags=system.cpu.dcache.tags tgts_per_mshr=20 write_buffers=8 +writeback_clean=false cpu_side=system.cpu.dcache_port mem_side=system.cpu.toL2Bus.slave[1] @@ -139,9 +142,9 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +clusivity=mostly_incl demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=2 is_read_only=true max_miss_count=0 @@ -155,6 +158,7 @@ system=system tags=system.cpu.icache.tags tgts_per_mshr=20 write_buffers=8 +writeback_clean=true cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.slave[0] @@ -205,9 +209,9 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +clusivity=mostly_incl demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=20 is_read_only=false max_miss_count=0 @@ -221,6 +225,7 @@ system=system tags=system.cpu.l2cache.tags tgts_per_mshr=12 write_buffers=8 +writeback_clean=false cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] @@ -236,12 +241,14 @@ size=2097152 [system.cpu.toL2Bus] type=CoherentXBar +children=snoop_filter clk_domain=system.cpu_clk_domain eventq_index=0 forward_latency=0 frontend_latency=1 +point_of_coherency=false response_latency=1 -snoop_filter=Null +snoop_filter=system.cpu.toL2Bus.snoop_filter snoop_response_latency=1 system=system use_default_range=false @@ -249,6 +256,13 @@ width=32 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port +[system.cpu.toL2Bus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=0 +max_capacity=8388608 +system=system + [system.cpu.tracer] type=ExeTracer eventq_index=0 @@ -263,9 +277,9 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/parser +executable=/dist/m5/cpu2000/binaries/x86/linux/parser gid=100 -input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in +input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in kvmInSE=false max_stack_size=67108864 output=cout @@ -298,6 +312,7 @@ clk_domain=system.clk_domain eventq_index=0 forward_latency=4 frontend_latency=3 +point_of_coherency=true response_latency=2 snoop_filter=Null snoop_response_latency=4 diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/simerr b/tests/long/se/20.parser/ref/x86/linux/simple-timing/simerr index 1a4f96712..e69de29bb 100755 --- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/simerr +++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/simerr @@ -1 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/simout b/tests/long/se/20.parser/ref/x86/linux/simple-timing/simout index 530ac97a0..cd12e9ca0 100755 --- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/simout +++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/simout @@ -1,10 +1,13 @@ +Redirecting stdout to build/X86/tests/opt/long/se/20.parser/x86/linux/simple-timing/simout +Redirecting stderr to build/X86/tests/opt/long/se/20.parser/x86/linux/simple-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 22 2014 17:10:34 -gem5 started Jan 22 2014 20:57:08 -gem5 executing on u200540-lin -command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/simple-timing +gem5 compiled Mar 16 2016 15:38:19 +gem5 started Mar 16 2016 15:38:49 +gem5 executing on dinar2c11, pid 14355 +command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/simple-timing -re /home/stever/gem5-public/tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/simple-timing + Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -69,4 +72,4 @@ info: Increasing stack size by one page. about 2 million people attended the five best costumes got prizes No errors! -Exiting @ tick 1647872849000 because target called exit() +Exiting @ tick 1650600522500 because target called exit() diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt index 1b9df2638..58e8c99ef 100644 --- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt @@ -1,73 +1,73 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.650527 # Number of seconds simulated -sim_ticks 1650526667500 # Number of ticks simulated -final_tick 1650526667500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.650601 # Number of seconds simulated +sim_ticks 1650600522500 # Number of ticks simulated +final_tick 1650600522500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 726731 # Simulator instruction rate (inst/s) -host_op_rate 1343807 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1450624585 # Simulator tick rate (ticks/s) -host_mem_usage 327760 # Number of bytes of host memory used -host_seconds 1137.80 # Real time elapsed on the host -sim_insts 826877110 # Number of instructions simulated -sim_ops 1528988702 # Number of ops (including micro ops) simulated +host_inst_rate 236277 # Simulator instruction rate (inst/s) +host_op_rate 436901 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 471636555 # Simulator tick rate (ticks/s) +host_mem_usage 314152 # Number of bytes of host memory used +host_seconds 3499.73 # Real time elapsed on the host +sim_insts 826906380 # Number of instructions simulated +sim_ops 1529035683 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 115776 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24258944 # Number of bytes read from this memory -system.physmem.bytes_read::total 24374720 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24258880 # Number of bytes read from this memory +system.physmem.bytes_read::total 24374656 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 115776 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 115776 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 18765248 # Number of bytes written to this memory -system.physmem.bytes_written::total 18765248 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 18765184 # Number of bytes written to this memory +system.physmem.bytes_written::total 18765184 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 1809 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 379046 # Number of read requests responded to by this memory -system.physmem.num_reads::total 380855 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 293207 # Number of write requests responded to by this memory -system.physmem.num_writes::total 293207 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 70145 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 14697699 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14767844 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 70145 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 70145 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 11369249 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 11369249 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 11369249 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 70145 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 14697699 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 26137092 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_reads::cpu.data 379045 # Number of read requests responded to by this memory +system.physmem.num_reads::total 380854 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 293206 # Number of write requests responded to by this memory +system.physmem.num_writes::total 293206 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 70142 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 14697002 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 14767144 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 70142 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 70142 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 11368701 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 11368701 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 11368701 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 70142 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 14697002 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 26135845 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 551 # Number of system calls -system.cpu.numCycles 3301053335 # number of cpu cycles simulated +system.cpu.numCycles 3301201045 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 826877110 # Number of instructions committed -system.cpu.committedOps 1528988702 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 1526605510 # Number of integer alu accesses +system.cpu.committedInsts 826906380 # Number of instructions committed +system.cpu.committedOps 1529035683 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 1526653037 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu.num_func_calls 35346287 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 92658795 # number of instructions that are conditional controls -system.cpu.num_int_insts 1526605510 # number of integer instructions +system.cpu.num_conditional_control_insts 92662756 # number of instructions that are conditional controls +system.cpu.num_int_insts 1526653037 # number of integer instructions system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 3293771378 # number of times the integer registers were read -system.cpu.num_int_register_writes 1237355109 # number of times the integer registers were written +system.cpu.num_int_register_reads 3293861747 # number of times the integer registers were read +system.cpu.num_int_register_writes 1237389453 # number of times the integer registers were written system.cpu.num_fp_register_reads 0 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_cc_register_reads 561334882 # number of times the CC registers were read -system.cpu.num_cc_register_writes 376685745 # number of times the CC registers were written -system.cpu.num_mem_refs 533262343 # number of memory refs -system.cpu.num_load_insts 384102157 # Number of load instructions -system.cpu.num_store_insts 149160186 # Number of store instructions +system.cpu.num_cc_register_reads 561356848 # number of times the CC registers were read +system.cpu.num_cc_register_writes 376698535 # number of times the CC registers were written +system.cpu.num_mem_refs 533282319 # number of memory refs +system.cpu.num_load_insts 384117825 # Number of load instructions +system.cpu.num_store_insts 149164494 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 3301053334.998000 # Number of busy cycles +system.cpu.num_busy_cycles 3301201044.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 149758583 # Number of branches fetched -system.cpu.op_class::No_OpClass 1819099 0.12% 0.12% # Class of executed instruction -system.cpu.op_class::IntAlu 989721890 64.73% 64.85% # Class of executed instruction +system.cpu.Branches 149762544 # Number of branches fetched +system.cpu.op_class::No_OpClass 1818553 0.12% 0.12% # Class of executed instruction +system.cpu.op_class::IntAlu 989751625 64.73% 64.85% # Class of executed instruction system.cpu.op_class::IntMult 306834 0.02% 64.87% # Class of executed instruction -system.cpu.op_class::IntDiv 3878536 0.25% 65.12% # Class of executed instruction +system.cpu.op_class::IntDiv 3876352 0.25% 65.12% # Class of executed instruction system.cpu.op_class::FloatAdd 0 0.00% 65.12% # Class of executed instruction system.cpu.op_class::FloatCmp 0 0.00% 65.12% # Class of executed instruction system.cpu.op_class::FloatCvt 0 0.00% 65.12% # Class of executed instruction @@ -94,18 +94,18 @@ system.cpu.op_class::SimdFloatMisc 0 0.00% 65.12% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 65.12% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.12% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.12% # Class of executed instruction -system.cpu.op_class::MemRead 384102157 25.12% 90.24% # Class of executed instruction -system.cpu.op_class::MemWrite 149160186 9.76% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 384117825 25.12% 90.24% # Class of executed instruction +system.cpu.op_class::MemWrite 149164494 9.76% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 1528988702 # Class of executed instruction -system.cpu.dcache.tags.replacements 2514362 # number of replacements -system.cpu.dcache.tags.tagsinuse 4086.386622 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 530743930 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2518458 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 210.741624 # Average number of references to valid blocks. +system.cpu.op_class::total 1529035683 # Class of executed instruction +system.cpu.dcache.tags.replacements 2515885 # number of replacements +system.cpu.dcache.tags.tagsinuse 4086.387052 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 530762383 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2519981 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 210.621581 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 8246025500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4086.386622 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 4086.387052 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.997653 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.997653 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id @@ -115,56 +115,56 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 29 system.cpu.dcache.tags.age_task_id_blocks_1024::3 4038 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1069043234 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1069043234 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 382374772 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 382374772 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 148369158 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 148369158 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 530743930 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 530743930 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 530743930 # number of overall hits -system.cpu.dcache.overall_hits::total 530743930 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1727414 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1727414 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 791044 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 791044 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2518458 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2518458 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2518458 # number of overall misses -system.cpu.dcache.overall_misses::total 2518458 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 30918235500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 30918235500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 20395021500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 20395021500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 51313257000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 51313257000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 51313257000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 51313257000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 384102186 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 384102186 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 149160202 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 149160202 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 533262388 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 533262388 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 533262388 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 533262388 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004497 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.004497 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005303 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.005303 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.004723 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.004723 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.004723 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.004723 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17898.567165 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 17898.567165 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 25782.410966 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 25782.410966 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 20374.871052 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 20374.871052 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 20374.871052 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 20374.871052 # average overall miss latency +system.cpu.dcache.tags.tag_accesses 1069084709 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1069084709 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 382389020 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 382389020 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 148373363 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 148373363 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 530762383 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 530762383 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 530762383 # number of overall hits +system.cpu.dcache.overall_hits::total 530762383 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1728834 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1728834 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 791147 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 791147 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2519981 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2519981 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2519981 # number of overall misses +system.cpu.dcache.overall_misses::total 2519981 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 30936646500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 30936646500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 20396358500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 20396358500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 51333005000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 51333005000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 51333005000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 51333005000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 384117854 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 384117854 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 149164510 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 149164510 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 533282364 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 533282364 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 533282364 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 533282364 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004501 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.004501 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005304 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.005304 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.004725 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.004725 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.004725 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.004725 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17894.515321 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 17894.515321 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 25780.744286 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 25780.744286 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 20370.393666 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 20370.393666 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 20370.393666 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 20370.393666 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -173,50 +173,50 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2323200 # number of writebacks -system.cpu.dcache.writebacks::total 2323200 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1727414 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1727414 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 791044 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 791044 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2518458 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2518458 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2518458 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2518458 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 29190821500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 29190821500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 19603977500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 19603977500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 48794799000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 48794799000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 48794799000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 48794799000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.004497 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.004497 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005303 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005303 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.004723 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.004723 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.004723 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.004723 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16898.567165 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16898.567165 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24782.410966 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24782.410966 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19374.871052 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 19374.871052 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19374.871052 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 19374.871052 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 2324237 # number of writebacks +system.cpu.dcache.writebacks::total 2324237 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1728834 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1728834 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 791147 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 791147 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2519981 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2519981 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2519981 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2519981 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 29207812500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 29207812500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 19605211500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 19605211500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 48813024000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 48813024000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 48813024000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 48813024000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.004501 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.004501 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005304 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005304 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.004725 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.004725 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.004725 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.004725 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16894.515321 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16894.515321 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24780.744286 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24780.744286 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19370.393666 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 19370.393666 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19370.393666 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 19370.393666 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 1253 # number of replacements -system.cpu.icache.tags.tagsinuse 881.361122 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1068344251 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 881.377882 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1068379901 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 2814 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 379653.251955 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 379665.920753 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 881.361122 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.430352 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.430352 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 881.377882 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.430360 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.430360 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1561 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id @@ -224,44 +224,44 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2 7 system.cpu.icache.tags.age_task_id_blocks_1024::3 8 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1507 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.762207 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 2136696944 # Number of tag accesses -system.cpu.icache.tags.data_accesses 2136696944 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 1068344251 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1068344251 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1068344251 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1068344251 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1068344251 # number of overall hits -system.cpu.icache.overall_hits::total 1068344251 # number of overall hits +system.cpu.icache.tags.tag_accesses 2136768244 # Number of tag accesses +system.cpu.icache.tags.data_accesses 2136768244 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 1068379901 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1068379901 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1068379901 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1068379901 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1068379901 # number of overall hits +system.cpu.icache.overall_hits::total 1068379901 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 2814 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 2814 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 2814 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 2814 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 2814 # number of overall misses system.cpu.icache.overall_misses::total 2814 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 125252000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 125252000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 125252000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 125252000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 125252000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 125252000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1068347065 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1068347065 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1068347065 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1068347065 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1068347065 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1068347065 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 125256000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 125256000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 125256000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 125256000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 125256000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 125256000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1068382715 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1068382715 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1068382715 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1068382715 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1068382715 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1068382715 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000003 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000003 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000003 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000003 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000003 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000003 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 44510.305615 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 44510.305615 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 44510.305615 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 44510.305615 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 44510.305615 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 44510.305615 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 44511.727079 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 44511.727079 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 44511.727079 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 44511.727079 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 44511.727079 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 44511.727079 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -278,126 +278,126 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 2814 system.cpu.icache.demand_mshr_misses::total 2814 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 2814 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 2814 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 122438000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 122438000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 122438000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 122438000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 122438000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 122438000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 122442000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 122442000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 122442000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 122442000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 122442000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 122442000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000003 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000003 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000003 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 43510.305615 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 43510.305615 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 43510.305615 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 43510.305615 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 43510.305615 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 43510.305615 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 43511.727079 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 43511.727079 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 43511.727079 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 43511.727079 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 43511.727079 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 43511.727079 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 348438 # number of replacements -system.cpu.l2cache.tags.tagsinuse 29288.473875 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3847001 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 380798 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 10.102472 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 348437 # number of replacements +system.cpu.l2cache.tags.tagsinuse 29288.556947 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 3849932 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 380797 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 10.110195 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 756996028500 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 20940.344841 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 131.252047 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 8216.876987 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.639049 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004005 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.250759 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.893813 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 20940.547795 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 131.260188 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 8216.748964 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.639055 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004006 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.250755 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.893816 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 32360 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 79 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 8220 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 24060 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 8218 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 24062 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.987549 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 41466938 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 41466938 # Number of data accesses -system.cpu.l2cache.WritebackDirty_hits::writebacks 2323200 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 2323200 # number of WritebackDirty hits +system.cpu.l2cache.tags.tag_accesses 41491408 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 41491408 # Number of data accesses +system.cpu.l2cache.WritebackDirty_hits::writebacks 2324237 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 2324237 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 1253 # number of WritebackClean hits system.cpu.l2cache.WritebackClean_hits::total 1253 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 584688 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 584688 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 584791 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 584791 # number of ReadExReq hits system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1005 # number of ReadCleanReq hits system.cpu.l2cache.ReadCleanReq_hits::total 1005 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1554724 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 1554724 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1556145 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 1556145 # number of ReadSharedReq hits system.cpu.l2cache.demand_hits::cpu.inst 1005 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 2139412 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2140417 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 2140936 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2141941 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 1005 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 2139412 # number of overall hits -system.cpu.l2cache.overall_hits::total 2140417 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 2140936 # number of overall hits +system.cpu.l2cache.overall_hits::total 2141941 # number of overall hits system.cpu.l2cache.ReadExReq_misses::cpu.data 206356 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 206356 # number of ReadExReq misses system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 1809 # number of ReadCleanReq misses system.cpu.l2cache.ReadCleanReq_misses::total 1809 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 172690 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 172690 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 172689 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 172689 # number of ReadSharedReq misses system.cpu.l2cache.demand_misses::cpu.inst 1809 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 379046 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 380855 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 379045 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 380854 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 1809 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 379046 # number of overall misses -system.cpu.l2cache.overall_misses::total 380855 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 12278187500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 12278187500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 107652500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 107652500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 10275095500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 10275095500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 107652500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 22553283000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 22660935500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 107652500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 22553283000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 22660935500 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 2323200 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 2323200 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.overall_misses::cpu.data 379045 # number of overall misses +system.cpu.l2cache.overall_misses::total 380854 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 12278185500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 12278185500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 107657000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 107657000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 10275036000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 10275036000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 107657000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 22553221500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 22660878500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 107657000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 22553221500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 22660878500 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 2324237 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 2324237 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::writebacks 1253 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::total 1253 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 791044 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 791044 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 791147 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 791147 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 2814 # number of ReadCleanReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::total 2814 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1727414 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 1727414 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1728834 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 1728834 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 2814 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 2518458 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2521272 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 2519981 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2522795 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 2814 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 2518458 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2521272 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.260865 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.260865 # miss rate for ReadExReq accesses +system.cpu.l2cache.overall_accesses::cpu.data 2519981 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2522795 # number of overall (read+write) accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.260831 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.260831 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.642857 # miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.642857 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.099970 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.099970 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.099888 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.099888 # miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.642857 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.150507 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.151057 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.150416 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.150965 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.642857 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.150507 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.151057 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500.026653 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500.026653 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59509.397457 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59509.397457 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500.234524 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500.234524 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59509.397457 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59500.121357 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 59500.165417 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59509.397457 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500.121357 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 59500.165417 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::cpu.data 0.150416 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.150965 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500.016961 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500.016961 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59511.885019 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59511.885019 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500.234526 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500.234526 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59511.885019 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59500.116081 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 59500.171982 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59511.885019 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500.116081 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 59500.171982 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -406,125 +406,125 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 293208 # number of writebacks -system.cpu.l2cache.writebacks::total 293208 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 293207 # number of writebacks +system.cpu.l2cache.writebacks::total 293207 # number of writebacks system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 6 # number of CleanEvict MSHR misses system.cpu.l2cache.CleanEvict_mshr_misses::total 6 # number of CleanEvict MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206356 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 206356 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1809 # number of ReadCleanReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1809 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 172690 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 172690 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 172689 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 172689 # number of ReadSharedReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 1809 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 379046 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 380855 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 379045 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 380854 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 1809 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 379046 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 380855 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10214627500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10214627500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 89562500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 89562500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 8548195500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 8548195500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 89562500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 18762823000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 18852385500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 89562500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 18762823000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 18852385500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::cpu.data 379045 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 380854 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10214625500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10214625500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 89567000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 89567000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 8548146000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 8548146000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 89567000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 18762771500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 18852338500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 89567000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 18762771500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 18852338500 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.260865 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.260865 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.260831 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.260831 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.642857 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.642857 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.099970 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.099970 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.099888 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.099888 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.642857 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.150507 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.151057 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.150416 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.150965 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.642857 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.150507 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.151057 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500.026653 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500.026653 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49509.397457 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49509.397457 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500.234524 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500.234524 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49509.397457 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500.121357 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49500.165417 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49509.397457 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500.121357 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49500.165417 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.150416 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.150965 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500.016961 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500.016961 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49511.885019 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49511.885019 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500.234526 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500.234526 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49511.885019 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500.116081 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49500.171982 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49511.885019 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500.116081 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49500.171982 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 5036887 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2515615 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 5039933 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2517138 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 1729 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1729 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadResp 1730228 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 2616408 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 1731648 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 2617444 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 1253 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 246392 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 791044 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 791044 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 246878 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 791147 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 791147 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 2814 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1727414 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1728834 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 6881 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7551278 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7558159 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7555847 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7562728 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 260288 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 309866112 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 310126400 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 348438 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 2869710 # Request fanout histogram +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 310029952 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 310290240 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 348437 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 2871232 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 0.000602 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.024538 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.024532 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 2867981 99.94% 99.94% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 2869503 99.94% 99.94% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 1729 0.06% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 2869710 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4842896500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 2871232 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4845456500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 4221000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3777687000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3779971500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.trans_dist::ReadResp 174499 # Transaction distribution -system.membus.trans_dist::WritebackDirty 293207 # Transaction distribution +system.membus.trans_dist::ReadResp 174498 # Transaction distribution +system.membus.trans_dist::WritebackDirty 293206 # Transaction distribution system.membus.trans_dist::CleanEvict 53507 # Transaction distribution system.membus.trans_dist::ReadExReq 206356 # Transaction distribution system.membus.trans_dist::ReadExResp 206356 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 174499 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1108424 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1108424 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1108424 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43139968 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43139968 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 43139968 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 174498 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1108421 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1108421 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1108421 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43139840 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43139840 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 43139840 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 727569 # Request fanout histogram +system.membus.snoop_fanout::samples 727567 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 727569 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 727567 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 727569 # Request fanout histogram -system.membus.reqLayer0.occupancy 1900428500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 727567 # Request fanout histogram +system.membus.reqLayer0.occupancy 1900421500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 1904275000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1904270000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini b/tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini index 892e458ed..2a5bb3732 100644 --- a/tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini @@ -15,6 +15,7 @@ boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain eventq_index=0 +exit_on_work_items=false init_param=0 kernel= kernel_addr_check=true @@ -24,6 +25,7 @@ mem_mode=timing mem_ranges= memories=system.physmem mmap_using_noreserve=false +multi_thread=false num_work_ids=16 readfile= symbolfile= @@ -85,9 +87,9 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +clusivity=mostly_incl demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=2 is_read_only=false max_miss_count=0 @@ -101,6 +103,7 @@ system=system tags=system.cpu.dcache.tags tgts_per_mshr=20 write_buffers=8 +writeback_clean=false cpu_side=system.cpu.dcache_port mem_side=system.cpu.toL2Bus.slave[1] @@ -161,9 +164,9 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +clusivity=mostly_incl demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=2 is_read_only=true max_miss_count=0 @@ -177,6 +180,7 @@ system=system tags=system.cpu.icache.tags tgts_per_mshr=20 write_buffers=8 +writeback_clean=true cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.slave[0] @@ -196,6 +200,7 @@ eventq_index=0 [system.cpu.isa] type=ArmISA +decoderFlavour=Generic eventq_index=0 fpsid=1090793632 id_aa64afr0_el1=0 @@ -271,9 +276,9 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +clusivity=mostly_incl demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=20 is_read_only=false max_miss_count=0 @@ -287,6 +292,7 @@ system=system tags=system.cpu.l2cache.tags tgts_per_mshr=12 write_buffers=8 +writeback_clean=false cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] @@ -302,12 +308,14 @@ size=2097152 [system.cpu.toL2Bus] type=CoherentXBar +children=snoop_filter clk_domain=system.cpu_clk_domain eventq_index=0 forward_latency=0 frontend_latency=1 +point_of_coherency=false response_latency=1 -snoop_filter=Null +snoop_filter=system.cpu.toL2Bus.snoop_filter snoop_response_latency=1 system=system use_default_range=false @@ -315,6 +323,13 @@ width=32 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port +[system.cpu.toL2Bus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=0 +max_capacity=8388608 +system=system + [system.cpu.tracer] type=ExeTracer eventq_index=0 @@ -329,7 +344,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/eon +executable=/dist/m5/cpu2000/binaries/arm/linux/eon gid=100 input=cin kvmInSE=false @@ -364,6 +379,7 @@ clk_domain=system.clk_domain eventq_index=0 forward_latency=4 frontend_latency=3 +point_of_coherency=true response_latency=2 snoop_filter=Null snoop_response_latency=4 diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-timing/simerr b/tests/long/se/30.eon/ref/arm/linux/simple-timing/simerr index a25196116..7e050de51 100755 --- a/tests/long/se/30.eon/ref/arm/linux/simple-timing/simerr +++ b/tests/long/se/30.eon/ref/arm/linux/simple-timing/simerr @@ -1,4 +1,3 @@ -warn: Sockets disabled, not accepting gdb connections getting pixel output filename pixels_out.cook opening control file chair.control.cook opening camera file chair.camera diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-timing/simout b/tests/long/se/30.eon/ref/arm/linux/simple-timing/simout index d5cd58d2c..7ed803ee9 100755 --- a/tests/long/se/30.eon/ref/arm/linux/simple-timing/simout +++ b/tests/long/se/30.eon/ref/arm/linux/simple-timing/simout @@ -3,10 +3,10 @@ Redirecting stderr to build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-timing gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 14 2015 23:29:19 -gem5 started Sep 15 2015 03:56:42 -gem5 executing on ribera.cs.wisc.edu -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-timing -re /scratch/nilay/GEM5/gem5/tests/run.py build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-timing +gem5 compiled Mar 16 2016 15:51:04 +gem5 started Mar 16 2016 17:19:39 +gem5 executing on dinar2c11, pid 17050 +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-timing -re /home/stever/gem5-public/tests/run.py build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -16,4 +16,4 @@ info: Increasing stack size by one page. info: Increasing stack size by one page. info: Increasing stack size by one page. OO-style eon Time= 0.510000 -Exiting @ tick 517235407500 because target called exit() +Exiting @ tick 517287152500 because target called exit() diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt index 42b8a5c86..7d459034e 100644 --- a/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt @@ -1,34 +1,34 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.517291 # Number of seconds simulated -sim_ticks 517291025500 # Number of ticks simulated -final_tick 517291025500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.517287 # Number of seconds simulated +sim_ticks 517287152500 # Number of ticks simulated +final_tick 517287152500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 634406 # Simulator instruction rate (inst/s) -host_op_rate 761628 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1203245454 # Simulator tick rate (ticks/s) -host_mem_usage 324572 # Number of bytes of host memory used -host_seconds 429.91 # Real time elapsed on the host -sim_insts 272739286 # Number of instructions simulated -sim_ops 327433744 # Number of ops (including micro ops) simulated +host_inst_rate 131506 # Simulator instruction rate (inst/s) +host_op_rate 157879 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 249419657 # Simulator tick rate (ticks/s) +host_mem_usage 307088 # Number of bytes of host memory used +host_seconds 2073.96 # Real time elapsed on the host +sim_insts 272737951 # Number of instructions simulated +sim_ops 327435116 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 166912 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 270336 # Number of bytes read from this memory -system.physmem.bytes_read::total 437248 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 166912 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 166912 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 2608 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 4224 # Number of read requests responded to by this memory -system.physmem.num_reads::total 6832 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 322666 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 522599 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 845265 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 322666 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 322666 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 322666 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 522599 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 845265 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 166976 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 269696 # Number of bytes read from this memory +system.physmem.bytes_read::total 436672 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 166976 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 166976 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 2609 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 4214 # Number of read requests responded to by this memory +system.physmem.num_reads::total 6823 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 322792 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 521366 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 844158 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 322792 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 322792 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 322792 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 521366 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 844158 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -147,33 +147,33 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 191 # Number of system calls -system.cpu.numCycles 1034582051 # number of cpu cycles simulated +system.cpu.numCycles 1034574305 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 272739286 # Number of instructions committed -system.cpu.committedOps 327433744 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 258331537 # Number of integer alu accesses +system.cpu.committedInsts 272737951 # Number of instructions committed +system.cpu.committedOps 327435116 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 258332236 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 114216705 # Number of float alu accesses -system.cpu.num_func_calls 12448615 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 15799349 # number of instructions that are conditional controls -system.cpu.num_int_insts 258331537 # number of integer instructions +system.cpu.num_func_calls 12449970 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 15800021 # number of instructions that are conditional controls +system.cpu.num_int_insts 258332236 # number of integer instructions system.cpu.num_fp_insts 114216705 # number of float instructions -system.cpu.num_int_register_reads 1215888421 # number of times the integer registers were read -system.cpu.num_int_register_writes 162499693 # number of times the integer registers were written +system.cpu.num_int_register_reads 1215886434 # number of times the integer registers were read +system.cpu.num_int_register_writes 162499715 # number of times the integer registers were written system.cpu.num_fp_register_reads 180262959 # number of times the floating registers were read system.cpu.num_fp_register_writes 126152315 # number of times the floating registers were written -system.cpu.num_cc_register_reads 1242915503 # number of times the CC registers were read -system.cpu.num_cc_register_writes 76361814 # number of times the CC registers were written -system.cpu.num_mem_refs 168107847 # number of memory refs -system.cpu.num_load_insts 85732248 # Number of load instructions -system.cpu.num_store_insts 82375599 # Number of store instructions +system.cpu.num_cc_register_reads 1242911540 # number of times the CC registers were read +system.cpu.num_cc_register_writes 76355719 # number of times the CC registers were written +system.cpu.num_mem_refs 168105830 # number of memory refs +system.cpu.num_load_insts 85730232 # Number of load instructions +system.cpu.num_store_insts 82375598 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 1034582050.998000 # Number of busy cycles +system.cpu.num_busy_cycles 1034574304.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 30563503 # Number of branches fetched +system.cpu.Branches 30566209 # Number of branches fetched system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 104312544 31.82% 31.82% # Class of executed instruction +system.cpu.op_class::IntAlu 104315933 31.82% 31.82% # Class of executed instruction system.cpu.op_class::IntMult 2145905 0.65% 32.48% # Class of executed instruction system.cpu.op_class::IntDiv 0 0.00% 32.48% # Class of executed instruction system.cpu.op_class::FloatAdd 0 0.00% 32.48% # Class of executed instruction @@ -198,79 +198,79 @@ system.cpu.op_class::SimdFloatAlu 0 0.00% 34.49% # Cl system.cpu.op_class::SimdFloatCmp 7943502 2.42% 36.91% # Class of executed instruction system.cpu.op_class::SimdFloatCvt 3118180 0.95% 37.86% # Class of executed instruction system.cpu.op_class::SimdFloatDiv 1563217 0.48% 38.34% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 19652356 6.00% 44.33% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 19652356 5.99% 44.33% # Class of executed instruction system.cpu.op_class::SimdFloatMult 7136937 2.18% 46.51% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 7062098 2.15% 48.66% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 7062098 2.15% 48.67% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 175285 0.05% 48.72% # Class of executed instruction -system.cpu.op_class::MemRead 85732248 26.15% 74.87% # Class of executed instruction -system.cpu.op_class::MemWrite 82375599 25.13% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 85730232 26.15% 74.87% # Class of executed instruction +system.cpu.op_class::MemWrite 82375598 25.13% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 327812214 # Class of executed instruction -system.cpu.dcache.tags.replacements 1332 # number of replacements -system.cpu.dcache.tags.tagsinuse 3078.335714 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 168359617 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 4478 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 37597.056052 # Average number of references to valid blocks. +system.cpu.op_class::total 327813586 # Class of executed instruction +system.cpu.dcache.tags.replacements 1326 # number of replacements +system.cpu.dcache.tags.tagsinuse 3078.339297 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 168357609 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 4469 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 37672.322443 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3078.335714 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.751547 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.751547 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 3146 # Occupied blocks per task id +system.cpu.dcache.tags.occ_blocks::cpu.data 3078.339297 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.751548 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.751548 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 3143 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 10 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 677 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 2428 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.768066 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 336732670 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 336732670 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 86233963 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 86233963 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 82049805 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 82049805 # number of WriteReq hits +system.cpu.dcache.tags.age_task_id_blocks_1024::1 18 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 678 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 2434 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.767334 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 336728627 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 336728627 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 86231946 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 86231946 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 82049814 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 82049814 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 54059 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 54059 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 10895 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 10895 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 168283768 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 168283768 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 168337827 # number of overall hits -system.cpu.dcache.overall_hits::total 168337827 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1604 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1604 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2872 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2872 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 168281760 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 168281760 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 168335819 # number of overall hits +system.cpu.dcache.overall_hits::total 168335819 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1605 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1605 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2862 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2862 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 3 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 3 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 4476 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 4476 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 4479 # number of overall misses -system.cpu.dcache.overall_misses::total 4479 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 88052000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 88052000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 177422500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 177422500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 265474500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 265474500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 265474500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 265474500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 86235567 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 86235567 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 82052677 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 82052677 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 4467 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 4467 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 4470 # number of overall misses +system.cpu.dcache.overall_misses::total 4470 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 88066000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 88066000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 176802500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 176802500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 264868500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 264868500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 264868500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 264868500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 86233551 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 86233551 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 82052676 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 82052676 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 54062 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::total 54062 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10895 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 10895 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 168288244 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 168288244 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 168342306 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 168342306 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 168286227 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 168286227 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 168340289 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 168340289 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000019 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000019 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000035 # miss rate for WriteReq accesses @@ -281,14 +281,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000027 system.cpu.dcache.demand_miss_rate::total 0.000027 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000027 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000027 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54895.261845 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 54895.261845 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61776.636490 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 61776.636490 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 59310.656836 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 59310.656836 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 59270.931011 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 59270.931011 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54869.781931 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 54869.781931 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61775.856045 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 61775.856045 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 59294.492948 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 59294.492948 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 59254.697987 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 59254.697987 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -297,34 +297,34 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 998 # number of writebacks -system.cpu.dcache.writebacks::total 998 # number of writebacks +system.cpu.dcache.writebacks::writebacks 997 # number of writebacks +system.cpu.dcache.writebacks::total 997 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits system.cpu.dcache.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits system.cpu.dcache.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits::total 1 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1603 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1603 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2872 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 2872 # number of WriteReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1604 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1604 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2862 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 2862 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 3 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 3 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 4475 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 4475 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 4478 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 4478 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 86402000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 86402000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 174550500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 174550500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 4466 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 4466 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 4469 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 4469 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 86415000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 86415000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 173940500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 173940500 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 183000 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 183000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 260952500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 260952500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 261135500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 261135500 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 260355500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 260355500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 260538500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 260538500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000019 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000019 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses @@ -335,71 +335,71 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53900.187149 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53900.187149 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 60776.636490 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 60776.636490 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53874.688279 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53874.688279 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 60775.856045 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 60775.856045 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 61000 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 61000 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 58313.407821 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 58313.407821 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 58315.207682 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 58315.207682 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 58297.245858 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 58297.245858 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 58299.060192 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 58299.060192 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 13796 # number of replacements -system.cpu.icache.tags.tagsinuse 1765.948116 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 348644750 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 15603 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 22344.725373 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 13798 # number of replacements +system.cpu.icache.tags.tagsinuse 1765.947853 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 348643415 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 15605 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 22341.776033 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1765.948116 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 1765.947853 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.862279 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.862279 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1807 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 66 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 161 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1524 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 163 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1522 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.882324 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 697336309 # Number of tag accesses -system.cpu.icache.tags.data_accesses 697336309 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 348644750 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 348644750 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 348644750 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 348644750 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 348644750 # number of overall hits -system.cpu.icache.overall_hits::total 348644750 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 15603 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 15603 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 15603 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 15603 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 15603 # number of overall misses -system.cpu.icache.overall_misses::total 15603 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 338446000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 338446000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 338446000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 338446000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 338446000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 338446000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 348660353 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 348660353 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 348660353 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 348660353 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 348660353 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 348660353 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 697333645 # Number of tag accesses +system.cpu.icache.tags.data_accesses 697333645 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 348643415 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 348643415 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 348643415 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 348643415 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 348643415 # number of overall hits +system.cpu.icache.overall_hits::total 348643415 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 15605 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 15605 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 15605 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 15605 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 15605 # number of overall misses +system.cpu.icache.overall_misses::total 15605 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 338522000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 338522000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 338522000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 338522000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 338522000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 338522000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 348659020 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 348659020 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 348659020 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 348659020 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 348659020 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 348659020 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000045 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000045 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000045 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000045 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000045 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000045 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21691.085048 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 21691.085048 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 21691.085048 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 21691.085048 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 21691.085048 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 21691.085048 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21693.175264 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 21693.175264 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 21693.175264 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 21693.175264 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 21693.175264 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 21693.175264 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -408,42 +408,42 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks::writebacks 13796 # number of writebacks -system.cpu.icache.writebacks::total 13796 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15603 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 15603 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 15603 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 15603 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 15603 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 15603 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 322843000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 322843000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 322843000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 322843000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 322843000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 322843000 # number of overall MSHR miss cycles +system.cpu.icache.writebacks::writebacks 13798 # number of writebacks +system.cpu.icache.writebacks::total 13798 # number of writebacks +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15605 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 15605 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 15605 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 15605 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 15605 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 15605 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 322917000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 322917000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 322917000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 322917000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 322917000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 322917000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000045 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000045 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000045 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20691.085048 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20691.085048 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20691.085048 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 20691.085048 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20691.085048 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 20691.085048 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20693.175264 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20693.175264 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20693.175264 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 20693.175264 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20693.175264 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 20693.175264 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 3487.622109 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 3487.616981 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 19775 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 4882 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 4.050594 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 341.605293 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2407.328378 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 738.688437 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 341.600605 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2407.332701 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 738.683674 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.010425 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.073466 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.022543 # Average percentage of cache occupancy @@ -451,92 +451,92 @@ system.cpu.l2cache.tags.occ_percent::total 0.106434 # system.cpu.l2cache.tags.occ_task_id_blocks::1024 4882 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 35 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 46 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1232 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 25 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1233 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3543 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.148987 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 228106 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 228106 # Number of data accesses -system.cpu.l2cache.WritebackDirty_hits::writebacks 998 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 998 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 6212 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 6212 # number of WritebackClean hits +system.cpu.l2cache.tags.tag_accesses 228016 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 228016 # Number of data accesses +system.cpu.l2cache.WritebackDirty_hits::writebacks 997 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 997 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 6213 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 6213 # number of WritebackClean hits system.cpu.l2cache.ReadExReq_hits::cpu.data 16 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 16 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 12995 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 12995 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 238 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 238 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 12995 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 254 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 13249 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 12995 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 254 # number of overall hits -system.cpu.l2cache.overall_hits::total 13249 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 2856 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 2856 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2608 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 2608 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 12996 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 12996 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 239 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 239 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 12996 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 255 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 13251 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 12996 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 255 # number of overall hits +system.cpu.l2cache.overall_hits::total 13251 # number of overall hits +system.cpu.l2cache.ReadExReq_misses::cpu.data 2846 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 2846 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2609 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 2609 # number of ReadCleanReq misses system.cpu.l2cache.ReadSharedReq_misses::cpu.data 1368 # number of ReadSharedReq misses system.cpu.l2cache.ReadSharedReq_misses::total 1368 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 2608 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 4224 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 6832 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 2608 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 4224 # number of overall misses -system.cpu.l2cache.overall_misses::total 6832 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 170070500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 170070500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 155292000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 155292000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.demand_misses::cpu.inst 2609 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 4214 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 6823 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 2609 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 4214 # number of overall misses +system.cpu.l2cache.overall_misses::total 6823 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 169475500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 169475500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 155351500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 155351500 # number of ReadCleanReq miss cycles system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 81591000 # number of ReadSharedReq miss cycles system.cpu.l2cache.ReadSharedReq_miss_latency::total 81591000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 155292000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 251661500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 406953500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 155292000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 251661500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 406953500 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 998 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 998 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 6212 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 6212 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 2872 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 2872 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 15603 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 15603 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1606 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 1606 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 15603 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 4478 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 20081 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 15603 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 4478 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 20081 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.994429 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.994429 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.167147 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.167147 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.851806 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.851806 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.167147 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.943278 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.340222 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.167147 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.943278 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.340222 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59548.494398 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59548.494398 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59544.478528 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59544.478528 # average ReadCleanReq miss latency +system.cpu.l2cache.demand_miss_latency::cpu.inst 155351500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 251066500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 406418000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 155351500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 251066500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 406418000 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 997 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 997 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 6213 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 6213 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 2862 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 2862 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 15605 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 15605 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1607 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 1607 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 15605 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 4469 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 20074 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 15605 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 4469 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 20074 # number of overall (read+write) accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.994410 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.994410 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.167190 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.167190 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.851276 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.851276 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.167190 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.942940 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.339892 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.167190 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.942940 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.339892 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59548.664793 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59548.664793 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59544.461479 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59544.461479 # average ReadCleanReq miss latency system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59642.543860 # average ReadSharedReq miss latency system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59642.543860 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59544.478528 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59578.953598 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 59565.793326 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59544.478528 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59578.953598 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 59565.793326 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59544.461479 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59579.140959 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 59565.880111 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59544.461479 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59579.140959 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 59565.880111 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -545,115 +545,115 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 2856 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 2856 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2608 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2608 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 2846 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 2846 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2609 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2609 # number of ReadCleanReq MSHR misses system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1368 # number of ReadSharedReq MSHR misses system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1368 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 2608 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 4224 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 6832 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 2608 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 4224 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 6832 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 141510500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 141510500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 129212000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 129212000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2609 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 4214 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 6823 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2609 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 4214 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 6823 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 141015500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 141015500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 129261500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 129261500 # number of ReadCleanReq MSHR miss cycles system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 67911000 # number of ReadSharedReq MSHR miss cycles system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 67911000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 129212000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 209421500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 338633500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 129212000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 209421500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 338633500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994429 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994429 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.167147 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.167147 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.851806 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.851806 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.167147 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.943278 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.340222 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.167147 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.943278 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.340222 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49548.494398 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49548.494398 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49544.478528 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49544.478528 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 129261500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 208926500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 338188000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 129261500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 208926500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 338188000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994410 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994410 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.167190 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.167190 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.851276 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.851276 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.167190 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.942940 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.339892 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.167190 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.942940 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.339892 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49548.664793 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49548.664793 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49544.461479 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49544.461479 # average ReadCleanReq mshr miss latency system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49642.543860 # average ReadSharedReq mshr miss latency system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49642.543860 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49544.478528 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49578.953598 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49565.793326 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49544.478528 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49578.953598 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49565.793326 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49544.461479 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49579.140959 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49565.880111 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49544.461479 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49579.140959 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49565.880111 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 35209 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 15221 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 7665 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 35198 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 15220 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 7664 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadResp 17209 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 998 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 13796 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 334 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 2872 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 2872 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 15603 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1606 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45002 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10288 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 55290 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1881536 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 350464 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 2232000 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadResp 17212 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 997 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 13798 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 329 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 2862 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 2862 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 15605 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1607 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45008 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10264 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 55272 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1881792 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 349824 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 2231616 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 20081 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.386335 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.486921 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 20074 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.386570 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.486976 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 12323 61.37% 61.37% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 7758 38.63% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 12314 61.34% 61.34% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 7760 38.66% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 20081 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 32398500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 20074 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 32394000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 23404500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 23407500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 6717000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 6703500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.trans_dist::ReadResp 3976 # Transaction distribution -system.membus.trans_dist::ReadExReq 2856 # Transaction distribution -system.membus.trans_dist::ReadExResp 2856 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 3976 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 13664 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 13664 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 437248 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 437248 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadResp 3977 # Transaction distribution +system.membus.trans_dist::ReadExReq 2846 # Transaction distribution +system.membus.trans_dist::ReadExResp 2846 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 3977 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 13646 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 13646 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 436672 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 436672 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 6833 # Request fanout histogram +system.membus.snoop_fanout::samples 6824 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 6833 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 6824 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 6833 # Request fanout histogram -system.membus.reqLayer0.occupancy 7281500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 6824 # Request fanout histogram +system.membus.reqLayer0.occupancy 7272500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 34160000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 34115000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/config.ini b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/config.ini index 802d9b780..4b3e2746a 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/config.ini +++ b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/config.ini @@ -15,6 +15,7 @@ boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain eventq_index=0 +exit_on_work_items=false init_param=0 kernel= kernel_addr_check=true @@ -24,6 +25,7 @@ mem_mode=timing mem_ranges= memories=system.physmem mmap_using_noreserve=false +multi_thread=false num_work_ids=16 readfile= symbolfile= @@ -132,9 +134,9 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +clusivity=mostly_incl demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=2 is_read_only=false max_miss_count=0 @@ -148,6 +150,7 @@ system=system tags=system.cpu.dcache.tags tgts_per_mshr=20 write_buffers=8 +writeback_clean=false cpu_side=system.cpu.dcache_port mem_side=system.cpu.toL2Bus.slave[1] @@ -591,9 +594,9 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +clusivity=mostly_incl demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=2 is_read_only=true max_miss_count=0 @@ -607,6 +610,7 @@ system=system tags=system.cpu.icache.tags tgts_per_mshr=20 write_buffers=8 +writeback_clean=true cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.slave[0] @@ -626,6 +630,7 @@ eventq_index=0 [system.cpu.isa] type=ArmISA +decoderFlavour=Generic eventq_index=0 fpsid=1090793632 id_aa64afr0_el1=0 @@ -701,9 +706,9 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +clusivity=mostly_incl demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=20 is_read_only=false max_miss_count=0 @@ -717,6 +722,7 @@ system=system tags=system.cpu.l2cache.tags tgts_per_mshr=12 write_buffers=8 +writeback_clean=false cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] @@ -732,12 +738,14 @@ size=2097152 [system.cpu.toL2Bus] type=CoherentXBar +children=snoop_filter clk_domain=system.cpu_clk_domain eventq_index=0 forward_latency=0 frontend_latency=1 +point_of_coherency=false response_latency=1 -snoop_filter=Null +snoop_filter=system.cpu.toL2Bus.snoop_filter snoop_response_latency=1 system=system use_default_range=false @@ -745,6 +753,13 @@ width=32 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port +[system.cpu.toL2Bus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=0 +max_capacity=8388608 +system=system + [system.cpu.tracer] type=ExeTracer eventq_index=0 @@ -759,7 +774,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/vortex +executable=/dist/m5/cpu2000/binaries/arm/linux/vortex gid=100 input=cin kvmInSE=false @@ -794,6 +809,7 @@ clk_domain=system.clk_domain eventq_index=0 forward_latency=4 frontend_latency=3 +point_of_coherency=true response_latency=2 snoop_filter=Null snoop_response_latency=4 diff --git a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/simerr b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/simerr index 341b479f7..f9e2ef3b2 100755 --- a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/simerr +++ b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/simerr @@ -1,2 +1 @@ warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) -warn: Sockets disabled, not accepting gdb connections diff --git a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/simout b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/simout index f97f5968b..9ad30ac44 100755 --- a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/simout +++ b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/simout @@ -3,12 +3,12 @@ Redirecting stderr to build/ARM/tests/opt/long/se/50.vortex/arm/linux/minor-timi gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 14 2015 23:29:19 -gem5 started Sep 15 2015 03:05:45 -gem5 executing on ribera.cs.wisc.edu -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/50.vortex/arm/linux/minor-timing -re /scratch/nilay/GEM5/gem5/tests/run.py build/ARM/tests/opt/long/se/50.vortex/arm/linux/minor-timing +gem5 compiled Mar 16 2016 15:51:04 +gem5 started Mar 16 2016 16:24:45 +gem5 executing on dinar2c11, pid 15928 +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/50.vortex/arm/linux/minor-timing -re /home/stever/gem5-public/tests/run.py build/ARM/tests/opt/long/se/50.vortex/arm/linux/minor-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. -Exiting @ tick 56986224500 because target called exit() +Exiting @ tick 56966152500 because target called exit() diff --git a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt index 6fa7b21e8..357735e21 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt @@ -1,49 +1,49 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.056961 # Number of seconds simulated -sim_ticks 56960656500 # Number of ticks simulated -final_tick 56960656500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.056966 # Number of seconds simulated +sim_ticks 56966152500 # Number of ticks simulated +final_tick 56966152500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 189048 # Simulator instruction rate (inst/s) -host_op_rate 241764 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 151847358 # Simulator tick rate (ticks/s) -host_mem_usage 327812 # Number of bytes of host memory used -host_seconds 375.12 # Real time elapsed on the host -sim_insts 70915128 # Number of instructions simulated -sim_ops 90690084 # Number of ops (including micro ops) simulated +host_inst_rate 83103 # Simulator instruction rate (inst/s) +host_op_rate 106277 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 66756773 # Simulator tick rate (ticks/s) +host_mem_usage 309512 # Number of bytes of host memory used +host_seconds 853.34 # Real time elapsed on the host +sim_insts 70915150 # Number of instructions simulated +sim_ops 90690106 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 285184 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 7924608 # Number of bytes read from this memory -system.physmem.bytes_read::total 8209792 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 7924672 # Number of bytes read from this memory +system.physmem.bytes_read::total 8209856 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 285184 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 285184 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 5517504 # Number of bytes written to this memory system.physmem.bytes_written::total 5517504 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 4456 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 123822 # Number of read requests responded to by this memory -system.physmem.num_reads::total 128278 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 123823 # Number of read requests responded to by this memory +system.physmem.num_reads::total 128279 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 86211 # Number of write requests responded to by this memory system.physmem.num_writes::total 86211 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 5006684 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 139124239 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 144130923 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 5006684 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 5006684 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 96865176 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 96865176 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 96865176 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 5006684 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 139124239 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 240996099 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 128278 # Number of read requests accepted +system.physmem.bw_read::cpu.inst 5006201 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 139111940 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 144118141 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 5006201 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 5006201 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 96855830 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 96855830 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 96855830 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 5006201 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 139111940 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 240973971 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 128279 # Number of read requests accepted system.physmem.writeReqs 86211 # Number of write requests accepted -system.physmem.readBursts 128278 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 128279 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 86211 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 8209408 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 8209472 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 384 # Total number of bytes read from write queue -system.physmem.bytesWritten 5515712 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 8209792 # Total read bytes from the system interface side +system.physmem.bytesWritten 5515584 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 8209856 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 5517504 # Total written bytes from the system interface side system.physmem.servicedByWrQ 6 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one @@ -53,11 +53,11 @@ system.physmem.perBankRdBursts::1 8314 # Pe system.physmem.perBankRdBursts::2 8233 # Per bank write bursts system.physmem.perBankRdBursts::3 8140 # Per bank write bursts system.physmem.perBankRdBursts::4 8284 # Per bank write bursts -system.physmem.perBankRdBursts::5 8402 # Per bank write bursts -system.physmem.perBankRdBursts::6 8056 # Per bank write bursts +system.physmem.perBankRdBursts::5 8403 # Per bank write bursts +system.physmem.perBankRdBursts::6 8055 # Per bank write bursts system.physmem.perBankRdBursts::7 7915 # Per bank write bursts system.physmem.perBankRdBursts::8 8035 # Per bank write bursts -system.physmem.perBankRdBursts::9 7586 # Per bank write bursts +system.physmem.perBankRdBursts::9 7587 # Per bank write bursts system.physmem.perBankRdBursts::10 7763 # Per bank write bursts system.physmem.perBankRdBursts::11 7815 # Per bank write bursts system.physmem.perBankRdBursts::12 7871 # Per bank write bursts @@ -66,12 +66,12 @@ system.physmem.perBankRdBursts::14 7968 # Pe system.physmem.perBankRdBursts::15 7962 # Per bank write bursts system.physmem.perBankWrBursts::0 5394 # Per bank write bursts system.physmem.perBankWrBursts::1 5541 # Per bank write bursts -system.physmem.perBankWrBursts::2 5465 # Per bank write bursts +system.physmem.perBankWrBursts::2 5468 # Per bank write bursts system.physmem.perBankWrBursts::3 5335 # Per bank write bursts -system.physmem.perBankWrBursts::4 5367 # Per bank write bursts -system.physmem.perBankWrBursts::5 5560 # Per bank write bursts -system.physmem.perBankWrBursts::6 5259 # Per bank write bursts -system.physmem.perBankWrBursts::7 5181 # Per bank write bursts +system.physmem.perBankWrBursts::4 5366 # Per bank write bursts +system.physmem.perBankWrBursts::5 5559 # Per bank write bursts +system.physmem.perBankWrBursts::6 5257 # Per bank write bursts +system.physmem.perBankWrBursts::7 5180 # Per bank write bursts system.physmem.perBankWrBursts::8 5155 # Per bank write bursts system.physmem.perBankWrBursts::9 5101 # Per bank write bursts system.physmem.perBankWrBursts::10 5292 # Per bank write bursts @@ -82,14 +82,14 @@ system.physmem.perBankWrBursts::14 5703 # Pe system.physmem.perBankWrBursts::15 5432 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 56960624500 # Total gap between requests +system.physmem.totGap 56966120500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 128278 # Read request sizes (log2) +system.physmem.readPktSize::6 128279 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -97,9 +97,9 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 86211 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 116041 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 12210 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 21 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 116084 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 12167 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 22 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -144,27 +144,27 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 661 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 668 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4041 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5199 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5287 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5309 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5322 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 648 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 663 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4078 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5185 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5288 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5314 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5318 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 5319 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5319 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 5327 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5345 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5368 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5453 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 5411 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 5463 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5922 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5462 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5323 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 5324 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5352 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5373 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5466 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 5451 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 5471 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5868 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5446 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 5300 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 8 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see @@ -193,98 +193,101 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 38843 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 353.305769 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 214.370646 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 335.820424 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 12327 31.74% 31.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 8308 21.39% 53.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4009 10.32% 63.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2908 7.49% 70.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2579 6.64% 77.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1645 4.23% 81.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1295 3.33% 85.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1183 3.05% 88.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 4589 11.81% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 38843 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5293 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 24.231438 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 352.038332 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 5291 99.96% 99.96% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 38803 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 353.679870 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 214.740030 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 335.847890 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 12299 31.70% 31.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 8268 21.31% 53.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4108 10.59% 63.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2801 7.22% 70.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2598 6.70% 77.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1655 4.27% 81.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1337 3.45% 85.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1145 2.95% 88.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 4592 11.83% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 38803 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5292 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 24.235639 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 352.487123 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 5289 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::24576-25599 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5293 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5293 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.282449 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.265601 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.771117 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 4623 87.34% 87.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 6 0.11% 87.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 534 10.09% 97.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 111 2.10% 99.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 13 0.25% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 2 0.04% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 2 0.04% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 2 0.04% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5293 # Writes before turning the bus around for reads -system.physmem.totQLat 1678352000 # Total ticks spent queuing -system.physmem.totMemAccLat 4083452000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 641360000 # Total ticks spent in databus transfers -system.physmem.avgQLat 13084.32 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5292 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5292 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.285147 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.266957 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.809216 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 4635 87.59% 87.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 6 0.11% 87.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 507 9.58% 97.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 117 2.21% 99.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 17 0.32% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 4 0.08% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 3 0.06% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 1 0.02% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5292 # Writes before turning the bus around for reads +system.physmem.totQLat 1670425750 # Total ticks spent queuing +system.physmem.totMemAccLat 4075544500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 641365000 # Total ticks spent in databus transfers +system.physmem.avgQLat 13022.43 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 31834.32 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 144.12 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 96.83 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 144.13 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 96.87 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 31772.43 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 144.11 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 96.82 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 144.12 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 96.86 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 1.88 # Data bus utilization in percentage system.physmem.busUtilRead 1.13 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.76 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing -system.physmem.avgWrQLen 23.44 # Average write queue length when enqueuing -system.physmem.readRowHits 111810 # Number of row buffer hits during reads -system.physmem.writeRowHits 63793 # Number of row buffer hits during writes -system.physmem.readRowHitRate 87.17 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 74.00 # Row buffer hit rate for writes -system.physmem.avgGap 265564.32 # Average gap between requests -system.physmem.pageHitRate 81.87 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 153158040 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 83568375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 509862600 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 279223200 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3720116400 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 11565367830 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 24028947750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 40340244195 # Total energy per rank (pJ) -system.physmem_0.averagePower 708.261877 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 39847901500 # Time in different power states -system.physmem_0.memoryStateTime::REF 1901900000 # Time in different power states +system.physmem.avgWrQLen 23.35 # Average write queue length when enqueuing +system.physmem.readRowHits 111858 # Number of row buffer hits during reads +system.physmem.writeRowHits 63787 # Number of row buffer hits during writes +system.physmem.readRowHitRate 87.20 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 73.99 # Row buffer hit rate for writes +system.physmem.avgGap 265588.70 # Average gap between requests +system.physmem.pageHitRate 81.89 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 152953920 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 83457000 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 510065400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 279210240 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3720624960 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 11616680655 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 23988608250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 40351600425 # Total energy per rank (pJ) +system.physmem_0.averagePower 708.364424 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 39782190750 # Time in different power states +system.physmem_0.memoryStateTime::REF 1902160000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 15206891000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 15280128000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 140419440 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 76617750 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 490214400 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 140358960 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 76584750 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 490315800 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 279138960 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3720116400 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 10938128715 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 24579157500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 40223793165 # Total energy per rank (pJ) -system.physmem_1.averagePower 706.217322 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 40763292250 # Time in different power states -system.physmem_1.memoryStateTime::REF 1901900000 # Time in different power states +system.physmem_1.refreshEnergy 3720624960 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 10974085740 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 24552288000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 40233397170 # Total energy per rank (pJ) +system.physmem_1.averagePower 706.289389 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 40717988750 # Time in different power states +system.physmem_1.memoryStateTime::REF 1902160000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 14291603250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 14344414250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 14800638 # Number of BP lookups -system.cpu.branchPred.condPredicted 9905777 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 381686 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9438449 # Number of BTB lookups -system.cpu.branchPred.BTBHits 6732187 # Number of BTB hits +system.cpu.branchPred.lookups 14806373 # Number of BP lookups +system.cpu.branchPred.condPredicted 9910083 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 383814 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9538678 # Number of BTB lookups +system.cpu.branchPred.BTBHits 6734058 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 71.327259 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1714133 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 70.597393 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1715002 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 3 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested @@ -404,97 +407,97 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 113921313 # number of cpu cycles simulated +system.cpu.numCycles 113932305 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 70915128 # Number of instructions committed -system.cpu.committedOps 90690084 # Number of ops (including micro ops) committed -system.cpu.discardedOps 1144928 # Number of ops (including micro ops) which were discarded before commit +system.cpu.committedInsts 70915150 # Number of instructions committed +system.cpu.committedOps 90690106 # Number of ops (including micro ops) committed +system.cpu.discardedOps 1148486 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.606446 # CPI: cycles per instruction -system.cpu.ipc 0.622492 # IPC: instructions per cycle -system.cpu.tickCycles 95595424 # Number of cycles that the object actually ticked -system.cpu.idleCycles 18325889 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 156436 # number of replacements -system.cpu.dcache.tags.tagsinuse 4067.127430 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 42624259 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 160532 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 265.518769 # Average number of references to valid blocks. +system.cpu.cpi 1.606600 # CPI: cycles per instruction +system.cpu.ipc 0.622432 # IPC: instructions per cycle +system.cpu.tickCycles 95622082 # Number of cycles that the object actually ticked +system.cpu.idleCycles 18310223 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 156441 # number of replacements +system.cpu.dcache.tags.tagsinuse 4067.130215 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 42625643 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 160537 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 265.519120 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 822760500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4067.127430 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.992951 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.992951 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 4067.130215 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.992952 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.992952 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 1105 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 2947 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 1097 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2955 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 86016734 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 86016734 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 22866824 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 22866824 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 19642179 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 19642179 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 83418 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 83418 # number of SoftPFReq hits +system.cpu.dcache.tags.tag_accesses 86019473 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 86019473 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 22868200 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 22868200 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 19642188 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 19642188 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 83417 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 83417 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 15919 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 15919 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 42509003 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 42509003 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 42592421 # number of overall hits -system.cpu.dcache.overall_hits::total 42592421 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 51533 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 51533 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 207722 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 207722 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 44587 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 44587 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 259255 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 259255 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 303842 # number of overall misses -system.cpu.dcache.overall_misses::total 303842 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 1489955500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 1489955500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 16807631000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 16807631000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 18297586500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 18297586500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 18297586500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 18297586500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 22918357 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 22918357 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 42510388 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 42510388 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 42593805 # number of overall hits +system.cpu.dcache.overall_hits::total 42593805 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 51522 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 51522 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 207713 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 207713 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 44590 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 44590 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 259235 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 259235 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 303825 # number of overall misses +system.cpu.dcache.overall_misses::total 303825 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 1488627000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 1488627000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 16793358000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 16793358000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 18281985000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 18281985000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 18281985000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 18281985000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 22919722 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 22919722 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 128005 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 128005 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 128007 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 128007 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15919 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 15919 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 42768258 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 42768258 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 42896263 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 42896263 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002249 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.002249 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010465 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.010465 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.348322 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.348322 # miss rate for SoftPFReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.006062 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.006062 # miss rate for demand accesses +system.cpu.dcache.demand_accesses::cpu.data 42769623 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 42769623 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 42897630 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 42897630 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002248 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.002248 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010464 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.010464 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.348340 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.348340 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.006061 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.006061 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.007083 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.007083 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28912.648206 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 28912.648206 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 80914.063027 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 80914.063027 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 70577.564560 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 70577.564560 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 60220.728207 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 60220.728207 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28893.035985 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 28893.035985 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 80848.853948 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 80848.853948 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 70522.826779 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 70522.826779 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 60172.747470 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 60172.747470 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -503,110 +506,110 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 128377 # number of writebacks -system.cpu.dcache.writebacks::total 128377 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 22014 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 22014 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 100694 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 100694 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 122708 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 122708 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 122708 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 122708 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 29519 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 29519 # number of ReadReq MSHR misses +system.cpu.dcache.writebacks::writebacks 128384 # number of writebacks +system.cpu.dcache.writebacks::total 128384 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 22002 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 22002 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 100685 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 100685 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 122687 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 122687 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 122687 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 122687 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 29520 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 29520 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107028 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 107028 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 23985 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 23985 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 136547 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 136547 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 160532 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 160532 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 577658500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 577658500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8488450500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8488450500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1712416500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1712416500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9066109000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 9066109000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10778525500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10778525500 # number of overall MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 23989 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 23989 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 136548 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 136548 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 160537 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 160537 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 575604000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 575604000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8480832000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8480832000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1713530500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1713530500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9056436000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9056436000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10769966500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10769966500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001288 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001288 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005392 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005392 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.187375 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.187375 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.187404 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.187404 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003193 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.003193 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003742 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.003742 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19569.040279 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19569.040279 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79310.558919 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79310.558919 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 71395.309568 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 71395.309568 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66395.519491 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 66395.519491 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67142.535445 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 67142.535445 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19498.780488 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19498.780488 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79239.376612 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79239.376612 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 71429.842845 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 71429.842845 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66324.193690 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 66324.193690 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67087.129447 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 67087.129447 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 42868 # number of replacements -system.cpu.icache.tags.tagsinuse 1852.481887 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 24941232 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 44910 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 555.360321 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 42871 # number of replacements +system.cpu.icache.tags.tagsinuse 1852.494475 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 24951243 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 44913 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 555.546123 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1852.481887 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.904532 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.904532 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1852.494475 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.904538 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.904538 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 2042 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 79 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 41 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 918 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1004 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 76 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 44 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 917 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1005 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.997070 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 50017196 # Number of tag accesses -system.cpu.icache.tags.data_accesses 50017196 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 24941232 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 24941232 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 24941232 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 24941232 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 24941232 # number of overall hits -system.cpu.icache.overall_hits::total 24941232 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 44911 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 44911 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 44911 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 44911 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 44911 # number of overall misses -system.cpu.icache.overall_misses::total 44911 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 896725000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 896725000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 896725000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 896725000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 896725000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 896725000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 24986143 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 24986143 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 24986143 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 24986143 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 24986143 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 24986143 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 50037227 # Number of tag accesses +system.cpu.icache.tags.data_accesses 50037227 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 24951243 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 24951243 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 24951243 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 24951243 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 24951243 # number of overall hits +system.cpu.icache.overall_hits::total 24951243 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 44914 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 44914 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 44914 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 44914 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 44914 # number of overall misses +system.cpu.icache.overall_misses::total 44914 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 896931500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 896931500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 896931500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 896931500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 896931500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 896931500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 24996157 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 24996157 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 24996157 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 24996157 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 24996157 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 24996157 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001797 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.001797 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.001797 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.001797 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.001797 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.001797 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19966.711941 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 19966.711941 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 19966.711941 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 19966.711941 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 19966.711941 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 19966.711941 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19969.975954 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 19969.975954 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 19969.975954 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 19969.975954 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 19969.975954 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 19969.975954 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -615,135 +618,135 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks::writebacks 42868 # number of writebacks -system.cpu.icache.writebacks::total 42868 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 44911 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 44911 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 44911 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 44911 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 44911 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 44911 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 851815000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 851815000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 851815000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 851815000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 851815000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 851815000 # number of overall MSHR miss cycles +system.cpu.icache.writebacks::writebacks 42871 # number of writebacks +system.cpu.icache.writebacks::total 42871 # number of writebacks +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 44914 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 44914 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 44914 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 44914 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 44914 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 44914 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 852018500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 852018500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 852018500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 852018500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 852018500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 852018500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001797 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001797 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001797 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.001797 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001797 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.001797 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18966.734208 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18966.734208 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18966.734208 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 18966.734208 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18966.734208 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 18966.734208 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18969.998219 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18969.998219 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18969.998219 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 18969.998219 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18969.998219 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 18969.998219 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 96386 # number of replacements -system.cpu.l2cache.tags.tagsinuse 29871.418055 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 162162 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 127539 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 1.271470 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 96387 # number of replacements +system.cpu.l2cache.tags.tagsinuse 29871.556792 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 162176 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 127540 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 1.271570 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 26782.423909 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1431.670582 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 1657.323564 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.817335 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.043691 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.050578 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.911603 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 26781.739932 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1431.627084 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 1658.189777 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.817314 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.043690 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.050604 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.911608 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 31153 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 197 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1851 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 12724 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 15788 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 593 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 191 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1857 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 12727 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 15784 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 594 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.950714 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 3410031 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 3410031 # Number of data accesses -system.cpu.l2cache.WritebackDirty_hits::writebacks 128377 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 128377 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 39288 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 39288 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 4751 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 4751 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 40441 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 40441 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 31897 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 31897 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 40441 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 36648 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 77089 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 40441 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 36648 # number of overall hits -system.cpu.l2cache.overall_hits::total 77089 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 102277 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 102277 # number of ReadExReq misses +system.cpu.l2cache.tags.tag_accesses 3410152 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 3410152 # Number of data accesses +system.cpu.l2cache.WritebackDirty_hits::writebacks 128384 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 128384 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 39291 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 39291 # number of WritebackClean hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 4752 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 4752 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 40444 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 40444 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 31900 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 31900 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 40444 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 36652 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 77096 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 40444 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 36652 # number of overall hits +system.cpu.l2cache.overall_hits::total 77096 # number of overall hits +system.cpu.l2cache.ReadExReq_misses::cpu.data 102276 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 102276 # number of ReadExReq misses system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 4470 # number of ReadCleanReq misses system.cpu.l2cache.ReadCleanReq_misses::total 4470 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 21607 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 21607 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 21609 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 21609 # number of ReadSharedReq misses system.cpu.l2cache.demand_misses::cpu.inst 4470 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 123884 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 128354 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 123885 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 128355 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 4470 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 123884 # number of overall misses -system.cpu.l2cache.overall_misses::total 128354 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8277973500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 8277973500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 355961000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 355961000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1870485000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 1870485000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 355961000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 10148458500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 10504419500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 355961000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 10148458500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 10504419500 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 128377 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 128377 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 39288 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 39288 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.overall_misses::cpu.data 123885 # number of overall misses +system.cpu.l2cache.overall_misses::total 128355 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8270346500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 8270346500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 356128000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 356128000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1869505500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 1869505500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 356128000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 10139852000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 10495980000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 356128000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 10139852000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 10495980000 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 128384 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 128384 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 39291 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 39291 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 107028 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 107028 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 44911 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 44911 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 53504 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 53504 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 44911 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 160532 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 205443 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 44911 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 160532 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 205443 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.955610 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.955610 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.099530 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.099530 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 44914 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 44914 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 53509 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 53509 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 44914 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 160537 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 205451 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 44914 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 160537 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 205451 # number of overall (read+write) accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.955600 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.955600 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.099524 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.099524 # miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.403839 # miss rate for ReadSharedReq accesses system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.403839 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.099530 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.771709 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.624767 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.099530 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.771709 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.624767 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80936.803974 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80936.803974 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 79633.333333 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 79633.333333 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 86568.473180 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 86568.473180 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79633.333333 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81919.041200 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 81839.440142 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79633.333333 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81919.041200 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 81839.440142 # average overall miss latency +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.099524 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.771691 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.624748 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.099524 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.771691 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.624748 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80863.022605 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80863.022605 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 79670.693512 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 79670.693512 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 86515.132584 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 86515.132584 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79670.693512 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81848.908262 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 81773.051303 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79670.693512 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81848.908262 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 81773.051303 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -766,119 +769,119 @@ system.cpu.l2cache.overall_mshr_hits::cpu.data 62 system.cpu.l2cache.overall_mshr_hits::total 75 # number of overall MSHR hits system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 96 # number of CleanEvict MSHR misses system.cpu.l2cache.CleanEvict_mshr_misses::total 96 # number of CleanEvict MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102277 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 102277 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102276 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 102276 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 4457 # number of ReadCleanReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::total 4457 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 21545 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 21545 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 21547 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 21547 # number of ReadSharedReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 4457 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 123822 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 128279 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 123823 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 128280 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 4457 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 123822 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 128279 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7255203500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7255203500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 310493500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 310493500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1649955000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1649955000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 310493500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8905158500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 9215652000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 310493500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8905158500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 9215652000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::cpu.data 123823 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 128280 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7247586500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7247586500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 310540000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 310540000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1649696000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1649696000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 310540000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8897282500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 9207822500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 310540000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8897282500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 9207822500 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955610 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955610 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.099241 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.099241 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955600 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955600 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.099234 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.099234 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.402680 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.402680 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.099241 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.771323 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.624402 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.099241 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.771323 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.624402 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70936.803974 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70936.803974 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69664.236033 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69664.236033 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 76581.805523 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76581.805523 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69664.236033 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71919.032967 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71840.690994 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69664.236033 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71919.032967 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71840.690994 # average overall mshr miss latency +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.099234 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.771305 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.624382 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.099234 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.771305 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.624382 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70863.022605 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70863.022605 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69674.669060 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69674.669060 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 76562.676939 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76562.676939 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69674.669060 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71854.845223 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71779.096508 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69674.669060 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71854.845223 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71779.096508 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 404747 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 199340 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 7814 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 404763 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 199348 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 7815 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 3362 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3333 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 29 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadResp 98414 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 214588 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 42868 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 38234 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 98422 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 214595 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 42871 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 38233 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 107028 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 107028 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 44911 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 53504 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 132689 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 477500 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 610189 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5617792 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18490176 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 24107968 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 96386 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 301829 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.037243 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.189864 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadCleanReq 44914 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 53509 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 132698 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 477515 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 610213 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5618176 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18490944 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 24109120 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 96387 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 301838 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.037245 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.189869 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 290617 96.29% 96.29% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 11183 3.71% 99.99% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 290625 96.29% 96.29% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 11184 3.71% 99.99% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 29 0.01% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 301829 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 373618500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 301838 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 373636500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 67384461 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 67388961 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 240832431 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 240839931 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%) -system.membus.trans_dist::ReadResp 26001 # Transaction distribution +system.membus.trans_dist::ReadResp 26003 # Transaction distribution system.membus.trans_dist::WritebackDirty 86211 # Transaction distribution -system.membus.trans_dist::CleanEvict 6908 # Transaction distribution -system.membus.trans_dist::ReadExReq 102277 # Transaction distribution -system.membus.trans_dist::ReadExResp 102277 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 26001 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 349675 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 349675 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13727296 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 13727296 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::CleanEvict 6909 # Transaction distribution +system.membus.trans_dist::ReadExReq 102276 # Transaction distribution +system.membus.trans_dist::ReadExResp 102276 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 26003 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 349678 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 349678 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13727360 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 13727360 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 221397 # Request fanout histogram +system.membus.snoop_fanout::samples 221399 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 221397 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 221399 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 221397 # Request fanout histogram -system.membus.reqLayer0.occupancy 590585500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 221399 # Request fanout histogram +system.membus.reqLayer0.occupancy 590619000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 676907000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 676896750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout index 84fd6d051..afe952dfb 100755 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout @@ -3,12 +3,12 @@ Redirecting stderr to build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing/ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 15 2016 19:53:43 -gem5 started Mar 15 2016 20:46:50 -gem5 executing on dinar2c11, pid 11157 +gem5 compiled Mar 16 2016 15:51:04 +gem5 started Mar 16 2016 17:20:18 +gem5 executing on dinar2c11, pid 17075 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing -re /home/stever/gem5-public/tests/run.py build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. -Exiting @ tick 33784139000 because target called exit() +Exiting @ tick 33708718000 because target called exit() diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt index cb62ae8cf..7ec2ce465 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt @@ -1,118 +1,118 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.033784 # Number of seconds simulated -sim_ticks 33784139000 # Number of ticks simulated -final_tick 33784139000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.033709 # Number of seconds simulated +sim_ticks 33708718000 # Number of ticks simulated +final_tick 33708718000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 59206 # Simulator instruction rate (inst/s) -host_op_rate 75718 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 28209032 # Simulator tick rate (ticks/s) -host_mem_usage 312216 # Number of bytes of host memory used -host_seconds 1197.64 # Real time elapsed on the host -sim_insts 70907630 # Number of instructions simulated -sim_ops 90682585 # Number of ops (including micro ops) simulated +host_inst_rate 58097 # Simulator instruction rate (inst/s) +host_op_rate 74299 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 27618733 # Simulator tick rate (ticks/s) +host_mem_usage 312228 # Number of bytes of host memory used +host_seconds 1220.50 # Real time elapsed on the host +sim_insts 70907652 # Number of instructions simulated +sim_ops 90682607 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 781248 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 2836288 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 6167232 # Number of bytes read from this memory -system.physmem.bytes_read::total 9784768 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 781248 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 781248 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6226432 # Number of bytes written to this memory -system.physmem.bytes_written::total 6226432 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 12207 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 44317 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 96363 # Number of read requests responded to by this memory -system.physmem.num_reads::total 152887 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 97288 # Number of write requests responded to by this memory -system.physmem.num_writes::total 97288 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 23124698 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 83953242 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 182548148 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 289626088 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 23124698 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 23124698 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 184300449 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 184300449 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 184300449 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 23124698 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 83953242 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 182548148 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 473926537 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 152888 # Number of read requests accepted -system.physmem.writeReqs 97288 # Number of write requests accepted -system.physmem.readBursts 152888 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 97288 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 9777152 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 7680 # Total number of bytes read from write queue -system.physmem.bytesWritten 6224960 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 9784832 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6226432 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 120 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 642112 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 2851904 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 6180288 # Number of bytes read from this memory +system.physmem.bytes_read::total 9674304 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 642112 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 642112 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6216192 # Number of bytes written to this memory +system.physmem.bytes_written::total 6216192 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 10033 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 44561 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 96567 # Number of read requests responded to by this memory +system.physmem.num_reads::total 151161 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 97128 # Number of write requests responded to by this memory +system.physmem.num_writes::total 97128 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 19048841 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 84604345 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 183343905 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 286997091 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 19048841 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 19048841 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 184409030 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 184409030 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 184409030 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 19048841 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 84604345 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 183343905 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 471406121 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 151162 # Number of read requests accepted +system.physmem.writeReqs 97128 # Number of write requests accepted +system.physmem.readBursts 151162 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 97128 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 9665216 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 9152 # Total number of bytes read from write queue +system.physmem.bytesWritten 6214528 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 9674368 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6216192 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 143 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 9124 # Per bank write bursts -system.physmem.perBankRdBursts::1 9348 # Per bank write bursts -system.physmem.perBankRdBursts::2 9757 # Per bank write bursts -system.physmem.perBankRdBursts::3 12566 # Per bank write bursts -system.physmem.perBankRdBursts::4 10929 # Per bank write bursts -system.physmem.perBankRdBursts::5 10090 # Per bank write bursts -system.physmem.perBankRdBursts::6 9786 # Per bank write bursts -system.physmem.perBankRdBursts::7 8974 # Per bank write bursts -system.physmem.perBankRdBursts::8 9178 # Per bank write bursts -system.physmem.perBankRdBursts::9 9832 # Per bank write bursts -system.physmem.perBankRdBursts::10 9165 # Per bank write bursts -system.physmem.perBankRdBursts::11 8819 # Per bank write bursts -system.physmem.perBankRdBursts::12 8693 # Per bank write bursts -system.physmem.perBankRdBursts::13 8672 # Per bank write bursts -system.physmem.perBankRdBursts::14 8813 # Per bank write bursts -system.physmem.perBankRdBursts::15 9022 # Per bank write bursts -system.physmem.perBankWrBursts::0 5950 # Per bank write bursts -system.physmem.perBankWrBursts::1 6192 # Per bank write bursts -system.physmem.perBankWrBursts::2 6162 # Per bank write bursts -system.physmem.perBankWrBursts::3 6171 # Per bank write bursts -system.physmem.perBankWrBursts::4 6089 # Per bank write bursts -system.physmem.perBankWrBursts::5 6262 # Per bank write bursts -system.physmem.perBankWrBursts::6 6013 # Per bank write bursts -system.physmem.perBankWrBursts::7 5971 # Per bank write bursts -system.physmem.perBankWrBursts::8 5978 # Per bank write bursts -system.physmem.perBankWrBursts::9 6080 # Per bank write bursts -system.physmem.perBankWrBursts::10 6215 # Per bank write bursts -system.physmem.perBankWrBursts::11 5915 # Per bank write bursts -system.physmem.perBankWrBursts::12 6050 # Per bank write bursts -system.physmem.perBankWrBursts::13 6057 # Per bank write bursts -system.physmem.perBankWrBursts::14 6142 # Per bank write bursts -system.physmem.perBankWrBursts::15 6018 # Per bank write bursts +system.physmem.perBankRdBursts::0 9070 # Per bank write bursts +system.physmem.perBankRdBursts::1 9361 # Per bank write bursts +system.physmem.perBankRdBursts::2 9561 # Per bank write bursts +system.physmem.perBankRdBursts::3 11292 # Per bank write bursts +system.physmem.perBankRdBursts::4 10590 # Per bank write bursts +system.physmem.perBankRdBursts::5 10416 # Per bank write bursts +system.physmem.perBankRdBursts::6 9949 # Per bank write bursts +system.physmem.perBankRdBursts::7 8975 # Per bank write bursts +system.physmem.perBankRdBursts::8 9423 # Per bank write bursts +system.physmem.perBankRdBursts::9 9187 # Per bank write bursts +system.physmem.perBankRdBursts::10 9162 # Per bank write bursts +system.physmem.perBankRdBursts::11 8879 # Per bank write bursts +system.physmem.perBankRdBursts::12 8652 # Per bank write bursts +system.physmem.perBankRdBursts::13 8689 # Per bank write bursts +system.physmem.perBankRdBursts::14 8733 # Per bank write bursts +system.physmem.perBankRdBursts::15 9080 # Per bank write bursts +system.physmem.perBankWrBursts::0 5971 # Per bank write bursts +system.physmem.perBankWrBursts::1 6177 # Per bank write bursts +system.physmem.perBankWrBursts::2 6109 # Per bank write bursts +system.physmem.perBankWrBursts::3 6172 # Per bank write bursts +system.physmem.perBankWrBursts::4 6049 # Per bank write bursts +system.physmem.perBankWrBursts::5 6259 # Per bank write bursts +system.physmem.perBankWrBursts::6 6017 # Per bank write bursts +system.physmem.perBankWrBursts::7 5953 # Per bank write bursts +system.physmem.perBankWrBursts::8 5939 # Per bank write bursts +system.physmem.perBankWrBursts::9 6100 # Per bank write bursts +system.physmem.perBankWrBursts::10 6208 # Per bank write bursts +system.physmem.perBankWrBursts::11 5866 # Per bank write bursts +system.physmem.perBankWrBursts::12 6052 # Per bank write bursts +system.physmem.perBankWrBursts::13 6067 # Per bank write bursts +system.physmem.perBankWrBursts::14 6159 # Per bank write bursts +system.physmem.perBankWrBursts::15 6004 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 33784127500 # Total gap between requests +system.physmem.totGap 33708706500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 152888 # Read request sizes (log2) +system.physmem.readPktSize::6 151162 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 97288 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 50168 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 54297 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 13893 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 10288 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 6063 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 5243 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 4693 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 4371 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3656 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 66 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 26 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 3 # What read queue length does an incoming req see +system.physmem.writePktSize::6 97128 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 48274 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 54259 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 13865 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 10322 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 6132 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 5295 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 4724 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 4390 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3645 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 73 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 33 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 6 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see @@ -148,33 +148,33 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1235 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1284 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 1747 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 2248 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 2973 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 3847 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4816 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5412 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5903 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 6387 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 6879 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7477 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 8147 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8715 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 9142 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7742 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6712 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6230 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 224 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 84 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 39 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 19 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1199 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1243 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 1720 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 2271 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 2935 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 3759 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4746 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5409 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5932 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6426 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 6856 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7461 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 8097 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8693 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 9095 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7779 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6737 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6264 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 232 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 117 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 50 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 30 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 23 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 6 # What write queue length does an incoming req see system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see @@ -197,98 +197,103 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 95539 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 167.474225 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 105.587098 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 235.887781 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 59486 62.26% 62.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 22475 23.52% 85.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4141 4.33% 90.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 1560 1.63% 91.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 915 0.96% 92.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 855 0.89% 93.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 603 0.63% 94.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 793 0.83% 95.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 4711 4.93% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 95539 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5851 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 26.107332 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 198.473486 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 5850 99.98% 99.98% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 94915 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 167.290734 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 105.391717 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 236.347458 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 59184 62.35% 62.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 22349 23.55% 85.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4070 4.29% 90.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 1460 1.54% 91.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 942 0.99% 92.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 824 0.87% 93.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 583 0.61% 94.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 753 0.79% 95.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 4750 5.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 94915 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5848 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 25.821990 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 198.480384 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 5847 99.98% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::14848-15359 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5851 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5851 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.623654 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.576655 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.320793 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 4551 77.78% 77.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 30 0.51% 78.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 752 12.85% 91.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 225 3.85% 94.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 138 2.36% 97.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 80 1.37% 98.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 45 0.77% 99.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 22 0.38% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 8 0.14% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5851 # Writes before turning the bus around for reads -system.physmem.totQLat 6694958033 # Total ticks spent queuing -system.physmem.totMemAccLat 9559358033 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 763840000 # Total ticks spent in databus transfers -system.physmem.avgQLat 43824.35 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5848 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5848 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.604309 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.557483 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.326112 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 4590 78.49% 78.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 34 0.58% 79.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 732 12.52% 91.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 206 3.52% 95.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 140 2.39% 97.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 85 1.45% 98.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 32 0.55% 99.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 13 0.22% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 5 0.09% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 7 0.12% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 1 0.02% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 1 0.02% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5848 # Writes before turning the bus around for reads +system.physmem.totQLat 6766168330 # Total ticks spent queuing +system.physmem.totMemAccLat 9597774580 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 755095000 # Total ticks spent in databus transfers +system.physmem.avgQLat 44803.42 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 62574.35 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 289.40 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 184.26 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 289.63 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 184.30 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 63553.42 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 286.73 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 184.36 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 287.00 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 184.41 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 3.70 # Data bus utilization in percentage -system.physmem.busUtilRead 2.26 # Data bus utilization in percentage for reads +system.physmem.busUtil 3.68 # Data bus utilization in percentage +system.physmem.busUtilRead 2.24 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 1.44 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.42 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.31 # Average write queue length when enqueuing -system.physmem.readRowHits 121417 # Number of row buffer hits during reads -system.physmem.writeRowHits 33065 # Number of row buffer hits during writes -system.physmem.readRowHitRate 79.48 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 33.99 # Row buffer hit rate for writes -system.physmem.avgGap 135041.44 # Average gap between requests -system.physmem.pageHitRate 61.78 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 374855040 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 204534000 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 627829800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 316068480 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 2206133280 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 15176758725 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 6953261250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 25859440575 # Total energy per rank (pJ) -system.physmem_0.averagePower 765.592889 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 11461051997 # Time in different power states -system.physmem_0.memoryStateTime::REF 1127880000 # Time in different power states +system.physmem.avgRdQLen 1.45 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.44 # Average write queue length when enqueuing +system.physmem.readRowHits 120218 # Number of row buffer hits during reads +system.physmem.writeRowHits 32977 # Number of row buffer hits during writes +system.physmem.readRowHitRate 79.60 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 33.95 # Row buffer hit rate for writes +system.physmem.avgGap 135763.45 # Average gap between requests +system.physmem.pageHitRate 61.74 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 372428280 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 203209875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 617682000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 315563040 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 2201556240 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 14512366440 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 7494015750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 25716821625 # Total energy per rank (pJ) +system.physmem_0.averagePower 762.953400 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 12364292410 # Time in different power states +system.physmem_0.memoryStateTime::REF 1125540000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 21188094253 # Time in different power states +system.physmem_0.memoryStateTime::ACT 20217117590 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 346777200 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 189213750 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 562754400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 313787520 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 2206133280 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 13818315060 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 8144878500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 25581859710 # Total energy per rank (pJ) -system.physmem_1.averagePower 757.374848 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 13453093141 # Time in different power states -system.physmem_1.memoryStateTime::REF 1127880000 # Time in different power states +system.physmem_1.actEnergy 345038400 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 188265000 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 559977600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 313554240 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 2201556240 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 13559944320 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 8329473750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 25497809550 # Total energy per rank (pJ) +system.physmem_1.averagePower 756.455863 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 13760038430 # Time in different power states +system.physmem_1.memoryStateTime::REF 1125540000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 19196289859 # Time in different power states +system.physmem_1.memoryStateTime::ACT 18821462070 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 17214384 # Number of BP lookups -system.cpu.branchPred.condPredicted 11522342 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 650449 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9351216 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7679376 # Number of BTB hits +system.cpu.branchPred.lookups 17213709 # Number of BP lookups +system.cpu.branchPred.condPredicted 11523003 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 650148 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9341134 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7678896 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 82.121683 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1872997 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 82.205180 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1872990 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 101556 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested @@ -408,95 +413,95 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 67568279 # number of cpu cycles simulated +system.cpu.numCycles 67417437 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 5160872 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 88245051 # Number of instructions fetch has processed -system.cpu.fetch.Branches 17214384 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9552373 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 60651743 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1327287 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 6028 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.icacheStallCycles 5107349 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 88247579 # Number of instructions fetch has processed +system.cpu.fetch.Branches 17213709 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9551886 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 60722717 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1326923 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 4938 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 27 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 12780 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 22780660 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 69845 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 66495093 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.679326 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.300807 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheWaitRetryStallCycles 12869 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 22781060 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 69770 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 66511361 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.678949 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.300919 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 20690371 31.12% 31.12% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 8267529 12.43% 43.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 9212157 13.85% 57.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 28325036 42.60% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 20706181 31.13% 31.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 8267608 12.43% 43.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 9211127 13.85% 57.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 28326445 42.59% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 66495093 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.254770 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.306013 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 8713541 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 20066003 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 31587262 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 5634718 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 493569 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3182821 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 172049 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 101434518 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 3052676 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 493569 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 13478922 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 5884192 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 838725 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 32239032 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 13560653 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 99228097 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 981180 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 3845119 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 69162 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 4384146 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 5165586 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 103939784 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 457840373 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 115445962 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 66511361 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.255330 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.308973 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 8663293 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 20135580 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 31585821 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 5633203 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 493464 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3182521 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 171963 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 101430430 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 3050546 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 493464 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 13424917 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 5969682 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 834240 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 32240480 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 13548578 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 99223336 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 980873 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 3826325 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 67087 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 4382425 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 5163178 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 103933922 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 457817395 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 115439825 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 550 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 93629226 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 10310558 # Number of HB maps that are undone due to squashing +system.cpu.rename.CommittedMaps 93629369 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 10304553 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 18670 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 18667 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12730367 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 24327975 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 22005134 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1415958 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2369050 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 98190630 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 34517 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 94916965 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 695759 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 7542562 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 20296667 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 731 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 66495093 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.427428 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.151996 # Number of insts issued each cycle +system.cpu.rename.tempSerializingInsts 18666 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12721444 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 24327620 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 22002844 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1418421 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2362163 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 98185716 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 34529 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 94914966 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 694952 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 7537638 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 20282691 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 743 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 66511361 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.427049 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.152183 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 18174968 27.33% 27.33% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 17486428 26.30% 53.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 17117325 25.74% 79.37% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 11670567 17.55% 96.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 2044839 3.08% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 966 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 18195190 27.36% 27.36% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 17483152 26.29% 53.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 17116175 25.73% 79.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 11668879 17.54% 96.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 2046998 3.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 967 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 66495093 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 66511361 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 6711532 22.43% 22.43% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 41 0.00% 22.43% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 6715190 22.43% 22.43% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 42 0.00% 22.43% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 22.43% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 22.43% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 22.43% # attempts to use FU when none available @@ -524,13 +529,13 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 22.43% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 22.43% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 22.43% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 22.43% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 11180045 37.36% 59.79% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 12034310 40.21% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 11181767 37.35% 59.78% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 12039186 40.22% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 49505832 52.16% 52.16% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 89861 0.09% 52.25% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 49504183 52.16% 52.16% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 89872 0.09% 52.25% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.25% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 31 0.00% 52.25% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.25% # Type of FU issued @@ -558,94 +563,94 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 8 0.00% 52.25% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.25% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 24073706 25.36% 77.61% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 21247526 22.39% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 24074068 25.36% 77.61% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 21246803 22.39% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 94916965 # Type of FU issued -system.cpu.iq.rate 1.404756 # Inst issue rate -system.cpu.iq.fu_busy_cnt 29925928 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.315285 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 286950501 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 105779157 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 93480434 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 94914966 # Type of FU issued +system.cpu.iq.rate 1.407870 # Inst issue rate +system.cpu.iq.fu_busy_cnt 29936185 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.315400 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 286972221 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 105769455 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 93478190 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 209 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 248 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 59 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 124842774 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 124851032 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 119 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1366701 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 1366282 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1461713 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 2105 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 11942 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1449396 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1461358 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 2098 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 12063 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1447106 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 140491 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 185859 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 140885 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 185939 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 493569 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 630289 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 523749 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 98235038 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 493464 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 630348 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 519071 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 98230120 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 24327975 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 22005134 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 18597 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1652 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 519239 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 11942 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 303965 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 221737 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 525702 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 93996105 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 23765772 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 920860 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 24327620 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 22002844 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 18609 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1657 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 514382 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 12063 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 303781 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 221600 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 525381 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 93994405 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 23766194 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 920561 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 9891 # number of nop insts executed -system.cpu.iew.exec_refs 44755693 # number of memory reference insts executed -system.cpu.iew.exec_branches 14254152 # Number of branches executed -system.cpu.iew.exec_stores 20989921 # Number of stores executed -system.cpu.iew.exec_rate 1.391128 # Inst execution rate -system.cpu.iew.wb_sent 93602702 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 93480493 # cumulative count of insts written-back -system.cpu.iew.wb_producers 44980132 # num instructions producing a value -system.cpu.iew.wb_consumers 76556790 # num instructions consuming a value -system.cpu.iew.wb_rate 1.383497 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.587539 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 6559945 # The number of squashed insts skipped by commit +system.cpu.iew.exec_nop 9875 # number of nop insts executed +system.cpu.iew.exec_refs 44755394 # number of memory reference insts executed +system.cpu.iew.exec_branches 14253394 # Number of branches executed +system.cpu.iew.exec_stores 20989200 # Number of stores executed +system.cpu.iew.exec_rate 1.394215 # Inst execution rate +system.cpu.iew.wb_sent 93600457 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 93478249 # cumulative count of insts written-back +system.cpu.iew.wb_producers 44984526 # num instructions producing a value +system.cpu.iew.wb_consumers 76573166 # num instructions consuming a value +system.cpu.iew.wb_rate 1.386559 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.587471 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 6555355 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 33786 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 480375 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 65432608 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.385978 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.157554 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 480151 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 65449475 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.385621 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.157530 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 31819625 48.63% 48.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 16816004 25.70% 74.33% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4349451 6.65% 80.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 4164400 6.36% 87.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1932309 2.95% 90.29% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1260445 1.93% 92.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 747040 1.14% 93.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 580342 0.89% 94.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 3762992 5.75% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 31837500 48.64% 48.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 16816023 25.69% 74.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4347616 6.64% 80.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 4166544 6.37% 87.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1933514 2.95% 90.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1257718 1.92% 92.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 744905 1.14% 93.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 580044 0.89% 94.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 3765611 5.75% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 65432608 # Number of insts commited each cycle -system.cpu.commit.committedInsts 70913182 # Number of instructions committed -system.cpu.commit.committedOps 90688137 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 65449475 # Number of insts commited each cycle +system.cpu.commit.committedInsts 70913204 # Number of instructions committed +system.cpu.commit.committedOps 90688159 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 43422000 # Number of memory references committed system.cpu.commit.loads 22866262 # Number of loads committed system.cpu.commit.membars 15920 # Number of memory barriers committed -system.cpu.commit.branches 13741486 # Number of branches committed +system.cpu.commit.branches 13741468 # Number of branches committed system.cpu.commit.fp_insts 56 # Number of committed floating point instructions. -system.cpu.commit.int_insts 81528487 # Number of committed integer instructions. +system.cpu.commit.int_insts 81528527 # Number of committed integer instructions. system.cpu.commit.function_calls 1679850 # Number of function calls committed. system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 47186011 52.03% 52.03% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 47186033 52.03% 52.03% # Class of committed instruction system.cpu.commit.op_class_0::IntMult 80119 0.09% 52.12% # Class of committed instruction system.cpu.commit.op_class_0::IntDiv 0 0.00% 52.12% # Class of committed instruction system.cpu.commit.op_class_0::FloatAdd 0 0.00% 52.12% # Class of committed instruction @@ -678,387 +683,389 @@ system.cpu.commit.op_class_0::MemRead 22866262 25.21% 77.33% # Cl system.cpu.commit.op_class_0::MemWrite 20555738 22.67% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 90688137 # Class of committed instruction -system.cpu.commit.bw_lim_events 3762992 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 158892399 # The number of ROB reads -system.cpu.rob.rob_writes 195560325 # The number of ROB writes -system.cpu.timesIdled 28658 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 1073186 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 70907630 # Number of Instructions Simulated -system.cpu.committedOps 90682585 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.952906 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.952906 # CPI: Total CPI of All Threads -system.cpu.ipc 1.049422 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.049422 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 102292438 # number of integer regfile reads -system.cpu.int_regfile_writes 56802415 # number of integer regfile writes +system.cpu.commit.op_class_0::total 90688159 # Class of committed instruction +system.cpu.commit.bw_lim_events 3765611 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 158902079 # The number of ROB reads +system.cpu.rob.rob_writes 195550630 # The number of ROB writes +system.cpu.timesIdled 26501 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 906076 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 70907652 # Number of Instructions Simulated +system.cpu.committedOps 90682607 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 0.950778 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.950778 # CPI: Total CPI of All Threads +system.cpu.ipc 1.051770 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.051770 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 102290676 # number of integer regfile reads +system.cpu.int_regfile_writes 56801575 # number of integer regfile writes system.cpu.fp_regfile_reads 38 # number of floating regfile reads system.cpu.fp_regfile_writes 22 # number of floating regfile writes -system.cpu.cc_regfile_reads 346166780 # number of cc regfile reads -system.cpu.cc_regfile_writes 38809001 # number of cc regfile writes -system.cpu.misc_regfile_reads 44218310 # number of misc regfile reads +system.cpu.cc_regfile_reads 346161860 # number of cc regfile reads +system.cpu.cc_regfile_writes 38808202 # number of cc regfile writes +system.cpu.misc_regfile_reads 44217642 # number of misc regfile reads system.cpu.misc_regfile_writes 31840 # number of misc regfile writes -system.cpu.dcache.tags.replacements 485025 # number of replacements -system.cpu.dcache.tags.tagsinuse 510.752435 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 40412261 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 485537 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 83.232094 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 485010 # number of replacements +system.cpu.dcache.tags.tagsinuse 510.749644 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 40413326 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 485522 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 83.236858 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 153371500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 510.752435 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.997563 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.997563 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 510.749644 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.997558 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.997558 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 455 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 456 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 84614979 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 84614979 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 21489272 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 21489272 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 18831416 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 18831416 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 60267 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 60267 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 15347 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 15347 # number of LoadLockedReq hits +system.cpu.dcache.tags.tag_accesses 84616114 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 84616114 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 21490425 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 21490425 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 18831304 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 18831304 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 60283 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 60283 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 15350 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 15350 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 40320688 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 40320688 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 40380955 # number of overall hits -system.cpu.dcache.overall_hits::total 40380955 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 564863 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 564863 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1018485 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1018485 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 68573 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 68573 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 579 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 579 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1583348 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1583348 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1651921 # number of overall misses -system.cpu.dcache.overall_misses::total 1651921 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 9285321000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 9285321000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 14250906929 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 14250906929 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 5341000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 5341000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 23536227929 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 23536227929 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 23536227929 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 23536227929 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 22054135 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 22054135 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 40321729 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 40321729 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 40382012 # number of overall hits +system.cpu.dcache.overall_hits::total 40382012 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 564289 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 564289 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1018597 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1018597 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 68553 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 68553 # number of SoftPFReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 576 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 576 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1582886 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1582886 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1651439 # number of overall misses +system.cpu.dcache.overall_misses::total 1651439 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 9271463500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 9271463500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 14268416431 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 14268416431 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 5543500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 5543500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 23539879931 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 23539879931 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 23539879931 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 23539879931 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 22054714 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 22054714 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 128840 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 128840 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 128836 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 128836 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15926 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 15926 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 41904036 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 41904036 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 42032876 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 42032876 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.025613 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.025613 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.051309 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.051309 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.532234 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.532234 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.036356 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.036356 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.037785 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.037785 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.039301 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.039301 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16438.182356 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 16438.182356 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 13992.260003 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 13992.260003 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 9224.525043 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 9224.525043 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 14864.848365 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 14864.848365 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 14247.792678 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 14247.792678 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 81 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 2899485 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 41904615 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 41904615 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 42033451 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 42033451 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.025586 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.025586 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.051315 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.051315 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.532095 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.532095 # miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.036167 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.036167 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.037774 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.037774 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.039289 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.039289 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16430.345975 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 16430.345975 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 14007.911304 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 14007.911304 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 9624.131944 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 9624.131944 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 14871.494176 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 14871.494176 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 14254.162540 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 14254.162540 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 63 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 2905402 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 11 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 131229 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 7.363636 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 22.094849 # average number of cycles each access was blocked +system.cpu.dcache.blocked::no_targets 131245 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 5.727273 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 22.137240 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 485025 # number of writebacks -system.cpu.dcache.writebacks::total 485025 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 265446 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 265446 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 869952 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 869952 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 579 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 579 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1135398 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1135398 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1135398 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1135398 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 299417 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 299417 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 148533 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 148533 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 37597 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 37597 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 447950 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 447950 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 485547 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 485547 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3589129000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3589129000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2306203970 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2306203970 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1890576000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1890576000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5895332970 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 5895332970 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7785908970 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7785908970 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 485010 # number of writebacks +system.cpu.dcache.writebacks::total 485010 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 264882 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 264882 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 870061 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 870061 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 576 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 576 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1134943 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1134943 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1134943 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1134943 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 299407 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 299407 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 148536 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 148536 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 37590 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 37590 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 447943 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 447943 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 485533 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 485533 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3623952500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3623952500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2306335972 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2306335972 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1883780500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1883780500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5930288472 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 5930288472 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7814068972 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7814068972 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013576 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013576 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.007483 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.007483 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.291812 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.291812 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.291766 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.291766 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.010690 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.010690 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.011552 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.011552 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11987.058183 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11987.058183 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 15526.542721 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 15526.542721 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 50285.288720 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 50285.288720 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13160.694207 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 13160.694207 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16035.335343 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 16035.335343 # average overall mshr miss latency +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.011551 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.011551 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12103.766779 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12103.766779 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 15527.117817 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 15527.117817 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 50113.873371 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 50113.873371 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13238.935472 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 13238.935472 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16093.795833 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 16093.795833 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 323129 # number of replacements -system.cpu.icache.tags.tagsinuse 510.280955 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 22445799 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 323641 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 69.354003 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 1133816500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.280955 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.996642 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.996642 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 322968 # number of replacements +system.cpu.icache.tags.tagsinuse 510.276903 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 22446876 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 323480 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 69.391851 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 1134274500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 510.276903 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.996635 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.996635 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 88 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 59 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 23 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 335 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 58 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 21 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 338 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 7 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 45884745 # Number of tag accesses -system.cpu.icache.tags.data_accesses 45884745 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 22445799 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 22445799 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 22445799 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 22445799 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 22445799 # number of overall hits -system.cpu.icache.overall_hits::total 22445799 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 334748 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 334748 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 334748 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 334748 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 334748 # number of overall misses -system.cpu.icache.overall_misses::total 334748 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 3612917411 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 3612917411 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 3612917411 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 3612917411 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 3612917411 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 3612917411 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 22780547 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 22780547 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 22780547 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 22780547 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 22780547 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 22780547 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014694 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.014694 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.014694 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.014694 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.014694 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.014694 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 10792.946966 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 10792.946966 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 10792.946966 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 10792.946966 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 10792.946966 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 10792.946966 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 264495 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 45885393 # Number of tag accesses +system.cpu.icache.tags.data_accesses 45885393 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 22446876 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 22446876 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 22446876 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 22446876 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 22446876 # number of overall hits +system.cpu.icache.overall_hits::total 22446876 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 334075 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 334075 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 334075 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 334075 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 334075 # number of overall misses +system.cpu.icache.overall_misses::total 334075 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 3448429403 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 3448429403 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 3448429403 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 3448429403 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 3448429403 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 3448429403 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 22780951 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 22780951 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 22780951 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 22780951 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 22780951 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 22780951 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014665 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.014665 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.014665 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.014665 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.014665 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.014665 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 10322.321045 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 10322.321045 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 10322.321045 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 10322.321045 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 10322.321045 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 10322.321045 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 262312 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 50 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 16626 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 16368 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 15.908517 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 16.025904 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets 25 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks::writebacks 323129 # number of writebacks -system.cpu.icache.writebacks::total 323129 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 11096 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 11096 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 11096 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 11096 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 11096 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 11096 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 323652 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 323652 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 323652 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 323652 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 323652 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 323652 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 3313255946 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 3313255946 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 3313255946 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 3313255946 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 3313255946 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 3313255946 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.014207 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.014207 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014207 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.014207 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014207 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.014207 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 10237.093996 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 10237.093996 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 10237.093996 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 10237.093996 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 10237.093996 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 10237.093996 # average overall mshr miss latency +system.cpu.icache.writebacks::writebacks 322968 # number of writebacks +system.cpu.icache.writebacks::total 322968 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 10583 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 10583 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 10583 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 10583 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 10583 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 10583 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 323492 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 323492 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 323492 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 323492 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 323492 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 323492 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 3173672438 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 3173672438 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 3173672438 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 3173672438 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 3173672438 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 3173672438 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.014200 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.014200 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014200 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.014200 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014200 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.014200 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 9810.667460 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 9810.667460 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 9810.667460 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 9810.667460 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 9810.667460 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 9810.667460 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.prefetcher.num_hwpf_issued 821921 # number of hwpf issued -system.cpu.l2cache.prefetcher.pfIdentified 825508 # number of prefetch candidates identified -system.cpu.l2cache.prefetcher.pfBufferHit 3147 # number of redundant prefetches already in prefetch queue +system.cpu.l2cache.prefetcher.num_hwpf_issued 822850 # number of hwpf issued +system.cpu.l2cache.prefetcher.pfIdentified 826406 # number of prefetch candidates identified +system.cpu.l2cache.prefetcher.pfBufferHit 3117 # number of redundant prefetches already in prefetch queue system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu.l2cache.prefetcher.pfSpanPage 78532 # number of prefetches not generated due to page crossing -system.cpu.l2cache.tags.replacements 128137 # number of replacements -system.cpu.l2cache.tags.tagsinuse 15990.250829 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1182553 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 144496 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 8.183984 # Average number of references to valid blocks. +system.cpu.l2cache.prefetcher.pfSpanPage 78938 # number of prefetches not generated due to page crossing +system.cpu.l2cache.tags.replacements 127914 # number of replacements +system.cpu.l2cache.tags.tagsinuse 15989.309751 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1181667 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 144275 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 8.190379 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 15899.758864 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 90.491965 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.970444 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.005523 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.975967 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1022 33 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 16326 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_blocks::writebacks 15893.511070 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 95.798681 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.970063 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.005847 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.975910 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1022 28 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 16333 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1022::1 8 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::2 5 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::3 17 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::4 3 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 137 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 2752 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 12114 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 551 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 772 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1022 0.002014 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.996460 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 24991467 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 24991467 # Number of data accesses -system.cpu.l2cache.WritebackDirty_hits::writebacks 256728 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 256728 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 471596 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 471596 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 137032 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 137032 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 311398 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 311398 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 300922 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 300922 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 311398 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 437954 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 749352 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 311398 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 437954 # number of overall hits -system.cpu.l2cache.overall_hits::total 749352 # number of overall hits +system.cpu.l2cache.tags.age_task_id_blocks_1022::2 1 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::3 12 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::4 7 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 136 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 2736 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 12138 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 528 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 795 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1022 0.001709 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.996887 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 24987971 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 24987971 # Number of data accesses +system.cpu.l2cache.WritebackDirty_hits::writebacks 259400 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 259400 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 468713 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 468713 # number of WritebackClean hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 1 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 137243 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 137243 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 313417 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 313417 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 300447 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 300447 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 313417 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 437690 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 751107 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 313417 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 437690 # number of overall hits +system.cpu.l2cache.overall_hits::total 751107 # number of overall hits system.cpu.l2cache.UpgradeReq_misses::cpu.data 10 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_misses::total 10 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 11535 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 11535 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 12242 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 12242 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 36048 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 36048 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 12242 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 47583 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 59825 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 12242 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 47583 # number of overall misses -system.cpu.l2cache.overall_misses::total 59825 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1188658000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1188658000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 916670500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 916670500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 2966913000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 2966913000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 916670500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 4155571000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 5072241500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 916670500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 4155571000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 5072241500 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 256728 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 256728 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 471596 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 471596 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 10 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 10 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 148567 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 148567 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 323640 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 323640 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 336970 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 336970 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 323640 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 485537 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 809177 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 323640 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 485537 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 809177 # number of overall (read+write) accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.077642 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.077642 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.037826 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.037826 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.106977 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.106977 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.037826 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.098001 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.073933 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.037826 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.098001 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.073933 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 103047.941049 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 103047.941049 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74879.145564 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74879.145564 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 82304.510652 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 82304.510652 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74879.145564 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 87333.102158 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 84784.646887 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74879.145564 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 87333.102158 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 84784.646887 # average overall miss latency +system.cpu.l2cache.ReadExReq_misses::cpu.data 11329 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 11329 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 10064 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 10064 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 36503 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 36503 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 10064 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 47832 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 57896 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 10064 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 47832 # number of overall misses +system.cpu.l2cache.overall_misses::total 57896 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1187627500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1187627500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 761841000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 761841000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 2998033500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 2998033500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 761841000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 4185661000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 4947502000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 761841000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 4185661000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 4947502000 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 259400 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 259400 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 468713 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 468713 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 11 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 11 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 148572 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 148572 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 323481 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 323481 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 336950 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 336950 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 323481 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 485522 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 809003 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 323481 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 485522 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 809003 # number of overall (read+write) accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.909091 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.909091 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.076253 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.076253 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.031112 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.031112 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.108334 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.108334 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.031112 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.098517 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.071565 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.031112 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.098517 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.071565 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 104830.744108 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 104830.744108 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75699.622417 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75699.622417 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 82131.153604 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 82131.153604 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75699.622417 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 87507.547249 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 85454.988255 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75699.622417 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 87507.547249 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 85454.988255 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1067,155 +1074,155 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 97288 # number of writebacks -system.cpu.l2cache.writebacks::total 97288 # number of writebacks -system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 3173 # number of ReadExReq MSHR hits -system.cpu.l2cache.ReadExReq_mshr_hits::total 3173 # number of ReadExReq MSHR hits -system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 34 # number of ReadCleanReq MSHR hits -system.cpu.l2cache.ReadCleanReq_mshr_hits::total 34 # number of ReadCleanReq MSHR hits -system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 93 # number of ReadSharedReq MSHR hits -system.cpu.l2cache.ReadSharedReq_mshr_hits::total 93 # number of ReadSharedReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 34 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 3266 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 3300 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 34 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 3266 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 3300 # number of overall MSHR hits -system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 112494 # number of HardPFReq MSHR misses -system.cpu.l2cache.HardPFReq_mshr_misses::total 112494 # number of HardPFReq MSHR misses +system.cpu.l2cache.writebacks::writebacks 97128 # number of writebacks +system.cpu.l2cache.writebacks::total 97128 # number of writebacks +system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 3171 # number of ReadExReq MSHR hits +system.cpu.l2cache.ReadExReq_mshr_hits::total 3171 # number of ReadExReq MSHR hits +system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 30 # number of ReadCleanReq MSHR hits +system.cpu.l2cache.ReadCleanReq_mshr_hits::total 30 # number of ReadCleanReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 100 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::total 100 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 30 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 3271 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 3301 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 30 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 3271 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 3301 # number of overall MSHR hits +system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 112673 # number of HardPFReq MSHR misses +system.cpu.l2cache.HardPFReq_mshr_misses::total 112673 # number of HardPFReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 10 # number of UpgradeReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::total 10 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 8362 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 8362 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 12208 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 12208 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 35955 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 35955 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 12208 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 44317 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 56525 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 12208 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 44317 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 112494 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 169019 # number of overall MSHR misses -system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 10322993748 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 10322993748 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 147000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 147000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 658062000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 658062000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 841432500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 841432500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2745124500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2745124500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 841432500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3403186500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 4244619000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 841432500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3403186500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 10322993748 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 14567612748 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 8158 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 8158 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 10034 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 10034 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 36403 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 36403 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 10034 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 44561 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 54595 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 10034 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 44561 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 112673 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 167268 # number of overall MSHR misses +system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 10413466023 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 10413466023 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 149500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 149500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 654073000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 654073000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 699673000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 699673000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2773387500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2773387500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 699673000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3427460500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 4127133500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 699673000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3427460500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 10413466023 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 14540599523 # number of overall MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.056284 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.056284 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.037721 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.037721 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.106701 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.106701 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.037721 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.091274 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.069855 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.037721 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.091274 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.909091 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.909091 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.054909 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.054909 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.031019 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.031019 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.108037 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.108037 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.031019 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.091780 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.067484 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.031019 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.091780 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.208878 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 91764.838551 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 91764.838551 # average HardPFReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14700 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14700 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 78696.723272 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 78696.723272 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 68924.680537 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 68924.680537 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 76348.894451 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76348.894451 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68924.680537 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 76791.897015 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 75092.773109 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68924.680537 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 76791.897015 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 91764.838551 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 86189.202090 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.206758 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 92422.017901 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 92422.017901 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14950 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14950 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80175.655798 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 80175.655798 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69730.217261 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69730.217261 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 76185.685246 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76185.685246 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69730.217261 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 76916.148650 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 75595.448301 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69730.217261 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 76916.148650 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 92422.017901 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 86929.953864 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 1617353 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 808194 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 79842 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 67170 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 56578 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 10592 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadResp 660621 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 354016 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 551426 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 79011 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 142034 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 10 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 10 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 148567 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 148567 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 323652 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 336970 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 970420 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1456119 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 2426539 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 41393152 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 62115968 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 103509120 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 318345 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 1127532 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.139813 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.372899 # Request fanout histogram +system.cpu.toL2Bus.snoop_filter.tot_requests 1617003 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 808019 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 79877 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 65377 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 56343 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 9034 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.trans_dist::ReadResp 660441 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 356528 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 548578 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 77222 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 142341 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 11 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 11 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 148572 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 148572 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 323492 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 336950 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 969940 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1456076 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 2426016 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 41372672 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 62114048 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 103486720 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 316702 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 1125716 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.137094 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.366537 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 980480 86.96% 86.96% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 136460 12.10% 99.06% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 10592 0.94% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 980421 87.09% 87.09% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 136261 12.10% 99.20% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 9034 0.80% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 1127532 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 1616830500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 1125716 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 1616479500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 4.8 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 485918614 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 485683604 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 1.4 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 728566986 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 728543988 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 2.2 # Layer utilization (%) -system.membus.trans_dist::ReadResp 144525 # Transaction distribution -system.membus.trans_dist::WritebackDirty 97288 # Transaction distribution -system.membus.trans_dist::CleanEvict 27973 # Transaction distribution +system.membus.trans_dist::ReadResp 143003 # Transaction distribution +system.membus.trans_dist::WritebackDirty 97128 # Transaction distribution +system.membus.trans_dist::CleanEvict 27951 # Transaction distribution system.membus.trans_dist::UpgradeReq 10 # Transaction distribution -system.membus.trans_dist::ReadExReq 8362 # Transaction distribution -system.membus.trans_dist::ReadExResp 8362 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 144526 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 431046 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 431046 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16011200 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 16011200 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadExReq 8158 # Transaction distribution +system.membus.trans_dist::ReadExResp 8158 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 143004 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 427412 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 427412 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15890496 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 15890496 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 278159 # Request fanout histogram +system.membus.snoop_fanout::samples 276251 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 278159 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 276251 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 278159 # Request fanout histogram -system.membus.reqLayer0.occupancy 748401121 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 276251 # Request fanout histogram +system.membus.reqLayer0.occupancy 745073302 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 798557507 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 2.4 # Layer utilization (%) +system.membus.respLayer1.occupancy 789293648 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 2.3 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout index 8f9f5bdd9..96efea7df 100755 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout @@ -3,13 +3,11 @@ Redirecting stderr to build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/s gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 15 2016 19:39:16 -gem5 started Mar 15 2016 19:40:28 -gem5 executing on dinar2c11, pid 3690 +gem5 compiled Mar 16 2016 15:38:19 +gem5 started Mar 16 2016 15:38:50 +gem5 executing on dinar2c11, pid 14357 command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing -re /home/stever/gem5-public/tests/run.py build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing -Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/smred.sav -Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt index f2dc6cd5a..a8124019a 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.079141 # Nu sim_ticks 79140979500 # Number of ticks simulated final_tick 79140979500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 48534 # Simulator instruction rate (inst/s) -host_op_rate 81347 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 29082810 # Simulator tick rate (ticks/s) -host_mem_usage 336912 # Number of bytes of host memory used -host_seconds 2721.23 # Real time elapsed on the host +host_inst_rate 48369 # Simulator instruction rate (inst/s) +host_op_rate 81071 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 28984226 # Simulator tick rate (ticks/s) +host_mem_usage 336892 # Number of bytes of host memory used +host_seconds 2730.48 # Real time elapsed on the host sim_insts 132071192 # Number of instructions simulated sim_ops 221363384 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -266,7 +266,7 @@ system.cpu.numCycles 158281960 # nu system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.fetch.icacheStallCycles 25261186 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 227540230 # Number of instructions fetch has processed +system.cpu.fetch.Insts 227540228 # Number of instructions fetch has processed system.cpu.fetch.Branches 20604097 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 13459793 # Number of branches that fetch has predicted taken system.cpu.fetch.Cycles 131194120 # Number of cycles fetch has run and was not squashing or blocked @@ -280,17 +280,17 @@ system.cpu.fetch.CacheLines 24267792 # Nu system.cpu.fetch.IcacheSquashes 266999 # Number of outstanding Icache misses that were squashed system.cpu.fetch.rateDist::samples 158076676 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::mean 2.380152 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.324972 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.324971 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 95737540 60.56% 60.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 95737539 60.56% 60.56% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::1 4758449 3.01% 63.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 3804662 2.41% 65.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 3804663 2.41% 65.98% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::3 4365114 2.76% 68.74% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::4 4234763 2.68% 71.42% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::5 4816061 3.05% 74.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 4706873 2.98% 77.45% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 4706874 2.98% 77.45% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::7 3702906 2.34% 79.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 31950308 20.21% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 31950307 20.21% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) @@ -299,8 +299,8 @@ system.cpu.fetch.branchRate 0.130173 # Nu system.cpu.fetch.rate 1.437563 # Number of inst fetches per cycle system.cpu.decode.IdleCycles 15410588 # Number of cycles decode is idle system.cpu.decode.BlockedCycles 96165479 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 23286260 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 21616249 # Number of cycles decode is unblocking +system.cpu.decode.RunCycles 23286259 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 21616250 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 1598100 # Number of cycles decode is squashing system.cpu.decode.DecodedInsts 336629364 # Number of instructions handled by decode system.cpu.rename.SquashCycles 1598100 # Number of cycles rename is squashing @@ -314,22 +314,22 @@ system.cpu.rename.ROBFullEvents 1575 # Nu system.cpu.rename.IQFullEvents 57713162 # Number of times rename has blocked due to IQ full system.cpu.rename.LQFullEvents 7745606 # Number of times rename has blocked due to LQ full system.cpu.rename.SQFullEvents 167786 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 380441374 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 910027756 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 600617832 # Number of integer rename lookups +system.cpu.rename.RenamedOperands 380441368 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 910027762 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 600617825 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 4182134 # Number of floating rename lookups system.cpu.rename.CommittedMaps 259429450 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 121011924 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 121011918 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 1942 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 1920 # count of temporary serializing insts renamed system.cpu.rename.skidInsts 120996232 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 82787392 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedLoads 82787391 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 29790688 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 59618216 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 20385329 # Number of conflicting stores. system.cpu.iq.iqInstsAdded 317847109 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 5129 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 259397690 # Number of instructions issued +system.cpu.iq.iqInstsIssued 259397692 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 74444 # Number of squashed instructions issued system.cpu.iq.iqSquashedInstsExamined 96488854 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedOperandsExamined 197170724 # Number of squashed operands that are examined and possibly removed from graph @@ -338,8 +338,8 @@ system.cpu.iq.issued_per_cycle::samples 158076676 # Nu system.cpu.iq.issued_per_cycle::mean 1.640961 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::stdev 1.524821 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 40037946 25.33% 25.33% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 47502915 30.05% 55.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 40037944 25.33% 25.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 47502917 30.05% 55.38% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::2 33077309 20.92% 76.30% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::3 17993681 11.38% 87.69% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::4 10964078 6.94% 94.62% # Number of insts issued each cycle @@ -386,7 +386,7 @@ system.cpu.iq.fu_full::MemWrite 383461 12.07% 100.00% # at system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 1212757 0.47% 0.47% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 161810980 62.38% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 161810982 62.38% 62.85% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 789695 0.30% 63.15% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 7037932 2.71% 65.86% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 1186383 0.46% 66.32% # Type of FU issued @@ -419,21 +419,21 @@ system.cpu.iq.FU_type_0::MemRead 64896242 25.02% 91.34% # Ty system.cpu.iq.FU_type_0::MemWrite 22463701 8.66% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 259397690 # Type of FU issued +system.cpu.iq.FU_type_0::total 259397692 # Type of FU issued system.cpu.iq.rate 1.638833 # Inst issue rate system.cpu.iq.fu_busy_cnt 3176512 # FU busy when requested system.cpu.iq.fu_busy_rate 0.012246 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 675268343 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_reads 675268347 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 410944123 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 253662317 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_wakeup_accesses 253662320 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 4854669 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 3693735 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 2339703 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 258916834 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 258916836 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 2444611 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 18724074 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 26137805 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 26137804 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 13130 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 303242 # Number of memory ordering violations system.cpu.iew.lsq.thread0.squashedStores 9274971 # Number of stores squashed @@ -447,7 +447,7 @@ system.cpu.iew.iewBlockCycles 12496396 # Nu system.cpu.iew.iewUnblockCycles 489060 # Number of cycles IEW is unblocking system.cpu.iew.iewDispatchedInsts 317852238 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 92568 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 82787392 # Number of dispatched load instructions +system.cpu.iew.iewDispLoadInsts 82787391 # Number of dispatched load instructions system.cpu.iew.iewDispStoreInsts 29790688 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 2962 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 383739 # Number of times the IQ has become full, causing a stall @@ -456,19 +456,19 @@ system.cpu.iew.memOrderViolationEvents 303242 # Nu system.cpu.iew.predictedTakenIncorrect 551670 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 826736 # Number of branches that were predicted not taken incorrectly system.cpu.iew.branchMispredicts 1378406 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 257339860 # Number of executed instructions +system.cpu.iew.iewExecutedInsts 257339863 # Number of executed instructions system.cpu.iew.iewExecLoadInsts 64084690 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2057830 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecSquashedInsts 2057829 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 86369701 # number of memory reference insts executed +system.cpu.iew.exec_refs 86369702 # number of memory reference insts executed system.cpu.iew.exec_branches 14330688 # Number of branches executed -system.cpu.iew.exec_stores 22285011 # Number of stores executed +system.cpu.iew.exec_stores 22285012 # Number of stores executed system.cpu.iew.exec_rate 1.625832 # Inst execution rate -system.cpu.iew.wb_sent 256690834 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 256002020 # cumulative count of insts written-back +system.cpu.iew.wb_sent 256690837 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 256002023 # cumulative count of insts written-back system.cpu.iew.wb_producers 204396158 # num instructions producing a value -system.cpu.iew.wb_consumers 369708067 # num instructions consuming a value +system.cpu.iew.wb_consumers 369708068 # num instructions consuming a value system.cpu.iew.wb_rate 1.617380 # insts written-back per cycle system.cpu.iew.wb_fanout 0.552858 # average fanout of values written-back system.cpu.commit.commitSquashedInsts 96496531 # The number of squashed insts skipped by commit @@ -547,13 +547,13 @@ system.cpu.cpi 1.198459 # CP system.cpu.cpi_total 1.198459 # CPI: Total CPI of All Threads system.cpu.ipc 0.834405 # IPC: Instructions Per Cycle system.cpu.ipc_total 0.834405 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 448575235 # number of integer regfile reads +system.cpu.int_regfile_reads 448575238 # number of integer regfile reads system.cpu.int_regfile_writes 232602901 # number of integer regfile writes system.cpu.fp_regfile_reads 3212636 # number of floating regfile reads system.cpu.fp_regfile_writes 1997796 # number of floating regfile writes system.cpu.cc_regfile_reads 102540240 # number of cc regfile reads system.cpu.cc_regfile_writes 59516414 # number of cc regfile writes -system.cpu.misc_regfile_reads 132474844 # number of misc regfile reads +system.cpu.misc_regfile_reads 132474845 # number of misc regfile reads system.cpu.misc_regfile_writes 1689 # number of misc regfile writes system.cpu.dcache.tags.replacements 51 # number of replacements system.cpu.dcache.tags.tagsinuse 1429.115986 # Cycle average of tags in use diff --git a/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/config.ini b/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/config.ini index 0946d7533..66af6c729 100644 --- a/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/config.ini +++ b/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/config.ini @@ -216,7 +216,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/dist/m5/cpu2000/binaries/arm/linux/vortex +executable=/home/stever/m5/dist/cpu2000/binaries/arm/linux/vortex gid=100 input=cin kvmInSE=false @@ -251,6 +251,7 @@ clk_domain=system.clk_domain eventq_index=0 forward_latency=4 frontend_latency=3 +point_of_coherency=true response_latency=2 snoop_filter=Null snoop_response_latency=4 diff --git a/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/simout b/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/simout index 84e37158c..315146752 100755 --- a/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/simout +++ b/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/simout @@ -1,12 +1,14 @@ +Redirecting stdout to build/ARM/tests/opt/quick/se/50.vortex/arm/linux/simple-atomic/simout +Redirecting stderr to build/ARM/tests/opt/quick/se/50.vortex/arm/linux/simple-atomic/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 21 2016 14:45:42 -gem5 started Jan 21 2016 14:46:23 -gem5 executing on zizzer, pid 20742 -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/50.vortex/arm/linux/simple-atomic -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ARM/tests/opt/quick/se/50.vortex/arm/linux/simple-atomic +gem5 compiled Mar 14 2016 17:50:51 +gem5 started Mar 14 2016 18:07:36 +gem5 executing on phenom, pid 27152 +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/50.vortex/arm/linux/simple-atomic -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ARM/tests/opt/quick/se/50.vortex/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. -Exiting @ tick 48960011500 because target called exit() +Exiting @ tick 48960022500 because target called exit() diff --git a/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt b/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt index ecfc0b9ca..bcdad61b2 100644 --- a/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt @@ -1,40 +1,40 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.048960 # Number of seconds simulated -sim_ticks 48960011500 # Number of ticks simulated -final_tick 48960011500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 48960022500 # Number of ticks simulated +final_tick 48960022500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 622932 # Simulator instruction rate (inst/s) -host_op_rate 796644 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 430085915 # Simulator tick rate (ticks/s) -host_mem_usage 246536 # Number of bytes of host memory used -host_seconds 113.84 # Real time elapsed on the host -sim_insts 70913182 # Number of instructions simulated -sim_ops 90688137 # Number of ops (including micro ops) simulated +host_inst_rate 991674 # Simulator instruction rate (inst/s) +host_op_rate 1268214 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 684673258 # Simulator tick rate (ticks/s) +host_mem_usage 242788 # Number of bytes of host memory used +host_seconds 71.51 # Real time elapsed on the host +sim_insts 70913204 # Number of instructions simulated +sim_ops 90688159 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 312580276 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 312580364 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 106573345 # Number of bytes read from this memory -system.physmem.bytes_read::total 419153621 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 312580276 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 312580276 # Number of instructions bytes read from this memory +system.physmem.bytes_read::total 419153709 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 312580364 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 312580364 # Number of instructions bytes read from this memory system.physmem.bytes_written::cpu.data 78660211 # Number of bytes written to this memory system.physmem.bytes_written::total 78660211 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 78145069 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 78145091 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 22919730 # Number of read requests responded to by this memory -system.physmem.num_reads::total 101064799 # Number of read requests responded to by this memory +system.physmem.num_reads::total 101064821 # Number of read requests responded to by this memory system.physmem.num_writes::cpu.data 19865820 # Number of write requests responded to by this memory system.physmem.num_writes::total 19865820 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 6384399562 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2176742646 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 8561142209 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 6384399562 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 6384399562 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1606621579 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1606621579 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 6384399562 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3783364226 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 10167763788 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 6384399925 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2176742157 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 8561142083 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 6384399925 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 6384399925 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1606621218 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1606621218 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 6384399925 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3783363376 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 10167763301 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -153,33 +153,33 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 97920024 # number of cpu cycles simulated +system.cpu.numCycles 97920046 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 70913182 # Number of instructions committed -system.cpu.committedOps 90688137 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 81528488 # Number of integer alu accesses +system.cpu.committedInsts 70913204 # Number of instructions committed +system.cpu.committedOps 90688159 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 81528528 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 56 # Number of float alu accesses system.cpu.num_func_calls 3311620 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 9253644 # number of instructions that are conditional controls -system.cpu.num_int_insts 81528488 # number of integer instructions +system.cpu.num_conditional_control_insts 9253630 # number of instructions that are conditional controls +system.cpu.num_int_insts 81528528 # number of integer instructions system.cpu.num_fp_insts 56 # number of float instructions -system.cpu.num_int_register_reads 141479310 # number of times the integer registers were read -system.cpu.num_int_register_writes 53916283 # number of times the integer registers were written +system.cpu.num_int_register_reads 141479386 # number of times the integer registers were read +system.cpu.num_int_register_writes 53916335 # number of times the integer registers were written system.cpu.num_fp_register_reads 36 # number of times the floating registers were read system.cpu.num_fp_register_writes 20 # number of times the floating registers were written -system.cpu.num_cc_register_reads 266608031 # number of times the CC registers were read -system.cpu.num_cc_register_writes 36877020 # number of times the CC registers were written +system.cpu.num_cc_register_reads 266608097 # number of times the CC registers were read +system.cpu.num_cc_register_writes 36877111 # number of times the CC registers were written system.cpu.num_mem_refs 43422001 # number of memory refs system.cpu.num_load_insts 22866262 # Number of load instructions system.cpu.num_store_insts 20555739 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 97920023.998000 # Number of busy cycles +system.cpu.num_busy_cycles 97920045.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 13741486 # Number of branches fetched +system.cpu.Branches 13741468 # Number of branches fetched system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 47187957 52.03% 52.03% # Class of executed instruction +system.cpu.op_class::IntAlu 47187979 52.03% 52.03% # Class of executed instruction system.cpu.op_class::IntMult 80119 0.09% 52.12% # Class of executed instruction system.cpu.op_class::IntDiv 0 0.00% 52.12% # Class of executed instruction system.cpu.op_class::FloatAdd 0 0.00% 52.12% # Class of executed instruction @@ -212,9 +212,9 @@ system.cpu.op_class::MemRead 22866262 25.21% 77.33% # Cl system.cpu.op_class::MemWrite 20555739 22.67% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 90690084 # Class of executed instruction -system.membus.trans_dist::ReadReq 100925136 # Transaction distribution -system.membus.trans_dist::ReadResp 100941055 # Transaction distribution +system.cpu.op_class::total 90690106 # Class of executed instruction +system.membus.trans_dist::ReadReq 100925158 # Transaction distribution +system.membus.trans_dist::ReadResp 100941077 # Transaction distribution system.membus.trans_dist::WriteReq 19849901 # Transaction distribution system.membus.trans_dist::WriteResp 19849901 # Transaction distribution system.membus.trans_dist::SoftPFReq 123744 # Transaction distribution @@ -222,22 +222,22 @@ system.membus.trans_dist::SoftPFResp 123744 # Tr system.membus.trans_dist::LoadLockedReq 15919 # Transaction distribution system.membus.trans_dist::StoreCondReq 15919 # Transaction distribution system.membus.trans_dist::StoreCondResp 15919 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 156290138 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 156290182 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 85571100 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 241861238 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 312580276 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 241861282 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 312580364 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 185233556 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 497813832 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 497813920 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 120930619 # Request fanout histogram +system.membus.snoop_fanout::samples 120930641 # Request fanout histogram system.membus.snoop_fanout::mean 0.646198 # Request fanout histogram system.membus.snoop_fanout::stdev 0.478149 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 42785550 35.38% 35.38% # Request fanout histogram -system.membus.snoop_fanout::1 78145069 64.62% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 78145091 64.62% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 120930619 # Request fanout histogram +system.membus.snoop_fanout::total 120930641 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/config.ini b/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/config.ini index 5ef054f5d..e8b410808 100644 --- a/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/config.ini +++ b/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/config.ini @@ -90,7 +90,6 @@ clk_domain=system.cpu_clk_domain clusivity=mostly_incl demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=2 is_read_only=false max_miss_count=0 @@ -168,7 +167,6 @@ clk_domain=system.cpu_clk_domain clusivity=mostly_incl demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=2 is_read_only=true max_miss_count=0 @@ -281,7 +279,6 @@ clk_domain=system.cpu_clk_domain clusivity=mostly_incl demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=20 is_read_only=false max_miss_count=0 @@ -316,6 +313,7 @@ clk_domain=system.cpu_clk_domain eventq_index=0 forward_latency=0 frontend_latency=1 +point_of_coherency=false response_latency=1 snoop_filter=system.cpu.toL2Bus.snoop_filter snoop_response_latency=1 @@ -346,7 +344,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/dist/m5/cpu2000/binaries/arm/linux/vortex +executable=/home/stever/m5/dist/cpu2000/binaries/arm/linux/vortex gid=100 input=cin kvmInSE=false @@ -381,6 +379,7 @@ clk_domain=system.clk_domain eventq_index=0 forward_latency=4 frontend_latency=3 +point_of_coherency=true response_latency=2 snoop_filter=Null snoop_response_latency=4 diff --git a/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/simout b/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/simout index de3c6dccc..6b39172d0 100755 --- a/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/simout +++ b/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/simout @@ -1,12 +1,14 @@ +Redirecting stdout to build/ARM/tests/opt/quick/se/50.vortex/arm/linux/simple-timing/simout +Redirecting stderr to build/ARM/tests/opt/quick/se/50.vortex/arm/linux/simple-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 21 2016 14:45:42 -gem5 started Jan 21 2016 14:46:19 -gem5 executing on zizzer, pid 20723 -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/50.vortex/arm/linux/simple-timing -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ARM/tests/opt/quick/se/50.vortex/arm/linux/simple-timing +gem5 compiled Mar 14 2016 17:50:51 +gem5 started Mar 14 2016 18:03:19 +gem5 executing on phenom, pid 27037 +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/50.vortex/arm/linux/simple-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ARM/tests/opt/quick/se/50.vortex/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. -Exiting @ tick 128076812500 because target called exit() +Exiting @ tick 128076834500 because target called exit() diff --git a/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt index 7f5c6bd39..c10ef56cb 100644 --- a/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt +++ b/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.128077 # Number of seconds simulated -sim_ticks 128076812500 # Number of ticks simulated -final_tick 128076812500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 128076834500 # Number of ticks simulated +final_tick 128076834500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 887065 # Simulator instruction rate (inst/s) -host_op_rate 1132533 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1614418321 # Simulator tick rate (ticks/s) -host_mem_usage 277452 # Number of bytes of host memory used -host_seconds 79.33 # Real time elapsed on the host -sim_insts 70373629 # Number of instructions simulated -sim_ops 89847363 # Number of ops (including micro ops) simulated +host_inst_rate 508798 # Simulator instruction rate (inst/s) +host_op_rate 649592 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 925989388 # Simulator tick rate (ticks/s) +host_mem_usage 253236 # Number of bytes of host memory used +host_seconds 138.31 # Real time elapsed on the host +sim_insts 70373651 # Number of instructions simulated +sim_ops 89847385 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 233152 # Number of bytes read from this memory @@ -25,17 +25,17 @@ system.physmem.num_reads::cpu.data 123832 # Nu system.physmem.num_reads::total 127475 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 86150 # Number of write requests responded to by this memory system.physmem.num_writes::total 86150 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 1820408 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 61878867 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 63699274 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1820408 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1820408 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 43049166 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 43049166 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 43049166 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1820408 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 61878867 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 106748441 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1820407 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 61878856 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 63699263 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1820407 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1820407 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 43049159 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 43049159 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 43049159 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1820407 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 61878856 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 106748422 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -154,33 +154,33 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 256153625 # number of cpu cycles simulated +system.cpu.numCycles 256153669 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 70373629 # Number of instructions committed -system.cpu.committedOps 89847363 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 81528488 # Number of integer alu accesses +system.cpu.committedInsts 70373651 # Number of instructions committed +system.cpu.committedOps 89847385 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 81528528 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 56 # Number of float alu accesses system.cpu.num_func_calls 3311620 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 9253644 # number of instructions that are conditional controls -system.cpu.num_int_insts 81528488 # number of integer instructions +system.cpu.num_conditional_control_insts 9253630 # number of instructions that are conditional controls +system.cpu.num_int_insts 81528528 # number of integer instructions system.cpu.num_fp_insts 56 # number of float instructions -system.cpu.num_int_register_reads 141328474 # number of times the integer registers were read -system.cpu.num_int_register_writes 53916283 # number of times the integer registers were written +system.cpu.num_int_register_reads 141328550 # number of times the integer registers were read +system.cpu.num_int_register_writes 53916335 # number of times the integer registers were written system.cpu.num_fp_register_reads 36 # number of times the floating registers were read system.cpu.num_fp_register_writes 20 # number of times the floating registers were written -system.cpu.num_cc_register_reads 334802006 # number of times the CC registers were read -system.cpu.num_cc_register_writes 36877020 # number of times the CC registers were written +system.cpu.num_cc_register_reads 334802072 # number of times the CC registers were read +system.cpu.num_cc_register_writes 36877111 # number of times the CC registers were written system.cpu.num_mem_refs 43422001 # number of memory refs system.cpu.num_load_insts 22866262 # Number of load instructions system.cpu.num_store_insts 20555739 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 256153624.998000 # Number of busy cycles +system.cpu.num_busy_cycles 256153668.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 13741486 # Number of branches fetched +system.cpu.Branches 13741468 # Number of branches fetched system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 47187957 52.03% 52.03% # Class of executed instruction +system.cpu.op_class::IntAlu 47187979 52.03% 52.03% # Class of executed instruction system.cpu.op_class::IntMult 80119 0.09% 52.12% # Class of executed instruction system.cpu.op_class::IntDiv 0 0.00% 52.12% # Class of executed instruction system.cpu.op_class::FloatAdd 0 0.00% 52.12% # Class of executed instruction @@ -213,14 +213,14 @@ system.cpu.op_class::MemRead 22866262 25.21% 77.33% # Cl system.cpu.op_class::MemWrite 20555739 22.67% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 90690084 # Class of executed instruction +system.cpu.op_class::total 90690106 # Class of executed instruction system.cpu.dcache.tags.replacements 155902 # number of replacements -system.cpu.dcache.tags.tagsinuse 4075.927151 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 4075.927155 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 42601677 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 159998 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 266.263810 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 1109655500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4075.927151 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 4075.927155 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.995099 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.995099 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id @@ -352,12 +352,12 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 49964.608933 system.cpu.dcache.overall_avg_mshr_miss_latency::total 49964.608933 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 16890 # number of replacements -system.cpu.icache.tags.tagsinuse 1732.356647 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 78126162 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 1732.356634 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 78126184 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 18908 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 4131.910408 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 4131.911572 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1732.356647 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 1732.356634 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.845877 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.845877 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 2018 # Occupied blocks per task id @@ -366,14 +366,14 @@ system.cpu.icache.tags.age_task_id_blocks_1024::1 22 system.cpu.icache.tags.age_task_id_blocks_1024::3 294 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1645 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.985352 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 156309048 # Number of tag accesses -system.cpu.icache.tags.data_accesses 156309048 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 78126162 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 78126162 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 78126162 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 78126162 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 78126162 # number of overall hits -system.cpu.icache.overall_hits::total 78126162 # number of overall hits +system.cpu.icache.tags.tag_accesses 156309092 # Number of tag accesses +system.cpu.icache.tags.data_accesses 156309092 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 78126184 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 78126184 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 78126184 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 78126184 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 78126184 # number of overall hits +system.cpu.icache.overall_hits::total 78126184 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 18908 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 18908 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 18908 # number of demand (read+write) misses @@ -386,12 +386,12 @@ system.cpu.icache.demand_miss_latency::cpu.inst 426200500 system.cpu.icache.demand_miss_latency::total 426200500 # number of demand (read+write) miss cycles system.cpu.icache.overall_miss_latency::cpu.inst 426200500 # number of overall miss cycles system.cpu.icache.overall_miss_latency::total 426200500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 78145070 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 78145070 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 78145070 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 78145070 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 78145070 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 78145070 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_accesses::cpu.inst 78145092 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 78145092 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 78145092 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 78145092 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 78145092 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 78145092 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000242 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000242 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000242 # miss rate for demand accesses @@ -440,14 +440,14 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21540.749947 system.cpu.icache.overall_avg_mshr_miss_latency::total 21540.749947 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 95333 # number of replacements -system.cpu.l2cache.tags.tagsinuse 30336.891349 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 30336.891531 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 114380 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 126455 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.904511 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 27758.605172 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1088.258764 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 1490.027413 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 27758.605525 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1088.258663 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 1490.027343 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.847125 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.033211 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.045472 # Average percentage of cache occupancy diff --git a/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/config.ini b/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/config.ini index b68bc2a7d..20fc06e75 100644 --- a/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/config.ini @@ -115,7 +115,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/dist/m5/cpu2000/binaries/sparc/linux/vortex +executable=/home/stever/m5/dist/cpu2000/binaries/sparc/linux/vortex gid=100 input=cin kvmInSE=false @@ -150,6 +150,7 @@ clk_domain=system.clk_domain eventq_index=0 forward_latency=4 frontend_latency=3 +point_of_coherency=true response_latency=2 snoop_filter=Null snoop_response_latency=4 diff --git a/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/simout b/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/simout index 51bf0b517..98ece2f0d 100755 --- a/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/simout +++ b/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/simout @@ -1,12 +1,14 @@ +Redirecting stdout to build/SPARC/tests/opt/quick/se/50.vortex/sparc/linux/simple-atomic/simout +Redirecting stderr to build/SPARC/tests/opt/quick/se/50.vortex/sparc/linux/simple-atomic/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 21 2016 14:30:54 -gem5 started Jan 21 2016 14:31:25 -gem5 executing on zizzer, pid 8713 -command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/50.vortex/sparc/linux/simple-atomic -re /z/atgutier/gem5/gem5-commit/tests/run.py build/SPARC/tests/opt/quick/se/50.vortex/sparc/linux/simple-atomic +gem5 compiled Mar 14 2016 17:46:51 +gem5 started Mar 14 2016 17:54:20 +gem5 executing on phenom, pid 26843 +command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/50.vortex/sparc/linux/simple-atomic -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/SPARC/tests/opt/quick/se/50.vortex/sparc/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. -Exiting @ tick 68148672000 because target called exit() +Exiting @ tick 68148677000 because target called exit() diff --git a/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt b/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt index ba8d2e144..3ed030f96 100644 --- a/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt @@ -1,69 +1,69 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.068149 # Number of seconds simulated -sim_ticks 68148672000 # Number of ticks simulated -final_tick 68148672000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 68148677000 # Number of ticks simulated +final_tick 68148677000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1099944 # Simulator instruction rate (inst/s) -host_op_rate 1114186 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 557740246 # Simulator tick rate (ticks/s) -host_mem_usage 228968 # Number of bytes of host memory used -host_seconds 122.19 # Real time elapsed on the host -sim_insts 134398962 # Number of instructions simulated -sim_ops 136139190 # Number of ops (including micro ops) simulated +host_inst_rate 1843276 # Simulator instruction rate (inst/s) +host_op_rate 1867142 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 934655607 # Simulator tick rate (ticks/s) +host_mem_usage 225200 # Number of bytes of host memory used +host_seconds 72.91 # Real time elapsed on the host +sim_insts 134398959 # Number of instructions simulated +sim_ops 136139187 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 538214280 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 538214320 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 147559360 # Number of bytes read from this memory -system.physmem.bytes_read::total 685773640 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 538214280 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 538214280 # Number of instructions bytes read from this memory +system.physmem.bytes_read::total 685773680 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 538214320 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 538214320 # Number of instructions bytes read from this memory system.physmem.bytes_written::cpu.data 89882950 # Number of bytes written to this memory system.physmem.bytes_written::total 89882950 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 134553570 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 134553580 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 37231300 # Number of read requests responded to by this memory -system.physmem.num_reads::total 171784870 # Number of read requests responded to by this memory +system.physmem.num_reads::total 171784880 # Number of read requests responded to by this memory system.physmem.num_writes::cpu.data 20864304 # Number of write requests responded to by this memory system.physmem.num_writes::total 20864304 # Number of write requests responded to by this memory system.physmem.num_other::cpu.data 15916 # Number of other requests responded to by this memory system.physmem.num_other::total 15916 # Number of other requests responded to by this memory -system.physmem.bw_read::cpu.inst 7897648835 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2165256573 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 10062905408 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 7897648835 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 7897648835 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1318924454 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1318924454 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 7897648835 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3484181027 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 11381829862 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 7897648842 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2165256414 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 10062905256 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 7897648842 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 7897648842 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1318924357 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1318924357 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 7897648842 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3484180771 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 11381829614 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 136297345 # number of cpu cycles simulated +system.cpu.numCycles 136297355 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 134398962 # Number of instructions committed -system.cpu.committedOps 136139190 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 115187746 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 2326977 # Number of float alu accesses +system.cpu.committedInsts 134398959 # Number of instructions committed +system.cpu.committedOps 136139187 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 115187757 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 2326976 # Number of float alu accesses system.cpu.num_func_calls 1709332 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 8898969 # number of instructions that are conditional controls -system.cpu.num_int_insts 115187746 # number of integer instructions -system.cpu.num_fp_insts 2326977 # number of float instructions -system.cpu.num_int_register_reads 263032361 # number of times the integer registers were read -system.cpu.num_int_register_writes 113147734 # number of times the integer registers were written -system.cpu.num_fp_register_reads 4725607 # number of times the floating registers were read +system.cpu.num_conditional_control_insts 8898968 # number of instructions that are conditional controls +system.cpu.num_int_insts 115187757 # number of integer instructions +system.cpu.num_fp_insts 2326976 # number of float instructions +system.cpu.num_int_register_reads 263032419 # number of times the integer registers were read +system.cpu.num_int_register_writes 113147731 # number of times the integer registers were written +system.cpu.num_fp_register_reads 4725606 # number of times the floating registers were read system.cpu.num_fp_register_writes 1150968 # number of times the floating registers were written -system.cpu.num_mem_refs 58160248 # number of memory refs -system.cpu.num_load_insts 37275867 # Number of load instructions -system.cpu.num_store_insts 20884381 # Number of store instructions +system.cpu.num_mem_refs 58160261 # number of memory refs +system.cpu.num_load_insts 37275864 # Number of load instructions +system.cpu.num_store_insts 20884397 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 136297344.998000 # Number of busy cycles +system.cpu.num_busy_cycles 136297354.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 12719095 # Number of branches fetched +system.cpu.Branches 12719094 # Number of branches fetched system.cpu.op_class::No_OpClass 11445042 8.40% 8.40% # Class of executed instruction -system.cpu.op_class::IntAlu 66342070 48.68% 57.07% # Class of executed instruction +system.cpu.op_class::IntAlu 66342067 48.68% 57.07% # Class of executed instruction system.cpu.op_class::IntMult 0 0.00% 57.07% # Class of executed instruction system.cpu.op_class::IntDiv 0 0.00% 57.07% # Class of executed instruction system.cpu.op_class::FloatAdd 325584 0.24% 57.31% # Class of executed instruction @@ -92,33 +92,33 @@ system.cpu.op_class::SimdFloatMisc 0 0.00% 57.31% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 57.31% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 57.31% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::MemRead 37296721 27.36% 84.68% # Class of executed instruction -system.cpu.op_class::MemWrite 20884381 15.32% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 37296718 27.36% 84.68% # Class of executed instruction +system.cpu.op_class::MemWrite 20884397 15.32% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 136293798 # Class of executed instruction -system.membus.trans_dist::ReadReq 171784870 # Transaction distribution -system.membus.trans_dist::ReadResp 171784870 # Transaction distribution +system.cpu.op_class::total 136293808 # Class of executed instruction +system.membus.trans_dist::ReadReq 171784880 # Transaction distribution +system.membus.trans_dist::ReadResp 171784880 # Transaction distribution system.membus.trans_dist::WriteReq 20864304 # Transaction distribution system.membus.trans_dist::WriteResp 20864304 # Transaction distribution system.membus.trans_dist::SwapReq 15916 # Transaction distribution system.membus.trans_dist::SwapResp 15916 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 269107140 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 269107160 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 116223040 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 385330180 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 538214280 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 385330200 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 538214320 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 237569638 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 775783918 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 775783958 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 192665090 # Request fanout histogram +system.membus.snoop_fanout::samples 192665100 # Request fanout histogram system.membus.snoop_fanout::mean 0.698381 # Request fanout histogram system.membus.snoop_fanout::stdev 0.458961 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 58111520 30.16% 30.16% # Request fanout histogram -system.membus.snoop_fanout::1 134553570 69.84% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 134553580 69.84% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 192665090 # Request fanout histogram +system.membus.snoop_fanout::total 192665100 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/config.ini b/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/config.ini index 4aa8d2f80..9da4061be 100644 --- a/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/config.ini +++ b/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/config.ini @@ -88,7 +88,6 @@ clk_domain=system.cpu_clk_domain clusivity=mostly_incl demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=2 is_read_only=false max_miss_count=0 @@ -130,7 +129,6 @@ clk_domain=system.cpu_clk_domain clusivity=mostly_incl demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=2 is_read_only=true max_miss_count=0 @@ -180,7 +178,6 @@ clk_domain=system.cpu_clk_domain clusivity=mostly_incl demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=20 is_read_only=false max_miss_count=0 @@ -215,6 +212,7 @@ clk_domain=system.cpu_clk_domain eventq_index=0 forward_latency=0 frontend_latency=1 +point_of_coherency=false response_latency=1 snoop_filter=system.cpu.toL2Bus.snoop_filter snoop_response_latency=1 @@ -245,7 +243,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/dist/m5/cpu2000/binaries/sparc/linux/vortex +executable=/home/stever/m5/dist/cpu2000/binaries/sparc/linux/vortex gid=100 input=cin kvmInSE=false @@ -280,6 +278,7 @@ clk_domain=system.clk_domain eventq_index=0 forward_latency=4 frontend_latency=3 +point_of_coherency=true response_latency=2 snoop_filter=Null snoop_response_latency=4 diff --git a/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/simout b/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/simout index a1ad3bacc..d24399f8c 100755 --- a/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/simout +++ b/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/simout @@ -1,12 +1,14 @@ +Redirecting stdout to build/SPARC/tests/opt/quick/se/50.vortex/sparc/linux/simple-timing/simout +Redirecting stderr to build/SPARC/tests/opt/quick/se/50.vortex/sparc/linux/simple-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 21 2016 14:30:54 -gem5 started Jan 21 2016 14:31:26 -gem5 executing on zizzer, pid 8734 -command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/50.vortex/sparc/linux/simple-timing -re /z/atgutier/gem5/gem5-commit/tests/run.py build/SPARC/tests/opt/quick/se/50.vortex/sparc/linux/simple-timing +gem5 compiled Mar 14 2016 17:46:51 +gem5 started Mar 14 2016 17:55:53 +gem5 executing on phenom, pid 26906 +command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/50.vortex/sparc/linux/simple-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/SPARC/tests/opt/quick/se/50.vortex/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. -Exiting @ tick 203115876500 because target called exit() +Exiting @ tick 203115946500 because target called exit() diff --git a/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt index d6835fc82..75f9fb3c6 100644 --- a/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt @@ -1,68 +1,68 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.203116 # Number of seconds simulated -sim_ticks 203115876500 # Number of ticks simulated -final_tick 203115876500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 203115946500 # Number of ticks simulated +final_tick 203115946500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1130669 # Simulator instruction rate (inst/s) -host_op_rate 1145309 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1708768878 # Simulator tick rate (ticks/s) -host_mem_usage 305928 # Number of bytes of host memory used -host_seconds 118.87 # Real time elapsed on the host -sim_insts 134398962 # Number of instructions simulated -sim_ops 136139190 # Number of ops (including micro ops) simulated +host_inst_rate 864116 # Simulator instruction rate (inst/s) +host_op_rate 875304 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1305930078 # Simulator tick rate (ticks/s) +host_mem_usage 235576 # Number of bytes of host memory used +host_seconds 155.53 # Real time elapsed on the host +sim_insts 134398959 # Number of instructions simulated +sim_ops 136139187 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 525056 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 7828288 # Number of bytes read from this memory -system.physmem.bytes_read::total 8353344 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 7828352 # Number of bytes read from this memory +system.physmem.bytes_read::total 8353408 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 525056 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 525056 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 5457280 # Number of bytes written to this memory system.physmem.bytes_written::total 5457280 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 8204 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 122317 # Number of read requests responded to by this memory -system.physmem.num_reads::total 130521 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 122318 # Number of read requests responded to by this memory +system.physmem.num_reads::total 130522 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 85270 # Number of write requests responded to by this memory system.physmem.num_writes::total 85270 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 2585007 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 38540995 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 41126002 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2585007 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2585007 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 26867816 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 26867816 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 26867816 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2585007 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 38540995 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 67993818 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 2585006 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 38541297 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 41126303 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2585006 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2585006 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 26867807 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 26867807 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 26867807 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2585006 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 38541297 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 67994110 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 406231753 # number of cpu cycles simulated +system.cpu.numCycles 406231893 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 134398962 # Number of instructions committed -system.cpu.committedOps 136139190 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 115187746 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 2326977 # Number of float alu accesses +system.cpu.committedInsts 134398959 # Number of instructions committed +system.cpu.committedOps 136139187 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 115187757 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 2326976 # Number of float alu accesses system.cpu.num_func_calls 1709332 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 8898969 # number of instructions that are conditional controls -system.cpu.num_int_insts 115187746 # number of integer instructions -system.cpu.num_fp_insts 2326977 # number of float instructions -system.cpu.num_int_register_reads 263032361 # number of times the integer registers were read -system.cpu.num_int_register_writes 113147733 # number of times the integer registers were written -system.cpu.num_fp_register_reads 4725607 # number of times the floating registers were read +system.cpu.num_conditional_control_insts 8898968 # number of instructions that are conditional controls +system.cpu.num_int_insts 115187757 # number of integer instructions +system.cpu.num_fp_insts 2326976 # number of float instructions +system.cpu.num_int_register_reads 263032419 # number of times the integer registers were read +system.cpu.num_int_register_writes 113147730 # number of times the integer registers were written +system.cpu.num_fp_register_reads 4725606 # number of times the floating registers were read system.cpu.num_fp_register_writes 1150968 # number of times the floating registers were written -system.cpu.num_mem_refs 58160248 # number of memory refs -system.cpu.num_load_insts 37275867 # Number of load instructions -system.cpu.num_store_insts 20884381 # Number of store instructions +system.cpu.num_mem_refs 58160261 # number of memory refs +system.cpu.num_load_insts 37275864 # Number of load instructions +system.cpu.num_store_insts 20884397 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 406231752.998000 # Number of busy cycles +system.cpu.num_busy_cycles 406231892.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 12719095 # Number of branches fetched +system.cpu.Branches 12719094 # Number of branches fetched system.cpu.op_class::No_OpClass 11445042 8.40% 8.40% # Class of executed instruction -system.cpu.op_class::IntAlu 66342070 48.68% 57.07% # Class of executed instruction +system.cpu.op_class::IntAlu 66342067 48.68% 57.07% # Class of executed instruction system.cpu.op_class::IntMult 0 0.00% 57.07% # Class of executed instruction system.cpu.op_class::IntDiv 0 0.00% 57.07% # Class of executed instruction system.cpu.op_class::FloatAdd 325584 0.24% 57.31% # Class of executed instruction @@ -91,18 +91,18 @@ system.cpu.op_class::SimdFloatMisc 0 0.00% 57.31% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 57.31% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 57.31% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::MemRead 37296721 27.36% 84.68% # Class of executed instruction -system.cpu.op_class::MemWrite 20884381 15.32% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 37296718 27.36% 84.68% # Class of executed instruction +system.cpu.op_class::MemWrite 20884397 15.32% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 136293798 # Class of executed instruction -system.cpu.dcache.tags.replacements 146582 # number of replacements -system.cpu.dcache.tags.tagsinuse 4087.268920 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 57960842 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 150678 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 384.666919 # Average number of references to valid blocks. +system.cpu.op_class::total 136293808 # Class of executed instruction +system.cpu.dcache.tags.replacements 146583 # number of replacements +system.cpu.dcache.tags.tagsinuse 4087.268923 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 57960841 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 150679 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 384.664359 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 822359500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4087.268920 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 4087.268923 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.997868 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.997868 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id @@ -110,38 +110,38 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0 36 system.cpu.dcache.tags.age_task_id_blocks_1024::1 474 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 3586 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 116373718 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 116373718 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 37185801 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 37185801 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 116373719 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 116373719 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 37185800 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 37185800 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 20759140 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 20759140 # number of WriteReq hits system.cpu.dcache.SwapReq_hits::cpu.data 15901 # number of SwapReq hits system.cpu.dcache.SwapReq_hits::total 15901 # number of SwapReq hits -system.cpu.dcache.demand_hits::cpu.data 57944941 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 57944941 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 57944941 # number of overall hits -system.cpu.dcache.overall_hits::total 57944941 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 45499 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 45499 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 57944940 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 57944940 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 57944940 # number of overall hits +system.cpu.dcache.overall_hits::total 57944940 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 45500 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 45500 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 105164 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 105164 # number of WriteReq misses system.cpu.dcache.SwapReq_misses::cpu.data 15 # number of SwapReq misses system.cpu.dcache.SwapReq_misses::total 15 # number of SwapReq misses -system.cpu.dcache.demand_misses::cpu.data 150663 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 150663 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 150663 # number of overall misses -system.cpu.dcache.overall_misses::total 150663 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 1623254000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 1623254000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 6329554500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 6329554500 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 150664 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 150664 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 150664 # number of overall misses +system.cpu.dcache.overall_misses::total 150664 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 1623315500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 1623315500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 6329554000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 6329554000 # number of WriteReq miss cycles system.cpu.dcache.SwapReq_miss_latency::cpu.data 441000 # number of SwapReq miss cycles system.cpu.dcache.SwapReq_miss_latency::total 441000 # number of SwapReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 7952808500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 7952808500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 7952808500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 7952808500 # number of overall miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 7952869500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 7952869500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 7952869500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 7952869500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 37231300 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 37231300 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 20864304 # number of WriteReq accesses(hits+misses) @@ -162,16 +162,16 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.002593 system.cpu.dcache.demand_miss_rate::total 0.002593 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.002593 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.002593 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 35676.696191 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 35676.696191 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60187.464341 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 60187.464341 # average WriteReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 35677.263736 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 35677.263736 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60187.459587 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 60187.459587 # average WriteReq miss latency system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 29400 # average SwapReq miss latency system.cpu.dcache.SwapReq_avg_miss_latency::total 29400 # average SwapReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 52785.411813 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 52785.411813 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 52785.411813 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 52785.411813 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 52785.466336 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 52785.466336 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 52785.466336 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 52785.466336 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -182,26 +182,26 @@ system.cpu.dcache.fast_writes 0 # nu system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 123865 # number of writebacks system.cpu.dcache.writebacks::total 123865 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 45499 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 45499 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 45500 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 45500 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 105164 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 105164 # number of WriteReq MSHR misses system.cpu.dcache.SwapReq_mshr_misses::cpu.data 15 # number of SwapReq MSHR misses system.cpu.dcache.SwapReq_mshr_misses::total 15 # number of SwapReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 150663 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 150663 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 150663 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 150663 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1577755000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 1577755000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6224390500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 6224390500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 150664 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 150664 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 150664 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 150664 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1577815500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 1577815500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6224390000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 6224390000 # number of WriteReq MSHR miss cycles system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 426000 # number of SwapReq MSHR miss cycles system.cpu.dcache.SwapReq_mshr_miss_latency::total 426000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7802145500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7802145500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7802145500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7802145500 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7802205500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 7802205500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7802205500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7802205500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001222 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001222 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005040 # mshr miss rate for WriteReq accesses @@ -212,24 +212,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002593 system.cpu.dcache.demand_mshr_miss_rate::total 0.002593 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002593 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002593 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34676.696191 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34676.696191 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59187.464341 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59187.464341 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34677.263736 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34677.263736 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59187.459587 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59187.459587 # average WriteReq mshr miss latency system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 28400 # average SwapReq mshr miss latency system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 28400 # average SwapReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51785.411813 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 51785.411813 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51785.411813 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 51785.411813 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51785.466336 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 51785.466336 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51785.466336 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 51785.466336 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 184976 # number of replacements -system.cpu.icache.tags.tagsinuse 2004.181257 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 134366547 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 2004.181265 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 134366557 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 187024 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 718.445478 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 144582729500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 2004.181257 # Average occupied blocks per requestor +system.cpu.icache.tags.avg_refs 718.445531 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 144582800500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 2004.181265 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.978604 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.978604 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 2048 # Occupied blocks per task id @@ -239,14 +239,14 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2 2 system.cpu.icache.tags.age_task_id_blocks_1024::3 456 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1427 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 269294166 # Number of tag accesses -system.cpu.icache.tags.data_accesses 269294166 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 134366547 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 134366547 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 134366547 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 134366547 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 134366547 # number of overall hits -system.cpu.icache.overall_hits::total 134366547 # number of overall hits +system.cpu.icache.tags.tag_accesses 269294186 # Number of tag accesses +system.cpu.icache.tags.data_accesses 269294186 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 134366557 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 134366557 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 134366557 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 134366557 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 134366557 # number of overall hits +system.cpu.icache.overall_hits::total 134366557 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 187024 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 187024 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 187024 # number of demand (read+write) misses @@ -259,12 +259,12 @@ system.cpu.icache.demand_miss_latency::cpu.inst 2835239000 system.cpu.icache.demand_miss_latency::total 2835239000 # number of demand (read+write) miss cycles system.cpu.icache.overall_miss_latency::cpu.inst 2835239000 # number of overall miss cycles system.cpu.icache.overall_miss_latency::total 2835239000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 134553571 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 134553571 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 134553571 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 134553571 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 134553571 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 134553571 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_accesses::cpu.inst 134553581 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 134553581 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 134553581 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 134553581 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 134553581 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 134553581 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001390 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.001390 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.001390 # miss rate for demand accesses @@ -312,19 +312,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 14159.760245 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14159.760245 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 14159.760245 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 99021 # number of replacements -system.cpu.l2cache.tags.tagsinuse 30843.659201 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 433831 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 130064 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 3.335519 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 99022 # number of replacements +system.cpu.l2cache.tags.tagsinuse 30843.699683 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 433832 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 130065 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 3.335501 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 26289.730201 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 3249.863843 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 1304.065157 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.802299 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 26289.169168 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 3249.863620 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 1304.666895 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.802282 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.099178 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.039797 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.941274 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.039815 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.941275 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 31043 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 193 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 566 # Occupied blocks per task id @@ -332,8 +332,8 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::2 11257 system.cpu.l2cache.tags.age_task_id_blocks_1024::3 18470 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 557 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.947357 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 5588795 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 5588795 # Number of data accesses +system.cpu.l2cache.tags.tag_accesses 5588812 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 5588812 # Number of data accesses system.cpu.l2cache.WritebackDirty_hits::writebacks 123865 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 123865 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 184923 # number of WritebackClean hits @@ -354,26 +354,26 @@ system.cpu.l2cache.ReadExReq_misses::cpu.data 101264 system.cpu.l2cache.ReadExReq_misses::total 101264 # number of ReadExReq misses system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 8204 # number of ReadCleanReq misses system.cpu.l2cache.ReadCleanReq_misses::total 8204 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 21053 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 21053 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 21054 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 21054 # number of ReadSharedReq misses system.cpu.l2cache.demand_misses::cpu.inst 8204 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 122317 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 130521 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 122318 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 130522 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 8204 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 122317 # number of overall misses -system.cpu.l2cache.overall_misses::total 130521 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6025890500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 6025890500 # number of ReadExReq miss cycles +system.cpu.l2cache.overall_misses::cpu.data 122318 # number of overall misses +system.cpu.l2cache.overall_misses::total 130522 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6025890000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 6025890000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 488461500 # number of ReadCleanReq miss cycles system.cpu.l2cache.ReadCleanReq_miss_latency::total 488461500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1252774500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 1252774500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1252834000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 1252834000 # number of ReadSharedReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 488461500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7278665000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 7767126500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 7278724000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 7767185500 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 488461500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7278665000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 7767126500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 7278724000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 7767185500 # number of overall miss cycles system.cpu.l2cache.WritebackDirty_accesses::writebacks 123865 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackDirty_accesses::total 123865 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::writebacks 184923 # number of WritebackClean accesses(hits+misses) @@ -382,38 +382,38 @@ system.cpu.l2cache.ReadExReq_accesses::cpu.data 105179 system.cpu.l2cache.ReadExReq_accesses::total 105179 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 187024 # number of ReadCleanReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::total 187024 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 45499 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 45499 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 45500 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 45500 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 187024 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 150678 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 337702 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 150679 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 337703 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 187024 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 150678 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 337702 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 150679 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 337703 # number of overall (read+write) accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.962778 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.962778 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.043866 # miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.043866 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.462713 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.462713 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.462725 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.462725 # miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.043866 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.811777 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.386498 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.811779 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.386499 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.043866 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.811777 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.386498 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59506.739809 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59506.739809 # average ReadExReq miss latency +system.cpu.l2cache.overall_miss_rate::cpu.data 0.811779 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.386499 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59506.734871 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59506.734871 # average ReadExReq miss latency system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59539.431984 # average ReadCleanReq miss latency system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59539.431984 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59505.747399 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59505.747399 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59505.747126 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59505.747126 # average ReadSharedReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59539.431984 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59506.568997 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 59508.634626 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59506.564856 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 59508.630729 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59539.431984 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59506.568997 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 59508.634626 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59506.564856 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 59508.630729 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -430,115 +430,115 @@ system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 101264 system.cpu.l2cache.ReadExReq_mshr_misses::total 101264 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 8204 # number of ReadCleanReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::total 8204 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 21053 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 21053 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 21054 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 21054 # number of ReadSharedReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 8204 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 122317 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 130521 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 122318 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 130522 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 8204 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 122317 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 130521 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5013250500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5013250500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::cpu.data 122318 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 130522 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5013250000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5013250000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 406421500 # number of ReadCleanReq MSHR miss cycles system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 406421500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1042244500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1042244500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1042294000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1042294000 # number of ReadSharedReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 406421500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6055495000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 6461916500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6055544000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 6461965500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 406421500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6055495000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 6461916500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6055544000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 6461965500 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.962778 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.962778 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.043866 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.043866 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.462713 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.462713 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.462725 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.462725 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.043866 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.811777 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.386498 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.811779 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.386499 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.043866 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.811777 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.386498 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49506.739809 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49506.739809 # average ReadExReq mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.811779 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.386499 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49506.734871 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49506.734871 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49539.431984 # average ReadCleanReq mshr miss latency system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49539.431984 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49505.747399 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49505.747399 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49505.747126 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49505.747126 # average ReadSharedReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49539.431984 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49506.568997 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49508.634626 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49506.564856 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49508.630729 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49539.431984 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49506.568997 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49508.634626 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49506.564856 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49508.630729 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 669260 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 331558 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 669262 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 331559 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 66 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 3547 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3547 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadResp 232523 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 232524 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 209135 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 184976 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 36468 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 36470 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 105179 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 105179 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 187024 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 45499 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 45500 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 559024 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 447938 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 1006962 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 447941 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 1006965 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23808000 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 17570752 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 41378752 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 99021 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 436723 # Request fanout histogram +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 17570816 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 41378816 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 99022 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 436725 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 0.008273 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0.090579 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 433110 99.17% 99.17% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 433112 99.17% 99.17% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 3613 0.83% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 436723 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 643471000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 436725 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 643472000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 280536000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 226017000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 226018500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.trans_dist::ReadResp 29257 # Transaction distribution +system.membus.trans_dist::ReadResp 29258 # Transaction distribution system.membus.trans_dist::WritebackDirty 85270 # Transaction distribution -system.membus.trans_dist::CleanEvict 10300 # Transaction distribution +system.membus.trans_dist::CleanEvict 10301 # Transaction distribution system.membus.trans_dist::ReadExReq 101264 # Transaction distribution system.membus.trans_dist::ReadExResp 101264 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 29257 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 356612 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 356612 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13810624 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 13810624 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 29258 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 356615 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 356615 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13810688 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 13810688 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 226091 # Request fanout histogram +system.membus.snoop_fanout::samples 226093 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 226091 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 226093 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 226091 # Request fanout histogram -system.membus.reqLayer0.occupancy 568572500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 226093 # Request fanout histogram +system.membus.reqLayer0.occupancy 568574500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.membus.respLayer1.occupancy 652605000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 652610000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.3 # Layer utilization (%) ---------- End Simulation Statistics ---------- |