diff options
| -rw-r--r-- | src/arch/arm/isa/insts/misc.isa | 19 |
1 files changed, 15 insertions, 4 deletions
diff --git a/src/arch/arm/isa/insts/misc.isa b/src/arch/arm/isa/insts/misc.isa index cf3d0e00f..566ea4b9d 100644 --- a/src/arch/arm/isa/insts/misc.isa +++ b/src/arch/arm/isa/insts/misc.isa @@ -40,15 +40,26 @@ let {{ svcCode = ''' - fault = std::make_shared<SupervisorCall>(machInst, imm); + ThreadContext *tc = xc->tcBase(); + + const auto semihost_imm = Thumb? 0xAB : 0x123456; + + if (ArmSystem::haveSemihosting(tc) && imm == semihost_imm) { + R0 = ArmSystem::callSemihosting32(tc, R0, R1); + } else { + fault = std::make_shared<SupervisorCall>(machInst, imm); + } ''' svcIop = InstObjParams("svc", "Svc", "ImmOp", { "code": svcCode, - "predicate_test": predicateTest }, - ["IsSyscall", "IsNonSpeculative", "IsSerializeAfter"]) + "predicate_test": predicateTest, + "thumb_semihost": '0xAB', + "arm_semihost": '0x123456' }, + ["IsSyscall", "IsNonSpeculative", + "IsSerializeAfter"]) header_output = ImmOpDeclare.subst(svcIop) - decoder_output = ImmOpConstructor.subst(svcIop) + decoder_output = SemihostConstructor.subst(svcIop) exec_output = PredOpExecute.subst(svcIop) smcCode = ''' |