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-rw-r--r--python/m5/objects/AlphaConsole.py6
-rw-r--r--python/m5/objects/BadDevice.py4
-rw-r--r--python/m5/objects/BaseCPU.py4
-rw-r--r--python/m5/objects/Bridge.py9
-rw-r--r--python/m5/objects/Bus.py7
-rw-r--r--python/m5/objects/Device.py33
-rw-r--r--python/m5/objects/Ethernet.py6
-rw-r--r--python/m5/objects/Ide.py1
-rw-r--r--python/m5/objects/MemObject.py5
-rw-r--r--python/m5/objects/Pci.py6
-rw-r--r--python/m5/objects/PhysicalMemory.py6
-rw-r--r--python/m5/objects/Process.py10
-rw-r--r--python/m5/objects/Root.py4
-rw-r--r--python/m5/objects/SimpleDisk.py2
-rw-r--r--python/m5/objects/System.py18
-rw-r--r--python/m5/objects/Tsunami.py14
-rw-r--r--python/m5/objects/Uart.py7
17 files changed, 68 insertions, 74 deletions
diff --git a/python/m5/objects/AlphaConsole.py b/python/m5/objects/AlphaConsole.py
index f8f034682..68e6089ab 100644
--- a/python/m5/objects/AlphaConsole.py
+++ b/python/m5/objects/AlphaConsole.py
@@ -1,9 +1,9 @@
from m5 import *
-from Device import PioDevice
+from Device import BasicPioDevice
-class AlphaConsole(PioDevice):
+class AlphaConsole(BasicPioDevice):
type = 'AlphaConsole'
cpu = Param.BaseCPU(Parent.any, "Processor")
disk = Param.SimpleDisk("Simple Disk")
sim_console = Param.SimConsole(Parent.any, "The Simulator Console")
- system = Param.System(Parent.any, "system object")
+ system = Param.AlphaSystem(Parent.any, "system object")
diff --git a/python/m5/objects/BadDevice.py b/python/m5/objects/BadDevice.py
index 3fba4637d..9cb9a8f03 100644
--- a/python/m5/objects/BadDevice.py
+++ b/python/m5/objects/BadDevice.py
@@ -1,6 +1,6 @@
from m5 import *
-from Device import PioDevice
+from Device import BasicPioDevice
-class BadDevice(PioDevice):
+class BadDevice(BasicPioDevice):
type = 'BadDevice'
devicename = Param.String("Name of device to error on")
diff --git a/python/m5/objects/BaseCPU.py b/python/m5/objects/BaseCPU.py
index a90203729..49cb2a8f3 100644
--- a/python/m5/objects/BaseCPU.py
+++ b/python/m5/objects/BaseCPU.py
@@ -2,13 +2,11 @@ from m5 import *
class BaseCPU(SimObject):
type = 'BaseCPU'
abstract = True
- icache = Param.BaseMem(NULL, "L1 instruction cache object")
- dcache = Param.BaseMem(NULL, "L1 data cache object")
+ mem = Param.MemObject("memory")
if build_env['FULL_SYSTEM']:
dtb = Param.AlphaDTB("Data TLB")
itb = Param.AlphaITB("Instruction TLB")
- mem = Param.FunctionalMemory("memory")
system = Param.System(Parent.any, "system object")
cpu_id = Param.Int(-1, "CPU identifier")
else:
diff --git a/python/m5/objects/Bridge.py b/python/m5/objects/Bridge.py
new file mode 100644
index 000000000..ada715ce9
--- /dev/null
+++ b/python/m5/objects/Bridge.py
@@ -0,0 +1,9 @@
+from m5 import *
+from MemObject import MemObject
+
+class Bridge(MemObject):
+ type = 'Bridge'
+ queue_size_a = Param.Int(16, "The number of requests to buffer")
+ queue_size_b = Param.Int(16, "The number of requests to buffer")
+ delay = Param.Latency('0ns', "The latency of this bridge")
+ write_ack = Param.Bool(False, "Should this bridge ack writes")
diff --git a/python/m5/objects/Bus.py b/python/m5/objects/Bus.py
index 26509d7d2..8c5397281 100644
--- a/python/m5/objects/Bus.py
+++ b/python/m5/objects/Bus.py
@@ -1,7 +1,6 @@
from m5 import *
-from BaseHier import BaseHier
+from MemObject import MemObject
-class Bus(BaseHier):
+class Bus(MemObject):
type = 'Bus'
- clock = Param.Clock("bus frequency")
- width = Param.Int("bus width in bytes")
+ bus_id = Param.Int(0, "blah")
diff --git a/python/m5/objects/Device.py b/python/m5/objects/Device.py
index d7ca014a9..2a71bbc65 100644
--- a/python/m5/objects/Device.py
+++ b/python/m5/objects/Device.py
@@ -1,35 +1,18 @@
from m5 import *
-from FunctionalMemory import FunctionalMemory
+from MemObject import MemObject
-# This device exists only because there are some devices that I don't
-# want to have a Platform parameter because it would cause a cycle in
-# the C++ that cannot be easily solved.
-#
-# The real solution to this problem is to pass the ParamXXX structure
-# to the constructor, but with the express condition that SimObject
-# parameter values are not to be available at construction time. If
-# some further configuration must be done, it must be done during the
-# initialization phase at which point all SimObject pointers will be
-# valid.
-class FooPioDevice(FunctionalMemory):
+class PioDevice(MemObject):
type = 'PioDevice'
abstract = True
- addr = Param.Addr("Device Address")
- mmu = Param.MemoryController(Parent.any, "Memory Controller")
- pio_bus = Param.Bus(NULL, "Bus to attach to for PIO")
- pio_latency = Param.Tick(1, "Programmed IO latency in bus cycles")
+ platform = Param.Platform(Parent.any, "Platform this device is part of")
+ system = Param.System(Parent.any, "System this device is part of")
-class FooDmaDevice(FooPioDevice):
- type = 'DmaDevice'
- abstract = True
- dma_bus = Param.Bus(Self.pio_bus, "Bus to attach to for DMA")
-
-class PioDevice(FooPioDevice):
- type = 'PioDevice'
+class BasicPioDevice(PioDevice):
+ type = 'BasicPioDevice'
abstract = True
- platform = Param.Platform(Parent.any, "Platform")
+ pio_addr = Param.Addr("Device Address")
+ pio_latency = Param.Tick(1, "Programmed IO latency in simticks")
class DmaDevice(PioDevice):
type = 'DmaDevice'
abstract = True
- dma_bus = Param.Bus(Self.pio_bus, "Bus to attach to for DMA")
diff --git a/python/m5/objects/Ethernet.py b/python/m5/objects/Ethernet.py
index 68b21b404..4286c71c8 100644
--- a/python/m5/objects/Ethernet.py
+++ b/python/m5/objects/Ethernet.py
@@ -67,15 +67,10 @@ class EtherDevBase(PciDevice):
clock = Param.Clock('0ns', "State machine processor frequency")
- physmem = Param.PhysicalMemory(Parent.any, "Physical Memory")
-
- hier = Param.HierParams(Parent.any, "Hierarchy global variables")
- payload_bus = Param.Bus(NULL, "The IO Bus to attach to for payload")
dma_read_delay = Param.Latency('0us', "fixed delay for dma reads")
dma_read_factor = Param.Latency('0us', "multiplier for dma reads")
dma_write_delay = Param.Latency('0us', "fixed delay for dma writes")
dma_write_factor = Param.Latency('0us', "multiplier for dma writes")
- dma_no_allocate = Param.Bool(True, "Should we allocate cache on read")
rx_delay = Param.Latency('1us', "Receive Delay")
tx_delay = Param.Latency('1us', "Transmit Delay")
@@ -93,6 +88,7 @@ class NSGigE(EtherDevBase):
dma_data_free = Param.Bool(False, "DMA of Data is free")
dma_desc_free = Param.Bool(False, "DMA of Descriptors is free")
+ dma_no_allocate = Param.Bool(True, "Should we allocate cache on read")
class NSGigEInt(EtherInt):
diff --git a/python/m5/objects/Ide.py b/python/m5/objects/Ide.py
index 6855ec653..2403e6d36 100644
--- a/python/m5/objects/Ide.py
+++ b/python/m5/objects/Ide.py
@@ -8,7 +8,6 @@ class IdeDisk(SimObject):
delay = Param.Latency('1us', "Fixed disk delay in microseconds")
driveID = Param.IdeID('master', "Drive ID")
image = Param.DiskImage("Disk image")
- physmem = Param.PhysicalMemory(Parent.any, "Physical memory")
class IdeController(PciDevice):
type = 'IdeController'
diff --git a/python/m5/objects/MemObject.py b/python/m5/objects/MemObject.py
new file mode 100644
index 000000000..4d68243e6
--- /dev/null
+++ b/python/m5/objects/MemObject.py
@@ -0,0 +1,5 @@
+from m5 import *
+
+class MemObject(SimObject):
+ type = 'MemObject'
+ abstract = True
diff --git a/python/m5/objects/Pci.py b/python/m5/objects/Pci.py
index 4124d0b92..85cefcd44 100644
--- a/python/m5/objects/Pci.py
+++ b/python/m5/objects/Pci.py
@@ -1,5 +1,5 @@
from m5 import *
-from Device import FooPioDevice, DmaDevice
+from Device import BasicPioDevice, DmaDevice
class PciConfigData(SimObject):
type = 'PciConfigData'
@@ -38,16 +38,16 @@ class PciConfigData(SimObject):
MaximumLatency = Param.UInt8(0x00, "Maximum Latency")
MinimumGrant = Param.UInt8(0x00, "Minimum Grant")
-class PciConfigAll(FooPioDevice):
+class PciConfigAll(BasicPioDevice):
type = 'PciConfigAll'
class PciDevice(DmaDevice):
type = 'PciDevice'
abstract = True
- addr = 0xffffffffL
pci_bus = Param.Int("PCI bus")
pci_dev = Param.Int("PCI device number")
pci_func = Param.Int("PCI function code")
+ pio_latency = Param.Tick(1, "Programmed IO latency in simticks")
configdata = Param.PciConfigData(Parent.any, "PCI Config data")
configspace = Param.PciConfigAll(Parent.any, "PCI Configspace")
diff --git a/python/m5/objects/PhysicalMemory.py b/python/m5/objects/PhysicalMemory.py
index f50937ee6..e59e94e9b 100644
--- a/python/m5/objects/PhysicalMemory.py
+++ b/python/m5/objects/PhysicalMemory.py
@@ -1,8 +1,8 @@
from m5 import *
-from FunctionalMemory import FunctionalMemory
+from MemObject import *
-class PhysicalMemory(FunctionalMemory):
+class PhysicalMemory(MemObject):
type = 'PhysicalMemory'
range = Param.AddrRange("Device Address")
file = Param.String('', "memory mapped file")
- mmu = Param.MemoryController(Parent.any, "Memory Controller")
+ latency = Param.Latency('10ns', "latency of an access")
diff --git a/python/m5/objects/Process.py b/python/m5/objects/Process.py
index b4ccc1bec..60b00229e 100644
--- a/python/m5/objects/Process.py
+++ b/python/m5/objects/Process.py
@@ -3,6 +3,7 @@ class Process(SimObject):
type = 'Process'
abstract = True
output = Param.String('cout', 'filename for stdout/stderr')
+ system = Param.System(Parent.any, "system process will run on")
class LiveProcess(Process):
type = 'LiveProcess'
@@ -11,6 +12,15 @@ class LiveProcess(Process):
env = VectorParam.String('', "environment settings")
input = Param.String('cin', "filename for stdin")
+class AlphaLiveProcess(LiveProcess):
+ type = 'AlphaLiveProcess'
+
+class SparcLiveProcess(LiveProcess):
+ type = 'SparcLiveProcess'
+
+class MipsLiveProcess(LiveProcess):
+ type = 'MipsLiveProcess'
+
class EioProcess(Process):
type = 'EioProcess'
chkpt = Param.String('', "EIO checkpoint file name (optional)")
diff --git a/python/m5/objects/Root.py b/python/m5/objects/Root.py
index 23b13fc67..f51516098 100644
--- a/python/m5/objects/Root.py
+++ b/python/m5/objects/Root.py
@@ -1,5 +1,4 @@
from m5 import *
-from HierParams import HierParams
from Serialize import Serialize
from Statistics import Statistics
from Trace import Trace
@@ -13,12 +12,9 @@ class Root(SimObject):
"print a progress message every n ticks (0 = never)")
output_file = Param.String('cout', "file to dump simulator output to")
checkpoint = Param.String('', "checkpoint file to load")
-# hier = Param.HierParams(HierParams(do_data = False, do_events = True),
-# "shared memory hierarchy parameters")
# stats = Param.Statistics(Statistics(), "statistics object")
# trace = Param.Trace(Trace(), "trace object")
# serialize = Param.Serialize(Serialize(), "checkpoint generation options")
- hier = HierParams(do_data = False, do_events = True)
stats = Statistics()
trace = Trace()
exetrace = ExecutionTrace()
diff --git a/python/m5/objects/SimpleDisk.py b/python/m5/objects/SimpleDisk.py
index 48448e6e5..e34155ace 100644
--- a/python/m5/objects/SimpleDisk.py
+++ b/python/m5/objects/SimpleDisk.py
@@ -2,4 +2,4 @@ from m5 import *
class SimpleDisk(SimObject):
type = 'SimpleDisk'
disk = Param.DiskImage("Disk Image")
- physmem = Param.PhysicalMemory(Parent.any, "Physical Memory")
+ system = Param.System(Parent.any, "Sysetm Pointer")
diff --git a/python/m5/objects/System.py b/python/m5/objects/System.py
index 5925cadf5..622b5a870 100644
--- a/python/m5/objects/System.py
+++ b/python/m5/objects/System.py
@@ -2,20 +2,20 @@ from m5 import *
class System(SimObject):
type = 'System'
- boot_cpu_frequency = Param.Frequency(Self.cpu[0].clock.frequency,
- "boot processor frequency")
- memctrl = Param.MemoryController(Parent.any, "memory controller")
physmem = Param.PhysicalMemory(Parent.any, "phsyical memory")
- init_param = Param.UInt64(0, "numerical value to pass into simulator")
- bin = Param.Bool(False, "is this system binned")
- binned_fns = VectorParam.String([], "functions broken down and binned")
- kernel = Param.String("file that contains the kernel code")
- readfile = Param.String("", "file to read startup script from")
+ if build_env['FULL_SYSTEM']:
+ boot_cpu_frequency = Param.Frequency(Self.cpu[0].clock.frequency,
+ "boot processor frequency")
+ init_param = Param.UInt64(0, "numerical value to pass into simulator")
+ bin = Param.Bool(False, "is this system binned")
+ binned_fns = VectorParam.String([], "functions broken down and binned")
+ boot_osflags = Param.String("a", "boot flags to pass to the kernel")
+ kernel = Param.String("file that contains the kernel code")
+ readfile = Param.String("", "file to read startup script from")
class AlphaSystem(System):
type = 'AlphaSystem'
console = Param.String("file that contains the console code")
pal = Param.String("file that contains palcode")
- boot_osflags = Param.String("a", "boot flags to pass to the kernel")
system_type = Param.UInt64("Type of system we are emulating")
system_rev = Param.UInt64("Revision of system we are emulating")
diff --git a/python/m5/objects/Tsunami.py b/python/m5/objects/Tsunami.py
index 5425f421f..27ea0bce8 100644
--- a/python/m5/objects/Tsunami.py
+++ b/python/m5/objects/Tsunami.py
@@ -1,27 +1,27 @@
from m5 import *
-from Device import FooPioDevice
+from Device import BasicPioDevice
from Platform import Platform
class Tsunami(Platform):
type = 'Tsunami'
- pciconfig = Param.PciConfigAll("PCI configuration")
+# pciconfig = Param.PciConfigAll("PCI configuration")
system = Param.System(Parent.any, "system")
-class TsunamiCChip(FooPioDevice):
+class TsunamiCChip(BasicPioDevice):
type = 'TsunamiCChip'
tsunami = Param.Tsunami(Parent.any, "Tsunami")
-class IsaFake(FooPioDevice):
+class IsaFake(BasicPioDevice):
type = 'IsaFake'
- size = Param.Addr("Size of address range")
+ pio_size = Param.Addr(0x8, "Size of address range")
-class TsunamiIO(FooPioDevice):
+class TsunamiIO(BasicPioDevice):
type = 'TsunamiIO'
time = Param.UInt64(1136073600,
"System time to use (0 for actual time, default is 1/1/06)")
tsunami = Param.Tsunami(Parent.any, "Tsunami")
frequency = Param.Frequency('1024Hz', "frequency of interrupts")
-class TsunamiPChip(FooPioDevice):
+class TsunamiPChip(BasicPioDevice):
type = 'TsunamiPChip'
tsunami = Param.Tsunami(Parent.any, "Tsunami")
diff --git a/python/m5/objects/Uart.py b/python/m5/objects/Uart.py
index 6eda5cdb3..54754aeb9 100644
--- a/python/m5/objects/Uart.py
+++ b/python/m5/objects/Uart.py
@@ -1,11 +1,10 @@
from m5 import *
-from Device import PioDevice
+from Device import BasicPioDevice
-class Uart(PioDevice):
+class Uart(BasicPioDevice):
type = 'Uart'
abstract = True
- console = Param.SimConsole(Parent.any, "The console")
- size = Param.Addr(0x8, "Device size")
+ sim_console = Param.SimConsole(Parent.any, "The console")
class Uart8250(Uart):
type = 'Uart8250'
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-14 11:59:09 +0000