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-rw-r--r--src/arch/alpha/AlphaTLB.py8
-rw-r--r--src/arch/alpha/tlb.cc13
-rw-r--r--src/arch/alpha/tlb.hh6
3 files changed, 14 insertions, 13 deletions
diff --git a/src/arch/alpha/AlphaTLB.py b/src/arch/alpha/AlphaTLB.py
index cdee54d26..51f636ec2 100644
--- a/src/arch/alpha/AlphaTLB.py
+++ b/src/arch/alpha/AlphaTLB.py
@@ -34,4 +34,10 @@ from BaseTLB import BaseTLB
class AlphaTLB(BaseTLB):
type = 'AlphaTLB'
cxx_class = 'AlphaISA::TLB'
- size = Param.Int(64, "TLB size")
+ size = Param.Int("TLB size")
+
+class AlphaDTB(AlphaTLB):
+ size = 64
+
+class AlphaITB(AlphaTLB):
+ size = 48
diff --git a/src/arch/alpha/tlb.cc b/src/arch/alpha/tlb.cc
index d20a0adc2..d4f31b421 100644
--- a/src/arch/alpha/tlb.cc
+++ b/src/arch/alpha/tlb.cc
@@ -607,23 +607,20 @@ TLB::index(bool advance)
}
Fault
-TLB::translateAtomic(RequestPtr req, ThreadContext *tc,
- bool write, bool execute)
+TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode)
{
- if (execute)
+ if (mode == Execute)
return translateInst(req, tc);
else
- return translateData(req, tc, write);
+ return translateData(req, tc, mode == Write);
}
void
TLB::translateTiming(RequestPtr req, ThreadContext *tc,
- Translation *translation,
- bool write, bool execute)
+ Translation *translation, Mode mode)
{
assert(translation);
- translation->finish(translateAtomic(req, tc, write, execute),
- req, tc, write, execute);
+ translation->finish(translateAtomic(req, tc, mode), req, tc, mode);
}
/* end namespace AlphaISA */ }
diff --git a/src/arch/alpha/tlb.hh b/src/arch/alpha/tlb.hh
index 292ba15f4..b84c26451 100644
--- a/src/arch/alpha/tlb.hh
+++ b/src/arch/alpha/tlb.hh
@@ -141,11 +141,9 @@ class TLB : public BaseTLB
Fault translateInst(RequestPtr req, ThreadContext *tc);
public:
- Fault translateAtomic(RequestPtr req, ThreadContext *tc,
- bool write = false, bool execute = false);
+ Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode);
void translateTiming(RequestPtr req, ThreadContext *tc,
- Translation *translation,
- bool write = false, bool execute = false);
+ Translation *translation, Mode mode);
};
} // namespace AlphaISA