diff options
Diffstat (limited to 'src/arch/arm/isa')
-rw-r--r-- | src/arch/arm/isa/formats/aarch64.isa | 29 | ||||
-rw-r--r-- | src/arch/arm/isa/formats/neon64.isa | 38 | ||||
-rw-r--r-- | src/arch/arm/isa/includes.isa | 1 | ||||
-rw-r--r-- | src/arch/arm/isa/insts/neon64.isa | 19 |
4 files changed, 62 insertions, 25 deletions
diff --git a/src/arch/arm/isa/formats/aarch64.isa b/src/arch/arm/isa/formats/aarch64.isa index b5a4dfa21..2d94aff51 100644 --- a/src/arch/arm/isa/formats/aarch64.isa +++ b/src/arch/arm/isa/formats/aarch64.isa @@ -1,4 +1,4 @@ -// Copyright (c) 2011-2014 ARM Limited +// Copyright (c) 2011-2015 ARM Limited // All rights reserved // // The license below extends only to copyright in the software and shall @@ -46,8 +46,10 @@ namespace Aarch64 StaticInstPtr decodeLoadsStores(ExtMachInst machInst); StaticInstPtr decodeDataProcReg(ExtMachInst machInst); + template <typename DecoderFeatures> StaticInstPtr decodeFpAdvSIMD(ExtMachInst machInst); StaticInstPtr decodeFp(ExtMachInst machInst); + template <typename DecoderFeatures> StaticInstPtr decodeAdvSIMD(ExtMachInst machInst); StaticInstPtr decodeAdvSIMDScalar(ExtMachInst machInst); @@ -1278,12 +1280,13 @@ namespace Aarch64 output decoder {{ namespace Aarch64 { + template <typename DecoderFeatures> StaticInstPtr decodeAdvSIMD(ExtMachInst machInst) { if (bits(machInst, 24) == 1) { if (bits(machInst, 10) == 0) { - return decodeNeonIndexedElem(machInst); + return decodeNeonIndexedElem<DecoderFeatures>(machInst); } else if (bits(machInst, 23) == 1) { return new Unknown64(machInst); } else { @@ -1295,7 +1298,7 @@ namespace Aarch64 } } else if (bits(machInst, 21) == 1) { if (bits(machInst, 10) == 1) { - return decodeNeon3Same(machInst); + return decodeNeon3Same<DecoderFeatures>(machInst); } else if (bits(machInst, 11) == 0) { return decodeNeon3Diff(machInst); } else if (bits(machInst, 20, 17) == 0x0) { @@ -1957,13 +1960,14 @@ namespace Aarch64 output decoder {{ namespace Aarch64 { + template <typename DecoderFeatures> StaticInstPtr decodeFpAdvSIMD(ExtMachInst machInst) { if (bits(machInst, 28) == 0) { if (bits(machInst, 31) == 0) { - return decodeAdvSIMD(machInst); + return decodeAdvSIMD<DecoderFeatures>(machInst); } else { return new Unknown64(machInst); } @@ -1978,6 +1982,18 @@ namespace Aarch64 } }}; +let {{ + decoder_output =''' +namespace Aarch64 +{''' + for decoderFlavour, type_dict in decoders.iteritems(): + decoder_output +=''' +template StaticInstPtr decodeFpAdvSIMD<%(df)sDecoder>(ExtMachInst machInst); +''' % { "df" : decoderFlavour } + decoder_output +=''' +}''' +}}; + output decoder {{ namespace Aarch64 { @@ -2041,7 +2057,10 @@ def format Aarch64() {{ return decodeGem5Ops(machInst); } else { // bit 27:25=111 - return decodeFpAdvSIMD(machInst); + switch(decoderFlavour){ + default: + return decodeFpAdvSIMD<GenericDecoder>(machInst); + } } } ''' diff --git a/src/arch/arm/isa/formats/neon64.isa b/src/arch/arm/isa/formats/neon64.isa index 72bbd0c60..e0a913a6b 100644 --- a/src/arch/arm/isa/formats/neon64.isa +++ b/src/arch/arm/isa/formats/neon64.isa @@ -40,51 +40,54 @@ output header {{ namespace Aarch64 { // AdvSIMD three same + template <typename DecoderFeatures> StaticInstPtr decodeNeon3Same(ExtMachInst machInst); // AdvSIMD three different - StaticInstPtr decodeNeon3Diff(ExtMachInst machInst); + inline StaticInstPtr decodeNeon3Diff(ExtMachInst machInst); // AdvSIMD two-reg misc - StaticInstPtr decodeNeon2RegMisc(ExtMachInst machInst); + inline StaticInstPtr decodeNeon2RegMisc(ExtMachInst machInst); // AdvSIMD across lanes - StaticInstPtr decodeNeonAcrossLanes(ExtMachInst machInst); + inline StaticInstPtr decodeNeonAcrossLanes(ExtMachInst machInst); // AdvSIMD copy - StaticInstPtr decodeNeonCopy(ExtMachInst machInst); + inline StaticInstPtr decodeNeonCopy(ExtMachInst machInst); // AdvSIMD vector x indexed element + template <typename DecoderFeatures> StaticInstPtr decodeNeonIndexedElem(ExtMachInst machInst); // AdvSIMD modified immediate - StaticInstPtr decodeNeonModImm(ExtMachInst machInst); + inline StaticInstPtr decodeNeonModImm(ExtMachInst machInst); // AdvSIMD shift by immediate - StaticInstPtr decodeNeonShiftByImm(ExtMachInst machInst); + inline StaticInstPtr decodeNeonShiftByImm(ExtMachInst machInst); // AdvSIMD TBL/TBX - StaticInstPtr decodeNeonTblTbx(ExtMachInst machInst); + inline StaticInstPtr decodeNeonTblTbx(ExtMachInst machInst); // AdvSIMD ZIP/UZP/TRN - StaticInstPtr decodeNeonZipUzpTrn(ExtMachInst machInst); + inline StaticInstPtr decodeNeonZipUzpTrn(ExtMachInst machInst); // AdvSIMD EXT - StaticInstPtr decodeNeonExt(ExtMachInst machInst); + inline StaticInstPtr decodeNeonExt(ExtMachInst machInst); // AdvSIMD scalar three same - StaticInstPtr decodeNeonSc3Same(ExtMachInst machInst); + inline StaticInstPtr decodeNeonSc3Same(ExtMachInst machInst); // AdvSIMD scalar three different - StaticInstPtr decodeNeonSc3Diff(ExtMachInst machInst); + inline StaticInstPtr decodeNeonSc3Diff(ExtMachInst machInst); // AdvSIMD scalar two-reg misc - StaticInstPtr decodeNeonSc2RegMisc(ExtMachInst machInst); + inline StaticInstPtr decodeNeonSc2RegMisc(ExtMachInst machInst); // AdvSIMD scalar pairwise - StaticInstPtr decodeNeonScPwise(ExtMachInst machInst); + inline StaticInstPtr decodeNeonScPwise(ExtMachInst machInst); // AdvSIMD scalar copy - StaticInstPtr decodeNeonScCopy(ExtMachInst machInst); + inline StaticInstPtr decodeNeonScCopy(ExtMachInst machInst); // AdvSIMD scalar x indexed element - StaticInstPtr decodeNeonScIndexedElem(ExtMachInst machInst); + inline StaticInstPtr decodeNeonScIndexedElem(ExtMachInst machInst); // AdvSIMD scalar shift by immediate - StaticInstPtr decodeNeonScShiftByImm(ExtMachInst machInst); + inline StaticInstPtr decodeNeonScShiftByImm(ExtMachInst machInst); // AdvSIMD load/store - StaticInstPtr decodeNeonMem(ExtMachInst machInst); + inline StaticInstPtr decodeNeonMem(ExtMachInst machInst); } }}; output decoder {{ namespace Aarch64 { + template <typename DecoderFeatures> StaticInstPtr decodeNeon3Same(ExtMachInst machInst) { @@ -1267,6 +1270,7 @@ namespace Aarch64 } } + template <typename DecoderFeatures> StaticInstPtr decodeNeonIndexedElem(ExtMachInst machInst) { diff --git a/src/arch/arm/isa/includes.isa b/src/arch/arm/isa/includes.isa index 8f44e7e86..4fa032f55 100644 --- a/src/arch/arm/isa/includes.isa +++ b/src/arch/arm/isa/includes.isa @@ -67,6 +67,7 @@ output header {{ #include "arch/arm/isa_traits.hh" #include "mem/packet.hh" #include "sim/faults.hh" +#include "enums/DecoderFlavour.hh" }}; output decoder {{ diff --git a/src/arch/arm/isa/insts/neon64.isa b/src/arch/arm/isa/insts/neon64.isa index f6565efe5..697ea80e2 100644 --- a/src/arch/arm/isa/insts/neon64.isa +++ b/src/arch/arm/isa/insts/neon64.isa @@ -1,6 +1,6 @@ // -*- mode: c++ -*- -// Copyright (c) 2012-2013 ARM Limited +// Copyright (c) 2012-2013, 2015 ARM Limited // All rights reserved // // The license below extends only to copyright in the software and shall @@ -42,6 +42,7 @@ let {{ header_output = "" exec_output = "" + decoders = { 'Generic' : {} } # FP types (FP operations always work with unsigned representations) floatTypes = ("uint32_t", "uint64_t") @@ -49,9 +50,9 @@ let {{ def threeEqualRegInstX(name, Name, opClass, types, rCount, op, readDest=False, pairwise=False, scalar=False, - byElem=False): + byElem=False, decoder='Generic'): assert (not pairwise) or ((not byElem) and (not scalar)) - global header_output, exec_output + global header_output, exec_output, decoders eWalkCode = simd64EnabledCheckCode + ''' RegVect srcReg1, destReg; ''' @@ -3356,4 +3357,16 @@ let {{ threeRegScrambleInstX("zip2", "Zip2QX", "SimdAluOp", unsignedTypes, 4, zipCode % "eCount / 2") + for decoderFlavour, type_dict in decoders.iteritems(): + header_output += ''' + class %(decoder_flavour)sDecoder { + public: + ''' % { "decoder_flavour" : decoderFlavour } + for type,name in type_dict.iteritems(): + header_output += ''' + template<typename Elem> using %(type)s = %(new_name)s<Elem>;''' % { + "type" : type, "new_name" : name + } + header_output += ''' + };''' }}; |