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-rw-r--r--src/arch/mips/MipsTLB.py17
1 files changed, 7 insertions, 10 deletions
diff --git a/src/arch/mips/MipsTLB.py b/src/arch/mips/MipsTLB.py
index ce8847365..41d46c572 100644
--- a/src/arch/mips/MipsTLB.py
+++ b/src/arch/mips/MipsTLB.py
@@ -32,28 +32,25 @@
from m5.SimObject import SimObject
from m5.params import *
-class MipsTLB(SimObject):
- abstract = True
+from BaseTLB import BaseTLB
+
+class MipsTLB(BaseTLB):
type = 'MipsTLB'
- cxx_namespace = 'MipsISA'
- cxx_class = 'TLB'
+ abstract = True
size = Param.Int("TLB size")
class MipsDTB(MipsTLB):
type = 'MipsDTB'
- cxx_namespace = 'MipsISA'
- cxx_class = 'DTB'
+ cxx_class = 'MipsISA::DTB'
size = 64
class MipsITB(MipsTLB):
type = 'MipsITB'
- cxx_namespace = 'MipsISA'
- cxx_class = 'ITB'
+ cxx_class = 'MipsISA::ITB'
size = 64
class MipsUTB(MipsTLB):
type = 'MipsUTB'
- cxx_namespace = 'MipsISA'
- cxx_class = 'UTB'
+ cxx_class = 'MipsISA::UTB'
size = 64