3 files changed, 11 insertions, 2 deletions
diff --git a/src/arch/mips/MipsISA.py b/src/arch/mips/MipsISA.py
index bc969a906..22602ff0c 100644
--- a/src/arch/mips/MipsISA.py
+++ b/src/arch/mips/MipsISA.py
@@ -37,11 +37,14 @@
 
 from m5.SimObject import SimObject
 from m5.params import *
+from m5.proxy import *
 
 class MipsISA(SimObject):
     type = 'MipsISA'
     cxx_class = 'MipsISA::ISA'
     cxx_header = "arch/mips/isa.hh"
 
+    system = Param.System(Parent.any, "System this ISA object belongs to")
+
     num_threads = Param.UInt8(1, "Maximum number this ISA can handle")
     num_vpes = Param.UInt8(1, "Maximum number of vpes this ISA can handle")
diff --git a/src/arch/mips/isa.cc b/src/arch/mips/isa.cc
index 891ed5e2f..164f10d5d 100644
--- a/src/arch/mips/isa.cc
+++ b/src/arch/mips/isa.cc
@@ -89,8 +89,7 @@ ISA::miscRegNames[NumMiscRegs] =
 };
 
 ISA::ISA(Params *p)
-    : SimObject(p),
-      numThreads(p->num_threads), numVpes(p->num_vpes)
+    : SimObject(p), numThreads(p->num_threads), numVpes(p->num_vpes)
 {
     miscRegFile.resize(NumMiscRegs);
     bankType.resize(NumMiscRegs);
diff --git a/src/arch/mips/isa.hh b/src/arch/mips/isa.hh
index c601cfc1e..eddf75272 100644
--- a/src/arch/mips/isa.hh
+++ b/src/arch/mips/isa.hh
@@ -184,6 +184,13 @@ namespace MipsISA
         {
             return reg;
         }
+
+        int
+        flattenMiscIndex(int reg)
+        {
+            return reg;
+        }
+
     };
 }