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-rwxr-xr-xsrc/arch/mips/BISystem.py11
-rw-r--r--src/arch/mips/MipsSystem.py26
-rw-r--r--src/arch/mips/SConscript35
-rwxr-xr-xsrc/arch/mips/dsp.cc1
-rwxr-xr-xsrc/arch/mips/dsp.hh1
-rw-r--r--src/arch/mips/faults.cc7
-rw-r--r--src/arch/mips/faults.hh7
-rwxr-xr-xsrc/arch/mips/interrupts.cc1
-rw-r--r--src/arch/mips/isa/decoder.isa10
-rw-r--r--src/arch/mips/isa/formats/control.isa18
-rwxr-xr-xsrc/arch/mips/isa/formats/dsp.isa4
-rw-r--r--src/arch/mips/isa/formats/fp.isa4
-rw-r--r--src/arch/mips/isa/formats/unimp.isa6
-rw-r--r--src/arch/mips/isa/includes.isa2
-rw-r--r--src/arch/mips/isa_traits.hh2
-rw-r--r--src/arch/mips/linux/system.cc92
-rwxr-xr-xsrc/arch/mips/mips_core_specific.cc46
-rw-r--r--src/arch/mips/mips_core_specific.hh42
-rwxr-xr-xsrc/arch/mips/pagetable.hh53
-rw-r--r--src/arch/mips/remote_gdb.cc10
-rw-r--r--src/arch/mips/stacktrace.cc1
-rwxr-xr-xsrc/arch/mips/system.cc67
-rwxr-xr-xsrc/arch/mips/system.hh7
-rw-r--r--src/arch/mips/tlb.cc161
-rw-r--r--src/arch/mips/tlb.hh27
-rw-r--r--src/arch/mips/utility.cc31
-rw-r--r--src/arch/mips/utility.hh2
-rwxr-xr-xsrc/arch/mips/vtophys.cc20
-rw-r--r--src/arch/mips/vtophys.hh18
29 files changed, 122 insertions, 590 deletions
diff --git a/src/arch/mips/BISystem.py b/src/arch/mips/BISystem.py
index a6e4091f2..d5e02485e 100755
--- a/src/arch/mips/BISystem.py
+++ b/src/arch/mips/BISystem.py
@@ -32,10 +32,9 @@ from m5.defines import buildEnv
from System import *
-if buildEnv['FULL_SYSTEM']:
- class BareIronMipsSystem(MipsSystem):
- type = 'BareIronMipsSystem'
- system_type = 34
- system_rev = 1 << 10
- hex_file_name = Param.String('test.hex',"hex file that contains [address,data] pairs")
+class BareIronMipsSystem(MipsSystem):
+ type = 'BareIronMipsSystem'
+ system_type = 34
+ system_rev = 1 << 10
+ hex_file_name = Param.String('test.hex',"hex file that contains [address,data] pairs")
diff --git a/src/arch/mips/MipsSystem.py b/src/arch/mips/MipsSystem.py
index fc4f1efa3..4a0851eba 100644
--- a/src/arch/mips/MipsSystem.py
+++ b/src/arch/mips/MipsSystem.py
@@ -43,16 +43,18 @@ class MipsSystem(System):
system_rev = Param.UInt64("Revision of system we are emulating")
load_addr_mask = 0xffffffffff
-if buildEnv['FULL_SYSTEM']:
- class LinuxMipsSystem(MipsSystem):
- type = 'LinuxMipsSystem'
- system_type = 34
- system_rev = 1 << 10
-
- class BareIronMipsSystem(MipsSystem):
- type = 'BareIronMipsSystem'
- bare_iron = True
- system_type = 34
- system_rev = 1 << 10
- hex_file_name = Param.String('test.hex',"hex file that contains [address,data] pairs")
+class LinuxMipsSystem(MipsSystem):
+ type = 'LinuxMipsSystem'
+ system_type = 34
+ system_rev = 1 << 10
+
+ boot_cpu_frequency = Param.Frequency(Self.cpu[0].clock.frequency,
+ "boot processor frequency")
+
+class BareIronMipsSystem(MipsSystem):
+ type = 'BareIronMipsSystem'
+ bare_iron = True
+ system_type = 34
+ system_rev = 1 << 10
+ hex_file_name = Param.String('test.hex',"hex file that contains [address,data] pairs")
diff --git a/src/arch/mips/SConscript b/src/arch/mips/SConscript
index 9fc2b71ff..7e2d4b806 100644
--- a/src/arch/mips/SConscript
+++ b/src/arch/mips/SConscript
@@ -33,32 +33,29 @@
Import('*')
if env['TARGET_ISA'] == 'mips':
+ Source('bare_iron/system.cc')
+ Source('dsp.cc')
Source('faults.cc')
+ Source('idle_event.cc')
+ Source('interrupts.cc')
Source('isa.cc')
- Source('tlb.cc')
+ Source('linux/linux.cc')
+ Source('linux/process.cc')
+ Source('linux/system.cc')
Source('pagetable.cc')
- Source('utility.cc')
- Source('dsp.cc')
+ Source('process.cc')
Source('remote_gdb.cc')
+ Source('stacktrace.cc')
+ Source('system.cc')
+ Source('tlb.cc')
+ Source('utility.cc')
+ Source('vtophys.cc')
+ SimObject('MipsInterrupts.py')
+ SimObject('MipsSystem.py')
SimObject('MipsTLB.py')
- DebugFlag('MipsPRA')
- if env['FULL_SYSTEM']:
- SimObject('MipsSystem.py')
- SimObject('MipsInterrupts.py')
- Source('idle_event.cc')
- Source('mips_core_specific.cc')
- Source('vtophys.cc')
- Source('system.cc')
- Source('stacktrace.cc')
- Source('linux/system.cc')
- Source('interrupts.cc')
- Source('bare_iron/system.cc')
- else:
- Source('process.cc')
- Source('linux/linux.cc')
- Source('linux/process.cc')
+ DebugFlag('MipsPRA')
# Add in files generated by the ISA description.
isa_desc_files = env.ISADesc('isa/main.isa')
diff --git a/src/arch/mips/dsp.cc b/src/arch/mips/dsp.cc
index 49698eec6..3f6c6866e 100755
--- a/src/arch/mips/dsp.cc
+++ b/src/arch/mips/dsp.cc
@@ -32,7 +32,6 @@
#include "arch/mips/isa_traits.hh"
#include "base/bitfield.hh"
#include "base/misc.hh"
-#include "config/full_system.hh"
#include "cpu/static_inst.hh"
#include "sim/serialize.hh"
diff --git a/src/arch/mips/dsp.hh b/src/arch/mips/dsp.hh
index f13431714..0e9424f38 100755
--- a/src/arch/mips/dsp.hh
+++ b/src/arch/mips/dsp.hh
@@ -35,7 +35,6 @@
#include "arch/mips/types.hh"
#include "base/misc.hh"
#include "base/types.hh"
-#include "config/full_system.hh"
class ThreadContext;
diff --git a/src/arch/mips/faults.cc b/src/arch/mips/faults.cc
index 00471aece..3076e0afe 100644
--- a/src/arch/mips/faults.cc
+++ b/src/arch/mips/faults.cc
@@ -39,11 +39,8 @@
#include "cpu/base.hh"
#include "cpu/thread_context.hh"
#include "debug/MipsPRA.hh"
-
-#if !FULL_SYSTEM
#include "mem/page_table.hh"
#include "sim/process.hh"
-#endif
namespace MipsISA
{
@@ -136,7 +133,7 @@ MipsFaultBase::setExceptionState(ThreadContext *tc, uint8_t excCode)
void
MipsFaultBase::invoke(ThreadContext *tc, StaticInstPtr inst)
{
- if (FULL_SYSTEM) {
+ if (FullSystem) {
DPRINTF(MipsPRA, "Fault %s encountered.\n", name());
setExceptionState(tc, code());
tc->pcState(vect(tc));
@@ -148,7 +145,7 @@ MipsFaultBase::invoke(ThreadContext *tc, StaticInstPtr inst)
void
ResetFault::invoke(ThreadContext *tc, StaticInstPtr inst)
{
- if (FULL_SYSTEM) {
+ if (FullSystem) {
DPRINTF(MipsPRA, "%s encountered.\n", name());
/* All reset activity must be invoked from here */
Addr handler = vect(tc);
diff --git a/src/arch/mips/faults.hh b/src/arch/mips/faults.hh
index 76d4fff23..b90c38e99 100644
--- a/src/arch/mips/faults.hh
+++ b/src/arch/mips/faults.hh
@@ -40,6 +40,7 @@
#include "cpu/thread_context.hh"
#include "debug/MipsPRA.hh"
#include "sim/faults.hh"
+#include "sim/full_system.hh"
namespace MipsISA
{
@@ -165,7 +166,7 @@ class CoprocessorUnusableFault : public MipsFault<CoprocessorUnusableFault>
StaticInstPtr inst = StaticInst::nullStaticInstPtr)
{
MipsFault<CoprocessorUnusableFault>::invoke(tc, inst);
- if (FULL_SYSTEM) {
+ if (FullSystem) {
CauseReg cause = tc->readMiscReg(MISCREG_CAUSE);
cause.ce = coProcID;
tc->setMiscRegNoEffect(MISCREG_CAUSE, cause);
@@ -200,7 +201,7 @@ class AddressFault : public MipsFault<T>
StaticInstPtr inst = StaticInst::nullStaticInstPtr)
{
MipsFault<T>::invoke(tc, inst);
- if (FULL_SYSTEM)
+ if (FullSystem)
tc->setMiscRegNoEffect(MISCREG_BADVADDR, vaddr);
}
};
@@ -252,7 +253,7 @@ class TlbFault : public AddressFault<T>
invoke(ThreadContext * tc,
StaticInstPtr inst = StaticInst::nullStaticInstPtr)
{
- if (FULL_SYSTEM) {
+ if (FullSystem) {
DPRINTF(MipsPRA, "Fault %s encountered.\n", this->name());
Addr vect = this->vect(tc);
setTlbExceptionState(tc, this->code());
diff --git a/src/arch/mips/interrupts.cc b/src/arch/mips/interrupts.cc
index 096aa628f..f4221ab2c 100755
--- a/src/arch/mips/interrupts.cc
+++ b/src/arch/mips/interrupts.cc
@@ -36,6 +36,7 @@
#include "arch/mips/pra_constants.hh"
#include "base/trace.hh"
#include "cpu/thread_context.hh"
+#include "debug/Interrupt.hh"
namespace MipsISA
{
diff --git a/src/arch/mips/isa/decoder.isa b/src/arch/mips/isa/decoder.isa
index 8ebfa66bf..034133f96 100644
--- a/src/arch/mips/isa/decoder.isa
+++ b/src/arch/mips/isa/decoder.isa
@@ -163,7 +163,7 @@ decode OPCODE_HI default Unknown::unknown() {
format BasicOp {
0x2: movz({{ Rd = (Rt == 0) ? Rs : Rd; }});
0x3: movn({{ Rd = (Rt != 0) ? Rs : Rd; }});
- 0x4: decode FULL_SYSTEM {
+ 0x4: decode FullSystem {
0: syscall_se({{ xc->syscall(R2); }},
IsSerializeAfter, IsNonSpeculative);
default: syscall({{ fault = new SystemCallFault(); }});
@@ -212,7 +212,7 @@ decode OPCODE_HI default Unknown::unknown() {
0x0: add({{
IntReg result;
Rd = result = Rs + Rt;
- if (FULL_SYSTEM &&
+ if (FullSystem &&
findOverflow(32, result, Rs, Rt)) {
fault = new IntegerOverflowFault();
}
@@ -221,7 +221,7 @@ decode OPCODE_HI default Unknown::unknown() {
0x2: sub({{
IntReg result;
Rd = result = Rs - Rt;
- if (FULL_SYSTEM &&
+ if (FullSystem &&
findOverflow(32, result, Rs, ~Rt)) {
fault = new IntegerOverflowFault();
}
@@ -325,7 +325,7 @@ decode OPCODE_HI default Unknown::unknown() {
0x0: addi({{
IntReg result;
Rt = result = Rs + imm;
- if (FULL_SYSTEM &&
+ if (FullSystem &&
findOverflow(32, result, Rs, imm)) {
fault = new IntegerOverflowFault();
}
@@ -2431,7 +2431,7 @@ decode OPCODE_HI default Unknown::unknown() {
}
}
0x3: decode OP default FailUnimpl::rdhwr() {
- 0x0: decode FULL_SYSTEM {
+ 0x0: decode FullSystem {
0: decode RD {
29: BasicOp::rdhwr_se({{ Rt = TpValue; }});
}
diff --git a/src/arch/mips/isa/formats/control.isa b/src/arch/mips/isa/formats/control.isa
index 7e90ed3e5..d8e5eb111 100644
--- a/src/arch/mips/isa/formats/control.isa
+++ b/src/arch/mips/isa/formats/control.isa
@@ -88,14 +88,14 @@ def template CP0Execute {{
if (isCoprocessorEnabled(xc, 0)) {
%(code)s;
+
+ if(fault == NoFault)
+ {
+ %(op_wb)s;
+ }
} else {
fault = new CoprocessorUnusableFault(0);
}
-
- if(fault == NoFault)
- {
- %(op_wb)s;
- }
return fault;
}
}};
@@ -128,7 +128,7 @@ def template ControlTLBExecute {{
%(op_decl)s;
%(op_rd)s;
- if (FULL_SYSTEM) {
+ if (FullSystem) {
if (isCoprocessor0Enabled(xc)) {
if(isMMUTLB(xc)){
%(code)s;
@@ -176,7 +176,7 @@ output exec {{
bool
isCoprocessorEnabled(%(CPU_exec_context)s *xc, unsigned cop_num)
{
- if (!FULL_SYSTEM)
+ if (!FullSystem)
return true;
MiscReg Stat = xc->readMiscReg(MISCREG_STATUS);
@@ -198,7 +198,7 @@ output exec {{
bool inline
isCoprocessor0Enabled(%(CPU_exec_context)s *xc)
{
- if (FULL_SYSTEM) {
+ if (FullSystem) {
MiscReg Stat = xc->readMiscReg(MISCREG_STATUS);
MiscReg Dbg = xc->readMiscReg(MISCREG_DEBUG);
// In Stat, EXL, ERL or CU0 set, CP0 accessible
@@ -215,7 +215,7 @@ output exec {{
isMMUTLB(%(CPU_exec_context)s *xc)
{
MiscReg Config = xc->readMiscReg(MISCREG_CONFIG);
- return FULL_SYSTEM && (Config & 0x380) == 0x80;
+ return FullSystem && (Config & 0x380) == 0x80;
}
}};
diff --git a/src/arch/mips/isa/formats/dsp.isa b/src/arch/mips/isa/formats/dsp.isa
index 2eeefe806..b288b7b20 100755
--- a/src/arch/mips/isa/formats/dsp.isa
+++ b/src/arch/mips/isa/formats/dsp.isa
@@ -143,7 +143,7 @@ output exec {{
bool
isDspEnabled(%(CPU_exec_context)s *xc)
{
- return !FULL_SYSTEM || bits(xc->readMiscReg(MISCREG_STATUS), 24);
+ return !FullSystem || bits(xc->readMiscReg(MISCREG_STATUS), 24);
}
}};
@@ -151,7 +151,7 @@ output exec {{
bool
isDspPresent(%(CPU_exec_context)s *xc)
{
- return !FULL_SYSTEM || bits(xc->readMiscReg(MISCREG_CONFIG3), 10);
+ return !FullSystem || bits(xc->readMiscReg(MISCREG_CONFIG3), 10);
}
}};
diff --git a/src/arch/mips/isa/formats/fp.isa b/src/arch/mips/isa/formats/fp.isa
index f99d2327e..63823f404 100644
--- a/src/arch/mips/isa/formats/fp.isa
+++ b/src/arch/mips/isa/formats/fp.isa
@@ -174,7 +174,7 @@ def template FloatingPointExecute {{
//When is the right time to reset cause bits?
//start of every instruction or every cycle?
- if (FULL_SYSTEM)
+ if (FullSystem)
fpResetCauseBits(xc);
%(op_decl)s;
%(op_rd)s;
@@ -191,7 +191,7 @@ def template FloatingPointExecute {{
//Check for IEEE 754 FP Exceptions
//fault = fpNanOperands((FPOp*)this, xc, Fd, traceData);
bool invalid_op = false;
- if (FULL_SYSTEM) {
+ if (FullSystem) {
invalid_op =
fpInvalidOp((FPOp*)this, xc, Fd, traceData);
}
diff --git a/src/arch/mips/isa/formats/unimp.isa b/src/arch/mips/isa/formats/unimp.isa
index 65b4425af..d567a113f 100644
--- a/src/arch/mips/isa/formats/unimp.isa
+++ b/src/arch/mips/isa/formats/unimp.isa
@@ -193,7 +193,7 @@ output exec {{
CP0Unimplemented::execute(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
- if (FULL_SYSTEM) {
+ if (FullSystem) {
if (!isCoprocessorEnabled(xc, 0))
return new CoprocessorUnusableFault(0);
else
@@ -210,7 +210,7 @@ output exec {{
CP1Unimplemented::execute(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
- if (FULL_SYSTEM) {
+ if (FullSystem) {
if (!isCoprocessorEnabled(xc, 1))
return new CoprocessorUnusableFault(1);
else
@@ -227,7 +227,7 @@ output exec {{
CP2Unimplemented::execute(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
- if (FULL_SYSTEM) {
+ if (FullSystem) {
if (!isCoprocessorEnabled(xc, 2))
return new CoprocessorUnusableFault(2);
else
diff --git a/src/arch/mips/isa/includes.isa b/src/arch/mips/isa/includes.isa
index 4ce03b1c2..d2e9c797e 100644
--- a/src/arch/mips/isa/includes.isa
+++ b/src/arch/mips/isa/includes.isa
@@ -60,6 +60,7 @@ output decoder {{
#include "base/cprintf.hh"
#include "cpu/thread_context.hh"
#include "mem/packet.hh"
+#include "sim/full_system.hh"
#if defined(linux)
#include <fenv.h>
#endif
@@ -92,6 +93,7 @@ output exec {{
#include "mem/packet.hh"
#include "mem/packet_access.hh"
#include "sim/eventq.hh"
+#include "sim/full_system.hh"
#include "sim/sim_events.hh"
#include "sim/sim_exit.hh"
diff --git a/src/arch/mips/isa_traits.hh b/src/arch/mips/isa_traits.hh
index 5cef45523..f2a748da9 100644
--- a/src/arch/mips/isa_traits.hh
+++ b/src/arch/mips/isa_traits.hh
@@ -34,10 +34,8 @@
#ifndef __ARCH_MIPS_ISA_TRAITS_HH__
#define __ARCH_MIPS_ISA_TRAITS_HH__
-#include "arch/mips/mips_core_specific.hh"
#include "arch/mips/types.hh"
#include "base/types.hh"
-#include "config/full_system.hh"
#include "cpu/static_inst_fwd.hh"
namespace LittleEndianGuest {}
diff --git a/src/arch/mips/linux/system.cc b/src/arch/mips/linux/system.cc
index 7cfa043e2..f97426f85 100644
--- a/src/arch/mips/linux/system.cc
+++ b/src/arch/mips/linux/system.cc
@@ -47,6 +47,7 @@
#include "base/loader/symtab.hh"
#include "cpu/base.hh"
#include "cpu/thread_context.hh"
+#include "debug/Thread.hh"
#include "dev/platform.hh"
#include "kern/linux/events.hh"
#include "kern/linux/printk.hh"
@@ -62,106 +63,17 @@ using namespace Linux;
LinuxMipsSystem::LinuxMipsSystem(Params *p)
: MipsSystem(p)
{
- Addr addr = 0;
-
- /**
- * The symbol swapper_pg_dir marks the beginning of the kernel and
- * the location of bootloader passed arguments
- */
- if (!kernelSymtab->findAddress("swapper_pg_dir", KernelStart)) {
- panic("Could not determine start location of kernel");
- }
-
- /**
- * Since we aren't using a bootloader, we have to copy the
- * kernel arguments directly into the kernel's memory.
- */
- virtPort.writeBlob(CommandLine(), (uint8_t*)params()->boot_osflags.c_str(),
- params()->boot_osflags.length()+1);
-
- /**
- * find the address of the est_cycle_freq variable and insert it
- * so we don't through the lengthly process of trying to
- * calculated it by using the PIT, RTC, etc.
- */
- if (kernelSymtab->findAddress("est_cycle_freq", addr))
- virtPort.write(addr, (uint64_t)(SimClock::Frequency /
- p->boot_cpu_frequency));
-
- /**
- * EV5 only supports 127 ASNs so we are going to tell the kernel that the
- * paritiuclar EV6 we have only supports 127 asns.
- * @todo At some point we should change ev5.hh and the palcode to support
- * 255 ASNs.
- */
- if (kernelSymtab->findAddress("dp264_mv", addr))
- virtPort.write(addr + 0x18, LittleEndianGuest::htog((uint32_t)127));
- else
- panic("could not find dp264_mv\n");
-
-#ifndef NDEBUG
- kernelPanicEvent = addKernelFuncEvent<BreakPCEvent>("panic");
- if (!kernelPanicEvent)
- panic("could not find kernel symbol \'panic\'");
-
-#endif
-
- /**
- * Any time ide_delay_50ms, calibarte_delay or
- * determine_cpu_caches is called just skip the
- * function. Currently determine_cpu_caches only is used put
- * information in proc, however if that changes in the future we
- * will have to fill in the cache size variables appropriately.
- */
-
- skipIdeDelay50msEvent =
- addKernelFuncEvent<SkipFuncEvent>("ide_delay_50ms");
- skipDelayLoopEvent =
- addKernelFuncEvent<SkipDelayLoopEvent>("calibrate_delay");
- skipCacheProbeEvent =
- addKernelFuncEvent<SkipFuncEvent>("determine_cpu_caches");
- debugPrintkEvent = addKernelFuncEvent<DebugPrintkEvent>("dprintk");
- idleStartEvent = addKernelFuncEvent<IdleStartEvent>("cpu_idle");
-
- // Disable for now as it runs into panic() calls in VPTr methods
- // (see sim/vptr.hh). Once those bugs are fixed, we can
- // re-enable, but we should find a better way to turn it on than
- // using DTRACE(Thread), since looking at a trace flag at tick 0
- // leads to non-intuitive behavior with --trace-start.
- if (false && kernelSymtab->findAddress("mips_switch_to", addr)) {
- printThreadEvent = new PrintThreadInfo(&pcEventQueue, "threadinfo",
- addr + sizeof(MachInst) * 6);
- } else {
- printThreadEvent = NULL;
- }
}
LinuxMipsSystem::~LinuxMipsSystem()
{
-#ifndef NDEBUG
- delete kernelPanicEvent;
-#endif
- delete skipIdeDelay50msEvent;
- delete skipDelayLoopEvent;
- delete skipCacheProbeEvent;
- delete debugPrintkEvent;
- delete idleStartEvent;
- delete printThreadEvent;
}
void
LinuxMipsSystem::setDelayLoop(ThreadContext *tc)
{
- Addr addr = 0;
- if (kernelSymtab->findAddress("loops_per_jiffy", addr)) {
- Tick cpuFreq = tc->getCpuPtr()->frequency();
- Tick intrFreq = platform->intrFrequency();
- FSTranslatingPortProxy* vp;
-
- vp = tc->getVirtProxy();
- vp->writeHtoG(addr, (uint32_t)((cpuFreq / intrFreq) * 0.9988));
- }
+ panic("setDelayLoop not implemented.\n");
}
diff --git a/src/arch/mips/mips_core_specific.cc b/src/arch/mips/mips_core_specific.cc
deleted file mode 100755
index 31d47c842..000000000
--- a/src/arch/mips/mips_core_specific.cc
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- * Copyright (c) 2002, 2005 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Nathan Binkert
- * Steve Reinhardt
- */
-
-#include "config/full_system.hh"
-#include "cpu/base.hh"
-#include "cpu/thread_context.hh"
-
-#if FULL_SYSTEM
-
-////////////////////////////////////////////////////////////////////////
-//
-// Machine dependent functions
-//
-void
-MipsISA::initCPU(ThreadContext *tc, int cpuId)
-{}
-
-#endif // FULL_SYSTEM || BARE_IRON
diff --git a/src/arch/mips/mips_core_specific.hh b/src/arch/mips/mips_core_specific.hh
deleted file mode 100644
index bd66e049f..000000000
--- a/src/arch/mips/mips_core_specific.hh
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * Copyright (c) 2007 MIPS Technologies, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Jaidev Patwardhan
- */
-
-#ifndef __ARCH_MIPS_CORE_SPECIFIC_HH__
-#define __ARCH_MIPS_CORE_SPECIFIC_HH__
-
-#include "arch/mips/isa_traits.hh"
-
-class ThreadContext;
-
-namespace MipsISA {
- void initCPU(ThreadContext *tc, int cpuId);
-};
-
-#endif // __ARCH_MIPS_CORE_SPECIFIC_HH__
diff --git a/src/arch/mips/pagetable.hh b/src/arch/mips/pagetable.hh
index cd269f1af..8678eb7e4 100755
--- a/src/arch/mips/pagetable.hh
+++ b/src/arch/mips/pagetable.hh
@@ -34,34 +34,14 @@
#ifndef __ARCH_MIPS_PAGETABLE_H__
#define __ARCH_MIPS_PAGETABLE_H__
-#include "arch/mips/isa_traits.hh"
-#include "arch/mips/utility.hh"
-#include "arch/mips/vtophys.hh"
-#include "config/full_system.hh"
+#include "base/misc.hh"
+#include "base/types.hh"
+#include "sim/serialize.hh"
namespace MipsISA {
struct VAddr
{
- static const int ImplBits = 43;
- static const Addr ImplMask = (ULL(1) << ImplBits) - 1;
- static const Addr UnImplMask = ~ImplMask;
-
- VAddr(Addr a) : addr(a) {}
- Addr addr;
- operator Addr() const { return addr; }
- const VAddr &operator=(Addr a) { addr = a; return *this; }
-
- Addr vpn() const { return (addr & ImplMask) >> PageShift; }
- Addr page() const { return addr & Page_Mask; }
- Addr offset() const { return addr & PageOffset; }
-
- Addr level3() const
- { return MipsISA::PteAddr(addr >> PageShift); }
- Addr level2() const
- { return MipsISA::PteAddr(addr >> (NPtePageShift + PageShift)); }
- Addr level1() const
- { return MipsISA::PteAddr(addr >> (2 * NPtePageShift + PageShift)); }
};
// ITB/DTB page table entry
@@ -98,6 +78,33 @@ struct PTE
void unserialize(Checkpoint *cp, const std::string &section);
};
+// WARN: This particular TLB entry is not necessarily conformed to MIPS ISA
+struct TlbEntry
+{
+ Addr _pageStart;
+ TlbEntry() {}
+ TlbEntry(Addr asn, Addr vaddr, Addr paddr) : _pageStart(paddr) {}
+
+ Addr pageStart()
+ {
+ return _pageStart;
+ }
+
+ void
+ updateVaddr(Addr new_vaddr) {}
+
+ void serialize(std::ostream &os)
+ {
+ SERIALIZE_SCALAR(_pageStart);
+ }
+
+ void unserialize(Checkpoint *cp, const std::string &section)
+ {
+ UNSERIALIZE_SCALAR(_pageStart);
+ }
+
+};
+
};
#endif // __ARCH_MIPS_PAGETABLE_H__
diff --git a/src/arch/mips/remote_gdb.cc b/src/arch/mips/remote_gdb.cc
index 1fd157758..656cb8cbb 100644
--- a/src/arch/mips/remote_gdb.cc
+++ b/src/arch/mips/remote_gdb.cc
@@ -137,12 +137,12 @@
#include "arch/mips/remote_gdb.hh"
#include "arch/mips/vtophys.hh"
-#include "config/full_system.hh"
#include "cpu/decode.hh"
#include "cpu/thread_state.hh"
#include "debug/GDBAcc.hh"
#include "debug/GDBMisc.hh"
#include "mem/page_table.hh"
+#include "sim/full_system.hh"
using namespace std;
using namespace MipsISA;
@@ -158,13 +158,13 @@ RemoteGDB::RemoteGDB(System *_system, ThreadContext *tc)
bool
RemoteGDB::acc(Addr va, size_t len)
{
-#if FULL_SYSTEM
- panic("acc not implemented for MIPS FS!");
-#endif
TlbEntry entry;
//Check to make sure the first byte is mapped into the processes address
//space.
- return context->getProcessPtr()->pTable->lookup(va, entry);
+ if (FullSystem)
+ panic("acc not implemented for MIPS FS!");
+ else
+ return context->getProcessPtr()->pTable->lookup(va, entry);
}
/*
diff --git a/src/arch/mips/stacktrace.cc b/src/arch/mips/stacktrace.cc
index ced60b88e..d4548b4bb 100644
--- a/src/arch/mips/stacktrace.cc
+++ b/src/arch/mips/stacktrace.cc
@@ -37,6 +37,7 @@
#include "base/trace.hh"
#include "cpu/base.hh"
#include "cpu/thread_context.hh"
+#include "mem/fs_translating_port_proxy.hh"
#include "sim/system.hh"
using namespace std;
diff --git a/src/arch/mips/system.cc b/src/arch/mips/system.cc
index c1735b740..f0d4c250e 100755
--- a/src/arch/mips/system.cc
+++ b/src/arch/mips/system.cc
@@ -45,77 +45,12 @@ using namespace LittleEndianGuest;
MipsSystem::MipsSystem(Params *p) : System(p)
{
-
-#if FULL_SYSTEM
- if (p->bare_iron == true) {
- hexFile = new HexFile(params()->hex_file_name);
- if (!hexFile->loadSections(functionalPort))
- panic("Could not load hex file\n");
- }
-
- Addr addr = 0;
-
- consoleSymtab = new SymbolTable;
-
-
- /**
- * Load the console code into memory
- */
- // Load Console Code
- console = createObjectFile(params()->console);
-
- warn("console code is located at: %s\n", params()->console);
-
- if (console == NULL)
- fatal("Could not load console file %s", params()->console);
- //Load program sections into memory
- console->loadSections(functionalPort, loadAddrMask);
-
- //load symbols
- if (!console->loadGlobalSymbols(consoleSymtab))
- panic("could not load console symbols\n");
-
- if (!console->loadGlobalSymbols(debugSymbolTable))
- panic("could not load console symbols\n");
-
-
-#ifndef NDEBUG
- consolePanicEvent = addConsoleFuncEvent<BreakPCEvent>("panic");
-#endif
-
- /**
- * Copy the osflags (kernel arguments) into the consoles
- * memory. (Presently Linux does not use the console service
- * routine to get these command line arguments, but Tru64 and
- * others do.)
- */
- if (consoleSymtab->findAddress("env_booted_osflags", addr)) {
- warn("writing addr starting from %#x", addr);
- virtPort->writeBlob(addr, (uint8_t*)params()->boot_osflags.c_str(),
- strlen(params()->boot_osflags.c_str()));
- }
-
- /**
- * Set the hardware reset parameter block system type and revision
- * information to Tsunami.
- */
- if (consoleSymtab->findAddress("m5_rpb", addr)) {
- uint64_t data;
- data = htog(params()->system_type);
- virtPort->write(addr + 0x50, data);
- data = htog(params()->system_rev);
- virtPort->write(addr + 0x58, data);
- } else {
- panic("could not find hwrpb\n");
- }
-#endif
}
MipsSystem::~MipsSystem()
{
}
-#if FULL_SYSTEM
Addr
MipsSystem::fixFuncEventAddr(Addr addr)
{
@@ -126,8 +61,6 @@ void
MipsSystem::setMipsAccess(Addr access)
{}
-#endif
-
bool
MipsSystem::breakpoint()
{
diff --git a/src/arch/mips/system.hh b/src/arch/mips/system.hh
index 128f36581..fcaceadcd 100755
--- a/src/arch/mips/system.hh
+++ b/src/arch/mips/system.hh
@@ -66,7 +66,6 @@ class MipsSystem : public System
*/
void setMipsAccess(Addr access);
-#if FULL_SYSTEM
/** console symbol table */
SymbolTable *consoleSymtab;
@@ -75,7 +74,6 @@ class MipsSystem : public System
/** Used by some Bare Iron Configurations */
HexFile *hexFile;
-#endif
#ifndef NDEBUG
/** Event to halt the simulator if the console calls panic() */
@@ -85,9 +83,7 @@ class MipsSystem : public System
protected:
const Params *params() const { return (const Params *)_params; }
-
-#if FULL_SYSTEM
- /** Add a function-based event to the console code. */
+ /** Add a function-based event to the console code. */
template <class T>
T *
addConsoleFuncEvent(const char *lbl)
@@ -96,7 +92,6 @@ class MipsSystem : public System
}
virtual Addr fixFuncEventAddr(Addr addr);
-#endif
};
diff --git a/src/arch/mips/tlb.cc b/src/arch/mips/tlb.cc
index b3ed09621..cd6d47d1e 100644
--- a/src/arch/mips/tlb.cc
+++ b/src/arch/mips/tlb.cc
@@ -295,7 +295,9 @@ TLB::regStats()
Fault
TLB::translateInst(RequestPtr req, ThreadContext *tc)
{
-#if !FULL_SYSTEM
+ if (FullSystem)
+ panic("translateInst not implemented in MIPS.\n");
+
Process * p = tc->getProcessPtr();
Fault fault = p->pTable->translate(req);
@@ -303,93 +305,13 @@ TLB::translateInst(RequestPtr req, ThreadContext *tc)
return fault;
return NoFault;
-#else
- Addr vaddr = req->getVaddr();
-
- bool misaligned = (req->getSize() - 1) & vaddr;
-
- if (IsKSeg0(vaddr)) {
- // Address will not be translated through TLB, set response, and go!
- req->setPaddr(KSeg02Phys(vaddr));
- if (getOperatingMode(tc->readMiscReg(MISCREG_STATUS)) != mode_kernel ||
- misaligned) {
- return new AddressErrorFault(vaddr, false);
- }
- } else if(IsKSeg1(vaddr)) {
- // Address will not be translated through TLB, set response, and go!
- req->setPaddr(KSeg02Phys(vaddr));
- } else {
- /*
- * This is an optimization - smallPages is updated every time a TLB
- * operation is performed. That way, we don't need to look at
- * Config3 _ SP and PageGrain _ ESP every time we do a TLB lookup
- */
- Addr VPN;
- if (smallPages == 1) {
- VPN = (vaddr >> 11);
- } else {
- VPN = ((vaddr >> 11) & 0xFFFFFFFC);
- }
- uint8_t Asid = req->getAsid();
- if (misaligned) {
- // Unaligned address!
- return new AddressErrorFault(vaddr, false);
- }
- PTE *pte = lookup(VPN,Asid);
- if (pte != NULL) {
- // Ok, found something
- /* Check for valid bits */
- int EvenOdd;
- bool Valid;
- if ((((vaddr) >> pte->AddrShiftAmount) & 1) == 0) {
- // Check even bits
- Valid = pte->V0;
- EvenOdd = 0;
- } else {
- // Check odd bits
- Valid = pte->V1;
- EvenOdd = 1;
- }
-
- if (Valid == false) {
- return new TlbInvalidFault(Asid, vaddr, VPN, false);
- } else {
- // Ok, this is really a match, set paddr
- Addr PAddr;
- if (EvenOdd == 0) {
- PAddr = pte->PFN0;
- } else {
- PAddr = pte->PFN1;
- }
- PAddr >>= (pte->AddrShiftAmount - 12);
- PAddr <<= pte->AddrShiftAmount;
- PAddr |= (vaddr & pte->OffsetMask);
- req->setPaddr(PAddr);
- }
- } else {
- // Didn't find any match, return a TLB Refill Exception
- return new TlbRefillFault(Asid, vaddr, VPN, false);
- }
- }
- return checkCacheability(req);
-#endif
}
Fault
TLB::translateData(RequestPtr req, ThreadContext *tc, bool write)
{
-#if !FULL_SYSTEM
- //@TODO: This should actually use TLB instead of going directly
- // to the page table in syscall mode.
- /**
- * Check for alignment faults
- */
- if (req->getVaddr() & (req->getSize() - 1)) {
- DPRINTF(TLB, "Alignment Fault on %#x, size = %d", req->getVaddr(),
- req->getSize());
- return new AddressErrorFault(req->getVaddr(), write);
- }
-
+ if (FullSystem)
+ panic("translateData not implemented in MIPS.\n");
Process * p = tc->getProcessPtr();
@@ -398,79 +320,6 @@ TLB::translateData(RequestPtr req, ThreadContext *tc, bool write)
return fault;
return NoFault;
-#else
- Addr vaddr = req->getVaddr();
-
- bool misaligned = (req->getSize() - 1) & vaddr;
-
- if (IsKSeg0(vaddr)) {
- // Address will not be translated through TLB, set response, and go!
- req->setPaddr(KSeg02Phys(vaddr));
- if (getOperatingMode(tc->readMiscReg(MISCREG_STATUS)) != mode_kernel ||
- misaligned) {
- return new AddressErrorFault(vaddr, true);
- }
- } else if(IsKSeg1(vaddr)) {
- // Address will not be translated through TLB, set response, and go!
- req->setPaddr(KSeg02Phys(vaddr));
- } else {
- /*
- * This is an optimization - smallPages is updated every time a TLB
- * operation is performed. That way, we don't need to look at
- * Config3 _ SP and PageGrain _ ESP every time we do a TLB lookup
- */
- Addr VPN = (vaddr >> 11) & 0xFFFFFFFC;
- if (smallPages == 1) {
- VPN = vaddr >> 11;
- }
- uint8_t Asid = req->getAsid();
- PTE *pte = lookup(VPN, Asid);
- if (misaligned) {
- return new AddressErrorFault(vaddr, true);
- }
- if (pte != NULL) {
- // Ok, found something
- /* Check for valid bits */
- int EvenOdd;
- bool Valid;
- bool Dirty;
- if ((((vaddr >> pte->AddrShiftAmount) & 1)) == 0) {
- // Check even bits
- Valid = pte->V0;
- Dirty = pte->D0;
- EvenOdd = 0;
- } else {
- // Check odd bits
- Valid = pte->V1;
- Dirty = pte->D1;
- EvenOdd = 1;
- }
-
- if (Valid == false) {
- return new TlbInvalidFault(Asid, vaddr, VPN, write);
- } else {
- // Ok, this is really a match, set paddr
- if (!Dirty && write) {
- return new TlbModifiedFault(Asid, vaddr, VPN);
- }
- Addr PAddr;
- if (EvenOdd == 0) {
- PAddr = pte->PFN0;
- } else {
- PAddr = pte->PFN1;
- }
- PAddr >>= (pte->AddrShiftAmount - 12);
- PAddr <<= pte->AddrShiftAmount;
- PAddr |= (vaddr & pte->OffsetMask);
- req->setPaddr(PAddr);
- }
- } else {
- // Didn't find any match, return a TLB Refill Exception
- return new TlbRefillFault(Asid, vaddr, VPN, write);
- }
- }
- return checkCacheability(req);
-#endif
}
Fault
diff --git a/src/arch/mips/tlb.hh b/src/arch/mips/tlb.hh
index 4b1456862..834431536 100644
--- a/src/arch/mips/tlb.hh
+++ b/src/arch/mips/tlb.hh
@@ -55,33 +55,6 @@ class ThreadContext;
simply create an ITLB and DTLB that will point to the real TLB */
namespace MipsISA {
-// WARN: This particular TLB entry is not necessarily conformed to MIPS ISA
-struct TlbEntry
-{
- Addr _pageStart;
- TlbEntry() {}
- TlbEntry(Addr asn, Addr vaddr, Addr paddr) : _pageStart(paddr) {}
-
- Addr pageStart()
- {
- return _pageStart;
- }
-
- void
- updateVaddr(Addr new_vaddr) {}
-
- void serialize(std::ostream &os)
- {
- SERIALIZE_SCALAR(_pageStart);
- }
-
- void unserialize(Checkpoint *cp, const std::string &section)
- {
- UNSERIALIZE_SCALAR(_pageStart);
- }
-
-};
-
class TLB : public BaseTLB
{
protected:
diff --git a/src/arch/mips/utility.cc b/src/arch/mips/utility.cc
index fc6e9e2f9..65432b4ea 100644
--- a/src/arch/mips/utility.cc
+++ b/src/arch/mips/utility.cc
@@ -31,19 +31,15 @@
#include <cmath>
#include "arch/mips/isa_traits.hh"
+#include "arch/mips/registers.hh"
#include "arch/mips/utility.hh"
+#include "arch/mips/vtophys.hh"
#include "base/bitfield.hh"
#include "base/misc.hh"
-#include "config/full_system.hh"
#include "cpu/static_inst.hh"
#include "cpu/thread_context.hh"
-#include "sim/serialize.hh"
-
-#if FULL_SYSTEM
-#include "arch/mips/registers.hh"
-#include "arch/mips/vtophys.hh"
#include "mem/fs_translating_port_proxy.hh"
-#endif
+#include "sim/serialize.hh"
using namespace MipsISA;
@@ -54,23 +50,8 @@ namespace MipsISA {
uint64_t
getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp)
{
-#if FULL_SYSTEM
- if (number < 4) {
- if (fp)
- return tc->readFloatRegBits(FirstArgumentReg + number);
- else
- return tc->readIntReg(FirstArgumentReg + number);
- } else {
- Addr sp = tc->readIntReg(StackPointerReg);
- FSTranslatingPortProxy* vp = tc->getVirtProxy();
- uint64_t arg = vp->read<uint64_t>(sp +
- (number - 4) * sizeof(uint64_t));
- return arg;
- }
-#else
- panic("getArgument() is Full system only\n");
+ panic("getArgument() not implemented\n");
M5_DUMMY_RETURN
-#endif
}
uint64_t
@@ -254,6 +235,10 @@ startupCPU(ThreadContext *tc, int cpuId)
}
void
+initCPU(ThreadContext *tc, int cpuId)
+{}
+
+void
copyRegs(ThreadContext *src, ThreadContext *dest)
{
panic("Copy Regs Not Implemented Yet\n");
diff --git a/src/arch/mips/utility.hh b/src/arch/mips/utility.hh
index a2995b098..876066203 100644
--- a/src/arch/mips/utility.hh
+++ b/src/arch/mips/utility.hh
@@ -37,7 +37,6 @@
#include "arch/mips/types.hh"
#include "base/misc.hh"
#include "base/types.hh"
-#include "config/full_system.hh"
#include "cpu/static_inst.hh"
#include "cpu/thread_context.hh"
@@ -108,6 +107,7 @@ RoundPage(Addr addr)
// CPU Utility
//
void startupCPU(ThreadContext *tc, int cpuId);
+void initCPU(ThreadContext *tc, int cpuId);
void copyRegs(ThreadContext *src, ThreadContext *dest);
void copyMiscRegs(ThreadContext *src, ThreadContext *dest);
diff --git a/src/arch/mips/vtophys.cc b/src/arch/mips/vtophys.cc
index 08e1a1e1c..60d9bc1ba 100755
--- a/src/arch/mips/vtophys.cc
+++ b/src/arch/mips/vtophys.cc
@@ -37,7 +37,7 @@
#include "base/chunk_generator.hh"
#include "base/trace.hh"
#include "cpu/thread_context.hh"
-#include "mem/vport.hh"
+#include "debug/VtoPhys.hh"
using namespace std;
using namespace MipsISA;
@@ -45,25 +45,13 @@ using namespace MipsISA;
Addr
MipsISA::vtophys(Addr vaddr)
{
- Addr paddr = 0;
- if (MipsISA::IsUSeg(vaddr))
- DPRINTF(VtoPhys, "vtophys: invalid vaddr %#x", vaddr);
- else if (MipsISA::IsKSeg0(vaddr))
- paddr = MipsISA::KSeg02Phys(vaddr);
- else if(MipsISA::IsKSeg1(vaddr))
- paddr = MipsISA::KSeg12Phys(vaddr);
- else
- panic("vtophys: ptbr is not set on "
- "virtual lookup for vaddr %#x", vaddr);
-
- DPRINTF(VtoPhys, "vtophys(%#x) -> %#x\n", vaddr, paddr);
-
- return paddr;
+ fatal("VTOPHYS: Unimplemented on MIPS\n");
+ return 0;
}
Addr
MipsISA::vtophys(ThreadContext *tc, Addr addr)
{
- fatal("VTOPHYS: Unimplemented on MIPS\n");
+ fatal("VTOPHYS: Unimplemented on MIPS\n");
}
diff --git a/src/arch/mips/vtophys.hh b/src/arch/mips/vtophys.hh
index 741ac36bc..a3fbdd457 100644
--- a/src/arch/mips/vtophys.hh
+++ b/src/arch/mips/vtophys.hh
@@ -40,24 +40,6 @@
class ThreadContext;
namespace MipsISA {
- inline Addr PteAddr(Addr a) { return (a & PteMask) << PteShift; }
-
- // User Virtual
- inline bool IsUSeg(Addr a) { return USegBase <= a && a <= USegEnd; }
-
- inline bool IsKSeg0(Addr a) { return KSeg0Base <= a && a <= KSeg0End; }
-
- inline Addr KSeg02Phys(Addr addr) { return addr & KSeg0Mask; }
-
- inline Addr KSeg12Phys(Addr addr) { return addr & KSeg1Mask; }
-
- inline bool IsKSeg1(Addr a) { return KSeg1Base <= a && a <= KSeg1End; }
-
- inline bool IsKSSeg(Addr a) { return KSSegBase <= a && a <= KSSegEnd; }
-
- inline bool IsKSeg3(Addr a) { return KSeg3Base <= a && a <= KSeg3End; }
-
-
Addr vtophys(Addr vaddr);
Addr vtophys(ThreadContext *tc, Addr vaddr);