diff options
Diffstat (limited to 'src/arch')
| -rw-r--r-- | src/arch/alpha/AlphaISA.py | 4 | ||||
| -rw-r--r-- | src/arch/alpha/isa.cc | 2 | ||||
| -rw-r--r-- | src/arch/alpha/isa.hh | 10 | ||||
| -rw-r--r-- | src/arch/mips/MipsISA.py | 3 | ||||
| -rw-r--r-- | src/arch/mips/isa.cc | 3 | ||||
| -rw-r--r-- | src/arch/mips/isa.hh | 7 | ||||
| -rw-r--r-- | src/arch/power/isa.hh | 6 | ||||
| -rw-r--r-- | src/arch/sparc/isa.hh | 8 | ||||
| -rw-r--r-- | src/arch/x86/isa.hh | 6 |
9 files changed, 45 insertions, 4 deletions
diff --git a/src/arch/alpha/AlphaISA.py b/src/arch/alpha/AlphaISA.py index 64c9e4733..d85354704 100644 --- a/src/arch/alpha/AlphaISA.py +++ b/src/arch/alpha/AlphaISA.py @@ -35,9 +35,13 @@ # # Authors: Andreas Sandberg +from m5.params import * +from m5.proxy import * from m5.SimObject import SimObject class AlphaISA(SimObject): type = 'AlphaISA' cxx_class = 'AlphaISA::ISA' cxx_header = "arch/alpha/isa.hh" + + system = Param.System(Parent.any, "System this ISA object belongs to") diff --git a/src/arch/alpha/isa.cc b/src/arch/alpha/isa.cc index 9cfd840d9..95dfdedd6 100644 --- a/src/arch/alpha/isa.cc +++ b/src/arch/alpha/isa.cc @@ -40,7 +40,7 @@ namespace AlphaISA { ISA::ISA(Params *p) - : SimObject(p) + : SimObject(p), system(p->system) { clear(); initializeIprTable(); diff --git a/src/arch/alpha/isa.hh b/src/arch/alpha/isa.hh index d30499066..35a26c108 100644 --- a/src/arch/alpha/isa.hh +++ b/src/arch/alpha/isa.hh @@ -39,6 +39,7 @@ #include "arch/alpha/types.hh" #include "base/types.hh" #include "sim/sim_object.hh" +#include "sim/system.hh" struct AlphaISAParams; class BaseCPU; @@ -55,6 +56,9 @@ namespace AlphaISA typedef AlphaISAParams Params; protected: + // Parent system + System *system; + uint64_t fpcr; // floating point condition codes uint64_t uniq; // process-unique register bool lock_flag; // lock flag for LL/SC @@ -110,6 +114,12 @@ namespace AlphaISA return reg; } + int + flattenMiscIndex(int reg) + { + return reg; + } + const Params *params() const; ISA(Params *p); diff --git a/src/arch/mips/MipsISA.py b/src/arch/mips/MipsISA.py index bc969a906..22602ff0c 100644 --- a/src/arch/mips/MipsISA.py +++ b/src/arch/mips/MipsISA.py @@ -37,11 +37,14 @@ from m5.SimObject import SimObject from m5.params import * +from m5.proxy import * class MipsISA(SimObject): type = 'MipsISA' cxx_class = 'MipsISA::ISA' cxx_header = "arch/mips/isa.hh" + system = Param.System(Parent.any, "System this ISA object belongs to") + num_threads = Param.UInt8(1, "Maximum number this ISA can handle") num_vpes = Param.UInt8(1, "Maximum number of vpes this ISA can handle") diff --git a/src/arch/mips/isa.cc b/src/arch/mips/isa.cc index 891ed5e2f..164f10d5d 100644 --- a/src/arch/mips/isa.cc +++ b/src/arch/mips/isa.cc @@ -89,8 +89,7 @@ ISA::miscRegNames[NumMiscRegs] = }; ISA::ISA(Params *p) - : SimObject(p), - numThreads(p->num_threads), numVpes(p->num_vpes) + : SimObject(p), numThreads(p->num_threads), numVpes(p->num_vpes) { miscRegFile.resize(NumMiscRegs); bankType.resize(NumMiscRegs); diff --git a/src/arch/mips/isa.hh b/src/arch/mips/isa.hh index c601cfc1e..eddf75272 100644 --- a/src/arch/mips/isa.hh +++ b/src/arch/mips/isa.hh @@ -184,6 +184,13 @@ namespace MipsISA { return reg; } + + int + flattenMiscIndex(int reg) + { + return reg; + } + }; } diff --git a/src/arch/power/isa.hh b/src/arch/power/isa.hh index 7b59b2ad1..028142b50 100644 --- a/src/arch/power/isa.hh +++ b/src/arch/power/isa.hh @@ -105,6 +105,12 @@ class ISA : public SimObject return reg; } + int + flattenMiscIndex(int reg) + { + return reg; + } + void startup(ThreadContext *tc) {} /// Explicitly import the otherwise hidden startup diff --git a/src/arch/sparc/isa.hh b/src/arch/sparc/isa.hh index e6f023bc0..31cb09c7e 100644 --- a/src/arch/sparc/isa.hh +++ b/src/arch/sparc/isa.hh @@ -177,7 +177,6 @@ class ISA : public SimObject using SimObject::startup; protected: - bool isHyperPriv() { return hpstate.hpriv; } bool isPriv() { return hpstate.hpriv || pstate.priv; } bool isNonPriv() { return !isPriv(); } @@ -213,6 +212,13 @@ class ISA : public SimObject return reg; } + int + flattenMiscIndex(int reg) + { + return reg; + } + + typedef SparcISAParams Params; const Params *params() const; diff --git a/src/arch/x86/isa.hh b/src/arch/x86/isa.hh index 5f36fd7ad..14c8e98c9 100644 --- a/src/arch/x86/isa.hh +++ b/src/arch/x86/isa.hh @@ -91,6 +91,12 @@ namespace X86ISA return reg; } + int + flattenMiscIndex(int reg) + { + return reg; + } + void serialize(std::ostream &os); void unserialize(Checkpoint *cp, const std::string §ion); void startup(ThreadContext *tc); |