diff options
Diffstat (limited to 'src/cpu/checker/cpu.hh')
| -rw-r--r-- | src/cpu/checker/cpu.hh | 83 |
1 files changed, 46 insertions, 37 deletions
diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh index 14c0ad0b2..c77f964c0 100644 --- a/src/cpu/checker/cpu.hh +++ b/src/cpu/checker/cpu.hh @@ -98,7 +98,7 @@ class CheckerCPU : public BaseCPU, public ExecContext /** id attached to all issued requests */ MasterID masterId; public: - virtual void init(); + void init() override; typedef CheckerCPUParams Params; CheckerCPU(Params *p); @@ -110,7 +110,7 @@ class CheckerCPU : public BaseCPU, public ExecContext void setDcachePort(MasterPort *dcache_port); - MasterPort &getDataPort() + MasterPort &getDataPort() override { // the checker does not have ports on its own so return the // data port of the actual CPU core @@ -118,7 +118,7 @@ class CheckerCPU : public BaseCPU, public ExecContext return *dcachePort; } - MasterPort &getInstPort() + MasterPort &getInstPort() override { // the checker does not have ports on its own so return the // data port of the actual CPU core @@ -175,12 +175,12 @@ class CheckerCPU : public BaseCPU, public ExecContext TheISA::TLB* getITBPtr() { return itb; } TheISA::TLB* getDTBPtr() { return dtb; } - virtual Counter totalInsts() const + virtual Counter totalInsts() const override { return 0; } - virtual Counter totalOps() const + virtual Counter totalOps() const override { return 0; } @@ -194,8 +194,10 @@ class CheckerCPU : public BaseCPU, public ExecContext // These functions are only used in CPU models that split // effective address computation from the actual memory access. - void setEA(Addr EA) { panic("SimpleCPU::setEA() not implemented\n"); } - Addr getEA() const { panic("SimpleCPU::getEA() not implemented\n"); } + void setEA(Addr EA) override + { panic("CheckerCPU::setEA() not implemented\n"); } + Addr getEA() const override + { panic("CheckerCPU::getEA() not implemented\n"); } // The register accessor methods provide the index of the // instruction's operand (e.g., 0 or 1), not the architectural @@ -208,24 +210,25 @@ class CheckerCPU : public BaseCPU, public ExecContext // storage (which is pretty hard to imagine they would have reason // to do). - IntReg readIntRegOperand(const StaticInst *si, int idx) + IntReg readIntRegOperand(const StaticInst *si, int idx) override { return thread->readIntReg(si->srcRegIdx(idx)); } - FloatReg readFloatRegOperand(const StaticInst *si, int idx) + FloatReg readFloatRegOperand(const StaticInst *si, int idx) override { int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Reg_Base; return thread->readFloatReg(reg_idx); } - FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx) + FloatRegBits readFloatRegOperandBits(const StaticInst *si, + int idx) override { int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Reg_Base; return thread->readFloatRegBits(reg_idx); } - CCReg readCCRegOperand(const StaticInst *si, int idx) + CCReg readCCRegOperand(const StaticInst *si, int idx) override { int reg_idx = si->srcRegIdx(idx) - TheISA::CC_Reg_Base; return thread->readCCReg(reg_idx); @@ -239,13 +242,15 @@ class CheckerCPU : public BaseCPU, public ExecContext result.push(instRes); } - void setIntRegOperand(const StaticInst *si, int idx, IntReg val) + void setIntRegOperand(const StaticInst *si, int idx, + IntReg val) override { thread->setIntReg(si->destRegIdx(idx), val); setResult<uint64_t>(val); } - void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val) + void setFloatRegOperand(const StaticInst *si, int idx, + FloatReg val) override { int reg_idx = si->destRegIdx(idx) - TheISA::FP_Reg_Base; thread->setFloatReg(reg_idx, val); @@ -253,28 +258,28 @@ class CheckerCPU : public BaseCPU, public ExecContext } void setFloatRegOperandBits(const StaticInst *si, int idx, - FloatRegBits val) + FloatRegBits val) override { int reg_idx = si->destRegIdx(idx) - TheISA::FP_Reg_Base; thread->setFloatRegBits(reg_idx, val); setResult<uint64_t>(val); } - void setCCRegOperand(const StaticInst *si, int idx, CCReg val) + void setCCRegOperand(const StaticInst *si, int idx, CCReg val) override { int reg_idx = si->destRegIdx(idx) - TheISA::CC_Reg_Base; thread->setCCReg(reg_idx, val); setResult<uint64_t>(val); } - bool readPredicate() { return thread->readPredicate(); } - void setPredicate(bool val) + bool readPredicate() override { return thread->readPredicate(); } + void setPredicate(bool val) override { thread->setPredicate(val); } - TheISA::PCState pcState() const { return thread->pcState(); } - void pcState(const TheISA::PCState &val) + TheISA::PCState pcState() const override { return thread->pcState(); } + void pcState(const TheISA::PCState &val) override { DPRINTF(Checker, "Changing PC to %s, old PC %s.\n", val, thread->pcState()); @@ -290,7 +295,7 @@ class CheckerCPU : public BaseCPU, public ExecContext return thread->readMiscRegNoEffect(misc_reg); } - MiscReg readMiscReg(int misc_reg) + MiscReg readMiscReg(int misc_reg) override { return thread->readMiscReg(misc_reg); } @@ -302,21 +307,21 @@ class CheckerCPU : public BaseCPU, public ExecContext return thread->setMiscRegNoEffect(misc_reg, val); } - void setMiscReg(int misc_reg, const MiscReg &val) + void setMiscReg(int misc_reg, const MiscReg &val) override { DPRINTF(Checker, "Setting misc reg %d with effect to check later\n", misc_reg); miscRegIdxs.push(misc_reg); return thread->setMiscReg(misc_reg, val); } - MiscReg readMiscRegOperand(const StaticInst *si, int idx) + MiscReg readMiscRegOperand(const StaticInst *si, int idx) override { int reg_idx = si->srcRegIdx(idx) - TheISA::Misc_Reg_Base; return thread->readMiscReg(reg_idx); } - void setMiscRegOperand( - const StaticInst *si, int idx, const MiscReg &val) + void setMiscRegOperand(const StaticInst *si, int idx, + const MiscReg &val) override { int reg_idx = si->destRegIdx(idx) - TheISA::Misc_Reg_Base; return this->setMiscReg(reg_idx, val); @@ -343,18 +348,20 @@ class CheckerCPU : public BaseCPU, public ExecContext newPCState = val; } - void demapPage(Addr vaddr, uint64_t asn) + void demapPage(Addr vaddr, uint64_t asn) override { this->itb->demapPage(vaddr, asn); this->dtb->demapPage(vaddr, asn); } // monitor/mwait funtions - virtual void armMonitor(Addr address) { BaseCPU::armMonitor(0, address); } - bool mwait(PacketPtr pkt) { return BaseCPU::mwait(0, pkt); } - void mwaitAtomic(ThreadContext *tc) + void armMonitor(Addr address) override + { BaseCPU::armMonitor(0, address); } + bool mwait(PacketPtr pkt) override { return BaseCPU::mwait(0, pkt); } + void mwaitAtomic(ThreadContext *tc) override { return BaseCPU::mwaitAtomic(0, tc, thread->dtb); } - AddressMonitor *getAddrMonitor() { return BaseCPU::getCpuAddrMonitor(0); } + AddressMonitor *getAddrMonitor() override + { return BaseCPU::getCpuAddrMonitor(0); } void demapInstPage(Addr vaddr, uint64_t asn) { @@ -366,24 +373,26 @@ class CheckerCPU : public BaseCPU, public ExecContext this->dtb->demapPage(vaddr, asn); } - Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags); + Fault readMem(Addr addr, uint8_t *data, unsigned size, + unsigned flags) override; Fault writeMem(uint8_t *data, unsigned size, - Addr addr, unsigned flags, uint64_t *res); + Addr addr, unsigned flags, uint64_t *res) override; - unsigned int readStCondFailures() const { + unsigned int readStCondFailures() const override { return thread->readStCondFailures(); } - void setStCondFailures(unsigned int sc_failures) + void setStCondFailures(unsigned int sc_failures) override {} ///////////////////////////////////////////////////// - Fault hwrei() { return thread->hwrei(); } - bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); } + Fault hwrei() override { return thread->hwrei(); } + bool simPalCheck(int palFunc) override + { return thread->simPalCheck(palFunc); } void wakeup(ThreadID tid) override { } // Assume that the normal CPU's call to syscall was successful. // The checker's state would have already been updated by the syscall. - void syscall(int64_t callnum) { } + void syscall(int64_t callnum) override { } void handleError() { @@ -396,7 +405,7 @@ class CheckerCPU : public BaseCPU, public ExecContext void dumpAndExit(); - ThreadContext *tcBase() { return tc; } + ThreadContext *tcBase() override { return tc; } SimpleThread *threadBase() { return thread; } Result unverifiedResult; |