diff options
Diffstat (limited to 'src/cpu/o3')
-rw-r--r-- | src/cpu/o3/cpu.cc | 42 | ||||
-rw-r--r-- | src/cpu/o3/cpu.hh | 12 | ||||
-rw-r--r-- | src/cpu/o3/dyn_inst.hh | 11 | ||||
-rw-r--r-- | src/cpu/o3/regfile.hh | 24 | ||||
-rw-r--r-- | src/cpu/o3/thread_context.hh | 13 | ||||
-rw-r--r-- | src/cpu/o3/thread_context_impl.hh | 20 |
6 files changed, 6 insertions, 116 deletions
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc index 2f793453d..e5b8103ab 100644 --- a/src/cpu/o3/cpu.cc +++ b/src/cpu/o3/cpu.cc @@ -1284,14 +1284,6 @@ FullO3CPU<Impl>::readIntReg(PhysRegIdPtr phys_reg) } template <class Impl> -FloatReg -FullO3CPU<Impl>::readFloatReg(PhysRegIdPtr phys_reg) -{ - fpRegfileReads++; - return regFile.readFloatReg(phys_reg); -} - -template <class Impl> FloatRegBits FullO3CPU<Impl>::readFloatRegBits(PhysRegIdPtr phys_reg) { @@ -1343,14 +1335,6 @@ FullO3CPU<Impl>::setIntReg(PhysRegIdPtr phys_reg, uint64_t val) template <class Impl> void -FullO3CPU<Impl>::setFloatReg(PhysRegIdPtr phys_reg, FloatReg val) -{ - fpRegfileWrites++; - regFile.setFloatReg(phys_reg, val); -} - -template <class Impl> -void FullO3CPU<Impl>::setFloatRegBits(PhysRegIdPtr phys_reg, FloatRegBits val) { fpRegfileWrites++; @@ -1393,19 +1377,8 @@ FullO3CPU<Impl>::readArchIntReg(int reg_idx, ThreadID tid) } template <class Impl> -float -FullO3CPU<Impl>::readArchFloatReg(int reg_idx, ThreadID tid) -{ - fpRegfileReads++; - PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup( - RegId(FloatRegClass, reg_idx)); - - return regFile.readFloatReg(phys_reg); -} - -template <class Impl> uint64_t -FullO3CPU<Impl>::readArchFloatRegInt(int reg_idx, ThreadID tid) +FullO3CPU<Impl>::readArchFloatRegBits(int reg_idx, ThreadID tid) { fpRegfileReads++; PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup( @@ -1468,18 +1441,7 @@ FullO3CPU<Impl>::setArchIntReg(int reg_idx, uint64_t val, ThreadID tid) template <class Impl> void -FullO3CPU<Impl>::setArchFloatReg(int reg_idx, float val, ThreadID tid) -{ - fpRegfileWrites++; - PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup( - RegId(FloatRegClass, reg_idx)); - - regFile.setFloatReg(phys_reg, val); -} - -template <class Impl> -void -FullO3CPU<Impl>::setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid) +FullO3CPU<Impl>::setArchFloatRegBits(int reg_idx, uint64_t val, ThreadID tid) { fpRegfileWrites++; PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup( diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh index 19b9a34e0..4c4677615 100644 --- a/src/cpu/o3/cpu.hh +++ b/src/cpu/o3/cpu.hh @@ -401,8 +401,6 @@ class FullO3CPU : public BaseO3CPU uint64_t readIntReg(PhysRegIdPtr phys_reg); - TheISA::FloatReg readFloatReg(PhysRegIdPtr phys_reg); - TheISA::FloatRegBits readFloatRegBits(PhysRegIdPtr phys_reg); const VecRegContainer& readVecReg(PhysRegIdPtr reg_idx) const; @@ -449,8 +447,6 @@ class FullO3CPU : public BaseO3CPU void setIntReg(PhysRegIdPtr phys_reg, uint64_t val); - void setFloatReg(PhysRegIdPtr phys_reg, TheISA::FloatReg val); - void setFloatRegBits(PhysRegIdPtr phys_reg, TheISA::FloatRegBits val); void setVecReg(PhysRegIdPtr reg_idx, const VecRegContainer& val); @@ -461,9 +457,7 @@ class FullO3CPU : public BaseO3CPU uint64_t readArchIntReg(int reg_idx, ThreadID tid); - float readArchFloatReg(int reg_idx, ThreadID tid); - - uint64_t readArchFloatRegInt(int reg_idx, ThreadID tid); + uint64_t readArchFloatRegBits(int reg_idx, ThreadID tid); const VecRegContainer& readArchVecReg(int reg_idx, ThreadID tid) const; /** Read architectural vector register for modification. */ @@ -502,9 +496,7 @@ class FullO3CPU : public BaseO3CPU */ void setArchIntReg(int reg_idx, uint64_t val, ThreadID tid); - void setArchFloatReg(int reg_idx, float val, ThreadID tid); - - void setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid); + void setArchFloatRegBits(int reg_idx, uint64_t val, ThreadID tid); void setArchVecReg(int reg_idx, const VecRegContainer& val, ThreadID tid); diff --git a/src/cpu/o3/dyn_inst.hh b/src/cpu/o3/dyn_inst.hh index 47dc830e0..d4fbc78f9 100644 --- a/src/cpu/o3/dyn_inst.hh +++ b/src/cpu/o3/dyn_inst.hh @@ -273,11 +273,6 @@ class BaseO3DynInst : public BaseDynInst<Impl> return this->cpu->readIntReg(this->_srcRegIdx[idx]); } - FloatReg readFloatRegOperand(const StaticInst *si, int idx) - { - return this->cpu->readFloatReg(this->_srcRegIdx[idx]); - } - FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx) { return this->cpu->readFloatRegBits(this->_srcRegIdx[idx]); @@ -380,12 +375,6 @@ class BaseO3DynInst : public BaseDynInst<Impl> BaseDynInst<Impl>::setIntRegOperand(si, idx, val); } - void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val) - { - this->cpu->setFloatReg(this->_destRegIdx[idx], val); - BaseDynInst<Impl>::setFloatRegOperand(si, idx, val); - } - void setFloatRegOperandBits(const StaticInst *si, int idx, FloatRegBits val) { diff --git a/src/cpu/o3/regfile.hh b/src/cpu/o3/regfile.hh index 7feec933f..2f874213f 100644 --- a/src/cpu/o3/regfile.hh +++ b/src/cpu/o3/regfile.hh @@ -187,18 +187,6 @@ class PhysRegFile return intRegFile[phys_reg->index()]; } - /** Reads a floating point register (double precision). */ - FloatReg readFloatReg(PhysRegIdPtr phys_reg) const - { - assert(phys_reg->isFloatPhysReg()); - - DPRINTF(IEW, "RegFile: Access to float register %i, has " - "data %#x\n", phys_reg->index(), - floatRegFile[phys_reg->index()].q); - - return floatRegFile[phys_reg->index()].d; - } - FloatRegBits readFloatRegBits(PhysRegIdPtr phys_reg) const { assert(phys_reg->isFloatPhysReg()); @@ -298,18 +286,6 @@ class PhysRegFile intRegFile[phys_reg->index()] = val; } - /** Sets a double precision floating point register to the given value. */ - void setFloatReg(PhysRegIdPtr phys_reg, FloatReg val) - { - assert(phys_reg->isFloatPhysReg()); - - DPRINTF(IEW, "RegFile: Setting float register %i to %#x\n", - phys_reg->index(), (uint64_t)val); - - if (!phys_reg->isZeroReg()) - floatRegFile[phys_reg->index()].d = val; - } - void setFloatRegBits(PhysRegIdPtr phys_reg, FloatRegBits val) { assert(phys_reg->isFloatPhysReg()); diff --git a/src/cpu/o3/thread_context.hh b/src/cpu/o3/thread_context.hh index 2256a8a14..1fbf565f5 100644 --- a/src/cpu/o3/thread_context.hh +++ b/src/cpu/o3/thread_context.hh @@ -184,11 +184,6 @@ class O3ThreadContext : public ThreadContext reg_idx)).index()); } - virtual FloatReg readFloatReg(int reg_idx) { - return readFloatRegFlat(flattenRegId(RegId(FloatRegClass, - reg_idx)).index()); - } - virtual FloatRegBits readFloatRegBits(int reg_idx) { return readFloatRegBitsFlat(flattenRegId(RegId(FloatRegClass, reg_idx)).index()); @@ -268,11 +263,6 @@ class O3ThreadContext : public ThreadContext setIntRegFlat(flattenRegId(RegId(IntRegClass, reg_idx)).index(), val); } - virtual void setFloatReg(int reg_idx, FloatReg val) { - setFloatRegFlat(flattenRegId(RegId(FloatRegClass, - reg_idx)).index(), val); - } - virtual void setFloatRegBits(int reg_idx, FloatRegBits val) { setFloatRegBitsFlat(flattenRegId(RegId(FloatRegClass, reg_idx)).index(), val); @@ -364,9 +354,6 @@ class O3ThreadContext : public ThreadContext virtual uint64_t readIntRegFlat(int idx); virtual void setIntRegFlat(int idx, uint64_t val); - virtual FloatReg readFloatRegFlat(int idx); - virtual void setFloatRegFlat(int idx, FloatReg val); - virtual FloatRegBits readFloatRegBitsFlat(int idx); virtual void setFloatRegBitsFlat(int idx, FloatRegBits val); diff --git a/src/cpu/o3/thread_context_impl.hh b/src/cpu/o3/thread_context_impl.hh index d9f84fb52..f4b5cb4f4 100644 --- a/src/cpu/o3/thread_context_impl.hh +++ b/src/cpu/o3/thread_context_impl.hh @@ -200,17 +200,10 @@ O3ThreadContext<Impl>::readIntRegFlat(int reg_idx) } template <class Impl> -TheISA::FloatReg -O3ThreadContext<Impl>::readFloatRegFlat(int reg_idx) -{ - return cpu->readArchFloatReg(reg_idx, thread->threadId()); -} - -template <class Impl> TheISA::FloatRegBits O3ThreadContext<Impl>::readFloatRegBitsFlat(int reg_idx) { - return cpu->readArchFloatRegInt(reg_idx, thread->threadId()); + return cpu->readArchFloatRegBits(reg_idx, thread->threadId()); } template <class Impl> @@ -253,18 +246,9 @@ O3ThreadContext<Impl>::setIntRegFlat(int reg_idx, uint64_t val) template <class Impl> void -O3ThreadContext<Impl>::setFloatRegFlat(int reg_idx, FloatReg val) -{ - cpu->setArchFloatReg(reg_idx, val, thread->threadId()); - - conditionalSquash(); -} - -template <class Impl> -void O3ThreadContext<Impl>::setFloatRegBitsFlat(int reg_idx, FloatRegBits val) { - cpu->setArchFloatRegInt(reg_idx, val, thread->threadId()); + cpu->setArchFloatRegBits(reg_idx, val, thread->threadId()); conditionalSquash(); } |