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-rw-r--r--src/cpu/simple/timing.cc8
-rw-r--r--src/cpu/simple/timing.hh7
2 files changed, 7 insertions, 8 deletions
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index fa7bb4f86..1c79fcf6b 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -168,9 +168,7 @@ TimingSimpleCPU::resume()
delete fetchEvent;
}
- fetchEvent =
- new EventWrapper<TimingSimpleCPU, &TimingSimpleCPU::fetch>(this, false);
- fetchEvent->schedule(nextCycle());
+ fetchEvent = new FetchEvent(this, nextCycle());
}
changeState(SimObject::Running);
@@ -224,9 +222,7 @@ TimingSimpleCPU::activateContext(int thread_num, int delay)
_status = Running;
// kick things off by initiating the fetch of the next instruction
- fetchEvent =
- new EventWrapper<TimingSimpleCPU, &TimingSimpleCPU::fetch>(this, false);
- fetchEvent->schedule(nextCycle(curTick + cycles(delay)));
+ fetchEvent = new FetchEvent(this, nextCycle(curTick + cycles(delay)));
}
diff --git a/src/cpu/simple/timing.hh b/src/cpu/simple/timing.hh
index ef062d24a..e65cbe46b 100644
--- a/src/cpu/simple/timing.hh
+++ b/src/cpu/simple/timing.hh
@@ -66,8 +66,6 @@ class TimingSimpleCPU : public BaseSimpleCPU
Event *drainEvent;
- Event *fetchEvent;
-
private:
class CpuPort : public Port
@@ -199,7 +197,12 @@ class TimingSimpleCPU : public BaseSimpleCPU
void completeIfetch(PacketPtr );
void completeDataAccess(PacketPtr );
void advanceInst(Fault fault);
+
private:
+
+ typedef EventWrapper<TimingSimpleCPU, &TimingSimpleCPU::fetch> FetchEvent;
+ FetchEvent *fetchEvent;
+
void completeDrain();
};