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-rw-r--r--src/mem/XBar.py18
-rw-r--r--src/mem/coherent_xbar.cc3
-rw-r--r--src/mem/coherent_xbar.hh5
3 files changed, 23 insertions, 3 deletions
diff --git a/src/mem/XBar.py b/src/mem/XBar.py
index 59f0d8d8d..655d9808a 100644
--- a/src/mem/XBar.py
+++ b/src/mem/XBar.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2012, 2015 ARM Limited
+# Copyright (c) 2012, 2015, 2017 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
@@ -106,6 +106,10 @@ class CoherentXBar(BaseXBar):
point_of_coherency = Param.Bool(False, "Consider this crossbar the " \
"point of coherency")
+ # Specify whether this crossbar is the point of unification.
+ point_of_unification = Param.Bool(False, "Consider this crossbar the " \
+ "point of unification")
+
system = Param.System(Parent.any, "System that the crossbar belongs to.")
class SnoopFilter(SimObject):
@@ -139,6 +143,11 @@ class L2XBar(CoherentXBar):
# the crossbar
snoop_filter = SnoopFilter(lookup_latency = 0)
+ # This specialisation of the coherent crossbar is to be considered
+ # the point of unification, it connects the dcache and the icache
+ # to the first level of unified cache.
+ point_of_unification = True
+
# One of the key coherent crossbar instances is the system
# interconnect, tying together the CPU clusters, GPUs, and any I/O
# coherent masters, and DRAM controllers.
@@ -161,6 +170,13 @@ class SystemXBar(CoherentXBar):
# caches.
point_of_coherency = True
+ # This specialisation of the coherent crossbar is to be considered
+ # the point of unification, it connects the dcache and the icache
+ # to the first level of unified cache. This is needed for systems
+ # without caches where the SystemXBar is also the point of
+ # unification.
+ point_of_unification = True
+
# In addition to the system interconnect, we typically also have one
# or more on-chip I/O crossbars. Note that at some point we might want
# to also define an off-chip I/O crossbar such as PCIe.
diff --git a/src/mem/coherent_xbar.cc b/src/mem/coherent_xbar.cc
index ede409503..e90f9c1c8 100644
--- a/src/mem/coherent_xbar.cc
+++ b/src/mem/coherent_xbar.cc
@@ -58,7 +58,8 @@
CoherentXBar::CoherentXBar(const CoherentXBarParams *p)
: BaseXBar(p), system(p->system), snoopFilter(p->snoop_filter),
snoopResponseLatency(p->snoop_response_latency),
- pointOfCoherency(p->point_of_coherency)
+ pointOfCoherency(p->point_of_coherency),
+ pointOfUnification(p->point_of_unification)
{
// create the ports based on the size of the master and slave
// vector ports, and the presence of the default port, the ports
diff --git a/src/mem/coherent_xbar.hh b/src/mem/coherent_xbar.hh
index edfc47d4b..214a29071 100644
--- a/src/mem/coherent_xbar.hh
+++ b/src/mem/coherent_xbar.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2011-2015 ARM Limited
+ * Copyright (c) 2011-2015, 2017 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -278,6 +278,9 @@ class CoherentXBar : public BaseXBar
/** Is this crossbar the point of coherency? **/
const bool pointOfCoherency;
+ /** Is this crossbar the point of unification? **/
+ const bool pointOfUnification;
+
/**
* Upstream caches need this packet until true is returned, so
* hold it for deletion until a subsequent call