diff options
Diffstat (limited to 'src/sim')
-rw-r--r-- | src/sim/System.py | 2 | ||||
-rw-r--r-- | src/sim/system.cc | 12 | ||||
-rw-r--r-- | src/sim/system.hh | 8 |
3 files changed, 19 insertions, 3 deletions
diff --git a/src/sim/System.py b/src/sim/System.py index 2cc171881..302e2fa60 100644 --- a/src/sim/System.py +++ b/src/sim/System.py @@ -63,6 +63,8 @@ class System(MemObject): # I/O bridge or cache mem_ranges = VectorParam.AddrRange([], "Ranges that constitute main memory") + cache_line_size = Param.Unsigned(64, "Cache line size in bytes") + work_item_id = Param.Int(-1, "specific work item id") num_work_ids = Param.Int(16, "Number of distinct work item types") work_begin_cpu_id_exit = Param.Int(-1, diff --git a/src/sim/system.cc b/src/sim/system.cc index 03f8f8180..f9799d26f 100644 --- a/src/sim/system.cc +++ b/src/sim/system.cc @@ -1,5 +1,5 @@ /* - * Copyright (c) 2011-2012 ARM Limited + * Copyright (c) 2011-2013 ARM Limited * All rights reserved * * The license below extends only to copyright in the software and shall @@ -78,12 +78,13 @@ System::System(Params *p) _numContexts(0), pagePtr(0), init_param(p->init_param), - physProxy(_systemPort), - virtProxy(_systemPort), + physProxy(_systemPort, p->cache_line_size), + virtProxy(_systemPort, p->cache_line_size), loadAddrMask(p->load_addr_mask), nextPID(0), physmem(name() + ".physmem", p->memories), memoryMode(p->mem_mode), + _cacheLineSize(p->cache_line_size), workItemsBegin(0), workItemsEnd(0), numWorkIds(p->num_work_ids), @@ -100,6 +101,11 @@ System::System(Params *p) debugSymbolTable = new SymbolTable; } + // check if the cache line size is a value known to work + if (!(_cacheLineSize == 16 || _cacheLineSize == 32 || + _cacheLineSize == 64 || _cacheLineSize == 128)) + warn_once("Cache line size is neither 16, 32, 64 nor 128 bytes.\n"); + // Get the generic system master IDs MasterID tmp_id M5_VAR_USED; tmp_id = getMasterId("writebacks"); diff --git a/src/sim/system.hh b/src/sim/system.hh index e7407105a..6e44d0ab5 100644 --- a/src/sim/system.hh +++ b/src/sim/system.hh @@ -179,6 +179,11 @@ class System : public MemObject void setMemoryMode(Enums::MemoryMode mode); /** @} */ + /** + * Get the cache line size of the system. + */ + unsigned int cacheLineSize() const { return _cacheLineSize; } + PCEventQueue pcEventQueue; std::vector<ThreadContext *> threadContexts; @@ -263,6 +268,9 @@ class System : public MemObject PhysicalMemory physmem; Enums::MemoryMode memoryMode; + + const unsigned int _cacheLineSize; + uint64_t workItemsBegin; uint64_t workItemsEnd; uint32_t numWorkIds; |