diff options
Diffstat (limited to 'src/systemc/tests/tlm/endian_conv')
-rw-r--r-- | src/systemc/tests/tlm/endian_conv/golden/test_endian_conv.log | 1204 | ||||
-rw-r--r-- | src/systemc/tests/tlm/endian_conv/input.txt | 198 | ||||
-rw-r--r-- | src/systemc/tests/tlm/endian_conv/test_endian_conv.cpp | 419 | ||||
-rw-r--r-- | src/systemc/tests/tlm/endian_conv/testall.py | 456 |
4 files changed, 2277 insertions, 0 deletions
diff --git a/src/systemc/tests/tlm/endian_conv/golden/test_endian_conv.log b/src/systemc/tests/tlm/endian_conv/golden/test_endian_conv.log new file mode 100644 index 000000000..356868498 --- /dev/null +++ b/src/systemc/tests/tlm/endian_conv/golden/test_endian_conv.log @@ -0,0 +1,1204 @@ +SystemC Simulation + +TLM-2 Endianness Conversion Helper Functions Tester +March 2008 +January 2012 Updated to read from endian_conv/input.txt + +0 enter {R|W}, addr=a, len=l, bus width=b, word width=w, initiator offset=i, be={x|01}, stream width=s +Pool status: +enter initiator memory state = (2048 characters) +enter target memory state = (2048 characters) +enter converter choice = (0 => generic, 1 => word, 2 => aligned, 3 => single) +Initiator Intent + Cmd = R + Addr = 0 + Len = 16 + Bus Width = 8 + Data Word = 4 + Initiator offset = 0 + Byte enables = x + Byte enable length = 0 + Streaming width = 16 + Initiator memory = xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + Target memory = 0123456789abcdefghijklmnopqrstuvwxyz + Converter = 0 + +Converted Transaction + Addr = 0 + Len = 16 + Txn data pointer = changed + Byte enables and byte enable pointer = 1111111111111111, changed + Byte enable length = 16 + Streaming width = 16 + +Memory States after Transaction + initiator = 45670123cdef89abxxxxxxxxxxxxxxxxxxxx + target = 0123456789abcdefghijklmnopqrstuvwxyz + +1 enter {R|W}, addr=a, len=l, bus width=b, word width=w, initiator offset=i, be={x|01}, stream width=s +Pool status: +enter initiator memory state = (2048 characters) +enter target memory state = (2048 characters) +enter converter choice = (0 => generic, 1 => word, 2 => aligned, 3 => single) +Initiator Intent + Cmd = R + Addr = 0 + Len = 16 + Bus Width = 8 + Data Word = 4 + Initiator offset = 0 + Byte enables = x + Byte enable length = 0 + Streaming width = 16 + Initiator memory = xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + Target memory = 0123456789abcdefghijklmnopqrstuvwxyz + Converter = 1 + +Converted Transaction + Addr = 0 + Len = 16 + Txn data pointer = changed + Byte enables and byte enable pointer = 1111111111111111, changed + Byte enable length = 16 + Streaming width = 16 + +Memory States after Transaction + initiator = 45670123cdef89abxxxxxxxxxxxxxxxxxxxx + target = 0123456789abcdefghijklmnopqrstuvwxyz + +2 enter {R|W}, addr=a, len=l, bus width=b, word width=w, initiator offset=i, be={x|01}, stream width=s +Pool status: +enter initiator memory state = (2048 characters) +enter target memory state = (2048 characters) +enter converter choice = (0 => generic, 1 => word, 2 => aligned, 3 => single) +Initiator Intent + Cmd = R + Addr = 16 + Len = 16 + Bus Width = 8 + Data Word = 4 + Initiator offset = 0 + Byte enables = x + Byte enable length = 0 + Streaming width = 16 + Initiator memory = xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + Target memory = 0123456789abcdefghijklmnopqrstuvwxyz + Converter = 2 + +Converted Transaction + Addr = 16 + Len = 16 + Txn data pointer = changed + Byte enable length = 0 + Streaming width = 16 + +Memory States after Transaction + initiator = klmnghijstuvopqrxxxxxxxxxxxxxxxxxxxx + target = 0123456789abcdefghijklmnopqrstuvwxyz + +3 enter {R|W}, addr=a, len=l, bus width=b, word width=w, initiator offset=i, be={x|01}, stream width=s +Pool status: +enter initiator memory state = (2048 characters) +enter target memory state = (2048 characters) +enter converter choice = (0 => generic, 1 => word, 2 => aligned, 3 => single) +Initiator Intent + Cmd = W + Addr = 16 + Len = 16 + Bus Width = 8 + Data Word = 4 + Initiator offset = 4 + Byte enables = x + Byte enable length = 0 + Streaming width = 16 + Initiator memory = 0123456789abcdefghijklmnopqrstuvwxyz + Target memory = xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + Converter = 0 + +Converted Transaction + Addr = 16 + Len = 16 + Txn data pointer = changed + Byte enables and byte enable pointer = 1111111111111111, changed + Byte enable length = 16 + Streaming width = 16 + +Memory States after Transaction + initiator = 0123456789abcdefghijklmnopqrstuvwxyz + target = xxxxxxxxxxxxxxxx89ab4567ghijcdefxxxx + +4 enter {R|W}, addr=a, len=l, bus width=b, word width=w, initiator offset=i, be={x|01}, stream width=s +Pool status: +Pool status: +Pool status: (16,16) +Pool status: (16,16) +enter initiator memory state = (2048 characters) +enter target memory state = (2048 characters) +enter converter choice = (0 => generic, 1 => word, 2 => aligned, 3 => single) +Initiator Intent + Cmd = W + Addr = 16 + Len = 16 + Bus Width = 8 + Data Word = 4 + Initiator offset = 4 + Byte enables = x + Byte enable length = 0 + Streaming width = 16 + Initiator memory = 0123456789abcdefghijklmnopqrstuvwxyz + Target memory = xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + Converter = 1 + +Converted Transaction + Addr = 16 + Len = 16 + Txn data pointer = changed + Byte enables and byte enable pointer = 1111111111111111, changed + Byte enable length = 16 + Streaming width = 16 + +Memory States after Transaction + initiator = 0123456789abcdefghijklmnopqrstuvwxyz + target = xxxxxxxxxxxxxxxx89ab4567ghijcdefxxxx + +5 enter {R|W}, addr=a, len=l, bus width=b, word width=w, initiator offset=i, be={x|01}, stream width=s +Pool status: +enter initiator memory state = (2048 characters) +enter target memory state = (2048 characters) +enter converter choice = (0 => generic, 1 => word, 2 => aligned, 3 => single) +Initiator Intent + Cmd = W + Addr = 0 + Len = 16 + Bus Width = 8 + Data Word = 4 + Initiator offset = 0 + Byte enables = x + Byte enable length = 0 + Streaming width = 16 + Initiator memory = 0123456789abcdefghijklmnopqrstuvwxyz + Target memory = xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + Converter = 2 + +Converted Transaction + Addr = 0 + Len = 16 + Txn data pointer = changed + Byte enable length = 0 + Streaming width = 16 + +Memory States after Transaction + initiator = 0123456789abcdefghijklmnopqrstuvwxyz + target = 45670123cdef89abxxxxxxxxxxxxxxxxxxxx + +6 enter {R|W}, addr=a, len=l, bus width=b, word width=w, initiator offset=i, be={x|01}, stream width=s +Pool status: +enter initiator memory state = (2048 characters) +enter target memory state = (2048 characters) +enter converter choice = (0 => generic, 1 => word, 2 => aligned, 3 => single) +Initiator Intent + Cmd = R + Addr = 0 + Len = 16 + Bus Width = 8 + Data Word = 4 + Initiator offset = 0 + Byte enables = 1111000011110000 + Byte enable length = 16 + Streaming width = 16 + Initiator memory = xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + Target memory = 0123456789abcdefghijklmnopqrstuvwxyz + Converter = 0 + +Converted Transaction + Addr = 0 + Len = 16 + Txn data pointer = changed + Byte enables and byte enable pointer = 0000111100001111, changed + Byte enable length = 16 + Streaming width = 16 + +Memory States after Transaction + initiator = 4567xxxxcdefxxxxxxxxxxxxxxxxxxxxxxxx + target = 0123456789abcdefghijklmnopqrstuvwxyz + +0 enter {R|W}, addr=a, len=l, bus width=b, word width=w, initiator offset=i, be={x|01}, stream width=s +Pool status: +enter initiator memory state = (2048 characters) +enter target memory state = (2048 characters) +enter converter choice = (0 => generic, 1 => word, 2 => aligned, 3 => single) +Initiator Intent + Cmd = R + Addr = 0 + Len = 16 + Bus Width = 8 + Data Word = 4 + Initiator offset = 0 + Byte enables = 1111000011110000 + Byte enable length = 16 + Streaming width = 16 + Initiator memory = xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + Target memory = 0123456789abcdefghijklmnopqrstuvwxyz + Converter = 1 + +Converted Transaction + Addr = 0 + Len = 16 + Txn data pointer = changed + Byte enables and byte enable pointer = 0000111100001111, changed + Byte enable length = 16 + Streaming width = 16 + +Memory States after Transaction + initiator = 4567xxxxcdefxxxxxxxxxxxxxxxxxxxxxxxx + target = 0123456789abcdefghijklmnopqrstuvwxyz + +1 enter {R|W}, addr=a, len=l, bus width=b, word width=w, initiator offset=i, be={x|01}, stream width=s +Pool status: +enter initiator memory state = (2048 characters) +enter target memory state = (2048 characters) +enter converter choice = (0 => generic, 1 => word, 2 => aligned, 3 => single) +Initiator Intent + Cmd = R + Addr = 16 + Len = 16 + Bus Width = 8 + Data Word = 4 + Initiator offset = 0 + Byte enables = 1111000011110000 + Byte enable length = 16 + Streaming width = 16 + Initiator memory = xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + Target memory = 0123456789abcdefghijklmnopqrstuvwxyz + Converter = 2 + +Converted Transaction + Addr = 16 + Len = 16 + Txn data pointer = changed + Byte enables and byte enable pointer = 0000111100001111, changed + Byte enable length = 16 + Streaming width = 16 + +Memory States after Transaction + initiator = klmnxxxxstuvxxxxxxxxxxxxxxxxxxxxxxxx + target = 0123456789abcdefghijklmnopqrstuvwxyz + +2 enter {R|W}, addr=a, len=l, bus width=b, word width=w, initiator offset=i, be={x|01}, stream width=s +Pool status: +enter initiator memory state = (2048 characters) +enter target memory state = (2048 characters) +enter converter choice = (0 => generic, 1 => word, 2 => aligned, 3 => single) +Initiator Intent + Cmd = W + Addr = 16 + Len = 16 + Bus Width = 8 + Data Word = 4 + Initiator offset = 4 + Byte enables = 1111000000001111 + Byte enable length = 16 + Streaming width = 16 + Initiator memory = 0123456789abcdefghijklmnopqrstuvwxyz + Target memory = xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + Converter = 0 + +Converted Transaction + Addr = 16 + Len = 16 + Txn data pointer = changed + Byte enables and byte enable pointer = 0000111111110000, changed + Byte enable length = 16 + Streaming width = 16 + +Memory States after Transaction + initiator = 0123456789abcdefghijklmnopqrstuvwxyz + target = xxxxxxxxxxxxxxxxxxxx4567ghijxxxxxxxx + +3 enter {R|W}, addr=a, len=l, bus width=b, word width=w, initiator offset=i, be={x|01}, stream width=s +Pool status: +enter initiator memory state = (2048 characters) +enter target memory state = (2048 characters) +enter converter choice = (0 => generic, 1 => word, 2 => aligned, 3 => single) +Initiator Intent + Cmd = W + Addr = 16 + Len = 16 + Bus Width = 8 + Data Word = 4 + Initiator offset = 4 + Byte enables = 1111000000001111 + Byte enable length = 16 + Streaming width = 16 + Initiator memory = 0123456789abcdefghijklmnopqrstuvwxyz + Target memory = xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + Converter = 1 + +Converted Transaction + Addr = 16 + Len = 16 + Txn data pointer = changed + Byte enables and byte enable pointer = 0000111111110000, changed + Byte enable length = 16 + Streaming width = 16 + +Memory States after Transaction + initiator = 0123456789abcdefghijklmnopqrstuvwxyz + target = xxxxxxxxxxxxxxxxxxxx4567ghijxxxxxxxx + +4 enter {R|W}, addr=a, len=l, bus width=b, word width=w, initiator offset=i, be={x|01}, stream width=s +Pool status: +Pool status: (32,32) +Pool status: (32,32) (32,32) +Pool status: (32,32) (32,32) +enter initiator memory state = (2048 characters) +enter target memory state = (2048 characters) +enter converter choice = (0 => generic, 1 => word, 2 => aligned, 3 => single) +Initiator Intent + Cmd = W + Addr = 0 + Len = 16 + Bus Width = 8 + Data Word = 4 + Initiator offset = 0 + Byte enables = 1111000000001111 + Byte enable length = 16 + Streaming width = 16 + Initiator memory = 0123456789abcdefghijklmnopqrstuvwxyz + Target memory = xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + Converter = 2 + +Converted Transaction + Addr = 0 + Len = 16 + Txn data pointer = changed + Byte enables and byte enable pointer = 0000111111110000, changed + Byte enable length = 16 + Streaming width = 16 + +Memory States after Transaction + initiator = 0123456789abcdefghijklmnopqrstuvwxyz + target = xxxx0123cdefxxxxxxxxxxxxxxxxxxxxxxxx + +5 enter {R|W}, addr=a, len=l, bus width=b, word width=w, initiator offset=i, be={x|01}, stream width=s +Pool status: (32,32) +enter initiator memory state = (2048 characters) +enter target memory state = (2048 characters) +enter converter choice = (0 => generic, 1 => word, 2 => aligned, 3 => single) +Initiator Intent + Cmd = R + Addr = 20 + Len = 4 + Bus Width = 8 + Data Word = 4 + Initiator offset = 0 + Byte enables = x + Byte enable length = 0 + Streaming width = 4 + Initiator memory = xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + Target memory = 0123456789abcdefghijklmnopqrstuvwxyz + Converter = 0 + +Converted Transaction + Addr = 16 + Len = 8 + Txn data pointer = changed + Byte enables and byte enable pointer = 11110000, changed + Byte enable length = 8 + Streaming width = 8 + +Memory States after Transaction + initiator = ghijxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + target = 0123456789abcdefghijklmnopqrstuvwxyz + +6 enter {R|W}, addr=a, len=l, bus width=b, word width=w, initiator offset=i, be={x|01}, stream width=s +Pool status: (32,32) +enter initiator memory state = (2048 characters) +enter target memory state = (2048 characters) +enter converter choice = (0 => generic, 1 => word, 2 => aligned, 3 => single) +Initiator Intent + Cmd = R + Addr = 20 + Len = 4 + Bus Width = 8 + Data Word = 4 + Initiator offset = 0 + Byte enables = x + Byte enable length = 0 + Streaming width = 4 + Initiator memory = xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + Target memory = 0123456789abcdefghijklmnopqrstuvwxyz + Converter = 1 + +Converted Transaction + Addr = 16 + Len = 4 + Txn data pointer = changed + Byte enables and byte enable pointer = 1111, changed + Byte enable length = 4 + Streaming width = 4 + +Memory States after Transaction + initiator = ghijxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + target = 0123456789abcdefghijklmnopqrstuvwxyz + +0 enter {R|W}, addr=a, len=l, bus width=b, word width=w, initiator offset=i, be={x|01}, stream width=s +Pool status: (32,32) +enter initiator memory state = (2048 characters) +enter target memory state = (2048 characters) +enter converter choice = (0 => generic, 1 => word, 2 => aligned, 3 => single) +Initiator Intent + Cmd = R + Addr = 20 + Len = 4 + Bus Width = 8 + Data Word = 4 + Initiator offset = 0 + Byte enables = x + Byte enable length = 0 + Streaming width = 4 + Initiator memory = xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + Target memory = 0123456789abcdefghijklmnopqrstuvwxyz + Converter = 3 + +Converted Transaction + Addr = 16 + Len = 4 + Txn data pointer = unchanged + Byte enable length = 0 + Streaming width = 4 + +Memory States after Transaction + initiator = ghijxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + target = 0123456789abcdefghijklmnopqrstuvwxyz + +1 enter {R|W}, addr=a, len=l, bus width=b, word width=w, initiator offset=i, be={x|01}, stream width=s +Pool status: (32,32) +enter initiator memory state = (2048 characters) +enter target memory state = (2048 characters) +enter converter choice = (0 => generic, 1 => word, 2 => aligned, 3 => single) +Initiator Intent + Cmd = W + Addr = 28 + Len = 4 + Bus Width = 8 + Data Word = 4 + Initiator offset = 4 + Byte enables = x + Byte enable length = 0 + Streaming width = 4 + Initiator memory = 0123456789abcdefghijklmnopqrstuvwxyz + Target memory = xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + Converter = 0 + +Converted Transaction + Addr = 24 + Len = 8 + Txn data pointer = changed + Byte enables and byte enable pointer = 11110000, changed + Byte enable length = 8 + Streaming width = 8 + +Memory States after Transaction + initiator = 0123456789abcdefghijklmnopqrstuvwxyz + target = xxxxxxxxxxxxxxxxxxxxxxxx4567xxxxxxxx + +2 enter {R|W}, addr=a, len=l, bus width=b, word width=w, initiator offset=i, be={x|01}, stream width=s +Pool status: (32,32) +enter initiator memory state = (2048 characters) +enter target memory state = (2048 characters) +enter converter choice = (0 => generic, 1 => word, 2 => aligned, 3 => single) +Initiator Intent + Cmd = W + Addr = 28 + Len = 4 + Bus Width = 8 + Data Word = 4 + Initiator offset = 4 + Byte enables = x + Byte enable length = 0 + Streaming width = 4 + Initiator memory = 0123456789abcdefghijklmnopqrstuvwxyz + Target memory = xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + Converter = 1 + +Converted Transaction + Addr = 24 + Len = 4 + Txn data pointer = changed + Byte enables and byte enable pointer = 1111, changed + Byte enable length = 4 + Streaming width = 4 + +Memory States after Transaction + initiator = 0123456789abcdefghijklmnopqrstuvwxyz + target = xxxxxxxxxxxxxxxxxxxxxxxx4567xxxxxxxx + +3 enter {R|W}, addr=a, len=l, bus width=b, word width=w, initiator offset=i, be={x|01}, stream width=s +Pool status: (32,32) +enter initiator memory state = (2048 characters) +enter target memory state = (2048 characters) +enter converter choice = (0 => generic, 1 => word, 2 => aligned, 3 => single) +Initiator Intent + Cmd = W + Addr = 28 + Len = 4 + Bus Width = 8 + Data Word = 4 + Initiator offset = 4 + Byte enables = x + Byte enable length = 0 + Streaming width = 4 + Initiator memory = 0123456789abcdefghijklmnopqrstuvwxyz + Target memory = xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + Converter = 3 + +Converted Transaction + Addr = 24 + Len = 4 + Txn data pointer = unchanged + Byte enable length = 0 + Streaming width = 4 + +Memory States after Transaction + initiator = 0123456789abcdefghijklmnopqrstuvwxyz + target = xxxxxxxxxxxxxxxxxxxxxxxx4567xxxxxxxx + +4 enter {R|W}, addr=a, len=l, bus width=b, word width=w, initiator offset=i, be={x|01}, stream width=s +Pool status: +Pool status: (32,32) +Pool status: (32,32) (32,32) +Pool status: (32,32) (32,32) +enter initiator memory state = (2048 characters) +enter target memory state = (2048 characters) +enter converter choice = (0 => generic, 1 => word, 2 => aligned, 3 => single) +Initiator Intent + Cmd = R + Addr = 21 + Len = 2 + Bus Width = 8 + Data Word = 2 + Initiator offset = 0 + Byte enables = 11 + Byte enable length = 2 + Streaming width = 2 + Initiator memory = xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + Target memory = 0123456789abcdefghijklmnopqrstuvwxyz + Converter = 0 + +Converted Transaction + Addr = 16 + Len = 8 + Txn data pointer = changed + Byte enables and byte enable pointer = 01100000, changed + Byte enable length = 8 + Streaming width = 8 + +Memory States after Transaction + initiator = hixxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + target = 0123456789abcdefghijklmnopqrstuvwxyz + +5 enter {R|W}, addr=a, len=l, bus width=b, word width=w, initiator offset=i, be={x|01}, stream width=s +Pool status: (32,32) +enter initiator memory state = (2048 characters) +enter target memory state = (2048 characters) +enter converter choice = (0 => generic, 1 => word, 2 => aligned, 3 => single) +Initiator Intent + Cmd = R + Addr = 21 + Len = 2 + Bus Width = 8 + Data Word = 2 + Initiator offset = 0 + Byte enables = 11 + Byte enable length = 2 + Streaming width = 2 + Initiator memory = xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + Target memory = 0123456789abcdefghijklmnopqrstuvwxyz + Converter = 1 + +Converted Transaction + Addr = 16 + Len = 3 + Txn data pointer = changed + Byte enables and byte enable pointer = 011, changed + Byte enable length = 3 + Streaming width = 3 + +Memory States after Transaction + initiator = hixxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + target = 0123456789abcdefghijklmnopqrstuvwxyz + +6 enter {R|W}, addr=a, len=l, bus width=b, word width=w, initiator offset=i, be={x|01}, stream width=s +Pool status: (32,32) +enter initiator memory state = (2048 characters) +enter target memory state = (2048 characters) +enter converter choice = (0 => generic, 1 => word, 2 => aligned, 3 => single) +Initiator Intent + Cmd = R + Addr = 21 + Len = 2 + Bus Width = 8 + Data Word = 2 + Initiator offset = 0 + Byte enables = 11 + Byte enable length = 2 + Streaming width = 2 + Initiator memory = xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + Target memory = 0123456789abcdefghijklmnopqrstuvwxyz + Converter = 3 + +Converted Transaction + Addr = 17 + Len = 2 + Txn data pointer = unchanged + Byte enables and byte enable pointer = 11, unchanged + Byte enable length = 2 + Streaming width = 2 + +Memory States after Transaction + initiator = hixxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + target = 0123456789abcdefghijklmnopqrstuvwxyz + +0 enter {R|W}, addr=a, len=l, bus width=b, word width=w, initiator offset=i, be={x|01}, stream width=s +Pool status: (32,32) +enter initiator memory state = (2048 characters) +enter target memory state = (2048 characters) +enter converter choice = (0 => generic, 1 => word, 2 => aligned, 3 => single) +Initiator Intent + Cmd = W + Addr = 0 + Len = 4 + Bus Width = 4 + Data Word = 4 + Initiator offset = 25 + Byte enables = 1111 + Byte enable length = 4 + Streaming width = 4 + Initiator memory = 0123456789abcdefghijklmnopqrstuvwxyz + Target memory = xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + Converter = 0 + +Converted Transaction + Addr = 0 + Len = 4 + Txn data pointer = changed + Byte enables and byte enable pointer = 1111, changed + Byte enable length = 4 + Streaming width = 4 + +Memory States after Transaction + initiator = 0123456789abcdefghijklmnopqrstuvwxyz + target = pqrsxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + +1 enter {R|W}, addr=a, len=l, bus width=b, word width=w, initiator offset=i, be={x|01}, stream width=s +Pool status: (32,32) +enter initiator memory state = (2048 characters) +enter target memory state = (2048 characters) +enter converter choice = (0 => generic, 1 => word, 2 => aligned, 3 => single) +Initiator Intent + Cmd = W + Addr = 0 + Len = 4 + Bus Width = 4 + Data Word = 4 + Initiator offset = 25 + Byte enables = 1111 + Byte enable length = 4 + Streaming width = 4 + Initiator memory = 0123456789abcdefghijklmnopqrstuvwxyz + Target memory = xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + Converter = 1 + +Converted Transaction + Addr = 0 + Len = 4 + Txn data pointer = changed + Byte enables and byte enable pointer = 1111, changed + Byte enable length = 4 + Streaming width = 4 + +Memory States after Transaction + initiator = 0123456789abcdefghijklmnopqrstuvwxyz + target = pqrsxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + +2 enter {R|W}, addr=a, len=l, bus width=b, word width=w, initiator offset=i, be={x|01}, stream width=s +Pool status: (32,32) +enter initiator memory state = (2048 characters) +enter target memory state = (2048 characters) +enter converter choice = (0 => generic, 1 => word, 2 => aligned, 3 => single) +Initiator Intent + Cmd = W + Addr = 0 + Len = 4 + Bus Width = 4 + Data Word = 4 + Initiator offset = 25 + Byte enables = 1111 + Byte enable length = 4 + Streaming width = 4 + Initiator memory = 0123456789abcdefghijklmnopqrstuvwxyz + Target memory = xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + Converter = 3 + +Converted Transaction + Addr = 0 + Len = 4 + Txn data pointer = unchanged + Byte enables and byte enable pointer = 1111, unchanged + Byte enable length = 4 + Streaming width = 4 + +Memory States after Transaction + initiator = 0123456789abcdefghijklmnopqrstuvwxyz + target = pqrsxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + +3 enter {R|W}, addr=a, len=l, bus width=b, word width=w, initiator offset=i, be={x|01}, stream width=s +Pool status: (32,32) +enter initiator memory state = (2048 characters) +enter target memory state = (2048 characters) +enter converter choice = (0 => generic, 1 => word, 2 => aligned, 3 => single) +Initiator Intent + Cmd = R + Addr = 13 + Len = 14 + Bus Width = 8 + Data Word = 2 + Initiator offset = 0 + Byte enables = x + Byte enable length = 0 + Streaming width = 14 + Initiator memory = xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + Target memory = 0123456789abcdefghijklmnopqrstuvwxyz + Converter = 0 + +Converted Transaction + Addr = 8 + Len = 24 + Txn data pointer = changed + Byte enables and byte enable pointer = 111000001111111100000111, changed + Byte enable length = 24 + Streaming width = 24 + +Memory States after Transaction + initiator = 9an8lmjkhivgtuxxxxxxxxxxxxxxxxxxxxxx + target = 0123456789abcdefghijklmnopqrstuvwxyz + +4 enter {R|W}, addr=a, len=l, bus width=b, word width=w, initiator offset=i, be={x|01}, stream width=s +Pool status: +Pool status: (32,32) +Pool status: (32,32) (32,32) +Pool status: (32,32) (32,32) +enter initiator memory state = (2048 characters) +enter target memory state = (2048 characters) +enter converter choice = (0 => generic, 1 => word, 2 => aligned, 3 => single) +Initiator Intent + Cmd = W + Addr = 5 + Len = 4 + Bus Width = 4 + Data Word = 1 + Initiator offset = 25 + Byte enables = x + Byte enable length = 0 + Streaming width = 4 + Initiator memory = 0123456789abcdefghijklmnopqrstuvwxyz + Target memory = xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + Converter = 0 + +Converted Transaction + Addr = 4 + Len = 8 + Txn data pointer = changed + Byte enables and byte enable pointer = 11100001, changed + Byte enable length = 8 + Streaming width = 8 + +Memory States after Transaction + initiator = 0123456789abcdefghijklmnopqrstuvwxyz + target = xxxxrqpxxxxsxxxxxxxxxxxxxxxxxxxxxxxx + +5 enter {R|W}, addr=a, len=l, bus width=b, word width=w, initiator offset=i, be={x|01}, stream width=s +Pool status: (32,32) +enter initiator memory state = (2048 characters) +enter target memory state = (2048 characters) +enter converter choice = (0 => generic, 1 => word, 2 => aligned, 3 => single) +Initiator Intent + Cmd = R + Addr = 10 + Len = 12 + Bus Width = 4 + Data Word = 4 + Initiator offset = 0 + Byte enables = 111100001111 + Byte enable length = 12 + Streaming width = 12 + Initiator memory = xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + Target memory = 0123456789abcdefghijklmnopqrstuvwxyz + Converter = 0 + +Converted Transaction + Addr = 8 + Len = 16 + Txn data pointer = changed + Byte enables and byte enable pointer = 1100001111000011, changed + Byte enable length = 16 + Streaming width = 16 + +Memory States after Transaction + initiator = ef89xxxxmnghxxxxxxxxxxxxxxxxxxxxxxxx + target = 0123456789abcdefghijklmnopqrstuvwxyz + +6 enter {R|W}, addr=a, len=l, bus width=b, word width=w, initiator offset=i, be={x|01}, stream width=s +Pool status: (32,32) +enter initiator memory state = (2048 characters) +enter target memory state = (2048 characters) +enter converter choice = (0 => generic, 1 => word, 2 => aligned, 3 => single) +Initiator Intent + Cmd = W + Addr = 15 + Len = 8 + Bus Width = 8 + Data Word = 4 + Initiator offset = 25 + Byte enables = 00001111 + Byte enable length = 8 + Streaming width = 8 + Initiator memory = 0123456789abcdefghijklmnopqrstuvwxyz + Target memory = xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + Converter = 0 + +Converted Transaction + Addr = 8 + Len = 16 + Txn data pointer = changed + Byte enables and byte enable pointer = 0000000001111000, changed + Byte enable length = 16 + Streaming width = 16 + +Memory States after Transaction + initiator = 0123456789abcdefghijklmnopqrstuvwxyz + target = xxxxxxxxxxxxxxxxxtuvwxxxxxxxxxxxxxxx + +0 enter {R|W}, addr=a, len=l, bus width=b, word width=w, initiator offset=i, be={x|01}, stream width=s +Pool status: (32,32) +enter initiator memory state = (2048 characters) +enter target memory state = (2048 characters) +enter converter choice = (0 => generic, 1 => word, 2 => aligned, 3 => single) +Initiator Intent + Cmd = R + Addr = 13 + Len = 14 + Bus Width = 8 + Data Word = 2 + Initiator offset = 0 + Byte enables = x + Byte enable length = 0 + Streaming width = 14 + Initiator memory = xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + Target memory = 0123456789abcdefghijklmnopqrstuvwxyz + Converter = 1 + +Converted Transaction + Addr = 8 + Len = 24 + Txn data pointer = changed + Byte enables and byte enable pointer = 111000001111111100000111, changed + Byte enable length = 24 + Streaming width = 24 + +Memory States after Transaction + initiator = 9an8lmjkhivgtuxxxxxxxxxxxxxxxxxxxxxx + target = 0123456789abcdefghijklmnopqrstuvwxyz + +1 enter {R|W}, addr=a, len=l, bus width=b, word width=w, initiator offset=i, be={x|01}, stream width=s +Pool status: (32,32) +enter initiator memory state = (2048 characters) +enter target memory state = (2048 characters) +enter converter choice = (0 => generic, 1 => word, 2 => aligned, 3 => single) +Initiator Intent + Cmd = W + Addr = 5 + Len = 4 + Bus Width = 4 + Data Word = 1 + Initiator offset = 25 + Byte enables = x + Byte enable length = 0 + Streaming width = 4 + Initiator memory = 0123456789abcdefghijklmnopqrstuvwxyz + Target memory = xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + Converter = 1 + +Converted Transaction + Addr = 4 + Len = 8 + Txn data pointer = changed + Byte enables and byte enable pointer = 11100001, changed + Byte enable length = 8 + Streaming width = 8 + +Memory States after Transaction + initiator = 0123456789abcdefghijklmnopqrstuvwxyz + target = xxxxrqpxxxxsxxxxxxxxxxxxxxxxxxxxxxxx + +2 enter {R|W}, addr=a, len=l, bus width=b, word width=w, initiator offset=i, be={x|01}, stream width=s +Pool status: (32,32) +enter initiator memory state = (2048 characters) +enter target memory state = (2048 characters) +enter converter choice = (0 => generic, 1 => word, 2 => aligned, 3 => single) +Initiator Intent + Cmd = R + Addr = 10 + Len = 12 + Bus Width = 4 + Data Word = 4 + Initiator offset = 0 + Byte enables = 111100001111 + Byte enable length = 12 + Streaming width = 12 + Initiator memory = xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + Target memory = 0123456789abcdefghijklmnopqrstuvwxyz + Converter = 1 + +Converted Transaction + Addr = 8 + Len = 16 + Txn data pointer = changed + Byte enables and byte enable pointer = 1100001111000011, changed + Byte enable length = 16 + Streaming width = 16 + +Memory States after Transaction + initiator = ef89xxxxmnghxxxxxxxxxxxxxxxxxxxxxxxx + target = 0123456789abcdefghijklmnopqrstuvwxyz + +3 enter {R|W}, addr=a, len=l, bus width=b, word width=w, initiator offset=i, be={x|01}, stream width=s +Pool status: (32,32) +enter initiator memory state = (2048 characters) +enter target memory state = (2048 characters) +enter converter choice = (0 => generic, 1 => word, 2 => aligned, 3 => single) +Initiator Intent + Cmd = W + Addr = 15 + Len = 8 + Bus Width = 8 + Data Word = 4 + Initiator offset = 25 + Byte enables = 00001111 + Byte enable length = 8 + Streaming width = 8 + Initiator memory = 0123456789abcdefghijklmnopqrstuvwxyz + Target memory = xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + Converter = 1 + +Converted Transaction + Addr = 8 + Len = 16 + Txn data pointer = changed + Byte enables and byte enable pointer = 0000000001111000, changed + Byte enable length = 16 + Streaming width = 16 + +Memory States after Transaction + initiator = 0123456789abcdefghijklmnopqrstuvwxyz + target = xxxxxxxxxxxxxxxxxtuvwxxxxxxxxxxxxxxx + +4 enter {R|W}, addr=a, len=l, bus width=b, word width=w, initiator offset=i, be={x|01}, stream width=s +Pool status: +Pool status: (32,32) +Pool status: (32,32) (32,32) +Pool status: (32,32) (32,32) +enter initiator memory state = (2048 characters) +enter target memory state = (2048 characters) +enter converter choice = (0 => generic, 1 => word, 2 => aligned, 3 => single) +Initiator Intent + Cmd = R + Addr = 13 + Len = 14 + Bus Width = 8 + Data Word = 2 + Initiator offset = 0 + Byte enables = x + Byte enable length = 0 + Streaming width = 2 + Initiator memory = xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + Target memory = 0123456789abcdefghijklmnopqrstuvwxyz + Converter = 0 + +Converted Transaction + Addr = 8 + Len = 56 + Txn data pointer = changed + Byte enables and byte enable pointer = 01100000011000000110000001100000011000000110000001100000, changed + Byte enable length = 56 + Streaming width = 8 + +Memory States after Transaction + initiator = 9a9a9a9a9a9a9axxxxxxxxxxxxxxxxxxxxxx + target = 0123456789abcdefghijklmnopqrstuvwxyz + +5 enter {R|W}, addr=a, len=l, bus width=b, word width=w, initiator offset=i, be={x|01}, stream width=s +Pool status: (32,32) +enter initiator memory state = (2048 characters) +enter target memory state = (2048 characters) +enter converter choice = (0 => generic, 1 => word, 2 => aligned, 3 => single) +Initiator Intent + Cmd = W + Addr = 5 + Len = 4 + Bus Width = 4 + Data Word = 1 + Initiator offset = 25 + Byte enables = 1101 + Byte enable length = 4 + Streaming width = 2 + Initiator memory = 0123456789abcdefghijklmnopqrstuvwxyz + Target memory = xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + Converter = 0 + +Converted Transaction + Addr = 4 + Len = 8 + Txn data pointer = changed + Byte enables and byte enable pointer = 01100100, changed + Byte enable length = 8 + Streaming width = 4 + +Memory States after Transaction + initiator = 0123456789abcdefghijklmnopqrstuvwxyz + target = xxxxxspxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + +6 enter {R|W}, addr=a, len=l, bus width=b, word width=w, initiator offset=i, be={x|01}, stream width=s +Pool status: (32,32) +enter initiator memory state = (2048 characters) +enter target memory state = (2048 characters) +enter converter choice = (0 => generic, 1 => word, 2 => aligned, 3 => single) +Initiator Intent + Cmd = R + Addr = 10 + Len = 12 + Bus Width = 4 + Data Word = 4 + Initiator offset = 0 + Byte enables = 11110000 + Byte enable length = 8 + Streaming width = 12 + Initiator memory = xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + Target memory = 0123456789abcdefghijklmnopqrstuvwxyz + Converter = 0 + +Converted Transaction + Addr = 8 + Len = 16 + Txn data pointer = changed + Byte enables and byte enable pointer = 1100001111000011, changed + Byte enable length = 16 + Streaming width = 16 + +Memory States after Transaction + initiator = ef89xxxxmnghxxxxxxxxxxxxxxxxxxxxxxxx + target = 0123456789abcdefghijklmnopqrstuvwxyz + +0 enter {R|W}, addr=a, len=l, bus width=b, word width=w, initiator offset=i, be={x|01}, stream width=s +Pool status: (32,32) +enter initiator memory state = (2048 characters) +enter target memory state = (2048 characters) +enter converter choice = (0 => generic, 1 => word, 2 => aligned, 3 => single) +Initiator Intent + Cmd = W + Addr = 15 + Len = 16 + Bus Width = 8 + Data Word = 4 + Initiator offset = 25 + Byte enables = 00001111 + Byte enable length = 8 + Streaming width = 30 + Initiator memory = 0123456789abcdefghijklmnopqrstuvwxyz01234567890abcdefghijklmnopqrstuvwxyz + Target memory = xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + Converter = 0 + +Converted Transaction + Addr = 8 + Len = 24 + Txn data pointer = changed + Byte enables and byte enable pointer = 000000000111100001111000, changed + Byte enable length = 24 + Streaming width = 24 + +Memory States after Transaction + initiator = 0123456789abcdefghijklmnopqrstuvwxyz01234567890abcdefghijklmnopqrstuvwxyz + target = xxxxxxxxxxxxxxxxxtuvwxxxx1234xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + +1 enter {R|W}, addr=a, len=l, bus width=b, word width=w, initiator offset=i, be={x|01}, stream width=s +Pool status: (32,32) +enter initiator memory state = (2048 characters) +enter target memory state = (2048 characters) +enter converter choice = (0 => generic, 1 => word, 2 => aligned, 3 => single) +Initiator Intent + Cmd = R + Addr = 10 + Len = 12 + Bus Width = 4 + Data Word = 4 + Initiator offset = 0 + Byte enables = 11110000 + Byte enable length = 8 + Streaming width = 15 + Initiator memory = xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + Target memory = 0123456789abcdefghijklmnopqrstuvwxyz + Converter = 0 + +Converted Transaction + Addr = 8 + Len = 16 + Txn data pointer = changed + Byte enables and byte enable pointer = 1100001111000011, changed + Byte enable length = 16 + Streaming width = 16 + +Memory States after Transaction + initiator = ef89xxxxmnghxxxxxxxxxxxxxxxxxxxxxxxx + target = 0123456789abcdefghijklmnopqrstuvwxyz + +2 enter {R|W}, addr=a, len=l, bus width=b, word width=w, initiator offset=i, be={x|01}, stream width=s +Pool status: (32,32) +enter initiator memory state = (2048 characters) +enter target memory state = (2048 characters) +enter converter choice = (0 => generic, 1 => word, 2 => aligned, 3 => single) +Initiator Intent + Cmd = W + Addr = 15 + Len = 16 + Bus Width = 8 + Data Word = 4 + Initiator offset = 25 + Byte enables = 00001111 + Byte enable length = 8 + Streaming width = 16 + Initiator memory = 0123456789abcdefghijklmnopqrstuvwxyz01234567890abcdefghijklmnopqrstuvwxyz + Target memory = xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + Converter = 0 + +Converted Transaction + Addr = 8 + Len = 24 + Txn data pointer = changed + Byte enables and byte enable pointer = 000000000111100001111000, changed + Byte enable length = 24 + Streaming width = 24 + +Memory States after Transaction + initiator = 0123456789abcdefghijklmnopqrstuvwxyz01234567890abcdefghijklmnopqrstuvwxyz + target = xxxxxxxxxxxxxxxxxtuvwxxxx1234xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + +3 enter {R|W}, addr=a, len=l, bus width=b, word width=w, initiator offset=i, be={x|01}, stream width=s +Pool status: (32,32) +Pool status: (32,32) (32,32) +Pool status: (32,32) (32,32) (32,32) +Pool status: (24,24) (32,32) (32,32) (32,32) +Pool status: (24,24) (32,32) (32,32) (32,32) +Pool status: (56,56) (24,24) (32,32) (32,32) (32,32) +Pool status: (18,18) (56,56) (24,24) (32,32) (32,32) (32,32) +Pool status: (20,20) (18,18) (56,56) (24,24) (32,32) (32,32) (32,32) diff --git a/src/systemc/tests/tlm/endian_conv/input.txt b/src/systemc/tests/tlm/endian_conv/input.txt new file mode 100644 index 000000000..672c1a55e --- /dev/null +++ b/src/systemc/tests/tlm/endian_conv/input.txt @@ -0,0 +1,198 @@ + +R aligned: addr=0 len=16 bus=8 word=4 dptr=0 be=x s=16 +i=xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +t=0123456789abcdefghijklmnopqrstuvwxyz +c=0 + +R aligned: addr=0 len=16 bus=8 word=4 dptr=0 be=x s=16 +i=xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +t=0123456789abcdefghijklmnopqrstuvwxyz +c=1 + +R aligned: addr=16 len=16 bus=8 word=4 dptr=0 be=x s=16 +i=xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +t=0123456789abcdefghijklmnopqrstuvwxyz +c=2 + +W aligned: addr=16 len=16 bus=8 word=4 dptr=4 be=x s=16 +i=0123456789abcdefghijklmnopqrstuvwxyz +t=xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +c=0 + +W aligned: addr=16 len=16 bus=8 word=4 dptr=4 be=x s=16 +i=0123456789abcdefghijklmnopqrstuvwxyz +t=xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +c=1 + +W aligned: addr=0 len=16 bus=8 word=4 dptr=0 be=x s=16 +i=0123456789abcdefghijklmnopqrstuvwxyz +t=xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +c=2 + +R aligned: addr=0 len=16 bus=8 word=4 dptr=0 be=1111000011110000 s=16 +i=xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +t=0123456789abcdefghijklmnopqrstuvwxyz +c=0 + +R aligned: addr=0 len=16 bus=8 word=4 dptr=0 be=1111000011110000 s=16 +i=xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +t=0123456789abcdefghijklmnopqrstuvwxyz +c=1 + +R aligned: addr=16 len=16 bus=8 word=4 dptr=0 be=1111000011110000 s=16 +i=xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +t=0123456789abcdefghijklmnopqrstuvwxyz +c=2 + +W aligned: addr=16 len=16 bus=8 word=4 dptr=4 be=1111000000001111 s=16 +i=0123456789abcdefghijklmnopqrstuvwxyz +t=xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +c=0 + +W aligned: addr=16 len=16 bus=8 word=4 dptr=4 be=1111000000001111 s=16 +i=0123456789abcdefghijklmnopqrstuvwxyz +t=xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +c=1 + +W aligned: addr=0 len=16 bus=8 word=4 dptr=0 be=1111000000001111 s=16 +i=0123456789abcdefghijklmnopqrstuvwxyz +t=xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +c=2 + + +R single: addr=20 len=4 bus=8 word=4 dptr=0 be=x s=4 +i=xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +t=0123456789abcdefghijklmnopqrstuvwxyz +c=0 + +R single: addr=20 len=4 bus=8 word=4 dptr=0 be=x s=4 +i=xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +t=0123456789abcdefghijklmnopqrstuvwxyz +c=1 + +R single: addr=20 len=4 bus=8 word=4 dptr=0 be=x s=4 +i=xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +t=0123456789abcdefghijklmnopqrstuvwxyz +c=3 + +W single: addr=28 len=4 bus=8 word=4 dptr=4 be=x s=4 +i=0123456789abcdefghijklmnopqrstuvwxyz +t=xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +c=0 + +W single: addr=28 len=4 bus=8 word=4 dptr=4 be=x s=4 +i=0123456789abcdefghijklmnopqrstuvwxyz +t=xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +c=1 + +W single: addr=28 len=4 bus=8 word=4 dptr=4 be=x s=4 +i=0123456789abcdefghijklmnopqrstuvwxyz +t=xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +c=3 + +R single: addr=21 len=2 bus=8 word=2 dptr=0 be=11 s=2 +i=xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +t=0123456789abcdefghijklmnopqrstuvwxyz +c=0 + +R single: addr=21 len=2 bus=8 word=2 dptr=0 be=11 s=2 +i=xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +t=0123456789abcdefghijklmnopqrstuvwxyz +c=1 + +R single: addr=21 len=2 bus=8 word=2 dptr=0 be=11 s=2 +i=xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +t=0123456789abcdefghijklmnopqrstuvwxyz +c=3 + +W single: addr=0 len=4 bus=4 word=4 dptr=25 be=1111 s=4 +i=0123456789abcdefghijklmnopqrstuvwxyz +t=xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +c=0 + +W single: addr=0 len=4 bus=4 word=4 dptr=25 be=1111 s=4 +i=0123456789abcdefghijklmnopqrstuvwxyz +t=xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +c=1 + +W single: addr=0 len=4 bus=4 word=4 dptr=25 be=1111 s=4 +i=0123456789abcdefghijklmnopqrstuvwxyz +t=xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +c=3 + + +R awkward: addr=13 len=14 bus=8 word=2 dptr=0 be=x s=14 +i=xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +t=0123456789abcdefghijklmnopqrstuvwxyz +c=0 + +W awkward: addr=5 len=4 bus=4 word=1 dptr=25 be=x s=4 +i=0123456789abcdefghijklmnopqrstuvwxyz +t=xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +c=0 + +R awkward: addr=10 len=12 bus=4 word=4 dptr=0 be=111100001111 s=12 +i=xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +t=0123456789abcdefghijklmnopqrstuvwxyz +c=0 + +W awkward: addr=15 len=8 bus=8 word=4 dptr=25 be=00001111 s=8 +i=0123456789abcdefghijklmnopqrstuvwxyz +t=xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +c=0 + + +R awkward: addr=13 len=14 bus=8 word=2 dptr=0 be=x s=14 +i=xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +t=0123456789abcdefghijklmnopqrstuvwxyz +c=1 + +W awkward: addr=5 len=4 bus=4 word=1 dptr=25 be=x s=4 +i=0123456789abcdefghijklmnopqrstuvwxyz +t=xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +c=1 + +R awkward: addr=10 len=12 bus=4 word=4 dptr=0 be=111100001111 s=12 +i=xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +t=0123456789abcdefghijklmnopqrstuvwxyz +c=1 + +W awkward: addr=15 len=8 bus=8 word=4 dptr=25 be=00001111 s=8 +i=0123456789abcdefghijklmnopqrstuvwxyz +t=xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +c=1 + + +R stream: addr=13 len=14 bus=8 word=2 dptr=0 be=x s=2 +i=xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +t=0123456789abcdefghijklmnopqrstuvwxyz +c=0 + +W stream: addr=5 len=4 bus=4 word=1 dptr=25 be=1101 s=2 +i=0123456789abcdefghijklmnopqrstuvwxyz +t=xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +c=0 + + +R byte-en-len: addr=10 len=12 bus=4 word=4 dptr=0 be=11110000 s=12 +i=xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +t=0123456789abcdefghijklmnopqrstuvwxyz +c=0 + +W byte-en-len: addr=15 len=16 bus=8 word=4 dptr=25 be=00001111 s=30 +i=0123456789abcdefghijklmnopqrstuvwxyz01234567890abcdefghijklmnopqrstuvwxyz +t=xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +c=0 + + +R stream-byte-en-len: addr=10 len=12 bus=4 word=4 dptr=0 be=11110000 s=15 +i=xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +t=0123456789abcdefghijklmnopqrstuvwxyz +c=0 + +W stream-byte-en-len: addr=15 len=16 bus=8 word=4 dptr=25 be=00001111 s=16 +i=0123456789abcdefghijklmnopqrstuvwxyz01234567890abcdefghijklmnopqrstuvwxyz +t=xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +c=0 + + diff --git a/src/systemc/tests/tlm/endian_conv/test_endian_conv.cpp b/src/systemc/tests/tlm/endian_conv/test_endian_conv.cpp new file mode 100644 index 000000000..8a6ff5c56 --- /dev/null +++ b/src/systemc/tests/tlm/endian_conv/test_endian_conv.cpp @@ -0,0 +1,419 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + + +/* +This C++ programme runs single transactions through a single +endianness conversion function, then through a simple memory model, +then converts it back. +Takes the initial memory state as input and provides the final +memory state as output. +*/ + + +#define BUFFER_SIZE 2048 + +#include<systemc> +#include "tlm.h" +#include<iostream> +#include<time.h> +#include <fstream> + +using namespace std; +using namespace tlm; +using namespace sc_dt; + + +// simple set of types with known sizeof(), for testing // +template<int SIZE> class dt { + char content[SIZE]; +}; + + +#define convert(function) \ + switch(data_width) { \ + case 1: function<dt<1> >(&txn,bus_width); break; \ + case 2: function<dt<2> >(&txn,bus_width); break; \ + case 4: function<dt<4> >(&txn,bus_width); break; \ + case 8: function<dt<8> >(&txn,bus_width); break; \ + case 16: function<dt<16> >(&txn,bus_width); break; \ + case 32: function<dt<32> >(&txn,bus_width); break; \ + default: cout << "bad data width\n"; \ + exit(1); \ + } + + +// forward declarations - see below +template<class DATAWORD> inline void +local_single_tohe(tlm_generic_payload *txn, unsigned int sizeof_databus); +template<class DATAWORD> inline void +local_single_fromhe(tlm_generic_payload *txn, unsigned int sizeof_databus); + + +void test_a_conversion(char cmd, tlm_generic_payload &txn, std::ifstream & fin) { + + if(cmd == 'R') txn.set_read(); + else txn.set_write(); + + fin.ignore(10000,'='); + uint64 a; + fin >> a; + txn.set_address(a); + + fin.ignore(10000,'='); + int l; + fin >> l; + txn.set_data_length(l); + + int bus_width; + fin.ignore(10000,'='); fin >> bus_width; + + int data_width; + fin.ignore(10000,'='); fin >> data_width; + + int initiator_offset; + fin.ignore(10000,'='); fin >> initiator_offset; + + unsigned char *original_byte_enable = 0; + unsigned char *byte_enable_legible = + new unsigned char[txn.get_data_length() + 1]; + memset(byte_enable_legible, 0, txn.get_data_length() + 1); + fin.ignore(10000,'='); + for(unsigned b=0; b<txn.get_data_length(); b++) { + char tmp; fin >> tmp; + if((tmp=='0')||(tmp=='1')||(tmp=='x')) byte_enable_legible[b]=tmp; + else break; + } + if((byte_enable_legible[0] == '1') || (byte_enable_legible[0] == '0')) { + txn.set_byte_enable_ptr(new unsigned char[txn.get_data_length()]); + txn.set_byte_enable_length(txn.get_data_length()); + original_byte_enable = txn.get_byte_enable_ptr(); + for(unsigned int i=0; i<txn.get_data_length(); i++) { + if(byte_enable_legible[i] == '0') { + txn.get_byte_enable_ptr()[i] = TLM_BYTE_DISABLED; + } else if(byte_enable_legible[i] == '1') { + txn.get_byte_enable_ptr()[i] = TLM_BYTE_ENABLED; + } else { + // not enough byte enables + txn.set_byte_enable_length(i); + break; + } + } + } else { + txn.set_byte_enable_ptr(0); + txn.set_byte_enable_length(0); + } + + int stream_width; + fin.ignore(10000,'='); fin >> stream_width; + txn.set_streaming_width(stream_width); + + cout << "enter initiator memory state = ("<< BUFFER_SIZE << " characters)\n"; + unsigned char initiator_mem[BUFFER_SIZE+1]; + memset(initiator_mem, 0, BUFFER_SIZE+1); + fin.ignore(10000,'='); fin >> initiator_mem; + + txn.set_data_ptr(initiator_mem + initiator_offset); + + cout << "enter target memory state = ("<< BUFFER_SIZE << " characters)\n"; + unsigned char target_mem[BUFFER_SIZE+1]; + memset(target_mem, 0, BUFFER_SIZE+1); + fin.ignore(10000,'='); fin >> target_mem; + + cout << "enter converter choice = (0 => generic, 1 => word, 2 => aligned, 3 => single)\n"; + int converter; + fin.ignore(10000,'='); fin >> converter; + + cout << "Initiator Intent\n"; + cout << " Cmd = " << cmd << endl; + cout << " Addr = " << txn.get_address() << endl; + cout << " Len = " << txn.get_data_length() << endl; + cout << " Bus Width = " << bus_width << endl; + cout << " Data Word = " << data_width << endl; +#ifdef VERBOSE + cout << " Initiator offset and txn data pointer = " << initiator_offset << ", " << int(txn.get_data_ptr()) << endl; + cout << " Byte enables and byte enable pointer = " << byte_enable_legible << ", " << int(txn.get_byte_enable_ptr()) << endl; +#else + cout << " Initiator offset = " << initiator_offset << endl; + cout << " Byte enables = " << byte_enable_legible << endl; +#endif + cout << " Byte enable length = " << txn.get_byte_enable_length() << endl; + cout << " Streaming width = " << txn.get_streaming_width() << endl; + cout << " Initiator memory = " << initiator_mem << endl; + cout << " Target memory = " << target_mem << endl; + cout << " Converter = " << converter << endl << endl; + + // initiator // + switch(converter) { + case 0: convert(tlm_to_hostendian_generic); break; + case 1: convert(tlm_to_hostendian_word); break; + case 2: convert(tlm_to_hostendian_aligned); break; + case 3: convert(tlm_to_hostendian_single); break; + case 4: convert(local_single_tohe); break; + default: cout << "no such converter as " << converter << endl; + exit(1); + } + + cout << "Converted Transaction\n"; + cout << " Addr = " << txn.get_address() << endl; + cout << " Len = " << txn.get_data_length() << endl; +#ifdef VERBOSE + cout << " Txn data pointer = " << int(txn.get_data_ptr()) << endl; + if(txn.get_byte_enable_ptr() != 0) { + cout << " Byte enables and byte enable pointer = "; + for(unsigned int i=0; i<txn.get_data_length(); i++) + cout << (txn.get_byte_enable_ptr()[i] ? '1' : '0'); + cout << ", " << int(txn.get_byte_enable_ptr()) << endl; + } +#else + cout << " Txn data pointer = " << + (txn.get_data_ptr() == initiator_mem+initiator_offset ? "unchanged" : "changed") << endl; + if(txn.get_byte_enable_ptr() != 0) { + cout << " Byte enables and byte enable pointer = "; + for(unsigned int i=0; i<txn.get_data_length(); i++) + cout << (txn.get_byte_enable_ptr()[i] ? '1' : '0'); + cout << ", " << + (txn.get_byte_enable_ptr() == original_byte_enable ? "unchanged" : "changed") << endl; + } +#endif + cout << " Byte enable length = " << txn.get_byte_enable_length() << endl; + cout << " Streaming width = " << txn.get_streaming_width() << endl; + cout << endl; + + // target // + int sw = txn.get_streaming_width(); + if((txn.get_data_length()/sw)*sw != txn.get_data_length()) { + cout << "ERROR: Data length not a multiple of streaming width\n"; + exit(1); + } + for(unsigned int ss = 0; ss < txn.get_data_length(); ss += sw) { + if(txn.get_byte_enable_ptr() == 0) { + // simple transaction can be processed by mem-copy + if(txn.is_read()) + memcpy(ss+txn.get_data_ptr(), target_mem+txn.get_address(), sw); + else + memcpy(target_mem+txn.get_address(), ss+txn.get_data_ptr(), sw); + } else { + // complex transaction, byte enables, maybe shorter than data + int bel = txn.get_byte_enable_length(); + if(txn.is_read()) { + for(int j=0; j<sw; j++) { + if(txn.get_byte_enable_ptr()[(ss+j) % bel]) + (txn.get_data_ptr())[ss+j] = target_mem[j+txn.get_address()]; + } + } else { + for(int j=0; j<sw; j++) { + if(txn.get_byte_enable_ptr()[(ss+j) % bel]) + target_mem[j+txn.get_address()] = (txn.get_data_ptr())[ss+j]; + } + } + } + } + + // initiator again // + if((rand() & 0x100) && (converter < 4)) { +#ifdef VERBOSE + cout << "using single entry point for response\n"; +#endif + tlm_from_hostendian(&txn); + } else { +#ifdef VERBOSE + cout << "using specific entry point for response\n"; +#endif + switch(converter) { + case 0: convert(tlm_from_hostendian_generic); break; + case 1: convert(tlm_from_hostendian_word); break; + case 2: convert(tlm_from_hostendian_aligned); break; + case 3: convert(tlm_from_hostendian_single); break; + case 4: convert(local_single_fromhe); break; + default: cout << "no such converter as " << converter << endl; + exit(1); + } + } + + // print the results // + cout << "Memory States after Transaction\n"; + cout << " initiator = " << initiator_mem << endl; + cout << " target = " << target_mem << endl << endl; + + // clean up + delete [] byte_enable_legible; + if(original_byte_enable != 0) delete [] original_byte_enable; +} + + +void pool_status() { + cout << "Pool status: "; + tlm_endian_context *f = global_tlm_endian_context_pool.first; + while(f!=0) { + cout << "(" << f->dbuf_size << "," << f->bebuf_size << ") "; + f = f->next; + } + cout << endl; +} + + +int sc_main(int argc, char **argv) { + + #include <string> + + // no command line parameters // + // get everything from stdin and build transaction object // + cout << "\nTLM-2 Endianness Conversion Helper Functions Tester\n"; + cout << "March 2008\n"; + cout << "January 2012 Updated to read from endian_conv/input.txt\n\n"; + + std::string filename; + std::ifstream fin; + + if (1 == argc) + filename = "endian_conv/input.txt"; + else if (2 == argc) + filename = argv[1]; + else { + std::cerr << "Too many input arguments" << std::endl; + return 1; + } + + + fin.open(filename.c_str(), ios_base::in); + if (!fin) { + std::cerr << "Could not open input filename " << filename << std::endl; + return 1; + } + + srand(time(NULL)); + const int nr_txns_in_pool = 7; + const int txn_to_cycle = 4; + tlm_generic_payload *txns[nr_txns_in_pool]; + for(int i=0; i < nr_txns_in_pool; i++) txns[i] = new tlm_generic_payload; + + for(int i=0; true; i = ((i+1) % nr_txns_in_pool)) { + cout << i << " enter {R|W}, addr=a, len=l, bus width=b, word width=w, initiator offset=i, be={x|01}, stream width=s\n"; + pool_status(); + char command; + fin >> command; + if(fin.eof()) break; + if((command != 'R') && (command != 'W')) break; + if(i==txn_to_cycle) { + // should cause 2 extensions to get pushed to the pool once they've been used + delete txns[i]; + pool_status(); + delete txns[i-1]; + pool_status(); + // and popped back later when these new ones establish contexts + txns[i] = new tlm_generic_payload; + txns[i-1] = new tlm_generic_payload; + pool_status(); + } + test_a_conversion(command, *txns[i], fin); + } + + for(int i=0; i < nr_txns_in_pool; i++) { + delete txns[i]; + pool_status(); + } + return 0; +} + + +// converter functions for non-aligned single transactions +// included here for validation only. not designed for general use. + +unsigned char *original_dptr; +sc_dt::uint64 original_addr; + +template<class DATAWORD> inline void +local_single_tohe(tlm_generic_payload *txn, unsigned int sizeof_databus) { + if(txn->get_data_length() != sizeof(DATAWORD)) { + cout << "Error: local_single_tohe() wrongly called\n"; + exit(1); + } + + sc_dt::uint64 mask = sizeof_databus - 1; + + // set up new buffers, length and address + if(sizeof(DATAWORD) > sizeof_databus) + txn->set_data_length(sizeof_databus + sizeof(DATAWORD)); + else + txn->set_data_length(2 * sizeof_databus); + txn->set_streaming_width(txn->get_data_length()); + unsigned char *new_data = new unsigned char[txn->get_data_length()]; + unsigned char *new_be = new unsigned char[txn->get_data_length()]; + // drive all BEs to zero initially + for(unsigned int i=0; i<txn->get_data_length(); i++) new_be[i] = 0; + sc_dt::uint64 new_addr = txn->get_address() & ~mask; + + // Comments assume arithmetic mode big endian initiator modelled on little + // endian host (but the functionality is the same for LE initiator on BE host) + + // iterate over the initiator word byte by byte, MSB first + unsigned char *curr_d = txn->get_data_ptr() + sizeof(DATAWORD) - 1; + unsigned char *curr_b = txn->get_byte_enable_ptr() + sizeof(DATAWORD) - 1; + + // initiator intent is to put the MSB at the address given in the transaction + sc_dt::uint64 curr_a = txn->get_address(); + + // iterate copying data and byte enables + for( ; curr_d >= txn->get_data_ptr(); curr_d--, curr_b--, curr_a++) { + // work out the address in the TLM interpretation of the initiator's intent + sc_dt::uint64 he_addr = curr_a ^ mask; + int idx = he_addr - new_addr; + if(txn->is_write()) new_data[idx] = *curr_d; + if(txn->get_byte_enable_ptr() == 0) new_be[idx] = 1; + else new_be[idx] = *curr_b; + } + + // replace the pointers + original_dptr = txn->get_data_ptr(); + txn->set_data_ptr(new_data); + txn->set_byte_enable_ptr(new_be); + txn->set_byte_enable_length(txn->get_data_length()); + original_addr = txn->get_address(); + txn->set_address(new_addr); +} + + +template<class DATAWORD> inline void +local_single_fromhe(tlm_generic_payload *txn, unsigned int sizeof_databus) { + sc_dt::uint64 mask = sizeof_databus - 1; + + // Comments assume arithmetic mode big endian initiator modelled on little + // endian host (but the functionality is the same for LE initiator on BE host) + + // iterate over the initiator word byte by byte, MSB first + unsigned char *curr_d = original_dptr + sizeof(DATAWORD) - 1; + + // initiator intent is to put the MSB at the address given in the transaction + sc_dt::uint64 curr_a = original_addr; + + // iterate copying data and byte enables + for( ; curr_d >= original_dptr; curr_d--, curr_a++) { + // work out the address in the TLM interpretation of the initiator's intent + sc_dt::uint64 he_addr = curr_a ^ mask; + int idx = he_addr - txn->get_address(); + if((txn->is_read()) && (txn->get_byte_enable_ptr()[idx] != 0)) + *curr_d = txn->get_data_ptr()[idx]; + } + + // clean up + delete [] txn->get_data_ptr(); + delete [] txn->get_byte_enable_ptr(); +} + diff --git a/src/systemc/tests/tlm/endian_conv/testall.py b/src/systemc/tests/tlm/endian_conv/testall.py new file mode 100644 index 000000000..63bf6abe8 --- /dev/null +++ b/src/systemc/tests/tlm/endian_conv/testall.py @@ -0,0 +1,456 @@ +""" +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +Python Script to test Endianness Conversion Functions for OSCI TLM-2 + +There is a simple testbench programme in C++ which runs a single +transaction through a single conversion function, to a simple target +memory and back. This script will run the testbench many times and test for +- incomplete execution, seg-faults, etc +- distributability of conversion function: each transaction should have +the same effect on initiator/target memory as a set of smaller transactions +that sum to it +- equivalence: all conversion functions should have the same functional +effect as each other + +The approach is to provide the initial state of the initiator and +target memory (as strings) and to capture their final states, so that +only the effect of the transaction on the data buffers is measured. + +Script works out for itself which conversion functions are legal for a +given transaction and applies all of them. Note that where data is +wider than bus, only one conversion function is legal and testing is +somewhat limited. + +Testing space (select a transaction at random from the space): +- with and without byte-enables (generated at random for each data word +and can be all-zero) +- data widths of (1,2,4,8,16) +- bus widths of (1,2,4,8,16), lower priority for those smaller than data +width +- transaction lengths of (1..32) x data width, higher probability for +lower values +- base address (0..1023) at bus_width steps +- offset address (0..bus width) with a higher priority for 0 +- address in initiator buffer uniform random +- read or write +- byte-enable length may be smaller than transasction length +- may be a streaming burst + +Transaction breakdown +- individual words (always) +- one random breakdown with each segment containing between 1 and N-1 +words, where N is the length in words +- one breakdown with two segments interleaved, using (additional) byte +enables to suppress the part where the other segment is active + +Data buffer definition: starts at 0, randomly filled +with lower case letters and numbers. Size 2 kB. Addresses are limited to +1 kB. +""" + + +import random +import string + + +class transaction: + """ contains read_not_write, address, length, byte_enable, + bus_width, data_width, data_pointer, stream_width """ + def __init__(self, **a): self.__dict__ = a + def __str__(self): + if self.read_not_write: a = "R: " + else: a = "W: " + a += "addr = %d, len = %d, bus = %d, word = %d, data = %d" % \ + (self.address, self.length, self.bus_width, self.data_width, \ + self.data_pointer) + if self.byte_enable: a += ", be = " + self.byte_enable + else: a += ", be = x" + a += ", sw = %d" % (self.stream_width) + return a + + +def txn_generator(nr): + pr_read = 0.5 + pr_byte_enable = 0.5 + pr_enabled = 0.5 + bus_widths = [1, 2, 4, 8, 16] + data_widths = [1, 2, 4, 8, 16] + [1, 2, 4, 8] + [1, 2, 4] + [1, 2] + lengths = range(1,33) + range(1,17) + range(1,9) + range(1,5) + range(1,3) + pr_short_be = 0.2 + pr_stream = 0.1 + nr_generated = 0 + while nr_generated < nr: + # create a random transaction + bus_width = random.choice(bus_widths) + while True: + data_width = random.choice(data_widths) + if data_width <= bus_width: break + if random.random() < 0.25: break + length = random.choice(lengths) + addr_base = random.choice(range(0,1024,bus_width)) + addr_offset = random.choice(range(bus_width)+[0]*(bus_width/2)) + txn = transaction( + bus_width = bus_width, + data_width = data_width, + read_not_write = random.random() < pr_read, + length = length * data_width, + address = addr_base + addr_offset, + byte_enable = False, + stream_width = length * data_width, + data_pointer = random.randint(0,1023) + ) + if random.random() < pr_byte_enable: + belen = length + if random.random() < pr_short_be: + belen = min(random.choice(lengths), length) + bep = ["0" * data_width, "1" * data_width] + txn.byte_enable = "".join([random.choice(bep) for x in range(belen)]) + if random.random() < pr_stream and length > 1: + strlen = length + while True: + strlen -= 1 + if strlen == 1 or \ + (random.random() < 0.5 and (length/strlen)*strlen == length): + break + txn.stream_width = strlen * data_width + nr_generated += 1 + yield txn + +# test code for transaction generator +if False: + for t in txn_generator(20): + print t + raise Exception +# end test code + + +class memory_state_cl: + buffer_size = 2048 + repeats = 10 * buffer_size / 36 + population = (string.lowercase + string.digits) * repeats + def __init__(self): + self.initiator = "".join( + random.sample(memory_state_cl.population, memory_state_cl.buffer_size)) + self.target = "".join( + random.sample(memory_state_cl.population, memory_state_cl.buffer_size)) + def copy(self): + r = memory_state_cl() + r.initiator = self.initiator + r.target = self.target + return r + def __eq__(self, golden): + return self.initiator==golden.initiator and self.target==golden.target + def __ne__(self, golden): + return self.initiator!=golden.initiator or self.target!=golden.target + def __str__(self): + return "initiator = " + self.initiator + "\n" + "target = " + self.target + + +# all fragmentation generators +def __FRAG__null(txn): + yield txn + +def __FRAG__word(txn): + curr_address = txn.address + reset_address = curr_address + txn.stream_width + if txn.byte_enable: + full_byte_enable = txn.byte_enable * (1+txn.length/len(txn.byte_enable)) + be_pos = 0 + d_pos = txn.data_pointer + end = txn.length + d_pos + while d_pos < end: + new_txn = transaction( + bus_width = txn.bus_width, + data_width = txn.data_width, + read_not_write = txn.read_not_write, + length = txn.data_width, + address = curr_address, + byte_enable = False, + stream_width = txn.data_width, + data_pointer = d_pos + ) + curr_address += txn.data_width + if curr_address == reset_address: curr_address = txn.address + d_pos += txn.data_width + if txn.byte_enable: + new_txn.byte_enable = full_byte_enable[be_pos:be_pos+txn.data_width] + be_pos += txn.data_width + yield new_txn + +def __FRAG__stream(txn): + if txn.byte_enable: + full_byte_enable = txn.byte_enable * (1+txn.length/len(txn.byte_enable)) + be_pos = 0 + bytes_done = 0 + while bytes_done < txn.length: + new_txn = transaction( + bus_width = txn.bus_width, + data_width = txn.data_width, + read_not_write = txn.read_not_write, + length = txn.stream_width, + address = txn.address, + byte_enable = False, + stream_width = txn.stream_width, + data_pointer = bytes_done + txn.data_pointer + ) + if txn.byte_enable: + new_txn.byte_enable = full_byte_enable[be_pos:be_pos+txn.stream_width] + be_pos += txn.stream_width + yield new_txn + bytes_done += txn.stream_width + +def __FRAG__random(stream_txn): + for txn in __FRAG__stream(stream_txn): + # txn has full byte enables and no stream feature guaranteed + pr_nofrag = 0.5 + end_address = txn.address + txn.length + curr_address = txn.address + be_pos = 0 + d_pos = txn.data_pointer + while curr_address < end_address: + new_txn = transaction( + bus_width = txn.bus_width, + data_width = txn.data_width, + read_not_write = txn.read_not_write, + length = txn.data_width, + address = curr_address, + byte_enable = txn.byte_enable, + stream_width = txn.data_width, + data_pointer = d_pos + ) + curr_address += txn.data_width + d_pos += txn.data_width + if txn.byte_enable: + new_txn.byte_enable = txn.byte_enable[be_pos:be_pos+txn.data_width] + be_pos += txn.data_width + while random.random() < pr_nofrag and curr_address < end_address: + new_txn.length += txn.data_width + new_txn.stream_width += txn.data_width + curr_address += txn.data_width + d_pos += txn.data_width + if txn.byte_enable: + new_txn.byte_enable += txn.byte_enable[be_pos:be_pos+txn.data_width] + be_pos += txn.data_width + yield new_txn + +def __FRAG__randinterleave(stream_txn): + for txn in __FRAG__stream(stream_txn): + # txn has full byte enables and no stream feature guaranteed + pr_frag = 0.5 + txns = [ transaction( + bus_width = txn.bus_width, + data_width = txn.data_width, + read_not_write = txn.read_not_write, + length = txn.length, + address = txn.address, + byte_enable = "", + stream_width = txn.length, + data_pointer = txn.data_pointer + ), transaction( + bus_width = txn.bus_width, + data_width = txn.data_width, + read_not_write = txn.read_not_write, + length = txn.length, + address = txn.address, + byte_enable = "", + stream_width = txn.length, + data_pointer = txn.data_pointer + ) ] + curr = 0 + be_pos = 0 + on = "1" * txn.data_width + off = "0" * txn.data_width + while be_pos < txn.length: + if txn.byte_enable: bew = txn.byte_enable[be_pos:be_pos+txn.data_width] + else: bew = on + txns[curr].byte_enable += bew + txns[1-curr].byte_enable += off + be_pos += txn.data_width + if random.random() < pr_frag: curr = 1-curr + yield txns[0] + yield txns[1] + +fragmenters = [globals()[n] for n in globals().keys() if n[:8]=="__FRAG__"] + +# test code for fragmenters +if False: + for t in txn_generator(1): + print t + print + for u in fragmenters[4](t): + print u + raise Exception +# end test code + + +# conversion functions are determined by an index (shared with C++) and +# a function that tests if they can be applied to a transaction +def __CHCK__generic(txn): + __CHCK__generic.nr = 0 + return True + +def __CHCK__word(txn): + __CHCK__word.nr = 1 + if txn.data_width > txn.bus_width: return False + if txn.stream_width < txn.length: return False + if txn.byte_enable and len(txn.byte_enable) < txn.length: return False + return True + +def __CHCK__aligned(txn): + __CHCK__aligned.nr = 2 + if txn.data_width > txn.bus_width: return False + if txn.stream_width < txn.length: return False + if txn.byte_enable and len(txn.byte_enable) < txn.length: return False + base_addr = txn.address / txn.bus_width + if base_addr * txn.bus_width != txn.address: return False + nr_bus_words = txn.length / txn.bus_width + if nr_bus_words * txn.bus_width != txn.length: return False + return True + +def __CHCK__single(txn): + __CHCK__single.nr = 3 + if txn.length != txn.data_width: return False + base_addr = txn.address / txn.bus_width + end_base_addr = (txn.address + txn.length - 1) / txn.bus_width + if base_addr != end_base_addr: return False + return True + +def __CHCK__local_single(txn): + __CHCK__local_single.nr = 4 + if txn.length != txn.data_width: return False + return True + +all_converters = [globals()[n] for n in globals().keys() if n[:8]=="__CHCK__"] +for x in all_converters: x.usage = 0 + + +class TesterFailure(Exception): pass +class SystemCFailure(Exception): pass +class ConverterDifference(Exception): pass +class FragmenterDifference(Exception): pass + +from subprocess import Popen, PIPE + +# test a single fragment in multiple ways +def test_a_fragment(f, ms): + # f is the (fragment of a) transaction + # ms is the memory state to use at start of test + + # run the same fragment through all applicable conversion functions + # and check they all do the same thing + # use the same sub-process for all of them + + # build complete stdin + convs = [c for c in all_converters if c(f)] + if len(convs) == 0: raise TesterFailure(f.str()) + txtin = "\n".join( + [("%s\n%s\nconverter = %d\n" % (f, ms, c.nr)) for c in convs]) + + # run and get stdout + txtout = "no output" + try: + sp = Popen("../build-unix/test_endian_conv.exe", stdin=PIPE, stdout=PIPE) + txtout = sp.communicate(txtin)[0] + tmp = txtout.splitlines() + initiators = [l.split()[-1] for l in tmp if l[:14] == " initiator = "] + targets = [l.split()[-1] for l in tmp if l[:11] == " target = "] + except: + raise SystemCFailure("\n" + txtin + txtout) + if sp.returncode != 0: raise SystemCFailure("\n" + txtin + txtout) + if len(initiators) != len(convs): raise SystemCFailure("\n" + txtin + txtout) + if len(targets) != len(convs): raise SystemCFailure("\n" + txtin + txtout) + for c in convs: c.usage += 1 + + ms_out = memory_state_cl() + ms_out.initiator = initiators[0] + ms_out.target = targets[0] + for i in range(1,len(convs)): + if initiators[i]!=ms_out.initiator or targets[i]!=ms_out.target: + raise ConverterDifference(""" +%s +start memory: +%s +converter = %d +golden memory: +%s +actual memory: +%s""" % (f, ms, i, golden_ms, ms_out)) + + return ms_out + + +# main loop + +from sys import argv + +print "Testing Endianness Conversion Functions" +print "March 2008" +print "OSCI TLM-2" + +try: nr_txns_to_test = int(argv[1]) +except: + print "No command line input for number of tests, using default" + nr_txns_to_test = 1000 + +print "Number to test:", nr_txns_to_test + +# generate and test a number of transactions +for txn in txn_generator(nr_txns_to_test): + + # each transaction has a random initial memory state + initial_memory = memory_state_cl() + + # iterate over all defined fragmentation functions + first_time = True + for fragmenter in fragmenters: + + # all versions of the transaction start in the same place + memory_state = initial_memory.copy() + + # now iterate over the fragments of the transaction, accumulating + # the memory state + for partial_txn in fragmenter(txn): + memory_state = test_a_fragment(partial_txn, memory_state) + + if first_time: + golden_memory_state = memory_state.copy() + first_time = False + else: + if memory_state != golden_memory_state: raise FragmenterDifference(""" +fragmenter: %s +transaction: +%s +start memory: +%s +golden memory: +%s +actual memory: +%s""" % (fragmenter, txn, initial_memory, golden_memory_state, memory_state)) + + print ".", +print + + +print "Conversion functions usage frequency:" +for c in all_converters: + print c.nr, c.__name__, c.usage + + |