4 files changed, 4 insertions, 9 deletions
diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py
index f52c6b11f..e7613c5bb 100644
--- a/src/cpu/BaseCPU.py
+++ b/src/cpu/BaseCPU.py
@@ -281,10 +281,10 @@ class BaseCPU(MemObject):
 
     def addTwoLevelCacheHierarchy(self, ic, dc, l2c, iwc = None, dwc = None):
         self.addPrivateSplitL1Caches(ic, dc, iwc, dwc)
-        # Override the default bus clock of 1 GHz and uses the CPU
-        # clock for the L1-to-L2 bus, and also set a width of 32 bytes
-        # (256-bits), which is four times that of the default bus.
-        self.toL2Bus = CoherentBus(clock = Parent.clock, width = 32)
+        # Set a width of 32 bytes (256-bits), which is four times that
+        # of the default bus. The clock of the CPU is inherited by
+        # default.
+        self.toL2Bus = CoherentBus(width = 32)
         self.connectCachedPorts(self.toL2Bus)
         self.l2cache = l2c
         self.toL2Bus.master = self.l2cache.cpu_side
diff --git a/src/dev/CopyEngine.py b/src/dev/CopyEngine.py
index 68332e0a0..d56294d66 100644
--- a/src/dev/CopyEngine.py
+++ b/src/dev/CopyEngine.py
@@ -53,8 +53,6 @@ class CopyEngine(PciDevice):
     ChanCnt = Param.UInt8(4, "Number of DMA channels that exist on device")
     XferCap = Param.MemorySize('4kB', "Number of bits of transfer size that are supported")
 
-    # Override the default clock
-    clock = '500MHz'
     latBeforeBegin = Param.Latency('20ns', "Latency after a DMA command is seen before it's proccessed")
     latAfterCompletion = Param.Latency('20ns', "Latency after a DMA command is complete before it's reported as such")
 
diff --git a/src/dev/arm/RealView.py b/src/dev/arm/RealView.py
index ab994b6f0..5c2768fb9 100644
--- a/src/dev/arm/RealView.py
+++ b/src/dev/arm/RealView.py
@@ -118,8 +118,6 @@ class CpuLocalTimer(BasicPioDevice):
     gic = Param.BaseGic(Parent.any, "Gic to use for interrupting")
     int_num_timer = Param.UInt32("Interrrupt number used per-cpu to GIC")
     int_num_watchdog = Param.UInt32("Interrupt number for per-cpu watchdog to GIC")
-    # Override the default clock
-    clock = '1GHz'
 
 class PL031(AmbaIntDevice):
     type = 'PL031'
diff --git a/src/mem/ruby/system/RubySystem.py b/src/mem/ruby/system/RubySystem.py
index ba261cc36..29e395404 100644
--- a/src/mem/ruby/system/RubySystem.py
+++ b/src/mem/ruby/system/RubySystem.py
@@ -36,7 +36,6 @@ class RubySystem(ClockedObject):
     random_seed = Param.Int(1234, "random seed used by the simulation");
     randomization = Param.Bool(False,
         "insert random delays on message enqueue times");
-    clock = '1GHz'
     block_size_bytes = Param.UInt32(64,
         "default cache block size; must be a power of two");
     mem_size = Param.MemorySize("total memory size of the system");