6 files changed, 20 insertions, 17 deletions
diff --git a/src/mem/ruby/system/MemoryControl.cc b/src/mem/ruby/system/MemoryControl.cc
index c5f6ecb83..f1ebc07fa 100644
--- a/src/mem/ruby/system/MemoryControl.cc
+++ b/src/mem/ruby/system/MemoryControl.cc
@@ -42,7 +42,7 @@
 #include "mem/ruby/system/System.hh"
 
 using namespace std;
-MemoryControl::MemoryControl(const Params *p) : SimObject(p), m_event(this)
+MemoryControl::MemoryControl(const Params *p) : ClockedObject(p), m_event(this)
 {
     g_system_ptr->registerMemController(this);
 }
diff --git a/src/mem/ruby/system/MemoryControl.hh b/src/mem/ruby/system/MemoryControl.hh
index 80a55e9c1..b7de06c5e 100644
--- a/src/mem/ruby/system/MemoryControl.hh
+++ b/src/mem/ruby/system/MemoryControl.hh
@@ -34,24 +34,29 @@
 #include <list>
 #include <string>
 
-#include "mem/protocol/MemoryMsg.hh"
 #include "mem/protocol/MemoryControlRequestType.hh"
+#include "mem/protocol/MemoryMsg.hh"
 #include "mem/ruby/common/Consumer.hh"
 #include "mem/ruby/profiler/MemCntrlProfiler.hh"
 #include "mem/ruby/slicc_interface/Message.hh"
 #include "mem/ruby/system/AbstractMemOrCache.hh"
 #include "mem/ruby/system/MemoryNode.hh"
 #include "mem/ruby/system/System.hh"
-#include "sim/sim_object.hh"
+#include "params/MemoryControl.hh"
+#include "sim/clocked_object.hh"
 
 //////////////////////////////////////////////////////////////////////////////
 
 class Consumer;
 
 class MemoryControl :
-    public SimObject, public Consumer, public AbstractMemOrCache
+    public ClockedObject, public Consumer, public AbstractMemOrCache
 {
   public:
+    typedef MemoryControlParams Params;
+    const Params *params() const
+    { return dynamic_cast<const Params *>(_params); }
+
     MemoryControl(const Params *p);
     virtual void init() = 0;
     virtual void reset() = 0;
diff --git a/src/mem/ruby/system/MemoryControl.py b/src/mem/ruby/system/MemoryControl.py
index c4c852932..09c940fee 100644
--- a/src/mem/ruby/system/MemoryControl.py
+++ b/src/mem/ruby/system/MemoryControl.py
@@ -28,13 +28,11 @@
 #          Brad Beckmann
 
 from m5.params import *
-from m5.SimObject import SimObject
+from ClockedObject import ClockedObject
 
-class MemoryControl(SimObject):
+class MemoryControl(ClockedObject):
     abstract = True
     type = 'MemoryControl'
     cxx_class = 'MemoryControl'
     version = Param.Int("");
     ruby_system = Param.RubySystem("")
-
-    mem_bus_cycle_multiplier = Param.Int(10, "");
diff --git a/src/mem/ruby/system/RubyMemoryControl.cc b/src/mem/ruby/system/RubyMemoryControl.cc
index 230f652c2..f931e4618 100644
--- a/src/mem/ruby/system/RubyMemoryControl.cc
+++ b/src/mem/ruby/system/RubyMemoryControl.cc
@@ -149,7 +149,6 @@ operator<<(ostream& out, const RubyMemoryControl& obj)
 RubyMemoryControl::RubyMemoryControl(const Params *p)
     : MemoryControl(p)
 {
-    m_mem_bus_cycle_multiplier = p->mem_bus_cycle_multiplier;
     m_banks_per_rank = p->banks_per_rank;
     m_ranks_per_dimm = p->ranks_per_dimm;
     m_dimms_per_channel = p->dimms_per_channel;
@@ -309,7 +308,7 @@ RubyMemoryControl::enqueueMemRef(MemoryNode& memRef)
     m_input_queue.push_back(memRef);
 
     if (!m_event.scheduled()) {
-        schedule(m_event, curTick() + 1);
+        schedule(m_event, nextCycle());
     }
 }
 
@@ -377,17 +376,17 @@ RubyMemoryControl::printStats(ostream& out) const
 void
 RubyMemoryControl::enqueueToDirectory(MemoryNode req, int latency)
 {
-    Time arrival_time = g_system_ptr->getTime()
-        + (latency * m_mem_bus_cycle_multiplier);
-    req.m_time = arrival_time;
+    Time arrival_time = curTick() + (latency * clock);
+    Time ruby_arrival_time = arrival_time / g_system_ptr->getClock();
+    req.m_time = ruby_arrival_time;
     m_response_queue.push_back(req);
 
     DPRINTF(RubyMemory, "Enqueueing msg %#08x %c back to directory at %15d\n",
             req.m_addr, req.m_is_mem_read ? 'R':'W',
-            arrival_time * g_system_ptr->getClock());
+            arrival_time);
 
     // schedule the wake up
-    m_consumer_ptr->scheduleEventAbsolute(arrival_time);
+    m_consumer_ptr->scheduleEventAbsolute(ruby_arrival_time);
 }
 
 // getBank returns an integer that is unique for each
@@ -705,7 +704,7 @@ RubyMemoryControl::wakeup()
     m_idleCount--;
     if (m_idleCount > 0) {
         assert(!m_event.scheduled());
-        schedule(m_event, curTick() + m_mem_bus_cycle_multiplier);
+        schedule(m_event, curTick() + clock);
     }
 }
 
diff --git a/src/mem/ruby/system/RubyMemoryControl.hh b/src/mem/ruby/system/RubyMemoryControl.hh
index 512533f97..de0da56b5 100644
--- a/src/mem/ruby/system/RubyMemoryControl.hh
+++ b/src/mem/ruby/system/RubyMemoryControl.hh
@@ -116,7 +116,6 @@ class RubyMemoryControl : public MemoryControl
     std::string m_description;
     int m_msg_counter;
 
-    int m_mem_bus_cycle_multiplier;
     int m_banks_per_rank;
     int m_ranks_per_dimm;
     int m_dimms_per_channel;
diff --git a/src/mem/ruby/system/RubyMemoryControl.py b/src/mem/ruby/system/RubyMemoryControl.py
index f79ed9b18..e65b6f5cc 100644
--- a/src/mem/ruby/system/RubyMemoryControl.py
+++ b/src/mem/ruby/system/RubyMemoryControl.py
@@ -36,6 +36,8 @@ class RubyMemoryControl(MemoryControl):
     cxx_class = 'RubyMemoryControl'
     version = Param.Int("");
 
+    # Override the default clock
+    clock = '400MHz'
     banks_per_rank = Param.Int(8, "");
     ranks_per_dimm = Param.Int(2, "");
     dimms_per_channel = Param.Int(2, "");