diff options
Diffstat (limited to 'system/alpha/h')
| -rw-r--r-- | system/alpha/h/cserve.h | 52 | ||||
| -rw-r--r-- | system/alpha/h/dc21164FromGasSources.h | 886 | ||||
| -rw-r--r-- | system/alpha/h/ev5_alpha_defs.h | 314 | ||||
| -rw-r--r-- | system/alpha/h/ev5_defs.h | 598 | ||||
| -rw-r--r-- | system/alpha/h/ev5_impure.h | 420 | ||||
| -rw-r--r-- | system/alpha/h/ev5_osfalpha_defs.h | 152 | ||||
| -rw-r--r-- | system/alpha/h/ev5_paldef.h | 162 | ||||
| -rw-r--r-- | system/alpha/h/fromHudsonMacros.h | 88 | ||||
| -rw-r--r-- | system/alpha/h/fromHudsonOsf.h | 483 | ||||
| -rw-r--r-- | system/alpha/h/rpb.h | 387 | ||||
| -rw-r--r-- | system/alpha/h/tlaser.h | 34 |
11 files changed, 3576 insertions, 0 deletions
diff --git a/system/alpha/h/cserve.h b/system/alpha/h/cserve.h new file mode 100644 index 000000000..5b0e0f61c --- /dev/null +++ b/system/alpha/h/cserve.h @@ -0,0 +1,52 @@ +/* + * Copyright (c) 1993 The Hewlett-Packard Development Company + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#define __CSERVE_LOADED 1 + +/* + * Console Service (cserve) sub-function codes: + */ +#define CSERVE_K_LDQP 0x01 +#define CSERVE_K_STQP 0x02 +#define CSERVE_K_JTOPAL 0x09 +#define CSERVE_K_WR_INT 0x0A +#define CSERVE_K_RD_IMPURE 0x0B +#define CSERVE_K_PUTC 0x0F +#define CSERVE_K_WR_ICSR 0x10 +#define CSERVE_K_WR_ICCSR 0x10 /* for ev4 backwards compatibility */ +#define CSERVE_K_RD_ICSR 0x11 +#define CSERVE_K_RD_ICCSR 0x11 /* for ev4 backwards compatibility */ +#define CSERVE_K_RD_BCCTL 0x12 +#define CSERVE_K_RD_BCCFG 0x13 + +#define CSERVE_K_WR_BCACHE 0x16 + +#define CSERVE_K_RD_BCCFG_OFF 0x17 +#define CSERVE_K_JTOKERN 0x18 + + diff --git a/system/alpha/h/dc21164FromGasSources.h b/system/alpha/h/dc21164FromGasSources.h new file mode 100644 index 000000000..038861d36 --- /dev/null +++ b/system/alpha/h/dc21164FromGasSources.h @@ -0,0 +1,886 @@ +/* + * Copyright (c) 1993 The Hewlett-Packard Development Company + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef DC21164FROMGASSOURCES_INCLUDED +#define DC21164FROMGASSOURCES_INCLUDED 1 + +/* +** +** INTERNAL PROCESSOR REGISTER DEFINITIONS +** +** The internal processor register definitions below are annotated +** with one of the following symbols: +** +** RW - The register may be read and written +** RO - The register may only be read +** WO - The register may only be written +** +** For RO and WO registers, all bits and fields within the register are +** also read-only or write-only. For RW registers, each bit or field +** within the register is annotated with one of the following: +** +** RW - The bit/field may be read and written +** RO - The bit/field may be read; writes are ignored +** WO - The bit/field may be written; reads return UNPREDICTABLE +** WZ - The bit/field may be written; reads return a zero value +** W0C - The bit/field may be read; write-zero-to-clear +** W1C - The bit/field may be read; write-one-to-clear +** WA - The bit/field may be read; write-anything-to-clear +** RC - The bit/field may be read, causing state to clear; +** writes are ignored +** +*/ + + +/* +** +** Ibox IPR Definitions: +** +*/ + +// replaced by ev5_defs.h #define isr 0x100 /* RO - Interrupt Summary */ +#define itbTag 0x101 /* WO - ITB Tag */ +#define itbPte 0x102 /* RW - ITB Page Table Entry */ +#define itbAsn 0x103 /* RW - ITB Address Space Number */ +#define itbPteTemp 0x104 /* RO - ITB Page Table Entry Temporary */ +#define itbIa 0x105 /* WO - ITB Invalidate All */ +#define itbIap 0x106 /* WO - ITB Invalidate All Process */ +#define itbIs 0x107 /* WO - ITB Invalidate Single */ +// replaced by ev5_defs.h #define sirr 0x108 /* RW - Software Interrupt Request */ +// replaced by ev5_defs.h #define astrr 0x109 /* RW - Async. System Trap Request */ +// replaced by ev5_defs.h #define aster 0x10A /* RW - Async. System Trap Enable */ +#define excAddr 0x10B /* RW - Exception Address */ +#define excSum 0x10C /* RW - Exception Summary */ +#define excMask 0x10D /* RO - Exception Mask */ +#define palBase 0x10E /* RW - PAL Base */ +#define ips 0x10F /* RW - Processor Status */ +// replaced by ev5_defs.h #define ipl 0x110 /* RW - Interrupt Priority Level */ +#define intId 0x111 /* RO - Interrupt ID */ +#define iFaultVaForm 0x112 /* RO - Formatted Faulting VA */ +#define iVptBr 0x113 /* RW - I-Stream Virtual Page Table Base */ +#define hwIntClr 0x115 /* WO - Hardware Interrupt Clear */ +#define slXmit 0x116 /* WO - Serial Line Transmit */ +#define slRcv 0x117 /* RO - Serial Line Receive */ +// replaced by ev5_defs.h #define icsr 0x118 /* RW - Ibox Control/Status */ +#define icFlush 0x119 /* WO - I-Cache Flush Control */ +#define flushIc 0x119 /* WO - I-Cache Flush Control (DC21064 Symbol) */ +#define icPerr 0x11A /* RW - I-Cache Parity Error Status */ +#define PmCtr 0x11C /* RW - Performance Counter */ + +/* +** +** Ibox Control/Status Register (ICSR) Bit Summary +** +** Extent Size Name Type Function +** ------ ---- ---- ---- ------------------------------------ +** <39> 1 TST RW,0 Assert Test Status +** <38> 1 ISTA RO I-Cache BIST Status +** <37> 1 DBS RW,1 Debug Port Select +** <36> 1 FBD RW,0 Force Bad I-Cache Data Parity +** <35> 1 FBT RW,0 Force Bad I-Cache Tag Parity +** <34> 1 FMS RW,0 Force I-Cache Miss +** <33> 1 SLE RW,0 Enable Serial Line Interrupts +** <32> 1 CRDE RW,0 Enable Correctable Error Interrupts +** <30> 1 SDE RW,0 Enable PAL Shadow Registers +** <29:28> 2 SPE RW,0 Enable I-Stream Super Page Mode +** <27> 1 HWE RW,0 Enable PALRES Instrs in Kernel Mode +** <26> 1 FPE RW,0 Enable Floating Point Instructions +** <25> 1 TMD RW,0 Disable Ibox Timeout Counter +** <24> 1 TMM RW,0 Timeout Counter Mode +** +*/ + +#define ICSR_V_TST 39 +#define ICSR_M_TST (1<<ICSR_V_TST) +#define ICSR_V_ISTA 38 +#define ICSR_M_ISTA (1<<ICSR_V_ISTA) +#define ICSR_V_DBS 37 +#define ICSR_M_DBS (1<<ICSR_V_DBS) +#define ICSR_V_FBD 36 +#define ICSR_M_FBD (1<<ICSR_V_FBD) +#define ICSR_V_FBT 35 +#define ICSR_M_FBT (1<<ICSR_V_FBT) +#define ICSR_V_FMS 34 +#define ICSR_M_FMS (1<<ICSR_V_FMS) +#define ICSR_V_SLE 33 +#define ICSR_M_SLE (1<<ICSR_V_SLE) +#define ICSR_V_CRDE 32 +#define ICSR_M_CRDE (1<<ICSR_V_CRDE) +#define ICSR_V_SDE 30 +#define ICSR_M_SDE (1<<ICSR_V_SDE) +#define ICSR_V_SPE 28 +#define ICSR_M_SPE (3<<ICSR_V_SPE) +#define ICSR_V_HWE 27 +#define ICSR_M_HWE (1<<ICSR_V_HWE) +#define ICSR_V_FPE 26 +#define ICSR_M_FPE (1<<ICSR_V_FPE) +#define ICSR_V_TMD 25 +#define ICSR_M_TMD (1<<ICSR_V_TMD) +#define ICSR_V_TMM 24 +#define ICSR_M_TMM (1<<ICSR_V_TMM) + +/* +** +** Serial Line Tranmit Register (SL_XMIT) +** +** Extent Size Name Type Function +** ------ ---- ---- ---- ------------------------------------ +** <7> 1 TMT WO,1 Serial line transmit data +** +*/ + +#define SLXMIT_V_TMT 7 +#define SLXMIT_M_TMT (1<<SLXMIT_V_TMT) + +/* +** +** Serial Line Receive Register (SL_RCV) +** +** Extent Size Name Type Function +** ------ ---- ---- ---- ------------------------------------ +** <6> 1 RCV RO Serial line receive data +** +*/ + +#define SLRCV_V_RCV 6 +#define SLRCV_M_RCV (1<<SLRCV_V_RCV) + +/* +** +** Icache Parity Error Status Register (ICPERR) Bit Summary +** +** Extent Size Name Type Function +** ------ ---- ---- ---- ------------------------------------ +** <13> 1 TMR W1C Timeout reset error +** <12> 1 TPE W1C Tag parity error +** <11> 1 DPE W1C Data parity error +** +*/ + +#define ICPERR_V_TMR 13 +#define ICPERR_M_TMR (1<<ICPERR_V_TMR) +#define ICPERR_V_TPE 12 +#define ICPERR_M_TPE (1<<ICPERR_V_TPE) +#define ICPERR_V_DPE 11 +#define ICPERR_M_DPE (1<<ICPERR_V_DPE) + +#define ICPERR_M_ALL (ICPERR_M_TMR | ICPERR_M_TPE | ICPERR_M_DPE) + +/* +** +** Exception Summary Register (EXC_SUM) Bit Summary +** +** Extent Size Name Type Function +** ------ ---- ---- ---- ------------------------------------ +** <16> 1 IOV WA Integer overflow +** <15> 1 INE WA Inexact result +** <14> 1 UNF WA Underflow +** <13> 1 FOV WA Overflow +** <12> 1 DZE WA Division by zero +** <11> 1 INV WA Invalid operation +** <10> 1 SWC WA Software completion +** +*/ + +#define EXC_V_IOV 16 +#define EXC_M_IOV (1<<EXC_V_IOV) +#define EXC_V_INE 15 +#define EXC_M_INE (1<<EXC_V_INE) +#define EXC_V_UNF 14 +#define EXC_M_UNF (1<<EXC_V_UNF) +#define EXC_V_FOV 13 +#define EXC_M_FOV (1<<EXC_V_FOV) +#define EXC_V_DZE 12 +#define EXC_M_DZE (1<<EXC_V_DZE) +#define EXC_V_INV 11 +#define EXC_M_INV (1<<EXC_V_INV) +#define EXC_V_SWC 10 +#define EXC_M_SWC (1<<EXC_V_SWC) + +/* +** +** Hardware Interrupt Clear Register (HWINT_CLR) Bit Summary +** +** Extent Size Name Type Function +** ------ ---- ---- ---- --------------------------------- +** <33> 1 SLC W1C Clear Serial Line interrupt +** <32> 1 CRDC W1C Clear Correctable Read Data interrupt +** <29> 1 PC2C W1C Clear Performance Counter 2 interrupt +** <28> 1 PC1C W1C Clear Performance Counter 1 interrupt +** <27> 1 PC0C W1C Clear Performance Counter 0 interrupt +** +*/ + +#define HWINT_V_SLC 33 +#define HWINT_M_SLC (1<<HWINT_V_SLC) +#define HWINT_V_CRDC 32 +#define HWINT_M_CRDC (1<<HWINT_V_CRDC) +#define HWINT_V_PC2C 29 +#define HWINT_M_PC2C (1<<HWINT_V_PC2C) +#define HWINT_V_PC1C 28 +#define HWINT_M_PC1C (1<<HWINT_V_PC1C) +#define HWINT_V_PC0C 27 +#define HWINT_M_PC0C (1<<HWINT_V_PC0C) + +/* +** +** Interrupt Summary Register (ISR) Bit Summary +** +** Extent Size Name Type Function +** ------ ---- ---- ---- --------------------------------- +** <34> 1 HLT RO External Halt interrupt +** <33> 1 SLI RO Serial Line interrupt +** <32> 1 CRD RO Correctable ECC errors +** <31> 1 MCK RO System Machine Check +** <30> 1 PFL RO Power Fail +** <29> 1 PC2 RO Performance Counter 2 interrupt +** <28> 1 PC1 RO Performance Counter 1 interrupt +** <27> 1 PC0 RO Performance Counter 0 interrupt +** <23> 1 I23 RO External Hardware interrupt +** <22> 1 I22 RO External Hardware interrupt +** <21> 1 I21 RO External Hardware interrupt +** <20> 1 I20 RO External Hardware interrupt +** <19> 1 ATR RO Async. System Trap request +** <18:4> 15 SIRR RO,0 Software Interrupt request +** <3:0> 4 ASTRR RO Async. System Trap request (USEK) +** +**/ + +#define ISR_V_HLT 34 +#define ISR_M_HLT (1<<ISR_V_HLT) +#define ISR_V_SLI 33 +#define ISR_M_SLI (1<<ISR_V_SLI) +#define ISR_V_CRD 32 +#define ISR_M_CRD (1<<ISR_V_CRD) +#define ISR_V_MCK 31 +#define ISR_M_MCK (1<<ISR_V_MCK) +#define ISR_V_PFL 30 +#define ISR_M_PFL (1<<ISR_V_PFL) +#define ISR_V_PC2 29 +#define ISR_M_PC2 (1<<ISR_V_PC2) +#define ISR_V_PC1 28 +#define ISR_M_PC1 (1<<ISR_V_PC1) +#define ISR_V_PC0 27 +#define ISR_M_PC0 (1<<ISR_V_PC0) +#define ISR_V_I23 23 +#define ISR_M_I23 (1<<ISR_V_I23) +#define ISR_V_I22 22 +#define ISR_M_I22 (1<<ISR_V_I22) +#define ISR_V_I21 21 +#define ISR_M_I21 (1<<ISR_V_I21) +#define ISR_V_I20 20 +#define ISR_M_I20 (1<<ISR_V_I20) +#define ISR_V_ATR 19 +#define ISR_M_ATR (1<<ISR_V_ATR) +#define ISR_V_SIRR 4 +#define ISR_M_SIRR (0x7FFF<<ISR_V_SIRR) +#define ISR_V_ASTRR 0 +#define ISR_M_ASTRR (0xF<<ISR_V_ASTRR) + +/* +** +** Mbox and D-Cache IPR Definitions: +** +*/ + +#define dtbAsn 0x200 /* WO - DTB Address Space Number */ +#define dtbCm 0x201 /* WO - DTB Current Mode */ +#define dtbTag 0x202 /* WO - DTB Tag */ +#define dtbPte 0x203 /* RW - DTB Page Table Entry */ +#define dtbPteTemp 0x204 /* RO - DTB Page Table Entry Temporary */ +#define mmStat 0x205 /* RO - D-Stream MM Fault Status */ +// replaced by ev5_defs.h #define va 0x206 /* RO - Faulting Virtual Address */ +#define vaForm 0x207 /* RO - Formatted Virtual Address */ +#define mVptBr 0x208 /* WO - Mbox Virtual Page Table Base */ +#define dtbIap 0x209 /* WO - DTB Invalidate All Process */ +#define dtbIa 0x20A /* WO - DTB Invalidate All */ +#define dtbIs 0x20B /* WO - DTB Invalidate Single */ +#define altMode 0x20C /* WO - Alternate Mode */ +// replaced by ev5_defs.h #define cc 0x20D /* WO - Cycle Counter */ +#define ccCtl 0x20E /* WO - Cycle Counter Control */ +// replaced by ev5_defs.h #define mcsr 0x20F /* RW - Mbox Control Register */ +#define dcFlush 0x210 /* WO - Dcache Flush */ +#define dcPerr 0x212 /* RW - Dcache Parity Error Status */ +#define dcTestCtl 0x213 /* RW - Dcache Test Tag Control */ +#define dcTestTag 0x214 /* RW - Dcache Test Tag */ +#define dcTestTagTemp 0x215 /* RW - Dcache Test Tag Temporary */ +#define dcMode 0x216 /* RW - Dcache Mode */ +#define mafMode 0x217 /* RW - Miss Address File Mode */ + +/* +** +** D-Stream MM Fault Status Register (MM_STAT) Bit Summary +** +** Extent Size Name Type Function +** ------ ---- ---- ---- --------------------------------- +** <16:11> 6 OPCODE RO Opcode of faulting instruction +** <10:06> 5 RA RO Ra field of faulting instruction +** <5> 1 BAD_VA RO Bad virtual address +** <4> 1 DTB_MISS RO Reference resulted in DTB miss +** <3> 1 FOW RO Fault on write +** <2> 1 FOR RO Fault on read +** <1> 1 ACV RO Access violation +** <0> 1 WR RO Reference type +** +*/ + +#define MMSTAT_V_OPC 11 +#define MMSTAT_M_OPC (0x3F<<MMSTAT_V_OPC) +#define MMSTAT_V_RA 6 +#define MMSTAT_M_RA (0x1F<<MMSTAT_V_RA) +#define MMSTAT_V_BAD_VA 5 +#define MMSTAT_M_BAD_VA (1<<MMSTAT_V_BAD_VA) +#define MMSTAT_V_DTB_MISS 4 +#define MMSTAT_M_DTB_MISS (1<<MMSTAT_V_DTB_MISS) +#define MMSTAT_V_FOW 3 +#define MMSTAT_M_FOW (1<<MMSTAT_V_FOW) +#define MMSTAT_V_FOR 2 +#define MMSTAT_M_FOR (1<<MMSTAT_V_FOR) +#define MMSTAT_V_ACV 1 +#define MMSTAT_M_ACV (1<<MMSTAT_V_ACV) +#define MMSTAT_V_WR 0 +#define MMSTAT_M_WR (1<<MMSTAT_V_WR) + + +/* +** +** Mbox Control Register (MCSR) Bit Summary +** +** Extent Size Name Type Function +** ------ ---- ---- ---- --------------------------------- +** <5> 1 DBG1 RW,0 Mbox Debug Packet Select +** <4> 1 E_BE RW,0 Ebox Big Endian mode enable +** <3> 1 DBG0 RW,0 Debug Test Select +** <2:1> 2 SP RW,0 Superpage mode enable +** <0> 1 M_BE RW,0 Mbox Big Endian mode enable +** +*/ + +#define MCSR_V_DBG1 5 +#define MCSR_M_DBG1 (1<<MCSR_V_DBG1) +#define MCSR_V_E_BE 4 +#define MCSR_M_E_BE (1<<MCSR_V_E_BE) +#define MCSR_V_DBG0 3 +#define MCSR_M_DBG0 (1<<MCSR_V_DBG0) +#define MCSR_V_SP 1 +#define MCSR_M_SP (3<<MCSR_V_SP) +#define MCSR_V_M_BE 0 +#define MCSR_M_M_BE (1<<MCSR_V_M_BE) + +/* +** +** Dcache Parity Error Status Register (DCPERR) Bit Summary +** +** Extent Size Name Type Function +** ------ ---- ---- ---- ------------------------------------ +** <5> 1 TP1 RO Dcache bank 1 tag parity error +** <4> 1 TP0 RO Dcache bank 0 tag parity error +** <3> 1 DP1 RO Dcache bank 1 data parity error +** <2> 1 DP0 RO Dcache bank 0 data parity error +** <1> 1 LOCK W1C Locks/clears bits <5:2> +** <0> 1 SEO W1C Second Dcache parity error occurred +** +*/ + +#define DCPERR_V_TP1 5 +#define DCPERR_M_TP1 (1<<DCPERR_V_TP1) +#define DCPERR_V_TP0 4 +#define DCPERR_M_TP0 (1<<DCPERR_V_TP0) +#define DCPERR_V_DP1 3 +#define DCPERR_M_DP1 (1<<DCPERR_V_DP1) +#define DCPERR_V_DP0 2 +#define DCPERR_M_DP0 (1<<DCPERR_V_DP0) +#define DCPERR_V_LOCK 1 +#define DCPERR_M_LOCK (1<<DCPERR_V_LOCK) +#define DCPERR_V_SEO 0 +#define DCPERR_M_SEO (1<<DCPERR_V_SEO) + +#define DCPERR_M_ALL (DCPERR_M_LOCK | DCPERR_M_SEO) + +/* +** +** Dcache Mode Register (DC_MODE) Bit Summary +** +** Extent Size Name Type Function +** ------ ---- ---- ---- --------------------------------- +** <4> 1 DOA RO Hardware Dcache Disable +** <3> 1 PERR_DIS RW,0 Disable Dcache Parity Error reporting +** <2> 1 BAD_DP RW,0 Force Dcache data bad parity +** <1> 1 FHIT RW,0 Force Dcache hit +** <0> 1 ENA RW,0 Software Dcache Enable +** +*/ + +#define DC_V_DOA 4 +#define DC_M_DOA (1<<DC_V_DOA) +#define DC_V_PERR_DIS 3 +#define DC_M_PERR_DIS (1<<DC_V_PERR_DIS) +#define DC_V_BAD_DP 2 +#define DC_M_BAD_DP (1<<DC_V_BAD_DP) +#define DC_V_FHIT 1 +#define DC_M_FHIT (1<<DC_V_FHIT) +#define DC_V_ENA 0 +#define DC_M_ENA (1<<DC_V_ENA) + +/* +** +** Miss Address File Mode Register (MAF_MODE) Bit Summay +** +** Extent Size Name Type Function +** ------ ---- ---- ---- --------------------------------- +** <7> 1 WB RO,0 If set, pending WB request +** <6> 1 DREAD RO,0 If set, pending D-read request +** +*/ + +#define MAF_V_WB_PENDING 7 +#define MAF_M_WB_PENDING (1<<MAF_V_WB_PENDING) +#define MAF_V_DREAD_PENDING 6 +#define MAF_M_DREAD_PENDING (1<<MAF_V_DREAD_PENDING) + +/* +** +** Cbox IPR Definitions: +** +*/ + +#define scCtl 0x0A8 /* RW - Scache Control */ +#define scStat 0x0E8 /* RO - Scache Error Status */ +#define scAddr 0x188 /* RO - Scache Error Address */ +#define bcCtl 0x128 /* WO - Bcache/System Interface Control */ +#define bcCfg 0x1C8 /* WO - Bcache Configuration Parameters */ +#define bcTagAddr 0x108 /* RO - Bcache Tag */ +#define eiStat 0x168 /* RO - Bcache/System Error Status */ +#define eiAddr 0x148 /* RO - Bcache/System Error Address */ +#define fillSyn 0x068 /* RO - Fill Syndrome */ +#define ldLock 0x1E8 /* RO - LDx_L Address */ + +/* +** +** Scache Control Register (SC_CTL) Bit Summary +** +** Extent Size Name Type Function +** ------ ---- ---- ---- --------------------------------- +** <15:13> 3 SET_EN RW,1 Set enable +** <12> 1 BLK_SIZE RW,1 Scache/Bcache block size select +** <11:08> 4 FB_DP RW,0 Force bad data parity +** <07:02> 6 TAG_STAT RW Tag status and parity +** <1> 1 FLUSH RW,0 If set, clear all tag valid bits +** <0> 1 FHIT RW,0 Force hits +** +*/ + +#define SC_V_SET_EN 13 +#define SC_M_SET_EN (7<<SC_V_SET_EN) +#define SC_V_BLK_SIZE 12 +#define SC_M_BLK_SIZE (1<<SC_V_BLK_SIZE) +#define SC_V_FB_DP 8 +#define SC_M_FB_DP (0xF<<SC_V_FB_DP) +#define SC_V_TAG_STAT 2 +#define SC_M_TAG_STAT (0x3F<<SC_V_TAG_STAT) +#define SC_V_FLUSH 1 +#define SC_M_FLUSH (1<<SC_V_FLUSH) +#define SC_V_FHIT 0 +#define SC_M_FHIT (1<<SC_V_FHIT) + +/* +** +** Bcache Control Register (BC_CTL) Bit Summary +** +** Extent Size Name Type Function +** ------ ---- ---- ---- --------------------------------- +** <27> 1 DIS_VIC_BUF WO,0 Disable Scache victim buffer +** <26> 1 DIS_BAF_BYP WO,0 Disable speculative Bcache reads +** <25> 1 DBG_MUX_SEL WO,0 Debug MUX select +** <24:19> 6 PM_MUX_SEL WO,0 Performance counter MUX select +** <18:17> 2 BC_WAVE WO,0 Number of cycles of wave pipelining +** <16> 1 TL_PIPE_LATCH WO,0 Pipe system control pins +** <15> 1 EI_DIS_ERR WO,1 Disable ECC (parity) error +** <14:13> 2 BC_BAD_DAT WO,0 Force bad data +** <12:08> 5 BC_TAG_STAT WO Bcache tag status and parity +** <7> 1 BC_FHIT WO,0 Bcache force hit +** <6> 1 EI_ECC WO,1 ECC or byte parity mode +** <5> 1 VTM_FIRST WO,1 Drive out victim block address first +** <4> 1 CORR_FILL_DAT WO,1 Correct fill data +** <3> 1 EI_CMD_GRP3 WO,0 Drive MB command to external pins +** <2> 1 EI_CMD_GRP2 WO,0 Drive LOCK & SET_DIRTY to ext. pins +** <1> 1 ALLOC_CYC WO,0 Allocate cycle for non-cached LDs. +** <0> 1 BC_ENA W0,0 Bcache enable +** +*/ +#define BC_V_DIS_SC_VIC_BUF 27 +#define BC_M_DIS_SC_VIC_BUF (1<<BC_V_DIS_SC_VIC_BUF) +#define BC_V_DIS_BAF_BYP 26 +#define BC_M_DIS_BAF_BYP (1<<BC_V_DIS_BAF_BYP) +#define BC_V_DBG_MUX_SEL 25 +#define BC_M_DBG_MUX_SEL (1<<BC_V_DBG_MUX_SEL) +#define BC_V_PM_MUX_SEL 19 +#define BC_M_PM_MUX_SEL (0x3F<<BC_V_PM_MUX_SEL) +#define BC_V_BC_WAVE 17 +#define BC_M_BC_WAVE (3<<BC_V_BC_WAVE) +#define BC_V_TL_PIPE_LATCH 16 +#define BC_M_TL_PIPE_LATCH (1<<BC_V_TL_PIPE_LATCH) +#define BC_V_EI_DIS_ERR 15 +#define BC_M_EI_DIS_ERR (1<<BC_V_EI_DIS_ERR) +#define BC_V_BC_BAD_DAT 13 +#define BC_M_BC_BAD_DAT (3<<BC_V_BC_BAD_DAT) +#define BC_V_BC_TAG_STAT 8 +#define BC_M_BC_TAG_STAT (0x1F<<BC_V_BC_TAG_STAT) +#define BC_V_BC_FHIT 7 +#define BC_M_BC_FHIT (1<<BC_V_BC_FHIT) +#define BC_V_EI_ECC_OR_PARITY 6 +#define BC_M_EI_ECC_OR_PARITY (1<<BC_V_EI_ECC_OR_PARITY) +#define BC_V_VTM_FIRST 5 +#define BC_M_VTM_FIRST (1<<BC_V_VTM_FIRST) +#define BC_V_CORR_FILL_DAT 4 +#define BC_M_CORR_FILL_DAT (1<<BC_V_CORR_FILL_DAT) +#define BC_V_EI_CMD_GRP3 3 +#define BC_M_EI_CMD_GRP3 (1<<BC_V_EI_CMD_GRP3) +#define BC_V_EI_CMD_GRP2 2 +#define BC_M_EI_CMD_GRP2 (1<<BC_V_EI_CMD_GRP2) +#define BC_V_ALLOC_CYC 1 +#define BC_M_ALLOC_CYC (1<<BC_V_ALLOC_CYC) +#define BC_V_BC_ENA 0 +#define BC_M_BC_ENA (1<<BC_V_BC_ENA) + +#define BC_K_DFAULT \ + (((BC_M_EI_DIS_ERR) | \ + (BC_M_EI_ECC_OR_PARITY) | \ + (BC_M_VTM_FIRST) | \ + (BC_M_CORR_FILL_DAT))>>1) +/* +** +** Bcache Configuration Register (BC_CONFIG) Bit Summary +** +** Extent Size Name Type Function +** ------ ---- ---- ---- --------------------------------- +** <35:29> 7 RSVD WO Reserved - Must Be Zero +** <28:20> 9 WE_CTL WO,0 Bcache write enable control +** <19:19> 1 RSVD WO,0 Reserved - Must Be Zero +** <18:16> 3 WE_OFF WO,1 Bcache fill write enable pulse offset +** <15:15> 1 RSVD WO,0 Reserved - Must Be Zero +** <14:12> 3 RD_WR_SPC WO,7 Bcache private read/write spacing +** <11:08> 4 WR_SPD WO,4 Bcache write speed in CPU cycles +** <07:04> 4 RD_SPD WO,4 Bcache read speed in CPU cycles +** <03:03> 1 RSVD WO,0 Reserved - Must Be Zero +** <02:00> 3 SIZE WO,1 Bcache size +*/ +#define BC_V_WE_CTL 20 +#define BC_M_WE_CTL (0x1FF<<BC_V_WE_CTL) +#define BC_V_WE_OFF 16 +#define BC_M_WE_OFF (0x7<<BC_V_WE_OFF) +#define BC_V_RD_WR_SPC 12 +#define BC_M_RD_WR_SPC (0x7<<BC_V_RD_WR_SPC) +#define BC_V_WR_SPD 8 +#define BC_M_WR_SPD (0xF<<BC_V_WR_SPD) +#define BC_V_RD_SPD 4 +#define BC_M_RD_SPD (0xF<<BC_V_RD_SPD) +#define BC_V_SIZE 0 +#define BC_M_SIZE (0x7<<BC_V_SIZE) + +#define BC_K_CONFIG \ + ((0x1<<BC_V_WE_OFF) | \ + (0x7<<BC_V_RD_WR_SPC) | \ + (0x4<<BC_V_WR_SPD) | \ + (0x4<<BC_V_RD_SPD) | \ + (0x1<<BC_V_SIZE)) + +/* +** +** DECchip 21164 Privileged Architecture Library Entry Offsets: +** +** Entry Name Offset (Hex) +** +** RESET 0000 +** IACCVIO 0080 +** INTERRUPT 0100 +** ITB_MISS 0180 +** DTB_MISS (Single) 0200 +** DTB_MISS (Double) 0280 +** UNALIGN 0300 +** D_FAULT 0380 +** MCHK 0400 +** OPCDEC 0480 +** ARITH 0500 +** FEN 0580 +** CALL_PAL (Privileged) 2000 +** CALL_PAL (Unprivileged) 3000 +** +*/ + +#define PAL_RESET_ENTRY 0x0000 +#define PAL_IACCVIO_ENTRY 0x0080 +#define PAL_INTERRUPT_ENTRY 0x0100 +#define PAL_ITB_MISS_ENTRY 0x0180 +#define PAL_DTB_MISS_ENTRY 0x0200 +#define PAL_DOUBLE_MISS_ENTRY 0x0280 +#define PAL_UNALIGN_ENTRY 0x0300 +#define PAL_D_FAULT_ENTRY 0x0380 +#define PAL_MCHK_ENTRY 0x0400 +#define PAL_OPCDEC_ENTRY 0x0480 +#define PAL_ARITH_ENTRY 0x0500 +#define PAL_FEN_ENTRY 0x0580 +#define PAL_CALL_PAL_PRIV_ENTRY 0x2000 +#define PAL_CALL_PAL_UNPRIV_ENTRY 0x3000 + +/* +** +** Architecturally Reserved Opcode (PALRES) Definitions: +** +*/ + +#define mtpr hw_mtpr +#define mfpr hw_mfpr + +#define ldl_a hw_ldl/a +#define ldq_a hw_ldq/a +#define stq_a hw_stq/a +#define stl_a hw_stl/a + +#define ldl_p hw_ldl/p +#define ldq_p hw_ldq/p +#define stl_p hw_stl/p +#define stq_p hw_stq/p + +/* +** Virtual PTE fetch variants of HW_LD. +*/ +#define ld_vpte hw_ldq/v + +/* +** Physical mode load-lock and store-conditional variants of +** HW_LD and HW_ST. +*/ + +#define ldq_lp hw_ldq/pl +#define stq_cp hw_stq/pc + +/* +** +** General Purpose Register Definitions: +** +*/ + +#define r0 $0 +#define r1 $1 +#define r2 $2 +#define r3 $3 +#define r4 $4 +#define r5 $5 +#define r6 $6 +#define r7 $7 +#define r8 $8 +#define r9 $9 +#define r10 $10 +#define r11 $11 +#define r12 $12 +#define r13 $13 +#define r14 $14 +#define r15 $15 +#define r16 $16 +#define r17 $17 +#define r18 $18 +#define r19 $19 +#define r20 $20 +#define r21 $21 +#define r22 $22 +#define r23 $23 +#define r24 $24 +#define r25 $25 +#define r26 $26 +#define r27 $27 +#define r28 $28 +#define r29 $29 +#define r30 $30 +#define r31 $31 + +/* +** +** Floating Point Register Definitions: +** +*/ + +#define f0 $f0 +#define f1 $f1 +#define f2 $f2 +#define f3 $f3 +#define f4 $f4 +#define f5 $f5 +#define f6 $f6 +#define f7 $f7 +#define f8 $f8 +#define f9 $f9 +#define f10 $f10 +#define f11 $f11 +#define f12 $f12 +#define f13 $f13 +#define f14 $f14 +#define f15 $f15 +#define f16 $f16 +#define f17 $f17 +#define f18 $f18 +#define f19 $f19 +#define f20 $f20 +#define f21 $f21 +#define f22 $f22 +#define f23 $f23 +#define f24 $f24 +#define f25 $f25 +#define f26 $f26 +#define f27 $f27 +#define f28 $f28 +#define f29 $f29 +#define f30 $f30 +#define f31 $f31 + +/* +** +** PAL Temporary Register Definitions: +** +*/ + +// covered by fetch distribution..pb Nov/95 + +// #define pt0 0x140 +// #define pt1 0x141 +// #define pt2 0x142 +// #define pt3 0x143 +// #define pt4 0x144 +// #define pt5 0x145 +// #define pt6 0x146 +// #define pt7 0x147 +// #define pt8 0x148 +// #define pt9 0x149 +// #define pt10 0x14A +// #define pt11 0x14B +// #define pt12 0x14C +// #define pt13 0x14D +// #define pt14 0x14E +// #define pt15 0x14F +// #define pt16 0x150 +// #define pt17 0x151 +// #define pt18 0x152 +// #define pt19 0x153 +// #define pt20 0x154 +// #define pt21 0x155 +// #define pt22 0x156 +// #define pt23 0x157 + +/* +** PAL Shadow Registers: +** +** The DECchip 21164 shadows r8-r14 and r25 when in PALmode and +** ICSR<SDE> = 1. +*/ + +#define p0 r8 /* ITB/DTB Miss Scratch */ +#define p1 r9 /* ITB/DTB Miss Scratch */ +#define p2 r10 /* ITB/DTB Miss Scratch */ +#define p3 r11 +// #define ps r11 /* Processor Status */ +#define p4 r12 /* Local Scratch */ +#define p5 r13 /* Local Scratch */ +#define p6 r14 /* Local Scratch */ +#define p7 r25 /* Local Scratch */ + +/* +** SRM Defined State Definitions: +*/ + +/* +** This table is an accounting of the DECchip 21164 storage used to +** implement the SRM defined state for OSF/1. +** +** IPR Name Internal Storage +** -------- ---------------- +** Processor Status ps, dtbCm, ipl, r11 +** Program Counter Ibox +** Interrupt Entry ptEntInt +** Arith Trap Entry ptEntArith +** MM Fault Entry ptEntMM +** Unaligned Access Entry ptEntUna +** Instruction Fault Entry ptEntIF +** Call System Entry ptEntSys +** User Stack Pointer ptUsp +** Kernel Stack Pointer ptKsp +** Kernel Global Pointer ptKgp +** System Value ptSysVal +** Page Table Base Register ptPtbr +** Virtual Page Table Base iVptBr, mVptBr +** Process Control Block Base ptPcbb +** Address Space Number itbAsn, dtbAsn +** Cycle Counter cc, ccCtl +** Float Point Enable icsr +** Lock Flag Cbox/System +** Unique PCB +** Who-Am-I ptWhami +*/ + +#define ptEntUna pt2 /* Unaligned Access Dispatch Entry */ +#define ptImpure pt3 /* Pointer To PAL Scratch Area */ +#define ptEntIF pt7 /* Instruction Fault Dispatch Entry */ +#define ptIntMask pt8 /* Interrupt Enable Mask */ +#define ptEntSys pt9 /* Call System Dispatch Entry */ +#define ptTrap pt11 +#define ptEntInt pt11 /* Hardware Interrupt Dispatch Entry */ +#define ptEntArith pt12 /* Arithmetic Trap Dispatch Entry */ +#if defined(KDEBUG) +#define ptEntDbg pt13 /* Kernel Debugger Dispatch Entry */ +#endif /* KDEBUG */ +#define ptMisc pt16 /* Miscellaneous Flags */ +#define ptWhami pt16 /* Who-Am-I Register Pt16<15:8> */ +#define ptMces pt16 /* Machine Check Error Summary Pt16<4:0> */ +#define ptSysVal pt17 /* Per-Processor System Value */ +#define ptUsp pt18 /* User Stack Pointer */ +#define ptKsp pt19 /* Kernel Stack Pointer */ +#define ptPtbr pt20 /* Page Table Base Register */ +#define ptEntMM pt21 /* MM Fault Dispatch Entry */ +#define ptKgp pt22 /* Kernel Global Pointer */ +#define ptPcbb pt23 /* Process Control Block Base */ + +/* +** +** Miscellaneous PAL State Flags (ptMisc) Bit Summary +** +** Extent Size Name Function +** ------ ---- ---- --------------------------------- +** <55:48> 8 SWAP Swap PALcode flag -- character 'S' +** <47:32> 16 MCHK Machine Check Error code +** <31:16> 16 SCB System Control Block vector +** <15:08> 8 WHAMI Who-Am-I identifier +** <04:00> 5 MCES Machine Check Error Summary bits +** +*/ + +#define PT16_V_MCES 0 +#define PT16_V_WHAMI 8 +#define PT16_V_SCB 16 +#define PT16_V_MCHK 32 +#define PT16_V_SWAP 48 + +#endif /* DC21164FROMGASSOURCES_INCLUDED */ diff --git a/system/alpha/h/ev5_alpha_defs.h b/system/alpha/h/ev5_alpha_defs.h new file mode 100644 index 000000000..d0264a4ca --- /dev/null +++ b/system/alpha/h/ev5_alpha_defs.h @@ -0,0 +1,314 @@ +/* + * Copyright (c) 1993 The Hewlett-Packard Development Company + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef EV5_ALPHA_DEFS_INCLUDED +#define EV5_ALPHA_DEFS_INCLUDED 1 + +// from ev5_alpha_defs.mar from Lance's fetch directory +// Lower-caseified and $ signs removed ... pb Nov/95 + +// +// PS Layout - PS +// Loc Size name function +// ------ ------ ______ ----------------------------------- +// <31:29> 3 SA stack alignment +// <31:13> 24 RES Reserved MBZ +// <12:8> 5 IPL Priority level +// <7> 1 VMM Virtual Mach Monitor +// <6:5> 2 RES Reserved MBZ +// <4:3> 2 CM Current Mode +// <2> 1 IP Interrupt Pending +// <1:0> 2 SW Software bits +// + +#define ps_v_sw 0 +#define ps_m_sw (3<<ps_v_sw) + +#define ps_v_ip 2 +#define ps_m_ip (1<<ps_v_ip) + +#define ps_v_cm 3 +#define ps_m_cm (3<<ps_v_cm) + +#define ps_v_vmm 7 +#define ps_m_vmm (1<<ps_v_vmm) + +#define ps_v_ipl 8 +#define ps_m_ipl (0x1f<<ps_v_ipl) + +#define ps_v_sp (0x38) +#define ps_m_sp (0x3f<<ps_v_sp) + + +#define ps_c_kern (0x00) +#define ps_c_exec (0x08) +#define ps_c_supr (0x10) +#define ps_c_user (0x18) +#define ps_c_ipl0 (0x0000) +#define ps_c_ipl1 (0x0100) +#define ps_c_ipl2 (0x0200) +#define ps_c_ipl3 (0x0300) +#define ps_c_ipl4 (0x0400) +#define ps_c_ipl5 (0x0500) +#define ps_c_ipl6 (0x0600) +#define ps_c_ipl7 (0x0700) +#define ps_c_ipl8 (0x0800) +#define ps_c_ipl9 (0x0900) +#define ps_c_ipl10 (0x0A00) +#define ps_c_ipl11 (0x0B00) +#define ps_c_ipl12 (0x0C00) +#define ps_c_ipl13 (0x0D00) +#define ps_c_ipl14 (0x0E00) +#define ps_c_ipl15 (0x0F00) +#define ps_c_ipl16 (0x1000) +#define ps_c_ipl17 (0x1100) +#define ps_c_ipl18 (0x1200) +#define ps_c_ipl19 (0x1300) +#define ps_c_ipl20 (0x1400) +#define ps_c_ipl21 (0x1500) +#define ps_c_ipl22 (0x1600) +#define ps_c_ipl23 (0x1700) +#define ps_c_ipl24 (0x1800) +#define ps_c_ipl25 (0x1900) +#define ps_c_ipl26 (0x1A00) +#define ps_c_ipl27 (0x1B00) +#define ps_c_ipl28 (0x1C00) +#define ps_c_ipl29 (0x1D00) +#define ps_c_ipl30 (0x1E00) +#define ps_c_ipl31 (0x1F00) + +// +// PTE layout - symbol prefix PTE_ +// +// Loc Size name function +// ------ ------ ------ ----------------------------------- +// <63:32> 32 PFN Page Frame Number +// <31:16> 16 SOFT Bits reserved for software use +// <15> 1 UWE User write enable +// <14> 1 SWE Super write enable +// <13> 1 EWE Exec write enable +// <12> 1 KWE Kernel write enable +// <11> 1 URE User read enable +// <10> 1 SRE Super read enable +// <9> 1 ERE Exec read enable +// <8> 1 KRE Kernel read enable +// <7:6> 2 RES Reserved SBZ +// <5> 1 HPF Huge Page Flag +// <4> 1 ASM Wild card address space number match +// <3> 1 FOE Fault On execute +// <2> 1 FOW Fault On Write +// <1> 1 FOR Fault On Read +// <0> 1 V valid bit +// + +#define pte_v_pfn 32 +#define pte_m_soft (0xFFFF0000) +#define pte_v_soft 16 +#define pte_m_uwe (0x8000) +#define pte_v_uwe 15 +#define pte_m_swe (0x4000) +#define pte_v_swe 14 +#define pte_m_ewe (0x2000) +#define pte_v_ewe 13 +#define pte_m_kwe (0x1000) +#define pte_v_kwe 12 +#define pte_m_ure (0x0800) +#define pte_v_ure 11 +#define pte_m_sre (0x0400) +#define pte_v_sre 10 +#define pte_m_ere (0x0200) +#define pte_v_ere 9 +#define pte_m_kre (0x0100) +#define pte_v_kre 8 +#define pte_m_hpf (0x0020) +#define pte_v_hpf 5 +#define pte_m_asm (0x0010) +#define pte_v_asm 4 +#define pte_m_foe (0x0008) +#define pte_v_foe 3 +#define pte_m_fow (0x0004) +#define pte_v_fow 2 +#define pte_m_for (0x0002) +#define pte_v_for 1 +#define pte_m_v (0x0001) +#define pte_v_v 0 + +// +// VA layout - symbol prefix VA_ +// +// Loc Size name function +// ------ ------ ------- ----------------------------------- +// <42:33> 10 SEG1 First seg table offset for mapping +// <32:23> 10 SEG2 Second seg table offset for mapping +// <22:13> 10 SEG3 Third seg table offset for mapping +// <12:0> 13 OFFSET Byte within page +// + +#define va_m_offset (0x000000001FFF) +#define va_v_offset 0 +#define va_m_seg3 (0x0000007FE000) +#define va_v_seg3 13 +#define va_m_seg2 (0x0001FF800000) +#define va_v_seg2 23 +#define va_m_seg1 (0x7FE00000000) +#define va_v_seg1 33 + +// +//PRIVILEGED CONTEXT BLOCK (PCB) +// +#define pcb_q_ksp 0 +#define pcb_q_esp 8 +#define pcb_q_ssp 16 +#define pcb_q_usp 24 +#define pcb_q_ptbr 32 +#define pcb_q_asn 40 +#define pcb_q_ast 48 +#define pcb_q_fen 56 +#define pcb_q_cc 64 +#define pcb_q_unq 72 +#define pcb_q_sct 80 + +#define pcb_v_asten 0 +#define pcb_m_asten (0x0f<<pcb_v_asten) +#define pcb_v_astsr 4 +#define pcb_m_astsr (0x0f<<pcb_v_astsr) +#define pcb_v_dat 63 +#define pcb_v_pme 62 + +// +// SYSTEM CONTROL BLOCK (SCB) +// + +#define scb_v_fen (0x0010) +#define scb_v_acv (0x0080) +#define scb_v_tnv (0x0090) +#define scb_v_for (0x00A0) +#define scb_v_fow (0x00B0) +#define scb_v_foe (0x00C0) +#define scb_v_arith (0x0200) +#define scb_v_kast (0x0240) +#define scb_v_east (0x0250) +#define scb_v_sast (0x0260) +#define scb_v_uast (0x0270) +#define scb_v_unalign (0x0280) +#define scb_v_bpt (0x0400) +#define scb_v_bugchk (0x0410) +#define scb_v_opcdec (0x0420) +#define scb_v_illpal (0x0430) +#define scb_v_trap (0x0440) +#define scb_v_chmk (0x0480) +#define scb_v_chme (0x0490) +#define scb_v_chms (0x04A0) +#define scb_v_chmu (0x04B0) +#define scb_v_sw0 (0x0500) +#define scb_v_sw1 (0x0510) +#define scb_v_sw2 (0x0520) +#define scb_v_sw3 (0x0530) +#define scb_v_sw4 (0x0540) +#define scb_v_sw5 (0x0550) +#define scb_v_sw6 (0x0560) +#define scb_v_sw7 (0x0570) +#define scb_v_sw8 (0x0580) +#define scb_v_sw9 (0x0590) +#define scb_v_sw10 (0x05A0) +#define scb_v_sw11 (0x05B0) +#define scb_v_sw12 (0x05C0) +#define scb_v_sw13 (0x05D0) +#define scb_v_sw14 (0x05E0) +#define scb_v_sw15 (0x05F0) +#define scb_v_clock (0x0600) +#define scb_v_inter (0x0610) +#define scb_v_sys_corr_err (0x0620) +#define scb_v_proc_corr_err (0x0630) +#define scb_v_pwrfail (0x0640) +#define scb_v_perfmon (0x0650) +#define scb_v_sysmchk (0x0660) +#define scb_v_procmchk (0x0670) +#define scb_v_passive_rel (0x06F0) + +// +// Stack frame (FRM) +// + +#define frm_v_r2 (0x0000) +#define frm_v_r3 (0x0008) +#define frm_v_r4 (0x0010) +#define frm_v_r5 (0x0018) +#define frm_v_r6 (0x0020) +#define frm_v_r7 (0x0028) +#define frm_v_pc (0x0030) +#define frm_v_ps (0x0038) + +// +// Exeception summary register (EXS) +// +// exs_v_swc <0> ; Software completion +// exs_v_inv <1> ; Ivalid operation +// exs_v_dze <2> ; Div by zero +// exs_v_fov <3> ; Floating point overflow +// exs_v_unf <4> ; Floating point underflow +// exs_v_ine <5> ; Floating point inexact +// exs_v_iov <6> ; Floating convert to integer overflow +#define exs_v_swc 0 +#define exs_v_inv 1 +#define exs_v_dze 2 +#define exs_v_fov 3 +#define exs_v_unf 4 +#define exs_v_ine 5 +#define exs_v_iov 6 + +#define exs_m_swc (1<<exs_v_swc) +#define exs_m_inv (1<<exs_v_inv) +#define exs_m_dze (1<<exs_v_dze) +#define exs_m_fov (1<<exs_v_fov) +#define exs_m_unf (1<<exs_v_unf) +#define exs_m_ine (1<<exs_v_ine) +#define exs_m_iov (1<<exs_v_iov) + +// +// machine check error summary register (mces) +// +// mces_v_mchk <0> ; machine check in progress +// mces_v_sce <1> ; system correctable error +// mces_v_pce <2> ; processor correctable error +// mces_v_dpc <3> ; disable reporting of processor correctable errors +// mces_v_dsc <4> ; disable reporting of system correctable errors +#define mces_v_mchk 0 +#define mces_v_sce 1 +#define mces_v_pce 2 +#define mces_v_dpc 3 +#define mces_v_dsc 4 + +#define mces_m_mchk (1<<mces_v_mchk) +#define mces_m_sce (1<<mces_v_sce) +#define mces_m_pce (1<<mces_v_pce) +#define mces_m_dpc (1<<mces_v_dpc) +#define mces_m_dsc (1<<mces_v_dsc) +#define mces_m_all ((1<<mces_v_mchk) | (1<<mces_v_sce) | (1<<mces_v_pce) | (1<<mces_v_dpc) | (1<<mces_v_dsc)) + +#endif diff --git a/system/alpha/h/ev5_defs.h b/system/alpha/h/ev5_defs.h new file mode 100644 index 000000000..c8b2f5b2e --- /dev/null +++ b/system/alpha/h/ev5_defs.h @@ -0,0 +1,598 @@ +/* + * Copyright (c) 1995 The Hewlett-Packard Development Company + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef EV5_DEFS_INCLUDED +#define EV5_DEFS_INCLUDED 1 + +// adapted from the version emailed to lance..pb Nov/95 + +// In the definitions below, registers are annotated with one of the +// following symbols: +// +// RW - The register may be read and written +// RO - The register may only be read +// WO - The register may only be written +// +// For RO and WO registers, all bits and fields within the register +// are also read-only or write-only. For RW registers, each bit or +// field within the register is annotated with one of the following: +// +// RW - The bit/field may be read and written +// RO - The bit/field may be read; writes are ignored +// WO - The bit/field may be written; reads return an UNPREDICTABLE result +// WZ - The bit/field may be written; reads return a 0 +// WC - The bit/field may be read; writes cause state to clear +// RC - The bit/field may be read, which also causes state to clear; +// writes are ignored +// Architecturally-defined (SRM) registers for EVMS + +#define pt0 320 +#define pt1 321 +#define pt2 322 +#define pt3 323 +#define pt4 324 +#define pt5 325 +#define pt6 326 +#define pt7 327 +#define pt8 328 +#define pt9 329 +#define pt10 330 +#define pt11 331 +#define pt12 332 +#define pt13 333 +#define pt14 334 +#define pt15 335 +#define pt16 336 +#define pt17 337 +#define pt18 338 +#define pt19 339 +#define pt20 340 +#define pt21 341 +#define pt22 342 +#define pt23 343 +#define cbox_ipr_offset 16777200 +#define sc_ctl 168 +#define sc_stat 232 +#define sc_addr 392 +#define sc_addr_nm 392 +#define sc_addr_fhm 392 +#define bc_ctl 296 +#define bc_config 456 +#define ei_stat 360 +#define ei_addr 328 +#define fill_syn 104 +#define bc_tag_addr 264 +#define ld_lock 488 +#define aster 266 +#define astrr 265 +#define exc_addr 267 +#define exc_sum 268 +#define exc_mask 269 +#define hwint_clr 277 +#define ic_flush_ctl 281 +#define icperr_stat 282 +#define ic_perr_stat 282 +#define ic_row_map 283 +#define icsr 280 +#define ifault_va_form 274 +#define intid 273 +#define ipl 272 +#define isr 256 +#define itb_is 263 +#define itb_asn 259 +#define itb_ia 261 +#define itb_iap 262 +#define itb_pte 258 +#define itb_pte_temp 260 +#define itb_tag 257 +#define ivptbr 275 +#define pal_base 270 +#define pmctr 284 +// this is not the register ps .. pb #define ps 271 +#define sirr 264 +#define sl_txmit 278 +#define sl_rcv 279 +#define alt_mode 524 +#define cc 525 +#define cc_ctl 526 +#define dc_flush 528 +#define dcperr_stat 530 +#define dc_test_ctl 531 +#define dc_test_tag 532 +#define dc_test_tag_temp 533 +#define dtb_asn 512 +#define dtb_cm 513 +#define dtb_ia 522 +#define dtb_iap 521 +#define dtb_is 523 +#define dtb_pte 515 +#define dtb_pte_temp 516 +#define dtb_tag 514 +#define mcsr 527 +#define dc_mode 534 +#define maf_mode 535 +#define mm_stat 517 +#define mvptbr 520 +#define va 518 +#define va_form 519 +#define ev5_srm__ps 0 +#define ev5_srm__pc 0 +#define ev5_srm__asten 0 +#define ev5_srm__astsr 0 +#define ev5_srm__ipir 0 +#define ev5_srm__ipl 0 +#define ev5_srm__mces 0 +#define ev5_srm__pcbb 0 +#define ev5_srm__prbr 0 +#define ev5_srm__ptbr 0 +#define ev5_srm__scbb 0 +#define ev5_srm__sirr 0 +#define ev5_srm__sisr 0 +#define ev5_srm__tbchk 0 +#define ev5_srm__tb1a 0 +#define ev5_srm__tb1ap 0 +#define ev5_srm__tb1ad 0 +#define ev5_srm__tb1ai 0 +#define ev5_srm__tbis 0 +#define ev5_srm__ksp 0 +#define ev5_srm__esp 0 +#define ev5_srm__ssp 0 +#define ev5_srm__usp 0 +#define ev5_srm__vptb 0 +#define ev5_srm__whami 0 +#define ev5_srm__cc 0 +#define ev5_srm__unq 0 +// processor-specific iprs. +#define ev5__sc_ctl 168 +#define ev5__sc_stat 232 +#define ev5__sc_addr 392 +#define ev5__bc_ctl 296 +#define ev5__bc_config 456 +#define bc_config_k_size_1mb 1 +#define bc_config_k_size_2mb 2 +#define bc_config_k_size_4mb 3 +#define bc_config_k_size_8mb 4 +#define bc_config_k_size_16mb 5 +#define bc_config_k_size_32mb 6 +#define bc_config_k_size_64mb 7 +#define ev5__ei_stat 360 +#define ev5__ei_addr 328 +#define ev5__fill_syn 104 +#define ev5__bc_tag_addr 264 +#define ev5__aster 266 +#define ev5__astrr 265 +#define ev5__exc_addr 267 +#define exc_addr_v_pa 2 +#define exc_addr_s_pa 62 +#define ev5__exc_sum 268 +#define ev5__exc_mask 269 +#define ev5__hwint_clr 277 +#define ev5__ic_flush_ctl 281 +#define ev5__icperr_stat 282 +#define ev5__ic_perr_stat 282 +#define ev5__ic_row_map 283 +#define ev5__icsr 280 +#define ev5__ifault_va_form 274 +#define ev5__ifault_va_form_nt 274 +#define ifault_va_form_nt_v_vptb 30 +#define ifault_va_form_nt_s_vptb 34 +#define ev5__intid 273 +#define ev5__ipl 272 +#define ev5__itb_is 263 +#define ev5__itb_asn 259 +#define ev5__itb_ia 261 +#define ev5__itb_iap 262 +#define ev5__itb_pte 258 +#define ev5__itb_pte_temp 260 +#define ev5__itb_tag 257 +#define ev5__ivptbr 275 +#define ivptbr_v_vptb 30 +#define ivptbr_s_vptb 34 +#define ev5__pal_base 270 +#define ev5__pmctr 284 +#define ev5__ps 271 +#define ev5__isr 256 +#define ev5__sirr 264 +#define ev5__sl_txmit 278 +#define ev5__sl_rcv 279 +#define ev5__alt_mode 524 +#define ev5__cc 525 +#define ev5__cc_ctl 526 +#define ev5__dc_flush 528 +#define ev5__dcperr_stat 530 +#define ev5__dc_test_ctl 531 +#define ev5__dc_test_tag 532 +#define ev5__dc_test_tag_temp 533 +#define ev5__dtb_asn 512 +#define ev5__dtb_cm 513 +#define ev5__dtb_ia 522 +#define ev5__dtb_iap 521 +#define ev5__dtb_is 523 +#define ev5__dtb_pte 515 +#define ev5__dtb_pte_temp 516 +#define ev5__dtb_tag 514 +#define ev5__mcsr 527 +#define ev5__dc_mode 534 +#define ev5__maf_mode 535 +#define ev5__mm_stat 517 +#define ev5__mvptbr 520 +#define ev5__va 518 +#define ev5__va_form 519 +#define ev5__va_form_nt 519 +#define va_form_nt_s_va 19 +#define va_form_nt_v_vptb 30 +#define va_form_nt_s_vptb 34 +#define ev5s_ev5_def 10 +#define ev5_def 0 +// cbox registers. +#define sc_ctl_v_sc_fhit 0 +#define sc_ctl_v_sc_flush 1 +#define sc_ctl_s_sc_tag_stat 6 +#define sc_ctl_v_sc_tag_stat 2 +#define sc_ctl_s_sc_fb_dp 4 +#define sc_ctl_v_sc_fb_dp 8 +#define sc_ctl_v_sc_blk_size 12 +#define sc_ctl_s_sc_set_en 3 +#define sc_ctl_v_sc_set_en 13 +#define sc_ctl_s_sc_soft_repair 3 +#define sc_ctl_v_sc_soft_repair 16 +#define sc_stat_s_sc_tperr 3 +#define sc_stat_v_sc_tperr 0 +#define sc_stat_s_sc_dperr 8 +#define sc_stat_v_sc_dperr 3 +#define sc_stat_s_cbox_cmd 5 +#define sc_stat_v_cbox_cmd 11 +#define sc_stat_v_sc_scnd_err 16 +#define sc_addr_fhm_v_sc_tag_parity 4 +#define sc_addr_fhm_s_tag_stat_sb0 3 +#define sc_addr_fhm_v_tag_stat_sb0 5 +#define sc_addr_fhm_s_tag_stat_sb1 3 +#define sc_addr_fhm_v_tag_stat_sb1 8 +#define sc_addr_fhm_s_ow_mod0 2 +#define sc_addr_fhm_v_ow_mod0 11 +#define sc_addr_fhm_s_ow_mod1 2 +#define sc_addr_fhm_v_ow_mod1 13 +#define sc_addr_fhm_s_tag_lo 17 +#define sc_addr_fhm_v_tag_lo 15 +#define sc_addr_fhm_s_tag_hi 7 +#define sc_addr_fhm_v_tag_hi 32 +#define bc_ctl_v_bc_enabled 0 +#define bc_ctl_v_alloc_cyc 1 +#define bc_ctl_v_ei_opt_cmd 2 +#define bc_ctl_v_ei_opt_cmd_mb 3 +#define bc_ctl_v_corr_fill_dat 4 +#define bc_ctl_v_vtm_first 5 +#define bc_ctl_v_ei_ecc_or_parity 6 +#define bc_ctl_v_bc_fhit 7 +#define bc_ctl_s_bc_tag_stat 5 +#define bc_ctl_v_bc_tag_stat 8 +#define bc_ctl_s_bc_bad_dat 2 +#define bc_ctl_v_bc_bad_dat 13 +#define bc_ctl_v_ei_dis_err 15 +#define bc_ctl_v_tl_pipe_latch 16 +#define bc_ctl_s_bc_wave_pipe 2 +#define bc_ctl_v_bc_wave_pipe 17 +#define bc_ctl_s_pm_mux_sel 6 +#define bc_ctl_v_pm_mux_sel 19 +#define bc_ctl_v_dbg_mux_sel 25 +#define bc_ctl_v_dis_baf_byp 26 +#define bc_ctl_v_dis_sc_vic_buf 27 +#define bc_ctl_v_dis_sys_addr_par 28 +#define bc_ctl_v_read_dirty_cln_shr 29 +#define bc_ctl_v_write_read_bubble 30 +#define bc_ctl_v_bc_wave_pipe_2 31 +#define bc_ctl_v_auto_dack 32 +#define bc_ctl_v_dis_byte_word 33 +#define bc_ctl_v_stclk_delay 34 +#define bc_ctl_v_write_under_miss 35 +#define bc_config_s_bc_size 3 +#define bc_config_v_bc_size 0 +#define bc_config_s_bc_rd_spd 4 +#define bc_config_v_bc_rd_spd 4 +#define bc_config_s_bc_wr_spd 4 +#define bc_config_v_bc_wr_spd 8 +#define bc_config_s_bc_rd_wr_spc 3 +#define bc_config_v_bc_rd_wr_spc 12 +#define bc_config_s_fill_we_offset 3 +#define bc_config_v_fill_we_offset 16 +#define bc_config_s_bc_we_ctl 9 +#define bc_config_v_bc_we_ctl 20 +// cbox registers, continued +#define ei_stat_s_sys_id 4 +#define ei_stat_v_sys_id 24 +#define ei_stat_v_bc_tperr 28 +#define ei_stat_v_bc_tc_perr 29 +#define ei_stat_v_ei_es 30 +#define ei_stat_v_cor_ecc_err 31 +#define ei_stat_v_unc_ecc_err 32 +#define ei_stat_v_ei_par_err 33 +#define ei_stat_v_fil_ird 34 +#define ei_stat_v_seo_hrd_err 35 +// +#define bc_tag_addr_v_hit 12 +#define bc_tag_addr_v_tagctl_p 13 +#define bc_tag_addr_v_tagctl_d 14 +#define bc_tag_addr_v_tagctl_s 15 +#define bc_tag_addr_v_tagctl_v 16 +#define bc_tag_addr_v_tag_p 17 +#define bc_tag_addr_s_bc_tag 19 +#define bc_tag_addr_v_bc_tag 20 +// ibox and icache registers. +#define aster_v_kar 0 +#define aster_v_ear 1 +#define aster_v_sar 2 +#define aster_v_uar 3 +#define astrr_v_kar 0 +#define astrr_v_ear 1 +#define astrr_v_sar 2 +#define astrr_v_uar 3 +#define exc_addr_v_pal 0 +#define exc_sum_v_swc 10 +#define exc_sum_v_inv 11 +#define exc_sum_v_dze 12 +#define exc_sum_v_fov 13 +#define exc_sum_v_unf 14 +#define exc_sum_v_ine 15 +#define exc_sum_v_iov 16 +#define hwint_clr_v_pc0c 27 +#define hwint_clr_v_pc1c 28 +#define hwint_clr_v_pc2c 29 +#define hwint_clr_v_crdc 32 +#define hwint_clr_v_slc 33 +// ibox and icache registers, continued +#define icperr_stat_v_dpe 11 +#define icperr_stat_v_tpe 12 +#define icperr_stat_v_tmr 13 +#define ic_perr_stat_v_dpe 11 +#define ic_perr_stat_v_tpe 12 +#define ic_perr_stat_v_tmr 13 +#define icsr_v_pma 8 +#define icsr_v_pmp 9 +#define icsr_v_byt 17 +#define icsr_v_fmp 18 +#define icsr_v_im0 20 +#define icsr_v_im1 21 +#define icsr_v_im2 22 +#define icsr_v_im3 23 +#define icsr_v_tmm 24 +#define icsr_v_tmd 25 +#define icsr_v_fpe 26 +#define icsr_v_hwe 27 +#define icsr_s_spe 2 +#define icsr_v_spe 28 +#define icsr_v_sde 30 +#define icsr_v_crde 32 +#define icsr_v_sle 33 +#define icsr_v_fms 34 +#define icsr_v_fbt 35 +#define icsr_v_fbd 36 +#define icsr_v_dbs 37 +#define icsr_v_ista 38 +#define icsr_v_tst 39 +#define ifault_va_form_s_va 30 +#define ifault_va_form_v_va 3 +#define ifault_va_form_s_vptb 31 +#define ifault_va_form_v_vptb 33 +#define ifault_va_form_nt_s_va 19 +#define ifault_va_form_nt_v_va 3 +#define intid_s_intid 5 +#define intid_v_intid 0 +// ibox and icache registers, continued +#define ipl_s_ipl 5 +#define ipl_v_ipl 0 +#define itb_is_s_va 30 +#define itb_is_v_va 13 +#define itb_asn_s_asn 7 +#define itb_asn_v_asn 4 +#define itb_pte_v_asm 4 +#define itb_pte_s_gh 2 +#define itb_pte_v_gh 5 +#define itb_pte_v_kre 8 +#define itb_pte_v_ere 9 +#define itb_pte_v_sre 10 +#define itb_pte_v_ure 11 +#define itb_pte_s_pfn 27 +#define itb_pte_v_pfn 32 +#define itb_pte_temp_v_asm 13 +#define itb_pte_temp_v_kre 18 +#define itb_pte_temp_v_ere 19 +#define itb_pte_temp_v_sre 20 +#define itb_pte_temp_v_ure 21 +#define itb_pte_temp_s_gh 3 +#define itb_pte_temp_v_gh 29 +#define itb_pte_temp_s_pfn 27 +#define itb_pte_temp_v_pfn 32 +// ibox and icache registers, continued +#define itb_tag_s_va 30 +#define itb_tag_v_va 13 +#define pal_base_s_pal_base 26 +#define pal_base_v_pal_base 14 +#define pmctr_s_sel2 4 +#define pmctr_v_sel2 0 +#define pmctr_s_sel1 4 +#define pmctr_v_sel1 4 +#define pmctr_v_killk 8 +#define pmctr_v_killp 9 +#define pmctr_s_ctl2 2 +#define pmctr_v_ctl2 10 +#define pmctr_s_ctl1 2 +#define pmctr_v_ctl1 12 +#define pmctr_s_ctl0 2 +#define pmctr_v_ctl0 14 +#define pmctr_s_ctr2 14 +#define pmctr_v_ctr2 16 +#define pmctr_v_killu 30 +#define pmctr_v_sel0 31 +#define pmctr_s_ctr1 16 +#define pmctr_v_ctr1 32 +#define pmctr_s_ctr0 16 +#define pmctr_v_ctr0 48 +#define ps_v_cm0 3 +#define ps_v_cm1 4 +#define isr_s_astrr 4 +#define isr_v_astrr 0 +#define isr_s_sisr 15 +#define isr_v_sisr 4 +#define isr_v_atr 19 +#define isr_v_i20 20 +#define isr_v_i21 21 +#define isr_v_i22 22 +#define isr_v_i23 23 +#define isr_v_pc0 27 +#define isr_v_pc1 28 +#define isr_v_pc2 29 +#define isr_v_pfl 30 +#define isr_v_mck 31 +#define isr_v_crd 32 +#define isr_v_sli 33 +#define isr_v_hlt 34 +#define sirr_s_sirr 15 +#define sirr_v_sirr 4 +// ibox and icache registers, continued +#define sl_txmit_v_tmt 7 +#define sl_rcv_v_rcv 6 +// mbox and dcache registers. +#define alt_mode_v_am0 3 +#define alt_mode_v_am1 4 +#define cc_ctl_v_cc_ena 32 +#define dcperr_stat_v_seo 0 +#define dcperr_stat_v_lock 1 +#define dcperr_stat_v_dp0 2 +#define dcperr_stat_v_dp1 3 +#define dcperr_stat_v_tp0 4 +#define dcperr_stat_v_tp1 5 +// the following two registers are used exclusively for test and diagnostics. +// they should not be referenced in normal operation. +#define dc_test_ctl_v_bank0 0 +#define dc_test_ctl_v_bank1 1 +#define dc_test_ctl_v_fill_0 2 +#define dc_test_ctl_s_index 10 +#define dc_test_ctl_v_index 3 +#define dc_test_ctl_s_fill_1 19 +#define dc_test_ctl_v_fill_1 13 +#define dc_test_ctl_s_fill_2 32 +#define dc_test_ctl_v_fill_2 32 +// mbox and dcache registers, continued. +#define dc_test_tag_v_tag_par 2 +#define dc_test_tag_v_ow0 11 +#define dc_test_tag_v_ow1 12 +#define dc_test_tag_s_tag 26 +#define dc_test_tag_v_tag 13 +#define dc_test_tag_temp_v_tag_par 2 +#define dc_test_tag_temp_v_d0p0 3 +#define dc_test_tag_temp_v_d0p1 4 +#define dc_test_tag_temp_v_d1p0 5 +#define dc_test_tag_temp_v_d1p1 6 +#define dc_test_tag_temp_v_ow0 11 +#define dc_test_tag_temp_v_ow1 12 +#define dc_test_tag_temp_s_tag 26 +#define dc_test_tag_temp_v_tag 13 +#define dtb_asn_s_asn 7 +#define dtb_asn_v_asn 57 +#define dtb_cm_v_cm0 3 +#define dtb_cm_v_cm1 4 +#define dtbis_s_va0 30 +#define dtbis_v_va0 13 +#define dtb_pte_v_for 1 +#define dtb_pte_v_fow 2 +#define dtb_pte_v_asm 4 +#define dtb_pte_s_gh 2 +#define dtb_pte_v_gh 5 +#define dtb_pte_v_kre 8 +#define dtb_pte_v_ere 9 +#define dtb_pte_v_sre 10 +#define dtb_pte_v_ure 11 +#define dtb_pte_v_kwe 12 +#define dtb_pte_v_ewe 13 +#define dtb_pte_v_swe 14 +#define dtb_pte_v_uwe 15 +#define dtb_pte_s_pfn 27 +#define dtb_pte_v_pfn 32 +// mbox and dcache registers, continued. +#define dtb_pte_temp_v_for 0 +#define dtb_pte_temp_v_fow 1 +#define dtb_pte_temp_v_kre 2 +#define dtb_pte_temp_v_ere 3 +#define dtb_pte_temp_v_sre 4 +#define dtb_pte_temp_v_ure 5 +#define dtb_pte_temp_v_kwe 6 +#define dtb_pte_temp_v_ewe 7 +#define dtb_pte_temp_v_swe 8 +#define dtb_pte_temp_v_uwe 9 +#define dtb_pte_temp_v_asm 10 +#define dtb_pte_temp_s_fill_0 2 +#define dtb_pte_temp_v_fill_0 11 +#define dtb_pte_temp_s_pfn 27 +#define dtb_pte_temp_v_pfn 13 +#define dtb_tag_s_va 30 +#define dtb_tag_v_va 13 +// most mcsr bits are used for testability and diagnostics only. +// for normal operation, they will be supported in the following configuration: +// split_dcache = 1, maf_nomerge = 0, wb_flush_always = 0, wb_nomerge = 0, +// dc_ena<1:0> = 1, dc_fhit = 0, dc_bad_parity = 0 +#define mcsr_v_big_endian 0 +#define mcsr_v_sp0 1 +#define mcsr_v_sp1 2 +#define mcsr_v_mbox_sel 3 +#define mcsr_v_e_big_endian 4 +#define mcsr_v_dbg_packet_sel 5 +#define dc_mode_v_dc_ena 0 +#define dc_mode_v_dc_fhit 1 +#define dc_mode_v_dc_bad_parity 2 +#define dc_mode_v_dc_perr_dis 3 +#define dc_mode_v_dc_doa 4 +#define maf_mode_v_maf_nomerge 0 +#define maf_mode_v_wb_flush_always 1 +#define maf_mode_v_wb_nomerge 2 +#define maf_mode_v_io_nomerge 3 +#define maf_mode_v_wb_cnt_disable 4 +#define maf_mode_v_maf_arb_disable 5 +#define maf_mode_v_dread_pending 6 +#define maf_mode_v_wb_pending 7 +// mbox and dcache registers, continued. +#define mm_stat_v_wr 0 +#define mm_stat_v_acv 1 +#define mm_stat_v_for 2 +#define mm_stat_v_fow 3 +#define mm_stat_v_dtb_miss 4 +#define mm_stat_v_bad_va 5 +#define mm_stat_s_ra 5 +#define mm_stat_v_ra 6 +#define mm_stat_s_opcode 6 +#define mm_stat_v_opcode 11 +#define mvptbr_s_vptb 31 +#define mvptbr_v_vptb 33 +#define va_form_s_va 30 +#define va_form_v_va 3 +#define va_form_s_vptb 31 +#define va_form_v_vptb 33 +#define va_form_nt_s_va 19 +#define va_form_nt_v_va 3 +//.endm + +#endif diff --git a/system/alpha/h/ev5_impure.h b/system/alpha/h/ev5_impure.h new file mode 100644 index 000000000..88634a7ef --- /dev/null +++ b/system/alpha/h/ev5_impure.h @@ -0,0 +1,420 @@ +/* + * Copyright (c) 1993 The Hewlett-Packard Development Company + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef EV5_IMPURE_INCLUDED +#define EV5_IMPURE_INCLUDED + +// This uses the Hudson file format from "impure.h" but with the fields from +// the distrubuted palcode "ev5_impure.sdl" .. pboyle Nov/95 + +// file: impure.sdl +// +// PAL impure scratch area and logout area data structure definitions for +// Alpha firmware. +// +// +// module $pal_impure; +// +// Edit Date Who Description +// ---- --------- --- --------------------- +// 1 7-Jul-93 JEM Initial Entry +// 2 18-nov-93 JEM Add shadow bc_ctl and pmctr_ctl to impure area +// Delete mvptbr +// Calculate pal$logout from end of impure area +// 3 6-dec-93 JEM Add pmctr_ctl bitfield definitions +// 4 3-feb-94 JEM Remove f31,r31 from impure area; Remove bc_ctl, +// pmctr_ctl; add ic_perr_stat, pmctr, dc_perr_stat, +// sc_stat, sc_addr, sc_ctl, bc_tag_addr, ei_stat, +// ei_addr, fill_syn, ld_lock +// 5 19-feb-94 JEM add gpr constants, and add f31,r31 back in to be +// consistent with ev4 +// add cns$ipr_offset +// 6 18-apr-94 JEM Add shadow bc_ctl and pmctr_ctl to impure area again. +// 7 18-jul-94 JEM Add bc_config shadow. Add mchk$sys_base constant +// to mchk logout frame +// +// +// constant REVISION equals 7 prefix IMPURE$; // Revision number of this file +//orig + +/* +** Macros for saving/restoring data to/from the PAL impure scratch +** area. +** +** The console save state area is larger than the addressibility +** of the HW_LD/ST instructions (10-bit signed byte displacement), +** so some adjustments to the base offsets, as well as the offsets +** within each base region, are necessary. +** +** The console save state area is divided into two segments; the +** CPU-specific segment and the platform-specific segment. The +** state that is saved in the CPU-specific segment includes GPRs, +** FPRs, IPRs, halt code, MCHK flag, etc. All other state is saved +** in the platform-specific segment. +** +** The impure pointer will need to be adjusted by a different offset +** value for each region within a given segment. The SAVE and RESTORE +** macros will auto-magically adjust the offsets accordingly. +** +*/ +//#define SEXT10(X) (((X) & 0x200) ? ((X) | 0xfffffffffffffc00) : (X)) +#define SEXT10(X) ((X) & 0x3ff) +//#define SEXT10(X) (((X) << 55) >> 55) + +#define SAVE_GPR(reg,offset,base) \ + stq_p reg, (SEXT10(offset-0x200))(base) + +#define RESTORE_GPR(reg,offset,base) \ + ldq_p reg, (SEXT10(offset-0x200))(base) + + +#define SAVE_FPR(reg,offset,base) \ + stt reg, (SEXT10(offset-0x200))(base) + +#define RESTORE_FPR(reg,offset,base) \ + ldt reg, (SEXT10(offset-0x200))(base) + +#define SAVE_IPR(reg,offset,base) \ + mfpr v0, reg; \ + stq_p v0, (SEXT10(offset-CNS_Q_IPR))(base) + +#define RESTORE_IPR(reg,offset,base) \ + ldq_p v0, (SEXT10(offset-CNS_Q_IPR))(base); \ + mtpr v0, reg + +#define SAVE_SHADOW(reg,offset,base) \ + stq_p reg, (SEXT10(offset-CNS_Q_IPR))(base) + +#define RESTORE_SHADOW(reg,offset,base)\ + ldq_p reg, (SEXT10(offset-CNS_Q_IPR))(base) + +/* Structure of the processor-specific impure area */ + +/* aggregate impure struct prefix "" tag ""; + * cns$flag quadword; + * cns$hlt quadword; + */ + +/* Define base for debug monitor compatibility */ +#define CNS_Q_BASE 0x000 +#define CNS_Q_FLAG 0x100 +#define CNS_Q_HALT 0x108 + + +/* constant ( + * cns$r0,cns$r1,cns$r2,cns$r3,cns$r4,cns$r5,cns$r6,cns$r7, + * cns$r8,cns$r9,cns$r10,cns$r11,cns$r12,cns$r13,cns$r14,cns$r15, + * cns$r16,cns$r17,cns$r18,cns$r19,cns$r20,cns$r21,cns$r22,cns$r23, + * cns$r24,cns$r25,cns$r26,cns$r27,cns$r28,cns$r29,cns$r30,cns$r31 + * ) equals . increment 8 prefix "" tag ""; + * cns$gpr quadword dimension 32; + */ + +/* Offset to base of saved GPR area - 32 quadword */ +#define CNS_Q_GPR 0x110 +#define cns_gpr CNS_Q_GPR + +/* constant ( + * cns$f0,cns$f1,cns$f2,cns$f3,cns$f4,cns$f5,cns$f6,cns$f7, + * cns$f8,cns$f9,cns$f10,cns$f11,cns$f12,cns$f13,cns$f14,cns$f15, + * cns$f16,cns$f17,cns$f18,cns$f19,cns$f20,cns$f21,cns$f22,cns$f23, + * cns$f24,cns$f25,cns$f26,cns$f27,cns$f28,cns$f29,cns$f30,cns$f31 + * ) equals . increment 8 prefix "" tag ""; + * cns$fpr quadword dimension 32; + */ + +/* Offset to base of saved FPR area - 32 quadwords */ +#define CNS_Q_FPR 0x210 + +/* #t=.; + * cns$mchkflag quadword; + */ +#define CNS_Q_MCHK 0x310 + +/* constant cns$pt_offset equals .; + * constant ( + * cns$pt0,cns$pt1,cns$pt2,cns$pt3,cns$pt4,cns$pt5,cns$pt6, + * cns$pt7,cns$pt8,cns$pt9,cns$pt10,cns$pt11,cns$pt12,cns$pt13, + * cns$pt14,cns$pt15,cns$pt16,cns$pt17,cns$pt18,cns$pt19,cns$pt20, + * cns$pt21,cns$pt22,cns$pt23 + * ) equals . increment 8 prefix "" tag ""; + * cns$pt quadword dimension 24; + */ +/* Offset to base of saved PALtemp area - 25 quadwords */ +#define CNS_Q_PT 0x318 + +/* cns$shadow8 quadword; + * cns$shadow9 quadword; + * cns$shadow10 quadword; + * cns$shadow11 quadword; + * cns$shadow12 quadword; + * cns$shadow13 quadword; + * cns$shadow14 quadword; + * cns$shadow25 quadword; + */ +/* Offset to base of saved PALshadow area - 8 quadwords */ +#define CNS_Q_SHADOW 0x3D8 + +/* Offset to base of saved IPR area */ +#define CNS_Q_IPR 0x418 + +/* constant cns$ipr_offset equals .; */ +/* cns$exc_addr quadword; */ +#define CNS_Q_EXC_ADDR 0x418 +/* cns$pal_base quadword; */ +#define CNS_Q_PAL_BASE 0x420 +/* cns$mm_stat quadword; */ +#define CNS_Q_MM_STAT 0x428 +/* cns$va quadword; */ +#define CNS_Q_VA 0x430 +/* cns$icsr quadword; */ +#define CNS_Q_ICSR 0x438 +/* cns$ipl quadword; */ +#define CNS_Q_IPL 0x440 +/* cns$ps quadword; // Ibox current mode */ +#define CNS_Q_IPS 0x448 +/* cns$itb_asn quadword; */ +#define CNS_Q_ITB_ASN 0x450 +/* cns$aster quadword; */ +#define CNS_Q_ASTER 0x458 +/* cns$astrr quadword; */ +#define CNS_Q_ASTRR 0x460 +/* cns$isr quadword; */ +#define CNS_Q_ISR 0x468 +/* cns$ivptbr quadword; */ +#define CNS_Q_IVPTBR 0x470 +/* cns$mcsr quadword; */ +#define CNS_Q_MCSR 0x478 +/* cns$dc_mode quadword; */ +#define CNS_Q_DC_MODE 0x480 +/* cns$maf_mode quadword; */ +#define CNS_Q_MAF_MODE 0x488 +/* cns$sirr quadword; */ +#define CNS_Q_SIRR 0x490 +/* cns$fpcsr quadword; */ +#define CNS_Q_FPCSR 0x498 +/* cns$icperr_stat quadword; */ +#define CNS_Q_ICPERR_STAT 0x4A0 +/* cns$pmctr quadword; */ +#define CNS_Q_PM_CTR 0x4A8 +/* cns$exc_sum quadword; */ +#define CNS_Q_EXC_SUM 0x4B0 +/* cns$exc_mask quadword; */ +#define CNS_Q_EXC_MASK 0x4B8 +/* cns$intid quadword; */ +#define CNS_Q_INT_ID 0x4C0 +/* cns$dcperr_stat quadword; */ +#define CNS_Q_DCPERR_STAT 0x4C8 +/* cns$sc_stat quadword; */ +#define CNS_Q_SC_STAT 0x4D0 +/* cns$sc_addr quadword; */ +#define CNS_Q_SC_ADDR 0x4D8 +/* cns$sc_ctl quadword; */ +#define CNS_Q_SC_CTL 0x4E0 +/* cns$bc_tag_addr quadword; */ +#define CNS_Q_BC_TAG_ADDR 0x4E8 +/* cns$ei_stat quadword; */ +#define CNS_Q_EI_STAT 0x4F0 +/* cns$ei_addr quadword; */ +#define CNS_Q_EI_ADDR 0x4F8 +/* cns$fill_syn quadword; */ +#define CNS_Q_FILL_SYN 0x500 +/* cns$ld_lock quadword; */ +#define CNS_Q_LD_LOCK 0x508 +/* cns$bc_ctl quadword; // shadow of on chip bc_ctl */ +#define CNS_Q_BC_CTL 0x510 +/* cns$pmctr_ctl quadword; // saved frequency select info for performance monitor counter */ +#define CNS_Q_PM_CTL 0x518 +/* cns$bc_config quadword; // shadow of on chip bc_config */ +#define CNS_Q_BC_CFG 0x520 + +/* constant cns$size equals .; + * + * constant pal$impure_common_size equals (%x0200 +7) & %xfff8; + * constant pal$impure_specific_size equals (.+7) & %xfff8; + * constant cns$mchksize equals (.+7-#t) & %xfff8; + * constant pal$logout_area equals pal$impure_specific_size ; + * end impure; +*/ + +/* This next set of stuff came from the old code ..pb */ +#define CNS_Q_SROM_REV 0x528 +#define CNS_Q_PROC_ID 0x530 +#define CNS_Q_MEM_SIZE 0x538 +#define CNS_Q_CYCLE_CNT 0x540 +#define CNS_Q_SIGNATURE 0x548 +#define CNS_Q_PROC_MASK 0x550 +#define CNS_Q_SYSCTX 0x558 + + + +#define MACHINE_CHECK_CRD_BASE 0 +#define MACHINE_CHECK_SIZE ((CNS_Q_SYSCTX + 7 - CNS_Q_MCHK) & 0xfff8) + + + +/* + * aggregate EV5PMCTRCTL_BITS structure fill prefix PMCTR_CTL$; + * SPROCESS bitfield length 1 ; + * FILL_0 bitfield length 3 fill tag $$; + * FRQ2 bitfield length 2 ; + * FRQ1 bitfield length 2 ; + * FRQ0 bitfield length 2 ; + * CTL2 bitfield length 2 ; + * CTL1 bitfield length 2 ; + * CTL0 bitfield length 2 ; + * FILL_1 bitfield length 16 fill tag $$; + * FILL_2 bitfield length 32 fill tag $$; + * end EV5PMCTRCTL_BITS; + * + * end_module $pal_impure; + * + * module $pal_logout; + * + * // + * // Start definition of Corrected Error Frame + * // + */ + +/* + * aggregate crd_logout struct prefix "" tag ""; + */ + +#define pal_logout_area 0x600 +#define mchk_crd_base 0 + +/* mchk$crd_flag quadword; */ +#define mchk_crd_flag 0 +/* mchk$crd_offsets quadword; */ +#define mchk_crd_offsets 8 +/* + * // Pal-specific information */ +#define mchk_crd_mchk_code 0x10 +/* mchk$crd_mchk_code quadword; + * + * // CPU-specific information + * constant mchk$crd_cpu_base equals . ; + * mchk$crd_ei_addr quadword; */ +#define mchk_crd_ei_addr 0x18 +/* mchk$crd_fill_syn quadword; */ +#define mchk_crd_fill_syn 0x20 +/* mchk$crd_ei_stat quadword; */ +#define mchk_crd_ei_stat 0x28 +/* mchk$crd_isr quadword; */ +#define mchk_crd_isr 0x30 + +/* + * Hacked up constants for the turbolaser build. Hope + * this is moreless correct + */ + +#define mchk_crd_whami 0x38 +#define mchk_crd_tldev 0x40 +#define mchk_crd_tlber 0x48 +#define mchk_crd_tlesr0 0x50 +#define mchk_crd_tlesr1 0x58 +#define mchk_crd_tlesr2 0x60 +#define mchk_crd_tlesr3 0x68 +#define mchk_crd_rsvd 0x70 + + +/* + * mchk area seems different for tlaser + */ + +#define mchk_crd_size 0x80 +#define mchk_mchk_base (mchk_crd_size) + +#define mchk_tlber 0x0 +#define mchk_tlepaerr 0x8 +#define mchk_tlepderr 0x10 +#define mchk_tlepmerr 0x18 + + +/* + * // System-specific information + * constant mchk$crd_sys_base equals . ; + * constant mchk$crd_size equals (.+7) & %xfff8; + * + * end crd_logout; + * // + * // Start definition of Machine check logout Frame + * // + * aggregate logout struct prefix "" tag ""; + * mchk$flag quadword; */ +/* mchk$offsets quadword; */ +/* + * // Pal-specific information + * mchk$mchk_code quadword; */ +/* + + * mchk$pt quadword dimension 24; + * + * // CPU-specific information + * constant mchk$cpu_base equals . ; + * mchk$exc_addr quadword; + * mchk$exc_sum quadword; + * mchk$exc_mask quadword; + * mchk$pal_base quadword; + * mchk$isr quadword; + * mchk$icsr quadword; + * mchk$ic_perr_stat quadword; + * mchk$dc_perr_stat quadword; + * mchk$va quadword; + * mchk$mm_stat quadword; + * mchk$sc_addr quadword; + * mchk$sc_stat quadword; + * mchk$bc_tag_addr quadword; + * mchk$ei_addr quadword; + * mchk$fill_syn quadword; + * mchk$ei_stat quadword; + * mchk$ld_lock quadword; + * + * // System-specific information + * + * constant mchk$sys_base equals . ; + * mchk$sys_ipr1 quadword ; // Holder for system-specific stuff + * + * constant mchk$size equals (.+7) & %xfff8; + * + * + * constant mchk$crd_base equals 0 ; + * constant mchk$mchk_base equals mchk$crd_size ; + * + * + * end logout; + * + * end_module $pal_logout; +*/ + +/* + * this is lingering in the old ladbx code but looks like it was from + * ev4 days. This was 0x160 in the old days..pb + */ +#define LAF_K_SIZE MACHINE_CHECK_SIZE +#endif diff --git a/system/alpha/h/ev5_osfalpha_defs.h b/system/alpha/h/ev5_osfalpha_defs.h new file mode 100644 index 000000000..bb98503b4 --- /dev/null +++ b/system/alpha/h/ev5_osfalpha_defs.h @@ -0,0 +1,152 @@ +/* + * Copyright (c) 1993 The Hewlett-Packard Development Company + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef EV5_OSFALPHA_DEFS_INCLUDED +#define EV5_OSFALPHA_DEFS_INCLUDED 1 + +// from ev5_osfalpha_defs.mar from Lance's fetch directory +// lowercaseified and $ changed to _ and reformatting for gas...pb Nov/95 + +// +// PS Layout - PS +// Loc Size name function +// ------ ------ ----- ----------------------------------- +// <0:2> 3 IPL Prio level +// <3> 1 CM Current Mode +// + +#define osfps_v_mode 3 +#define osfps_m_mode (1<<osfps_v_mode) +#define osfps_v_ipl 0 +#define osfps_m_ipl (7<<osfps_v_ipl) + +#define osfipl_c_mchk 7 +#define osfipl_c_rt 6 +#define osfipl_c_clk 5 +#define osfipl_c_dev1 4 +#define osfipl_c_dev0 3 +#define osfipl_c_sw1 2 +#define osfipl_c_sw0 1 +#define osfipl_c_zero 0 + +#define osfint_c_mchk 2 +#define osfint_c_clk 1 +#define osfint_c_dev 3 +#define osfint_c_ip 0 +#define osfint_c_perf 4 +#define osfint_c_passrel 5 + +// +// PTE layout - symbol prefix osfpte_ +// +// Loc Size name function +// ------ ------ ------ ----------------------------------- +// <63:32> 32 PFN Page Frame Number +// <31:16> 16 SOFT Bits reserved for software use +// <15:14> 2 +// <13> 1 UWE User write enable +// <12> 1 KWE Kernel write enable +// <11:10> 2 +// <9> 1 URE User read enable +// <8> 1 KRE Kernel read enable +// <7:6> 2 RES Reserved SBZ +// <5> 1 HPF Huge Page Flag +// <4> 1 ASM Wild card address space number match +// <3> 1 FOE Fault On execute +// <2> 1 FOW Fault On Write +// <1> 1 FOR Fault On Read +// <0> 1 V valid bit +// + +#define osfpte_v_pfn 32 +#define osfpte_m_soft (0xFFFF0000) +#define osfpte_v_soft 16 +#define osfpte_m_uwe (0x2000) +#define osfpte_v_uwe 13 +#define osfpte_m_kwe (0x1000) +#define osfpte_v_kwe 12 +#define osfpte_m_ure (0x0200) +#define osfpte_v_ure 9 +#define osfpte_m_kre (0x0100) +#define osfpte_v_kre 8 +#define osfpte_m_hpf (0x0020) +#define osfpte_v_hpf 5 +#define osfpte_m_asm (0x0010) +#define osfpte_v_asm 4 +#define osfpte_m_foe (0x0008) +#define osfpte_v_foe 3 +#define osfpte_m_fow (0x0004) +#define osfpte_v_fow 2 +#define osfpte_m_for (0x0002) +#define osfpte_v_for 1 +#define osfpte_m_v (0x0001) +#define osfpte_v_v 0 + +#define osfpte_m_ksegbits (osfpte_m_kre | osfpte_m_kwe | osfpte_m_v | osfpte_m_asm) +#define osfpte_m_prot (osfpte_m_ure+osfpte_m_uwe | osfpte_m_kre | osfpte_m_kwe) + +// +// VA layout - symbol prefix VA_ +// +// Loc Size name function +// ------ ------ ------- ----------------------------------- +// <42:33> 10 SEG1 First seg table offset for mapping +// <32:23> 10 SEG2 Second seg table offset for mapping +// <22:13> 10 SEG3 Third seg table offset for mapping +// <12:0> 13 OFFSET Byte within page +// + +#define osfva_m_offset (0x000000001FFF) +#define osfva_v_offset 0 +#define osfva_m_seg3 (0x0000007FE000) +#define osfva_v_seg3 13 +#define osfva_m_seg2 (0x0001FF800000) +#define osfva_v_seg2 23 +#define osfva_m_seg1 (0x7FE00000000) +#define osfva_v_seg1 33 + +#define osfpcb_q_ksp (0x0000) +#define osfpcb_q_usp (0x0008) +#define osfpcb_q_Usp (0x0008) +#define osfpcb_q_mmptr (0x0010) +#define osfpcb_q_Mmptr (0x0010) +#define osfpcb_l_cc (0x0018) +#define osfpcb_l_asn (0x001C) +#define osfpcb_q_unique (0x0020) +#define osfpcb_q_fen (0x0028) +#define osfpcb_v_pme 62 + +#define osfsf_ps (0x00) +#define osfsf_pc (0x08) +#define osfsf_gp (0x10) +#define osfsf_a0 (0x18) +#define osfsf_a1 (0x20) +#define osfsf_a2 (0x28) +#define osfsf_c_size (0x30) + +#endif diff --git a/system/alpha/h/ev5_paldef.h b/system/alpha/h/ev5_paldef.h new file mode 100644 index 000000000..49cea5faa --- /dev/null +++ b/system/alpha/h/ev5_paldef.h @@ -0,0 +1,162 @@ +/* + * Copyright (c) 1993 The Hewlett-Packard Development Company + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef EV5_PALDEF_INCLUDED +#define EV5_PALDEF_INCLUDED 1 + +// from ev5_paldef.mar from Lance's fetch directory...pb Nov/95 +// some entries have been superceeded by the more recent evt_defs.h + +// These are lower-caseified and have the $ signs (unnecessarily we +// now discover) removed. + +// Note that at the bottom of this file is the version of ev5_defs.mar +// which is more recent than the top part of the file and contains +// overlapping information...pb Nov/95 + +#define hlt_c_reset 0 +#define hlt_c_hw_halt 1 +#define hlt_c_ksp_inval 2 +#define hlt_c_scbb_inval 3 +#define hlt_c_ptbr_inval 4 +#define hlt_c_sw_halt 5 +#define hlt_c_dbl_mchk 6 +#define hlt_c_mchk_from_pal 7 +#define hlt_c_start 32 +#define hlt_c_callback 33 +#define hlt_c_mpstart 34 +#define hlt_c_lfu_start 35 + +#define mchk_c_tperr (64<<1) +#define mchk_c_tcperr (65<<1) +#define mchk_c_herr (66<<1) +#define mchk_c_ecc_c (67<<1) +#define mchk_c_ecc_nc (68<<1) +#define mchk_c_unknown (69<<1) +#define mchk_c_cacksoft (70<<1) +#define mchk_c_bugcheck (71<<1) +#define mchk_c_os_bugcheck (72<<1) +#define mchk_c_dcperr (73<<1) +#define mchk_c_icperr (74<<1) +#define mchk_c_retryable_ird (75<<1) +#define mchk_c_proc_hrd_error (76<<1) +#define mchk_c_scperr (77<<1) +#define mchk_c_bcperr (78<<1) +//; mchk codes above 255 reserved for platform specific errors + + +#define mchk_c_read_nxm (256<<1) +#define mchk_c_sys_hrd_error (257<<1) +#define mchk_c_sys_ecc (258<<1) + +#define page_seg_size_bits 10 +#define page_offset_size_bits 13 +#define page_size_bytes 8192 +#define va_size_bits 43 +#define pa_size_bits 45 + +// replaced by ev5_defs.h #define pt0 (0x140) +// replaced by ev5_defs.h #define pt1 (0x141) +// replaced by ev5_defs.h #define pt2 (0x142) +#define pt_entuna (0x142) +// replaced by ev5_defs.h #define pt3 (0x143) +#define pt_impure (0x143) +// replaced by ev5_defs.h #define pt4 (0x144) +// replaced by ev5_defs.h #define pt5 (0x145) +// replaced by ev5_defs.h #define pt6 (0x146) +// replaced by ev5_defs.h #define pt7 (0x147) +#define pt_entif (0x147) +// replaced by ev5_defs.h #define pt8 (0x148) +#define pt_intmask (0x148) +// replaced by ev5_defs.h #define pt9 (0x149) +#define pt_entsys (0x149) +#define pt_ps (0x149) +// replaced by ev5_defs.h #define pt10 (0x14a) +// replaced by ev5_defs.h #define pt11 (0x14b) +#define pt_trap (0x14b) +#define pt_entint (0x14b) +// replaced by ev5_defs.h #define pt12 (0x14c) +#define pt_entarith (0x14c) +// replaced by ev5_defs.h #define pt13 (0x14d) +#define pt_sys0 (0x14d) +// replaced by ev5_defs.h #define pt14 (0x14e) +#define pt_sys1 (0x14e) +// replaced by ev5_defs.h #define pt15 (0x14f) +#define pt_sys2 (0x14f) +// replaced by ev5_defs.h #define pt16 (0x150) +#define pt_whami (0x150) +#define pt_mces (0x150) +#define pt_misc (0x150) +// replaced by ev5_defs.h #define pt17 (0x151) +#define pt_scc (0x151) +#define pt_sysval (0x151) +// replaced by ev5_defs.h #define pt18 (0x152) +#define pt_prbr (0x152) +#define pt_usp (0x152) +// replaced by ev5_defs.h #define pt19 (0x153) +#define pt_ksp (0x153) +// replaced by ev5_defs.h #define pt20 (0x154) +#define pt_ptbr (0x154) +// replaced by ev5_defs.h #define pt21 (0x155) +#define pt_vptbr (0x155) +#define pt_entmm (0x155) +// replaced by ev5_defs.h #define pt22 (0x156) +#define pt_scbb (0x156) +#define pt_kgp (0x156) +// replaced by ev5_defs.h #define pt23 (0x157) +#define pt_pcbb (0x157) + + +#define pt_misc_v_switch 48 +#define pt_misc_v_cm 56 + +#define mmcsr_c_tnv 0 +#define mmcsr_c_acv 1 +#define mmcsr_c_for 2 +#define mmcsr_c_foe 3 +#define mmcsr_c_fow 4 + +#define mm_stat_m_opcode (0x3F) +#define mm_stat_m_ra (0x1F) +#define evx_opc_sync (0x18) +#define EVX_OPC_SYNC (0x18) +#define evx_opc_hw_ld (0x1B) + +#define osf_a0_bpt (0x0) +#define osf_a0_bugchk (0x1) +#define osf_a0_gentrap (0x2) +#define osf_a0_fen (0x3) +#define osf_a0_opdec (0x4) + +#define ipl_machine_check 31 +#define ipl_powerfail 30 +#define ipl_perf_count 29 +#define ipl_clock 22 +#define ipl_interprocessor 22 + +#endif diff --git a/system/alpha/h/fromHudsonMacros.h b/system/alpha/h/fromHudsonMacros.h new file mode 100644 index 000000000..68f8999c0 --- /dev/null +++ b/system/alpha/h/fromHudsonMacros.h @@ -0,0 +1,88 @@ +/* + * Copyright (c) 1993-1994 The Hewlett-Packard Development Company + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef HUDSON_MACROS_LOADED +#define HUDSON_MACROS_LOADED 1 + +#define STALL \ + mfpr r31, pt0 + +#define NOP \ + bis $31, $31, $31 + +/* +** Align code on an 8K byte page boundary. +*/ + +#define ALIGN_PAGE \ + .align 13 + +/* +** Align code on a 32 byte block boundary. +*/ + +#define ALIGN_BLOCK \ + .align 5 + +/* +** Align code on a quadword boundary. +*/ + +#define ALIGN_BRANCH \ + .align 3 + +/* +** Hardware vectors go in .text 0 sub-segment. +*/ + +#define HDW_VECTOR(offset) \ + . = offset + +/* +** Privileged CALL_PAL functions are in .text 1 sub-segment. +*/ + +#define CALL_PAL_PRIV(vector) \ + . = (PAL_CALL_PAL_PRIV_ENTRY+(vector<<6)) + +/* +** Unprivileged CALL_PAL functions are in .text 1 sub-segment, +** the privileged bit is removed from these vectors. +*/ + +#define CALL_PAL_UNPRIV(vector) \ + . = (PAL_CALL_PAL_UNPRIV_ENTRY+((vector&0x3F)<<6)) + +/* +** Implements a load "immediate" longword function +*/ +#define LDLI(reg,val) \ + ldah reg, ((val+0x8000) >> 16)(zero); \ + lda reg, (val&0xffff)(reg) + +#endif diff --git a/system/alpha/h/fromHudsonOsf.h b/system/alpha/h/fromHudsonOsf.h new file mode 100644 index 000000000..e1dfc8171 --- /dev/null +++ b/system/alpha/h/fromHudsonOsf.h @@ -0,0 +1,483 @@ +/* + * Copyright (c) 1993-1994 The Hewlett-Packard Development Company + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef FROMHUDSONOSF_INCLUDED +#define FROMHUDSONOSF_INCLUDED 1 + +#define __OSF_LOADED 1 +/* +** Seg0 and Seg1 Virtual Address (VA) Format +** +** Loc Size Name Function +** ----- ---- ---- --------------------------------- +** <42:33> 10 SEG1 First level page table offset +** <32:23> 10 SEG2 Second level page table offset +** <22:13> 10 SEG3 Third level page table offset +** <12:00> 13 OFFSET Byte within page offset +*/ + +#define VA_V_SEG1 33 +#define VA_M_SEG1 (0x3FF<<VA_V_SEG1) +#define VA_V_SEG2 23 +#define VA_M_SEG2 (0x3FF<<VA_V_SEG2) +#define VA_V_SEG3 13 +#define VA_M_SEG3 (0x3FF<<VA_V_SEG3) +#define VA_V_OFFSET 0 +#define VA_M_OFFSET 0x1FFF + +/* +** Virtual Address Options: 8K byte page size +*/ + +#define VA_S_SIZE 43 +#define VA_S_OFF 13 +#define va_s_off 13 +#define VA_S_SEG 10 +#define VA_S_PAGE_SIZE 8192 + +/* +** Page Table Entry (PTE) Format +** +** Extent Size Name Function +** ------ ---- ---- --------------------------------- +** <63:32> 32 PFN Page Frame Number +** <31:16> 16 SW Reserved for software +** <15:14> 2 RSV0 Reserved for hardware SBZ +** <13> 1 UWE User Write Enable +** <12> 1 KWE Kernel Write Enable +** <11:10> 2 RSV1 Reserved for hardware SBZ +** <9> 1 URE User Read Enable +** <8> 1 KRE Kernel Read Enable +** <7> 1 RSV2 Reserved for hardware SBZ +** <6:5> 2 GH Granularity Hint +** <4> 1 ASM Address Space Match +** <3> 1 FOE Fault On Execute +** <2> 1 FOW Fault On Write +** <1> 1 FOR Fault On Read +** <0> 1 V Valid +*/ + +#define PTE_V_PFN 32 +#define PTE_M_PFN 0xFFFFFFFF00000000 +#define PTE_V_SW 16 +#define PTE_M_SW 0x00000000FFFF0000 +#define PTE_V_UWE 13 +#define PTE_M_UWE (1<<PTE_V_UWE) +#define PTE_V_KWE 12 +#define PTE_M_KWE (1<<PTE_V_KWE) +#define PTE_V_URE 9 +#define PTE_M_URE (1<<PTE_V_URE) +#define PTE_V_KRE 8 +#define PTE_M_KRE (1<<PTE_V_KRE) +#define PTE_V_GH 5 +#define PTE_M_GH (3<<PTE_V_GH) +#define PTE_V_ASM 4 +#define PTE_M_ASM (1<<PTE_V_ASM) +#define PTE_V_FOE 3 +#define PTE_M_FOE (1<<PTE_V_FOE) +#define PTE_V_FOW 2 +#define PTE_M_FOW (1<<PTE_V_FOW) +#define PTE_V_FOR 1 +#define PTE_M_FOR (1<<PTE_V_FOR) +#define PTE_V_VALID 0 +#define PTE_M_VALID (1<<PTE_V_VALID) + +#define PTE_M_KSEG 0x1111 +#define PTE_M_PROT 0x3300 +#define pte_m_prot 0x3300 + +/* +** System Entry Instruction Fault (entIF) Constants: +*/ + +#define IF_K_BPT 0x0 +#define IF_K_BUGCHK 0x1 +#define IF_K_GENTRAP 0x2 +#define IF_K_FEN 0x3 +#define IF_K_OPCDEC 0x4 + +/* +** System Entry Hardware Interrupt (entInt) Constants: +*/ + +#define INT_K_IP 0x0 +#define INT_K_CLK 0x1 +#define INT_K_MCHK 0x2 +#define INT_K_DEV 0x3 +#define INT_K_PERF 0x4 + +/* +** System Entry MM Fault (entMM) Constants: +*/ + +#define MM_K_TNV 0x0 +#define MM_K_ACV 0x1 +#define MM_K_FOR 0x2 +#define MM_K_FOE 0x3 +#define MM_K_FOW 0x4 + +/* +** Process Control Block (PCB) Offsets: +*/ + +#define PCB_Q_KSP 0x0000 +#define PCB_Q_USP 0x0008 +#define PCB_Q_PTBR 0x0010 +#define PCB_L_PCC 0x0018 +#define PCB_L_ASN 0x001C +#define PCB_Q_UNIQUE 0x0020 +#define PCB_Q_FEN 0x0028 +#define PCB_Q_RSV0 0x0030 +#define PCB_Q_RSV1 0x0038 + +/* +** Processor Status Register (PS) Bit Summary +** +** Extent Size Name Function +** ------ ---- ---- --------------------------------- +** <3> 1 CM Current Mode +** <2:0> 3 IPL Interrupt Priority Level +**/ + +#define PS_V_CM 3 +#define PS_M_CM (1<<PS_V_CM) +#define PS_V_IPL 0 +#define PS_M_IPL (7<<PS_V_IPL) + +#define PS_K_KERN (0<<PS_V_CM) +#define PS_K_USER (1<<PS_V_CM) + +#define IPL_K_ZERO 0x0 +#define IPL_K_SW0 0x1 +#define IPL_K_SW1 0x2 +#define IPL_K_DEV0 0x3 +#define IPL_K_DEV1 0x4 +#define IPL_K_CLK 0x5 +#define IPL_K_RT 0x6 +#define IPL_K_PERF 0x6 +#define IPL_K_PFAIL 0x6 +#define IPL_K_MCHK 0x7 + +#define IPL_K_LOW 0x0 +#define IPL_K_HIGH 0x7 + +/* +** SCB Offset Definitions: +*/ + +#define SCB_Q_FEN 0x0010 +#define SCB_Q_ACV 0x0080 +#define SCB_Q_TNV 0x0090 +#define SCB_Q_FOR 0x00A0 +#define SCB_Q_FOW 0x00B0 +#define SCB_Q_FOE 0x00C0 +#define SCB_Q_ARITH 0x0200 +#define SCB_Q_KAST 0x0240 +#define SCB_Q_EAST 0x0250 +#define SCB_Q_SAST 0x0260 +#define SCB_Q_UAST 0x0270 +#define SCB_Q_UNALIGN 0x0280 +#define SCB_Q_BPT 0x0400 +#define SCB_Q_BUGCHK 0x0410 +#define SCB_Q_OPCDEC 0x0420 +#define SCB_Q_ILLPAL 0x0430 +#define SCB_Q_TRAP 0x0440 +#define SCB_Q_CHMK 0x0480 +#define SCB_Q_CHME 0x0490 +#define SCB_Q_CHMS 0x04A0 +#define SCB_Q_CHMU 0x04B0 +#define SCB_Q_SW0 0x0500 +#define SCB_Q_SW1 0x0510 +#define SCB_Q_SW2 0x0520 +#define SCB_Q_SW3 0x0530 +#define SCB_Q_SW4 0x0540 +#define SCB_Q_SW5 0x0550 +#define SCB_Q_SW6 0x0560 +#define SCB_Q_SW7 0x0570 +#define SCB_Q_SW8 0x0580 +#define SCB_Q_SW9 0x0590 +#define SCB_Q_SW10 0x05A0 +#define SCB_Q_SW11 0x05B0 +#define SCB_Q_SW12 0x05C0 +#define SCB_Q_SW13 0x05D0 +#define SCB_Q_SW14 0x05E0 +#define SCB_Q_SW15 0x05F0 +#define SCB_Q_CLOCK 0x0600 +#define SCB_Q_INTER 0x0610 +#define SCB_Q_SYSERR 0x0620 +#define SCB_Q_PROCERR 0x0630 +#define SCB_Q_PWRFAIL 0x0640 +#define SCB_Q_PERFMON 0x0650 +#define SCB_Q_SYSMCHK 0x0660 +#define SCB_Q_PROCMCHK 0x0670 +#define SCB_Q_PASSREL 0x0680 + +/* +** Stack Frame (FRM) Offsets: +** +** There are two types of system entries for OSF/1 - those for the +** callsys CALL_PAL function and those for exceptions and interrupts. +** Both entry types use the same stack frame layout. The stack frame +** contains space for the PC, the PS, the saved GP, and the saved +** argument registers a0, a1, and a2. On entry, SP points to the +** saved PS. +*/ + +#define FRM_Q_PS 0x0000 +#define FRM_Q_PC 0x0008 +#define FRM_Q_GP 0x0010 +#define FRM_Q_A0 0x0018 +#define FRM_Q_A1 0x0020 +#define FRM_Q_A2 0x0028 + +#define FRM_K_SIZE 48 + +#define STACK_FRAME(tmp1,tmp2) \ + sll ps, 63-PS_V_CM, p7; \ + bge p7, 0f; \ + bis zero, zero, ps; \ + mtpr sp, ptUsp; \ + mfpr sp, ptKsp; \ +0: lda sp, 0-FRM_K_SIZE(sp); \ + stq tmp1, FRM_Q_PS(sp); \ + stq tmp2, FRM_Q_PC(sp); \ + stq gp, FRM_Q_GP(sp); \ + stq a0, FRM_Q_A0(sp); \ + stq a1, FRM_Q_A1(sp); \ + stq a2, FRM_Q_A2(sp) + +/* +** Halt Codes: +*/ + +#define HLT_K_RESET 0x0000 +#define HLT_K_HW_HALT 0x0001 +#define HLT_K_KSP_INVAL 0x0002 +#define HLT_K_SCBB_INVAL 0x0003 +#define HLT_K_PTBR_INVAL 0x0004 +#define HLT_K_SW_HALT 0x0005 +#define HLT_K_DBL_MCHK 0x0006 +#define HLT_K_MCHK_FROM_PAL 0x0007 + +/* +** Machine Check Codes: +*/ + +#define MCHK_K_TPERR 0x0080 +#define MCHK_K_TCPERR 0x0082 +#define MCHK_K_HERR 0x0084 +#define MCHK_K_ECC_C 0x0086 +#define MCHK_K_ECC_NC 0x0088 +#define MCHK_K_UNKNOWN 0x008A +#define MCHK_K_CACKSOFT 0x008C +#define MCHK_K_BUGCHECK 0x008E +#define MCHK_K_OS_BUGCHECK 0x0090 +#define MCHK_K_DCPERR 0x0092 +#define MCHK_K_ICPERR 0x0094 +#define MCHK_K_RETRY_IRD 0x0096 +#define MCHK_K_PROC_HERR 0x0098 + +/* +** System Machine Check Codes: +*/ + +#define MCHK_K_READ_NXM 0x0200 +#define MCHK_K_SYS_HERR 0x0202 + +/* +** Machine Check Error Status Summary (MCES) Register Format +** +** Extent Size Name Function +** ------ ---- ---- --------------------------------- +** <0> 1 MIP Machine check in progress +** <1> 1 SCE System correctable error in progress +** <2> 1 PCE Processor correctable error in progress +** <3> 1 DPC Disable PCE error reporting +** <4> 1 DSC Disable SCE error reporting +*/ + +#define MCES_V_MIP 0 +#define MCES_M_MIP (1<<MCES_V_MIP) +#define MCES_V_SCE 1 +#define MCES_M_SCE (1<<MCES_V_SCE) +#define MCES_V_PCE 2 +#define MCES_M_PCE (1<<MCES_V_PCE) +#define MCES_V_DPC 3 +#define MCES_M_DPC (1<<MCES_V_DPC) +#define MCES_V_DSC 4 +#define MCES_M_DSC (1<<MCES_V_DSC) + +#define MCES_M_ALL (MCES_M_MIP | MCES_M_SCE | MCES_M_PCE | MCES_M_DPC \ + | MCES_M_DSC) + +/* +** Who-Am-I (WHAMI) Register Format +** +** Extent Size Name Function +** ------ ---- ---- --------------------------------- +** <7:0> 8 ID Who-Am-I identifier +** <15:8> 1 SWAP Swap PALcode flag - character 'S' +*/ + +#define WHAMI_V_SWAP 8 +#define WHAMI_M_SWAP (1<<WHAMI_V_SWAP) +#define WHAMI_V_ID 0 +#define WHAMI_M_ID 0xFF + +#define WHAMI_K_SWAP 0x53 /* Character 'S' */ + +/* +** Conventional Register Usage Definitions +** +** Assembler temporary `at' is `AT' so it doesn't conflict with the +** `.set at' assembler directive. +*/ + +#define v0 $0 /* Function Return Value Register */ +#define t0 $1 /* Scratch (Temporary) Registers ... */ +#define t1 $2 +#define t2 $3 +#define t3 $4 +#define t4 $5 +#define t5 $6 +#define t6 $7 +#define t7 $8 +#define s0 $9 /* Saved (Non-Volatile) Registers ... */ +#define s1 $10 +#define s2 $11 +#define s3 $12 +#define s4 $13 +#define s5 $14 +#define fp $15 /* Frame Pointer Register, Or S6 */ +#define s6 $15 +#define a0 $16 /* Argument Registers ... */ +#define a1 $17 +#define a2 $18 +#define a3 $19 +#define a4 $20 +#define a5 $21 +#define t8 $22 /* Scratch (Temporary) Registers ... */ +#define t9 $23 +#define t10 $24 +#define t11 $25 +#define ra $26 /* Return Address Register */ +#define pv $27 /* Procedure Value Register, Or T12 */ +#define t12 $27 +#define AT $28 /* Assembler Temporary (Volatile) Register */ +#define gp $29 /* Global Pointer Register */ +#define sp $30 /* Stack Pointer Register */ +#define zero $31 /* Zero Register */ + +/* +** OSF/1 Unprivileged CALL_PAL Entry Offsets: +** +** Entry Name Offset (Hex) +** +** bpt 0080 +** bugchk 0081 +** callsys 0083 +** imb 0086 +** rdunique 009E +** wrunique 009F +** gentrap 00AA +** dbgstop 00AD +*/ + +#define UNPRIV 0x80 +#define PAL_BPT_ENTRY 0x80 +#define PAL_BUGCHK_ENTRY 0x81 +#define PAL_CALLSYS_ENTRY 0x83 +#define PAL_IMB_ENTRY 0x86 +#define PAL_RDUNIQUE_ENTRY 0x9E +#define PAL_WRUNIQUE_ENTRY 0x9F +#define PAL_GENTRAP_ENTRY 0xAA + +#if defined(KDEBUG) +#define PAL_DBGSTOP_ENTRY 0xAD +/* #define NUM_UNPRIV_CALL_PALS 10 */ +#else +/* #define NUM_UNPRIV_CALL_PALS 9 */ +#endif /* KDEBUG */ + +/* +** OSF/1 Privileged CALL_PAL Entry Offsets: +** +** Entry Name Offset (Hex) +** +** halt 0000 +** cflush 0001 +** draina 0002 +** cserve 0009 +** swppal 000A +** rdmces 0010 +** wrmces 0011 +** wrfen 002B +** wrvptptr 002D +** swpctx 0030 +** wrval 0031 +** rdval 0032 +** tbi 0033 +** wrent 0034 +** swpipl 0035 +** rdps 0036 +** wrkgp 0037 +** wrusp 0038 +** rdusp 003A +** whami 003C +** retsys 003D +** rti 003F +*/ + +#define PAL_HALT_ENTRY 0x0000 +#define PAL_CFLUSH_ENTRY 0x0001 +#define PAL_DRAINA_ENTRY 0x0002 +#define PAL_CSERVE_ENTRY 0x0009 +#define PAL_SWPPAL_ENTRY 0x000A +#define PAL_WRIPIR_ENTRY 0x000D +#define PAL_RDMCES_ENTRY 0x0010 +#define PAL_WRMCES_ENTRY 0x0011 +#define PAL_WRFEN_ENTRY 0x002B +#define PAL_WRVPTPTR_ENTRY 0x002D +#define PAL_SWPCTX_ENTRY 0x0030 +#define PAL_WRVAL_ENTRY 0x0031 +#define PAL_RDVAL_ENTRY 0x0032 +#define PAL_TBI_ENTRY 0x0033 +#define PAL_WRENT_ENTRY 0x0034 +#define PAL_SWPIPL_ENTRY 0x0035 +#define PAL_RDPS_ENTRY 0x0036 +#define PAL_WRKGP_ENTRY 0x0037 +#define PAL_WRUSP_ENTRY 0x0038 +#define PAL_RDUSP_ENTRY 0x003A +#define PAL_WHAMI_ENTRY 0x003C +#define PAL_RETSYS_ENTRY 0x003D +#define PAL_RTI_ENTRY 0x003F + +#define NUM_PRIV_CALL_PALS 23 + +#endif + diff --git a/system/alpha/h/rpb.h b/system/alpha/h/rpb.h new file mode 100644 index 000000000..1adaf82e7 --- /dev/null +++ b/system/alpha/h/rpb.h @@ -0,0 +1,387 @@ +/* + * Copyright (c) 1990 The Hewlett-Packard Development Company + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +/* + * Copyright (c) 1994, 1995, 1996 Carnegie-Mellon University. + * All rights reserved. + * + * Author: Keith Bostic, Chris G. Demetriou + * + * Permission to use, copy, modify and distribute this software and + * its documentation is hereby granted, provided that both the copyright + * notice and this permission notice appear in all copies of the + * software, derivative works or modified versions, and any portions + * thereof, and that both notices appear in supporting documentation. + * + * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" + * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND + * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. + * + * Carnegie Mellon requests users of this software to return to + * + * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU + * School of Computer Science + * Carnegie Mellon University + * Pittsburgh PA 15213-3890 + * + * any improvements or extensions that they make and grant Carnegie the + * rights to redistribute these changes. + */ + +/* + * Defines for the architected startup addresses. + */ +#define HWRPB_ADDR 0x10000000 /* 256 MB */ +#define BOOT_ADDR 0x20000000 /* 512 MB */ +#define PGTBL_ADDR 0x40000000 /* 1 GB */ + +/* + * Values for the "haltcode" field in the per-cpu portion of the HWRPB + * + * Bit defines for the "sysvar" field in the HWRPB. + * Each platform has different values for SYSBOARD and IOBOARD bits. + */ +#define HALT_PWRUP 0 /* power up */ +#define HALT_OPR 1 /* operator issued halt cmd */ +#define HALT_KSTK 2 /* kernel stack not valid */ +#define HALT_SCBB 3 /* invalid SCBB */ +#define HALT_PTBR 4 /* invalid PTBR */ +#define HALT_EXE 5 /* kernel executed halt instruction */ +#define HALT_DBLE 6 /* double error abort */ + +/* + * Bit defines for the "state" field in the per-cpu portion of the HWRPB + */ +#define STATE_BIP 0x00000001 /* bootstrap in progress */ +#define STATE_RC 0x00000002 /* restart capable */ +#define STATE_PA 0x00000004 /* processor available to OS */ +#define STATE_PP 0x00000008 /* processor present */ +#define STATE_OH 0x00000010 /* operator halted */ +#define STATE_CV 0x00000020 /* context valid */ +#define STATE_PV 0x00000040 /* PALcode valid */ +#define STATE_PMV 0x00000080 /* PALcode memory valid */ +#define STATE_PL 0x00000100 /* PALcode loaded */ +#define STATE_HALT_MASK 0x00ff0000 /* Mask for Halt Requested field */ +#define STATE_DEFAULT 0x00000000 /* Default (no specific action) */ +#define STATE_SVRS_TERM 0x00010000 /* SAVE_TERM/RESTORE_TERM Exit */ +#define STATE_COLD_BOOT 0x00020000 /* Cold Bootstrap Requested */ +#define STATE_WARM_BOOT 0x00030000 /* Warm Bootstrap Requested */ +#define STATE_HALT 0x00040000 /* Remain halted (no restart) */ + + +#define SV_PF_RSVD 0x00000000 /* RESERVED */ +#define SV_RESERVED 0x00000000 /* All STS bits; 0 for back compat */ +#define SV_MPCAP 0x00000001 /* MP capable */ +#define SV_PF_UNITED 0x00000020 /* United */ +#define SV_PF_SEPARATE 0x00000040 /* Separate */ +#define SV_PF_FULLBB 0x00000060 /* Full battery backup */ +#define SV_POWERFAIL 0x000000e0 /* Powerfail implementation */ +#define SV_PF_RESTART 0x00000100 /* Powerfail restart */ + +#define SV_GRAPHICS 0x00000200 /* Embedded graphics processor */ + +#define SV_STS_MASK 0x0000fc00 /* STS bits - system and I/O board */ +#define SV_SANDPIPER 0x00000400 /* others define system platforms */ +#define SV_FLAMINGO 0x00000800 /* STS BIT SETTINGS */ +#define SV_HOTPINK 0x00000c00 /* STS BIT SETTINGS */ +#define SV_FLAMINGOPLUS 0x00001000 /* STS BIT SETTINGS */ +#define SV_ULTRA 0x00001400 /* STS BIT SETTINGS */ +#define SV_SANDPLUS 0x00001800 /* STS BIT SETTINGS */ +#define SV_SANDPIPER45 0x00001c00 /* STS BIT SETTINGS */ +#define SV_FLAMINGO45 0x00002000 /* STS BIT SETTINGS */ + +#define SV_SABLE 0x00000400 /* STS BIT SETTINGS */ + +#define SV_KN20AA 0x00000400 /* STS BIT SETTINGS */ + +/* + * Values for the "console type" field in the CTB portion of the HWRPB + */ +#define CONS_NONE 0 /* no console present */ +#define CONS_SRVC 1 /* console is service processor */ +#define CONS_DZ 2 /* console is dz/dl VT device */ +#define CONS_GRPH 3 /* cons is gfx dev w/ dz/dl keybd*/ +#define CONS_REM 4 /* cons is remote, protocal enet/MOP */ + +/* + * PALcode variants that we're interested in. + * Used as indices into the "palrev_avail" array in the per-cpu portion + * of the HWRPB. + */ +#define PALvar_reserved 0 +#define PALvar_OpenVMS 1 +#define PALvar_OSF1 2 + +/* + * The Alpha restart parameter block, which is a page or 2 in low memory + */ +struct rpb { + struct rpb *rpb_selfref; /* 000: physical self-reference */ + long rpb_string; /* 008: contains string "HWRPB" */ + long rpb_vers; /* 010: HWRPB version number */ + ulong rpb_size; /* 018: bytes in RPB perCPU CTB CRB MEMDSC */ + ulong rpb_cpuid; /* 020: primary cpu id */ + ulong rpb_pagesize; /* 028: page size in bytes */ + ulong rpb_addrbits; /* 030: number of phys addr bits */ + ulong rpb_maxasn; /* 038: max valid ASN */ + char rpb_ssn[16]; /* 040: system serial num: 10 ascii chars */ + ulong grpb_systype; /* 050: system type */ + long rpb_sysvar; /* 058: system variation */ + long rpb_sysrev; /* 060: system revision */ + ulong rpb_clock; /* 068: scaled interval clock intr freq */ + ulong rpb_counter; /* 070: cycle counter frequency */ + ulong rpb_vptb; /* 078: virtual page table base */ + long rpb_res1; /* 080: reserved */ + ulong rpb_trans_off; /* 088: offset to translation buffer hint */ + ulong rpb_numprocs; /* 090: number of processor slots */ + ulong rpb_slotsize; /* 098: per-cpu slot size */ + ulong rpb_percpu_off; /* 0A0: offset to per_cpu slots */ + ulong rpb_num_ctb; /* 0A8: number of CTBs */ + ulong rpb_ctb_size; /* 0B0: bytes in largest CTB */ + ulong rpb_ctb_off; /* 0B8: offset to CTB (cons term block) */ + ulong rpb_crb_off; /* 0C0: offset to CRB (cons routine block) */ + ulong rpb_mdt_off; /* 0C8: offset to memory descriptor table */ + ulong rpb_config_off; /* 0D0: offset to config data block */ + ulong rpb_fru_off; /* 0D8: offset to FRU table */ + void (*rpb_saveterm)(); /* 0E0: virt addr of save term routine */ + long rpb_saveterm_pv; /* 0E8: proc value for save term routine */ + void (*rpb_rstrterm)(); /* 0F0: virt addr of restore term routine */ + long rpb_rstrterm_pv; /* 0F8: proc value for restore term routine */ + void (*rpb_restart)(); /* 100: virt addr of CPU restart routine */ + long rpb_restart_pv; /* 108: proc value for CPU restart routine */ + long rpb_software; /* 110: used to determine presence of kdebug */ + long rpb_hardware; /* 118: reserved for hardware */ + long rpb_checksum; /* 120: checksum of prior entries in rpb */ + long rpb_rxrdy; /* 128: receive ready bitmask */ + long rpb_txrdy; /* 130: transmit ready bitmask */ + ulong rpb_dsr_off; /* 138: Dynamic System Recog. offset */ +}; + +#define rpb_kdebug rpb_software + +#define OSF_HWRPB_ADDR ((vm_offset_t)(-1L << 23)) + +/* + * This is the format for the boot/restart HWPCB. It must match the + * initial fields of the pcb structure as defined in pcb.h, but must + * additionally contain the appropriate amount of padding to line up + * with formats used by other palcode types. + */ +struct bootpcb { + long rpb_ksp; /* 000: kernel stack pointer */ + long rpb_usp; /* 008: user stack pointer */ + long rpb_ptbr; /* 010: page table base register */ + int rpb_cc; /* 018: cycle counter */ + int rpb_asn; /* 01C: address space number */ + long rpb_proc_uniq; /* 020: proc/thread unique value */ + long rpb_fen; /* 028: floating point enable */ + long rpb_palscr[2]; /* 030: pal scratch area */ + long rpb_pcbpad[8]; /* 040: padding for fixed size */ +}; + +/* + * Inter-Console Communications Buffer + * Used for the primary processor to communcate with the console + * of secondary processors. + */ +struct iccb { + uint iccb_rxlen; /* receive length in bytes */ + uint iccb_txlen; /* transmit length in bytes */ + char iccb_rxbuf[80]; /* receive buffer */ + char iccb_txbuf[80]; /* transmit buffer */ +}; + +/* + * The per-cpu portion of the Alpha HWRPB. + * Note that the main portion of the HWRPB is of variable size, + * hence this must be a separate structure. + * + */ +struct rpb_percpu { + struct bootpcb rpb_pcb; /* 000: boot/restart HWPCB */ + long rpb_state; /* 080: per-cpu state bits */ + long rpb_palmem; /* 088: palcode memory length */ + long rpb_palscratch; /* 090: palcode scratch length */ + long rpb_palmem_addr; /* 098: phys addr of palcode mem space */ + long rpb_palscratch_addr; /* 0A0: phys addr of palcode scratch space */ + long rpb_palrev; /* 0A8: PALcode rev required */ + long rpb_proctype; /* 0B0: processor type */ + long rpb_procvar; /* 0B8: processor variation */ + long rpb_procrev; /* 0C0: processor revision */ + char rpb_procsn[16]; /* 0C8: proc serial num: 10 ascii chars */ + long rpb_logout; /* 0D8: phys addr of logout area */ + long rpb_logout_len; /* 0E0: length in bytes of logout area */ + long rpb_haltpb; /* 0E8: halt pcb base */ + long rpb_haltpc; /* 0F0: halt pc */ + long rpb_haltps; /* 0F8: halt ps */ + long rpb_haltal; /* 100: halt arg list (R25) */ + long rpb_haltra; /* 108: halt return address (R26) */ + long rpb_haltpv; /* 110: halt procedure value (R27) */ + long rpb_haltcode; /* 118: reason for halt */ + long rpb_software; /* 120: for software */ + struct iccb rpb_iccb; /* 128: inter-console communications buffer */ + long rpb_palrev_avail[16]; /* 1D0: PALcode revs available */ + long rpb_pcrsvd[6]; /* 250: reserved for arch use */ +/* the dump stack grows from the end of the rpb page not to reach here */ +}; + +/* The firmware revision is in the (unused) first entry of palrevs available */ +#define rpb_firmrev rpb_palrev_avail[0] + +/* + * The memory cluster descriptor. + */ +struct rpb_cluster { + long rpb_pfn; /* 000: starting PFN of this cluster */ + long rpb_pfncount; /* 008: count of PFNs in this cluster */ + long rpb_pfntested; /* 010: count of tested PFNs in cluster */ + long rpb_va; /* 018: va of bitmap */ + long rpb_pa; /* 020: pa of bitmap */ + long rpb_checksum; /* 028: checksum of bitmap */ + long rpb_usage; /* 030: usage of cluster */ +}; +#define CLUSTER_USAGE_OS ((long)0) +#define CLUSTER_USAGE_PAL ((long)1) +#define CLUSTER_USAGE_NVRAM ((long)2) + +/* + * The "memory descriptor table" portion of the HWRPB. + * Note that the main portion of the HWRPB is of variable size and there is a + * variable number of per-cpu slots, hence this must be a separate structure. + * Also note that the memory descriptor table contains a fixed portion plus + * a variable number of "memory cluster descriptors" (one for each "cluster" + * of memory). + */ +struct rpb_mdt { + long rpb_checksum; /* 000: checksum of entire mem desc table */ + long rpb_impaddr; /* 008: PA of implementation dep info */ + long rpb_numcl; /* 010: number of clusters */ + struct rpb_cluster rpb_cluster[1]; /* first instance of a cluster */ +}; + +/* + * The "Console Terminal Block" portion of the HWRPB, for serial line + * UART console device. + */ +struct ctb_tt { + + long ctb_type; /* 0: always 4 */ + long ctb_unit; /* 8: */ + long ctb_reserved; /* 16: */ + long ctb_len; /* 24: bytes of info */ + long ctb_ipl; /* 32: console ipl level */ + long ctb_tintr_vec; /* 40: transmit vec (0x800) */ + long ctb_rintr_vec; /* 48: receive vec (0x800) */ +#define CTB_GRAPHICS 3 /* graphics device */ +#define CTB_NETWORK 0xC0 /* network device */ +#define CTB_PRINTERPORT 2 /* printer port on the SCC */ + long ctb_term_type; /* 56: terminal type */ + long ctb_keybd_type; /* 64: keyboard nationality */ + long ctb_keybd_trans; /* 72: trans. table addr */ + long ctb_keybd_map; /* 80: map table addr */ + long ctb_keybd_state; /* 88: keyboard flags */ + long ctb_keybd_last; /* 96: last key entered */ + long ctb_font_us; /* 104: US font table addr */ + long ctb_font_mcs; /* 112: MCS font table addr */ + long ctb_font_width; /* 120: font width, height */ + long ctb_font_height; /* 128: in pixels */ + long ctb_mon_width; /* 136: monitor width, height */ + long ctb_mon_height; /* 144: in pixels */ + long ctb_dpi; /* 152: monitor dots per inch */ + long ctb_planes; /* 160: # of planes */ + long ctb_cur_width; /* 168: cursor width, height */ + long ctb_cur_height; /* 176: in pixels */ + long ctb_head_cnt; /* 184: # of heads */ + long ctb_opwindow; /* 192: opwindow on screen */ + long ctb_head_offset; /* 200: offset to head info */ + long ctb_putchar; /* 208: output char to TURBO */ + long ctb_io_state; /* 216: I/O flags */ + long ctb_listen_state; /* 224: listener flags */ + long ctb_xaddr; /* 232: extended info addr */ + long ctb_turboslot; /* 248: TURBOchannel slot # */ + long ctb_server_off; /* 256: offset to server info */ + long ctb_line_off; /* 264: line parameter offset */ + char ctb_csd; /* 272: console specific data */ +}; + +/* + * The "Console Terminal Block" portion of the HWRPB. + */ +struct rpb_ctb { + long rpb_type; /* 000: console type */ + long rpb_unit; /* 008: console unit */ + long rpb_resv; /* 010: reserved */ + long rpb_length; /* 018: byte length of device dep portion */ + long rpb_first; /* 000: first field of device dep portion */ +}; + +/* + * The physical/virtual map for the console routine block. + */ +struct rpb_map { + long rpb_virt; /* virtual address for map entry */ + long rpb_phys; /* phys address for map entry */ + long rpb_pgcount; /* page count for map entry */ +}; + +/* + * The "Console Routine Block" portion of the HWRPB. + * Note: the "offsets" are all relative to the start of the HWRPB (HWRPB_ADDR). + */ +struct rpb_crb { + long rpb_va_disp; /* va of call-back dispatch rtn */ + long rpb_pa_disp; /* pa of call-back dispatch rtn */ + long rpb_va_fixup; /* va of call-back fixup rtn */ + long rpb_pa_fixup; /* pa of call-back fixup rtn */ + long rpb_num; /* number of entries in phys/virt map */ + long rpb_mapped_pages; /* Number of pages to be mapped */ + struct rpb_map rpb_map[1]; /* first instance of a map entry */ +}; + +/* + * These macros define where within the HWRPB the CTB and CRB are located. + */ +#define CTB_SETUP \ + ((struct rpb_ctb *) ((long)hwrpb_addr + (long)(hwrpb_addr->rpb_ctb_off))) + +#define CRB_SETUP \ + ((struct rpb_crb *) ((long)hwrpb_addr + (long)(hwrpb_addr->rpb_crb_off))) + +/* + * The "Dynamic System Recognition" portion of the HWRPB. + * It is used to obtain the platform specific data need to allow + * the platform define the platform name, the platform SMM and LURT + * data for software licensing + */ +struct rpb_dsr { + long rpb_smm; /* SMM nubber used by LMF */ + ulong rpb_lurt_off; /* offset to LURT table */ + ulong rpb_sysname_off; /* offset to sysname char count */ + int lurt[10]; /* XXM has one LURT entry */ +}; diff --git a/system/alpha/h/tlaser.h b/system/alpha/h/tlaser.h new file mode 100644 index 000000000..283d61be3 --- /dev/null +++ b/system/alpha/h/tlaser.h @@ -0,0 +1,34 @@ +/* + * Copyright (c) 1990 Hewlett-Packard Development Company + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#define tlsb_tlber 0x40 +#define tlsb_tldev 0x00 +#define tlsb_tlesr0 0x680 +#define tlsb_tlesr1 0x6C0 +#define tlsb_tlesr2 0x700 +#define tlsb_tlesr3 0x740 |