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-rw-r--r--tests/long/10.linux-boot/ref/arm/linux/realview-o3/config.ini24
-rwxr-xr-xtests/long/10.linux-boot/ref/arm/linux/realview-o3/simout12
-rw-r--r--tests/long/10.linux-boot/ref/arm/linux/realview-o3/stats.txt1067
-rw-r--r--tests/long/10.linux-boot/ref/arm/linux/realview-o3/system.terminalbin3941 -> 3941 bytes
4 files changed, 567 insertions, 536 deletions
diff --git a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/config.ini b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/config.ini
index 43cca93f6..4a2cdb533 100644
--- a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/config.ini
+++ b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/config.ini
@@ -15,7 +15,7 @@ boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 m
flags_addr=0
gic_cpu_addr=0
init_param=0
-kernel=/dist/m5/system/binaries/vmlinux.arm
+kernel=/arm/scratch/sysexplr/dist/binaries/vmlinux.arm
load_addr_mask=268435455
machine_type=RealView_PBX
mem_mode=timing
@@ -501,7 +501,7 @@ type=ExeTracer
[system.diskmem]
type=PhysicalMemory
-file=/dist/m5/system/disks/ael-arm.ext2
+file=/arm/scratch/sysexplr/dist/disks/ael-arm.ext2
latency=30000
latency_var=0
null=false
@@ -553,7 +553,7 @@ trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.iobus.port[25]
-mem_side=system.membus.port[6]
+mem_side=system.membus.port[7]
[system.l2c]
type=BaseCache
@@ -585,7 +585,7 @@ trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.toL2Bus.port[0]
-mem_side=system.membus.port[7]
+mem_side=system.membus.port[8]
[system.membus]
type=Bus
@@ -597,7 +597,7 @@ header_cycles=1
use_default_range=false
width=64
default=system.membus.badaddr_responder.pio
-port=system.bridge.side_b system.diskmem.port[0] system.physmem.port[0] system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.iocache.mem_side system.l2c.mem_side
+port=system.bridge.side_b system.diskmem.port[0] system.physmem.port[0] system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio system.iocache.mem_side system.l2c.mem_side
[system.membus.badaddr_responder]
type=IsaFake
@@ -628,7 +628,7 @@ port=system.membus.port[2]
[system.realview]
type=RealView
-children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake mmc_fake realview_io rtc_fake sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
+children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake realview_io rtc_fake sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake
intrctrl=system.intrctrl
system=system
@@ -836,6 +836,18 @@ update_data=false
warn_access=
pio=system.membus.port[4]
+[system.realview.local_cpu_timer]
+type=CpuLocalTimer
+clock=1000
+gic=system.realview.gic
+int_num_timer=29
+int_num_watchdog=30
+pio_addr=520095232
+pio_latency=1000
+platform=system.realview
+system=system
+pio=system.membus.port[6]
+
[system.realview.mmc_fake]
type=AmbaFake
amba_id=0
diff --git a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/simout b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/simout
index 707979289..3ff5b25a6 100755
--- a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/simout
+++ b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/simout
@@ -1,11 +1,13 @@
+Redirecting stdout to build/ARM_FS/tests/opt/long/10.linux-boot/arm/linux/realview-o3/simout
+Redirecting stderr to build/ARM_FS/tests/opt/long/10.linux-boot/arm/linux/realview-o3/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Aug 9 2011 03:11:31
-gem5 started Aug 9 2011 03:11:37
-gem5 executing on burrito
+gem5 compiled Aug 16 2011 18:25:06
+gem5 started Aug 16 2011 18:26:03
+gem5 executing on nadc-0270
command line: build/ARM_FS/gem5.opt -d build/ARM_FS/tests/opt/long/10.linux-boot/arm/linux/realview-o3 -re tests/run.py build/ARM_FS/tests/opt/long/10.linux-boot/arm/linux/realview-o3
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /dist/m5/system/binaries/vmlinux.arm
+info: kernel located at: /arm/scratch/sysexplr/dist/binaries/vmlinux.arm
info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 80748998500 because m5_exit instruction encountered
+Exiting @ tick 79671140500 because m5_exit instruction encountered
diff --git a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/stats.txt b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/stats.txt
index d56f088ea..149a25fba 100644
--- a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/stats.txt
+++ b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/stats.txt
@@ -1,97 +1,101 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 0.080749 # Number of seconds simulated
-sim_ticks 80748998500 # Number of ticks simulated
+sim_seconds 0.079671 # Number of seconds simulated
+sim_ticks 79671140500 # Number of ticks simulated
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 110010 # Simulator instruction rate (inst/s)
-host_tick_rate 171236576 # Simulator tick rate (ticks/s)
-host_mem_usage 368976 # Number of bytes of host memory used
-host_seconds 471.56 # Real time elapsed on the host
-sim_insts 51876948 # Number of instructions simulated
-system.l2c.replacements 94981 # number of replacements
-system.l2c.tagsinuse 38166.685860 # Cycle average of tags in use
-system.l2c.total_refs 1060946 # Total number of references to valid blocks.
-system.l2c.sampled_refs 127430 # Sample count of references to valid blocks.
-system.l2c.avg_refs 8.325716 # Average number of references to valid blocks.
+host_inst_rate 87754 # Simulator instruction rate (inst/s)
+host_tick_rate 134768287 # Simulator tick rate (ticks/s)
+host_mem_usage 390652 # Number of bytes of host memory used
+host_seconds 591.17 # Real time elapsed on the host
+sim_insts 51877383 # Number of instructions simulated
+system.l2c.replacements 94989 # number of replacements
+system.l2c.tagsinuse 38233.191793 # Cycle average of tags in use
+system.l2c.total_refs 1049232 # Total number of references to valid blocks.
+system.l2c.sampled_refs 127381 # Sample count of references to valid blocks.
+system.l2c.avg_refs 8.236958 # Average number of references to valid blocks.
system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::0 6723.855274 # Average occupied blocks per context
-system.l2c.occ_blocks::1 31442.830586 # Average occupied blocks per context
-system.l2c.occ_percent::0 0.102598 # Average percentage of cache occupancy
-system.l2c.occ_percent::1 0.479780 # Average percentage of cache occupancy
-system.l2c.ReadReq_hits::0 746399 # number of ReadReq hits
-system.l2c.ReadReq_hits::1 123135 # number of ReadReq hits
-system.l2c.ReadReq_hits::total 869534 # number of ReadReq hits
-system.l2c.Writeback_hits::0 435298 # number of Writeback hits
-system.l2c.Writeback_hits::total 435298 # number of Writeback hits
-system.l2c.UpgradeReq_hits::0 24 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total 24 # number of UpgradeReq hits
-system.l2c.ReadExReq_hits::0 60890 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total 60890 # number of ReadExReq hits
-system.l2c.demand_hits::0 807289 # number of demand (read+write) hits
-system.l2c.demand_hits::1 123135 # number of demand (read+write) hits
-system.l2c.demand_hits::total 930424 # number of demand (read+write) hits
-system.l2c.overall_hits::0 807289 # number of overall hits
-system.l2c.overall_hits::1 123135 # number of overall hits
-system.l2c.overall_hits::total 930424 # number of overall hits
-system.l2c.ReadReq_misses::0 21130 # number of ReadReq misses
-system.l2c.ReadReq_misses::1 101 # number of ReadReq misses
-system.l2c.ReadReq_misses::total 21231 # number of ReadReq misses
-system.l2c.UpgradeReq_misses::0 1677 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total 1677 # number of UpgradeReq misses
-system.l2c.ReadExReq_misses::0 107756 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total 107756 # number of ReadExReq misses
-system.l2c.demand_misses::0 128886 # number of demand (read+write) misses
-system.l2c.demand_misses::1 101 # number of demand (read+write) misses
-system.l2c.demand_misses::total 128987 # number of demand (read+write) misses
-system.l2c.overall_misses::0 128886 # number of overall misses
-system.l2c.overall_misses::1 101 # number of overall misses
-system.l2c.overall_misses::total 128987 # number of overall misses
-system.l2c.ReadReq_miss_latency 1109806000 # number of ReadReq miss cycles
-system.l2c.UpgradeReq_miss_latency 780500 # number of UpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency 5651942000 # number of ReadExReq miss cycles
-system.l2c.demand_miss_latency 6761748000 # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency 6761748000 # number of overall miss cycles
-system.l2c.ReadReq_accesses::0 767529 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::1 123236 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total 890765 # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::0 435298 # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total 435298 # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::0 1701 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total 1701 # number of UpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::0 168646 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total 168646 # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::0 936175 # number of demand (read+write) accesses
-system.l2c.demand_accesses::1 123236 # number of demand (read+write) accesses
-system.l2c.demand_accesses::total 1059411 # number of demand (read+write) accesses
-system.l2c.overall_accesses::0 936175 # number of overall (read+write) accesses
-system.l2c.overall_accesses::1 123236 # number of overall (read+write) accesses
-system.l2c.overall_accesses::total 1059411 # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::0 0.027530 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::1 0.000820 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total 0.028349 # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::0 0.985891 # miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::0 0.638948 # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::0 0.137673 # miss rate for demand accesses
-system.l2c.demand_miss_rate::1 0.000820 # miss rate for demand accesses
-system.l2c.demand_miss_rate::total 0.138493 # miss rate for demand accesses
-system.l2c.overall_miss_rate::0 0.137673 # miss rate for overall accesses
-system.l2c.overall_miss_rate::1 0.000820 # miss rate for overall accesses
-system.l2c.overall_miss_rate::total 0.138493 # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::0 52522.763843 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::1 10988178.217822 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 11040700.981665 # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::0 465.414431 # average UpgradeReq miss latency
+system.l2c.occ_blocks::0 6845.786735 # Average occupied blocks per context
+system.l2c.occ_blocks::1 31387.405058 # Average occupied blocks per context
+system.l2c.occ_percent::0 0.104458 # Average percentage of cache occupancy
+system.l2c.occ_percent::1 0.478934 # Average percentage of cache occupancy
+system.l2c.ReadReq_hits::0 745449 # number of ReadReq hits
+system.l2c.ReadReq_hits::1 96884 # number of ReadReq hits
+system.l2c.ReadReq_hits::total 842333 # number of ReadReq hits
+system.l2c.Writeback_hits::0 434303 # number of Writeback hits
+system.l2c.Writeback_hits::total 434303 # number of Writeback hits
+system.l2c.UpgradeReq_hits::0 53 # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total 53 # number of UpgradeReq hits
+system.l2c.SCUpgradeReq_hits::0 11 # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::total 11 # number of SCUpgradeReq hits
+system.l2c.ReadExReq_hits::0 61363 # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total 61363 # number of ReadExReq hits
+system.l2c.demand_hits::0 806812 # number of demand (read+write) hits
+system.l2c.demand_hits::1 96884 # number of demand (read+write) hits
+system.l2c.demand_hits::total 903696 # number of demand (read+write) hits
+system.l2c.overall_hits::0 806812 # number of overall hits
+system.l2c.overall_hits::1 96884 # number of overall hits
+system.l2c.overall_hits::total 903696 # number of overall hits
+system.l2c.ReadReq_misses::0 21092 # number of ReadReq misses
+system.l2c.ReadReq_misses::1 91 # number of ReadReq misses
+system.l2c.ReadReq_misses::total 21183 # number of ReadReq misses
+system.l2c.UpgradeReq_misses::0 1724 # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total 1724 # number of UpgradeReq misses
+system.l2c.ReadExReq_misses::0 107716 # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total 107716 # number of ReadExReq misses
+system.l2c.demand_misses::0 128808 # number of demand (read+write) misses
+system.l2c.demand_misses::1 91 # number of demand (read+write) misses
+system.l2c.demand_misses::total 128899 # number of demand (read+write) misses
+system.l2c.overall_misses::0 128808 # number of overall misses
+system.l2c.overall_misses::1 91 # number of overall misses
+system.l2c.overall_misses::total 128899 # number of overall misses
+system.l2c.ReadReq_miss_latency 1106899000 # number of ReadReq miss cycles
+system.l2c.UpgradeReq_miss_latency 676000 # number of UpgradeReq miss cycles
+system.l2c.ReadExReq_miss_latency 5649720000 # number of ReadExReq miss cycles
+system.l2c.demand_miss_latency 6756619000 # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency 6756619000 # number of overall miss cycles
+system.l2c.ReadReq_accesses::0 766541 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::1 96975 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total 863516 # number of ReadReq accesses(hits+misses)
+system.l2c.Writeback_accesses::0 434303 # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total 434303 # number of Writeback accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::0 1777 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total 1777 # number of UpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::0 11 # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::total 11 # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::0 169079 # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total 169079 # number of ReadExReq accesses(hits+misses)
+system.l2c.demand_accesses::0 935620 # number of demand (read+write) accesses
+system.l2c.demand_accesses::1 96975 # number of demand (read+write) accesses
+system.l2c.demand_accesses::total 1032595 # number of demand (read+write) accesses
+system.l2c.overall_accesses::0 935620 # number of overall (read+write) accesses
+system.l2c.overall_accesses::1 96975 # number of overall (read+write) accesses
+system.l2c.overall_accesses::total 1032595 # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::0 0.027516 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::1 0.000938 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total 0.028454 # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::0 0.970174 # miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::0 0.637075 # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::0 0.137671 # miss rate for demand accesses
+system.l2c.demand_miss_rate::1 0.000938 # miss rate for demand accesses
+system.l2c.demand_miss_rate::total 0.138610 # miss rate for demand accesses
+system.l2c.overall_miss_rate::0 0.137671 # miss rate for overall accesses
+system.l2c.overall_miss_rate::1 0.000938 # miss rate for overall accesses
+system.l2c.overall_miss_rate::total 0.138610 # miss rate for overall accesses
+system.l2c.ReadReq_avg_miss_latency::0 52479.565712 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::1 12163725.274725 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::total 12216204.840437 # average ReadReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::0 392.111369 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::1 inf # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::0 52451.297376 # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::0 52450.146682 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::1 inf # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency
-system.l2c.demand_avg_miss_latency::0 52463.013826 # average overall miss latency
-system.l2c.demand_avg_miss_latency::1 66948000 # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 67000463.013826 # average overall miss latency
-system.l2c.overall_avg_miss_latency::0 52463.013826 # average overall miss latency
-system.l2c.overall_avg_miss_latency::1 66948000 # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 67000463.013826 # average overall miss latency
+system.l2c.demand_avg_miss_latency::0 52454.963977 # average overall miss latency
+system.l2c.demand_avg_miss_latency::1 74248560.439560 # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 74301015.403538 # average overall miss latency
+system.l2c.overall_avg_miss_latency::0 52454.963977 # average overall miss latency
+system.l2c.overall_avg_miss_latency::1 74248560.439560 # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 74301015.403538 # average overall miss latency
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -100,44 +104,44 @@ system.l2c.avg_blocked_cycles::no_mshrs no_value # av
system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
-system.l2c.writebacks 87796 # number of writebacks
-system.l2c.ReadReq_mshr_hits 58 # number of ReadReq MSHR hits
-system.l2c.demand_mshr_hits 58 # number of demand (read+write) MSHR hits
-system.l2c.overall_mshr_hits 58 # number of overall MSHR hits
-system.l2c.ReadReq_mshr_misses 21173 # number of ReadReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses 1677 # number of UpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses 107756 # number of ReadExReq MSHR misses
-system.l2c.demand_mshr_misses 128929 # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses 128929 # number of overall MSHR misses
+system.l2c.writebacks 87788 # number of writebacks
+system.l2c.ReadReq_mshr_hits 54 # number of ReadReq MSHR hits
+system.l2c.demand_mshr_hits 54 # number of demand (read+write) MSHR hits
+system.l2c.overall_mshr_hits 54 # number of overall MSHR hits
+system.l2c.ReadReq_mshr_misses 21129 # number of ReadReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses 1724 # number of UpgradeReq MSHR misses
+system.l2c.ReadExReq_mshr_misses 107716 # number of ReadExReq MSHR misses
+system.l2c.demand_mshr_misses 128845 # number of demand (read+write) MSHR misses
+system.l2c.overall_mshr_misses 128845 # number of overall MSHR misses
system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.l2c.ReadReq_mshr_miss_latency 848032500 # number of ReadReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency 67081500 # number of UpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency 4311568500 # number of ReadExReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency 5159601000 # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency 5159601000 # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency 28946618000 # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency 748818447 # number of WriteReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency 29695436447 # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::0 0.027586 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::1 0.171809 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total 0.199394 # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::0 0.985891 # mshr miss rate for UpgradeReq accesses
+system.l2c.ReadReq_mshr_miss_latency 846282000 # number of ReadReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency 68961500 # number of UpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency 4309813000 # number of ReadExReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency 5156095000 # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency 5156095000 # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency 28946860000 # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency 748497446 # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency 29695357446 # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::0 0.027564 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::1 0.217881 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total 0.245445 # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::0 0.970174 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::0 0.638948 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::0 0.637075 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::1 inf # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::0 0.137719 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::1 1.046196 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total 1.183915 # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::0 0.137719 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::1 1.046196 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total 1.183915 # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency 40052.543333 # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency 40000.894454 # average UpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency 40012.328780 # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency 40018.932901 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency 40018.932901 # average overall mshr miss latency
+system.l2c.demand_mshr_miss_rate::0 0.137711 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::1 1.328641 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total 1.466352 # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::0 0.137711 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::1 1.328641 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total 1.466352 # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency 40053.102371 # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency 40000.870070 # average UpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency 40010.889747 # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency 40017.812100 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency 40017.812100 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
@@ -146,27 +150,27 @@ system.l2c.soft_prefetch_mshr_full 0 # nu
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.read_hits 28177040 # DTB read hits
-system.cpu.dtb.read_misses 72386 # DTB read misses
-system.cpu.dtb.write_hits 7691310 # DTB write hits
-system.cpu.dtb.write_misses 13556 # DTB write misses
+system.cpu.dtb.read_hits 13454003 # DTB read hits
+system.cpu.dtb.read_misses 56352 # DTB read misses
+system.cpu.dtb.write_hits 7087382 # DTB write hits
+system.cpu.dtb.write_misses 9992 # DTB write misses
system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 33678 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 40 # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries 2922 # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults 4054 # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults 1092 # Number of TLB faults due to prefetch
+system.cpu.dtb.flush_entries 2710 # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults 2485 # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults 947 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults 940 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses 28249426 # DTB read accesses
-system.cpu.dtb.write_accesses 7704866 # DTB write accesses
+system.cpu.dtb.perms_faults 572 # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses 13510355 # DTB read accesses
+system.cpu.dtb.write_accesses 7097374 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu.dtb.hits 35868350 # DTB hits
-system.cpu.dtb.misses 85942 # DTB misses
-system.cpu.dtb.accesses 35954292 # DTB accesses
-system.cpu.itb.inst_hits 7355634 # ITB inst hits
-system.cpu.itb.inst_misses 7654 # ITB inst misses
+system.cpu.dtb.hits 20541385 # DTB hits
+system.cpu.dtb.misses 66344 # DTB misses
+system.cpu.dtb.accesses 20607729 # DTB accesses
+system.cpu.itb.inst_hits 6364119 # ITB inst hits
+system.cpu.itb.inst_misses 7846 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
@@ -175,502 +179,515 @@ system.cpu.itb.flush_tlb 2 # Nu
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 33678 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 40 # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries 1641 # Number of entries that have been flushed from TLB
+system.cpu.itb.flush_entries 1638 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults 4616 # Number of TLB faults due to permissions restrictions
+system.cpu.itb.perms_faults 4337 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.inst_accesses 7363288 # ITB inst accesses
-system.cpu.itb.hits 7355634 # DTB hits
-system.cpu.itb.misses 7654 # DTB misses
-system.cpu.itb.accesses 7363288 # DTB accesses
-system.cpu.numCycles 161497998 # number of cpu cycles simulated
+system.cpu.itb.inst_accesses 6371965 # ITB inst accesses
+system.cpu.itb.hits 6364119 # DTB hits
+system.cpu.itb.misses 7846 # DTB misses
+system.cpu.itb.accesses 6371965 # DTB accesses
+system.cpu.numCycles 159342282 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 13590326 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 11456360 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 648707 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 12127952 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 9362916 # Number of BTB hits
+system.cpu.BPredUnit.lookups 12557399 # Number of BP lookups
+system.cpu.BPredUnit.condPredicted 10608534 # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect 646709 # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups 11154990 # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits 8780554 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 895596 # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect 148738 # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles 16866017 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 67484906 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 13590326 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 10258512 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 17034266 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 4123173 # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles 93207 # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.BlockedCycles 55393473 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 18245 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 90602 # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles 223 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 7350509 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 337942 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes 4453 # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples 92525962 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 0.899758 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.157294 # Number of instructions fetched each cycle (Total)
+system.cpu.BPredUnit.usedRAS 870083 # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect 147860 # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles 16065730 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 58984795 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 12557399 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 9650637 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 15473829 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 2924896 # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles 92331 # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.BlockedCycles 54317634 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 13079 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 97476 # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles 352 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 6359256 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 271099 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes 4481 # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples 88159945 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 0.843576 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.082771 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 75510639 81.61% 81.61% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 1420262 1.53% 83.15% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 1864587 2.02% 85.16% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 1402898 1.52% 86.68% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 4892259 5.29% 91.96% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 936046 1.01% 92.98% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 818442 0.88% 93.86% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 713663 0.77% 94.63% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 4967166 5.37% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 72705101 82.47% 82.47% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 1269251 1.44% 83.91% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 1767868 2.01% 85.91% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 1323104 1.50% 87.42% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 4670929 5.30% 92.71% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 784846 0.89% 93.60% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 764674 0.87% 94.47% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 594095 0.67% 95.15% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 4280077 4.85% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 92525962 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.084152 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.417868 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 18966191 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 54065669 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 15364429 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 1171991 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 2957682 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 1326698 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 73964 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 80385244 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 241077 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 2957682 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 20606631 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 33478689 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 16542065 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 13879452 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 5061443 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 77021348 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 458130 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 143873 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 2652425 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents 147 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 79088993 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 335825078 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 335758422 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 66656 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 51887194 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 27201798 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 847863 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 665654 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 14013888 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 13554810 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 9178167 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 336 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 727 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 69117949 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 4041398 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 82091279 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 240337 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 20597655 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 41996969 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 1078579 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 92525962 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 0.887224 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.470662 # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total 88159945 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.078808 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.370177 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 18165141 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 52904570 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 13778388 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 1284946 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 2026900 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 1217125 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 74219 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 71956332 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 242640 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 2026900 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 19696589 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 30046666 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 18688452 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 12532114 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 5169224 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 69519785 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 458017 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 271395 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 2649588 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents 136 # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands 71288380 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 300070248 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 300002932 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 67316 # Number of floating rename lookups
+system.cpu.rename.CommittedMaps 51888569 # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps 19399810 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 812076 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 663924 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 14280198 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 12080470 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 8183550 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 3516652 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 4162890 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 62699092 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 4040128 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 64163344 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 176578 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 14335802 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 27947195 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 1077859 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 88159945 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 0.727806 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.267218 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 58116859 62.81% 62.81% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 14058568 15.19% 78.01% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 6650411 7.19% 85.19% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 4537690 4.90% 90.10% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 6374184 6.89% 96.99% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 1626800 1.76% 98.74% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 758213 0.82% 99.56% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 287091 0.31% 99.87% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 116146 0.13% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 57192817 64.87% 64.87% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 14605860 16.57% 81.44% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 7161098 8.12% 89.56% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 4501948 5.11% 94.67% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 2827013 3.21% 97.88% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 1117751 1.27% 99.15% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 514797 0.58% 99.73% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 165433 0.19% 99.92% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 73228 0.08% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 92525962 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 88159945 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 27856 0.57% 0.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 1 0.00% 0.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 0.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 0.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 0.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 0.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 4535089 92.61% 93.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 334124 6.82% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 31666 2.83% 2.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 2 0.00% 2.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 2.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 2.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 2.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 2.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.83% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 952275 85.11% 87.94% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 134939 12.06% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass 2393223 2.92% 2.92% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 42162127 51.36% 54.28% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 71788 0.09% 54.36% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 54.36% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 54.36% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 54.36% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 54.36% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 54.36% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 54.36% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 54.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 54.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 54.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 54.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 54.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 54.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 14 0.00% 54.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 54.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 54.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 54.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 13 0.00% 54.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 54.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 54.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 54.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 54.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 54.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 54.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 883 0.00% 54.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 54.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 13 0.00% 54.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 54.36% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 29248881 35.63% 89.99% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 8214337 10.01% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass 2393223 3.73% 3.73% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 39946954 62.26% 65.99% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 68785 0.11% 66.10% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.10% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 66.10% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.10% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.10% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.10% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.10% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.10% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.10% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.10% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 1 0.00% 66.10% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.10% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.10% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 5 0.00% 66.10% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.10% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.10% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.10% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.10% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.10% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.10% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.10% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.10% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.10% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.10% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 883 0.00% 66.10% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.10% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.10% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.10% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 14271744 22.24% 88.34% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 7481749 11.66% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 82091279 # Type of FU issued
-system.cpu.iq.rate 0.508311 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 4897070 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.059654 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 261914662 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 94097771 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 62682872 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 16678 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 9625 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 6496 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 84586375 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 8751 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 425783 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 64163344 # Type of FU issued
+system.cpu.iq.rate 0.402676 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 1118882 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.017438 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 217833874 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 81127166 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 59171315 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 14043 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 9868 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 6386 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 62881739 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 7264 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 405736 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 4375336 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 13490 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 405193 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 2100755 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 2901377 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 4794 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 62495 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 1106451 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 17024856 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 9533 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 3460272 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 8665 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 2957682 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 21379595 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 254604 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 73328942 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 354348 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 13554810 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 9178167 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 4009809 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 13226 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 41705 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 405193 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 534373 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 174123 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 708496 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 80713996 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 28682342 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 1377283 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 2026900 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 18611531 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 438534 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 66914101 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 333018 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 12080470 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 8183550 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 4008088 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 19000 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 218050 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 62495 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 538548 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 174972 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 713520 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 63251439 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 13958320 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 911905 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 169595 # number of nop insts executed
-system.cpu.iew.exec_refs 36687563 # number of memory reference insts executed
-system.cpu.iew.exec_branches 10549834 # Number of branches executed
-system.cpu.iew.exec_stores 8005221 # Number of stores executed
-system.cpu.iew.exec_rate 0.499783 # Inst execution rate
-system.cpu.iew.wb_sent 80082379 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 62689368 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 33196620 # num instructions producing a value
-system.cpu.iew.wb_consumers 59589146 # num instructions consuming a value
+system.cpu.iew.exec_nop 174881 # number of nop insts executed
+system.cpu.iew.exec_refs 21351791 # number of memory reference insts executed
+system.cpu.iew.exec_branches 10154168 # Number of branches executed
+system.cpu.iew.exec_stores 7393471 # Number of stores executed
+system.cpu.iew.exec_rate 0.396953 # Inst execution rate
+system.cpu.iew.wb_sent 62861793 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 59177701 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 31313815 # num instructions producing a value
+system.cpu.iew.wb_consumers 56258797 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 0.388174 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.557092 # average fanout of values written-back
+system.cpu.iew.wb_rate 0.371387 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.556603 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitCommittedInsts 52000178 # The number of committed instructions
-system.cpu.commit.commitSquashedInsts 19092846 # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls 2962819 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 623054 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 89568308 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 0.580564 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.463287 # Number of insts commited each cycle
+system.cpu.commit.commitCommittedInsts 52000613 # The number of committed instructions
+system.cpu.commit.commitSquashedInsts 12648879 # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls 2962269 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts 619998 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 86133073 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 0.603724 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 1.472813 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 69902534 78.04% 78.04% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 9240090 10.32% 88.36% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 2668754 2.98% 91.34% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 1387483 1.55% 92.89% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 3444879 3.85% 96.73% # Number of insts commited each cycle
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system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
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-system.cpu.cpi_total 3.113098 # CPI: Total CPI of All Threads
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system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses
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system.cpu.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
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system.cpu.icache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
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-system.cpu.dcache.StoreCondReq_accesses::total 104941 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::0 16459430 # number of demand (read+write) accesses
+system.cpu.dcache.overall_misses::total 2525353 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency 7135135000 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency 80554552279 # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency 99000500 # number of LoadLockedReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency 159000 # number of StoreCondReq miss cycles
+system.cpu.dcache.demand_miss_latency 87689687279 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency 87689687279 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::0 8661257 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 8661257 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::0 6663047 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 6663047 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::0 109917 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total 109917 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::0 104410 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total 104410 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::0 15324304 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 16459430 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::0 16459430 # number of overall (read+write) accesses
+system.cpu.dcache.demand_accesses::total 15324304 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::0 15324304 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 16459430 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::0 0.054447 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::0 0.306842 # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::0 0.060123 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::0 0.156619 # miss rate for demand accesses
+system.cpu.dcache.overall_accesses::total 15324304 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::0 0.055763 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::0 0.306523 # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::0 0.059554 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_miss_rate::0 0.000105 # miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_miss_rate::0 0.164794 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::0 0.156619 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::0 0.164794 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::0 14716.407039 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::0 14773.270307 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::0 39931.073652 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::0 39441.568466 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 14978.814837 # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 15123.816071 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::0 34713.816713 # average overall miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::0 14454.545455 # average StoreCondReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::0 34723.734575 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::1 inf # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total inf # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::0 34713.816713 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::0 34723.734575 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::1 inf # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total inf # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 9881489 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 841000 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 1354 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 29 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 7297.997784 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 29000 # average number of cycles each access was blocked
+system.cpu.dcache.blocked_cycles::no_mshrs 7890493 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 750500 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 1025 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 25 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 7698.041951 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 30020 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks 392324 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits 282537 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits 1874151 # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits 1046 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits 2156688 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits 2156688 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses 250856 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses 170310 # number of WriteReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses 5586 # number of LoadLockedReq MSHR misses
-system.cpu.dcache.demand_mshr_misses 421166 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses 421166 # number of overall MSHR misses
+system.cpu.dcache.writebacks 390970 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits 234674 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits 1871578 # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits 927 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits 2106252 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits 2106252 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses 248302 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses 170799 # number of WriteReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses 5619 # number of LoadLockedReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses 11 # number of StoreCondReq MSHR misses
+system.cpu.dcache.demand_mshr_misses 419101 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses 419101 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 3355794000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency 6558107489 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency 66303500 # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency 9913901489 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency 9913901489 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency 38199628000 # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency 946945664 # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency 39146573664 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.025607 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_latency 3306153500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency 6559898993 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency 66534000 # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency 121000 # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency 9866052493 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency 9866052493 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency 38199897500 # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency 945697168 # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency 39145594668 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.028668 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.025561 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.025634 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.050640 # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.051120 # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::0 0.025588 # mshr miss rate for demand accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::0 0.000105 # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::0 0.027349 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::0 0.025588 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::0 0.027349 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13377.371879 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 38506.884440 # average WriteReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11869.584676 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 23539.178113 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 23539.178113 # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13315.049818 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 38407.127635 # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11840.896957 # average LoadLockedReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency 11000 # average StoreCondReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 23540.990103 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 23540.990103 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
diff --git a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/system.terminal b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/system.terminal
index 334b73543..97c12ec46 100644
--- a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/system.terminal
+++ b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/system.terminal
Binary files differ