diff options
Diffstat (limited to 'tests/long/40.perlbmk/ref/arm/linux/simple-timing/stats.txt')
-rw-r--r-- | tests/long/40.perlbmk/ref/arm/linux/simple-timing/stats.txt | 194 |
1 files changed, 99 insertions, 95 deletions
diff --git a/tests/long/40.perlbmk/ref/arm/linux/simple-timing/stats.txt b/tests/long/40.perlbmk/ref/arm/linux/simple-timing/stats.txt index 1e3225702..ae9492554 100644 --- a/tests/long/40.perlbmk/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/40.perlbmk/ref/arm/linux/simple-timing/stats.txt @@ -1,27 +1,31 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 494422 # Simulator instruction rate (inst/s) -host_mem_usage 242392 # Number of bytes of host memory used -host_seconds 3706.70 # Real time elapsed on the host -host_tick_rate 639353926 # Simulator tick rate (ticks/s) +host_inst_rate 678497 # Simulator instruction rate (inst/s) +host_mem_usage 259312 # Number of bytes of host memory used +host_seconds 2762.35 # Real time elapsed on the host +host_tick_rate 857930242 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 1832675505 # Number of instructions simulated -sim_seconds 2.369896 # Number of seconds simulated -sim_ticks 2369896178000 # Number of ticks simulated -system.cpu.dcache.ReadReq_accesses 620364065 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 54567.414542 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 51567.414542 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 618902904 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 79731778000 # number of ReadReq miss cycles +sim_insts 1874244950 # Number of instructions simulated +sim_seconds 2.369902 # Number of seconds simulated +sim_ticks 2369901960000 # Number of ticks simulated +system.cpu.dcache.LoadLockedReq_accesses 9985 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_hits 9985 # number of LoadLockedReq hits +system.cpu.dcache.ReadReq_accesses 620335414 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 54574.204602 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 51574.204602 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 618874541 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 79725982000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.002355 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 1461161 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 75348295000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_misses 1460873 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_miss_latency 75343363000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.002355 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 1461161 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 276945663 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.ReadReq_mshr_misses 1460873 # number of ReadReq MSHR misses +system.cpu.dcache.StoreCondReq_accesses 9985 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_hits 9985 # number of StoreCondReq hits +system.cpu.dcache.WriteReq_accesses 276935678 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_avg_miss_latency 52141.055235 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency 49141.055235 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 276872883 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits 276862898 # number of WriteReq hits system.cpu.dcache.WriteReq_miss_latency 3794826000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.000263 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 72780 # number of WriteReq misses @@ -30,48 +34,48 @@ system.cpu.dcache.WriteReq_mshr_miss_rate 0.000263 # m system.cpu.dcache.WriteReq_mshr_misses 72780 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 583.970170 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 584.067849 # Average number of references to valid blocks. system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 897309728 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 54452.292494 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 51452.292494 # average overall mshr miss latency -system.cpu.dcache.demand_hits 895775787 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 83526604000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_accesses 897271092 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 54458.738711 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 51458.738711 # average overall mshr miss latency +system.cpu.dcache.demand_hits 895737439 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 83520808000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.001709 # miss rate for demand accesses -system.cpu.dcache.demand_misses 1533941 # number of demand (read+write) misses +system.cpu.dcache.demand_misses 1533653 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 78924781000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 78919849000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.001709 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 1533941 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses 1533653 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.999748 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 4094.966269 # Average occupied blocks per context -system.cpu.dcache.overall_accesses 897309728 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 54452.292494 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 51452.292494 # average overall mshr miss latency +system.cpu.dcache.occ_%::0 0.999746 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 4094.960333 # Average occupied blocks per context +system.cpu.dcache.overall_accesses 897271092 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 54458.738711 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 51458.738711 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 895775787 # number of overall hits -system.cpu.dcache.overall_miss_latency 83526604000 # number of overall miss cycles +system.cpu.dcache.overall_hits 895737439 # number of overall hits +system.cpu.dcache.overall_miss_latency 83520808000 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.001709 # miss rate for overall accesses -system.cpu.dcache.overall_misses 1533941 # number of overall misses +system.cpu.dcache.overall_misses 1533653 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 78924781000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 78919849000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.001709 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 1533941 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses 1533653 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 1529845 # number of replacements -system.cpu.dcache.sampled_refs 1533941 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 1529557 # number of replacements +system.cpu.dcache.sampled_refs 1533653 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4094.966269 # Cycle average of tags in use -system.cpu.dcache.total_refs 895775787 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 993944000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tagsinuse 4094.960333 # Cycle average of tags in use +system.cpu.dcache.total_refs 895757409 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 997882000 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 107259 # number of writebacks system.cpu.dtb.accesses 0 # DTB accesses system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions @@ -94,10 +98,10 @@ system.cpu.dtb.read_misses 0 # DT system.cpu.dtb.write_accesses 0 # DTB write accesses system.cpu.dtb.write_hits 0 # DTB write hits system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.icache.ReadReq_accesses 1390241555 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses 1390271511 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_avg_miss_latency 18786.850477 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 15786.850477 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 1390221752 # number of ReadReq hits +system.cpu.icache.ReadReq_hits 1390251708 # number of ReadReq hits system.cpu.icache.ReadReq_miss_latency 372036000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000014 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 19803 # number of ReadReq misses @@ -106,16 +110,16 @@ system.cpu.icache.ReadReq_mshr_miss_rate 0.000014 # ms system.cpu.icache.ReadReq_mshr_misses 19803 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 70202.583043 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 70204.095743 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 1390241555 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses 1390271511 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency 18786.850477 # average overall miss latency system.cpu.icache.demand_avg_mshr_miss_latency 15786.850477 # average overall mshr miss latency -system.cpu.icache.demand_hits 1390221752 # number of demand (read+write) hits +system.cpu.icache.demand_hits 1390251708 # number of demand (read+write) hits system.cpu.icache.demand_miss_latency 372036000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000014 # miss rate for demand accesses system.cpu.icache.demand_misses 19803 # number of demand (read+write) misses @@ -127,12 +131,12 @@ system.cpu.icache.fast_writes 0 # nu system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.occ_%::0 0.679846 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 1392.325384 # Average occupied blocks per context -system.cpu.icache.overall_accesses 1390241555 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::0 1392.324437 # Average occupied blocks per context +system.cpu.icache.overall_accesses 1390271511 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency 18786.850477 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 15786.850477 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 1390221752 # number of overall hits +system.cpu.icache.overall_hits 1390251708 # number of overall hits system.cpu.icache.overall_miss_latency 372036000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000014 # miss rate for overall accesses system.cpu.icache.overall_misses 19803 # number of overall misses @@ -145,8 +149,8 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0 system.cpu.icache.replacements 18364 # number of replacements system.cpu.icache.sampled_refs 19803 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1392.325384 # Cycle average of tags in use -system.cpu.icache.total_refs 1390221752 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1392.324437 # Cycle average of tags in use +system.cpu.icache.total_refs 1390251708 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles @@ -181,84 +185,84 @@ system.cpu.l2cache.ReadExReq_misses 66093 # nu system.cpu.l2cache.ReadExReq_mshr_miss_latency 2643720000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.908120 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 66093 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 1480964 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses 1480676 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 67385 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 73506108000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.954499 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 1413579 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 56543160000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.954499 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 1413579 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_hits 67139 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 73503924000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.954657 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 1413537 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 56541480000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.954657 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 1413537 # number of ReadReq MSHR misses system.cpu.l2cache.Writeback_accesses 107259 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_hits 107259 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.050081 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.049920 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 1553744 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses 1553456 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 74072 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 76942944000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.952327 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 1479672 # number of demand (read+write) misses +system.cpu.l2cache.demand_hits 73826 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 76940760000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.952476 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 1479630 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 59186880000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.952327 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 1479672 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 59185200000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.952476 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 1479630 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.881760 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.092816 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 28893.501877 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 3041.393075 # Average occupied blocks per context -system.cpu.l2cache.overall_accesses 1553744 # number of overall (read+write) accesses +system.cpu.l2cache.occ_%::0 0.881757 # Average percentage of cache occupancy +system.cpu.l2cache.occ_%::1 0.092817 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 28893.420796 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 3041.423322 # Average occupied blocks per context +system.cpu.l2cache.overall_accesses 1553456 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 74072 # number of overall hits -system.cpu.l2cache.overall_miss_latency 76942944000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.952327 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 1479672 # number of overall misses +system.cpu.l2cache.overall_hits 73826 # number of overall hits +system.cpu.l2cache.overall_miss_latency 76940760000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.952476 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 1479630 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 59186880000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.952327 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 1479672 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 59185200000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.952476 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 1479630 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.replacements 1478797 # number of replacements -system.cpu.l2cache.sampled_refs 1511517 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 1478755 # number of replacements +system.cpu.l2cache.sampled_refs 1511475 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 31934.894953 # Cycle average of tags in use -system.cpu.l2cache.total_refs 75699 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 31934.844118 # Cycle average of tags in use +system.cpu.l2cache.total_refs 75453 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 66099 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 4739792356 # number of cpu cycles simulated +system.cpu.numCycles 4739803920 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.num_busy_cycles 4739792356 # Number of busy cycles -system.cpu.num_conditional_control_insts 0 # number of instructions that are conditional controls +system.cpu.num_busy_cycles 4739803920 # Number of busy cycles +system.cpu.num_conditional_control_insts 223597262 # number of instructions that are conditional controls system.cpu.num_fp_alu_accesses 52289415 # Number of float alu accesses system.cpu.num_fp_insts 52289415 # number of float instructions system.cpu.num_fp_register_reads 60540850 # number of times the floating registers were read system.cpu.num_fp_register_writes 46777010 # number of times the floating registers were written -system.cpu.num_func_calls 0 # number of times a function call or return occured +system.cpu.num_func_calls 84508263 # number of times a function call or return occured system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_insts 1832675505 # Number of instructions executed -system.cpu.num_int_alu_accesses 1619025871 # Number of integer alu accesses -system.cpu.num_int_insts 1619025871 # number of integer instructions -system.cpu.num_int_register_reads 5455211671 # number of times the integer registers were read -system.cpu.num_int_register_writes 1365288731 # number of times the integer registers were written -system.cpu.num_load_insts 631405848 # Number of load instructions -system.cpu.num_mem_refs 908401146 # number of memory refs +system.cpu.num_insts 1874244950 # Number of instructions executed +system.cpu.num_int_alu_accesses 1660575345 # Number of integer alu accesses +system.cpu.num_int_insts 1660575345 # number of integer instructions +system.cpu.num_int_register_reads 5538311924 # number of times the integer registers were read +system.cpu.num_int_register_writes 1405482554 # number of times the integer registers were written +system.cpu.num_load_insts 631387182 # Number of load instructions +system.cpu.num_mem_refs 908382480 # number of memory refs system.cpu.num_store_insts 276995298 # Number of store instructions system.cpu.workload.PROG:num_syscalls 1411 # Number of system calls |