diff options
Diffstat (limited to 'tests/long/70.twolf/ref/x86')
| -rw-r--r-- | tests/long/70.twolf/ref/x86/linux/o3-timing/config.ini | 5 | ||||
| -rwxr-xr-x | tests/long/70.twolf/ref/x86/linux/o3-timing/simout | 14 | ||||
| -rw-r--r-- | tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt | 713 |
3 files changed, 368 insertions, 364 deletions
diff --git a/tests/long/70.twolf/ref/x86/linux/o3-timing/config.ini b/tests/long/70.twolf/ref/x86/linux/o3-timing/config.ini index 15faea73a..733a1cda5 100644 --- a/tests/long/70.twolf/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/70.twolf/ref/x86/linux/o3-timing/config.ini @@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem mem_mode=atomic +memories=system.physmem physmem=system.physmem work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -493,12 +494,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=twolf smred -cwd=build/X86_SE/tests/fast/long/70.twolf/x86/linux/o3-timing +cwd=build/X86_SE/tests/opt/long/70.twolf/x86/linux/o3-timing egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/x86/linux/twolf +executable=/chips/pd/randd/dist/cpu2000/binaries/x86/linux/twolf gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/70.twolf/ref/x86/linux/o3-timing/simout b/tests/long/70.twolf/ref/x86/linux/o3-timing/simout index 46cb2af0c..13ca71321 100755 --- a/tests/long/70.twolf/ref/x86/linux/o3-timing/simout +++ b/tests/long/70.twolf/ref/x86/linux/o3-timing/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 27 2011 02:06:34 -gem5 started Jun 27 2011 02:06:35 -gem5 executing on burrito -command line: build/X86_SE/gem5.fast -d build/X86_SE/tests/fast/long/70.twolf/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/fast/long/70.twolf/x86/linux/o3-timing -Couldn't unlink build/X86_SE/tests/fast/long/70.twolf/x86/linux/o3-timing/smred.sav -Couldn't unlink build/X86_SE/tests/fast/long/70.twolf/x86/linux/o3-timing/smred.sv2 +gem5 compiled Jul 8 2011 15:18:15 +gem5 started Jul 9 2011 00:22:05 +gem5 executing on u200439-lin.austin.arm.com +command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/70.twolf/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/long/70.twolf/x86/linux/o3-timing +Couldn't unlink build/X86_SE/tests/opt/long/70.twolf/x86/linux/o3-timing/smred.sav +Couldn't unlink build/X86_SE/tests/opt/long/70.twolf/x86/linux/o3-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -24,4 +24,4 @@ info: Increasing stack size by one page. 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 106734154000 because target called exit() +122 123 124 Exiting @ tick 105045070000 because target called exit() diff --git a/tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt b/tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt index 934f22237..05846252d 100644 --- a/tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt @@ -1,248 +1,251 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.106734 # Number of seconds simulated -sim_ticks 106734154000 # Number of ticks simulated +sim_seconds 0.105045 # Number of seconds simulated +sim_ticks 105045070000 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 152335 # Simulator instruction rate (inst/s) -host_tick_rate 73451239 # Simulator tick rate (ticks/s) -host_mem_usage 239116 # Number of bytes of host memory used -host_seconds 1453.13 # Real time elapsed on the host +host_inst_rate 49247 # Simulator instruction rate (inst/s) +host_tick_rate 23369426 # Simulator tick rate (ticks/s) +host_mem_usage 262348 # Number of bytes of host memory used +host_seconds 4494.98 # Real time elapsed on the host sim_insts 221363017 # Number of instructions simulated system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 213468309 # number of cpu cycles simulated +system.cpu.numCycles 210090141 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 25050494 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 25050494 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 3072725 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 22404993 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 19578906 # Number of BTB hits +system.cpu.BPredUnit.lookups 25989444 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 25989444 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 2880460 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 23775424 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 20999107 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 27480404 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 261552197 # Number of instructions fetch has processed -system.cpu.fetch.Branches 25050494 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 19578906 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 69713468 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 3100277 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 57 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.CacheLines 27480404 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 444252 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 213378820 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.014955 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.225944 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 30913045 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 262360842 # Number of instructions fetch has processed +system.cpu.fetch.Branches 25989444 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 20999107 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 70912631 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 26788053 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 84314801 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 59 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 386 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 28891572 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 510286 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 210004513 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.080616 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.257688 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 145514774 68.20% 68.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 3945621 1.85% 70.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 3133148 1.47% 71.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 4337653 2.03% 73.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4594142 2.15% 75.70% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 4407004 2.07% 77.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 5010346 2.35% 80.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 3238927 1.52% 81.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 39197205 18.37% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 140976557 67.13% 67.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 4102515 1.95% 69.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 3266952 1.56% 70.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 4494510 2.14% 72.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4287341 2.04% 74.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 4445757 2.12% 76.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 5469335 2.60% 79.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 3067811 1.46% 81.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 39893735 19.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 213378820 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.117350 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.225251 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 66958522 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 57001085 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 60412397 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 5858231 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 23148585 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 419968775 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 23148585 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 74832356 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 18068346 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 22426 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 57435303 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 39871804 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 409779933 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 21501033 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 16352489 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 430797248 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1054244247 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1043122682 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 11121565 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 210004513 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.123706 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.248801 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 45877800 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 73040488 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 56067682 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 11154952 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 23863591 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 425695349 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 23863591 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 54978073 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 20531962 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 23888 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 57215372 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 53391627 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 414341081 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 9 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 29904351 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 20832303 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 439740854 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1072087884 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1060055510 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 12032374 # Number of floating rename lookups system.cpu.rename.CommittedMaps 234363409 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 196433839 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1440 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1310 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 83098346 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 104980766 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 37095594 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 90430174 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 30425407 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 395507957 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1424 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 281825994 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 65208 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 173816854 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 357698242 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 178 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 213378820 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.320778 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.372811 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 205377445 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1472 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1467 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 107891206 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 105317858 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 38075077 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 93159528 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 32053194 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 401973184 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1452 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 281949896 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 93319 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 180405521 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 380338666 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 206 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 210004513 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.342590 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.373881 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 72508898 33.98% 33.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 65573468 30.73% 64.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 36643591 17.17% 81.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 20570957 9.64% 91.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12013670 5.63% 97.16% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 3959812 1.86% 99.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1477782 0.69% 99.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 513095 0.24% 99.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 117547 0.06% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 69632726 33.16% 33.16% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 64637798 30.78% 63.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 36965443 17.60% 81.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 20500342 9.76% 91.30% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 11980383 5.70% 97.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 4341078 2.07% 99.07% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1469899 0.70% 99.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 380882 0.18% 99.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 95962 0.05% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 213378820 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 210004513 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 68694 2.44% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2379905 84.54% 86.98% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 366520 13.02% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 107259 3.58% 3.58% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 3.58% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 3.58% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.58% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.58% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.58% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 3.58% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.58% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 3.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 3.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.58% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2493480 83.26% 86.84% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 394104 13.16% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 1200241 0.43% 0.43% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 187039988 66.37% 66.79% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 66.79% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.79% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 1589434 0.56% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 68492447 24.30% 91.66% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 23503884 8.34% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 1205058 0.43% 0.43% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 187553155 66.52% 66.95% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 66.95% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.95% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 1592331 0.56% 67.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.51% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 67840384 24.06% 91.57% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 23758968 8.43% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 281825994 # Type of FU issued -system.cpu.iq.rate 1.320224 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2815119 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.009989 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 774676274 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 563666202 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 273457668 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 5234861 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 5690969 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 2532279 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 280803234 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 2637638 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 16340040 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 281949896 # Type of FU issued +system.cpu.iq.rate 1.342042 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2994843 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.010622 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 771774380 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 576023644 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 274192966 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 5218087 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 6409815 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 2516754 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 281110852 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 2628829 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 16405664 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 48331176 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 20419 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 34128 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 16579878 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 48668268 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 6062 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 61115 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 17559361 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 45973 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.rescheduledLoads 45288 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 23148585 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 533368 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 548562 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 395509381 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 255580 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 104980766 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 37095594 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1424 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 479390 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 13059 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 34128 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 2541200 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 744980 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 3286180 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 278309942 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 67077031 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 3516052 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 23863591 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 694538 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 427795 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 401974636 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 134263 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 105317858 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 38075077 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1452 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 312662 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 40441 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 61115 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 2496230 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 580255 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 3076485 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 278882390 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 66609586 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3067506 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 90250007 # number of memory reference insts executed -system.cpu.iew.exec_branches 15873940 # Number of branches executed -system.cpu.iew.exec_stores 23172976 # Number of stores executed -system.cpu.iew.exec_rate 1.303753 # Inst execution rate -system.cpu.iew.wb_sent 277022685 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 275989947 # cumulative count of insts written-back -system.cpu.iew.wb_producers 222941067 # num instructions producing a value -system.cpu.iew.wb_consumers 371922286 # num instructions consuming a value +system.cpu.iew.exec_refs 90001503 # number of memory reference insts executed +system.cpu.iew.exec_branches 15748098 # Number of branches executed +system.cpu.iew.exec_stores 23391917 # Number of stores executed +system.cpu.iew.exec_rate 1.327442 # Inst execution rate +system.cpu.iew.wb_sent 277747224 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 276709720 # cumulative count of insts written-back +system.cpu.iew.wb_producers 222890509 # num instructions producing a value +system.cpu.iew.wb_consumers 374197573 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.292885 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.599429 # average fanout of values written-back +system.cpu.iew.wb_rate 1.317100 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.595649 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 221363017 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 174164320 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 180623719 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 1246 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 3072754 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 190230235 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.163658 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.518986 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 2880510 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 186140922 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.189223 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.544912 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 74059520 38.93% 38.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 71187215 37.42% 76.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 18215863 9.58% 85.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 12685132 6.67% 92.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 5921003 3.11% 95.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 2781558 1.46% 97.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1922219 1.01% 98.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1098236 0.58% 98.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2359489 1.24% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 71104558 38.20% 38.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 70002292 37.61% 75.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 18277000 9.82% 85.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 12672001 6.81% 92.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 5444041 2.92% 95.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 2973709 1.60% 96.96% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 2048209 1.10% 98.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1096137 0.59% 98.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2522975 1.36% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 190230235 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 186140922 # Number of insts commited each cycle system.cpu.commit.count 221363017 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 77165306 # Number of memory references committed @@ -252,50 +255,50 @@ system.cpu.commit.branches 12326943 # Nu system.cpu.commit.fp_insts 2162459 # Number of committed floating point instructions. system.cpu.commit.int_insts 220339606 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 2359489 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 2522975 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 583398083 # The number of ROB reads -system.cpu.rob.rob_writes 814214435 # The number of ROB writes -system.cpu.timesIdled 1914 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 89489 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 585604683 # The number of ROB reads +system.cpu.rob.rob_writes 827851683 # The number of ROB writes +system.cpu.timesIdled 1839 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 85628 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 221363017 # Number of Instructions Simulated system.cpu.committedInsts_total 221363017 # Number of Instructions Simulated -system.cpu.cpi 0.964336 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.964336 # CPI: Total CPI of All Threads -system.cpu.ipc 1.036983 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.036983 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 516519288 # number of integer regfile reads -system.cpu.int_regfile_writes 284023651 # number of integer regfile writes -system.cpu.fp_regfile_reads 3512884 # number of floating regfile reads -system.cpu.fp_regfile_writes 2186553 # number of floating regfile writes -system.cpu.misc_regfile_reads 145156303 # number of misc regfile reads +system.cpu.cpi 0.949075 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.949075 # CPI: Total CPI of All Threads +system.cpu.ipc 1.053657 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.053657 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 516476198 # number of integer regfile reads +system.cpu.int_regfile_writes 284804952 # number of integer regfile writes +system.cpu.fp_regfile_reads 3512787 # number of floating regfile reads +system.cpu.fp_regfile_writes 2173928 # number of floating regfile writes +system.cpu.misc_regfile_reads 145108967 # number of misc regfile reads system.cpu.misc_regfile_writes 844 # number of misc regfile writes -system.cpu.icache.replacements 3419 # number of replacements -system.cpu.icache.tagsinuse 1603.937064 # Cycle average of tags in use -system.cpu.icache.total_refs 27474068 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 5377 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 5109.553282 # Average number of references to valid blocks. +system.cpu.icache.replacements 4263 # number of replacements +system.cpu.icache.tagsinuse 1631.686111 # Cycle average of tags in use +system.cpu.icache.total_refs 28884352 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 6229 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 4637.076898 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 1603.937064 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.783172 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 27474068 # number of ReadReq hits -system.cpu.icache.demand_hits 27474068 # number of demand (read+write) hits -system.cpu.icache.overall_hits 27474068 # number of overall hits -system.cpu.icache.ReadReq_misses 6336 # number of ReadReq misses -system.cpu.icache.demand_misses 6336 # number of demand (read+write) misses -system.cpu.icache.overall_misses 6336 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 161881500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 161881500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 161881500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 27480404 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 27480404 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 27480404 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.000231 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.000231 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.000231 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 25549.479167 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 25549.479167 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 25549.479167 # average overall miss latency +system.cpu.icache.occ_blocks::0 1631.686111 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.796722 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 28884352 # number of ReadReq hits +system.cpu.icache.demand_hits 28884352 # number of demand (read+write) hits +system.cpu.icache.overall_hits 28884352 # number of overall hits +system.cpu.icache.ReadReq_misses 7220 # number of ReadReq misses +system.cpu.icache.demand_misses 7220 # number of demand (read+write) misses +system.cpu.icache.overall_misses 7220 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 170089500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 170089500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 170089500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 28891572 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 28891572 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 28891572 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.000250 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.000250 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.000250 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 23558.102493 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 23558.102493 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 23558.102493 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -305,59 +308,59 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 957 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 957 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 957 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 5379 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 5379 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 5379 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_hits 990 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 990 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 990 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 6230 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 6230 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 6230 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 120710000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 120710000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 120710000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 125517500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 125517500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 125517500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000196 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.000196 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.000196 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 22440.974159 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 22440.974159 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 22440.974159 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate 0.000216 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.000216 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.000216 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 20147.271268 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 20147.271268 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 20147.271268 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 48 # number of replacements -system.cpu.dcache.tagsinuse 1400.553684 # Cycle average of tags in use -system.cpu.dcache.total_refs 71034499 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1955 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 36334.782097 # Average number of references to valid blocks. +system.cpu.dcache.replacements 50 # number of replacements +system.cpu.dcache.tagsinuse 1406.909972 # Cycle average of tags in use +system.cpu.dcache.total_refs 70508700 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1965 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 35882.290076 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 1400.553684 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.341932 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 50525866 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 20508631 # number of WriteReq hits -system.cpu.dcache.demand_hits 71034497 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 71034497 # number of overall hits -system.cpu.dcache.ReadReq_misses 700 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 7099 # number of WriteReq misses -system.cpu.dcache.demand_misses 7799 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 7799 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 23034500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 187834000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 210868500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 210868500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 50526566 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.occ_blocks::0 1406.909972 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.343484 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 50000081 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 20508618 # number of WriteReq hits +system.cpu.dcache.demand_hits 70508699 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 70508699 # number of overall hits +system.cpu.dcache.ReadReq_misses 707 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 7112 # number of WriteReq misses +system.cpu.dcache.demand_misses 7819 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 7819 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 23625000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 187799500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency 211424500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 211424500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 50000788 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 20515730 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 71042296 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 71042296 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses 70516518 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 70516518 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate 0.000014 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.000346 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.000110 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.000110 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 32906.428571 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 26459.219608 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 27037.889473 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 27037.889473 # average overall miss latency +system.cpu.dcache.WriteReq_miss_rate 0.000347 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate 0.000111 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.000111 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 33415.841584 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 26406.003937 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency 27039.838854 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 27039.838854 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -367,71 +370,71 @@ system.cpu.dcache.avg_blocked_cycles::no_targets no_value system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks 10 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 312 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 5530 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 5842 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 5842 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 388 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 1569 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 1957 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 1957 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_hits 303 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 5550 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits 5853 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 5853 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 404 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 1562 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 1966 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 1966 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 13276000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 55641500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 68917500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 68917500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 13769000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 54860000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 68629000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 68629000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.000008 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate 0.000076 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate 0.000028 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate 0.000028 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34216.494845 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35463.033779 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 35215.891671 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 35215.891671 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34081.683168 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35121.638924 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 34907.934893 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 34907.934893 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 2429.026594 # Cycle average of tags in use -system.cpu.l2cache.total_refs 2107 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 3661 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.575526 # Average number of references to valid blocks. +system.cpu.l2cache.tagsinuse 2506.517035 # Cycle average of tags in use +system.cpu.l2cache.total_refs 2870 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 3766 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.762082 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 2428.011682 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 1.014912 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.074097 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 2505.502143 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 1.014892 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.076462 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::1 0.000031 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 2107 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits 2870 # number of ReadReq hits system.cpu.l2cache.Writeback_hits 10 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits 6 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 2113 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 2113 # number of overall hits -system.cpu.l2cache.ReadReq_misses 3657 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses 2 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses 1562 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 5219 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 5219 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 125400000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 53945500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 179345500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 179345500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 5764 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.demand_hits 2876 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 2876 # number of overall hits +system.cpu.l2cache.ReadReq_misses 3762 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses 1 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses 1556 # number of ReadExReq misses +system.cpu.l2cache.demand_misses 5318 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 5318 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 128883000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 53194000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 182077000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 182077000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 6632 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses 10 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses 2 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 1568 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 7332 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 7332 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.634455 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_accesses 1 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 1562 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 8194 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 8194 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.567250 # miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.996173 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.711811 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.711811 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34290.401969 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34536.171575 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34363.958613 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34363.958613 # average overall miss latency +system.cpu.l2cache.ReadExReq_miss_rate 0.996159 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.649011 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.649011 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34259.170654 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34186.375321 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34237.871380 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34237.871380 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -443,28 +446,28 @@ system.cpu.l2cache.cache_copies 0 # nu system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 3657 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses 2 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 1562 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 5219 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 5219 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses 3762 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses 1 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 1556 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 5318 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 5318 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 113519000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 62000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 48964500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 162483500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 162483500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 116744500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 31000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 48343500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 165088000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 165088000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.634455 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.567250 # mshr miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.996173 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.711811 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.711811 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31041.564124 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.996159 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.649011 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.649011 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31032.562467 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31347.311140 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31133.071470 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31133.071470 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31069.087404 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31043.249342 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31043.249342 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions |