diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual')
3 files changed, 77 insertions, 63 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini index aca491b43..0d25f966b 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini @@ -12,15 +12,15 @@ children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus iocache l2c membus physmem boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 clock=1000 -console=/gem5/dist/binaries/console +console=/scratch/nilay/GEM5/system/binaries/console init_param=0 -kernel=/gem5/dist/binaries/vmlinux +kernel=/scratch/nilay/GEM5/system/binaries/vmlinux load_addr_mask=1099511627775 mem_mode=timing mem_ranges=0:134217727 memories=system.physmem num_work_ids=16 -pal=/gem5/dist/binaries/ts_osfpal +pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal readfile=tests/halt.sh symbolfile= system_rev=1024 @@ -46,22 +46,18 @@ slave=system.membus.master[0] [system.cpu0] type=DerivO3CPU -children=dcache dtb fuPool icache interrupts isa itb tracer -BTBEntries=4096 -BTBTagSize=16 +children=branchPred dcache dtb fuPool icache interrupts isa itb tracer LFSTSize=1024 LQEntries=32 LSQCheckLoads=true LSQDepCheckShift=4 -RASSize=16 SQEntries=32 SSITSize=1024 activity=0 backComSize=5 +branchPred=system.cpu0.branchPred cachePorts=200 checker=Null -choiceCtrBits=2 -choicePredictorSize=8192 clock=500 commitToDecodeDelay=1 commitToFetchDelay=1 @@ -84,23 +80,15 @@ forwardComSize=5 fuPool=system.cpu0.fuPool function_trace=false function_trace_start=0 -globalCtrBits=2 -globalHistoryBits=13 -globalPredictorSize=8192 iewToCommitDelay=1 iewToDecodeDelay=1 iewToFetchDelay=1 iewToRenameDelay=1 -instShiftAmt=2 interrupts=system.cpu0.interrupts isa=system.cpu0.isa issueToExecuteDelay=1 issueWidth=8 itb=system.cpu0.itb -localCtrBits=2 -localHistoryBits=11 -localHistoryTableSize=2048 -localPredictorSize=2048 max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 @@ -112,7 +100,6 @@ numPhysIntRegs=256 numROBEntries=192 numRobs=1 numThreads=1 -predType=tournament profile=0 progress_interval=0 renameToDecodeDelay=1 @@ -141,6 +128,24 @@ workload= dcache_port=system.cpu0.dcache.cpu_side icache_port=system.cpu0.icache.cpu_side +[system.cpu0.branchPred] +type=BranchPredictor +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +choiceCtrBits=2 +choicePredictorSize=8192 +globalCtrBits=2 +globalHistoryBits=13 +globalPredictorSize=8192 +instShiftAmt=2 +localCtrBits=2 +localHistoryBits=11 +localHistoryTableSize=2048 +localPredictorSize=2048 +numThreads=1 +predType=tournament + [system.cpu0.dcache] type=BaseCache addr_ranges=0:18446744073709551615 @@ -467,22 +472,18 @@ type=ExeTracer [system.cpu1] type=DerivO3CPU -children=dcache dtb fuPool icache interrupts isa itb tracer -BTBEntries=4096 -BTBTagSize=16 +children=branchPred dcache dtb fuPool icache interrupts isa itb tracer LFSTSize=1024 LQEntries=32 LSQCheckLoads=true LSQDepCheckShift=4 -RASSize=16 SQEntries=32 SSITSize=1024 activity=0 backComSize=5 +branchPred=system.cpu1.branchPred cachePorts=200 checker=Null -choiceCtrBits=2 -choicePredictorSize=8192 clock=500 commitToDecodeDelay=1 commitToFetchDelay=1 @@ -505,23 +506,15 @@ forwardComSize=5 fuPool=system.cpu1.fuPool function_trace=false function_trace_start=0 -globalCtrBits=2 -globalHistoryBits=13 -globalPredictorSize=8192 iewToCommitDelay=1 iewToDecodeDelay=1 iewToFetchDelay=1 iewToRenameDelay=1 -instShiftAmt=2 interrupts=system.cpu1.interrupts isa=system.cpu1.isa issueToExecuteDelay=1 issueWidth=8 itb=system.cpu1.itb -localCtrBits=2 -localHistoryBits=11 -localHistoryTableSize=2048 -localPredictorSize=2048 max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 @@ -533,7 +526,6 @@ numPhysIntRegs=256 numROBEntries=192 numRobs=1 numThreads=1 -predType=tournament profile=0 progress_interval=0 renameToDecodeDelay=1 @@ -562,6 +554,24 @@ workload= dcache_port=system.cpu1.dcache.cpu_side icache_port=system.cpu1.icache.cpu_side +[system.cpu1.branchPred] +type=BranchPredictor +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +choiceCtrBits=2 +choicePredictorSize=8192 +globalCtrBits=2 +globalHistoryBits=13 +globalPredictorSize=8192 +instShiftAmt=2 +localCtrBits=2 +localHistoryBits=11 +localHistoryTableSize=2048 +localPredictorSize=2048 +numThreads=1 +predType=tournament + [system.cpu1.dcache] type=BaseCache addr_ranges=0:18446744073709551615 @@ -903,7 +913,7 @@ table_size=65536 [system.disk0.image.child] type=RawDiskImage -image_file=/gem5/dist/disks/linux-latest.img +image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img read_only=true [system.disk2] @@ -923,7 +933,7 @@ table_size=65536 [system.disk2.image.child] type=RawDiskImage -image_file=/gem5/dist/disks/linux-bigswap2.img +image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img read_only=true [system.intrctrl] @@ -1048,7 +1058,7 @@ system=system [system.simple_disk.disk] type=RawDiskImage -image_file=/gem5/dist/disks/linux-latest.img +image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img read_only=true [system.terminal] diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout index f4163d49e..560862c38 100755 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout @@ -1,13 +1,15 @@ +Redirecting stdout to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual/simout +Redirecting stderr to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 4 2013 21:09:21 -gem5 started Jan 4 2013 21:41:13 -gem5 executing on u200540 +gem5 compiled Jan 23 2013 13:29:14 +gem5 started Jan 23 2013 13:29:25 +gem5 executing on ribera.cs.wisc.edu command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual Global frequency set at 1000000000000 ticks per second -info: kernel located at: /gem5/dist/binaries/vmlinux +info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 info: Entering event queue @ 0. Starting simulation... -info: Launching CPU 1 @ 107840000 -Exiting @ tick 1897857556000 because m5_exit instruction encountered +info: Launching CPU 1 @ 107825000 +Exiting @ tick 1901719660500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt index 46b1b53be..30313ea26 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.901720 # Nu sim_ticks 1901719660500 # Number of ticks simulated final_tick 1901719660500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 128809 # Simulator instruction rate (inst/s) -host_op_rate 128809 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4317556960 # Simulator tick rate (ticks/s) -host_mem_usage 340604 # Number of bytes of host memory used -host_seconds 440.46 # Real time elapsed on the host +host_inst_rate 97307 # Simulator instruction rate (inst/s) +host_op_rate 97307 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3261646555 # Simulator tick rate (ticks/s) +host_mem_usage 383552 # Number of bytes of host memory used +host_seconds 583.06 # Real time elapsed on the host sim_insts 56735321 # Number of instructions simulated sim_ops 56735321 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu0.inst 857600 # Number of bytes read from this memory @@ -612,6 +612,15 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. +system.cpu0.branchPred.lookups 12372868 # Number of BP lookups +system.cpu0.branchPred.condPredicted 10433314 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 330387 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 8151024 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 5278103 # Number of BTB hits +system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu0.branchPred.BTBHitPct 64.753864 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 784011 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 32544 # Number of incorrect RAS predictions. system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv @@ -647,14 +656,6 @@ system.cpu0.itb.data_accesses 0 # DT system.cpu0.numCycles 101814962 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.BPredUnit.lookups 12372868 # Number of BP lookups -system.cpu0.BPredUnit.condPredicted 10433314 # Number of conditional branches predicted -system.cpu0.BPredUnit.condIncorrect 330387 # Number of conditional branches incorrect -system.cpu0.BPredUnit.BTBLookups 8151024 # Number of BTB lookups -system.cpu0.BPredUnit.BTBHits 5278103 # Number of BTB hits -system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.BPredUnit.usedRAS 784011 # Number of times the RAS was used to get a target. -system.cpu0.BPredUnit.RASInCorrect 32544 # Number of incorrect RAS predictions. system.cpu0.fetch.icacheStallCycles 24931217 # Number of cycles fetch is stalled on an Icache miss system.cpu0.fetch.Insts 63627814 # Number of instructions fetch has processed system.cpu0.fetch.Branches 12372868 # Number of branches that fetch encountered @@ -1192,6 +1193,15 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.branchPred.lookups 2617746 # Number of BP lookups +system.cpu1.branchPred.condPredicted 2161338 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 77903 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 1516620 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 873996 # Number of BTB hits +system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu1.branchPred.BTBHitPct 57.627883 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 182212 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 8242 # Number of incorrect RAS predictions. system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv @@ -1227,14 +1237,6 @@ system.cpu1.itb.data_accesses 0 # DT system.cpu1.numCycles 16039611 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.BPredUnit.lookups 2617746 # Number of BP lookups -system.cpu1.BPredUnit.condPredicted 2161338 # Number of conditional branches predicted -system.cpu1.BPredUnit.condIncorrect 77903 # Number of conditional branches incorrect -system.cpu1.BPredUnit.BTBLookups 1516620 # Number of BTB lookups -system.cpu1.BPredUnit.BTBHits 873996 # Number of BTB hits -system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.BPredUnit.usedRAS 182212 # Number of times the RAS was used to get a target. -system.cpu1.BPredUnit.RASInCorrect 8242 # Number of incorrect RAS predictions. system.cpu1.fetch.icacheStallCycles 6032367 # Number of cycles fetch is stalled on an Icache miss system.cpu1.fetch.Insts 12375417 # Number of instructions fetch has processed system.cpu1.fetch.Branches 2617746 # Number of branches that fetch encountered |