diff options
Diffstat (limited to 'tests/long/se/00.gzip/ref/sparc/linux/simple-timing')
4 files changed, 492 insertions, 0 deletions
diff --git a/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/config.ini b/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/config.ini new file mode 100644 index 000000000..ea98a23a1 --- /dev/null +++ b/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/config.ini @@ -0,0 +1,205 @@ +[root] +type=Root +children=system +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=cpu membus physmem +mem_mode=atomic +memories=system.physmem +num_work_ids=16 +physmem=system.physmem +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.port[0] + +[system.cpu] +type=TimingSimpleCPU +children=dcache dtb icache itb l2cache toL2Bus tracer workload +checker=Null +clock=500 +cpu_id=0 +defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true +dtb=system.cpu.dtb +function_trace=false +function_trace_start=0 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +phase=0 +progress_interval=0 +system=system +tracer=system.cpu.tracer +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.dcache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=2 +block_size=64 +forward_snoops=true +hash_delay=1 +is_top_level=true +latency=1000 +max_miss_count=0 +mshrs=10 +num_cpus=1 +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_on_access=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=262144 +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.port[1] + +[system.cpu.dtb] +type=SparcTLB +size=64 + +[system.cpu.icache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=2 +block_size=64 +forward_snoops=true +hash_delay=1 +is_top_level=true +latency=1000 +max_miss_count=0 +mshrs=10 +num_cpus=1 +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=10000 +prefetch_on_access=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=131072 +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.port[0] + +[system.cpu.itb] +type=SparcTLB +size=64 + +[system.cpu.l2cache] +type=BaseCache +addr_range=0:18446744073709551615 +assoc=2 +block_size=64 +forward_snoops=true +hash_delay=1 +is_top_level=false +latency=10000 +max_miss_count=0 +mshrs=10 +num_cpus=1 +prefetch_data_accesses_only=false +prefetch_degree=1 +prefetch_latency=100000 +prefetch_on_access=false +prefetch_past_page=false +prefetch_policy=none +prefetch_serial_squash=false +prefetch_use_cpu_id=true +prefetcher_size=100 +prioritizeRequests=false +repl=Null +size=2097152 +subblock_size=0 +tgts_per_mshr=5 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.toL2Bus.port[2] +mem_side=system.membus.port[2] + +[system.cpu.toL2Bus] +type=Bus +block_size=64 +bus_id=0 +clock=1000 +header_cycles=1 +use_default_range=false +width=64 +port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side + +[system.cpu.tracer] +type=ExeTracer + +[system.cpu.workload] +type=LiveProcess +cmd=gzip input.log 1 +cwd=build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/simple-timing +egid=100 +env= +errout=cerr +euid=100 +executable=/dist/m5/cpu2000/binaries/sparc/linux/gzip +gid=100 +input=cin +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 + +[system.membus] +type=Bus +block_size=64 +bus_id=0 +clock=1000 +header_cycles=1 +use_default_range=false +width=64 +port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side + +[system.physmem] +type=PhysicalMemory +file= +latency=30000 +latency_var=0 +null=false +range=0:134217727 +zero=false +port=system.membus.port[1] + diff --git a/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/simerr b/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/simerr new file mode 100755 index 000000000..e45cd058f --- /dev/null +++ b/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/simerr @@ -0,0 +1,2 @@ +warn: Sockets disabled, not accepting gdb connections +hack: be nice to actually delete the event here diff --git a/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/simout b/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/simout new file mode 100755 index 000000000..b26fb3f41 --- /dev/null +++ b/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/simout @@ -0,0 +1,41 @@ +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Jan 23 2012 04:02:00 +gem5 started Jan 23 2012 06:19:05 +gem5 executing on zizzer +command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/simple-timing +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +spec_init +Loading Input Data +Duplicating 262144 bytes +Duplicating 524288 bytes +Input data 1048576 bytes in length +Compressing Input Data, level 1 +Compressed data 108074 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 3 +Compressed data 97831 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 5 +Compressed data 83382 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 7 +Compressed data 76606 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 9 +Compressed data 73189 bytes in length +Uncompressing Data +Uncompressed data 1048576 bytes in length +Uncompressed data compared correctly +Tested 1MB buffer: OK! +Exiting @ tick 2064258667000 because target called exit() diff --git a/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/stats.txt new file mode 100644 index 000000000..059312926 --- /dev/null +++ b/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/stats.txt @@ -0,0 +1,244 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 2.064259 # Number of seconds simulated +sim_ticks 2064258667000 # Number of ticks simulated +final_tick 2064258667000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 1766930 # Simulator instruction rate (inst/s) +host_tick_rate 2448703239 # Simulator tick rate (ticks/s) +host_mem_usage 214556 # Number of bytes of host memory used +host_seconds 843.00 # Real time elapsed on the host +sim_insts 1489523295 # Number of instructions simulated +system.physmem.bytes_read 5909952 # Number of bytes read from this memory +system.physmem.bytes_inst_read 70592 # Number of instructions bytes read from this memory +system.physmem.bytes_written 3778240 # Number of bytes written to this memory +system.physmem.num_reads 92343 # Number of read requests responded to by this memory +system.physmem.num_writes 59035 # Number of write requests responded to by this memory +system.physmem.num_other 0 # Number of other requests responded to by this memory +system.physmem.bw_read 2862990 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 34197 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write 1830313 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total 4693303 # Total bandwidth to/from this memory (bytes/s) +system.cpu.workload.num_syscalls 49 # Number of system calls +system.cpu.numCycles 4128517334 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.num_insts 1489523295 # Number of instructions executed +system.cpu.num_int_alu_accesses 1319481298 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 8454127 # Number of float alu accesses +system.cpu.num_func_calls 1207835 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 78161763 # number of instructions that are conditional controls +system.cpu.num_int_insts 1319481298 # number of integer instructions +system.cpu.num_fp_insts 8454127 # number of float instructions +system.cpu.num_int_register_reads 2499743582 # number of times the integer registers were read +system.cpu.num_int_register_writes 1234343157 # number of times the integer registers were written +system.cpu.num_fp_register_reads 16769332 # number of times the floating registers were read +system.cpu.num_fp_register_writes 10359244 # number of times the floating registers were written +system.cpu.num_mem_refs 569365767 # number of memory refs +system.cpu.num_load_insts 402515346 # Number of load instructions +system.cpu.num_store_insts 166850421 # Number of store instructions +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 4128517334 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.icache.replacements 118 # number of replacements +system.cpu.icache.tagsinuse 906.450625 # Cycle average of tags in use +system.cpu.icache.total_refs 1485111905 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1107 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 1341564.503162 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::0 906.450625 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.442603 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 1485111905 # number of ReadReq hits +system.cpu.icache.demand_hits 1485111905 # number of demand (read+write) hits +system.cpu.icache.overall_hits 1485111905 # number of overall hits +system.cpu.icache.ReadReq_misses 1107 # number of ReadReq misses +system.cpu.icache.demand_misses 1107 # number of demand (read+write) misses +system.cpu.icache.overall_misses 1107 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 61824000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 61824000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 61824000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 1485113012 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 1485113012 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 1485113012 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.000001 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.000001 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.000001 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 55848.238482 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 55848.238482 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 55848.238482 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 1107 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 1107 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 1107 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.ReadReq_mshr_miss_latency 58503000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 58503000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 58503000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000001 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.000001 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.000001 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 52848.238482 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 52848.238482 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 52848.238482 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements 449125 # number of replacements +system.cpu.dcache.tagsinuse 4095.226955 # Cycle average of tags in use +system.cpu.dcache.total_refs 568907765 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 453221 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 1255.254644 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 566994000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::0 4095.226955 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.999811 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 402319358 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 166587088 # number of WriteReq hits +system.cpu.dcache.SwapReq_hits 1319 # number of SwapReq hits +system.cpu.dcache.demand_hits 568906446 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 568906446 # number of overall hits +system.cpu.dcache.ReadReq_misses 193486 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 259728 # number of WriteReq misses +system.cpu.dcache.SwapReq_misses 7 # number of SwapReq misses +system.cpu.dcache.demand_misses 453214 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 453214 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 4019834000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 6156948000 # number of WriteReq miss cycles +system.cpu.dcache.SwapReq_miss_latency 392000 # number of SwapReq miss cycles +system.cpu.dcache.demand_miss_latency 10176782000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 10176782000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 402512844 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses 166846816 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SwapReq_accesses 1326 # number of SwapReq accesses(hits+misses) +system.cpu.dcache.demand_accesses 569359660 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 569359660 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.000481 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate 0.001557 # miss rate for WriteReq accesses +system.cpu.dcache.SwapReq_miss_rate 0.005279 # miss rate for SwapReq accesses +system.cpu.dcache.demand_miss_rate 0.000796 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.000796 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 20775.839079 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 23705.368693 # average WriteReq miss latency +system.cpu.dcache.SwapReq_avg_miss_latency 56000 # average SwapReq miss latency +system.cpu.dcache.demand_avg_miss_latency 22454.694692 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 22454.694692 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks 407009 # number of writebacks +system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 193486 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 259728 # number of WriteReq MSHR misses +system.cpu.dcache.SwapReq_mshr_misses 7 # number of SwapReq MSHR misses +system.cpu.dcache.demand_mshr_misses 453214 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 453214 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.ReadReq_mshr_miss_latency 3439376000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 5377764000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency 371000 # number of SwapReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 8817140000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 8817140000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.000481 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate 0.001557 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SwapReq_mshr_miss_rate 0.005279 # mshr miss rate for SwapReq accesses +system.cpu.dcache.demand_mshr_miss_rate 0.000796 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.000796 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 17775.839079 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 20705.368693 # average WriteReq mshr miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency 53000 # average SwapReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 19454.694692 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 19454.694692 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.replacements 74112 # number of replacements +system.cpu.l2cache.tagsinuse 17723.305524 # Cycle average of tags in use +system.cpu.l2cache.total_refs 427085 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 89611 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 4.765989 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::0 1873.919591 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 15849.385934 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.057187 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::1 0.483685 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 162275 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits 407009 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits 199710 # number of ReadExReq hits +system.cpu.l2cache.demand_hits 361985 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 361985 # number of overall hits +system.cpu.l2cache.ReadReq_misses 32318 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses 60025 # number of ReadExReq misses +system.cpu.l2cache.demand_misses 92343 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 92343 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 1680536000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 3121300000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 4801836000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 4801836000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 194593 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses 407009 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 259735 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 454328 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 454328 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.166080 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate 0.231101 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 0.203252 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.203252 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.writebacks 59035 # number of writebacks +system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses 32318 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 60025 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 92343 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 92343 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 1292720000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 2401000000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 3693720000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 3693720000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.166080 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.231101 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.203252 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.203252 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate + +---------- End Simulation Statistics ---------- |